Expand description
InterruptEn Register
Modules§
- SPDIF receiver found parity bit error
- SPDIF receive change in value of control channel
- SPDIF receiver’s DPLL is locked
- SPDIF receiver loss of lock
- Q Channel receive register full, can’t be cleared with reg
- Q Channel receive register overrun
- SPDIF Rx FIFO full, can’t be cleared with reg. IntClear. To clear it, read from Rx FIFO.
- Rx FIFO resync
- Rx FIFO underrun/overrun
- SPDIF receiver found illegal symbol
- SPDIF Tx FIFO empty, can’t be cleared with reg. IntClear. To clear it, write toTx FIFO.
- SPDIF Tx FIFO resync
- SPDIF Tx FIFO under/overrun
- U/Q Channel framing error
- U/Q Channel sync found
- U Channel receive register full, can’t be cleared with reg
- U Channel receive register overrun
- SPDIF validity flag no good