Module RW

Constants

• TXCLK_SOURCE_0
  XTALOSC input (XTALOSC clock)
• TXCLK_SOURCE_1
  tx_clk input (from SPDIF0_CLK_ROOT. See CCM.)
• TXCLK_SOURCE_2
  tx_clk1 (from SAI1)
• TXCLK_SOURCE_3
  tx_clk2 SPDIF_EXT_CLK, from pads
• TXCLK_SOURCE_4
  tx_clk3 (from SAI2)
• TXCLK_SOURCE_5
  ipg_clk input (frequency divided)
• TXCLK_SOURCE_6
  tx_clk4 (from SAI3)