1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180

#[doc = "GPC"]
#[repr(C)]
pub struct RegisterBlock {
    #[doc = "GPC Interface control register"]
    pub CNTR: crate::RWRegister<u32>,
    _reserved0: [u8; 0x04],
    #[doc = "IRQ masking register 1"]
    pub IMR1: crate::RWRegister<u32>,
    #[doc = "IRQ masking register 2"]
    pub IMR2: crate::RWRegister<u32>,
    #[doc = "IRQ masking register 3"]
    pub IMR3: crate::RWRegister<u32>,
    #[doc = "IRQ masking register 4"]
    pub IMR4: crate::RWRegister<u32>,
    #[doc = "IRQ status resister 1"]
    pub ISR1: crate::RORegister<u32>,
    #[doc = "IRQ status resister 2"]
    pub ISR2: crate::RORegister<u32>,
    #[doc = "IRQ status resister 3"]
    pub ISR3: crate::RORegister<u32>,
    #[doc = "IRQ status resister 4"]
    pub ISR4: crate::RORegister<u32>,
    _reserved1: [u8; 0x0c],
    #[doc = "IRQ masking register 5"]
    pub IMR5: crate::RWRegister<u32>,
    #[doc = "IRQ status resister 5"]
    pub ISR5: crate::RORegister<u32>,
}
#[doc = "GPC Interface control register"]
pub mod CNTR {
    #[doc = "MEGA domain power down request"]
    pub mod MEGA_PDN_REQ {
        pub const offset: u32 = 2;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "No Request"]
            pub const MEGA_PDN_REQ_0: u32 = 0;
            #[doc = "Request power down sequence"]
            pub const MEGA_PDN_REQ_1: u32 = 0x01;
        }
    }
    #[doc = "MEGA domain power up request"]
    pub mod MEGA_PUP_REQ {
        pub const offset: u32 = 3;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "No Request"]
            pub const MEGA_PUP_REQ_0: u32 = 0;
            #[doc = "Request power up sequence"]
            pub const MEGA_PUP_REQ_1: u32 = 0x01;
        }
    }
    #[doc = "FlexRAM PDRAM0 Power Gate Enable"]
    pub mod PDRAM0_PGE {
        pub const offset: u32 = 22;
        pub const mask: u32 = 0x01 << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {
            #[doc = "FlexRAM PDRAM0 domain will keep power even if the CPU core is powered down."]
            pub const PDRAM0_PGE_0: u32 = 0;
            #[doc = "FlexRAM PDRAM0 domain will be powered down when the CPU core is powered down.."]
            pub const PDRAM0_PGE_1: u32 = 0x01;
        }
    }
}
#[doc = "IRQ masking register 1"]
pub mod IMR1 {
    #[doc = "IRQ\\[31:0\\] masking bits: 1-irq masked, 0-irq is not masked"]
    pub mod IMR1 {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0xffff_ffff << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "IRQ masking register 2"]
pub mod IMR2 {
    #[doc = "IRQ\\[63:32\\] masking bits: 1-irq masked, 0-irq is not masked"]
    pub mod IMR2 {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0xffff_ffff << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "IRQ masking register 3"]
pub mod IMR3 {
    #[doc = "IRQ\\[95:64\\] masking bits: 1-irq masked, 0-irq is not masked"]
    pub mod IMR3 {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0xffff_ffff << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "IRQ masking register 4"]
pub mod IMR4 {
    #[doc = "IRQ\\[127:96\\] masking bits: 1-irq masked, 0-irq is not masked"]
    pub mod IMR4 {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0xffff_ffff << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "IRQ status resister 1"]
pub mod ISR1 {
    #[doc = "IRQ\\[31:0\\] status, read only"]
    pub mod ISR1 {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0xffff_ffff << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "IRQ status resister 2"]
pub mod ISR2 {
    #[doc = "IRQ\\[63:32\\] status, read only"]
    pub mod ISR2 {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0xffff_ffff << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "IRQ status resister 3"]
pub mod ISR3 {
    #[doc = "IRQ\\[95:64\\] status, read only"]
    pub mod ISR3 {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0xffff_ffff << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "IRQ status resister 4"]
pub mod ISR4 {
    #[doc = "IRQ\\[127:96\\] status, read only"]
    pub mod ISR4 {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0xffff_ffff << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "IRQ masking register 5"]
pub mod IMR5 {
    #[doc = "IRQ\\[159:128\\] masking bits: 1-irq masked, 0-irq is not masked"]
    pub mod IMR5 {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0xffff_ffff << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}
#[doc = "IRQ status resister 5"]
pub mod ISR5 {
    #[doc = "IRQ\\[159:128\\] status, read only"]
    pub mod ISR4 {
        pub const offset: u32 = 0;
        pub const mask: u32 = 0xffff_ffff << offset;
        pub mod R {}
        pub mod W {}
        pub mod RW {}
    }
}