imxrt_ral/blocks/imxrt1015/
bee.rs1#[doc = "Bus Encryption Engine"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "BEE Control Register"]
5 pub CTRL: crate::RWRegister<u32>,
6 #[doc = "no description available"]
7 pub ADDR_OFFSET0: crate::RWRegister<u32>,
8 #[doc = "no description available"]
9 pub ADDR_OFFSET1: crate::RWRegister<u32>,
10 #[doc = "no description available"]
11 pub AES_KEY0_W0: crate::RWRegister<u32>,
12 #[doc = "no description available"]
13 pub AES_KEY0_W1: crate::RWRegister<u32>,
14 #[doc = "no description available"]
15 pub AES_KEY0_W2: crate::RWRegister<u32>,
16 #[doc = "no description available"]
17 pub AES_KEY0_W3: crate::RWRegister<u32>,
18 #[doc = "no description available"]
19 pub STATUS: crate::RWRegister<u32>,
20 #[doc = "no description available"]
21 pub CTR_NONCE0_W0: crate::WORegister<u32>,
22 #[doc = "no description available"]
23 pub CTR_NONCE0_W1: crate::WORegister<u32>,
24 #[doc = "no description available"]
25 pub CTR_NONCE0_W2: crate::WORegister<u32>,
26 #[doc = "no description available"]
27 pub CTR_NONCE0_W3: crate::WORegister<u32>,
28 #[doc = "no description available"]
29 pub CTR_NONCE1_W0: crate::WORegister<u32>,
30 #[doc = "no description available"]
31 pub CTR_NONCE1_W1: crate::WORegister<u32>,
32 #[doc = "no description available"]
33 pub CTR_NONCE1_W2: crate::WORegister<u32>,
34 #[doc = "no description available"]
35 pub CTR_NONCE1_W3: crate::WORegister<u32>,
36 #[doc = "no description available"]
37 pub REGION1_TOP: crate::RWRegister<u32>,
38 #[doc = "no description available"]
39 pub REGION1_BOT: crate::RWRegister<u32>,
40}
41#[doc = "BEE Control Register"]
42pub mod CTRL {
43 #[doc = "BEE enable bit"]
44 pub mod BEE_ENABLE {
45 pub const offset: u32 = 0;
46 pub const mask: u32 = 0x01 << offset;
47 pub mod R {}
48 pub mod W {}
49 pub mod RW {
50 #[doc = "Disable BEE"]
51 pub const BEE_ENABLE_0: u32 = 0;
52 #[doc = "Enable BEE"]
53 pub const BEE_ENABLE_1: u32 = 0x01;
54 }
55 }
56 #[doc = "Clock enable input, low inactive"]
57 pub mod CTRL_CLK_EN {
58 pub const offset: u32 = 1;
59 pub const mask: u32 = 0x01 << offset;
60 pub mod R {}
61 pub mod W {}
62 pub mod RW {}
63 }
64 #[doc = "Soft reset input, low active"]
65 pub mod CTRL_SFTRST_N {
66 pub const offset: u32 = 2;
67 pub const mask: u32 = 0x01 << offset;
68 pub mod R {}
69 pub mod W {}
70 pub mod RW {}
71 }
72 #[doc = "AES-128 key is ready"]
73 pub mod KEY_VALID {
74 pub const offset: u32 = 4;
75 pub const mask: u32 = 0x01 << offset;
76 pub mod R {}
77 pub mod W {}
78 pub mod RW {}
79 }
80 #[doc = "AES key region select"]
81 pub mod KEY_REGION_SEL {
82 pub const offset: u32 = 5;
83 pub const mask: u32 = 0x01 << offset;
84 pub mod R {}
85 pub mod W {}
86 pub mod RW {
87 #[doc = "Load AES key for region0"]
88 pub const KEY_REGION_SEL_0: u32 = 0;
89 #[doc = "Load AES key for region1"]
90 pub const KEY_REGION_SEL_1: u32 = 0x01;
91 }
92 }
93 #[doc = "Enable access permission control When AC_PROT_EN is asserted, all encrypted regions are limited to be ARM core access only"]
94 pub mod AC_PROT_EN {
95 pub const offset: u32 = 6;
96 pub const mask: u32 = 0x01 << offset;
97 pub mod R {}
98 pub mod W {}
99 pub mod RW {}
100 }
101 #[doc = "Endian swap control for the 16 bytes input and output data of AES core."]
102 pub mod LITTLE_ENDIAN {
103 pub const offset: u32 = 7;
104 pub const mask: u32 = 0x01 << offset;
105 pub mod R {}
106 pub mod W {}
107 pub mod RW {
108 #[doc = "The input and output data of the AES core is swapped as below: {B15,B14,B13,B12,B11,B10,B9,B8, B7,B6,B5,B4,B3,B2,B1,B0} swap to {B0,B1,B2,B3,B4,B5,B6,B7, B8,B9,B10,B11,B12,B13,B14,B15}, where B0~B15 refers to Byte0 to Byte15."]
109 pub const LITTLE_ENDIAN_0: u32 = 0;
110 #[doc = "The input and output data of AES core is not swapped."]
111 pub const LITTLE_ENDIAN_1: u32 = 0x01;
112 }
113 }
114 #[doc = "Security level of the allowed access for memory region0"]
115 pub mod SECURITY_LEVEL_R0 {
116 pub const offset: u32 = 8;
117 pub const mask: u32 = 0x03 << offset;
118 pub mod R {}
119 pub mod W {}
120 pub mod RW {}
121 }
122 #[doc = "AES mode of region0"]
123 pub mod CTRL_AES_MODE_R0 {
124 pub const offset: u32 = 10;
125 pub const mask: u32 = 0x01 << offset;
126 pub mod R {}
127 pub mod W {}
128 pub mod RW {
129 #[doc = "ECB"]
130 pub const CTRL_AES_MODE_R0_0: u32 = 0;
131 #[doc = "CTR"]
132 pub const CTRL_AES_MODE_R0_1: u32 = 0x01;
133 }
134 }
135 #[doc = "Security level of the allowed access for memory region1"]
136 pub mod SECURITY_LEVEL_R1 {
137 pub const offset: u32 = 12;
138 pub const mask: u32 = 0x03 << offset;
139 pub mod R {}
140 pub mod W {}
141 pub mod RW {}
142 }
143 #[doc = "AES mode of region1"]
144 pub mod CTRL_AES_MODE_R1 {
145 pub const offset: u32 = 14;
146 pub const mask: u32 = 0x01 << offset;
147 pub mod R {}
148 pub mod W {}
149 pub mod RW {
150 #[doc = "ECB"]
151 pub const CTRL_AES_MODE_R1_0: u32 = 0;
152 #[doc = "CTR"]
153 pub const CTRL_AES_MODE_R1_1: u32 = 0x01;
154 }
155 }
156 #[doc = "Lock bit for bee_enable"]
157 pub mod BEE_ENABLE_LOCK {
158 pub const offset: u32 = 16;
159 pub const mask: u32 = 0x01 << offset;
160 pub mod R {}
161 pub mod W {}
162 pub mod RW {}
163 }
164 #[doc = "Lock bit for ctrl_clk_en"]
165 pub mod CTRL_CLK_EN_LOCK {
166 pub const offset: u32 = 17;
167 pub const mask: u32 = 0x01 << offset;
168 pub mod R {}
169 pub mod W {}
170 pub mod RW {}
171 }
172 #[doc = "Lock bit for ctrl_sftrst"]
173 pub mod CTRL_SFTRST_N_LOCK {
174 pub const offset: u32 = 18;
175 pub const mask: u32 = 0x01 << offset;
176 pub mod R {}
177 pub mod W {}
178 pub mod RW {}
179 }
180 #[doc = "Lock bit for region1 address boundary"]
181 pub mod REGION1_ADDR_LOCK {
182 pub const offset: u32 = 19;
183 pub const mask: u32 = 0x01 << offset;
184 pub mod R {}
185 pub mod W {}
186 pub mod RW {}
187 }
188 #[doc = "Lock bit for key_valid"]
189 pub mod KEY_VALID_LOCK {
190 pub const offset: u32 = 20;
191 pub const mask: u32 = 0x01 << offset;
192 pub mod R {}
193 pub mod W {}
194 pub mod RW {}
195 }
196 #[doc = "Lock bit for key_region_sel"]
197 pub mod KEY_REGION_SEL_LOCK {
198 pub const offset: u32 = 21;
199 pub const mask: u32 = 0x01 << offset;
200 pub mod R {}
201 pub mod W {}
202 pub mod RW {}
203 }
204 #[doc = "Lock bit for ac_prot"]
205 pub mod AC_PROT_EN_LOCK {
206 pub const offset: u32 = 22;
207 pub const mask: u32 = 0x01 << offset;
208 pub mod R {}
209 pub mod W {}
210 pub mod RW {}
211 }
212 #[doc = "Lock bit for little_endian"]
213 pub mod LITTLE_ENDIAN_LOCK {
214 pub const offset: u32 = 23;
215 pub const mask: u32 = 0x01 << offset;
216 pub mod R {}
217 pub mod W {}
218 pub mod RW {}
219 }
220 #[doc = "Lock bits for security_level_r0"]
221 pub mod SECURITY_LEVEL_R0_LOCK {
222 pub const offset: u32 = 24;
223 pub const mask: u32 = 0x03 << offset;
224 pub mod R {}
225 pub mod W {}
226 pub mod RW {}
227 }
228 #[doc = "Lock bit for region0 ctrl_aes_mode"]
229 pub mod CTRL_AES_MODE_R0_LOCK {
230 pub const offset: u32 = 26;
231 pub const mask: u32 = 0x01 << offset;
232 pub mod R {}
233 pub mod W {}
234 pub mod RW {}
235 }
236 #[doc = "Lock bit for region0 AES key"]
237 pub mod REGION0_KEY_LOCK {
238 pub const offset: u32 = 27;
239 pub const mask: u32 = 0x01 << offset;
240 pub mod R {}
241 pub mod W {}
242 pub mod RW {}
243 }
244 #[doc = "Lock bits for security_level_r1"]
245 pub mod SECURITY_LEVEL_R1_LOCK {
246 pub const offset: u32 = 28;
247 pub const mask: u32 = 0x03 << offset;
248 pub mod R {}
249 pub mod W {}
250 pub mod RW {}
251 }
252 #[doc = "Lock bit for region1 ctrl_aes_mode"]
253 pub mod CTRL_AES_MODE_R1_LOCK {
254 pub const offset: u32 = 30;
255 pub const mask: u32 = 0x01 << offset;
256 pub mod R {}
257 pub mod W {}
258 pub mod RW {}
259 }
260 #[doc = "Lock bit for region1 AES key"]
261 pub mod REGION1_KEY_LOCK {
262 pub const offset: u32 = 31;
263 pub const mask: u32 = 0x01 << offset;
264 pub mod R {}
265 pub mod W {}
266 pub mod RW {}
267 }
268}
269#[doc = "no description available"]
270pub mod ADDR_OFFSET0 {
271 #[doc = "Signed offset for BEE region 0"]
272 pub mod ADDR_OFFSET0 {
273 pub const offset: u32 = 0;
274 pub const mask: u32 = 0xffff << offset;
275 pub mod R {}
276 pub mod W {}
277 pub mod RW {}
278 }
279 #[doc = "Lock bits for addr_offset0"]
280 pub mod ADDR_OFFSET0_LOCK {
281 pub const offset: u32 = 16;
282 pub const mask: u32 = 0xffff << offset;
283 pub mod R {}
284 pub mod W {}
285 pub mod RW {}
286 }
287}
288#[doc = "no description available"]
289pub mod ADDR_OFFSET1 {
290 #[doc = "Signed offset for BEE region 1"]
291 pub mod ADDR_OFFSET1 {
292 pub const offset: u32 = 0;
293 pub const mask: u32 = 0xffff << offset;
294 pub mod R {}
295 pub mod W {}
296 pub mod RW {}
297 }
298 #[doc = "Lock bits for addr_offset1"]
299 pub mod ADDR_OFFSET1_LOCK {
300 pub const offset: u32 = 16;
301 pub const mask: u32 = 0xffff << offset;
302 pub mod R {}
303 pub mod W {}
304 pub mod RW {}
305 }
306}
307#[doc = "no description available"]
308pub mod AES_KEY0_W0 {
309 #[doc = "AES 128 key from software"]
310 pub mod KEY0 {
311 pub const offset: u32 = 0;
312 pub const mask: u32 = 0xffff_ffff << offset;
313 pub mod R {}
314 pub mod W {}
315 pub mod RW {}
316 }
317}
318#[doc = "no description available"]
319pub mod AES_KEY0_W1 {
320 #[doc = "AES 128 key from software"]
321 pub mod KEY1 {
322 pub const offset: u32 = 0;
323 pub const mask: u32 = 0xffff_ffff << offset;
324 pub mod R {}
325 pub mod W {}
326 pub mod RW {}
327 }
328}
329#[doc = "no description available"]
330pub mod AES_KEY0_W2 {
331 #[doc = "AES 128 key from software"]
332 pub mod KEY2 {
333 pub const offset: u32 = 0;
334 pub const mask: u32 = 0xffff_ffff << offset;
335 pub mod R {}
336 pub mod W {}
337 pub mod RW {}
338 }
339}
340#[doc = "no description available"]
341pub mod AES_KEY0_W3 {
342 #[doc = "AES 128 key from software"]
343 pub mod KEY3 {
344 pub const offset: u32 = 0;
345 pub const mask: u32 = 0xffff_ffff << offset;
346 pub mod R {}
347 pub mod W {}
348 pub mod RW {}
349 }
350}
351#[doc = "no description available"]
352pub mod STATUS {
353 #[doc = "bit 7: Protected region-3 access violation bit 6: Protected region-2 access violation bit 5: Protected region-1 access violation bit 4: Protected region-0 access violation bit 3: Region-1 read channel security violation bit 2: Read channel illegal access detected bit 1: Region-0 read channel security violation bit 0: Disable abort"]
354 pub mod IRQ_VEC {
355 pub const offset: u32 = 0;
356 pub const mask: u32 = 0xff << offset;
357 pub mod R {}
358 pub mod W {}
359 pub mod RW {}
360 }
361 #[doc = "1'b1: BEE is idle; 1'b0: BEE is active"]
362 pub mod BEE_IDLE {
363 pub const offset: u32 = 8;
364 pub const mask: u32 = 0x01 << offset;
365 pub mod R {}
366 pub mod W {}
367 pub mod RW {}
368 }
369}
370#[doc = "no description available"]
371pub mod CTR_NONCE0_W0 {
372 #[doc = "Nonce0 from software for CTR, for region0. Nonce0={Nonce03,Nonce02,Nonce01,Nonce00}"]
373 pub mod NONCE00 {
374 pub const offset: u32 = 0;
375 pub const mask: u32 = 0xffff_ffff << offset;
376 pub mod R {}
377 pub mod W {}
378 pub mod RW {}
379 }
380}
381#[doc = "no description available"]
382pub mod CTR_NONCE0_W1 {
383 #[doc = "Nonce0 from software for CTR, for region0. Nonce0={Nonce03,Nonce02,Nonce01,Nonce00}"]
384 pub mod NONCE01 {
385 pub const offset: u32 = 0;
386 pub const mask: u32 = 0xffff_ffff << offset;
387 pub mod R {}
388 pub mod W {}
389 pub mod RW {}
390 }
391}
392#[doc = "no description available"]
393pub mod CTR_NONCE0_W2 {
394 #[doc = "Nonce0 from software for CTR, for region0. Nonce0={Nonce03,Nonce02,Nonce01,Nonce00}"]
395 pub mod NONCE02 {
396 pub const offset: u32 = 0;
397 pub const mask: u32 = 0xffff_ffff << offset;
398 pub mod R {}
399 pub mod W {}
400 pub mod RW {}
401 }
402}
403#[doc = "no description available"]
404pub mod CTR_NONCE0_W3 {
405 #[doc = "Nonce0 from software for CTR, for region0. Nonce0={Nonce03,Nonce02,Nonce01,Nonce00}"]
406 pub mod NONCE03 {
407 pub const offset: u32 = 0;
408 pub const mask: u32 = 0xffff_ffff << offset;
409 pub mod R {}
410 pub mod W {}
411 pub mod RW {}
412 }
413}
414#[doc = "no description available"]
415pub mod CTR_NONCE1_W0 {
416 #[doc = "Nonce1 from software for CTR, for region1. Nonce1={Nonce13,Nonce12,Nonce11,Nonce10}"]
417 pub mod NONCE10 {
418 pub const offset: u32 = 0;
419 pub const mask: u32 = 0xffff_ffff << offset;
420 pub mod R {}
421 pub mod W {}
422 pub mod RW {}
423 }
424}
425#[doc = "no description available"]
426pub mod CTR_NONCE1_W1 {
427 #[doc = "Nonce1 from software for CTR, for region1. Nonce1={Nonce13,Nonce12,Nonce11,Nonce10}"]
428 pub mod NONCE11 {
429 pub const offset: u32 = 0;
430 pub const mask: u32 = 0xffff_ffff << offset;
431 pub mod R {}
432 pub mod W {}
433 pub mod RW {}
434 }
435}
436#[doc = "no description available"]
437pub mod CTR_NONCE1_W2 {
438 #[doc = "Nonce1 from software for CTR, for region1. Nonce1={Nonce13,Nonce12,Nonce11,Nonce10}"]
439 pub mod NONCE12 {
440 pub const offset: u32 = 0;
441 pub const mask: u32 = 0xffff_ffff << offset;
442 pub mod R {}
443 pub mod W {}
444 pub mod RW {}
445 }
446}
447#[doc = "no description available"]
448pub mod CTR_NONCE1_W3 {
449 #[doc = "Nonce1 from software for CTR, for region1. Nonce1={Nonce13,Nonce12,Nonce11,Nonce10}"]
450 pub mod NONCE13 {
451 pub const offset: u32 = 0;
452 pub const mask: u32 = 0xffff_ffff << offset;
453 pub mod R {}
454 pub mod W {}
455 pub mod RW {}
456 }
457}
458#[doc = "no description available"]
459pub mod REGION1_TOP {
460 #[doc = "Address upper limit of region1"]
461 pub mod REGION1_TOP {
462 pub const offset: u32 = 0;
463 pub const mask: u32 = 0xffff_ffff << offset;
464 pub mod R {}
465 pub mod W {}
466 pub mod RW {}
467 }
468}
469#[doc = "no description available"]
470pub mod REGION1_BOT {
471 #[doc = "Address lower limit of region1"]
472 pub mod REGION1_BOT {
473 pub const offset: u32 = 0;
474 pub const mask: u32 = 0xffff_ffff << offset;
475 pub mod R {}
476 pub mod W {}
477 pub mod RW {}
478 }
479}