imxrt_ral/blocks/imxrt1015/
flexram.rs

1#[doc = "FLEXRAM"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "TCM CRTL Register"]
5    pub TCM_CTRL: crate::RWRegister<u32>,
6    _reserved0: [u8; 0x0c],
7    #[doc = "Interrupt Status Register"]
8    pub INT_STATUS: crate::RWRegister<u32>,
9    #[doc = "Interrupt Status Enable Register"]
10    pub INT_STAT_EN: crate::RWRegister<u32>,
11    #[doc = "Interrupt Enable Register"]
12    pub INT_SIG_EN: crate::RWRegister<u32>,
13}
14#[doc = "TCM CRTL Register"]
15pub mod TCM_CTRL {
16    #[doc = "TCM Write Wait Mode Enable"]
17    pub mod TCM_WWAIT_EN {
18        pub const offset: u32 = 0;
19        pub const mask: u32 = 0x01 << offset;
20        pub mod R {}
21        pub mod W {}
22        pub mod RW {
23            #[doc = "TCM write fast mode: Write RAM accesses are expected to be finished in 1-cycle."]
24            pub const TCM_WWAIT_EN_0: u32 = 0;
25            #[doc = "TCM write wait mode: Write RAM accesses are expected to be finished in 2-cycles."]
26            pub const TCM_WWAIT_EN_1: u32 = 0x01;
27        }
28    }
29    #[doc = "TCM Read Wait Mode Enable"]
30    pub mod TCM_RWAIT_EN {
31        pub const offset: u32 = 1;
32        pub const mask: u32 = 0x01 << offset;
33        pub mod R {}
34        pub mod W {}
35        pub mod RW {
36            #[doc = "TCM read fast mode: Read RAM accesses are expected to be finished in 1-cycle."]
37            pub const TCM_RWAIT_EN_0: u32 = 0;
38            #[doc = "TCM read wait mode: Read RAM accesses are expected to be finished in 2-cycles."]
39            pub const TCM_RWAIT_EN_1: u32 = 0x01;
40        }
41    }
42    #[doc = "Force RAM Clock Always On"]
43    pub mod FORCE_CLK_ON {
44        pub const offset: u32 = 2;
45        pub const mask: u32 = 0x01 << offset;
46        pub mod R {}
47        pub mod W {}
48        pub mod RW {}
49    }
50}
51#[doc = "Interrupt Status Register"]
52pub mod INT_STATUS {
53    #[doc = "ITCM Access Error Status"]
54    pub mod ITCM_ERR_STATUS {
55        pub const offset: u32 = 3;
56        pub const mask: u32 = 0x01 << offset;
57        pub mod R {}
58        pub mod W {}
59        pub mod RW {
60            #[doc = "ITCM access error does not happen"]
61            pub const ITCM_ERR_STATUS_0: u32 = 0;
62            #[doc = "ITCM access error happens."]
63            pub const ITCM_ERR_STATUS_1: u32 = 0x01;
64        }
65    }
66    #[doc = "DTCM Access Error Status"]
67    pub mod DTCM_ERR_STATUS {
68        pub const offset: u32 = 4;
69        pub const mask: u32 = 0x01 << offset;
70        pub mod R {}
71        pub mod W {}
72        pub mod RW {
73            #[doc = "DTCM access error does not happen"]
74            pub const DTCM_ERR_STATUS_0: u32 = 0;
75            #[doc = "DTCM access error happens."]
76            pub const DTCM_ERR_STATUS_1: u32 = 0x01;
77        }
78    }
79    #[doc = "OCRAM Access Error Status"]
80    pub mod OCRAM_ERR_STATUS {
81        pub const offset: u32 = 5;
82        pub const mask: u32 = 0x01 << offset;
83        pub mod R {}
84        pub mod W {}
85        pub mod RW {
86            #[doc = "OCRAM access error does not happen"]
87            pub const OCRAM_ERR_STATUS_0: u32 = 0;
88            #[doc = "OCRAM access error happens."]
89            pub const OCRAM_ERR_STATUS_1: u32 = 0x01;
90        }
91    }
92}
93#[doc = "Interrupt Status Enable Register"]
94pub mod INT_STAT_EN {
95    #[doc = "ITCM Access Error Status Enable"]
96    pub mod ITCM_ERR_STAT_EN {
97        pub const offset: u32 = 3;
98        pub const mask: u32 = 0x01 << offset;
99        pub mod R {}
100        pub mod W {}
101        pub mod RW {
102            #[doc = "Masked"]
103            pub const ITCM_ERR_STAT_EN_0: u32 = 0;
104            #[doc = "Enabled"]
105            pub const ITCM_ERR_STAT_EN_1: u32 = 0x01;
106        }
107    }
108    #[doc = "DTCM Access Error Status Enable"]
109    pub mod DTCM_ERR_STAT_EN {
110        pub const offset: u32 = 4;
111        pub const mask: u32 = 0x01 << offset;
112        pub mod R {}
113        pub mod W {}
114        pub mod RW {
115            #[doc = "Masked"]
116            pub const DTCM_ERR_STAT_EN_0: u32 = 0;
117            #[doc = "Enabled"]
118            pub const DTCM_ERR_STAT_EN_1: u32 = 0x01;
119        }
120    }
121    #[doc = "OCRAM Access Error Status Enable"]
122    pub mod OCRAM_ERR_STAT_EN {
123        pub const offset: u32 = 5;
124        pub const mask: u32 = 0x01 << offset;
125        pub mod R {}
126        pub mod W {}
127        pub mod RW {
128            #[doc = "Masked"]
129            pub const OCRAM_ERR_STAT_EN_0: u32 = 0;
130            #[doc = "Enabled"]
131            pub const OCRAM_ERR_STAT_EN_1: u32 = 0x01;
132        }
133    }
134}
135#[doc = "Interrupt Enable Register"]
136pub mod INT_SIG_EN {
137    #[doc = "ITCM Access Error Interrupt Enable"]
138    pub mod ITCM_ERR_SIG_EN {
139        pub const offset: u32 = 3;
140        pub const mask: u32 = 0x01 << offset;
141        pub mod R {}
142        pub mod W {}
143        pub mod RW {
144            #[doc = "Masked"]
145            pub const ITCM_ERR_SIG_EN_0: u32 = 0;
146            #[doc = "Enabled"]
147            pub const ITCM_ERR_SIG_EN_1: u32 = 0x01;
148        }
149    }
150    #[doc = "DTCM Access Error Interrupt Enable"]
151    pub mod DTCM_ERR_SIG_EN {
152        pub const offset: u32 = 4;
153        pub const mask: u32 = 0x01 << offset;
154        pub mod R {}
155        pub mod W {}
156        pub mod RW {
157            #[doc = "Masked"]
158            pub const DTCM_ERR_SIG_EN_0: u32 = 0;
159            #[doc = "Enabled"]
160            pub const DTCM_ERR_SIG_EN_1: u32 = 0x01;
161        }
162    }
163    #[doc = "OCRAM Access Error Interrupt Enable"]
164    pub mod OCRAM_ERR_SIG_EN {
165        pub const offset: u32 = 5;
166        pub const mask: u32 = 0x01 << offset;
167        pub mod R {}
168        pub mod W {}
169        pub mod RW {
170            #[doc = "Masked"]
171            pub const OCRAM_ERR_SIG_EN_0: u32 = 0;
172            #[doc = "Enabled"]
173            pub const OCRAM_ERR_SIG_EN_1: u32 = 0x01;
174        }
175    }
176}
imxrt_ral/blocks/imxrt1015/flexram.rs

imxrt_ral/blocks/imxrt1015/
flexram.rs
