imxrt_ral/blocks/imxrt1021/
adc.rs

1#[doc = "Analog-to-Digital Converter"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "Control register for hardware triggers"]
5    pub HC0: crate::RWRegister<u32>,
6    #[doc = "Control register for hardware triggers"]
7    pub HC: [crate::RWRegister<u32>; 7usize],
8    #[doc = "Status register for HW triggers"]
9    pub HS: crate::RORegister<u32>,
10    #[doc = "Data result register for HW triggers"]
11    pub R0: crate::RORegister<u32>,
12    #[doc = "Data result register for HW triggers"]
13    pub R: [crate::RORegister<u32>; 7usize],
14    #[doc = "Configuration register"]
15    pub CFG: crate::RWRegister<u32>,
16    #[doc = "General control register"]
17    pub GC: crate::RWRegister<u32>,
18    #[doc = "General status register"]
19    pub GS: crate::RWRegister<u32>,
20    #[doc = "Compare value register"]
21    pub CV: crate::RWRegister<u32>,
22    #[doc = "Offset correction value register"]
23    pub OFS: crate::RWRegister<u32>,
24    #[doc = "Calibration value register"]
25    pub CAL: crate::RWRegister<u32>,
26}
27#[doc = "Control register for hardware triggers"]
28pub mod HC0 {
29    #[doc = "Input Channel Select"]
30    pub mod ADCH {
31        pub const offset: u32 = 0;
32        pub const mask: u32 = 0x1f << offset;
33        pub mod R {}
34        pub mod W {}
35        pub mod RW {
36            #[doc = "External channel selection from ADC_ETC"]
37            pub const ADCH_16: u32 = 0x10;
38            #[doc = "VREFSH = internal channel, for ADC self-test, hard connected to VRH internally"]
39            pub const ADCH_25: u32 = 0x19;
40            #[doc = "Conversion Disabled. Hardware Triggers will not initiate any conversion."]
41            pub const ADCH_31: u32 = 0x1f;
42        }
43    }
44    #[doc = "Conversion Complete Interrupt Enable/Disable Control"]
45    pub mod AIEN {
46        pub const offset: u32 = 7;
47        pub const mask: u32 = 0x01 << offset;
48        pub mod R {}
49        pub mod W {}
50        pub mod RW {
51            #[doc = "Conversion complete interrupt disabled"]
52            pub const AIEN_0: u32 = 0;
53            #[doc = "Conversion complete interrupt enabled"]
54            pub const AIEN_1: u32 = 0x01;
55        }
56    }
57}
58#[doc = "Control register for hardware triggers"]
59pub mod HC {
60    #[doc = "Input Channel Select"]
61    pub mod ADCH {
62        pub const offset: u32 = 0;
63        pub const mask: u32 = 0x1f << offset;
64        pub mod R {}
65        pub mod W {}
66        pub mod RW {
67            #[doc = "External channel selection from ADC_ETC"]
68            pub const ADCH_16: u32 = 0x10;
69            #[doc = "VREFSH = internal channel, for ADC self-test, hard connected to VRH internally"]
70            pub const ADCH_25: u32 = 0x19;
71            #[doc = "Conversion Disabled. Hardware Triggers will not initiate any conversion."]
72            pub const ADCH_31: u32 = 0x1f;
73        }
74    }
75    #[doc = "Conversion Complete Interrupt Enable/Disable Control"]
76    pub mod AIEN {
77        pub const offset: u32 = 7;
78        pub const mask: u32 = 0x01 << offset;
79        pub mod R {}
80        pub mod W {}
81        pub mod RW {
82            #[doc = "Conversion complete interrupt disabled"]
83            pub const AIEN_0: u32 = 0;
84            #[doc = "Conversion complete interrupt enabled"]
85            pub const AIEN_1: u32 = 0x01;
86        }
87    }
88}
89#[doc = "Status register for HW triggers"]
90pub mod HS {
91    #[doc = "Conversion Complete Flag"]
92    pub mod COCO0 {
93        pub const offset: u32 = 0;
94        pub const mask: u32 = 0x01 << offset;
95        pub mod R {}
96        pub mod W {}
97        pub mod RW {}
98    }
99}
100#[doc = "Data result register for HW triggers"]
101pub mod R0 {
102    #[doc = "Data (result of an ADC conversion)"]
103    pub mod CDATA {
104        pub const offset: u32 = 0;
105        pub const mask: u32 = 0x0fff << offset;
106        pub mod R {}
107        pub mod W {}
108        pub mod RW {}
109    }
110}
111#[doc = "Data result register for HW triggers"]
112pub mod R {
113    #[doc = "Data (result of an ADC conversion)"]
114    pub mod CDATA {
115        pub const offset: u32 = 0;
116        pub const mask: u32 = 0x0fff << offset;
117        pub mod R {}
118        pub mod W {}
119        pub mod RW {}
120    }
121}
122#[doc = "Configuration register"]
123pub mod CFG {
124    #[doc = "Input Clock Select"]
125    pub mod ADICLK {
126        pub const offset: u32 = 0;
127        pub const mask: u32 = 0x03 << offset;
128        pub mod R {}
129        pub mod W {}
130        pub mod RW {
131            #[doc = "IPG clock"]
132            pub const ADICLK_0: u32 = 0;
133            #[doc = "IPG clock divided by 2"]
134            pub const ADICLK_1: u32 = 0x01;
135            #[doc = "Asynchronous clock (ADACK)"]
136            pub const ADICLK_3: u32 = 0x03;
137        }
138    }
139    #[doc = "Conversion Mode Selection"]
140    pub mod MODE {
141        pub const offset: u32 = 2;
142        pub const mask: u32 = 0x03 << offset;
143        pub mod R {}
144        pub mod W {}
145        pub mod RW {
146            #[doc = "8-bit conversion"]
147            pub const MODE_0: u32 = 0;
148            #[doc = "10-bit conversion"]
149            pub const MODE_1: u32 = 0x01;
150            #[doc = "12-bit conversion"]
151            pub const MODE_2: u32 = 0x02;
152        }
153    }
154    #[doc = "Long Sample Time Configuration"]
155    pub mod ADLSMP {
156        pub const offset: u32 = 4;
157        pub const mask: u32 = 0x01 << offset;
158        pub mod R {}
159        pub mod W {}
160        pub mod RW {
161            #[doc = "Short sample mode."]
162            pub const ADLSMP_0: u32 = 0;
163            #[doc = "Long sample mode."]
164            pub const ADLSMP_1: u32 = 0x01;
165        }
166    }
167    #[doc = "Clock Divide Select"]
168    pub mod ADIV {
169        pub const offset: u32 = 5;
170        pub const mask: u32 = 0x03 << offset;
171        pub mod R {}
172        pub mod W {}
173        pub mod RW {
174            #[doc = "Input clock"]
175            pub const ADIV_0: u32 = 0;
176            #[doc = "Input clock / 2"]
177            pub const ADIV_1: u32 = 0x01;
178            #[doc = "Input clock / 4"]
179            pub const ADIV_2: u32 = 0x02;
180            #[doc = "Input clock / 8"]
181            pub const ADIV_3: u32 = 0x03;
182        }
183    }
184    #[doc = "Low-Power Configuration"]
185    pub mod ADLPC {
186        pub const offset: u32 = 7;
187        pub const mask: u32 = 0x01 << offset;
188        pub mod R {}
189        pub mod W {}
190        pub mod RW {
191            #[doc = "ADC hard block not in low power mode."]
192            pub const ADLPC_0: u32 = 0;
193            #[doc = "ADC hard block in low power mode."]
194            pub const ADLPC_1: u32 = 0x01;
195        }
196    }
197    #[doc = "Defines the sample time duration"]
198    pub mod ADSTS {
199        pub const offset: u32 = 8;
200        pub const mask: u32 = 0x03 << offset;
201        pub mod R {}
202        pub mod W {}
203        pub mod RW {
204            #[doc = "Sample period (ADC clocks) = 2 if ADLSMP=0b Sample period (ADC clocks) = 12 if ADLSMP=1b"]
205            pub const ADSTS_0: u32 = 0;
206            #[doc = "Sample period (ADC clocks) = 4 if ADLSMP=0b Sample period (ADC clocks) = 16 if ADLSMP=1b"]
207            pub const ADSTS_1: u32 = 0x01;
208            #[doc = "Sample period (ADC clocks) = 6 if ADLSMP=0b Sample period (ADC clocks) = 20 if ADLSMP=1b"]
209            pub const ADSTS_2: u32 = 0x02;
210            #[doc = "Sample period (ADC clocks) = 8 if ADLSMP=0b Sample period (ADC clocks) = 24 if ADLSMP=1b"]
211            pub const ADSTS_3: u32 = 0x03;
212        }
213    }
214    #[doc = "High Speed Configuration"]
215    pub mod ADHSC {
216        pub const offset: u32 = 10;
217        pub const mask: u32 = 0x01 << offset;
218        pub mod R {}
219        pub mod W {}
220        pub mod RW {
221            #[doc = "Normal conversion selected."]
222            pub const ADHSC_0: u32 = 0;
223            #[doc = "High speed conversion selected."]
224            pub const ADHSC_1: u32 = 0x01;
225        }
226    }
227    #[doc = "Voltage Reference Selection"]
228    pub mod REFSEL {
229        pub const offset: u32 = 11;
230        pub const mask: u32 = 0x03 << offset;
231        pub mod R {}
232        pub mod W {}
233        pub mod RW {
234            #[doc = "Selects VREFH/VREFL as reference voltage."]
235            pub const REFSEL_0: u32 = 0;
236        }
237    }
238    #[doc = "Conversion Trigger Select"]
239    pub mod ADTRG {
240        pub const offset: u32 = 13;
241        pub const mask: u32 = 0x01 << offset;
242        pub mod R {}
243        pub mod W {}
244        pub mod RW {
245            #[doc = "Software trigger selected"]
246            pub const ADTRG_0: u32 = 0;
247            #[doc = "Hardware trigger selected"]
248            pub const ADTRG_1: u32 = 0x01;
249        }
250    }
251    #[doc = "Hardware Average select"]
252    pub mod AVGS {
253        pub const offset: u32 = 14;
254        pub const mask: u32 = 0x03 << offset;
255        pub mod R {}
256        pub mod W {}
257        pub mod RW {
258            #[doc = "4 samples averaged"]
259            pub const AVGS_0: u32 = 0;
260            #[doc = "8 samples averaged"]
261            pub const AVGS_1: u32 = 0x01;
262            #[doc = "16 samples averaged"]
263            pub const AVGS_2: u32 = 0x02;
264            #[doc = "32 samples averaged"]
265            pub const AVGS_3: u32 = 0x03;
266        }
267    }
268    #[doc = "Data Overwrite Enable"]
269    pub mod OVWREN {
270        pub const offset: u32 = 16;
271        pub const mask: u32 = 0x01 << offset;
272        pub mod R {}
273        pub mod W {}
274        pub mod RW {
275            #[doc = "Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data."]
276            pub const OVWREN_0: u32 = 0;
277            #[doc = "Enable the overwriting."]
278            pub const OVWREN_1: u32 = 0x01;
279        }
280    }
281}
282#[doc = "General control register"]
283pub mod GC {
284    #[doc = "Asynchronous clock output enable"]
285    pub mod ADACKEN {
286        pub const offset: u32 = 0;
287        pub const mask: u32 = 0x01 << offset;
288        pub mod R {}
289        pub mod W {}
290        pub mod RW {
291            #[doc = "Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active."]
292            pub const ADACKEN_0: u32 = 0;
293            #[doc = "Asynchronous clock and clock output enabled regardless of the state of the ADC"]
294            pub const ADACKEN_1: u32 = 0x01;
295        }
296    }
297    #[doc = "DMA Enable"]
298    pub mod DMAEN {
299        pub const offset: u32 = 1;
300        pub const mask: u32 = 0x01 << offset;
301        pub mod R {}
302        pub mod W {}
303        pub mod RW {
304            #[doc = "DMA disabled (default)"]
305            pub const DMAEN_0: u32 = 0;
306            #[doc = "DMA enabled"]
307            pub const DMAEN_1: u32 = 0x01;
308        }
309    }
310    #[doc = "Compare Function Range Enable"]
311    pub mod ACREN {
312        pub const offset: u32 = 2;
313        pub const mask: u32 = 0x01 << offset;
314        pub mod R {}
315        pub mod W {}
316        pub mod RW {
317            #[doc = "Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared."]
318            pub const ACREN_0: u32 = 0;
319            #[doc = "Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared."]
320            pub const ACREN_1: u32 = 0x01;
321        }
322    }
323    #[doc = "Compare Function Greater Than Enable"]
324    pub mod ACFGT {
325        pub const offset: u32 = 3;
326        pub const mask: u32 = 0x01 << offset;
327        pub mod R {}
328        pub mod W {}
329        pub mod RW {
330            #[doc = "Configures \"Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive\" functionality based on the values placed in the ADC_CV register."]
331            pub const ACFGT_0: u32 = 0;
332            #[doc = "Configures \"Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive\" functionality based on the values placed in the ADC_CV registers."]
333            pub const ACFGT_1: u32 = 0x01;
334        }
335    }
336    #[doc = "Compare Function Enable"]
337    pub mod ACFE {
338        pub const offset: u32 = 4;
339        pub const mask: u32 = 0x01 << offset;
340        pub mod R {}
341        pub mod W {}
342        pub mod RW {
343            #[doc = "Compare function disabled"]
344            pub const ACFE_0: u32 = 0;
345            #[doc = "Compare function enabled"]
346            pub const ACFE_1: u32 = 0x01;
347        }
348    }
349    #[doc = "Hardware average enable"]
350    pub mod AVGE {
351        pub const offset: u32 = 5;
352        pub const mask: u32 = 0x01 << offset;
353        pub mod R {}
354        pub mod W {}
355        pub mod RW {
356            #[doc = "Hardware average function disabled"]
357            pub const AVGE_0: u32 = 0;
358            #[doc = "Hardware average function enabled"]
359            pub const AVGE_1: u32 = 0x01;
360        }
361    }
362    #[doc = "Continuous Conversion Enable"]
363    pub mod ADCO {
364        pub const offset: u32 = 6;
365        pub const mask: u32 = 0x01 << offset;
366        pub mod R {}
367        pub mod W {}
368        pub mod RW {
369            #[doc = "One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion."]
370            pub const ADCO_0: u32 = 0;
371            #[doc = "Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion."]
372            pub const ADCO_1: u32 = 0x01;
373        }
374    }
375    #[doc = "Calibration"]
376    pub mod CAL {
377        pub const offset: u32 = 7;
378        pub const mask: u32 = 0x01 << offset;
379        pub mod R {}
380        pub mod W {}
381        pub mod RW {}
382    }
383}
384#[doc = "General status register"]
385pub mod GS {
386    #[doc = "Conversion Active"]
387    pub mod ADACT {
388        pub const offset: u32 = 0;
389        pub const mask: u32 = 0x01 << offset;
390        pub mod R {}
391        pub mod W {}
392        pub mod RW {
393            #[doc = "Conversion not in progress."]
394            pub const ADACT_0: u32 = 0;
395            #[doc = "Conversion in progress."]
396            pub const ADACT_1: u32 = 0x01;
397        }
398    }
399    #[doc = "Calibration Failed Flag"]
400    pub mod CALF {
401        pub const offset: u32 = 1;
402        pub const mask: u32 = 0x01 << offset;
403        pub mod R {}
404        pub mod W {}
405        pub mod RW {
406            #[doc = "Calibration completed normally."]
407            pub const CALF_0: u32 = 0;
408            #[doc = "Calibration failed. ADC accuracy specifications are not guaranteed."]
409            pub const CALF_1: u32 = 0x01;
410        }
411    }
412    #[doc = "Asynchronous wakeup interrupt status"]
413    pub mod AWKST {
414        pub const offset: u32 = 2;
415        pub const mask: u32 = 0x01 << offset;
416        pub mod R {}
417        pub mod W {}
418        pub mod RW {
419            #[doc = "No asynchronous interrupt."]
420            pub const AWKST_0: u32 = 0;
421            #[doc = "Asynchronous wake up interrupt occurred in stop mode."]
422            pub const AWKST_1: u32 = 0x01;
423        }
424    }
425}
426#[doc = "Compare value register"]
427pub mod CV {
428    #[doc = "Compare Value 1"]
429    pub mod CV1 {
430        pub const offset: u32 = 0;
431        pub const mask: u32 = 0x0fff << offset;
432        pub mod R {}
433        pub mod W {}
434        pub mod RW {}
435    }
436    #[doc = "Compare Value 2"]
437    pub mod CV2 {
438        pub const offset: u32 = 16;
439        pub const mask: u32 = 0x0fff << offset;
440        pub mod R {}
441        pub mod W {}
442        pub mod RW {}
443    }
444}
445#[doc = "Offset correction value register"]
446pub mod OFS {
447    #[doc = "Offset value"]
448    pub mod OFS {
449        pub const offset: u32 = 0;
450        pub const mask: u32 = 0x0fff << offset;
451        pub mod R {}
452        pub mod W {}
453        pub mod RW {}
454    }
455    #[doc = "Sign bit"]
456    pub mod SIGN {
457        pub const offset: u32 = 12;
458        pub const mask: u32 = 0x01 << offset;
459        pub mod R {}
460        pub mod W {}
461        pub mod RW {
462            #[doc = "The offset value is added with the raw result"]
463            pub const SIGN_0: u32 = 0;
464            #[doc = "The offset value is subtracted from the raw converted value"]
465            pub const SIGN_1: u32 = 0x01;
466        }
467    }
468}
469#[doc = "Calibration value register"]
470pub mod CAL {
471    #[doc = "Calibration Result Value"]
472    pub mod CAL_CODE {
473        pub const offset: u32 = 0;
474        pub const mask: u32 = 0x0f << offset;
475        pub mod R {}
476        pub mod W {}
477        pub mod RW {}
478    }
479}