imxrt_ral/blocks/imxrt1021/
enc.rs

1#[doc = "Quadrature Decoder"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "Control Register"]
5    pub CTRL: crate::RWRegister<u16>,
6    #[doc = "Input Filter Register"]
7    pub FILT: crate::RWRegister<u16>,
8    #[doc = "Watchdog Timeout Register"]
9    pub WTR: crate::RWRegister<u16>,
10    #[doc = "Position Difference Counter Register"]
11    pub POSD: crate::RWRegister<u16>,
12    #[doc = "Position Difference Hold Register"]
13    pub POSDH: crate::RORegister<u16>,
14    #[doc = "Revolution Counter Register"]
15    pub REV: crate::RWRegister<u16>,
16    #[doc = "Revolution Hold Register"]
17    pub REVH: crate::RORegister<u16>,
18    #[doc = "Upper Position Counter Register"]
19    pub UPOS: crate::RWRegister<u16>,
20    #[doc = "Lower Position Counter Register"]
21    pub LPOS: crate::RWRegister<u16>,
22    #[doc = "Upper Position Hold Register"]
23    pub UPOSH: crate::RORegister<u16>,
24    #[doc = "Lower Position Hold Register"]
25    pub LPOSH: crate::RORegister<u16>,
26    #[doc = "Upper Initialization Register"]
27    pub UINIT: crate::RWRegister<u16>,
28    #[doc = "Lower Initialization Register"]
29    pub LINIT: crate::RWRegister<u16>,
30    #[doc = "Input Monitor Register"]
31    pub IMR: crate::RORegister<u16>,
32    #[doc = "Test Register"]
33    pub TST: crate::RWRegister<u16>,
34    #[doc = "Control 2 Register"]
35    pub CTRL2: crate::RWRegister<u16>,
36    #[doc = "Upper Modulus Register"]
37    pub UMOD: crate::RWRegister<u16>,
38    #[doc = "Lower Modulus Register"]
39    pub LMOD: crate::RWRegister<u16>,
40    #[doc = "Upper Position Compare Register"]
41    pub UCOMP: crate::RWRegister<u16>,
42    #[doc = "Lower Position Compare Register"]
43    pub LCOMP: crate::RWRegister<u16>,
44}
45#[doc = "Control Register"]
46pub mod CTRL {
47    #[doc = "Compare Interrupt Enable"]
48    pub mod CMPIE {
49        pub const offset: u16 = 0;
50        pub const mask: u16 = 0x01 << offset;
51        pub mod R {}
52        pub mod W {}
53        pub mod RW {
54            #[doc = "Compare interrupt is disabled"]
55            pub const CMPIE_0: u16 = 0;
56            #[doc = "Compare interrupt is enabled"]
57            pub const CMPIE_1: u16 = 0x01;
58        }
59    }
60    #[doc = "Compare Interrupt Request"]
61    pub mod CMPIRQ {
62        pub const offset: u16 = 1;
63        pub const mask: u16 = 0x01 << offset;
64        pub mod R {}
65        pub mod W {}
66        pub mod RW {
67            #[doc = "No match has occurred"]
68            pub const CMPIRQ_0: u16 = 0;
69            #[doc = "COMP match has occurred"]
70            pub const CMPIRQ_1: u16 = 0x01;
71        }
72    }
73    #[doc = "Watchdog Enable"]
74    pub mod WDE {
75        pub const offset: u16 = 2;
76        pub const mask: u16 = 0x01 << offset;
77        pub mod R {}
78        pub mod W {}
79        pub mod RW {
80            #[doc = "Watchdog timer is disabled"]
81            pub const WDE_0: u16 = 0;
82            #[doc = "Watchdog timer is enabled"]
83            pub const WDE_1: u16 = 0x01;
84        }
85    }
86    #[doc = "Watchdog Timeout Interrupt Enable"]
87    pub mod DIE {
88        pub const offset: u16 = 3;
89        pub const mask: u16 = 0x01 << offset;
90        pub mod R {}
91        pub mod W {}
92        pub mod RW {
93            #[doc = "Watchdog timer interrupt is disabled"]
94            pub const DIE_0: u16 = 0;
95            #[doc = "Watchdog timer interrupt is enabled"]
96            pub const DIE_1: u16 = 0x01;
97        }
98    }
99    #[doc = "Watchdog Timeout Interrupt Request"]
100    pub mod DIRQ {
101        pub const offset: u16 = 4;
102        pub const mask: u16 = 0x01 << offset;
103        pub mod R {}
104        pub mod W {}
105        pub mod RW {
106            #[doc = "No interrupt has occurred"]
107            pub const DIRQ_0: u16 = 0;
108            #[doc = "Watchdog timeout interrupt has occurred"]
109            pub const DIRQ_1: u16 = 0x01;
110        }
111    }
112    #[doc = "Use Negative Edge of INDEX Pulse"]
113    pub mod XNE {
114        pub const offset: u16 = 5;
115        pub const mask: u16 = 0x01 << offset;
116        pub mod R {}
117        pub mod W {}
118        pub mod RW {
119            #[doc = "Use positive transition edge of INDEX pulse"]
120            pub const XNE_0: u16 = 0;
121            #[doc = "Use negative transition edge of INDEX pulse"]
122            pub const XNE_1: u16 = 0x01;
123        }
124    }
125    #[doc = "INDEX Triggered Initialization of Position Counters UPOS and LPOS"]
126    pub mod XIP {
127        pub const offset: u16 = 6;
128        pub const mask: u16 = 0x01 << offset;
129        pub mod R {}
130        pub mod W {}
131        pub mod RW {
132            #[doc = "No action"]
133            pub const XIP_0: u16 = 0;
134            #[doc = "INDEX pulse initializes the position counter"]
135            pub const XIP_1: u16 = 0x01;
136        }
137    }
138    #[doc = "INDEX Pulse Interrupt Enable"]
139    pub mod XIE {
140        pub const offset: u16 = 7;
141        pub const mask: u16 = 0x01 << offset;
142        pub mod R {}
143        pub mod W {}
144        pub mod RW {
145            #[doc = "INDEX pulse interrupt is disabled"]
146            pub const XIE_0: u16 = 0;
147            #[doc = "INDEX pulse interrupt is enabled"]
148            pub const XIE_1: u16 = 0x01;
149        }
150    }
151    #[doc = "INDEX Pulse Interrupt Request"]
152    pub mod XIRQ {
153        pub const offset: u16 = 8;
154        pub const mask: u16 = 0x01 << offset;
155        pub mod R {}
156        pub mod W {}
157        pub mod RW {
158            #[doc = "No interrupt has occurred"]
159            pub const XIRQ_0: u16 = 0;
160            #[doc = "INDEX pulse interrupt has occurred"]
161            pub const XIRQ_1: u16 = 0x01;
162        }
163    }
164    #[doc = "Enable Signal Phase Count Mode"]
165    pub mod PH1 {
166        pub const offset: u16 = 9;
167        pub const mask: u16 = 0x01 << offset;
168        pub mod R {}
169        pub mod W {}
170        pub mod RW {
171            #[doc = "Use standard quadrature decoder where PHASEA and PHASEB represent a two phase quadrature signal."]
172            pub const PH1_0: u16 = 0;
173            #[doc = "Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The PHASEB input and the REV bit control the counter direction. If CTRL\\[REV\\] = 0, PHASEB = 0, then count up If CTRL\\[REV\\] = 0, PHASEB = 1, then count down If CTRL\\[REV\\] = 1, PHASEB = 0, then count down If CTRL\\[REV\\] = 1, PHASEB = 1, then count up"]
174            pub const PH1_1: u16 = 0x01;
175        }
176    }
177    #[doc = "Enable Reverse Direction Counting"]
178    pub mod REV {
179        pub const offset: u16 = 10;
180        pub const mask: u16 = 0x01 << offset;
181        pub mod R {}
182        pub mod W {}
183        pub mod RW {
184            #[doc = "Count normally"]
185            pub const REV_0: u16 = 0;
186            #[doc = "Count in the reverse direction"]
187            pub const REV_1: u16 = 0x01;
188        }
189    }
190    #[doc = "Software Triggered Initialization of Position Counters UPOS and LPOS"]
191    pub mod SWIP {
192        pub const offset: u16 = 11;
193        pub const mask: u16 = 0x01 << offset;
194        pub mod R {}
195        pub mod W {}
196        pub mod RW {
197            #[doc = "No action"]
198            pub const SWIP_0: u16 = 0;
199            #[doc = "Initialize position counter"]
200            pub const SWIP_1: u16 = 0x01;
201        }
202    }
203    #[doc = "Use Negative Edge of HOME Input"]
204    pub mod HNE {
205        pub const offset: u16 = 12;
206        pub const mask: u16 = 0x01 << offset;
207        pub mod R {}
208        pub mod W {}
209        pub mod RW {
210            #[doc = "Use positive going edge-to-trigger initialization of position counters UPOS and LPOS"]
211            pub const HNE_0: u16 = 0;
212            #[doc = "Use negative going edge-to-trigger initialization of position counters UPOS and LPOS"]
213            pub const HNE_1: u16 = 0x01;
214        }
215    }
216    #[doc = "Enable HOME to Initialize Position Counters UPOS and LPOS"]
217    pub mod HIP {
218        pub const offset: u16 = 13;
219        pub const mask: u16 = 0x01 << offset;
220        pub mod R {}
221        pub mod W {}
222        pub mod RW {
223            #[doc = "No action"]
224            pub const HIP_0: u16 = 0;
225            #[doc = "HOME signal initializes the position counter"]
226            pub const HIP_1: u16 = 0x01;
227        }
228    }
229    #[doc = "HOME Interrupt Enable"]
230    pub mod HIE {
231        pub const offset: u16 = 14;
232        pub const mask: u16 = 0x01 << offset;
233        pub mod R {}
234        pub mod W {}
235        pub mod RW {
236            #[doc = "Disable HOME interrupts"]
237            pub const HIE_0: u16 = 0;
238            #[doc = "Enable HOME interrupts"]
239            pub const HIE_1: u16 = 0x01;
240        }
241    }
242    #[doc = "HOME Signal Transition Interrupt Request"]
243    pub mod HIRQ {
244        pub const offset: u16 = 15;
245        pub const mask: u16 = 0x01 << offset;
246        pub mod R {}
247        pub mod W {}
248        pub mod RW {
249            #[doc = "No interrupt"]
250            pub const HIRQ_0: u16 = 0;
251            #[doc = "HOME signal transition interrupt request"]
252            pub const HIRQ_1: u16 = 0x01;
253        }
254    }
255}
256#[doc = "Input Filter Register"]
257pub mod FILT {
258    #[doc = "Input Filter Sample Period"]
259    pub mod FILT_PER {
260        pub const offset: u16 = 0;
261        pub const mask: u16 = 0xff << offset;
262        pub mod R {}
263        pub mod W {}
264        pub mod RW {}
265    }
266    #[doc = "Input Filter Sample Count"]
267    pub mod FILT_CNT {
268        pub const offset: u16 = 8;
269        pub const mask: u16 = 0x07 << offset;
270        pub mod R {}
271        pub mod W {}
272        pub mod RW {}
273    }
274    #[doc = "Clock prescaler value"]
275    pub mod FILT_PRSC {
276        pub const offset: u16 = 13;
277        pub const mask: u16 = 0x07 << offset;
278        pub mod R {}
279        pub mod W {}
280        pub mod RW {}
281    }
282}
283#[doc = "Watchdog Timeout Register"]
284pub mod WTR {
285    #[doc = "WDOG\\[15:0\\] is a binary representation of the number of clock cycles plus one that the watchdog timer counts before timing out and optionally generating an interrupt"]
286    pub mod WDOG {
287        pub const offset: u16 = 0;
288        pub const mask: u16 = 0xffff << offset;
289        pub mod R {}
290        pub mod W {}
291        pub mod RW {}
292    }
293}
294#[doc = "Position Difference Counter Register"]
295pub mod POSD {
296    #[doc = "This read/write register contains the position change in value occurring between each read of the position register"]
297    pub mod POSD {
298        pub const offset: u16 = 0;
299        pub const mask: u16 = 0xffff << offset;
300        pub mod R {}
301        pub mod W {}
302        pub mod RW {}
303    }
304}
305#[doc = "Position Difference Hold Register"]
306pub mod POSDH {
307    #[doc = "This read-only register contains a snapshot of the value of the POSD register"]
308    pub mod POSDH {
309        pub const offset: u16 = 0;
310        pub const mask: u16 = 0xffff << offset;
311        pub mod R {}
312        pub mod W {}
313        pub mod RW {}
314    }
315}
316#[doc = "Revolution Counter Register"]
317pub mod REV {
318    #[doc = "This read/write register contains the current value of the revolution counter."]
319    pub mod REV {
320        pub const offset: u16 = 0;
321        pub const mask: u16 = 0xffff << offset;
322        pub mod R {}
323        pub mod W {}
324        pub mod RW {}
325    }
326}
327#[doc = "Revolution Hold Register"]
328pub mod REVH {
329    #[doc = "This read-only register contains a snapshot of the value of the REV register."]
330    pub mod REVH {
331        pub const offset: u16 = 0;
332        pub const mask: u16 = 0xffff << offset;
333        pub mod R {}
334        pub mod W {}
335        pub mod RW {}
336    }
337}
338#[doc = "Upper Position Counter Register"]
339pub mod UPOS {
340    #[doc = "This read/write register contains the upper (most significant) half of the position counter"]
341    pub mod POS {
342        pub const offset: u16 = 0;
343        pub const mask: u16 = 0xffff << offset;
344        pub mod R {}
345        pub mod W {}
346        pub mod RW {}
347    }
348}
349#[doc = "Lower Position Counter Register"]
350pub mod LPOS {
351    #[doc = "This read/write register contains the lower (least significant) half of the position counter"]
352    pub mod POS {
353        pub const offset: u16 = 0;
354        pub const mask: u16 = 0xffff << offset;
355        pub mod R {}
356        pub mod W {}
357        pub mod RW {}
358    }
359}
360#[doc = "Upper Position Hold Register"]
361pub mod UPOSH {
362    #[doc = "This read-only register contains a snapshot of the UPOS register."]
363    pub mod POSH {
364        pub const offset: u16 = 0;
365        pub const mask: u16 = 0xffff << offset;
366        pub mod R {}
367        pub mod W {}
368        pub mod RW {}
369    }
370}
371#[doc = "Lower Position Hold Register"]
372pub mod LPOSH {
373    #[doc = "This read-only register contains a snapshot of the LPOS register."]
374    pub mod POSH {
375        pub const offset: u16 = 0;
376        pub const mask: u16 = 0xffff << offset;
377        pub mod R {}
378        pub mod W {}
379        pub mod RW {}
380    }
381}
382#[doc = "Upper Initialization Register"]
383pub mod UINIT {
384    #[doc = "This read/write register contains the value to be used to initialize the upper half of the position counter (UPOS)"]
385    pub mod INIT {
386        pub const offset: u16 = 0;
387        pub const mask: u16 = 0xffff << offset;
388        pub mod R {}
389        pub mod W {}
390        pub mod RW {}
391    }
392}
393#[doc = "Lower Initialization Register"]
394pub mod LINIT {
395    #[doc = "This read/write register contains the value to be used to initialize the lower half of the position counter (LPOS)"]
396    pub mod INIT {
397        pub const offset: u16 = 0;
398        pub const mask: u16 = 0xffff << offset;
399        pub mod R {}
400        pub mod W {}
401        pub mod RW {}
402    }
403}
404#[doc = "Input Monitor Register"]
405pub mod IMR {
406    #[doc = "This is the raw HOME input."]
407    pub mod HOME {
408        pub const offset: u16 = 0;
409        pub const mask: u16 = 0x01 << offset;
410        pub mod R {}
411        pub mod W {}
412        pub mod RW {}
413    }
414    #[doc = "This is the raw INDEX input."]
415    pub mod INDEX {
416        pub const offset: u16 = 1;
417        pub const mask: u16 = 0x01 << offset;
418        pub mod R {}
419        pub mod W {}
420        pub mod RW {}
421    }
422    #[doc = "This is the raw PHASEB input."]
423    pub mod PHB {
424        pub const offset: u16 = 2;
425        pub const mask: u16 = 0x01 << offset;
426        pub mod R {}
427        pub mod W {}
428        pub mod RW {}
429    }
430    #[doc = "This is the raw PHASEA input."]
431    pub mod PHA {
432        pub const offset: u16 = 3;
433        pub const mask: u16 = 0x01 << offset;
434        pub mod R {}
435        pub mod W {}
436        pub mod RW {}
437    }
438    #[doc = "This is the filtered version of HOME input."]
439    pub mod FHOM {
440        pub const offset: u16 = 4;
441        pub const mask: u16 = 0x01 << offset;
442        pub mod R {}
443        pub mod W {}
444        pub mod RW {}
445    }
446    #[doc = "This is the filtered version of INDEX input."]
447    pub mod FIND {
448        pub const offset: u16 = 5;
449        pub const mask: u16 = 0x01 << offset;
450        pub mod R {}
451        pub mod W {}
452        pub mod RW {}
453    }
454    #[doc = "This is the filtered version of PHASEB input."]
455    pub mod FPHB {
456        pub const offset: u16 = 6;
457        pub const mask: u16 = 0x01 << offset;
458        pub mod R {}
459        pub mod W {}
460        pub mod RW {}
461    }
462    #[doc = "This is the filtered version of PHASEA input."]
463    pub mod FPHA {
464        pub const offset: u16 = 7;
465        pub const mask: u16 = 0x01 << offset;
466        pub mod R {}
467        pub mod W {}
468        pub mod RW {}
469    }
470}
471#[doc = "Test Register"]
472pub mod TST {
473    #[doc = "These bits hold the number of quadrature advances to generate."]
474    pub mod TEST_COUNT {
475        pub const offset: u16 = 0;
476        pub const mask: u16 = 0xff << offset;
477        pub mod R {}
478        pub mod W {}
479        pub mod RW {}
480    }
481    #[doc = "These bits hold the period of quadrature phase in IPBus clock cycles."]
482    pub mod TEST_PERIOD {
483        pub const offset: u16 = 8;
484        pub const mask: u16 = 0x1f << offset;
485        pub mod R {}
486        pub mod W {}
487        pub mod RW {}
488    }
489    #[doc = "Quadrature Decoder Negative Signal"]
490    pub mod QDN {
491        pub const offset: u16 = 13;
492        pub const mask: u16 = 0x01 << offset;
493        pub mod R {}
494        pub mod W {}
495        pub mod RW {
496            #[doc = "Leaves quadrature decoder signal in a positive direction"]
497            pub const QDN_0: u16 = 0;
498            #[doc = "Generates a negative quadrature decoder signal"]
499            pub const QDN_1: u16 = 0x01;
500        }
501    }
502    #[doc = "Test Counter Enable"]
503    pub mod TCE {
504        pub const offset: u16 = 14;
505        pub const mask: u16 = 0x01 << offset;
506        pub mod R {}
507        pub mod W {}
508        pub mod RW {
509            #[doc = "Test count is not enabled"]
510            pub const TCE_0: u16 = 0;
511            #[doc = "Test count is enabled"]
512            pub const TCE_1: u16 = 0x01;
513        }
514    }
515    #[doc = "Test Mode Enable"]
516    pub mod TEN {
517        pub const offset: u16 = 15;
518        pub const mask: u16 = 0x01 << offset;
519        pub mod R {}
520        pub mod W {}
521        pub mod RW {
522            #[doc = "Test module is not enabled"]
523            pub const TEN_0: u16 = 0;
524            #[doc = "Test module is enabled"]
525            pub const TEN_1: u16 = 0x01;
526        }
527    }
528}
529#[doc = "Control 2 Register"]
530pub mod CTRL2 {
531    #[doc = "Update Hold Registers"]
532    pub mod UPDHLD {
533        pub const offset: u16 = 0;
534        pub const mask: u16 = 0x01 << offset;
535        pub mod R {}
536        pub mod W {}
537        pub mod RW {
538            #[doc = "Disable updates of hold registers on rising edge of TRIGGER"]
539            pub const UPDHLD_0: u16 = 0;
540            #[doc = "Enable updates of hold registers on rising edge of TRIGGER"]
541            pub const UPDHLD_1: u16 = 0x01;
542        }
543    }
544    #[doc = "Update Position Registers"]
545    pub mod UPDPOS {
546        pub const offset: u16 = 1;
547        pub const mask: u16 = 0x01 << offset;
548        pub mod R {}
549        pub mod W {}
550        pub mod RW {
551            #[doc = "No action for POSD, REV, UPOS and LPOS on rising edge of TRIGGER"]
552            pub const UPDPOS_0: u16 = 0;
553            #[doc = "Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER"]
554            pub const UPDPOS_1: u16 = 0x01;
555        }
556    }
557    #[doc = "Enable Modulo Counting"]
558    pub mod MOD {
559        pub const offset: u16 = 2;
560        pub const mask: u16 = 0x01 << offset;
561        pub mod R {}
562        pub mod W {}
563        pub mod RW {
564            #[doc = "Disable modulo counting"]
565            pub const MOD_0: u16 = 0;
566            #[doc = "Enable modulo counting"]
567            pub const MOD_1: u16 = 0x01;
568        }
569    }
570    #[doc = "Count Direction Flag"]
571    pub mod DIR {
572        pub const offset: u16 = 3;
573        pub const mask: u16 = 0x01 << offset;
574        pub mod R {}
575        pub mod W {}
576        pub mod RW {
577            #[doc = "Last count was in the down direction"]
578            pub const DIR_0: u16 = 0;
579            #[doc = "Last count was in the up direction"]
580            pub const DIR_1: u16 = 0x01;
581        }
582    }
583    #[doc = "Roll-under Interrupt Enable"]
584    pub mod RUIE {
585        pub const offset: u16 = 4;
586        pub const mask: u16 = 0x01 << offset;
587        pub mod R {}
588        pub mod W {}
589        pub mod RW {
590            #[doc = "Roll-under interrupt is disabled"]
591            pub const RUIE_0: u16 = 0;
592            #[doc = "Roll-under interrupt is enabled"]
593            pub const RUIE_1: u16 = 0x01;
594        }
595    }
596    #[doc = "Roll-under Interrupt Request"]
597    pub mod RUIRQ {
598        pub const offset: u16 = 5;
599        pub const mask: u16 = 0x01 << offset;
600        pub mod R {}
601        pub mod W {}
602        pub mod RW {
603            #[doc = "No roll-under has occurred"]
604            pub const RUIRQ_0: u16 = 0;
605            #[doc = "Roll-under has occurred"]
606            pub const RUIRQ_1: u16 = 0x01;
607        }
608    }
609    #[doc = "Roll-over Interrupt Enable"]
610    pub mod ROIE {
611        pub const offset: u16 = 6;
612        pub const mask: u16 = 0x01 << offset;
613        pub mod R {}
614        pub mod W {}
615        pub mod RW {
616            #[doc = "Roll-over interrupt is disabled"]
617            pub const ROIE_0: u16 = 0;
618            #[doc = "Roll-over interrupt is enabled"]
619            pub const ROIE_1: u16 = 0x01;
620        }
621    }
622    #[doc = "Roll-over Interrupt Request"]
623    pub mod ROIRQ {
624        pub const offset: u16 = 7;
625        pub const mask: u16 = 0x01 << offset;
626        pub mod R {}
627        pub mod W {}
628        pub mod RW {
629            #[doc = "No roll-over has occurred"]
630            pub const ROIRQ_0: u16 = 0;
631            #[doc = "Roll-over has occurred"]
632            pub const ROIRQ_1: u16 = 0x01;
633        }
634    }
635    #[doc = "Revolution Counter Modulus Enable"]
636    pub mod REVMOD {
637        pub const offset: u16 = 8;
638        pub const mask: u16 = 0x01 << offset;
639        pub mod R {}
640        pub mod W {}
641        pub mod RW {
642            #[doc = "Use INDEX pulse to increment/decrement revolution counter (REV)."]
643            pub const REVMOD_0: u16 = 0;
644            #[doc = "Use modulus counting roll-over/under to increment/decrement revolution counter (REV)."]
645            pub const REVMOD_1: u16 = 0x01;
646        }
647    }
648    #[doc = "Output Control"]
649    pub mod OUTCTL {
650        pub const offset: u16 = 9;
651        pub const mask: u16 = 0x01 << offset;
652        pub mod R {}
653        pub mod W {}
654        pub mod RW {
655            #[doc = "POSMATCH pulses when a match occurs between the position counters (POS) and the compare value (COMP)."]
656            pub const OUTCTL_0: u16 = 0;
657            #[doc = "POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read."]
658            pub const OUTCTL_1: u16 = 0x01;
659        }
660    }
661    #[doc = "Simultaneous PHASEA and PHASEB Change Interrupt Enable"]
662    pub mod SABIE {
663        pub const offset: u16 = 10;
664        pub const mask: u16 = 0x01 << offset;
665        pub mod R {}
666        pub mod W {}
667        pub mod RW {
668            #[doc = "Simultaneous PHASEA and PHASEB change interrupt disabled."]
669            pub const SABIE_0: u16 = 0;
670            #[doc = "Simultaneous PHASEA and PHASEB change interrupt enabled."]
671            pub const SABIE_1: u16 = 0x01;
672        }
673    }
674    #[doc = "Simultaneous PHASEA and PHASEB Change Interrupt Request"]
675    pub mod SABIRQ {
676        pub const offset: u16 = 11;
677        pub const mask: u16 = 0x01 << offset;
678        pub mod R {}
679        pub mod W {}
680        pub mod RW {
681            #[doc = "No simultaneous change of PHASEA and PHASEB has occurred."]
682            pub const SABIRQ_0: u16 = 0;
683            #[doc = "A simultaneous change of PHASEA and PHASEB has occurred."]
684            pub const SABIRQ_1: u16 = 0x01;
685        }
686    }
687}
688#[doc = "Upper Modulus Register"]
689pub mod UMOD {
690    #[doc = "This read/write register contains the upper (most significant) half of the modulus register"]
691    pub mod MOD {
692        pub const offset: u16 = 0;
693        pub const mask: u16 = 0xffff << offset;
694        pub mod R {}
695        pub mod W {}
696        pub mod RW {}
697    }
698}
699#[doc = "Lower Modulus Register"]
700pub mod LMOD {
701    #[doc = "This read/write register contains the lower (least significant) half of the modulus register"]
702    pub mod MOD {
703        pub const offset: u16 = 0;
704        pub const mask: u16 = 0xffff << offset;
705        pub mod R {}
706        pub mod W {}
707        pub mod RW {}
708    }
709}
710#[doc = "Upper Position Compare Register"]
711pub mod UCOMP {
712    #[doc = "This read/write register contains the upper (most significant) half of the position compare register"]
713    pub mod COMP {
714        pub const offset: u16 = 0;
715        pub const mask: u16 = 0xffff << offset;
716        pub mod R {}
717        pub mod W {}
718        pub mod RW {}
719    }
720}
721#[doc = "Lower Position Compare Register"]
722pub mod LCOMP {
723    #[doc = "This read/write register contains the lower (least significant) half of the position compare register"]
724    pub mod COMP {
725        pub const offset: u16 = 0;
726        pub const mask: u16 = 0xffff << offset;
727        pub mod R {}
728        pub mod W {}
729        pub mod RW {}
730    }
731}