imxrt_ral/blocks/imxrt1021/
iomuxc_snvs.rs1#[doc = "IOMUXC_SNVS"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register"]
5 pub SW_MUX_CTL_PAD_WAKEUP: crate::RWRegister<u32>,
6 #[doc = "SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register"]
7 pub SW_MUX_CTL_PAD_PMIC_ON_REQ: crate::RWRegister<u32>,
8 #[doc = "SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register"]
9 pub SW_MUX_CTL_PAD_PMIC_STBY_REQ: crate::RWRegister<u32>,
10 #[doc = "SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register"]
11 pub SW_PAD_CTL_PAD_TEST_MODE: crate::RWRegister<u32>,
12 #[doc = "SW_PAD_CTL_PAD_POR_B SW PAD Control Register"]
13 pub SW_PAD_CTL_PAD_POR_B: crate::RWRegister<u32>,
14 #[doc = "SW_PAD_CTL_PAD_ONOFF SW PAD Control Register"]
15 pub SW_PAD_CTL_PAD_ONOFF: crate::RWRegister<u32>,
16 #[doc = "SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register"]
17 pub SW_PAD_CTL_PAD_WAKEUP: crate::RWRegister<u32>,
18 #[doc = "SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register"]
19 pub SW_PAD_CTL_PAD_PMIC_ON_REQ: crate::RWRegister<u32>,
20 #[doc = "SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register"]
21 pub SW_PAD_CTL_PAD_PMIC_STBY_REQ: crate::RWRegister<u32>,
22}
23#[doc = "SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register"]
24pub mod SW_MUX_CTL_PAD_WAKEUP {
25 #[doc = "MUX Mode Select Field."]
26 pub mod MUX_MODE {
27 pub const offset: u32 = 0;
28 pub const mask: u32 = 0x07 << offset;
29 pub mod R {}
30 pub mod W {}
31 pub mod RW {
32 #[doc = "Select mux mode: ALT5 mux port: GPIO5_IO00 of instance: gpio5"]
33 pub const ALT5: u32 = 0x05;
34 #[doc = "Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue"]
35 pub const ALT7: u32 = 0x07;
36 }
37 }
38 #[doc = "Software Input On Field."]
39 pub mod SION {
40 pub const offset: u32 = 4;
41 pub const mask: u32 = 0x01 << offset;
42 pub mod R {}
43 pub mod W {}
44 pub mod RW {
45 #[doc = "Input Path is determined by functionality"]
46 pub const DISABLED: u32 = 0;
47 #[doc = "Force input path of pad WAKEUP"]
48 pub const ENABLED: u32 = 0x01;
49 }
50 }
51}
52#[doc = "SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register"]
53pub mod SW_MUX_CTL_PAD_PMIC_ON_REQ {
54 #[doc = "MUX Mode Select Field."]
55 pub mod MUX_MODE {
56 pub const offset: u32 = 0;
57 pub const mask: u32 = 0x07 << offset;
58 pub mod R {}
59 pub mod W {}
60 pub mod RW {
61 #[doc = "Select mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of instance: snvs_lp"]
62 pub const ALT0: u32 = 0;
63 #[doc = "Select mux mode: ALT5 mux port: GPIO5_IO01 of instance: gpio5"]
64 pub const ALT5: u32 = 0x05;
65 }
66 }
67 #[doc = "Software Input On Field."]
68 pub mod SION {
69 pub const offset: u32 = 4;
70 pub const mask: u32 = 0x01 << offset;
71 pub mod R {}
72 pub mod W {}
73 pub mod RW {
74 #[doc = "Input Path is determined by functionality"]
75 pub const DISABLED: u32 = 0;
76 #[doc = "Force input path of pad PMIC_ON_REQ"]
77 pub const ENABLED: u32 = 0x01;
78 }
79 }
80}
81#[doc = "SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register"]
82pub mod SW_MUX_CTL_PAD_PMIC_STBY_REQ {
83 #[doc = "MUX Mode Select Field."]
84 pub mod MUX_MODE {
85 pub const offset: u32 = 0;
86 pub const mask: u32 = 0x07 << offset;
87 pub mod R {}
88 pub mod W {}
89 pub mod RW {
90 #[doc = "Select mux mode: ALT0 mux port: CCM_PMIC_VSTBY_REQ of instance: ccm"]
91 pub const ALT0: u32 = 0;
92 #[doc = "Select mux mode: ALT5 mux port: GPIO5_IO02 of instance: gpio5"]
93 pub const ALT5: u32 = 0x05;
94 }
95 }
96 #[doc = "Software Input On Field."]
97 pub mod SION {
98 pub const offset: u32 = 4;
99 pub const mask: u32 = 0x01 << offset;
100 pub mod R {}
101 pub mod W {}
102 pub mod RW {
103 #[doc = "Input Path is determined by functionality"]
104 pub const DISABLED: u32 = 0;
105 #[doc = "Force input path of pad PMIC_STBY_REQ"]
106 pub const ENABLED: u32 = 0x01;
107 }
108 }
109}
110#[doc = "SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register"]
111pub mod SW_PAD_CTL_PAD_TEST_MODE {
112 #[doc = "Slew Rate Field"]
113 pub mod SRE {
114 pub const offset: u32 = 0;
115 pub const mask: u32 = 0x01 << offset;
116 pub mod R {}
117 pub mod W {}
118 pub mod RW {
119 #[doc = "Slow Slew Rate"]
120 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
121 #[doc = "Fast Slew Rate"]
122 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
123 }
124 }
125 #[doc = "Drive Strength Field"]
126 pub mod DSE {
127 pub const offset: u32 = 3;
128 pub const mask: u32 = 0x07 << offset;
129 pub mod R {}
130 pub mod W {}
131 pub mod RW {
132 #[doc = "output driver disabled;"]
133 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
134 #[doc = "R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)"]
135 pub const DSE_1_R0_260_OHM___3_3V__150_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
136 #[doc = "R0/2"]
137 pub const DSE_2_R0_2: u32 = 0x02;
138 #[doc = "R0/3"]
139 pub const DSE_3_R0_3: u32 = 0x03;
140 #[doc = "R0/4"]
141 pub const DSE_4_R0_4: u32 = 0x04;
142 #[doc = "R0/5"]
143 pub const DSE_5_R0_5: u32 = 0x05;
144 #[doc = "R0/6"]
145 pub const DSE_6_R0_6: u32 = 0x06;
146 #[doc = "R0/7"]
147 pub const DSE_7_R0_7: u32 = 0x07;
148 }
149 }
150 #[doc = "Speed Field"]
151 pub mod SPEED {
152 pub const offset: u32 = 6;
153 pub const mask: u32 = 0x03 << offset;
154 pub mod R {}
155 pub mod W {}
156 pub mod RW {
157 #[doc = "medium(100MHz)"]
158 pub const SPEED: u32 = 0x02;
159 }
160 }
161 #[doc = "Open Drain Enable Field"]
162 pub mod ODE {
163 pub const offset: u32 = 11;
164 pub const mask: u32 = 0x01 << offset;
165 pub mod R {}
166 pub mod W {}
167 pub mod RW {
168 #[doc = "Open Drain Disabled"]
169 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
170 #[doc = "Open Drain Enabled"]
171 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
172 }
173 }
174 #[doc = "Pull / Keep Enable Field"]
175 pub mod PKE {
176 pub const offset: u32 = 12;
177 pub const mask: u32 = 0x01 << offset;
178 pub mod R {}
179 pub mod W {}
180 pub mod RW {
181 #[doc = "Pull/Keeper Disabled"]
182 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
183 #[doc = "Pull/Keeper Enabled"]
184 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
185 }
186 }
187 #[doc = "Pull / Keep Select Field"]
188 pub mod PUE {
189 pub const offset: u32 = 13;
190 pub const mask: u32 = 0x01 << offset;
191 pub mod R {}
192 pub mod W {}
193 pub mod RW {
194 #[doc = "Keeper"]
195 pub const PUE_0_KEEPER: u32 = 0;
196 #[doc = "Pull"]
197 pub const PUE_1_PULL: u32 = 0x01;
198 }
199 }
200 #[doc = "Pull Up / Down Config. Field"]
201 pub mod PUS {
202 pub const offset: u32 = 14;
203 pub const mask: u32 = 0x03 << offset;
204 pub mod R {}
205 pub mod W {}
206 pub mod RW {
207 #[doc = "100K Ohm Pull Down"]
208 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
209 #[doc = "47K Ohm Pull Up"]
210 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
211 #[doc = "100K Ohm Pull Up"]
212 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
213 #[doc = "22K Ohm Pull Up"]
214 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
215 }
216 }
217 #[doc = "Hyst. Enable Field"]
218 pub mod HYS {
219 pub const offset: u32 = 16;
220 pub const mask: u32 = 0x01 << offset;
221 pub mod R {}
222 pub mod W {}
223 pub mod RW {
224 #[doc = "Hysteresis Disabled"]
225 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
226 #[doc = "Hysteresis Enabled"]
227 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
228 }
229 }
230}
231#[doc = "SW_PAD_CTL_PAD_POR_B SW PAD Control Register"]
232pub mod SW_PAD_CTL_PAD_POR_B {
233 #[doc = "Slew Rate Field"]
234 pub mod SRE {
235 pub const offset: u32 = 0;
236 pub const mask: u32 = 0x01 << offset;
237 pub mod R {}
238 pub mod W {}
239 pub mod RW {
240 #[doc = "Slow Slew Rate"]
241 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
242 #[doc = "Fast Slew Rate"]
243 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
244 }
245 }
246 #[doc = "Drive Strength Field"]
247 pub mod DSE {
248 pub const offset: u32 = 3;
249 pub const mask: u32 = 0x07 << offset;
250 pub mod R {}
251 pub mod W {}
252 pub mod RW {
253 #[doc = "output driver disabled;"]
254 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
255 #[doc = "R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)"]
256 pub const DSE_1_R0_260_OHM___3_3V__150_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
257 #[doc = "R0/2"]
258 pub const DSE_2_R0_2: u32 = 0x02;
259 #[doc = "R0/3"]
260 pub const DSE_3_R0_3: u32 = 0x03;
261 #[doc = "R0/4"]
262 pub const DSE_4_R0_4: u32 = 0x04;
263 #[doc = "R0/5"]
264 pub const DSE_5_R0_5: u32 = 0x05;
265 #[doc = "R0/6"]
266 pub const DSE_6_R0_6: u32 = 0x06;
267 #[doc = "R0/7"]
268 pub const DSE_7_R0_7: u32 = 0x07;
269 }
270 }
271 #[doc = "Speed Field"]
272 pub mod SPEED {
273 pub const offset: u32 = 6;
274 pub const mask: u32 = 0x03 << offset;
275 pub mod R {}
276 pub mod W {}
277 pub mod RW {
278 #[doc = "medium(100MHz)"]
279 pub const SPEED: u32 = 0x02;
280 }
281 }
282 #[doc = "Open Drain Enable Field"]
283 pub mod ODE {
284 pub const offset: u32 = 11;
285 pub const mask: u32 = 0x01 << offset;
286 pub mod R {}
287 pub mod W {}
288 pub mod RW {
289 #[doc = "Open Drain Disabled"]
290 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
291 #[doc = "Open Drain Enabled"]
292 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
293 }
294 }
295 #[doc = "Pull / Keep Enable Field"]
296 pub mod PKE {
297 pub const offset: u32 = 12;
298 pub const mask: u32 = 0x01 << offset;
299 pub mod R {}
300 pub mod W {}
301 pub mod RW {
302 #[doc = "Pull/Keeper Disabled"]
303 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
304 #[doc = "Pull/Keeper Enabled"]
305 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
306 }
307 }
308 #[doc = "Pull / Keep Select Field"]
309 pub mod PUE {
310 pub const offset: u32 = 13;
311 pub const mask: u32 = 0x01 << offset;
312 pub mod R {}
313 pub mod W {}
314 pub mod RW {
315 #[doc = "Keeper"]
316 pub const PUE_0_KEEPER: u32 = 0;
317 #[doc = "Pull"]
318 pub const PUE_1_PULL: u32 = 0x01;
319 }
320 }
321 #[doc = "Pull Up / Down Config. Field"]
322 pub mod PUS {
323 pub const offset: u32 = 14;
324 pub const mask: u32 = 0x03 << offset;
325 pub mod R {}
326 pub mod W {}
327 pub mod RW {
328 #[doc = "100K Ohm Pull Down"]
329 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
330 #[doc = "47K Ohm Pull Up"]
331 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
332 #[doc = "100K Ohm Pull Up"]
333 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
334 #[doc = "22K Ohm Pull Up"]
335 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
336 }
337 }
338 #[doc = "Hyst. Enable Field"]
339 pub mod HYS {
340 pub const offset: u32 = 16;
341 pub const mask: u32 = 0x01 << offset;
342 pub mod R {}
343 pub mod W {}
344 pub mod RW {
345 #[doc = "Hysteresis Disabled"]
346 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
347 #[doc = "Hysteresis Enabled"]
348 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
349 }
350 }
351}
352#[doc = "SW_PAD_CTL_PAD_ONOFF SW PAD Control Register"]
353pub mod SW_PAD_CTL_PAD_ONOFF {
354 #[doc = "Slew Rate Field"]
355 pub mod SRE {
356 pub const offset: u32 = 0;
357 pub const mask: u32 = 0x01 << offset;
358 pub mod R {}
359 pub mod W {}
360 pub mod RW {
361 #[doc = "Slow Slew Rate"]
362 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
363 #[doc = "Fast Slew Rate"]
364 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
365 }
366 }
367 #[doc = "Drive Strength Field"]
368 pub mod DSE {
369 pub const offset: u32 = 3;
370 pub const mask: u32 = 0x07 << offset;
371 pub mod R {}
372 pub mod W {}
373 pub mod RW {
374 #[doc = "output driver disabled;"]
375 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
376 #[doc = "R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)"]
377 pub const DSE_1_R0_260_OHM___3_3V__150_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
378 #[doc = "R0/2"]
379 pub const DSE_2_R0_2: u32 = 0x02;
380 #[doc = "R0/3"]
381 pub const DSE_3_R0_3: u32 = 0x03;
382 #[doc = "R0/4"]
383 pub const DSE_4_R0_4: u32 = 0x04;
384 #[doc = "R0/5"]
385 pub const DSE_5_R0_5: u32 = 0x05;
386 #[doc = "R0/6"]
387 pub const DSE_6_R0_6: u32 = 0x06;
388 #[doc = "R0/7"]
389 pub const DSE_7_R0_7: u32 = 0x07;
390 }
391 }
392 #[doc = "Speed Field"]
393 pub mod SPEED {
394 pub const offset: u32 = 6;
395 pub const mask: u32 = 0x03 << offset;
396 pub mod R {}
397 pub mod W {}
398 pub mod RW {
399 #[doc = "medium(100MHz)"]
400 pub const SPEED: u32 = 0x02;
401 }
402 }
403 #[doc = "Open Drain Enable Field"]
404 pub mod ODE {
405 pub const offset: u32 = 11;
406 pub const mask: u32 = 0x01 << offset;
407 pub mod R {}
408 pub mod W {}
409 pub mod RW {
410 #[doc = "Open Drain Disabled"]
411 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
412 #[doc = "Open Drain Enabled"]
413 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
414 }
415 }
416 #[doc = "Pull / Keep Enable Field"]
417 pub mod PKE {
418 pub const offset: u32 = 12;
419 pub const mask: u32 = 0x01 << offset;
420 pub mod R {}
421 pub mod W {}
422 pub mod RW {
423 #[doc = "Pull/Keeper Disabled"]
424 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
425 #[doc = "Pull/Keeper Enabled"]
426 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
427 }
428 }
429 #[doc = "Pull / Keep Select Field"]
430 pub mod PUE {
431 pub const offset: u32 = 13;
432 pub const mask: u32 = 0x01 << offset;
433 pub mod R {}
434 pub mod W {}
435 pub mod RW {
436 #[doc = "Keeper"]
437 pub const PUE_0_KEEPER: u32 = 0;
438 #[doc = "Pull"]
439 pub const PUE_1_PULL: u32 = 0x01;
440 }
441 }
442 #[doc = "Pull Up / Down Config. Field"]
443 pub mod PUS {
444 pub const offset: u32 = 14;
445 pub const mask: u32 = 0x03 << offset;
446 pub mod R {}
447 pub mod W {}
448 pub mod RW {
449 #[doc = "100K Ohm Pull Down"]
450 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
451 #[doc = "47K Ohm Pull Up"]
452 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
453 #[doc = "100K Ohm Pull Up"]
454 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
455 #[doc = "22K Ohm Pull Up"]
456 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
457 }
458 }
459 #[doc = "Hyst. Enable Field"]
460 pub mod HYS {
461 pub const offset: u32 = 16;
462 pub const mask: u32 = 0x01 << offset;
463 pub mod R {}
464 pub mod W {}
465 pub mod RW {
466 #[doc = "Hysteresis Disabled"]
467 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
468 #[doc = "Hysteresis Enabled"]
469 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
470 }
471 }
472}
473#[doc = "SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register"]
474pub mod SW_PAD_CTL_PAD_WAKEUP {
475 #[doc = "Slew Rate Field"]
476 pub mod SRE {
477 pub const offset: u32 = 0;
478 pub const mask: u32 = 0x01 << offset;
479 pub mod R {}
480 pub mod W {}
481 pub mod RW {
482 #[doc = "Slow Slew Rate"]
483 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
484 #[doc = "Fast Slew Rate"]
485 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
486 }
487 }
488 #[doc = "Drive Strength Field"]
489 pub mod DSE {
490 pub const offset: u32 = 3;
491 pub const mask: u32 = 0x07 << offset;
492 pub mod R {}
493 pub mod W {}
494 pub mod RW {
495 #[doc = "output driver disabled;"]
496 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
497 #[doc = "R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)"]
498 pub const DSE_1_R0_260_OHM___3_3V__150_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
499 #[doc = "R0/2"]
500 pub const DSE_2_R0_2: u32 = 0x02;
501 #[doc = "R0/3"]
502 pub const DSE_3_R0_3: u32 = 0x03;
503 #[doc = "R0/4"]
504 pub const DSE_4_R0_4: u32 = 0x04;
505 #[doc = "R0/5"]
506 pub const DSE_5_R0_5: u32 = 0x05;
507 #[doc = "R0/6"]
508 pub const DSE_6_R0_6: u32 = 0x06;
509 #[doc = "R0/7"]
510 pub const DSE_7_R0_7: u32 = 0x07;
511 }
512 }
513 #[doc = "Speed Field"]
514 pub mod SPEED {
515 pub const offset: u32 = 6;
516 pub const mask: u32 = 0x03 << offset;
517 pub mod R {}
518 pub mod W {}
519 pub mod RW {
520 #[doc = "medium(100MHz)"]
521 pub const SPEED: u32 = 0x02;
522 }
523 }
524 #[doc = "Open Drain Enable Field"]
525 pub mod ODE {
526 pub const offset: u32 = 11;
527 pub const mask: u32 = 0x01 << offset;
528 pub mod R {}
529 pub mod W {}
530 pub mod RW {
531 #[doc = "Open Drain Disabled"]
532 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
533 #[doc = "Open Drain Enabled"]
534 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
535 }
536 }
537 #[doc = "Pull / Keep Enable Field"]
538 pub mod PKE {
539 pub const offset: u32 = 12;
540 pub const mask: u32 = 0x01 << offset;
541 pub mod R {}
542 pub mod W {}
543 pub mod RW {
544 #[doc = "Pull/Keeper Disabled"]
545 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
546 #[doc = "Pull/Keeper Enabled"]
547 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
548 }
549 }
550 #[doc = "Pull / Keep Select Field"]
551 pub mod PUE {
552 pub const offset: u32 = 13;
553 pub const mask: u32 = 0x01 << offset;
554 pub mod R {}
555 pub mod W {}
556 pub mod RW {
557 #[doc = "Keeper"]
558 pub const PUE_0_KEEPER: u32 = 0;
559 #[doc = "Pull"]
560 pub const PUE_1_PULL: u32 = 0x01;
561 }
562 }
563 #[doc = "Pull Up / Down Config. Field"]
564 pub mod PUS {
565 pub const offset: u32 = 14;
566 pub const mask: u32 = 0x03 << offset;
567 pub mod R {}
568 pub mod W {}
569 pub mod RW {
570 #[doc = "100K Ohm Pull Down"]
571 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
572 #[doc = "47K Ohm Pull Up"]
573 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
574 #[doc = "100K Ohm Pull Up"]
575 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
576 #[doc = "22K Ohm Pull Up"]
577 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
578 }
579 }
580 #[doc = "Hyst. Enable Field"]
581 pub mod HYS {
582 pub const offset: u32 = 16;
583 pub const mask: u32 = 0x01 << offset;
584 pub mod R {}
585 pub mod W {}
586 pub mod RW {
587 #[doc = "Hysteresis Disabled"]
588 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
589 #[doc = "Hysteresis Enabled"]
590 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
591 }
592 }
593}
594#[doc = "SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register"]
595pub mod SW_PAD_CTL_PAD_PMIC_ON_REQ {
596 #[doc = "Slew Rate Field"]
597 pub mod SRE {
598 pub const offset: u32 = 0;
599 pub const mask: u32 = 0x01 << offset;
600 pub mod R {}
601 pub mod W {}
602 pub mod RW {
603 #[doc = "Slow Slew Rate"]
604 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
605 #[doc = "Fast Slew Rate"]
606 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
607 }
608 }
609 #[doc = "Drive Strength Field"]
610 pub mod DSE {
611 pub const offset: u32 = 3;
612 pub const mask: u32 = 0x07 << offset;
613 pub mod R {}
614 pub mod W {}
615 pub mod RW {
616 #[doc = "output driver disabled;"]
617 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
618 #[doc = "R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)"]
619 pub const DSE_1_R0_260_OHM___3_3V__150_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
620 #[doc = "R0/2"]
621 pub const DSE_2_R0_2: u32 = 0x02;
622 #[doc = "R0/3"]
623 pub const DSE_3_R0_3: u32 = 0x03;
624 #[doc = "R0/4"]
625 pub const DSE_4_R0_4: u32 = 0x04;
626 #[doc = "R0/5"]
627 pub const DSE_5_R0_5: u32 = 0x05;
628 #[doc = "R0/6"]
629 pub const DSE_6_R0_6: u32 = 0x06;
630 #[doc = "R0/7"]
631 pub const DSE_7_R0_7: u32 = 0x07;
632 }
633 }
634 #[doc = "Speed Field"]
635 pub mod SPEED {
636 pub const offset: u32 = 6;
637 pub const mask: u32 = 0x03 << offset;
638 pub mod R {}
639 pub mod W {}
640 pub mod RW {
641 #[doc = "medium(100MHz)"]
642 pub const SPEED: u32 = 0x02;
643 }
644 }
645 #[doc = "Open Drain Enable Field"]
646 pub mod ODE {
647 pub const offset: u32 = 11;
648 pub const mask: u32 = 0x01 << offset;
649 pub mod R {}
650 pub mod W {}
651 pub mod RW {
652 #[doc = "Open Drain Disabled"]
653 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
654 #[doc = "Open Drain Enabled"]
655 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
656 }
657 }
658 #[doc = "Pull / Keep Enable Field"]
659 pub mod PKE {
660 pub const offset: u32 = 12;
661 pub const mask: u32 = 0x01 << offset;
662 pub mod R {}
663 pub mod W {}
664 pub mod RW {
665 #[doc = "Pull/Keeper Disabled"]
666 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
667 #[doc = "Pull/Keeper Enabled"]
668 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
669 }
670 }
671 #[doc = "Pull / Keep Select Field"]
672 pub mod PUE {
673 pub const offset: u32 = 13;
674 pub const mask: u32 = 0x01 << offset;
675 pub mod R {}
676 pub mod W {}
677 pub mod RW {
678 #[doc = "Keeper"]
679 pub const PUE_0_KEEPER: u32 = 0;
680 #[doc = "Pull"]
681 pub const PUE_1_PULL: u32 = 0x01;
682 }
683 }
684 #[doc = "Pull Up / Down Config. Field"]
685 pub mod PUS {
686 pub const offset: u32 = 14;
687 pub const mask: u32 = 0x03 << offset;
688 pub mod R {}
689 pub mod W {}
690 pub mod RW {
691 #[doc = "100K Ohm Pull Down"]
692 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
693 #[doc = "47K Ohm Pull Up"]
694 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
695 #[doc = "100K Ohm Pull Up"]
696 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
697 #[doc = "22K Ohm Pull Up"]
698 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
699 }
700 }
701 #[doc = "Hyst. Enable Field"]
702 pub mod HYS {
703 pub const offset: u32 = 16;
704 pub const mask: u32 = 0x01 << offset;
705 pub mod R {}
706 pub mod W {}
707 pub mod RW {
708 #[doc = "Hysteresis Disabled"]
709 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
710 #[doc = "Hysteresis Enabled"]
711 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
712 }
713 }
714}
715#[doc = "SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register"]
716pub mod SW_PAD_CTL_PAD_PMIC_STBY_REQ {
717 #[doc = "Slew Rate Field"]
718 pub mod SRE {
719 pub const offset: u32 = 0;
720 pub const mask: u32 = 0x01 << offset;
721 pub mod R {}
722 pub mod W {}
723 pub mod RW {
724 #[doc = "Slow Slew Rate"]
725 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
726 #[doc = "Fast Slew Rate"]
727 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
728 }
729 }
730 #[doc = "Drive Strength Field"]
731 pub mod DSE {
732 pub const offset: u32 = 3;
733 pub const mask: u32 = 0x07 << offset;
734 pub mod R {}
735 pub mod W {}
736 pub mod RW {
737 #[doc = "output driver disabled;"]
738 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
739 #[doc = "R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)"]
740 pub const DSE_1_R0_260_OHM___3_3V__150_OHM_1_8V__240_OHM_FOR_DDR_: u32 = 0x01;
741 #[doc = "R0/2"]
742 pub const DSE_2_R0_2: u32 = 0x02;
743 #[doc = "R0/3"]
744 pub const DSE_3_R0_3: u32 = 0x03;
745 #[doc = "R0/4"]
746 pub const DSE_4_R0_4: u32 = 0x04;
747 #[doc = "R0/5"]
748 pub const DSE_5_R0_5: u32 = 0x05;
749 #[doc = "R0/6"]
750 pub const DSE_6_R0_6: u32 = 0x06;
751 #[doc = "R0/7"]
752 pub const DSE_7_R0_7: u32 = 0x07;
753 }
754 }
755 #[doc = "Speed Field"]
756 pub mod SPEED {
757 pub const offset: u32 = 6;
758 pub const mask: u32 = 0x03 << offset;
759 pub mod R {}
760 pub mod W {}
761 pub mod RW {
762 #[doc = "medium(100MHz)"]
763 pub const SPEED: u32 = 0x02;
764 }
765 }
766 #[doc = "Open Drain Enable Field"]
767 pub mod ODE {
768 pub const offset: u32 = 11;
769 pub const mask: u32 = 0x01 << offset;
770 pub mod R {}
771 pub mod W {}
772 pub mod RW {
773 #[doc = "Open Drain Disabled"]
774 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
775 #[doc = "Open Drain Enabled"]
776 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
777 }
778 }
779 #[doc = "Pull / Keep Enable Field"]
780 pub mod PKE {
781 pub const offset: u32 = 12;
782 pub const mask: u32 = 0x01 << offset;
783 pub mod R {}
784 pub mod W {}
785 pub mod RW {
786 #[doc = "Pull/Keeper Disabled"]
787 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
788 #[doc = "Pull/Keeper Enabled"]
789 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
790 }
791 }
792 #[doc = "Pull / Keep Select Field"]
793 pub mod PUE {
794 pub const offset: u32 = 13;
795 pub const mask: u32 = 0x01 << offset;
796 pub mod R {}
797 pub mod W {}
798 pub mod RW {
799 #[doc = "Keeper"]
800 pub const PUE_0_KEEPER: u32 = 0;
801 #[doc = "Pull"]
802 pub const PUE_1_PULL: u32 = 0x01;
803 }
804 }
805 #[doc = "Pull Up / Down Config. Field"]
806 pub mod PUS {
807 pub const offset: u32 = 14;
808 pub const mask: u32 = 0x03 << offset;
809 pub mod R {}
810 pub mod W {}
811 pub mod RW {
812 #[doc = "100K Ohm Pull Down"]
813 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
814 #[doc = "47K Ohm Pull Up"]
815 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
816 #[doc = "100K Ohm Pull Up"]
817 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
818 #[doc = "22K Ohm Pull Up"]
819 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
820 }
821 }
822 #[doc = "Hyst. Enable Field"]
823 pub mod HYS {
824 pub const offset: u32 = 16;
825 pub const mask: u32 = 0x01 << offset;
826 pub mod R {}
827 pub mod W {}
828 pub mod RW {
829 #[doc = "Hysteresis Disabled"]
830 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
831 #[doc = "Hysteresis Enabled"]
832 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
833 }
834 }
835}