1#[doc = "PWM"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "Cluster SM%s, containing SM?CNT, SM?INIT, SM?CTRL2, SM?CTRL, SM?VAL0, SM?FRACVAL1, SM?VAL1, SM?FRACVAL2, SM?VAL2, SM?FRACVAL3, SM?VAL3, SM?FRACVAL4, SM?VAL4, SM?FRACVAL5, SM?VAL5, SM?FRCTRL, SM?OCTRL, SM?STS, SM?INTEN, SM?DMAEN, SM?TCTRL, SM?DISMAP0, SM?DISMAP1, SM?DTCNT0, SM?DTCNT1, SM?CAPTCTRLA, SM?CAPTCOMPA, SM?CAPTCTRLB, SM?CAPTCOMPB, SM?CAPTCTRLX, SM?CAPTCOMPX, SM?CVAL0, SM?CVAL0CYC, SM?CVAL1, SM?CVAL1CYC, SM?CVAL2, SM?CVAL2CYC, SM?CVAL3, SM?CVAL3CYC, SM?CVAL4, SM?CVAL4CYC, SM?CVAL5, SM?CVAL5CYC"]
5 pub SM: [sm::RegisterBlock; 4usize],
6 #[doc = "Output Enable Register"]
7 pub OUTEN: crate::RWRegister<u16>,
8 #[doc = "Mask Register"]
9 pub MASK: crate::RWRegister<u16>,
10 #[doc = "Software Controlled Output Register"]
11 pub SWCOUT: crate::RWRegister<u16>,
12 #[doc = "PWM Source Select Register"]
13 pub DTSRCSEL: crate::RWRegister<u16>,
14 #[doc = "Master Control Register"]
15 pub MCTRL: crate::RWRegister<u16>,
16 #[doc = "Master Control 2 Register"]
17 pub MCTRL2: crate::RWRegister<u16>,
18 #[doc = "Fault Control Register"]
19 pub FCTRL0: crate::RWRegister<u16>,
20 #[doc = "Fault Status Register"]
21 pub FSTS0: crate::RWRegister<u16>,
22 #[doc = "Fault Filter Register"]
23 pub FFILT0: crate::RWRegister<u16>,
24 #[doc = "Fault Test Register"]
25 pub FTST0: crate::RWRegister<u16>,
26 #[doc = "Fault Control 2 Register"]
27 pub FCTRL20: crate::RWRegister<u16>,
28}
29#[doc = "Output Enable Register"]
30pub mod OUTEN {
31 #[doc = "PWM_X Output Enables"]
32 pub mod PWMX_EN {
33 pub const offset: u16 = 0;
34 pub const mask: u16 = 0x0f << offset;
35 pub mod R {}
36 pub mod W {}
37 pub mod RW {
38 #[doc = "PWM_X output disabled."]
39 pub const PWMX_EN_0: u16 = 0;
40 #[doc = "PWM_X output enabled."]
41 pub const PWMX_EN_1: u16 = 0x01;
42 }
43 }
44 #[doc = "PWM_B Output Enables"]
45 pub mod PWMB_EN {
46 pub const offset: u16 = 4;
47 pub const mask: u16 = 0x0f << offset;
48 pub mod R {}
49 pub mod W {}
50 pub mod RW {
51 #[doc = "PWM_B output disabled."]
52 pub const PWMB_EN_0: u16 = 0;
53 #[doc = "PWM_B output enabled."]
54 pub const PWMB_EN_1: u16 = 0x01;
55 }
56 }
57 #[doc = "PWM_A Output Enables"]
58 pub mod PWMA_EN {
59 pub const offset: u16 = 8;
60 pub const mask: u16 = 0x0f << offset;
61 pub mod R {}
62 pub mod W {}
63 pub mod RW {
64 #[doc = "PWM_A output disabled."]
65 pub const PWMA_EN_0: u16 = 0;
66 #[doc = "PWM_A output enabled."]
67 pub const PWMA_EN_1: u16 = 0x01;
68 }
69 }
70}
71#[doc = "Mask Register"]
72pub mod MASK {
73 #[doc = "PWM_X Masks"]
74 pub mod MASKX {
75 pub const offset: u16 = 0;
76 pub const mask: u16 = 0x0f << offset;
77 pub mod R {}
78 pub mod W {}
79 pub mod RW {
80 #[doc = "PWM_X output normal."]
81 pub const MASKX_0: u16 = 0;
82 #[doc = "PWM_X output masked."]
83 pub const MASKX_1: u16 = 0x01;
84 }
85 }
86 #[doc = "PWM_B Masks"]
87 pub mod MASKB {
88 pub const offset: u16 = 4;
89 pub const mask: u16 = 0x0f << offset;
90 pub mod R {}
91 pub mod W {}
92 pub mod RW {
93 #[doc = "PWM_B output normal."]
94 pub const MASKB_0: u16 = 0;
95 #[doc = "PWM_B output masked."]
96 pub const MASKB_1: u16 = 0x01;
97 }
98 }
99 #[doc = "PWM_A Masks"]
100 pub mod MASKA {
101 pub const offset: u16 = 8;
102 pub const mask: u16 = 0x0f << offset;
103 pub mod R {}
104 pub mod W {}
105 pub mod RW {
106 #[doc = "PWM_A output normal."]
107 pub const MASKA_0: u16 = 0;
108 #[doc = "PWM_A output masked."]
109 pub const MASKA_1: u16 = 0x01;
110 }
111 }
112 #[doc = "Update Mask Bits Immediately"]
113 pub mod UPDATE_MASK {
114 pub const offset: u16 = 12;
115 pub const mask: u16 = 0x0f << offset;
116 pub mod R {}
117 pub mod W {}
118 pub mod RW {
119 #[doc = "Normal operation. MASK* bits within the corresponding submodule are not updated until a FORCE_OUT event occurs within the submodule."]
120 pub const UPDATE_MASK_0: u16 = 0;
121 #[doc = "Immediate operation. MASK* bits within the corresponding submodule are updated on the following clock edge after setting this bit."]
122 pub const UPDATE_MASK_1: u16 = 0x01;
123 }
124 }
125}
126#[doc = "Software Controlled Output Register"]
127pub mod SWCOUT {
128 #[doc = "Submodule 0 Software Controlled Output 45"]
129 pub mod SM0OUT45 {
130 pub const offset: u16 = 0;
131 pub const mask: u16 = 0x01 << offset;
132 pub mod R {}
133 pub mod W {}
134 pub mod RW {
135 #[doc = "A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45."]
136 pub const SM0OUT45_0: u16 = 0;
137 #[doc = "A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45."]
138 pub const SM0OUT45_1: u16 = 0x01;
139 }
140 }
141 #[doc = "Submodule 0 Software Controlled Output 23"]
142 pub mod SM0OUT23 {
143 pub const offset: u16 = 1;
144 pub const mask: u16 = 0x01 << offset;
145 pub mod R {}
146 pub mod W {}
147 pub mod RW {
148 #[doc = "A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23."]
149 pub const SM0OUT23_0: u16 = 0;
150 #[doc = "A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23."]
151 pub const SM0OUT23_1: u16 = 0x01;
152 }
153 }
154 #[doc = "Submodule 1 Software Controlled Output 45"]
155 pub mod SM1OUT45 {
156 pub const offset: u16 = 2;
157 pub const mask: u16 = 0x01 << offset;
158 pub mod R {}
159 pub mod W {}
160 pub mod RW {
161 #[doc = "A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45."]
162 pub const SM1OUT45_0: u16 = 0;
163 #[doc = "A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45."]
164 pub const SM1OUT45_1: u16 = 0x01;
165 }
166 }
167 #[doc = "Submodule 1 Software Controlled Output 23"]
168 pub mod SM1OUT23 {
169 pub const offset: u16 = 3;
170 pub const mask: u16 = 0x01 << offset;
171 pub mod R {}
172 pub mod W {}
173 pub mod RW {
174 #[doc = "A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23."]
175 pub const SM1OUT23_0: u16 = 0;
176 #[doc = "A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23."]
177 pub const SM1OUT23_1: u16 = 0x01;
178 }
179 }
180 #[doc = "Submodule 2 Software Controlled Output 45"]
181 pub mod SM2OUT45 {
182 pub const offset: u16 = 4;
183 pub const mask: u16 = 0x01 << offset;
184 pub mod R {}
185 pub mod W {}
186 pub mod RW {
187 #[doc = "A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45."]
188 pub const SM2OUT45_0: u16 = 0;
189 #[doc = "A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45."]
190 pub const SM2OUT45_1: u16 = 0x01;
191 }
192 }
193 #[doc = "Submodule 2 Software Controlled Output 23"]
194 pub mod SM2OUT23 {
195 pub const offset: u16 = 5;
196 pub const mask: u16 = 0x01 << offset;
197 pub mod R {}
198 pub mod W {}
199 pub mod RW {
200 #[doc = "A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23."]
201 pub const SM2OUT23_0: u16 = 0;
202 #[doc = "A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23."]
203 pub const SM2OUT23_1: u16 = 0x01;
204 }
205 }
206 #[doc = "Submodule 3 Software Controlled Output 45"]
207 pub mod SM3OUT45 {
208 pub const offset: u16 = 6;
209 pub const mask: u16 = 0x01 << offset;
210 pub mod R {}
211 pub mod W {}
212 pub mod RW {
213 #[doc = "A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45."]
214 pub const SM3OUT45_0: u16 = 0;
215 #[doc = "A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45."]
216 pub const SM3OUT45_1: u16 = 0x01;
217 }
218 }
219 #[doc = "Submodule 3 Software Controlled Output 23"]
220 pub mod SM3OUT23 {
221 pub const offset: u16 = 7;
222 pub const mask: u16 = 0x01 << offset;
223 pub mod R {}
224 pub mod W {}
225 pub mod RW {
226 #[doc = "A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23."]
227 pub const SM3OUT23_0: u16 = 0;
228 #[doc = "A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23."]
229 pub const SM3OUT23_1: u16 = 0x01;
230 }
231 }
232}
233#[doc = "PWM Source Select Register"]
234pub mod DTSRCSEL {
235 #[doc = "Submodule 0 PWM45 Control Select"]
236 pub mod SM0SEL45 {
237 pub const offset: u16 = 0;
238 pub const mask: u16 = 0x03 << offset;
239 pub mod R {}
240 pub mod W {}
241 pub mod RW {
242 #[doc = "Generated SM0PWM45 signal is used by the deadtime logic."]
243 pub const SM0SEL45_0: u16 = 0;
244 #[doc = "Inverted generated SM0PWM45 signal is used by the deadtime logic."]
245 pub const SM0SEL45_1: u16 = 0x01;
246 #[doc = "SWCOUT\\[SM0OUT45\\] is used by the deadtime logic."]
247 pub const SM0SEL45_2: u16 = 0x02;
248 #[doc = "PWM0_EXTB signal is used by the deadtime logic."]
249 pub const SM0SEL45_3: u16 = 0x03;
250 }
251 }
252 #[doc = "Submodule 0 PWM23 Control Select"]
253 pub mod SM0SEL23 {
254 pub const offset: u16 = 2;
255 pub const mask: u16 = 0x03 << offset;
256 pub mod R {}
257 pub mod W {}
258 pub mod RW {
259 #[doc = "Generated SM0PWM23 signal is used by the deadtime logic."]
260 pub const SM0SEL23_0: u16 = 0;
261 #[doc = "Inverted generated SM0PWM23 signal is used by the deadtime logic."]
262 pub const SM0SEL23_1: u16 = 0x01;
263 #[doc = "SWCOUT\\[SM0OUT23\\] is used by the deadtime logic."]
264 pub const SM0SEL23_2: u16 = 0x02;
265 #[doc = "PWM0_EXTA signal is used by the deadtime logic."]
266 pub const SM0SEL23_3: u16 = 0x03;
267 }
268 }
269 #[doc = "Submodule 1 PWM45 Control Select"]
270 pub mod SM1SEL45 {
271 pub const offset: u16 = 4;
272 pub const mask: u16 = 0x03 << offset;
273 pub mod R {}
274 pub mod W {}
275 pub mod RW {
276 #[doc = "Generated SM1PWM45 signal is used by the deadtime logic."]
277 pub const SM1SEL45_0: u16 = 0;
278 #[doc = "Inverted generated SM1PWM45 signal is used by the deadtime logic."]
279 pub const SM1SEL45_1: u16 = 0x01;
280 #[doc = "SWCOUT\\[SM1OUT45\\] is used by the deadtime logic."]
281 pub const SM1SEL45_2: u16 = 0x02;
282 #[doc = "PWM1_EXTB signal is used by the deadtime logic."]
283 pub const SM1SEL45_3: u16 = 0x03;
284 }
285 }
286 #[doc = "Submodule 1 PWM23 Control Select"]
287 pub mod SM1SEL23 {
288 pub const offset: u16 = 6;
289 pub const mask: u16 = 0x03 << offset;
290 pub mod R {}
291 pub mod W {}
292 pub mod RW {
293 #[doc = "Generated SM1PWM23 signal is used by the deadtime logic."]
294 pub const SM1SEL23_0: u16 = 0;
295 #[doc = "Inverted generated SM1PWM23 signal is used by the deadtime logic."]
296 pub const SM1SEL23_1: u16 = 0x01;
297 #[doc = "SWCOUT\\[SM1OUT23\\] is used by the deadtime logic."]
298 pub const SM1SEL23_2: u16 = 0x02;
299 #[doc = "PWM1_EXTA signal is used by the deadtime logic."]
300 pub const SM1SEL23_3: u16 = 0x03;
301 }
302 }
303 #[doc = "Submodule 2 PWM45 Control Select"]
304 pub mod SM2SEL45 {
305 pub const offset: u16 = 8;
306 pub const mask: u16 = 0x03 << offset;
307 pub mod R {}
308 pub mod W {}
309 pub mod RW {
310 #[doc = "Generated SM2PWM45 signal is used by the deadtime logic."]
311 pub const SM2SEL45_0: u16 = 0;
312 #[doc = "Inverted generated SM2PWM45 signal is used by the deadtime logic."]
313 pub const SM2SEL45_1: u16 = 0x01;
314 #[doc = "SWCOUT\\[SM2OUT45\\] is used by the deadtime logic."]
315 pub const SM2SEL45_2: u16 = 0x02;
316 #[doc = "PWM2_EXTB signal is used by the deadtime logic."]
317 pub const SM2SEL45_3: u16 = 0x03;
318 }
319 }
320 #[doc = "Submodule 2 PWM23 Control Select"]
321 pub mod SM2SEL23 {
322 pub const offset: u16 = 10;
323 pub const mask: u16 = 0x03 << offset;
324 pub mod R {}
325 pub mod W {}
326 pub mod RW {
327 #[doc = "Generated SM2PWM23 signal is used by the deadtime logic."]
328 pub const SM2SEL23_0: u16 = 0;
329 #[doc = "Inverted generated SM2PWM23 signal is used by the deadtime logic."]
330 pub const SM2SEL23_1: u16 = 0x01;
331 #[doc = "SWCOUT\\[SM2OUT23\\] is used by the deadtime logic."]
332 pub const SM2SEL23_2: u16 = 0x02;
333 #[doc = "PWM2_EXTA signal is used by the deadtime logic."]
334 pub const SM2SEL23_3: u16 = 0x03;
335 }
336 }
337 #[doc = "Submodule 3 PWM45 Control Select"]
338 pub mod SM3SEL45 {
339 pub const offset: u16 = 12;
340 pub const mask: u16 = 0x03 << offset;
341 pub mod R {}
342 pub mod W {}
343 pub mod RW {
344 #[doc = "Generated SM3PWM45 signal is used by the deadtime logic."]
345 pub const SM3SEL45_0: u16 = 0;
346 #[doc = "Inverted generated SM3PWM45 signal is used by the deadtime logic."]
347 pub const SM3SEL45_1: u16 = 0x01;
348 #[doc = "SWCOUT\\[SM3OUT45\\] is used by the deadtime logic."]
349 pub const SM3SEL45_2: u16 = 0x02;
350 #[doc = "PWM3_EXTB signal is used by the deadtime logic."]
351 pub const SM3SEL45_3: u16 = 0x03;
352 }
353 }
354 #[doc = "Submodule 3 PWM23 Control Select"]
355 pub mod SM3SEL23 {
356 pub const offset: u16 = 14;
357 pub const mask: u16 = 0x03 << offset;
358 pub mod R {}
359 pub mod W {}
360 pub mod RW {
361 #[doc = "Generated SM3PWM23 signal is used by the deadtime logic."]
362 pub const SM3SEL23_0: u16 = 0;
363 #[doc = "Inverted generated SM3PWM23 signal is used by the deadtime logic."]
364 pub const SM3SEL23_1: u16 = 0x01;
365 #[doc = "SWCOUT\\[SM3OUT23\\] is used by the deadtime logic."]
366 pub const SM3SEL23_2: u16 = 0x02;
367 #[doc = "PWM3_EXTA signal is used by the deadtime logic."]
368 pub const SM3SEL23_3: u16 = 0x03;
369 }
370 }
371}
372#[doc = "Master Control Register"]
373pub mod MCTRL {
374 #[doc = "Load Okay"]
375 pub mod LDOK {
376 pub const offset: u16 = 0;
377 pub const mask: u16 = 0x0f << offset;
378 pub mod R {}
379 pub mod W {}
380 pub mod RW {
381 #[doc = "Do not load new values."]
382 pub const LDOK_0: u16 = 0;
383 #[doc = "Load prescaler, modulus, and PWM values of the corresponding submodule."]
384 pub const LDOK_1: u16 = 0x01;
385 }
386 }
387 #[doc = "Clear Load Okay"]
388 pub mod CLDOK {
389 pub const offset: u16 = 4;
390 pub const mask: u16 = 0x0f << offset;
391 pub mod R {}
392 pub mod W {}
393 pub mod RW {}
394 }
395 #[doc = "Run"]
396 pub mod RUN {
397 pub const offset: u16 = 8;
398 pub const mask: u16 = 0x0f << offset;
399 pub mod R {}
400 pub mod W {}
401 pub mod RW {
402 #[doc = "PWM generator is disabled in the corresponding submodule."]
403 pub const RUN_0: u16 = 0;
404 #[doc = "PWM generator is enabled in the corresponding submodule."]
405 pub const RUN_1: u16 = 0x01;
406 }
407 }
408 #[doc = "Current Polarity"]
409 pub mod IPOL {
410 pub const offset: u16 = 12;
411 pub const mask: u16 = 0x0f << offset;
412 pub mod R {}
413 pub mod W {}
414 pub mod RW {
415 #[doc = "PWM23 is used to generate complementary PWM pair in the corresponding submodule."]
416 pub const IPOL_0: u16 = 0;
417 #[doc = "PWM45 is used to generate complementary PWM pair in the corresponding submodule."]
418 pub const IPOL_1: u16 = 0x01;
419 }
420 }
421}
422#[doc = "Master Control 2 Register"]
423pub mod MCTRL2 {
424 #[doc = "Monitor PLL State"]
425 pub mod MONPLL {
426 pub const offset: u16 = 0;
427 pub const mask: u16 = 0x03 << offset;
428 pub mod R {}
429 pub mod W {}
430 pub mod RW {
431 #[doc = "Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software."]
432 pub const MONPLL_0: u16 = 0;
433 #[doc = "Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems."]
434 pub const MONPLL_1: u16 = 0x01;
435 #[doc = "Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. These bits are write protected until the next reset."]
436 pub const MONPLL_2: u16 = 0x02;
437 #[doc = "Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. These bits are write protected until the next reset."]
438 pub const MONPLL_3: u16 = 0x03;
439 }
440 }
441}
442#[doc = "Fault Control Register"]
443pub mod FCTRL0 {
444 #[doc = "Fault Interrupt Enables"]
445 pub mod FIE {
446 pub const offset: u16 = 0;
447 pub const mask: u16 = 0x0f << offset;
448 pub mod R {}
449 pub mod W {}
450 pub mod RW {
451 #[doc = "FAULTx CPU interrupt requests disabled."]
452 pub const FIE_0: u16 = 0;
453 #[doc = "FAULTx CPU interrupt requests enabled."]
454 pub const FIE_1: u16 = 0x01;
455 }
456 }
457 #[doc = "Fault Safety Mode"]
458 pub mod FSAFE {
459 pub const offset: u16 = 4;
460 pub const mask: u16 = 0x0f << offset;
461 pub mod R {}
462 pub mod W {}
463 pub mod RW {
464 #[doc = "Normal mode. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\] without regard to the state of FSTS\\[FFPINx\\]. If neither FHALF nor FFULL is setm then the fault condition cannot be cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn)."]
465 pub const FSAFE_0: u16 = 0;
466 #[doc = "Safe mode. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear and FSTS\\[FFPINx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared."]
467 pub const FSAFE_1: u16 = 0x01;
468 }
469 }
470 #[doc = "Automatic Fault Clearing"]
471 pub mod FAUTO {
472 pub const offset: u16 = 8;
473 pub const mask: u16 = 0x0f << offset;
474 pub mod R {}
475 pub mod W {}
476 pub mod RW {
477 #[doc = "Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS\\[FFLAGx\\] is clear at the start of a half cycle or full cycle depending the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled by FCTRL\\[FSAFE\\]."]
478 pub const FAUTO_0: u16 = 0;
479 #[doc = "Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS\\[FFPINx\\] is clear at the start of a half cycle or full cycle depending on the states of FSTS\\[FHALF\\] and FSTS\\[FFULL\\] without regard to the state of FSTS\\[FFLAGx\\]. If neither FFULL nor FHALF is set, then the fault condition cannot be cleared."]
480 pub const FAUTO_1: u16 = 0x01;
481 }
482 }
483 #[doc = "Fault Level"]
484 pub mod FLVL {
485 pub const offset: u16 = 12;
486 pub const mask: u16 = 0x0f << offset;
487 pub mod R {}
488 pub mod W {}
489 pub mod RW {
490 #[doc = "A logic 0 on the fault input indicates a fault condition."]
491 pub const FLVL_0: u16 = 0;
492 #[doc = "A logic 1 on the fault input indicates a fault condition."]
493 pub const FLVL_1: u16 = 0x01;
494 }
495 }
496}
497#[doc = "Fault Status Register"]
498pub mod FSTS0 {
499 #[doc = "Fault Flags"]
500 pub mod FFLAG {
501 pub const offset: u16 = 0;
502 pub const mask: u16 = 0x0f << offset;
503 pub mod R {}
504 pub mod W {}
505 pub mod RW {
506 #[doc = "No fault on the FAULTx pin."]
507 pub const FFLAG_0: u16 = 0;
508 #[doc = "Fault on the FAULTx pin."]
509 pub const FFLAG_1: u16 = 0x01;
510 }
511 }
512 #[doc = "Full Cycle"]
513 pub mod FFULL {
514 pub const offset: u16 = 4;
515 pub const mask: u16 = 0x0f << offset;
516 pub mod R {}
517 pub mod W {}
518 pub mod RW {
519 #[doc = "PWM outputs are not re-enabled at the start of a full cycle"]
520 pub const FFULL_0: u16 = 0;
521 #[doc = "PWM outputs are re-enabled at the start of a full cycle"]
522 pub const FFULL_1: u16 = 0x01;
523 }
524 }
525 #[doc = "Filtered Fault Pins"]
526 pub mod FFPIN {
527 pub const offset: u16 = 8;
528 pub const mask: u16 = 0x0f << offset;
529 pub mod R {}
530 pub mod W {}
531 pub mod RW {}
532 }
533 #[doc = "Half Cycle Fault Recovery"]
534 pub mod FHALF {
535 pub const offset: u16 = 12;
536 pub const mask: u16 = 0x0f << offset;
537 pub mod R {}
538 pub mod W {}
539 pub mod RW {
540 #[doc = "PWM outputs are not re-enabled at the start of a half cycle."]
541 pub const FHALF_0: u16 = 0;
542 #[doc = "PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0)."]
543 pub const FHALF_1: u16 = 0x01;
544 }
545 }
546}
547#[doc = "Fault Filter Register"]
548pub mod FFILT0 {
549 #[doc = "Fault Filter Period"]
550 pub mod FILT_PER {
551 pub const offset: u16 = 0;
552 pub const mask: u16 = 0xff << offset;
553 pub mod R {}
554 pub mod W {}
555 pub mod RW {}
556 }
557 #[doc = "Fault Filter Count"]
558 pub mod FILT_CNT {
559 pub const offset: u16 = 8;
560 pub const mask: u16 = 0x07 << offset;
561 pub mod R {}
562 pub mod W {}
563 pub mod RW {}
564 }
565 #[doc = "Fault Glitch Stretch Enable"]
566 pub mod GSTR {
567 pub const offset: u16 = 15;
568 pub const mask: u16 = 0x01 << offset;
569 pub mod R {}
570 pub mod W {}
571 pub mod RW {
572 #[doc = "Fault input glitch stretching is disabled."]
573 pub const GSTR_0: u16 = 0;
574 #[doc = "Input fault signals will be stretched to at least 2 IPBus clock cycles."]
575 pub const GSTR_1: u16 = 0x01;
576 }
577 }
578}
579#[doc = "Fault Test Register"]
580pub mod FTST0 {
581 #[doc = "Fault Test"]
582 pub mod FTEST {
583 pub const offset: u16 = 0;
584 pub const mask: u16 = 0x01 << offset;
585 pub mod R {}
586 pub mod W {}
587 pub mod RW {
588 #[doc = "No fault"]
589 pub const FTEST_0: u16 = 0;
590 #[doc = "Cause a simulated fault"]
591 pub const FTEST_1: u16 = 0x01;
592 }
593 }
594}
595#[doc = "Fault Control 2 Register"]
596pub mod FCTRL20 {
597 #[doc = "No Combinational Path From Fault Input To PWM Output"]
598 pub mod NOCOMB {
599 pub const offset: u16 = 0;
600 pub const mask: u16 = 0x0f << offset;
601 pub mod R {}
602 pub mod W {}
603 pub mod RW {
604 #[doc = "There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined with the filtered and latched fault signals to disable the PWM outputs."]
605 pub const NOCOMB_0: u16 = 0;
606 #[doc = "The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered and latched fault signals are used to disable the PWM outputs."]
607 pub const NOCOMB_1: u16 = 0x01;
608 }
609 }
610}
611pub mod sm {
612 #[doc = "Cluster SM%s, containing SM?CNT, SM?INIT, SM?CTRL2, SM?CTRL, SM?VAL0, SM?FRACVAL1, SM?VAL1, SM?FRACVAL2, SM?VAL2, SM?FRACVAL3, SM?VAL3, SM?FRACVAL4, SM?VAL4, SM?FRACVAL5, SM?VAL5, SM?FRCTRL, SM?OCTRL, SM?STS, SM?INTEN, SM?DMAEN, SM?TCTRL, SM?DISMAP0, SM?DISMAP1, SM?DTCNT0, SM?DTCNT1, SM?CAPTCTRLA, SM?CAPTCOMPA, SM?CAPTCTRLB, SM?CAPTCOMPB, SM?CAPTCTRLX, SM?CAPTCOMPX, SM?CVAL0, SM?CVAL0CYC, SM?CVAL1, SM?CVAL1CYC, SM?CVAL2, SM?CVAL2CYC, SM?CVAL3, SM?CVAL3CYC, SM?CVAL4, SM?CVAL4CYC, SM?CVAL5, SM?CVAL5CYC"]
613 #[repr(C)]
614 pub struct RegisterBlock {
615 #[doc = "Counter Register"]
616 pub SMCNT: crate::RORegister<u16>,
617 #[doc = "Initial Count Register"]
618 pub SMINIT: crate::RWRegister<u16>,
619 #[doc = "Control 2 Register"]
620 pub SMCTRL2: crate::RWRegister<u16>,
621 #[doc = "Control Register"]
622 pub SMCTRL: crate::RWRegister<u16>,
623 _reserved0: [u8; 0x02],
624 #[doc = "Value Register 0"]
625 pub SMVAL0: crate::RWRegister<u16>,
626 #[doc = "Fractional Value Register 1"]
627 pub SMFRACVAL1: crate::RWRegister<u16>,
628 #[doc = "Value Register 1"]
629 pub SMVAL1: crate::RWRegister<u16>,
630 #[doc = "Fractional Value Register 2"]
631 pub SMFRACVAL2: crate::RWRegister<u16>,
632 #[doc = "Value Register 2"]
633 pub SMVAL2: crate::RWRegister<u16>,
634 #[doc = "Fractional Value Register 3"]
635 pub SMFRACVAL3: crate::RWRegister<u16>,
636 #[doc = "Value Register 3"]
637 pub SMVAL3: crate::RWRegister<u16>,
638 #[doc = "Fractional Value Register 4"]
639 pub SMFRACVAL4: crate::RWRegister<u16>,
640 #[doc = "Value Register 4"]
641 pub SMVAL4: crate::RWRegister<u16>,
642 #[doc = "Fractional Value Register 5"]
643 pub SMFRACVAL5: crate::RWRegister<u16>,
644 #[doc = "Value Register 5"]
645 pub SMVAL5: crate::RWRegister<u16>,
646 #[doc = "Fractional Control Register"]
647 pub SMFRCTRL: crate::RWRegister<u16>,
648 #[doc = "Output Control Register"]
649 pub SMOCTRL: crate::RWRegister<u16>,
650 #[doc = "Status Register"]
651 pub SMSTS: crate::RWRegister<u16>,
652 #[doc = "Interrupt Enable Register"]
653 pub SMINTEN: crate::RWRegister<u16>,
654 #[doc = "DMA Enable Register"]
655 pub SMDMAEN: crate::RWRegister<u16>,
656 #[doc = "Output Trigger Control Register"]
657 pub SMTCTRL: crate::RWRegister<u16>,
658 #[doc = "Fault Disable Mapping Register 0"]
659 pub SMDISMAP0: crate::RWRegister<u16>,
660 #[doc = "Fault Disable Mapping Register 1"]
661 pub SMDISMAP1: crate::RWRegister<u16>,
662 #[doc = "Deadtime Count Register 0"]
663 pub SMDTCNT0: crate::RWRegister<u16>,
664 #[doc = "Deadtime Count Register 1"]
665 pub SMDTCNT1: crate::RWRegister<u16>,
666 #[doc = "Capture Control A Register"]
667 pub SMCAPTCTRLA: crate::RWRegister<u16>,
668 #[doc = "Capture Compare A Register"]
669 pub SMCAPTCOMPA: crate::RWRegister<u16>,
670 #[doc = "Capture Control B Register"]
671 pub SMCAPTCTRLB: crate::RWRegister<u16>,
672 #[doc = "Capture Compare B Register"]
673 pub SMCAPTCOMPB: crate::RWRegister<u16>,
674 #[doc = "Capture Control X Register"]
675 pub SMCAPTCTRLX: crate::RWRegister<u16>,
676 #[doc = "Capture Compare X Register"]
677 pub SMCAPTCOMPX: crate::RWRegister<u16>,
678 #[doc = "Capture Value 0 Register"]
679 pub SMCVAL0: crate::RORegister<u16>,
680 #[doc = "Capture Value 0 Cycle Register"]
681 pub SMCVAL0CYC: crate::RORegister<u16>,
682 #[doc = "Capture Value 1 Register"]
683 pub SMCVAL1: crate::RORegister<u16>,
684 #[doc = "Capture Value 1 Cycle Register"]
685 pub SMCVAL1CYC: crate::RORegister<u16>,
686 #[doc = "Capture Value 2 Register"]
687 pub SMCVAL2: crate::RORegister<u16>,
688 #[doc = "Capture Value 2 Cycle Register"]
689 pub SMCVAL2CYC: crate::RORegister<u16>,
690 #[doc = "Capture Value 3 Register"]
691 pub SMCVAL3: crate::RORegister<u16>,
692 #[doc = "Capture Value 3 Cycle Register"]
693 pub SMCVAL3CYC: crate::RORegister<u16>,
694 #[doc = "Capture Value 4 Register"]
695 pub SMCVAL4: crate::RORegister<u16>,
696 #[doc = "Capture Value 4 Cycle Register"]
697 pub SMCVAL4CYC: crate::RORegister<u16>,
698 #[doc = "Capture Value 5 Register"]
699 pub SMCVAL5: crate::RORegister<u16>,
700 #[doc = "Capture Value 5 Cycle Register"]
701 pub SMCVAL5CYC: crate::RORegister<u16>,
702 _reserved1: [u8; 0x08],
703 }
704 #[doc = "Counter Register"]
705 pub mod SMCNT {
706 #[doc = "Counter Register Bits"]
707 pub mod CNT {
708 pub const offset: u16 = 0;
709 pub const mask: u16 = 0xffff << offset;
710 pub mod R {}
711 pub mod W {}
712 pub mod RW {}
713 }
714 }
715 #[doc = "Initial Count Register"]
716 pub mod SMINIT {
717 #[doc = "Initial Count Register Bits"]
718 pub mod INIT {
719 pub const offset: u16 = 0;
720 pub const mask: u16 = 0xffff << offset;
721 pub mod R {}
722 pub mod W {}
723 pub mod RW {}
724 }
725 }
726 #[doc = "Control 2 Register"]
727 pub mod SMCTRL2 {
728 #[doc = "Clock Source Select"]
729 pub mod CLK_SEL {
730 pub const offset: u16 = 0;
731 pub const mask: u16 = 0x03 << offset;
732 pub mod R {}
733 pub mod W {}
734 pub mod RW {
735 #[doc = "The IPBus clock is used as the clock for the local prescaler and counter."]
736 pub const CLK_SEL_0: u16 = 0;
737 #[doc = "EXT_CLK is used as the clock for the local prescaler and counter."]
738 pub const CLK_SEL_1: u16 = 0x01;
739 #[doc = "Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0."]
740 pub const CLK_SEL_2: u16 = 0x02;
741 }
742 }
743 #[doc = "Reload Source Select"]
744 pub mod RELOAD_SEL {
745 pub const offset: u16 = 2;
746 pub const mask: u16 = 0x01 << offset;
747 pub mod R {}
748 pub mod W {}
749 pub mod RW {
750 #[doc = "The local RELOAD signal is used to reload registers."]
751 pub const RELOAD_SEL_0: u16 = 0;
752 #[doc = "The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0."]
753 pub const RELOAD_SEL_1: u16 = 0x01;
754 }
755 }
756 #[doc = "This read/write bit determines the source of the FORCE OUTPUT signal for this submodule."]
757 pub mod FORCE_SEL {
758 pub const offset: u16 = 3;
759 pub const mask: u16 = 0x07 << offset;
760 pub mod R {}
761 pub mod W {}
762 pub mod RW {
763 #[doc = "The local force signal, CTRL2\\[FORCE\\], from this submodule is used to force updates."]
764 pub const FORCE_SEL_0: u16 = 0;
765 #[doc = "The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0."]
766 pub const FORCE_SEL_1: u16 = 0x01;
767 #[doc = "The local reload signal from this submodule is used to force updates without regard to the state of LDOK."]
768 pub const FORCE_SEL_2: u16 = 0x02;
769 #[doc = "The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0."]
770 pub const FORCE_SEL_3: u16 = 0x03;
771 #[doc = "The local sync signal from this submodule is used to force updates."]
772 pub const FORCE_SEL_4: u16 = 0x04;
773 #[doc = "The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0."]
774 pub const FORCE_SEL_5: u16 = 0x05;
775 #[doc = "The external force signal, EXT_FORCE, from outside the PWM module causes updates."]
776 pub const FORCE_SEL_6: u16 = 0x06;
777 #[doc = "The external sync signal, EXT_SYNC, from outside the PWM module causes updates."]
778 pub const FORCE_SEL_7: u16 = 0x07;
779 }
780 }
781 #[doc = "Force Initialization"]
782 pub mod FORCE {
783 pub const offset: u16 = 6;
784 pub const mask: u16 = 0x01 << offset;
785 pub mod R {}
786 pub mod W {}
787 pub mod RW {}
788 }
789 #[doc = "FRCEN"]
790 pub mod FRCEN {
791 pub const offset: u16 = 7;
792 pub const mask: u16 = 0x01 << offset;
793 pub mod R {}
794 pub mod W {}
795 pub mod RW {
796 #[doc = "Initialization from a FORCE_OUT is disabled."]
797 pub const FRCEN_0: u16 = 0;
798 #[doc = "Initialization from a FORCE_OUT is enabled."]
799 pub const FRCEN_1: u16 = 0x01;
800 }
801 }
802 #[doc = "Initialization Control Select"]
803 pub mod INIT_SEL {
804 pub const offset: u16 = 8;
805 pub const mask: u16 = 0x03 << offset;
806 pub mod R {}
807 pub mod W {}
808 pub mod RW {
809 #[doc = "Local sync (PWM_X) causes initialization."]
810 pub const INIT_SEL_0: u16 = 0;
811 #[doc = "Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs."]
812 pub const INIT_SEL_1: u16 = 0x01;
813 #[doc = "Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0."]
814 pub const INIT_SEL_2: u16 = 0x02;
815 #[doc = "EXT_SYNC causes initialization."]
816 pub const INIT_SEL_3: u16 = 0x03;
817 }
818 }
819 #[doc = "PWM_X Initial Value"]
820 pub mod PWMX_INIT {
821 pub const offset: u16 = 10;
822 pub const mask: u16 = 0x01 << offset;
823 pub mod R {}
824 pub mod W {}
825 pub mod RW {}
826 }
827 #[doc = "PWM45 Initial Value"]
828 pub mod PWM45_INIT {
829 pub const offset: u16 = 11;
830 pub const mask: u16 = 0x01 << offset;
831 pub mod R {}
832 pub mod W {}
833 pub mod RW {}
834 }
835 #[doc = "PWM23 Initial Value"]
836 pub mod PWM23_INIT {
837 pub const offset: u16 = 12;
838 pub const mask: u16 = 0x01 << offset;
839 pub mod R {}
840 pub mod W {}
841 pub mod RW {}
842 }
843 #[doc = "Independent or Complementary Pair Operation"]
844 pub mod INDEP {
845 pub const offset: u16 = 13;
846 pub const mask: u16 = 0x01 << offset;
847 pub mod R {}
848 pub mod W {}
849 pub mod RW {
850 #[doc = "PWM_A and PWM_B form a complementary PWM pair."]
851 pub const INDEP_0: u16 = 0;
852 #[doc = "PWM_A and PWM_B outputs are independent PWMs."]
853 pub const INDEP_1: u16 = 0x01;
854 }
855 }
856 #[doc = "WAIT Enable"]
857 pub mod WAITEN {
858 pub const offset: u16 = 14;
859 pub const mask: u16 = 0x01 << offset;
860 pub mod R {}
861 pub mod W {}
862 pub mod RW {}
863 }
864 #[doc = "Debug Enable"]
865 pub mod DBGEN {
866 pub const offset: u16 = 15;
867 pub const mask: u16 = 0x01 << offset;
868 pub mod R {}
869 pub mod W {}
870 pub mod RW {}
871 }
872 }
873 #[doc = "Control Register"]
874 pub mod SMCTRL {
875 #[doc = "Double Switching Enable"]
876 pub mod DBLEN {
877 pub const offset: u16 = 0;
878 pub const mask: u16 = 0x01 << offset;
879 pub mod R {}
880 pub mod W {}
881 pub mod RW {
882 #[doc = "Double switching disabled."]
883 pub const DBLEN_0: u16 = 0;
884 #[doc = "Double switching enabled."]
885 pub const DBLEN_1: u16 = 0x01;
886 }
887 }
888 #[doc = "PWMX Double Switching Enable"]
889 pub mod DBLX {
890 pub const offset: u16 = 1;
891 pub const mask: u16 = 0x01 << offset;
892 pub mod R {}
893 pub mod W {}
894 pub mod RW {
895 #[doc = "PWMX double pulse disabled."]
896 pub const DBLX_0: u16 = 0;
897 #[doc = "PWMX double pulse enabled."]
898 pub const DBLX_1: u16 = 0x01;
899 }
900 }
901 #[doc = "Load Mode Select"]
902 pub mod LDMOD {
903 pub const offset: u16 = 2;
904 pub const mask: u16 = 0x01 << offset;
905 pub mod R {}
906 pub mod W {}
907 pub mod RW {
908 #[doc = "Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL\\[LDOK\\] is set."]
909 pub const LDMOD_0: u16 = 0;
910 #[doc = "Buffered registers of this submodule are loaded and take effect immediately upon MCTRL\\[LDOK\\] being set. In this case it is not necessary to set CTRL\\[FULL\\] or CTRL\\[HALF\\]."]
911 pub const LDMOD_1: u16 = 0x01;
912 }
913 }
914 #[doc = "Split the DBLPWM signal to PWMA and PWMB"]
915 pub mod SPLIT {
916 pub const offset: u16 = 3;
917 pub const mask: u16 = 0x01 << offset;
918 pub mod R {}
919 pub mod W {}
920 pub mod RW {
921 #[doc = "DBLPWM is not split. PWMA and PWMB each have double pulses."]
922 pub const SPLIT_0: u16 = 0;
923 #[doc = "DBLPWM is split to PWMA and PWMB."]
924 pub const SPLIT_1: u16 = 0x01;
925 }
926 }
927 #[doc = "Prescaler"]
928 pub mod PRSC {
929 pub const offset: u16 = 4;
930 pub const mask: u16 = 0x07 << offset;
931 pub mod R {}
932 pub mod W {}
933 pub mod RW {
934 #[doc = "PWM clock frequency = fclk"]
935 pub const PRSC_0: u16 = 0;
936 #[doc = "PWM clock frequency = fclk/2"]
937 pub const PRSC_1: u16 = 0x01;
938 #[doc = "PWM clock frequency = fclk/4"]
939 pub const PRSC_2: u16 = 0x02;
940 #[doc = "PWM clock frequency = fclk/8"]
941 pub const PRSC_3: u16 = 0x03;
942 #[doc = "PWM clock frequency = fclk/16"]
943 pub const PRSC_4: u16 = 0x04;
944 #[doc = "PWM clock frequency = fclk/32"]
945 pub const PRSC_5: u16 = 0x05;
946 #[doc = "PWM clock frequency = fclk/64"]
947 pub const PRSC_6: u16 = 0x06;
948 #[doc = "PWM clock frequency = fclk/128"]
949 pub const PRSC_7: u16 = 0x07;
950 }
951 }
952 #[doc = "Compare Mode"]
953 pub mod COMPMODE {
954 pub const offset: u16 = 7;
955 pub const mask: u16 = 0x01 << offset;
956 pub mod R {}
957 pub mod W {}
958 pub mod RW {
959 #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to\" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period."]
960 pub const COMPMODE_0: u16 = 0;
961 #[doc = "The VAL* registers and the PWM counter are compared using an \"equal to or greater than\" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value."]
962 pub const COMPMODE_1: u16 = 0x01;
963 }
964 }
965 #[doc = "Deadtime"]
966 pub mod DT {
967 pub const offset: u16 = 8;
968 pub const mask: u16 = 0x03 << offset;
969 pub mod R {}
970 pub mod W {}
971 pub mod RW {}
972 }
973 #[doc = "Full Cycle Reload"]
974 pub mod FULL {
975 pub const offset: u16 = 10;
976 pub const mask: u16 = 0x01 << offset;
977 pub mod R {}
978 pub mod W {}
979 pub mod RW {
980 #[doc = "Full-cycle reloads disabled."]
981 pub const FULL_0: u16 = 0;
982 #[doc = "Full-cycle reloads enabled."]
983 pub const FULL_1: u16 = 0x01;
984 }
985 }
986 #[doc = "Half Cycle Reload"]
987 pub mod HALF {
988 pub const offset: u16 = 11;
989 pub const mask: u16 = 0x01 << offset;
990 pub mod R {}
991 pub mod W {}
992 pub mod RW {
993 #[doc = "Half-cycle reloads disabled."]
994 pub const HALF_0: u16 = 0;
995 #[doc = "Half-cycle reloads enabled."]
996 pub const HALF_1: u16 = 0x01;
997 }
998 }
999 #[doc = "Load Frequency"]
1000 pub mod LDFQ {
1001 pub const offset: u16 = 12;
1002 pub const mask: u16 = 0x0f << offset;
1003 pub mod R {}
1004 pub mod W {}
1005 pub mod RW {
1006 #[doc = "Every PWM opportunity"]
1007 pub const LDFQ_0: u16 = 0;
1008 #[doc = "Every 2 PWM opportunities"]
1009 pub const LDFQ_1: u16 = 0x01;
1010 #[doc = "Every 3 PWM opportunities"]
1011 pub const LDFQ_2: u16 = 0x02;
1012 #[doc = "Every 4 PWM opportunities"]
1013 pub const LDFQ_3: u16 = 0x03;
1014 #[doc = "Every 5 PWM opportunities"]
1015 pub const LDFQ_4: u16 = 0x04;
1016 #[doc = "Every 6 PWM opportunities"]
1017 pub const LDFQ_5: u16 = 0x05;
1018 #[doc = "Every 7 PWM opportunities"]
1019 pub const LDFQ_6: u16 = 0x06;
1020 #[doc = "Every 8 PWM opportunities"]
1021 pub const LDFQ_7: u16 = 0x07;
1022 #[doc = "Every 9 PWM opportunities"]
1023 pub const LDFQ_8: u16 = 0x08;
1024 #[doc = "Every 10 PWM opportunities"]
1025 pub const LDFQ_9: u16 = 0x09;
1026 #[doc = "Every 11 PWM opportunities"]
1027 pub const LDFQ_10: u16 = 0x0a;
1028 #[doc = "Every 12 PWM opportunities"]
1029 pub const LDFQ_11: u16 = 0x0b;
1030 #[doc = "Every 13 PWM opportunities"]
1031 pub const LDFQ_12: u16 = 0x0c;
1032 #[doc = "Every 14 PWM opportunities"]
1033 pub const LDFQ_13: u16 = 0x0d;
1034 #[doc = "Every 15 PWM opportunities"]
1035 pub const LDFQ_14: u16 = 0x0e;
1036 #[doc = "Every 16 PWM opportunities"]
1037 pub const LDFQ_15: u16 = 0x0f;
1038 }
1039 }
1040 }
1041 #[doc = "Value Register 0"]
1042 pub mod SMVAL0 {
1043 #[doc = "Value Register 0"]
1044 pub mod VAL0 {
1045 pub const offset: u16 = 0;
1046 pub const mask: u16 = 0xffff << offset;
1047 pub mod R {}
1048 pub mod W {}
1049 pub mod RW {}
1050 }
1051 }
1052 #[doc = "Fractional Value Register 1"]
1053 pub mod SMFRACVAL1 {
1054 #[doc = "Fractional Value 1 Register"]
1055 pub mod FRACVAL1 {
1056 pub const offset: u16 = 11;
1057 pub const mask: u16 = 0x1f << offset;
1058 pub mod R {}
1059 pub mod W {}
1060 pub mod RW {}
1061 }
1062 }
1063 #[doc = "Value Register 1"]
1064 pub mod SMVAL1 {
1065 #[doc = "Value Register 1"]
1066 pub mod VAL1 {
1067 pub const offset: u16 = 0;
1068 pub const mask: u16 = 0xffff << offset;
1069 pub mod R {}
1070 pub mod W {}
1071 pub mod RW {}
1072 }
1073 }
1074 #[doc = "Fractional Value Register 2"]
1075 pub mod SMFRACVAL2 {
1076 #[doc = "Fractional Value 2"]
1077 pub mod FRACVAL2 {
1078 pub const offset: u16 = 11;
1079 pub const mask: u16 = 0x1f << offset;
1080 pub mod R {}
1081 pub mod W {}
1082 pub mod RW {}
1083 }
1084 }
1085 #[doc = "Value Register 2"]
1086 pub mod SMVAL2 {
1087 #[doc = "Value Register 2"]
1088 pub mod VAL2 {
1089 pub const offset: u16 = 0;
1090 pub const mask: u16 = 0xffff << offset;
1091 pub mod R {}
1092 pub mod W {}
1093 pub mod RW {}
1094 }
1095 }
1096 #[doc = "Fractional Value Register 3"]
1097 pub mod SMFRACVAL3 {
1098 #[doc = "Fractional Value 3"]
1099 pub mod FRACVAL3 {
1100 pub const offset: u16 = 11;
1101 pub const mask: u16 = 0x1f << offset;
1102 pub mod R {}
1103 pub mod W {}
1104 pub mod RW {}
1105 }
1106 }
1107 #[doc = "Value Register 3"]
1108 pub mod SMVAL3 {
1109 #[doc = "Value Register 3"]
1110 pub mod VAL3 {
1111 pub const offset: u16 = 0;
1112 pub const mask: u16 = 0xffff << offset;
1113 pub mod R {}
1114 pub mod W {}
1115 pub mod RW {}
1116 }
1117 }
1118 #[doc = "Fractional Value Register 4"]
1119 pub mod SMFRACVAL4 {
1120 #[doc = "Fractional Value 4"]
1121 pub mod FRACVAL4 {
1122 pub const offset: u16 = 11;
1123 pub const mask: u16 = 0x1f << offset;
1124 pub mod R {}
1125 pub mod W {}
1126 pub mod RW {}
1127 }
1128 }
1129 #[doc = "Value Register 4"]
1130 pub mod SMVAL4 {
1131 #[doc = "Value Register 4"]
1132 pub mod VAL4 {
1133 pub const offset: u16 = 0;
1134 pub const mask: u16 = 0xffff << offset;
1135 pub mod R {}
1136 pub mod W {}
1137 pub mod RW {}
1138 }
1139 }
1140 #[doc = "Fractional Value Register 5"]
1141 pub mod SMFRACVAL5 {
1142 #[doc = "Fractional Value 5"]
1143 pub mod FRACVAL5 {
1144 pub const offset: u16 = 11;
1145 pub const mask: u16 = 0x1f << offset;
1146 pub mod R {}
1147 pub mod W {}
1148 pub mod RW {}
1149 }
1150 }
1151 #[doc = "Value Register 5"]
1152 pub mod SMVAL5 {
1153 #[doc = "Value Register 5"]
1154 pub mod VAL5 {
1155 pub const offset: u16 = 0;
1156 pub const mask: u16 = 0xffff << offset;
1157 pub mod R {}
1158 pub mod W {}
1159 pub mod RW {}
1160 }
1161 }
1162 #[doc = "Fractional Control Register"]
1163 pub mod SMFRCTRL {
1164 #[doc = "Fractional Cycle PWM Period Enable"]
1165 pub mod FRAC1_EN {
1166 pub const offset: u16 = 1;
1167 pub const mask: u16 = 0x01 << offset;
1168 pub mod R {}
1169 pub mod W {}
1170 pub mod RW {
1171 #[doc = "Disable fractional cycle length for the PWM period."]
1172 pub const FRAC1_EN_0: u16 = 0;
1173 #[doc = "Enable fractional cycle length for the PWM period."]
1174 pub const FRAC1_EN_1: u16 = 0x01;
1175 }
1176 }
1177 #[doc = "Fractional Cycle Placement Enable for PWM_A"]
1178 pub mod FRAC23_EN {
1179 pub const offset: u16 = 2;
1180 pub const mask: u16 = 0x01 << offset;
1181 pub mod R {}
1182 pub mod W {}
1183 pub mod RW {
1184 #[doc = "Disable fractional cycle placement for PWM_A."]
1185 pub const FRAC23_EN_0: u16 = 0;
1186 #[doc = "Enable fractional cycle placement for PWM_A."]
1187 pub const FRAC23_EN_1: u16 = 0x01;
1188 }
1189 }
1190 #[doc = "Fractional Cycle Placement Enable for PWM_B"]
1191 pub mod FRAC45_EN {
1192 pub const offset: u16 = 4;
1193 pub const mask: u16 = 0x01 << offset;
1194 pub mod R {}
1195 pub mod W {}
1196 pub mod RW {
1197 #[doc = "Disable fractional cycle placement for PWM_B."]
1198 pub const FRAC45_EN_0: u16 = 0;
1199 #[doc = "Enable fractional cycle placement for PWM_B."]
1200 pub const FRAC45_EN_1: u16 = 0x01;
1201 }
1202 }
1203 #[doc = "Fractional Delay Circuit Power Up"]
1204 pub mod FRAC_PU {
1205 pub const offset: u16 = 8;
1206 pub const mask: u16 = 0x01 << offset;
1207 pub mod R {}
1208 pub mod W {}
1209 pub mod RW {
1210 #[doc = "Turn off fractional delay logic."]
1211 pub const FRAC_PU_0: u16 = 0;
1212 #[doc = "Power up fractional delay logic."]
1213 pub const FRAC_PU_1: u16 = 0x01;
1214 }
1215 }
1216 #[doc = "Test Status Bit"]
1217 pub mod TEST {
1218 pub const offset: u16 = 15;
1219 pub const mask: u16 = 0x01 << offset;
1220 pub mod R {}
1221 pub mod W {}
1222 pub mod RW {}
1223 }
1224 }
1225 #[doc = "Output Control Register"]
1226 pub mod SMOCTRL {
1227 #[doc = "PWM_X Fault State"]
1228 pub mod PWMXFS {
1229 pub const offset: u16 = 0;
1230 pub const mask: u16 = 0x03 << offset;
1231 pub mod R {}
1232 pub mod W {}
1233 pub mod RW {
1234 #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."]
1235 pub const PWMXFS_0: u16 = 0;
1236 #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."]
1237 pub const PWMXFS_1: u16 = 0x01;
1238 #[doc = "Output is tristated."]
1239 pub const PWMXFS_2: u16 = 0x02;
1240 #[doc = "Output is tristated."]
1241 pub const PWMXFS_3: u16 = 0x03;
1242 }
1243 }
1244 #[doc = "PWM_B Fault State"]
1245 pub mod PWMBFS {
1246 pub const offset: u16 = 2;
1247 pub const mask: u16 = 0x03 << offset;
1248 pub mod R {}
1249 pub mod W {}
1250 pub mod RW {
1251 #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."]
1252 pub const PWMBFS_0: u16 = 0;
1253 #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."]
1254 pub const PWMBFS_1: u16 = 0x01;
1255 #[doc = "Output is tristated."]
1256 pub const PWMBFS_2: u16 = 0x02;
1257 #[doc = "Output is tristated."]
1258 pub const PWMBFS_3: u16 = 0x03;
1259 }
1260 }
1261 #[doc = "PWM_A Fault State"]
1262 pub mod PWMAFS {
1263 pub const offset: u16 = 4;
1264 pub const mask: u16 = 0x03 << offset;
1265 pub mod R {}
1266 pub mod W {}
1267 pub mod RW {
1268 #[doc = "Output is forced to logic 0 state prior to consideration of output polarity control."]
1269 pub const PWMAFS_0: u16 = 0;
1270 #[doc = "Output is forced to logic 1 state prior to consideration of output polarity control."]
1271 pub const PWMAFS_1: u16 = 0x01;
1272 #[doc = "Output is tristated."]
1273 pub const PWMAFS_2: u16 = 0x02;
1274 #[doc = "Output is tristated."]
1275 pub const PWMAFS_3: u16 = 0x03;
1276 }
1277 }
1278 #[doc = "PWM_X Output Polarity"]
1279 pub mod POLX {
1280 pub const offset: u16 = 8;
1281 pub const mask: u16 = 0x01 << offset;
1282 pub mod R {}
1283 pub mod W {}
1284 pub mod RW {
1285 #[doc = "PWM_X output not inverted. A high level on the PWM_X pin represents the \"on\" or \"active\" state."]
1286 pub const POLX_0: u16 = 0;
1287 #[doc = "PWM_X output inverted. A low level on the PWM_X pin represents the \"on\" or \"active\" state."]
1288 pub const POLX_1: u16 = 0x01;
1289 }
1290 }
1291 #[doc = "PWM_B Output Polarity"]
1292 pub mod POLB {
1293 pub const offset: u16 = 9;
1294 pub const mask: u16 = 0x01 << offset;
1295 pub mod R {}
1296 pub mod W {}
1297 pub mod RW {
1298 #[doc = "PWM_B output not inverted. A high level on the PWM_B pin represents the \"on\" or \"active\" state."]
1299 pub const POLB_0: u16 = 0;
1300 #[doc = "PWM_B output inverted. A low level on the PWM_B pin represents the \"on\" or \"active\" state."]
1301 pub const POLB_1: u16 = 0x01;
1302 }
1303 }
1304 #[doc = "PWM_A Output Polarity"]
1305 pub mod POLA {
1306 pub const offset: u16 = 10;
1307 pub const mask: u16 = 0x01 << offset;
1308 pub mod R {}
1309 pub mod W {}
1310 pub mod RW {
1311 #[doc = "PWM_A output not inverted. A high level on the PWM_A pin represents the \"on\" or \"active\" state."]
1312 pub const POLA_0: u16 = 0;
1313 #[doc = "PWM_A output inverted. A low level on the PWM_A pin represents the \"on\" or \"active\" state."]
1314 pub const POLA_1: u16 = 0x01;
1315 }
1316 }
1317 #[doc = "PWM_X Input"]
1318 pub mod PWMX_IN {
1319 pub const offset: u16 = 13;
1320 pub const mask: u16 = 0x01 << offset;
1321 pub mod R {}
1322 pub mod W {}
1323 pub mod RW {}
1324 }
1325 #[doc = "PWM_B Input"]
1326 pub mod PWMB_IN {
1327 pub const offset: u16 = 14;
1328 pub const mask: u16 = 0x01 << offset;
1329 pub mod R {}
1330 pub mod W {}
1331 pub mod RW {}
1332 }
1333 #[doc = "PWM_A Input"]
1334 pub mod PWMA_IN {
1335 pub const offset: u16 = 15;
1336 pub const mask: u16 = 0x01 << offset;
1337 pub mod R {}
1338 pub mod W {}
1339 pub mod RW {}
1340 }
1341 }
1342 #[doc = "Status Register"]
1343 pub mod SMSTS {
1344 #[doc = "Compare Flags"]
1345 pub mod CMPF {
1346 pub const offset: u16 = 0;
1347 pub const mask: u16 = 0x3f << offset;
1348 pub mod R {}
1349 pub mod W {}
1350 pub mod RW {
1351 #[doc = "No compare event has occurred for a particular VALx value."]
1352 pub const CMPF_0: u16 = 0;
1353 #[doc = "A compare event has occurred for a particular VALx value."]
1354 pub const CMPF_1: u16 = 0x01;
1355 }
1356 }
1357 #[doc = "Capture Flag X0"]
1358 pub mod CFX0 {
1359 pub const offset: u16 = 6;
1360 pub const mask: u16 = 0x01 << offset;
1361 pub mod R {}
1362 pub mod W {}
1363 pub mod RW {}
1364 }
1365 #[doc = "Capture Flag X1"]
1366 pub mod CFX1 {
1367 pub const offset: u16 = 7;
1368 pub const mask: u16 = 0x01 << offset;
1369 pub mod R {}
1370 pub mod W {}
1371 pub mod RW {}
1372 }
1373 #[doc = "Capture Flag B0"]
1374 pub mod CFB0 {
1375 pub const offset: u16 = 8;
1376 pub const mask: u16 = 0x01 << offset;
1377 pub mod R {}
1378 pub mod W {}
1379 pub mod RW {}
1380 }
1381 #[doc = "Capture Flag B1"]
1382 pub mod CFB1 {
1383 pub const offset: u16 = 9;
1384 pub const mask: u16 = 0x01 << offset;
1385 pub mod R {}
1386 pub mod W {}
1387 pub mod RW {}
1388 }
1389 #[doc = "Capture Flag A0"]
1390 pub mod CFA0 {
1391 pub const offset: u16 = 10;
1392 pub const mask: u16 = 0x01 << offset;
1393 pub mod R {}
1394 pub mod W {}
1395 pub mod RW {}
1396 }
1397 #[doc = "Capture Flag A1"]
1398 pub mod CFA1 {
1399 pub const offset: u16 = 11;
1400 pub const mask: u16 = 0x01 << offset;
1401 pub mod R {}
1402 pub mod W {}
1403 pub mod RW {}
1404 }
1405 #[doc = "Reload Flag"]
1406 pub mod RF {
1407 pub const offset: u16 = 12;
1408 pub const mask: u16 = 0x01 << offset;
1409 pub mod R {}
1410 pub mod W {}
1411 pub mod RW {
1412 #[doc = "No new reload cycle since last STS\\[RF\\] clearing"]
1413 pub const RF_0: u16 = 0;
1414 #[doc = "New reload cycle since last STS\\[RF\\] clearing"]
1415 pub const RF_1: u16 = 0x01;
1416 }
1417 }
1418 #[doc = "Reload Error Flag"]
1419 pub mod REF {
1420 pub const offset: u16 = 13;
1421 pub const mask: u16 = 0x01 << offset;
1422 pub mod R {}
1423 pub mod W {}
1424 pub mod RW {
1425 #[doc = "No reload error occurred."]
1426 pub const REF_0: u16 = 0;
1427 #[doc = "Reload signal occurred with non-coherent data and MCTRL\\[LDOK\\] = 0."]
1428 pub const REF_1: u16 = 0x01;
1429 }
1430 }
1431 #[doc = "Registers Updated Flag"]
1432 pub mod RUF {
1433 pub const offset: u16 = 14;
1434 pub const mask: u16 = 0x01 << offset;
1435 pub mod R {}
1436 pub mod W {}
1437 pub mod RW {
1438 #[doc = "No register update has occurred since last reload."]
1439 pub const RUF_0: u16 = 0;
1440 #[doc = "At least one of the double buffered registers has been updated since the last reload."]
1441 pub const RUF_1: u16 = 0x01;
1442 }
1443 }
1444 }
1445 #[doc = "Interrupt Enable Register"]
1446 pub mod SMINTEN {
1447 #[doc = "Compare Interrupt Enables"]
1448 pub mod CMPIE {
1449 pub const offset: u16 = 0;
1450 pub const mask: u16 = 0x3f << offset;
1451 pub mod R {}
1452 pub mod W {}
1453 pub mod RW {
1454 #[doc = "The corresponding STS\\[CMPF\\] bit will not cause an interrupt request."]
1455 pub const CMPIE_0: u16 = 0;
1456 #[doc = "The corresponding STS\\[CMPF\\] bit will cause an interrupt request."]
1457 pub const CMPIE_1: u16 = 0x01;
1458 }
1459 }
1460 #[doc = "Capture X 0 Interrupt Enable"]
1461 pub mod CX0IE {
1462 pub const offset: u16 = 6;
1463 pub const mask: u16 = 0x01 << offset;
1464 pub mod R {}
1465 pub mod W {}
1466 pub mod RW {
1467 #[doc = "Interrupt request disabled for STS\\[CFX0\\]."]
1468 pub const CX0IE_0: u16 = 0;
1469 #[doc = "Interrupt request enabled for STS\\[CFX0\\]."]
1470 pub const CX0IE_1: u16 = 0x01;
1471 }
1472 }
1473 #[doc = "Capture X 1 Interrupt Enable"]
1474 pub mod CX1IE {
1475 pub const offset: u16 = 7;
1476 pub const mask: u16 = 0x01 << offset;
1477 pub mod R {}
1478 pub mod W {}
1479 pub mod RW {
1480 #[doc = "Interrupt request disabled for STS\\[CFX1\\]."]
1481 pub const CX1IE_0: u16 = 0;
1482 #[doc = "Interrupt request enabled for STS\\[CFX1\\]."]
1483 pub const CX1IE_1: u16 = 0x01;
1484 }
1485 }
1486 #[doc = "Capture B 0 Interrupt Enable"]
1487 pub mod CB0IE {
1488 pub const offset: u16 = 8;
1489 pub const mask: u16 = 0x01 << offset;
1490 pub mod R {}
1491 pub mod W {}
1492 pub mod RW {
1493 #[doc = "Interrupt request disabled for STS\\[CFB0\\]."]
1494 pub const CB0IE_0: u16 = 0;
1495 #[doc = "Interrupt request enabled for STS\\[CFB0\\]."]
1496 pub const CB0IE_1: u16 = 0x01;
1497 }
1498 }
1499 #[doc = "Capture B 1 Interrupt Enable"]
1500 pub mod CB1IE {
1501 pub const offset: u16 = 9;
1502 pub const mask: u16 = 0x01 << offset;
1503 pub mod R {}
1504 pub mod W {}
1505 pub mod RW {
1506 #[doc = "Interrupt request disabled for STS\\[CFB1\\]."]
1507 pub const CB1IE_0: u16 = 0;
1508 #[doc = "Interrupt request enabled for STS\\[CFB1\\]."]
1509 pub const CB1IE_1: u16 = 0x01;
1510 }
1511 }
1512 #[doc = "Capture A 0 Interrupt Enable"]
1513 pub mod CA0IE {
1514 pub const offset: u16 = 10;
1515 pub const mask: u16 = 0x01 << offset;
1516 pub mod R {}
1517 pub mod W {}
1518 pub mod RW {
1519 #[doc = "Interrupt request disabled for STS\\[CFA0\\]."]
1520 pub const CA0IE_0: u16 = 0;
1521 #[doc = "Interrupt request enabled for STS\\[CFA0\\]."]
1522 pub const CA0IE_1: u16 = 0x01;
1523 }
1524 }
1525 #[doc = "Capture A 1 Interrupt Enable"]
1526 pub mod CA1IE {
1527 pub const offset: u16 = 11;
1528 pub const mask: u16 = 0x01 << offset;
1529 pub mod R {}
1530 pub mod W {}
1531 pub mod RW {
1532 #[doc = "Interrupt request disabled for STS\\[CFA1\\]."]
1533 pub const CA1IE_0: u16 = 0;
1534 #[doc = "Interrupt request enabled for STS\\[CFA1\\]."]
1535 pub const CA1IE_1: u16 = 0x01;
1536 }
1537 }
1538 #[doc = "Reload Interrupt Enable"]
1539 pub mod RIE {
1540 pub const offset: u16 = 12;
1541 pub const mask: u16 = 0x01 << offset;
1542 pub mod R {}
1543 pub mod W {}
1544 pub mod RW {
1545 #[doc = "STS\\[RF\\] CPU interrupt requests disabled"]
1546 pub const RIE_0: u16 = 0;
1547 #[doc = "STS\\[RF\\] CPU interrupt requests enabled"]
1548 pub const RIE_1: u16 = 0x01;
1549 }
1550 }
1551 #[doc = "Reload Error Interrupt Enable"]
1552 pub mod REIE {
1553 pub const offset: u16 = 13;
1554 pub const mask: u16 = 0x01 << offset;
1555 pub mod R {}
1556 pub mod W {}
1557 pub mod RW {
1558 #[doc = "STS\\[REF\\] CPU interrupt requests disabled"]
1559 pub const REIE_0: u16 = 0;
1560 #[doc = "STS\\[REF\\] CPU interrupt requests enabled"]
1561 pub const REIE_1: u16 = 0x01;
1562 }
1563 }
1564 }
1565 #[doc = "DMA Enable Register"]
1566 pub mod SMDMAEN {
1567 #[doc = "Capture X0 FIFO DMA Enable"]
1568 pub mod CX0DE {
1569 pub const offset: u16 = 0;
1570 pub const mask: u16 = 0x01 << offset;
1571 pub mod R {}
1572 pub mod W {}
1573 pub mod RW {}
1574 }
1575 #[doc = "Capture X1 FIFO DMA Enable"]
1576 pub mod CX1DE {
1577 pub const offset: u16 = 1;
1578 pub const mask: u16 = 0x01 << offset;
1579 pub mod R {}
1580 pub mod W {}
1581 pub mod RW {}
1582 }
1583 #[doc = "Capture B0 FIFO DMA Enable"]
1584 pub mod CB0DE {
1585 pub const offset: u16 = 2;
1586 pub const mask: u16 = 0x01 << offset;
1587 pub mod R {}
1588 pub mod W {}
1589 pub mod RW {}
1590 }
1591 #[doc = "Capture B1 FIFO DMA Enable"]
1592 pub mod CB1DE {
1593 pub const offset: u16 = 3;
1594 pub const mask: u16 = 0x01 << offset;
1595 pub mod R {}
1596 pub mod W {}
1597 pub mod RW {}
1598 }
1599 #[doc = "Capture A0 FIFO DMA Enable"]
1600 pub mod CA0DE {
1601 pub const offset: u16 = 4;
1602 pub const mask: u16 = 0x01 << offset;
1603 pub mod R {}
1604 pub mod W {}
1605 pub mod RW {}
1606 }
1607 #[doc = "Capture A1 FIFO DMA Enable"]
1608 pub mod CA1DE {
1609 pub const offset: u16 = 5;
1610 pub const mask: u16 = 0x01 << offset;
1611 pub mod R {}
1612 pub mod W {}
1613 pub mod RW {}
1614 }
1615 #[doc = "Capture DMA Enable Source Select"]
1616 pub mod CAPTDE {
1617 pub const offset: u16 = 6;
1618 pub const mask: u16 = 0x03 << offset;
1619 pub mod R {}
1620 pub mod W {}
1621 pub mod RW {
1622 #[doc = "Read DMA requests disabled."]
1623 pub const CAPTDE_0: u16 = 0;
1624 #[doc = "Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN\\[CA1DE\\], DMAEN\\[CA0DE\\], DMAEN\\[CB1DE\\], DMAEN\\[CB0DE\\], DMAEN\\[CX1DE\\], or DMAEN\\[CX0DE\\] to also be set in order to determine to which watermark(s) the DMA request is sensitive."]
1625 pub const CAPTDE_1: u16 = 0x01;
1626 #[doc = "A local sync (VAL1 matches counter) sets the read DMA request."]
1627 pub const CAPTDE_2: u16 = 0x02;
1628 #[doc = "A local reload (STS\\[RF\\] being set) sets the read DMA request."]
1629 pub const CAPTDE_3: u16 = 0x03;
1630 }
1631 }
1632 #[doc = "FIFO Watermark AND Control"]
1633 pub mod FAND {
1634 pub const offset: u16 = 8;
1635 pub const mask: u16 = 0x01 << offset;
1636 pub mod R {}
1637 pub mod W {}
1638 pub mod RW {
1639 #[doc = "Selected FIFO watermarks are OR'ed together."]
1640 pub const FAND_0: u16 = 0;
1641 #[doc = "Selected FIFO watermarks are AND'ed together."]
1642 pub const FAND_1: u16 = 0x01;
1643 }
1644 }
1645 #[doc = "Value Registers DMA Enable"]
1646 pub mod VALDE {
1647 pub const offset: u16 = 9;
1648 pub const mask: u16 = 0x01 << offset;
1649 pub mod R {}
1650 pub mod W {}
1651 pub mod RW {
1652 #[doc = "DMA write requests disabled"]
1653 pub const VALDE_0: u16 = 0;
1654 #[doc = "DMA write requests for the VALx and FRACVALx registers enabled"]
1655 pub const VALDE_1: u16 = 0x01;
1656 }
1657 }
1658 }
1659 #[doc = "Output Trigger Control Register"]
1660 pub mod SMTCTRL {
1661 #[doc = "Output Trigger Enables"]
1662 pub mod OUT_TRIG_EN {
1663 pub const offset: u16 = 0;
1664 pub const mask: u16 = 0x3f << offset;
1665 pub mod R {}
1666 pub mod W {}
1667 pub mod RW {
1668 #[doc = "PWM_OUT_TRIGx will not set when the counter value matches the VALx value."]
1669 pub const OUT_TRIG_EN_0: u16 = 0;
1670 #[doc = "PWM_OUT_TRIGx will set when the counter value matches the VALx value."]
1671 pub const OUT_TRIG_EN_1: u16 = 0x01;
1672 }
1673 }
1674 #[doc = "Trigger frequency"]
1675 pub mod TRGFRQ {
1676 pub const offset: u16 = 12;
1677 pub const mask: u16 = 0x01 << offset;
1678 pub mod R {}
1679 pub mod W {}
1680 pub mod RW {
1681 #[doc = "Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."]
1682 pub const TRGFRQ_0: u16 = 0;
1683 #[doc = "Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL\\[LDFQ\\] being non-zero."]
1684 pub const TRGFRQ_1: u16 = 0x01;
1685 }
1686 }
1687 #[doc = "Output Trigger 1 Source Select"]
1688 pub mod PWBOT1 {
1689 pub const offset: u16 = 14;
1690 pub const mask: u16 = 0x01 << offset;
1691 pub mod R {}
1692 pub mod W {}
1693 pub mod RW {
1694 #[doc = "Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port."]
1695 pub const PWBOT1_0: u16 = 0;
1696 #[doc = "Route the PWMB output to the PWM_OUT_TRIG1 port."]
1697 pub const PWBOT1_1: u16 = 0x01;
1698 }
1699 }
1700 #[doc = "Output Trigger 0 Source Select"]
1701 pub mod PWAOT0 {
1702 pub const offset: u16 = 15;
1703 pub const mask: u16 = 0x01 << offset;
1704 pub mod R {}
1705 pub mod W {}
1706 pub mod RW {
1707 #[doc = "Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port."]
1708 pub const PWAOT0_0: u16 = 0;
1709 #[doc = "Route the PWMA output to the PWM_OUT_TRIG0 port."]
1710 pub const PWAOT0_1: u16 = 0x01;
1711 }
1712 }
1713 }
1714 #[doc = "Fault Disable Mapping Register 0"]
1715 pub mod SMDISMAP0 {
1716 #[doc = "PWM_A Fault Disable Mask 0"]
1717 pub mod DIS0A {
1718 pub const offset: u16 = 0;
1719 pub const mask: u16 = 0x0f << offset;
1720 pub mod R {}
1721 pub mod W {}
1722 pub mod RW {}
1723 }
1724 #[doc = "PWM_B Fault Disable Mask 0"]
1725 pub mod DIS0B {
1726 pub const offset: u16 = 4;
1727 pub const mask: u16 = 0x0f << offset;
1728 pub mod R {}
1729 pub mod W {}
1730 pub mod RW {}
1731 }
1732 #[doc = "PWM_X Fault Disable Mask 0"]
1733 pub mod DIS0X {
1734 pub const offset: u16 = 8;
1735 pub const mask: u16 = 0x0f << offset;
1736 pub mod R {}
1737 pub mod W {}
1738 pub mod RW {}
1739 }
1740 }
1741 #[doc = "Fault Disable Mapping Register 1"]
1742 pub mod SMDISMAP1 {
1743 #[doc = "PWM_A Fault Disable Mask 1"]
1744 pub mod DIS1A {
1745 pub const offset: u16 = 0;
1746 pub const mask: u16 = 0x0f << offset;
1747 pub mod R {}
1748 pub mod W {}
1749 pub mod RW {}
1750 }
1751 #[doc = "PWM_B Fault Disable Mask 1"]
1752 pub mod DIS1B {
1753 pub const offset: u16 = 4;
1754 pub const mask: u16 = 0x0f << offset;
1755 pub mod R {}
1756 pub mod W {}
1757 pub mod RW {}
1758 }
1759 #[doc = "PWM_X Fault Disable Mask 1"]
1760 pub mod DIS1X {
1761 pub const offset: u16 = 8;
1762 pub const mask: u16 = 0x0f << offset;
1763 pub mod R {}
1764 pub mod W {}
1765 pub mod RW {}
1766 }
1767 }
1768 #[doc = "Deadtime Count Register 0"]
1769 pub mod SMDTCNT0 {
1770 #[doc = "DTCNT0"]
1771 pub mod DTCNT0 {
1772 pub const offset: u16 = 0;
1773 pub const mask: u16 = 0xffff << offset;
1774 pub mod R {}
1775 pub mod W {}
1776 pub mod RW {}
1777 }
1778 }
1779 #[doc = "Deadtime Count Register 1"]
1780 pub mod SMDTCNT1 {
1781 #[doc = "DTCNT1"]
1782 pub mod DTCNT1 {
1783 pub const offset: u16 = 0;
1784 pub const mask: u16 = 0xffff << offset;
1785 pub mod R {}
1786 pub mod W {}
1787 pub mod RW {}
1788 }
1789 }
1790 #[doc = "Capture Control A Register"]
1791 pub mod SMCAPTCTRLA {
1792 #[doc = "Arm A"]
1793 pub mod ARMA {
1794 pub const offset: u16 = 0;
1795 pub const mask: u16 = 0x01 << offset;
1796 pub mod R {}
1797 pub mod W {}
1798 pub mod RW {
1799 #[doc = "Input capture operation is disabled."]
1800 pub const ARMA_0: u16 = 0;
1801 #[doc = "Input capture operation as specified by CAPTCTRLA\\[EDGAx\\] is enabled."]
1802 pub const ARMA_1: u16 = 0x01;
1803 }
1804 }
1805 #[doc = "One Shot Mode A"]
1806 pub mod ONESHOTA {
1807 pub const offset: u16 = 1;
1808 pub const mask: u16 = 0x01 << offset;
1809 pub mod R {}
1810 pub mod W {}
1811 pub mod RW {
1812 #[doc = "Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA\\[ARMA\\] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit."]
1813 pub const ONESHOTA_0: u16 = 0;
1814 #[doc = "One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA\\[ARMA\\] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA\\[ARMA\\] is cleared. No further captures will be performed until CAPTCTRLA\\[ARMA\\] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA\\[ARMA\\] is then cleared."]
1815 pub const ONESHOTA_1: u16 = 0x01;
1816 }
1817 }
1818 #[doc = "Edge A 0"]
1819 pub mod EDGA0 {
1820 pub const offset: u16 = 2;
1821 pub const mask: u16 = 0x03 << offset;
1822 pub mod R {}
1823 pub mod W {}
1824 pub mod RW {
1825 #[doc = "Disabled"]
1826 pub const EDGA0_0: u16 = 0;
1827 #[doc = "Capture falling edges"]
1828 pub const EDGA0_1: u16 = 0x01;
1829 #[doc = "Capture rising edges"]
1830 pub const EDGA0_2: u16 = 0x02;
1831 #[doc = "Capture any edge"]
1832 pub const EDGA0_3: u16 = 0x03;
1833 }
1834 }
1835 #[doc = "Edge A 1"]
1836 pub mod EDGA1 {
1837 pub const offset: u16 = 4;
1838 pub const mask: u16 = 0x03 << offset;
1839 pub mod R {}
1840 pub mod W {}
1841 pub mod RW {
1842 #[doc = "Disabled"]
1843 pub const EDGA1_0: u16 = 0;
1844 #[doc = "Capture falling edges"]
1845 pub const EDGA1_1: u16 = 0x01;
1846 #[doc = "Capture rising edges"]
1847 pub const EDGA1_2: u16 = 0x02;
1848 #[doc = "Capture any edge"]
1849 pub const EDGA1_3: u16 = 0x03;
1850 }
1851 }
1852 #[doc = "Input Select A"]
1853 pub mod INP_SELA {
1854 pub const offset: u16 = 6;
1855 pub const mask: u16 = 0x01 << offset;
1856 pub mod R {}
1857 pub mod W {}
1858 pub mod RW {
1859 #[doc = "Raw PWM_A input signal selected as source."]
1860 pub const INP_SELA_0: u16 = 0;
1861 #[doc = "Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA\\[EDGA0\\] and CAPTCTRLA\\[EDGA1\\] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA\\[EDGA0\\] and/or CAPTCTRLA\\[EDGA1\\] fields in order to enable one or both of the capture registers."]
1862 pub const INP_SELA_1: u16 = 0x01;
1863 }
1864 }
1865 #[doc = "Edge Counter A Enable"]
1866 pub mod EDGCNTA_EN {
1867 pub const offset: u16 = 7;
1868 pub const mask: u16 = 0x01 << offset;
1869 pub mod R {}
1870 pub mod W {}
1871 pub mod RW {
1872 #[doc = "Edge counter disabled and held in reset"]
1873 pub const EDGCNTA_EN_0: u16 = 0;
1874 #[doc = "Edge counter enabled"]
1875 pub const EDGCNTA_EN_1: u16 = 0x01;
1876 }
1877 }
1878 #[doc = "Capture A FIFOs Water Mark"]
1879 pub mod CFAWM {
1880 pub const offset: u16 = 8;
1881 pub const mask: u16 = 0x03 << offset;
1882 pub mod R {}
1883 pub mod W {}
1884 pub mod RW {}
1885 }
1886 #[doc = "Capture A0 FIFO Word Count"]
1887 pub mod CA0CNT {
1888 pub const offset: u16 = 10;
1889 pub const mask: u16 = 0x07 << offset;
1890 pub mod R {}
1891 pub mod W {}
1892 pub mod RW {}
1893 }
1894 #[doc = "Capture A1 FIFO Word Count"]
1895 pub mod CA1CNT {
1896 pub const offset: u16 = 13;
1897 pub const mask: u16 = 0x07 << offset;
1898 pub mod R {}
1899 pub mod W {}
1900 pub mod RW {}
1901 }
1902 }
1903 #[doc = "Capture Compare A Register"]
1904 pub mod SMCAPTCOMPA {
1905 #[doc = "Edge Compare A"]
1906 pub mod EDGCMPA {
1907 pub const offset: u16 = 0;
1908 pub const mask: u16 = 0xff << offset;
1909 pub mod R {}
1910 pub mod W {}
1911 pub mod RW {}
1912 }
1913 #[doc = "Edge Counter A"]
1914 pub mod EDGCNTA {
1915 pub const offset: u16 = 8;
1916 pub const mask: u16 = 0xff << offset;
1917 pub mod R {}
1918 pub mod W {}
1919 pub mod RW {}
1920 }
1921 }
1922 #[doc = "Capture Control B Register"]
1923 pub mod SMCAPTCTRLB {
1924 #[doc = "Arm B"]
1925 pub mod ARMB {
1926 pub const offset: u16 = 0;
1927 pub const mask: u16 = 0x01 << offset;
1928 pub mod R {}
1929 pub mod W {}
1930 pub mod RW {
1931 #[doc = "Input capture operation is disabled."]
1932 pub const ARMB_0: u16 = 0;
1933 #[doc = "Input capture operation as specified by CAPTCTRLB\\[EDGBx\\] is enabled."]
1934 pub const ARMB_1: u16 = 0x01;
1935 }
1936 }
1937 #[doc = "One Shot Mode B"]
1938 pub mod ONESHOTB {
1939 pub const offset: u16 = 1;
1940 pub const mask: u16 = 0x01 << offset;
1941 pub mod R {}
1942 pub mod W {}
1943 pub mod RW {
1944 #[doc = "Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB\\[ARMB\\] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit."]
1945 pub const ONESHOTB_0: u16 = 0;
1946 #[doc = "One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB\\[ARMB\\] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB\\[ARMB\\] is cleared. No further captures will be performed until CAPTCTRLB\\[ARMB\\] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB\\[ARMB\\] is then cleared."]
1947 pub const ONESHOTB_1: u16 = 0x01;
1948 }
1949 }
1950 #[doc = "Edge B 0"]
1951 pub mod EDGB0 {
1952 pub const offset: u16 = 2;
1953 pub const mask: u16 = 0x03 << offset;
1954 pub mod R {}
1955 pub mod W {}
1956 pub mod RW {
1957 #[doc = "Disabled"]
1958 pub const EDGB0_0: u16 = 0;
1959 #[doc = "Capture falling edges"]
1960 pub const EDGB0_1: u16 = 0x01;
1961 #[doc = "Capture rising edges"]
1962 pub const EDGB0_2: u16 = 0x02;
1963 #[doc = "Capture any edge"]
1964 pub const EDGB0_3: u16 = 0x03;
1965 }
1966 }
1967 #[doc = "Edge B 1"]
1968 pub mod EDGB1 {
1969 pub const offset: u16 = 4;
1970 pub const mask: u16 = 0x03 << offset;
1971 pub mod R {}
1972 pub mod W {}
1973 pub mod RW {
1974 #[doc = "Disabled"]
1975 pub const EDGB1_0: u16 = 0;
1976 #[doc = "Capture falling edges"]
1977 pub const EDGB1_1: u16 = 0x01;
1978 #[doc = "Capture rising edges"]
1979 pub const EDGB1_2: u16 = 0x02;
1980 #[doc = "Capture any edge"]
1981 pub const EDGB1_3: u16 = 0x03;
1982 }
1983 }
1984 #[doc = "Input Select B"]
1985 pub mod INP_SELB {
1986 pub const offset: u16 = 6;
1987 pub const mask: u16 = 0x01 << offset;
1988 pub mod R {}
1989 pub mod W {}
1990 pub mod RW {
1991 #[doc = "Raw PWM_B input signal selected as source."]
1992 pub const INP_SELB_0: u16 = 0;
1993 #[doc = "Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB\\[EDGB0\\] and CAPTCTRLB\\[EDGB1\\] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB\\[EDGB0\\] and/or CAPTCTRLB\\[EDGB1\\] fields in order to enable one or both of the capture registers."]
1994 pub const INP_SELB_1: u16 = 0x01;
1995 }
1996 }
1997 #[doc = "Edge Counter B Enable"]
1998 pub mod EDGCNTB_EN {
1999 pub const offset: u16 = 7;
2000 pub const mask: u16 = 0x01 << offset;
2001 pub mod R {}
2002 pub mod W {}
2003 pub mod RW {
2004 #[doc = "Edge counter disabled and held in reset"]
2005 pub const EDGCNTB_EN_0: u16 = 0;
2006 #[doc = "Edge counter enabled"]
2007 pub const EDGCNTB_EN_1: u16 = 0x01;
2008 }
2009 }
2010 #[doc = "Capture B FIFOs Water Mark"]
2011 pub mod CFBWM {
2012 pub const offset: u16 = 8;
2013 pub const mask: u16 = 0x03 << offset;
2014 pub mod R {}
2015 pub mod W {}
2016 pub mod RW {}
2017 }
2018 #[doc = "Capture B0 FIFO Word Count"]
2019 pub mod CB0CNT {
2020 pub const offset: u16 = 10;
2021 pub const mask: u16 = 0x07 << offset;
2022 pub mod R {}
2023 pub mod W {}
2024 pub mod RW {}
2025 }
2026 #[doc = "Capture B1 FIFO Word Count"]
2027 pub mod CB1CNT {
2028 pub const offset: u16 = 13;
2029 pub const mask: u16 = 0x07 << offset;
2030 pub mod R {}
2031 pub mod W {}
2032 pub mod RW {}
2033 }
2034 }
2035 #[doc = "Capture Compare B Register"]
2036 pub mod SMCAPTCOMPB {
2037 #[doc = "Edge Compare B"]
2038 pub mod EDGCMPB {
2039 pub const offset: u16 = 0;
2040 pub const mask: u16 = 0xff << offset;
2041 pub mod R {}
2042 pub mod W {}
2043 pub mod RW {}
2044 }
2045 #[doc = "Edge Counter B"]
2046 pub mod EDGCNTB {
2047 pub const offset: u16 = 8;
2048 pub const mask: u16 = 0xff << offset;
2049 pub mod R {}
2050 pub mod W {}
2051 pub mod RW {}
2052 }
2053 }
2054 #[doc = "Capture Control X Register"]
2055 pub mod SMCAPTCTRLX {
2056 #[doc = "Arm X"]
2057 pub mod ARMX {
2058 pub const offset: u16 = 0;
2059 pub const mask: u16 = 0x01 << offset;
2060 pub mod R {}
2061 pub mod W {}
2062 pub mod RW {
2063 #[doc = "Input capture operation is disabled."]
2064 pub const ARMX_0: u16 = 0;
2065 #[doc = "Input capture operation as specified by CAPTCTRLX\\[EDGXx\\] is enabled."]
2066 pub const ARMX_1: u16 = 0x01;
2067 }
2068 }
2069 #[doc = "One Shot Mode Aux"]
2070 pub mod ONESHOTX {
2071 pub const offset: u16 = 1;
2072 pub const mask: u16 = 0x01 << offset;
2073 pub mod R {}
2074 pub mod W {}
2075 pub mod RW {
2076 #[doc = "Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit."]
2077 pub const ONESHOTX_0: u16 = 0;
2078 #[doc = "One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared."]
2079 pub const ONESHOTX_1: u16 = 0x01;
2080 }
2081 }
2082 #[doc = "Edge X 0"]
2083 pub mod EDGX0 {
2084 pub const offset: u16 = 2;
2085 pub const mask: u16 = 0x03 << offset;
2086 pub mod R {}
2087 pub mod W {}
2088 pub mod RW {
2089 #[doc = "Disabled"]
2090 pub const EDGX0_0: u16 = 0;
2091 #[doc = "Capture falling edges"]
2092 pub const EDGX0_1: u16 = 0x01;
2093 #[doc = "Capture rising edges"]
2094 pub const EDGX0_2: u16 = 0x02;
2095 #[doc = "Capture any edge"]
2096 pub const EDGX0_3: u16 = 0x03;
2097 }
2098 }
2099 #[doc = "Edge X 1"]
2100 pub mod EDGX1 {
2101 pub const offset: u16 = 4;
2102 pub const mask: u16 = 0x03 << offset;
2103 pub mod R {}
2104 pub mod W {}
2105 pub mod RW {
2106 #[doc = "Disabled"]
2107 pub const EDGX1_0: u16 = 0;
2108 #[doc = "Capture falling edges"]
2109 pub const EDGX1_1: u16 = 0x01;
2110 #[doc = "Capture rising edges"]
2111 pub const EDGX1_2: u16 = 0x02;
2112 #[doc = "Capture any edge"]
2113 pub const EDGX1_3: u16 = 0x03;
2114 }
2115 }
2116 #[doc = "Input Select X"]
2117 pub mod INP_SELX {
2118 pub const offset: u16 = 6;
2119 pub const mask: u16 = 0x01 << offset;
2120 pub mod R {}
2121 pub mod W {}
2122 pub mod RW {
2123 #[doc = "Raw PWM_X input signal selected as source."]
2124 pub const INP_SELX_0: u16 = 0;
2125 #[doc = "Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX\\[EDGX0\\] and CAPTCTRLX\\[EDGX1\\] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX\\[EDGX0\\] and/or CAPTCTRLX\\[EDGX1\\] fields in order to enable one or both of the capture registers."]
2126 pub const INP_SELX_1: u16 = 0x01;
2127 }
2128 }
2129 #[doc = "Edge Counter X Enable"]
2130 pub mod EDGCNTX_EN {
2131 pub const offset: u16 = 7;
2132 pub const mask: u16 = 0x01 << offset;
2133 pub mod R {}
2134 pub mod W {}
2135 pub mod RW {
2136 #[doc = "Edge counter disabled and held in reset"]
2137 pub const EDGCNTX_EN_0: u16 = 0;
2138 #[doc = "Edge counter enabled"]
2139 pub const EDGCNTX_EN_1: u16 = 0x01;
2140 }
2141 }
2142 #[doc = "Capture X FIFOs Water Mark"]
2143 pub mod CFXWM {
2144 pub const offset: u16 = 8;
2145 pub const mask: u16 = 0x03 << offset;
2146 pub mod R {}
2147 pub mod W {}
2148 pub mod RW {}
2149 }
2150 #[doc = "Capture X0 FIFO Word Count"]
2151 pub mod CX0CNT {
2152 pub const offset: u16 = 10;
2153 pub const mask: u16 = 0x07 << offset;
2154 pub mod R {}
2155 pub mod W {}
2156 pub mod RW {}
2157 }
2158 #[doc = "Capture X1 FIFO Word Count"]
2159 pub mod CX1CNT {
2160 pub const offset: u16 = 13;
2161 pub const mask: u16 = 0x07 << offset;
2162 pub mod R {}
2163 pub mod W {}
2164 pub mod RW {}
2165 }
2166 }
2167 #[doc = "Capture Compare X Register"]
2168 pub mod SMCAPTCOMPX {
2169 #[doc = "Edge Compare X"]
2170 pub mod EDGCMPX {
2171 pub const offset: u16 = 0;
2172 pub const mask: u16 = 0xff << offset;
2173 pub mod R {}
2174 pub mod W {}
2175 pub mod RW {}
2176 }
2177 #[doc = "Edge Counter X"]
2178 pub mod EDGCNTX {
2179 pub const offset: u16 = 8;
2180 pub const mask: u16 = 0xff << offset;
2181 pub mod R {}
2182 pub mod W {}
2183 pub mod RW {}
2184 }
2185 }
2186 #[doc = "Capture Value 0 Register"]
2187 pub mod SMCVAL0 {
2188 #[doc = "CAPTVAL0"]
2189 pub mod CAPTVAL0 {
2190 pub const offset: u16 = 0;
2191 pub const mask: u16 = 0xffff << offset;
2192 pub mod R {}
2193 pub mod W {}
2194 pub mod RW {}
2195 }
2196 }
2197 #[doc = "Capture Value 0 Cycle Register"]
2198 pub mod SMCVAL0CYC {
2199 #[doc = "CVAL0CYC"]
2200 pub mod CVAL0CYC {
2201 pub const offset: u16 = 0;
2202 pub const mask: u16 = 0x0f << offset;
2203 pub mod R {}
2204 pub mod W {}
2205 pub mod RW {}
2206 }
2207 }
2208 #[doc = "Capture Value 1 Register"]
2209 pub mod SMCVAL1 {
2210 #[doc = "CAPTVAL1"]
2211 pub mod CAPTVAL1 {
2212 pub const offset: u16 = 0;
2213 pub const mask: u16 = 0xffff << offset;
2214 pub mod R {}
2215 pub mod W {}
2216 pub mod RW {}
2217 }
2218 }
2219 #[doc = "Capture Value 1 Cycle Register"]
2220 pub mod SMCVAL1CYC {
2221 #[doc = "CVAL1CYC"]
2222 pub mod CVAL1CYC {
2223 pub const offset: u16 = 0;
2224 pub const mask: u16 = 0x0f << offset;
2225 pub mod R {}
2226 pub mod W {}
2227 pub mod RW {}
2228 }
2229 }
2230 #[doc = "Capture Value 2 Register"]
2231 pub mod SMCVAL2 {
2232 #[doc = "CAPTVAL2"]
2233 pub mod CAPTVAL2 {
2234 pub const offset: u16 = 0;
2235 pub const mask: u16 = 0xffff << offset;
2236 pub mod R {}
2237 pub mod W {}
2238 pub mod RW {}
2239 }
2240 }
2241 #[doc = "Capture Value 2 Cycle Register"]
2242 pub mod SMCVAL2CYC {
2243 #[doc = "CVAL2CYC"]
2244 pub mod CVAL2CYC {
2245 pub const offset: u16 = 0;
2246 pub const mask: u16 = 0x0f << offset;
2247 pub mod R {}
2248 pub mod W {}
2249 pub mod RW {}
2250 }
2251 }
2252 #[doc = "Capture Value 3 Register"]
2253 pub mod SMCVAL3 {
2254 #[doc = "CAPTVAL3"]
2255 pub mod CAPTVAL3 {
2256 pub const offset: u16 = 0;
2257 pub const mask: u16 = 0xffff << offset;
2258 pub mod R {}
2259 pub mod W {}
2260 pub mod RW {}
2261 }
2262 }
2263 #[doc = "Capture Value 3 Cycle Register"]
2264 pub mod SMCVAL3CYC {
2265 #[doc = "CVAL3CYC"]
2266 pub mod CVAL3CYC {
2267 pub const offset: u16 = 0;
2268 pub const mask: u16 = 0x0f << offset;
2269 pub mod R {}
2270 pub mod W {}
2271 pub mod RW {}
2272 }
2273 }
2274 #[doc = "Capture Value 4 Register"]
2275 pub mod SMCVAL4 {
2276 #[doc = "CAPTVAL4"]
2277 pub mod CAPTVAL4 {
2278 pub const offset: u16 = 0;
2279 pub const mask: u16 = 0xffff << offset;
2280 pub mod R {}
2281 pub mod W {}
2282 pub mod RW {}
2283 }
2284 }
2285 #[doc = "Capture Value 4 Cycle Register"]
2286 pub mod SMCVAL4CYC {
2287 #[doc = "CVAL4CYC"]
2288 pub mod CVAL4CYC {
2289 pub const offset: u16 = 0;
2290 pub const mask: u16 = 0x0f << offset;
2291 pub mod R {}
2292 pub mod W {}
2293 pub mod RW {}
2294 }
2295 }
2296 #[doc = "Capture Value 5 Register"]
2297 pub mod SMCVAL5 {
2298 #[doc = "CAPTVAL5"]
2299 pub mod CAPTVAL5 {
2300 pub const offset: u16 = 0;
2301 pub const mask: u16 = 0xffff << offset;
2302 pub mod R {}
2303 pub mod W {}
2304 pub mod RW {}
2305 }
2306 }
2307 #[doc = "Capture Value 5 Cycle Register"]
2308 pub mod SMCVAL5CYC {
2309 #[doc = "CVAL5CYC"]
2310 pub mod CVAL5CYC {
2311 pub const offset: u16 = 0;
2312 pub const mask: u16 = 0x0f << offset;
2313 pub mod R {}
2314 pub mod W {}
2315 pub mod RW {}
2316 }
2317 }
2318}