imxrt_ral/blocks/imxrt1021/
tmr.rs1#[doc = "Quad Timer"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "Timer Channel Compare Register 1"]
5 pub COMP10: crate::RWRegister<u16>,
6 #[doc = "Timer Channel Compare Register 2"]
7 pub COMP20: crate::RWRegister<u16>,
8 #[doc = "Timer Channel Capture Register"]
9 pub CAPT0: crate::RWRegister<u16>,
10 #[doc = "Timer Channel Load Register"]
11 pub LOAD0: crate::RWRegister<u16>,
12 #[doc = "Timer Channel Hold Register"]
13 pub HOLD0: crate::RWRegister<u16>,
14 #[doc = "Timer Channel Counter Register"]
15 pub CNTR0: crate::RWRegister<u16>,
16 #[doc = "Timer Channel Control Register"]
17 pub CTRL0: crate::RWRegister<u16>,
18 #[doc = "Timer Channel Status and Control Register"]
19 pub SCTRL0: crate::RWRegister<u16>,
20 #[doc = "Timer Channel Comparator Load Register 1"]
21 pub CMPLD10: crate::RWRegister<u16>,
22 #[doc = "Timer Channel Comparator Load Register 2"]
23 pub CMPLD20: crate::RWRegister<u16>,
24 #[doc = "Timer Channel Comparator Status and Control Register"]
25 pub CSCTRL0: crate::RWRegister<u16>,
26 #[doc = "Timer Channel Input Filter Register"]
27 pub FILT0: crate::RWRegister<u16>,
28 #[doc = "Timer Channel DMA Enable Register"]
29 pub DMA0: crate::RWRegister<u16>,
30 _reserved0: [u8; 0x04],
31 #[doc = "Timer Channel Enable Register"]
32 pub ENBL: crate::RWRegister<u16>,
33 #[doc = "Timer Channel Compare Register 1"]
34 pub COMP11: crate::RWRegister<u16>,
35 #[doc = "Timer Channel Compare Register 2"]
36 pub COMP21: crate::RWRegister<u16>,
37 #[doc = "Timer Channel Capture Register"]
38 pub CAPT1: crate::RWRegister<u16>,
39 #[doc = "Timer Channel Load Register"]
40 pub LOAD1: crate::RWRegister<u16>,
41 #[doc = "Timer Channel Hold Register"]
42 pub HOLD1: crate::RWRegister<u16>,
43 #[doc = "Timer Channel Counter Register"]
44 pub CNTR1: crate::RWRegister<u16>,
45 #[doc = "Timer Channel Control Register"]
46 pub CTRL1: crate::RWRegister<u16>,
47 #[doc = "Timer Channel Status and Control Register"]
48 pub SCTRL1: crate::RWRegister<u16>,
49 #[doc = "Timer Channel Comparator Load Register 1"]
50 pub CMPLD11: crate::RWRegister<u16>,
51 #[doc = "Timer Channel Comparator Load Register 2"]
52 pub CMPLD21: crate::RWRegister<u16>,
53 #[doc = "Timer Channel Comparator Status and Control Register"]
54 pub CSCTRL1: crate::RWRegister<u16>,
55 #[doc = "Timer Channel Input Filter Register"]
56 pub FILT1: crate::RWRegister<u16>,
57 #[doc = "Timer Channel DMA Enable Register"]
58 pub DMA1: crate::RWRegister<u16>,
59 _reserved1: [u8; 0x06],
60 #[doc = "Timer Channel Compare Register 1"]
61 pub COMP12: crate::RWRegister<u16>,
62 #[doc = "Timer Channel Compare Register 2"]
63 pub COMP22: crate::RWRegister<u16>,
64 #[doc = "Timer Channel Capture Register"]
65 pub CAPT2: crate::RWRegister<u16>,
66 #[doc = "Timer Channel Load Register"]
67 pub LOAD2: crate::RWRegister<u16>,
68 #[doc = "Timer Channel Hold Register"]
69 pub HOLD2: crate::RWRegister<u16>,
70 #[doc = "Timer Channel Counter Register"]
71 pub CNTR2: crate::RWRegister<u16>,
72 #[doc = "Timer Channel Control Register"]
73 pub CTRL2: crate::RWRegister<u16>,
74 #[doc = "Timer Channel Status and Control Register"]
75 pub SCTRL2: crate::RWRegister<u16>,
76 #[doc = "Timer Channel Comparator Load Register 1"]
77 pub CMPLD12: crate::RWRegister<u16>,
78 #[doc = "Timer Channel Comparator Load Register 2"]
79 pub CMPLD22: crate::RWRegister<u16>,
80 #[doc = "Timer Channel Comparator Status and Control Register"]
81 pub CSCTRL2: crate::RWRegister<u16>,
82 #[doc = "Timer Channel Input Filter Register"]
83 pub FILT2: crate::RWRegister<u16>,
84 #[doc = "Timer Channel DMA Enable Register"]
85 pub DMA2: crate::RWRegister<u16>,
86 _reserved2: [u8; 0x06],
87 #[doc = "Timer Channel Compare Register 1"]
88 pub COMP13: crate::RWRegister<u16>,
89 #[doc = "Timer Channel Compare Register 2"]
90 pub COMP23: crate::RWRegister<u16>,
91 #[doc = "Timer Channel Capture Register"]
92 pub CAPT3: crate::RWRegister<u16>,
93 #[doc = "Timer Channel Load Register"]
94 pub LOAD3: crate::RWRegister<u16>,
95 #[doc = "Timer Channel Hold Register"]
96 pub HOLD3: crate::RWRegister<u16>,
97 #[doc = "Timer Channel Counter Register"]
98 pub CNTR3: crate::RWRegister<u16>,
99 #[doc = "Timer Channel Control Register"]
100 pub CTRL3: crate::RWRegister<u16>,
101 #[doc = "Timer Channel Status and Control Register"]
102 pub SCTRL3: crate::RWRegister<u16>,
103 #[doc = "Timer Channel Comparator Load Register 1"]
104 pub CMPLD13: crate::RWRegister<u16>,
105 #[doc = "Timer Channel Comparator Load Register 2"]
106 pub CMPLD23: crate::RWRegister<u16>,
107 #[doc = "Timer Channel Comparator Status and Control Register"]
108 pub CSCTRL3: crate::RWRegister<u16>,
109 #[doc = "Timer Channel Input Filter Register"]
110 pub FILT3: crate::RWRegister<u16>,
111 #[doc = "Timer Channel DMA Enable Register"]
112 pub DMA3: crate::RWRegister<u16>,
113}
114#[doc = "Timer Channel Compare Register 1"]
115pub mod COMP10 {
116 #[doc = "Comparison Value 1"]
117 pub mod COMPARISON_1 {
118 pub const offset: u16 = 0;
119 pub const mask: u16 = 0xffff << offset;
120 pub mod R {}
121 pub mod W {}
122 pub mod RW {}
123 }
124}
125#[doc = "Timer Channel Compare Register 2"]
126pub mod COMP20 {
127 #[doc = "Comparison Value 2"]
128 pub mod COMPARISON_2 {
129 pub const offset: u16 = 0;
130 pub const mask: u16 = 0xffff << offset;
131 pub mod R {}
132 pub mod W {}
133 pub mod RW {}
134 }
135}
136#[doc = "Timer Channel Capture Register"]
137pub mod CAPT0 {
138 #[doc = "Capture Value"]
139 pub mod CAPTURE {
140 pub const offset: u16 = 0;
141 pub const mask: u16 = 0xffff << offset;
142 pub mod R {}
143 pub mod W {}
144 pub mod RW {}
145 }
146}
147#[doc = "Timer Channel Load Register"]
148pub mod LOAD0 {
149 #[doc = "Timer Load Register"]
150 pub mod LOAD {
151 pub const offset: u16 = 0;
152 pub const mask: u16 = 0xffff << offset;
153 pub mod R {}
154 pub mod W {}
155 pub mod RW {}
156 }
157}
158#[doc = "Timer Channel Hold Register"]
159pub mod HOLD0 {
160 #[doc = "This read/write register stores the counter's values of specific channels whenever any of the four counters within a module is read"]
161 pub mod HOLD {
162 pub const offset: u16 = 0;
163 pub const mask: u16 = 0xffff << offset;
164 pub mod R {}
165 pub mod W {}
166 pub mod RW {}
167 }
168}
169#[doc = "Timer Channel Counter Register"]
170pub mod CNTR0 {
171 #[doc = "This read/write register is the counter for the corresponding channel in a timer module."]
172 pub mod COUNTER {
173 pub const offset: u16 = 0;
174 pub const mask: u16 = 0xffff << offset;
175 pub mod R {}
176 pub mod W {}
177 pub mod RW {}
178 }
179}
180#[doc = "Timer Channel Control Register"]
181pub mod CTRL0 {
182 #[doc = "Output Mode"]
183 pub mod OUTMODE {
184 pub const offset: u16 = 0;
185 pub const mask: u16 = 0x07 << offset;
186 pub mod R {}
187 pub mod W {}
188 pub mod RW {
189 #[doc = "Asserted while counter is active"]
190 pub const OUTMODE_0: u16 = 0;
191 #[doc = "Clear OFLAG output on successful compare"]
192 pub const OUTMODE_1: u16 = 0x01;
193 #[doc = "Set OFLAG output on successful compare"]
194 pub const OUTMODE_2: u16 = 0x02;
195 #[doc = "Toggle OFLAG output on successful compare"]
196 pub const OUTMODE_3: u16 = 0x03;
197 #[doc = "Toggle OFLAG output using alternating compare registers"]
198 pub const OUTMODE_4: u16 = 0x04;
199 #[doc = "Set on compare, cleared on secondary source input edge"]
200 pub const OUTMODE_5: u16 = 0x05;
201 #[doc = "Set on compare, cleared on counter rollover"]
202 pub const OUTMODE_6: u16 = 0x06;
203 #[doc = "Enable gated clock output while counter is active"]
204 pub const OUTMODE_7: u16 = 0x07;
205 }
206 }
207 #[doc = "Co-Channel Initialization"]
208 pub mod COINIT {
209 pub const offset: u16 = 3;
210 pub const mask: u16 = 0x01 << offset;
211 pub mod R {}
212 pub mod W {}
213 pub mod RW {
214 #[doc = "Co-channel counter/timers cannot force a re-initialization of this counter/timer"]
215 pub const COINIT_0: u16 = 0;
216 #[doc = "Co-channel counter/timers may force a re-initialization of this counter/timer"]
217 pub const COINIT_1: u16 = 0x01;
218 }
219 }
220 #[doc = "Count Direction"]
221 pub mod DIR {
222 pub const offset: u16 = 4;
223 pub const mask: u16 = 0x01 << offset;
224 pub mod R {}
225 pub mod W {}
226 pub mod RW {
227 #[doc = "Count up."]
228 pub const DIR_0: u16 = 0;
229 #[doc = "Count down."]
230 pub const DIR_1: u16 = 0x01;
231 }
232 }
233 #[doc = "Count Length"]
234 pub mod LENGTH {
235 pub const offset: u16 = 5;
236 pub const mask: u16 = 0x01 << offset;
237 pub mod R {}
238 pub mod W {}
239 pub mod RW {
240 #[doc = "Count until roll over at $FFFF and continue from $0000."]
241 pub const LENGTH_0: u16 = 0;
242 #[doc = "Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on."]
243 pub const LENGTH_1: u16 = 0x01;
244 }
245 }
246 #[doc = "Count Once"]
247 pub mod ONCE {
248 pub const offset: u16 = 6;
249 pub const mask: u16 = 0x01 << offset;
250 pub mod R {}
251 pub mod W {}
252 pub mod RW {
253 #[doc = "Count repeatedly."]
254 pub const ONCE_0: u16 = 0;
255 #[doc = "Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops."]
256 pub const ONCE_1: u16 = 0x01;
257 }
258 }
259 #[doc = "Secondary Count Source"]
260 pub mod SCS {
261 pub const offset: u16 = 7;
262 pub const mask: u16 = 0x03 << offset;
263 pub mod R {}
264 pub mod W {}
265 pub mod RW {
266 #[doc = "Counter 0 input pin"]
267 pub const SCS_0: u16 = 0;
268 #[doc = "Counter 1 input pin"]
269 pub const SCS_1: u16 = 0x01;
270 #[doc = "Counter 2 input pin"]
271 pub const SCS_2: u16 = 0x02;
272 #[doc = "Counter 3 input pin"]
273 pub const SCS_3: u16 = 0x03;
274 }
275 }
276 #[doc = "Primary Count Source"]
277 pub mod PCS {
278 pub const offset: u16 = 9;
279 pub const mask: u16 = 0x0f << offset;
280 pub mod R {}
281 pub mod W {}
282 pub mod RW {
283 #[doc = "Counter 0 input pin"]
284 pub const PCS_0: u16 = 0;
285 #[doc = "Counter 1 input pin"]
286 pub const PCS_1: u16 = 0x01;
287 #[doc = "Counter 2 input pin"]
288 pub const PCS_2: u16 = 0x02;
289 #[doc = "Counter 3 input pin"]
290 pub const PCS_3: u16 = 0x03;
291 #[doc = "Counter 0 output"]
292 pub const PCS_4: u16 = 0x04;
293 #[doc = "Counter 1 output"]
294 pub const PCS_5: u16 = 0x05;
295 #[doc = "Counter 2 output"]
296 pub const PCS_6: u16 = 0x06;
297 #[doc = "Counter 3 output"]
298 pub const PCS_7: u16 = 0x07;
299 #[doc = "IP bus clock divide by 1 prescaler"]
300 pub const PCS_8: u16 = 0x08;
301 #[doc = "IP bus clock divide by 2 prescaler"]
302 pub const PCS_9: u16 = 0x09;
303 #[doc = "IP bus clock divide by 4 prescaler"]
304 pub const PCS_10: u16 = 0x0a;
305 #[doc = "IP bus clock divide by 8 prescaler"]
306 pub const PCS_11: u16 = 0x0b;
307 #[doc = "IP bus clock divide by 16 prescaler"]
308 pub const PCS_12: u16 = 0x0c;
309 #[doc = "IP bus clock divide by 32 prescaler"]
310 pub const PCS_13: u16 = 0x0d;
311 #[doc = "IP bus clock divide by 64 prescaler"]
312 pub const PCS_14: u16 = 0x0e;
313 #[doc = "IP bus clock divide by 128 prescaler"]
314 pub const PCS_15: u16 = 0x0f;
315 }
316 }
317 #[doc = "Count Mode"]
318 pub mod CM {
319 pub const offset: u16 = 13;
320 pub const mask: u16 = 0x07 << offset;
321 pub mod R {}
322 pub mod W {}
323 pub mod RW {
324 #[doc = "No operation"]
325 pub const CM_0: u16 = 0;
326 #[doc = "Count rising edges of primary sourceRising edges are counted only when SCTRL\\[IPS\\] = 0. Falling edges are counted when SCTRL\\[IPS\\] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL\\[IPS\\]."]
327 pub const CM_1: u16 = 0x01;
328 #[doc = "Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode."]
329 pub const CM_2: u16 = 0x02;
330 #[doc = "Count rising edges of primary source while secondary input high active"]
331 pub const CM_3: u16 = 0x03;
332 #[doc = "Quadrature count mode, uses primary and secondary sources"]
333 pub const CM_4: u16 = 0x04;
334 #[doc = "Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL\\[IPS\\] = 0. Falling edges are counted when SCTRL\\[IPS\\] = 1."]
335 pub const CM_5: u16 = 0x05;
336 #[doc = "Edge of secondary source triggers primary count until compare"]
337 pub const CM_6: u16 = 0x06;
338 #[doc = "Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs."]
339 pub const CM_7: u16 = 0x07;
340 }
341 }
342}
343#[doc = "Timer Channel Status and Control Register"]
344pub mod SCTRL0 {
345 #[doc = "Output Enable"]
346 pub mod OEN {
347 pub const offset: u16 = 0;
348 pub const mask: u16 = 0x01 << offset;
349 pub mod R {}
350 pub mod W {}
351 pub mod RW {
352 #[doc = "The external pin is configured as an input."]
353 pub const OEN_0: u16 = 0;
354 #[doc = "The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as their input see the driven value. The polarity of the signal is determined by OPS."]
355 pub const OEN_1: u16 = 0x01;
356 }
357 }
358 #[doc = "Output Polarity Select"]
359 pub mod OPS {
360 pub const offset: u16 = 1;
361 pub const mask: u16 = 0x01 << offset;
362 pub mod R {}
363 pub mod W {}
364 pub mod RW {
365 #[doc = "True polarity."]
366 pub const OPS_0: u16 = 0;
367 #[doc = "Inverted polarity."]
368 pub const OPS_1: u16 = 0x01;
369 }
370 }
371 #[doc = "Force OFLAG Output"]
372 pub mod FORCE {
373 pub const offset: u16 = 2;
374 pub const mask: u16 = 0x01 << offset;
375 pub mod R {}
376 pub mod W {}
377 pub mod RW {}
378 }
379 #[doc = "Forced OFLAG Value"]
380 pub mod VAL {
381 pub const offset: u16 = 3;
382 pub const mask: u16 = 0x01 << offset;
383 pub mod R {}
384 pub mod W {}
385 pub mod RW {}
386 }
387 #[doc = "Enable External OFLAG Force"]
388 pub mod EEOF {
389 pub const offset: u16 = 4;
390 pub const mask: u16 = 0x01 << offset;
391 pub mod R {}
392 pub mod W {}
393 pub mod RW {}
394 }
395 #[doc = "Master Mode"]
396 pub mod MSTR {
397 pub const offset: u16 = 5;
398 pub const mask: u16 = 0x01 << offset;
399 pub mod R {}
400 pub mod W {}
401 pub mod RW {}
402 }
403 #[doc = "Input Capture Mode"]
404 pub mod CAPTURE_MODE {
405 pub const offset: u16 = 6;
406 pub const mask: u16 = 0x03 << offset;
407 pub mod R {}
408 pub mod W {}
409 pub mod RW {
410 #[doc = "Capture function is disabled"]
411 pub const CAPTURE_MODE_0: u16 = 0;
412 #[doc = "Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input"]
413 pub const CAPTURE_MODE_1: u16 = 0x01;
414 #[doc = "Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input"]
415 pub const CAPTURE_MODE_2: u16 = 0x02;
416 #[doc = "Load capture register on both edges of input"]
417 pub const CAPTURE_MODE_3: u16 = 0x03;
418 }
419 }
420 #[doc = "External Input Signal"]
421 pub mod INPUT {
422 pub const offset: u16 = 8;
423 pub const mask: u16 = 0x01 << offset;
424 pub mod R {}
425 pub mod W {}
426 pub mod RW {}
427 }
428 #[doc = "Input Polarity Select"]
429 pub mod IPS {
430 pub const offset: u16 = 9;
431 pub const mask: u16 = 0x01 << offset;
432 pub mod R {}
433 pub mod W {}
434 pub mod RW {}
435 }
436 #[doc = "Input Edge Flag Interrupt Enable"]
437 pub mod IEFIE {
438 pub const offset: u16 = 10;
439 pub const mask: u16 = 0x01 << offset;
440 pub mod R {}
441 pub mod W {}
442 pub mod RW {}
443 }
444 #[doc = "Input Edge Flag"]
445 pub mod IEF {
446 pub const offset: u16 = 11;
447 pub const mask: u16 = 0x01 << offset;
448 pub mod R {}
449 pub mod W {}
450 pub mod RW {}
451 }
452 #[doc = "Timer Overflow Flag Interrupt Enable"]
453 pub mod TOFIE {
454 pub const offset: u16 = 12;
455 pub const mask: u16 = 0x01 << offset;
456 pub mod R {}
457 pub mod W {}
458 pub mod RW {}
459 }
460 #[doc = "Timer Overflow Flag"]
461 pub mod TOF {
462 pub const offset: u16 = 13;
463 pub const mask: u16 = 0x01 << offset;
464 pub mod R {}
465 pub mod W {}
466 pub mod RW {}
467 }
468 #[doc = "Timer Compare Flag Interrupt Enable"]
469 pub mod TCFIE {
470 pub const offset: u16 = 14;
471 pub const mask: u16 = 0x01 << offset;
472 pub mod R {}
473 pub mod W {}
474 pub mod RW {}
475 }
476 #[doc = "Timer Compare Flag"]
477 pub mod TCF {
478 pub const offset: u16 = 15;
479 pub const mask: u16 = 0x01 << offset;
480 pub mod R {}
481 pub mod W {}
482 pub mod RW {}
483 }
484}
485#[doc = "Timer Channel Comparator Load Register 1"]
486pub mod CMPLD10 {
487 #[doc = "This read/write register is the comparator 1 preload value for the COMP1 register for the corresponding channel in a timer module"]
488 pub mod COMPARATOR_LOAD_1 {
489 pub const offset: u16 = 0;
490 pub const mask: u16 = 0xffff << offset;
491 pub mod R {}
492 pub mod W {}
493 pub mod RW {}
494 }
495}
496#[doc = "Timer Channel Comparator Load Register 2"]
497pub mod CMPLD20 {
498 #[doc = "This read/write register is the comparator 2 preload value for the COMP2 register for the corresponding channel in a timer module"]
499 pub mod COMPARATOR_LOAD_2 {
500 pub const offset: u16 = 0;
501 pub const mask: u16 = 0xffff << offset;
502 pub mod R {}
503 pub mod W {}
504 pub mod RW {}
505 }
506}
507#[doc = "Timer Channel Comparator Status and Control Register"]
508pub mod CSCTRL0 {
509 #[doc = "Compare Load Control 1"]
510 pub mod CL1 {
511 pub const offset: u16 = 0;
512 pub const mask: u16 = 0x03 << offset;
513 pub mod R {}
514 pub mod W {}
515 pub mod RW {
516 #[doc = "Never preload"]
517 pub const CL1_0: u16 = 0;
518 #[doc = "Load upon successful compare with the value in COMP1"]
519 pub const CL1_1: u16 = 0x01;
520 #[doc = "Load upon successful compare with the value in COMP2"]
521 pub const CL1_2: u16 = 0x02;
522 }
523 }
524 #[doc = "Compare Load Control 2"]
525 pub mod CL2 {
526 pub const offset: u16 = 2;
527 pub const mask: u16 = 0x03 << offset;
528 pub mod R {}
529 pub mod W {}
530 pub mod RW {
531 #[doc = "Never preload"]
532 pub const CL2_0: u16 = 0;
533 #[doc = "Load upon successful compare with the value in COMP1"]
534 pub const CL2_1: u16 = 0x01;
535 #[doc = "Load upon successful compare with the value in COMP2"]
536 pub const CL2_2: u16 = 0x02;
537 }
538 }
539 #[doc = "Timer Compare 1 Interrupt Flag"]
540 pub mod TCF1 {
541 pub const offset: u16 = 4;
542 pub const mask: u16 = 0x01 << offset;
543 pub mod R {}
544 pub mod W {}
545 pub mod RW {}
546 }
547 #[doc = "Timer Compare 2 Interrupt Flag"]
548 pub mod TCF2 {
549 pub const offset: u16 = 5;
550 pub const mask: u16 = 0x01 << offset;
551 pub mod R {}
552 pub mod W {}
553 pub mod RW {}
554 }
555 #[doc = "Timer Compare 1 Interrupt Enable"]
556 pub mod TCF1EN {
557 pub const offset: u16 = 6;
558 pub const mask: u16 = 0x01 << offset;
559 pub mod R {}
560 pub mod W {}
561 pub mod RW {}
562 }
563 #[doc = "Timer Compare 2 Interrupt Enable"]
564 pub mod TCF2EN {
565 pub const offset: u16 = 7;
566 pub const mask: u16 = 0x01 << offset;
567 pub mod R {}
568 pub mod W {}
569 pub mod RW {}
570 }
571 #[doc = "Counting Direction Indicator"]
572 pub mod UP {
573 pub const offset: u16 = 9;
574 pub const mask: u16 = 0x01 << offset;
575 pub mod R {}
576 pub mod W {}
577 pub mod RW {
578 #[doc = "The last count was in the DOWN direction."]
579 pub const UP_0: u16 = 0;
580 #[doc = "The last count was in the UP direction."]
581 pub const UP_1: u16 = 0x01;
582 }
583 }
584 #[doc = "Triggered Count Initialization Control"]
585 pub mod TCI {
586 pub const offset: u16 = 10;
587 pub const mask: u16 = 0x01 << offset;
588 pub mod R {}
589 pub mod W {}
590 pub mod RW {
591 #[doc = "Stop counter upon receiving a second trigger event while still counting from the first trigger event."]
592 pub const TCI_0: u16 = 0;
593 #[doc = "Reload the counter upon receiving a second trigger event while still counting from the first trigger event."]
594 pub const TCI_1: u16 = 0x01;
595 }
596 }
597 #[doc = "Reload on Capture"]
598 pub mod ROC {
599 pub const offset: u16 = 11;
600 pub const mask: u16 = 0x01 << offset;
601 pub mod R {}
602 pub mod W {}
603 pub mod RW {
604 #[doc = "Do not reload the counter on a capture event."]
605 pub const ROC_0: u16 = 0;
606 #[doc = "Reload the counter on a capture event."]
607 pub const ROC_1: u16 = 0x01;
608 }
609 }
610 #[doc = "Alternative Load Enable"]
611 pub mod ALT_LOAD {
612 pub const offset: u16 = 12;
613 pub const mask: u16 = 0x01 << offset;
614 pub mod R {}
615 pub mod W {}
616 pub mod RW {
617 #[doc = "Counter can be re-initialized only with the LOAD register."]
618 pub const ALT_LOAD_0: u16 = 0;
619 #[doc = "Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction."]
620 pub const ALT_LOAD_1: u16 = 0x01;
621 }
622 }
623 #[doc = "Fault Enable"]
624 pub mod FAULT {
625 pub const offset: u16 = 13;
626 pub const mask: u16 = 0x01 << offset;
627 pub mod R {}
628 pub mod W {}
629 pub mod RW {
630 #[doc = "Fault function disabled."]
631 pub const FAULT_0: u16 = 0;
632 #[doc = "Fault function enabled."]
633 pub const FAULT_1: u16 = 0x01;
634 }
635 }
636 #[doc = "Debug Actions Enable"]
637 pub mod DBG_EN {
638 pub const offset: u16 = 14;
639 pub const mask: u16 = 0x03 << offset;
640 pub mod R {}
641 pub mod W {}
642 pub mod RW {
643 #[doc = "Continue with normal operation during debug mode. (default)"]
644 pub const DBG_EN_0: u16 = 0;
645 #[doc = "Halt TMR counter during debug mode."]
646 pub const DBG_EN_1: u16 = 0x01;
647 #[doc = "Force TMR output to logic 0 (prior to consideration of SCTRL\\[OPS\\])."]
648 pub const DBG_EN_2: u16 = 0x02;
649 #[doc = "Both halt counter and force output to 0 during debug mode."]
650 pub const DBG_EN_3: u16 = 0x03;
651 }
652 }
653}
654#[doc = "Timer Channel Input Filter Register"]
655pub mod FILT0 {
656 #[doc = "Input Filter Sample Period"]
657 pub mod FILT_PER {
658 pub const offset: u16 = 0;
659 pub const mask: u16 = 0xff << offset;
660 pub mod R {}
661 pub mod W {}
662 pub mod RW {}
663 }
664 #[doc = "Input Filter Sample Count"]
665 pub mod FILT_CNT {
666 pub const offset: u16 = 8;
667 pub const mask: u16 = 0x07 << offset;
668 pub mod R {}
669 pub mod W {}
670 pub mod RW {}
671 }
672}
673#[doc = "Timer Channel DMA Enable Register"]
674pub mod DMA0 {
675 #[doc = "Input Edge Flag DMA Enable"]
676 pub mod IEFDE {
677 pub const offset: u16 = 0;
678 pub const mask: u16 = 0x01 << offset;
679 pub mod R {}
680 pub mod W {}
681 pub mod RW {}
682 }
683 #[doc = "Comparator Preload Register 1 DMA Enable"]
684 pub mod CMPLD1DE {
685 pub const offset: u16 = 1;
686 pub const mask: u16 = 0x01 << offset;
687 pub mod R {}
688 pub mod W {}
689 pub mod RW {}
690 }
691 #[doc = "Comparator Preload Register 2 DMA Enable"]
692 pub mod CMPLD2DE {
693 pub const offset: u16 = 2;
694 pub const mask: u16 = 0x01 << offset;
695 pub mod R {}
696 pub mod W {}
697 pub mod RW {}
698 }
699}
700#[doc = "Timer Channel Enable Register"]
701pub mod ENBL {
702 #[doc = "Timer Channel Enable"]
703 pub mod ENBL {
704 pub const offset: u16 = 0;
705 pub const mask: u16 = 0x0f << offset;
706 pub mod R {}
707 pub mod W {}
708 pub mod RW {
709 #[doc = "Timer channel is disabled."]
710 pub const ENBL_0: u16 = 0;
711 #[doc = "Timer channel is enabled. (default)"]
712 pub const ENBL_1: u16 = 0x01;
713 }
714 }
715}
716#[doc = "Timer Channel Compare Register 1"]
717pub mod COMP11 {
718 #[doc = "Comparison Value 1"]
719 pub mod COMPARISON_1 {
720 pub const offset: u16 = 0;
721 pub const mask: u16 = 0xffff << offset;
722 pub mod R {}
723 pub mod W {}
724 pub mod RW {}
725 }
726}
727#[doc = "Timer Channel Compare Register 2"]
728pub mod COMP21 {
729 #[doc = "Comparison Value 2"]
730 pub mod COMPARISON_2 {
731 pub const offset: u16 = 0;
732 pub const mask: u16 = 0xffff << offset;
733 pub mod R {}
734 pub mod W {}
735 pub mod RW {}
736 }
737}
738#[doc = "Timer Channel Capture Register"]
739pub mod CAPT1 {
740 #[doc = "Capture Value"]
741 pub mod CAPTURE {
742 pub const offset: u16 = 0;
743 pub const mask: u16 = 0xffff << offset;
744 pub mod R {}
745 pub mod W {}
746 pub mod RW {}
747 }
748}
749#[doc = "Timer Channel Load Register"]
750pub mod LOAD1 {
751 #[doc = "Timer Load Register"]
752 pub mod LOAD {
753 pub const offset: u16 = 0;
754 pub const mask: u16 = 0xffff << offset;
755 pub mod R {}
756 pub mod W {}
757 pub mod RW {}
758 }
759}
760#[doc = "Timer Channel Hold Register"]
761pub mod HOLD1 {
762 #[doc = "This read/write register stores the counter's values of specific channels whenever any of the four counters within a module is read"]
763 pub mod HOLD {
764 pub const offset: u16 = 0;
765 pub const mask: u16 = 0xffff << offset;
766 pub mod R {}
767 pub mod W {}
768 pub mod RW {}
769 }
770}
771#[doc = "Timer Channel Counter Register"]
772pub mod CNTR1 {
773 #[doc = "This read/write register is the counter for the corresponding channel in a timer module."]
774 pub mod COUNTER {
775 pub const offset: u16 = 0;
776 pub const mask: u16 = 0xffff << offset;
777 pub mod R {}
778 pub mod W {}
779 pub mod RW {}
780 }
781}
782#[doc = "Timer Channel Control Register"]
783pub mod CTRL1 {
784 #[doc = "Output Mode"]
785 pub mod OUTMODE {
786 pub const offset: u16 = 0;
787 pub const mask: u16 = 0x07 << offset;
788 pub mod R {}
789 pub mod W {}
790 pub mod RW {
791 #[doc = "Asserted while counter is active"]
792 pub const OUTMODE_0: u16 = 0;
793 #[doc = "Clear OFLAG output on successful compare"]
794 pub const OUTMODE_1: u16 = 0x01;
795 #[doc = "Set OFLAG output on successful compare"]
796 pub const OUTMODE_2: u16 = 0x02;
797 #[doc = "Toggle OFLAG output on successful compare"]
798 pub const OUTMODE_3: u16 = 0x03;
799 #[doc = "Toggle OFLAG output using alternating compare registers"]
800 pub const OUTMODE_4: u16 = 0x04;
801 #[doc = "Set on compare, cleared on secondary source input edge"]
802 pub const OUTMODE_5: u16 = 0x05;
803 #[doc = "Set on compare, cleared on counter rollover"]
804 pub const OUTMODE_6: u16 = 0x06;
805 #[doc = "Enable gated clock output while counter is active"]
806 pub const OUTMODE_7: u16 = 0x07;
807 }
808 }
809 #[doc = "Co-Channel Initialization"]
810 pub mod COINIT {
811 pub const offset: u16 = 3;
812 pub const mask: u16 = 0x01 << offset;
813 pub mod R {}
814 pub mod W {}
815 pub mod RW {
816 #[doc = "Co-channel counter/timers cannot force a re-initialization of this counter/timer"]
817 pub const COINIT_0: u16 = 0;
818 #[doc = "Co-channel counter/timers may force a re-initialization of this counter/timer"]
819 pub const COINIT_1: u16 = 0x01;
820 }
821 }
822 #[doc = "Count Direction"]
823 pub mod DIR {
824 pub const offset: u16 = 4;
825 pub const mask: u16 = 0x01 << offset;
826 pub mod R {}
827 pub mod W {}
828 pub mod RW {
829 #[doc = "Count up."]
830 pub const DIR_0: u16 = 0;
831 #[doc = "Count down."]
832 pub const DIR_1: u16 = 0x01;
833 }
834 }
835 #[doc = "Count Length"]
836 pub mod LENGTH {
837 pub const offset: u16 = 5;
838 pub const mask: u16 = 0x01 << offset;
839 pub mod R {}
840 pub mod W {}
841 pub mod RW {
842 #[doc = "Count until roll over at $FFFF and continue from $0000."]
843 pub const LENGTH_0: u16 = 0;
844 #[doc = "Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on."]
845 pub const LENGTH_1: u16 = 0x01;
846 }
847 }
848 #[doc = "Count Once"]
849 pub mod ONCE {
850 pub const offset: u16 = 6;
851 pub const mask: u16 = 0x01 << offset;
852 pub mod R {}
853 pub mod W {}
854 pub mod RW {
855 #[doc = "Count repeatedly."]
856 pub const ONCE_0: u16 = 0;
857 #[doc = "Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops."]
858 pub const ONCE_1: u16 = 0x01;
859 }
860 }
861 #[doc = "Secondary Count Source"]
862 pub mod SCS {
863 pub const offset: u16 = 7;
864 pub const mask: u16 = 0x03 << offset;
865 pub mod R {}
866 pub mod W {}
867 pub mod RW {
868 #[doc = "Counter 0 input pin"]
869 pub const SCS_0: u16 = 0;
870 #[doc = "Counter 1 input pin"]
871 pub const SCS_1: u16 = 0x01;
872 #[doc = "Counter 2 input pin"]
873 pub const SCS_2: u16 = 0x02;
874 #[doc = "Counter 3 input pin"]
875 pub const SCS_3: u16 = 0x03;
876 }
877 }
878 #[doc = "Primary Count Source"]
879 pub mod PCS {
880 pub const offset: u16 = 9;
881 pub const mask: u16 = 0x0f << offset;
882 pub mod R {}
883 pub mod W {}
884 pub mod RW {
885 #[doc = "Counter 0 input pin"]
886 pub const PCS_0: u16 = 0;
887 #[doc = "Counter 1 input pin"]
888 pub const PCS_1: u16 = 0x01;
889 #[doc = "Counter 2 input pin"]
890 pub const PCS_2: u16 = 0x02;
891 #[doc = "Counter 3 input pin"]
892 pub const PCS_3: u16 = 0x03;
893 #[doc = "Counter 0 output"]
894 pub const PCS_4: u16 = 0x04;
895 #[doc = "Counter 1 output"]
896 pub const PCS_5: u16 = 0x05;
897 #[doc = "Counter 2 output"]
898 pub const PCS_6: u16 = 0x06;
899 #[doc = "Counter 3 output"]
900 pub const PCS_7: u16 = 0x07;
901 #[doc = "IP bus clock divide by 1 prescaler"]
902 pub const PCS_8: u16 = 0x08;
903 #[doc = "IP bus clock divide by 2 prescaler"]
904 pub const PCS_9: u16 = 0x09;
905 #[doc = "IP bus clock divide by 4 prescaler"]
906 pub const PCS_10: u16 = 0x0a;
907 #[doc = "IP bus clock divide by 8 prescaler"]
908 pub const PCS_11: u16 = 0x0b;
909 #[doc = "IP bus clock divide by 16 prescaler"]
910 pub const PCS_12: u16 = 0x0c;
911 #[doc = "IP bus clock divide by 32 prescaler"]
912 pub const PCS_13: u16 = 0x0d;
913 #[doc = "IP bus clock divide by 64 prescaler"]
914 pub const PCS_14: u16 = 0x0e;
915 #[doc = "IP bus clock divide by 128 prescaler"]
916 pub const PCS_15: u16 = 0x0f;
917 }
918 }
919 #[doc = "Count Mode"]
920 pub mod CM {
921 pub const offset: u16 = 13;
922 pub const mask: u16 = 0x07 << offset;
923 pub mod R {}
924 pub mod W {}
925 pub mod RW {
926 #[doc = "No operation"]
927 pub const CM_0: u16 = 0;
928 #[doc = "Count rising edges of primary sourceRising edges are counted only when SCTRL\\[IPS\\] = 0. Falling edges are counted when SCTRL\\[IPS\\] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL\\[IPS\\]."]
929 pub const CM_1: u16 = 0x01;
930 #[doc = "Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode."]
931 pub const CM_2: u16 = 0x02;
932 #[doc = "Count rising edges of primary source while secondary input high active"]
933 pub const CM_3: u16 = 0x03;
934 #[doc = "Quadrature count mode, uses primary and secondary sources"]
935 pub const CM_4: u16 = 0x04;
936 #[doc = "Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL\\[IPS\\] = 0. Falling edges are counted when SCTRL\\[IPS\\] = 1."]
937 pub const CM_5: u16 = 0x05;
938 #[doc = "Edge of secondary source triggers primary count until compare"]
939 pub const CM_6: u16 = 0x06;
940 #[doc = "Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs."]
941 pub const CM_7: u16 = 0x07;
942 }
943 }
944}
945#[doc = "Timer Channel Status and Control Register"]
946pub mod SCTRL1 {
947 #[doc = "Output Enable"]
948 pub mod OEN {
949 pub const offset: u16 = 0;
950 pub const mask: u16 = 0x01 << offset;
951 pub mod R {}
952 pub mod W {}
953 pub mod RW {
954 #[doc = "The external pin is configured as an input."]
955 pub const OEN_0: u16 = 0;
956 #[doc = "The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as their input see the driven value. The polarity of the signal is determined by OPS."]
957 pub const OEN_1: u16 = 0x01;
958 }
959 }
960 #[doc = "Output Polarity Select"]
961 pub mod OPS {
962 pub const offset: u16 = 1;
963 pub const mask: u16 = 0x01 << offset;
964 pub mod R {}
965 pub mod W {}
966 pub mod RW {
967 #[doc = "True polarity."]
968 pub const OPS_0: u16 = 0;
969 #[doc = "Inverted polarity."]
970 pub const OPS_1: u16 = 0x01;
971 }
972 }
973 #[doc = "Force OFLAG Output"]
974 pub mod FORCE {
975 pub const offset: u16 = 2;
976 pub const mask: u16 = 0x01 << offset;
977 pub mod R {}
978 pub mod W {}
979 pub mod RW {}
980 }
981 #[doc = "Forced OFLAG Value"]
982 pub mod VAL {
983 pub const offset: u16 = 3;
984 pub const mask: u16 = 0x01 << offset;
985 pub mod R {}
986 pub mod W {}
987 pub mod RW {}
988 }
989 #[doc = "Enable External OFLAG Force"]
990 pub mod EEOF {
991 pub const offset: u16 = 4;
992 pub const mask: u16 = 0x01 << offset;
993 pub mod R {}
994 pub mod W {}
995 pub mod RW {}
996 }
997 #[doc = "Master Mode"]
998 pub mod MSTR {
999 pub const offset: u16 = 5;
1000 pub const mask: u16 = 0x01 << offset;
1001 pub mod R {}
1002 pub mod W {}
1003 pub mod RW {}
1004 }
1005 #[doc = "Input Capture Mode"]
1006 pub mod CAPTURE_MODE {
1007 pub const offset: u16 = 6;
1008 pub const mask: u16 = 0x03 << offset;
1009 pub mod R {}
1010 pub mod W {}
1011 pub mod RW {
1012 #[doc = "Capture function is disabled"]
1013 pub const CAPTURE_MODE_0: u16 = 0;
1014 #[doc = "Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input"]
1015 pub const CAPTURE_MODE_1: u16 = 0x01;
1016 #[doc = "Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input"]
1017 pub const CAPTURE_MODE_2: u16 = 0x02;
1018 #[doc = "Load capture register on both edges of input"]
1019 pub const CAPTURE_MODE_3: u16 = 0x03;
1020 }
1021 }
1022 #[doc = "External Input Signal"]
1023 pub mod INPUT {
1024 pub const offset: u16 = 8;
1025 pub const mask: u16 = 0x01 << offset;
1026 pub mod R {}
1027 pub mod W {}
1028 pub mod RW {}
1029 }
1030 #[doc = "Input Polarity Select"]
1031 pub mod IPS {
1032 pub const offset: u16 = 9;
1033 pub const mask: u16 = 0x01 << offset;
1034 pub mod R {}
1035 pub mod W {}
1036 pub mod RW {}
1037 }
1038 #[doc = "Input Edge Flag Interrupt Enable"]
1039 pub mod IEFIE {
1040 pub const offset: u16 = 10;
1041 pub const mask: u16 = 0x01 << offset;
1042 pub mod R {}
1043 pub mod W {}
1044 pub mod RW {}
1045 }
1046 #[doc = "Input Edge Flag"]
1047 pub mod IEF {
1048 pub const offset: u16 = 11;
1049 pub const mask: u16 = 0x01 << offset;
1050 pub mod R {}
1051 pub mod W {}
1052 pub mod RW {}
1053 }
1054 #[doc = "Timer Overflow Flag Interrupt Enable"]
1055 pub mod TOFIE {
1056 pub const offset: u16 = 12;
1057 pub const mask: u16 = 0x01 << offset;
1058 pub mod R {}
1059 pub mod W {}
1060 pub mod RW {}
1061 }
1062 #[doc = "Timer Overflow Flag"]
1063 pub mod TOF {
1064 pub const offset: u16 = 13;
1065 pub const mask: u16 = 0x01 << offset;
1066 pub mod R {}
1067 pub mod W {}
1068 pub mod RW {}
1069 }
1070 #[doc = "Timer Compare Flag Interrupt Enable"]
1071 pub mod TCFIE {
1072 pub const offset: u16 = 14;
1073 pub const mask: u16 = 0x01 << offset;
1074 pub mod R {}
1075 pub mod W {}
1076 pub mod RW {}
1077 }
1078 #[doc = "Timer Compare Flag"]
1079 pub mod TCF {
1080 pub const offset: u16 = 15;
1081 pub const mask: u16 = 0x01 << offset;
1082 pub mod R {}
1083 pub mod W {}
1084 pub mod RW {}
1085 }
1086}
1087#[doc = "Timer Channel Comparator Load Register 1"]
1088pub mod CMPLD11 {
1089 #[doc = "This read/write register is the comparator 1 preload value for the COMP1 register for the corresponding channel in a timer module"]
1090 pub mod COMPARATOR_LOAD_1 {
1091 pub const offset: u16 = 0;
1092 pub const mask: u16 = 0xffff << offset;
1093 pub mod R {}
1094 pub mod W {}
1095 pub mod RW {}
1096 }
1097}
1098#[doc = "Timer Channel Comparator Load Register 2"]
1099pub mod CMPLD21 {
1100 #[doc = "This read/write register is the comparator 2 preload value for the COMP2 register for the corresponding channel in a timer module"]
1101 pub mod COMPARATOR_LOAD_2 {
1102 pub const offset: u16 = 0;
1103 pub const mask: u16 = 0xffff << offset;
1104 pub mod R {}
1105 pub mod W {}
1106 pub mod RW {}
1107 }
1108}
1109#[doc = "Timer Channel Comparator Status and Control Register"]
1110pub mod CSCTRL1 {
1111 #[doc = "Compare Load Control 1"]
1112 pub mod CL1 {
1113 pub const offset: u16 = 0;
1114 pub const mask: u16 = 0x03 << offset;
1115 pub mod R {}
1116 pub mod W {}
1117 pub mod RW {
1118 #[doc = "Never preload"]
1119 pub const CL1_0: u16 = 0;
1120 #[doc = "Load upon successful compare with the value in COMP1"]
1121 pub const CL1_1: u16 = 0x01;
1122 #[doc = "Load upon successful compare with the value in COMP2"]
1123 pub const CL1_2: u16 = 0x02;
1124 }
1125 }
1126 #[doc = "Compare Load Control 2"]
1127 pub mod CL2 {
1128 pub const offset: u16 = 2;
1129 pub const mask: u16 = 0x03 << offset;
1130 pub mod R {}
1131 pub mod W {}
1132 pub mod RW {
1133 #[doc = "Never preload"]
1134 pub const CL2_0: u16 = 0;
1135 #[doc = "Load upon successful compare with the value in COMP1"]
1136 pub const CL2_1: u16 = 0x01;
1137 #[doc = "Load upon successful compare with the value in COMP2"]
1138 pub const CL2_2: u16 = 0x02;
1139 }
1140 }
1141 #[doc = "Timer Compare 1 Interrupt Flag"]
1142 pub mod TCF1 {
1143 pub const offset: u16 = 4;
1144 pub const mask: u16 = 0x01 << offset;
1145 pub mod R {}
1146 pub mod W {}
1147 pub mod RW {}
1148 }
1149 #[doc = "Timer Compare 2 Interrupt Flag"]
1150 pub mod TCF2 {
1151 pub const offset: u16 = 5;
1152 pub const mask: u16 = 0x01 << offset;
1153 pub mod R {}
1154 pub mod W {}
1155 pub mod RW {}
1156 }
1157 #[doc = "Timer Compare 1 Interrupt Enable"]
1158 pub mod TCF1EN {
1159 pub const offset: u16 = 6;
1160 pub const mask: u16 = 0x01 << offset;
1161 pub mod R {}
1162 pub mod W {}
1163 pub mod RW {}
1164 }
1165 #[doc = "Timer Compare 2 Interrupt Enable"]
1166 pub mod TCF2EN {
1167 pub const offset: u16 = 7;
1168 pub const mask: u16 = 0x01 << offset;
1169 pub mod R {}
1170 pub mod W {}
1171 pub mod RW {}
1172 }
1173 #[doc = "Counting Direction Indicator"]
1174 pub mod UP {
1175 pub const offset: u16 = 9;
1176 pub const mask: u16 = 0x01 << offset;
1177 pub mod R {}
1178 pub mod W {}
1179 pub mod RW {
1180 #[doc = "The last count was in the DOWN direction."]
1181 pub const UP_0: u16 = 0;
1182 #[doc = "The last count was in the UP direction."]
1183 pub const UP_1: u16 = 0x01;
1184 }
1185 }
1186 #[doc = "Triggered Count Initialization Control"]
1187 pub mod TCI {
1188 pub const offset: u16 = 10;
1189 pub const mask: u16 = 0x01 << offset;
1190 pub mod R {}
1191 pub mod W {}
1192 pub mod RW {
1193 #[doc = "Stop counter upon receiving a second trigger event while still counting from the first trigger event."]
1194 pub const TCI_0: u16 = 0;
1195 #[doc = "Reload the counter upon receiving a second trigger event while still counting from the first trigger event."]
1196 pub const TCI_1: u16 = 0x01;
1197 }
1198 }
1199 #[doc = "Reload on Capture"]
1200 pub mod ROC {
1201 pub const offset: u16 = 11;
1202 pub const mask: u16 = 0x01 << offset;
1203 pub mod R {}
1204 pub mod W {}
1205 pub mod RW {
1206 #[doc = "Do not reload the counter on a capture event."]
1207 pub const ROC_0: u16 = 0;
1208 #[doc = "Reload the counter on a capture event."]
1209 pub const ROC_1: u16 = 0x01;
1210 }
1211 }
1212 #[doc = "Alternative Load Enable"]
1213 pub mod ALT_LOAD {
1214 pub const offset: u16 = 12;
1215 pub const mask: u16 = 0x01 << offset;
1216 pub mod R {}
1217 pub mod W {}
1218 pub mod RW {
1219 #[doc = "Counter can be re-initialized only with the LOAD register."]
1220 pub const ALT_LOAD_0: u16 = 0;
1221 #[doc = "Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction."]
1222 pub const ALT_LOAD_1: u16 = 0x01;
1223 }
1224 }
1225 #[doc = "Fault Enable"]
1226 pub mod FAULT {
1227 pub const offset: u16 = 13;
1228 pub const mask: u16 = 0x01 << offset;
1229 pub mod R {}
1230 pub mod W {}
1231 pub mod RW {
1232 #[doc = "Fault function disabled."]
1233 pub const FAULT_0: u16 = 0;
1234 #[doc = "Fault function enabled."]
1235 pub const FAULT_1: u16 = 0x01;
1236 }
1237 }
1238 #[doc = "Debug Actions Enable"]
1239 pub mod DBG_EN {
1240 pub const offset: u16 = 14;
1241 pub const mask: u16 = 0x03 << offset;
1242 pub mod R {}
1243 pub mod W {}
1244 pub mod RW {
1245 #[doc = "Continue with normal operation during debug mode. (default)"]
1246 pub const DBG_EN_0: u16 = 0;
1247 #[doc = "Halt TMR counter during debug mode."]
1248 pub const DBG_EN_1: u16 = 0x01;
1249 #[doc = "Force TMR output to logic 0 (prior to consideration of SCTRL\\[OPS\\])."]
1250 pub const DBG_EN_2: u16 = 0x02;
1251 #[doc = "Both halt counter and force output to 0 during debug mode."]
1252 pub const DBG_EN_3: u16 = 0x03;
1253 }
1254 }
1255}
1256#[doc = "Timer Channel Input Filter Register"]
1257pub mod FILT1 {
1258 #[doc = "Input Filter Sample Period"]
1259 pub mod FILT_PER {
1260 pub const offset: u16 = 0;
1261 pub const mask: u16 = 0xff << offset;
1262 pub mod R {}
1263 pub mod W {}
1264 pub mod RW {}
1265 }
1266 #[doc = "Input Filter Sample Count"]
1267 pub mod FILT_CNT {
1268 pub const offset: u16 = 8;
1269 pub const mask: u16 = 0x07 << offset;
1270 pub mod R {}
1271 pub mod W {}
1272 pub mod RW {}
1273 }
1274}
1275#[doc = "Timer Channel DMA Enable Register"]
1276pub mod DMA1 {
1277 #[doc = "Input Edge Flag DMA Enable"]
1278 pub mod IEFDE {
1279 pub const offset: u16 = 0;
1280 pub const mask: u16 = 0x01 << offset;
1281 pub mod R {}
1282 pub mod W {}
1283 pub mod RW {}
1284 }
1285 #[doc = "Comparator Preload Register 1 DMA Enable"]
1286 pub mod CMPLD1DE {
1287 pub const offset: u16 = 1;
1288 pub const mask: u16 = 0x01 << offset;
1289 pub mod R {}
1290 pub mod W {}
1291 pub mod RW {}
1292 }
1293 #[doc = "Comparator Preload Register 2 DMA Enable"]
1294 pub mod CMPLD2DE {
1295 pub const offset: u16 = 2;
1296 pub const mask: u16 = 0x01 << offset;
1297 pub mod R {}
1298 pub mod W {}
1299 pub mod RW {}
1300 }
1301}
1302#[doc = "Timer Channel Compare Register 1"]
1303pub mod COMP12 {
1304 #[doc = "Comparison Value 1"]
1305 pub mod COMPARISON_1 {
1306 pub const offset: u16 = 0;
1307 pub const mask: u16 = 0xffff << offset;
1308 pub mod R {}
1309 pub mod W {}
1310 pub mod RW {}
1311 }
1312}
1313#[doc = "Timer Channel Compare Register 2"]
1314pub mod COMP22 {
1315 #[doc = "Comparison Value 2"]
1316 pub mod COMPARISON_2 {
1317 pub const offset: u16 = 0;
1318 pub const mask: u16 = 0xffff << offset;
1319 pub mod R {}
1320 pub mod W {}
1321 pub mod RW {}
1322 }
1323}
1324#[doc = "Timer Channel Capture Register"]
1325pub mod CAPT2 {
1326 #[doc = "Capture Value"]
1327 pub mod CAPTURE {
1328 pub const offset: u16 = 0;
1329 pub const mask: u16 = 0xffff << offset;
1330 pub mod R {}
1331 pub mod W {}
1332 pub mod RW {}
1333 }
1334}
1335#[doc = "Timer Channel Load Register"]
1336pub mod LOAD2 {
1337 #[doc = "Timer Load Register"]
1338 pub mod LOAD {
1339 pub const offset: u16 = 0;
1340 pub const mask: u16 = 0xffff << offset;
1341 pub mod R {}
1342 pub mod W {}
1343 pub mod RW {}
1344 }
1345}
1346#[doc = "Timer Channel Hold Register"]
1347pub mod HOLD2 {
1348 #[doc = "This read/write register stores the counter's values of specific channels whenever any of the four counters within a module is read"]
1349 pub mod HOLD {
1350 pub const offset: u16 = 0;
1351 pub const mask: u16 = 0xffff << offset;
1352 pub mod R {}
1353 pub mod W {}
1354 pub mod RW {}
1355 }
1356}
1357#[doc = "Timer Channel Counter Register"]
1358pub mod CNTR2 {
1359 #[doc = "This read/write register is the counter for the corresponding channel in a timer module."]
1360 pub mod COUNTER {
1361 pub const offset: u16 = 0;
1362 pub const mask: u16 = 0xffff << offset;
1363 pub mod R {}
1364 pub mod W {}
1365 pub mod RW {}
1366 }
1367}
1368#[doc = "Timer Channel Control Register"]
1369pub mod CTRL2 {
1370 #[doc = "Output Mode"]
1371 pub mod OUTMODE {
1372 pub const offset: u16 = 0;
1373 pub const mask: u16 = 0x07 << offset;
1374 pub mod R {}
1375 pub mod W {}
1376 pub mod RW {
1377 #[doc = "Asserted while counter is active"]
1378 pub const OUTMODE_0: u16 = 0;
1379 #[doc = "Clear OFLAG output on successful compare"]
1380 pub const OUTMODE_1: u16 = 0x01;
1381 #[doc = "Set OFLAG output on successful compare"]
1382 pub const OUTMODE_2: u16 = 0x02;
1383 #[doc = "Toggle OFLAG output on successful compare"]
1384 pub const OUTMODE_3: u16 = 0x03;
1385 #[doc = "Toggle OFLAG output using alternating compare registers"]
1386 pub const OUTMODE_4: u16 = 0x04;
1387 #[doc = "Set on compare, cleared on secondary source input edge"]
1388 pub const OUTMODE_5: u16 = 0x05;
1389 #[doc = "Set on compare, cleared on counter rollover"]
1390 pub const OUTMODE_6: u16 = 0x06;
1391 #[doc = "Enable gated clock output while counter is active"]
1392 pub const OUTMODE_7: u16 = 0x07;
1393 }
1394 }
1395 #[doc = "Co-Channel Initialization"]
1396 pub mod COINIT {
1397 pub const offset: u16 = 3;
1398 pub const mask: u16 = 0x01 << offset;
1399 pub mod R {}
1400 pub mod W {}
1401 pub mod RW {
1402 #[doc = "Co-channel counter/timers cannot force a re-initialization of this counter/timer"]
1403 pub const COINIT_0: u16 = 0;
1404 #[doc = "Co-channel counter/timers may force a re-initialization of this counter/timer"]
1405 pub const COINIT_1: u16 = 0x01;
1406 }
1407 }
1408 #[doc = "Count Direction"]
1409 pub mod DIR {
1410 pub const offset: u16 = 4;
1411 pub const mask: u16 = 0x01 << offset;
1412 pub mod R {}
1413 pub mod W {}
1414 pub mod RW {
1415 #[doc = "Count up."]
1416 pub const DIR_0: u16 = 0;
1417 #[doc = "Count down."]
1418 pub const DIR_1: u16 = 0x01;
1419 }
1420 }
1421 #[doc = "Count Length"]
1422 pub mod LENGTH {
1423 pub const offset: u16 = 5;
1424 pub const mask: u16 = 0x01 << offset;
1425 pub mod R {}
1426 pub mod W {}
1427 pub mod RW {
1428 #[doc = "Count until roll over at $FFFF and continue from $0000."]
1429 pub const LENGTH_0: u16 = 0;
1430 #[doc = "Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on."]
1431 pub const LENGTH_1: u16 = 0x01;
1432 }
1433 }
1434 #[doc = "Count Once"]
1435 pub mod ONCE {
1436 pub const offset: u16 = 6;
1437 pub const mask: u16 = 0x01 << offset;
1438 pub mod R {}
1439 pub mod W {}
1440 pub mod RW {
1441 #[doc = "Count repeatedly."]
1442 pub const ONCE_0: u16 = 0;
1443 #[doc = "Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops."]
1444 pub const ONCE_1: u16 = 0x01;
1445 }
1446 }
1447 #[doc = "Secondary Count Source"]
1448 pub mod SCS {
1449 pub const offset: u16 = 7;
1450 pub const mask: u16 = 0x03 << offset;
1451 pub mod R {}
1452 pub mod W {}
1453 pub mod RW {
1454 #[doc = "Counter 0 input pin"]
1455 pub const SCS_0: u16 = 0;
1456 #[doc = "Counter 1 input pin"]
1457 pub const SCS_1: u16 = 0x01;
1458 #[doc = "Counter 2 input pin"]
1459 pub const SCS_2: u16 = 0x02;
1460 #[doc = "Counter 3 input pin"]
1461 pub const SCS_3: u16 = 0x03;
1462 }
1463 }
1464 #[doc = "Primary Count Source"]
1465 pub mod PCS {
1466 pub const offset: u16 = 9;
1467 pub const mask: u16 = 0x0f << offset;
1468 pub mod R {}
1469 pub mod W {}
1470 pub mod RW {
1471 #[doc = "Counter 0 input pin"]
1472 pub const PCS_0: u16 = 0;
1473 #[doc = "Counter 1 input pin"]
1474 pub const PCS_1: u16 = 0x01;
1475 #[doc = "Counter 2 input pin"]
1476 pub const PCS_2: u16 = 0x02;
1477 #[doc = "Counter 3 input pin"]
1478 pub const PCS_3: u16 = 0x03;
1479 #[doc = "Counter 0 output"]
1480 pub const PCS_4: u16 = 0x04;
1481 #[doc = "Counter 1 output"]
1482 pub const PCS_5: u16 = 0x05;
1483 #[doc = "Counter 2 output"]
1484 pub const PCS_6: u16 = 0x06;
1485 #[doc = "Counter 3 output"]
1486 pub const PCS_7: u16 = 0x07;
1487 #[doc = "IP bus clock divide by 1 prescaler"]
1488 pub const PCS_8: u16 = 0x08;
1489 #[doc = "IP bus clock divide by 2 prescaler"]
1490 pub const PCS_9: u16 = 0x09;
1491 #[doc = "IP bus clock divide by 4 prescaler"]
1492 pub const PCS_10: u16 = 0x0a;
1493 #[doc = "IP bus clock divide by 8 prescaler"]
1494 pub const PCS_11: u16 = 0x0b;
1495 #[doc = "IP bus clock divide by 16 prescaler"]
1496 pub const PCS_12: u16 = 0x0c;
1497 #[doc = "IP bus clock divide by 32 prescaler"]
1498 pub const PCS_13: u16 = 0x0d;
1499 #[doc = "IP bus clock divide by 64 prescaler"]
1500 pub const PCS_14: u16 = 0x0e;
1501 #[doc = "IP bus clock divide by 128 prescaler"]
1502 pub const PCS_15: u16 = 0x0f;
1503 }
1504 }
1505 #[doc = "Count Mode"]
1506 pub mod CM {
1507 pub const offset: u16 = 13;
1508 pub const mask: u16 = 0x07 << offset;
1509 pub mod R {}
1510 pub mod W {}
1511 pub mod RW {
1512 #[doc = "No operation"]
1513 pub const CM_0: u16 = 0;
1514 #[doc = "Count rising edges of primary sourceRising edges are counted only when SCTRL\\[IPS\\] = 0. Falling edges are counted when SCTRL\\[IPS\\] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL\\[IPS\\]."]
1515 pub const CM_1: u16 = 0x01;
1516 #[doc = "Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode."]
1517 pub const CM_2: u16 = 0x02;
1518 #[doc = "Count rising edges of primary source while secondary input high active"]
1519 pub const CM_3: u16 = 0x03;
1520 #[doc = "Quadrature count mode, uses primary and secondary sources"]
1521 pub const CM_4: u16 = 0x04;
1522 #[doc = "Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL\\[IPS\\] = 0. Falling edges are counted when SCTRL\\[IPS\\] = 1."]
1523 pub const CM_5: u16 = 0x05;
1524 #[doc = "Edge of secondary source triggers primary count until compare"]
1525 pub const CM_6: u16 = 0x06;
1526 #[doc = "Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs."]
1527 pub const CM_7: u16 = 0x07;
1528 }
1529 }
1530}
1531#[doc = "Timer Channel Status and Control Register"]
1532pub mod SCTRL2 {
1533 #[doc = "Output Enable"]
1534 pub mod OEN {
1535 pub const offset: u16 = 0;
1536 pub const mask: u16 = 0x01 << offset;
1537 pub mod R {}
1538 pub mod W {}
1539 pub mod RW {
1540 #[doc = "The external pin is configured as an input."]
1541 pub const OEN_0: u16 = 0;
1542 #[doc = "The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as their input see the driven value. The polarity of the signal is determined by OPS."]
1543 pub const OEN_1: u16 = 0x01;
1544 }
1545 }
1546 #[doc = "Output Polarity Select"]
1547 pub mod OPS {
1548 pub const offset: u16 = 1;
1549 pub const mask: u16 = 0x01 << offset;
1550 pub mod R {}
1551 pub mod W {}
1552 pub mod RW {
1553 #[doc = "True polarity."]
1554 pub const OPS_0: u16 = 0;
1555 #[doc = "Inverted polarity."]
1556 pub const OPS_1: u16 = 0x01;
1557 }
1558 }
1559 #[doc = "Force OFLAG Output"]
1560 pub mod FORCE {
1561 pub const offset: u16 = 2;
1562 pub const mask: u16 = 0x01 << offset;
1563 pub mod R {}
1564 pub mod W {}
1565 pub mod RW {}
1566 }
1567 #[doc = "Forced OFLAG Value"]
1568 pub mod VAL {
1569 pub const offset: u16 = 3;
1570 pub const mask: u16 = 0x01 << offset;
1571 pub mod R {}
1572 pub mod W {}
1573 pub mod RW {}
1574 }
1575 #[doc = "Enable External OFLAG Force"]
1576 pub mod EEOF {
1577 pub const offset: u16 = 4;
1578 pub const mask: u16 = 0x01 << offset;
1579 pub mod R {}
1580 pub mod W {}
1581 pub mod RW {}
1582 }
1583 #[doc = "Master Mode"]
1584 pub mod MSTR {
1585 pub const offset: u16 = 5;
1586 pub const mask: u16 = 0x01 << offset;
1587 pub mod R {}
1588 pub mod W {}
1589 pub mod RW {}
1590 }
1591 #[doc = "Input Capture Mode"]
1592 pub mod CAPTURE_MODE {
1593 pub const offset: u16 = 6;
1594 pub const mask: u16 = 0x03 << offset;
1595 pub mod R {}
1596 pub mod W {}
1597 pub mod RW {
1598 #[doc = "Capture function is disabled"]
1599 pub const CAPTURE_MODE_0: u16 = 0;
1600 #[doc = "Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input"]
1601 pub const CAPTURE_MODE_1: u16 = 0x01;
1602 #[doc = "Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input"]
1603 pub const CAPTURE_MODE_2: u16 = 0x02;
1604 #[doc = "Load capture register on both edges of input"]
1605 pub const CAPTURE_MODE_3: u16 = 0x03;
1606 }
1607 }
1608 #[doc = "External Input Signal"]
1609 pub mod INPUT {
1610 pub const offset: u16 = 8;
1611 pub const mask: u16 = 0x01 << offset;
1612 pub mod R {}
1613 pub mod W {}
1614 pub mod RW {}
1615 }
1616 #[doc = "Input Polarity Select"]
1617 pub mod IPS {
1618 pub const offset: u16 = 9;
1619 pub const mask: u16 = 0x01 << offset;
1620 pub mod R {}
1621 pub mod W {}
1622 pub mod RW {}
1623 }
1624 #[doc = "Input Edge Flag Interrupt Enable"]
1625 pub mod IEFIE {
1626 pub const offset: u16 = 10;
1627 pub const mask: u16 = 0x01 << offset;
1628 pub mod R {}
1629 pub mod W {}
1630 pub mod RW {}
1631 }
1632 #[doc = "Input Edge Flag"]
1633 pub mod IEF {
1634 pub const offset: u16 = 11;
1635 pub const mask: u16 = 0x01 << offset;
1636 pub mod R {}
1637 pub mod W {}
1638 pub mod RW {}
1639 }
1640 #[doc = "Timer Overflow Flag Interrupt Enable"]
1641 pub mod TOFIE {
1642 pub const offset: u16 = 12;
1643 pub const mask: u16 = 0x01 << offset;
1644 pub mod R {}
1645 pub mod W {}
1646 pub mod RW {}
1647 }
1648 #[doc = "Timer Overflow Flag"]
1649 pub mod TOF {
1650 pub const offset: u16 = 13;
1651 pub const mask: u16 = 0x01 << offset;
1652 pub mod R {}
1653 pub mod W {}
1654 pub mod RW {}
1655 }
1656 #[doc = "Timer Compare Flag Interrupt Enable"]
1657 pub mod TCFIE {
1658 pub const offset: u16 = 14;
1659 pub const mask: u16 = 0x01 << offset;
1660 pub mod R {}
1661 pub mod W {}
1662 pub mod RW {}
1663 }
1664 #[doc = "Timer Compare Flag"]
1665 pub mod TCF {
1666 pub const offset: u16 = 15;
1667 pub const mask: u16 = 0x01 << offset;
1668 pub mod R {}
1669 pub mod W {}
1670 pub mod RW {}
1671 }
1672}
1673#[doc = "Timer Channel Comparator Load Register 1"]
1674pub mod CMPLD12 {
1675 #[doc = "This read/write register is the comparator 1 preload value for the COMP1 register for the corresponding channel in a timer module"]
1676 pub mod COMPARATOR_LOAD_1 {
1677 pub const offset: u16 = 0;
1678 pub const mask: u16 = 0xffff << offset;
1679 pub mod R {}
1680 pub mod W {}
1681 pub mod RW {}
1682 }
1683}
1684#[doc = "Timer Channel Comparator Load Register 2"]
1685pub mod CMPLD22 {
1686 #[doc = "This read/write register is the comparator 2 preload value for the COMP2 register for the corresponding channel in a timer module"]
1687 pub mod COMPARATOR_LOAD_2 {
1688 pub const offset: u16 = 0;
1689 pub const mask: u16 = 0xffff << offset;
1690 pub mod R {}
1691 pub mod W {}
1692 pub mod RW {}
1693 }
1694}
1695#[doc = "Timer Channel Comparator Status and Control Register"]
1696pub mod CSCTRL2 {
1697 #[doc = "Compare Load Control 1"]
1698 pub mod CL1 {
1699 pub const offset: u16 = 0;
1700 pub const mask: u16 = 0x03 << offset;
1701 pub mod R {}
1702 pub mod W {}
1703 pub mod RW {
1704 #[doc = "Never preload"]
1705 pub const CL1_0: u16 = 0;
1706 #[doc = "Load upon successful compare with the value in COMP1"]
1707 pub const CL1_1: u16 = 0x01;
1708 #[doc = "Load upon successful compare with the value in COMP2"]
1709 pub const CL1_2: u16 = 0x02;
1710 }
1711 }
1712 #[doc = "Compare Load Control 2"]
1713 pub mod CL2 {
1714 pub const offset: u16 = 2;
1715 pub const mask: u16 = 0x03 << offset;
1716 pub mod R {}
1717 pub mod W {}
1718 pub mod RW {
1719 #[doc = "Never preload"]
1720 pub const CL2_0: u16 = 0;
1721 #[doc = "Load upon successful compare with the value in COMP1"]
1722 pub const CL2_1: u16 = 0x01;
1723 #[doc = "Load upon successful compare with the value in COMP2"]
1724 pub const CL2_2: u16 = 0x02;
1725 }
1726 }
1727 #[doc = "Timer Compare 1 Interrupt Flag"]
1728 pub mod TCF1 {
1729 pub const offset: u16 = 4;
1730 pub const mask: u16 = 0x01 << offset;
1731 pub mod R {}
1732 pub mod W {}
1733 pub mod RW {}
1734 }
1735 #[doc = "Timer Compare 2 Interrupt Flag"]
1736 pub mod TCF2 {
1737 pub const offset: u16 = 5;
1738 pub const mask: u16 = 0x01 << offset;
1739 pub mod R {}
1740 pub mod W {}
1741 pub mod RW {}
1742 }
1743 #[doc = "Timer Compare 1 Interrupt Enable"]
1744 pub mod TCF1EN {
1745 pub const offset: u16 = 6;
1746 pub const mask: u16 = 0x01 << offset;
1747 pub mod R {}
1748 pub mod W {}
1749 pub mod RW {}
1750 }
1751 #[doc = "Timer Compare 2 Interrupt Enable"]
1752 pub mod TCF2EN {
1753 pub const offset: u16 = 7;
1754 pub const mask: u16 = 0x01 << offset;
1755 pub mod R {}
1756 pub mod W {}
1757 pub mod RW {}
1758 }
1759 #[doc = "Counting Direction Indicator"]
1760 pub mod UP {
1761 pub const offset: u16 = 9;
1762 pub const mask: u16 = 0x01 << offset;
1763 pub mod R {}
1764 pub mod W {}
1765 pub mod RW {
1766 #[doc = "The last count was in the DOWN direction."]
1767 pub const UP_0: u16 = 0;
1768 #[doc = "The last count was in the UP direction."]
1769 pub const UP_1: u16 = 0x01;
1770 }
1771 }
1772 #[doc = "Triggered Count Initialization Control"]
1773 pub mod TCI {
1774 pub const offset: u16 = 10;
1775 pub const mask: u16 = 0x01 << offset;
1776 pub mod R {}
1777 pub mod W {}
1778 pub mod RW {
1779 #[doc = "Stop counter upon receiving a second trigger event while still counting from the first trigger event."]
1780 pub const TCI_0: u16 = 0;
1781 #[doc = "Reload the counter upon receiving a second trigger event while still counting from the first trigger event."]
1782 pub const TCI_1: u16 = 0x01;
1783 }
1784 }
1785 #[doc = "Reload on Capture"]
1786 pub mod ROC {
1787 pub const offset: u16 = 11;
1788 pub const mask: u16 = 0x01 << offset;
1789 pub mod R {}
1790 pub mod W {}
1791 pub mod RW {
1792 #[doc = "Do not reload the counter on a capture event."]
1793 pub const ROC_0: u16 = 0;
1794 #[doc = "Reload the counter on a capture event."]
1795 pub const ROC_1: u16 = 0x01;
1796 }
1797 }
1798 #[doc = "Alternative Load Enable"]
1799 pub mod ALT_LOAD {
1800 pub const offset: u16 = 12;
1801 pub const mask: u16 = 0x01 << offset;
1802 pub mod R {}
1803 pub mod W {}
1804 pub mod RW {
1805 #[doc = "Counter can be re-initialized only with the LOAD register."]
1806 pub const ALT_LOAD_0: u16 = 0;
1807 #[doc = "Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction."]
1808 pub const ALT_LOAD_1: u16 = 0x01;
1809 }
1810 }
1811 #[doc = "Fault Enable"]
1812 pub mod FAULT {
1813 pub const offset: u16 = 13;
1814 pub const mask: u16 = 0x01 << offset;
1815 pub mod R {}
1816 pub mod W {}
1817 pub mod RW {
1818 #[doc = "Fault function disabled."]
1819 pub const FAULT_0: u16 = 0;
1820 #[doc = "Fault function enabled."]
1821 pub const FAULT_1: u16 = 0x01;
1822 }
1823 }
1824 #[doc = "Debug Actions Enable"]
1825 pub mod DBG_EN {
1826 pub const offset: u16 = 14;
1827 pub const mask: u16 = 0x03 << offset;
1828 pub mod R {}
1829 pub mod W {}
1830 pub mod RW {
1831 #[doc = "Continue with normal operation during debug mode. (default)"]
1832 pub const DBG_EN_0: u16 = 0;
1833 #[doc = "Halt TMR counter during debug mode."]
1834 pub const DBG_EN_1: u16 = 0x01;
1835 #[doc = "Force TMR output to logic 0 (prior to consideration of SCTRL\\[OPS\\])."]
1836 pub const DBG_EN_2: u16 = 0x02;
1837 #[doc = "Both halt counter and force output to 0 during debug mode."]
1838 pub const DBG_EN_3: u16 = 0x03;
1839 }
1840 }
1841}
1842#[doc = "Timer Channel Input Filter Register"]
1843pub mod FILT2 {
1844 #[doc = "Input Filter Sample Period"]
1845 pub mod FILT_PER {
1846 pub const offset: u16 = 0;
1847 pub const mask: u16 = 0xff << offset;
1848 pub mod R {}
1849 pub mod W {}
1850 pub mod RW {}
1851 }
1852 #[doc = "Input Filter Sample Count"]
1853 pub mod FILT_CNT {
1854 pub const offset: u16 = 8;
1855 pub const mask: u16 = 0x07 << offset;
1856 pub mod R {}
1857 pub mod W {}
1858 pub mod RW {}
1859 }
1860}
1861#[doc = "Timer Channel DMA Enable Register"]
1862pub mod DMA2 {
1863 #[doc = "Input Edge Flag DMA Enable"]
1864 pub mod IEFDE {
1865 pub const offset: u16 = 0;
1866 pub const mask: u16 = 0x01 << offset;
1867 pub mod R {}
1868 pub mod W {}
1869 pub mod RW {}
1870 }
1871 #[doc = "Comparator Preload Register 1 DMA Enable"]
1872 pub mod CMPLD1DE {
1873 pub const offset: u16 = 1;
1874 pub const mask: u16 = 0x01 << offset;
1875 pub mod R {}
1876 pub mod W {}
1877 pub mod RW {}
1878 }
1879 #[doc = "Comparator Preload Register 2 DMA Enable"]
1880 pub mod CMPLD2DE {
1881 pub const offset: u16 = 2;
1882 pub const mask: u16 = 0x01 << offset;
1883 pub mod R {}
1884 pub mod W {}
1885 pub mod RW {}
1886 }
1887}
1888#[doc = "Timer Channel Compare Register 1"]
1889pub mod COMP13 {
1890 #[doc = "Comparison Value 1"]
1891 pub mod COMPARISON_1 {
1892 pub const offset: u16 = 0;
1893 pub const mask: u16 = 0xffff << offset;
1894 pub mod R {}
1895 pub mod W {}
1896 pub mod RW {}
1897 }
1898}
1899#[doc = "Timer Channel Compare Register 2"]
1900pub mod COMP23 {
1901 #[doc = "Comparison Value 2"]
1902 pub mod COMPARISON_2 {
1903 pub const offset: u16 = 0;
1904 pub const mask: u16 = 0xffff << offset;
1905 pub mod R {}
1906 pub mod W {}
1907 pub mod RW {}
1908 }
1909}
1910#[doc = "Timer Channel Capture Register"]
1911pub mod CAPT3 {
1912 #[doc = "Capture Value"]
1913 pub mod CAPTURE {
1914 pub const offset: u16 = 0;
1915 pub const mask: u16 = 0xffff << offset;
1916 pub mod R {}
1917 pub mod W {}
1918 pub mod RW {}
1919 }
1920}
1921#[doc = "Timer Channel Load Register"]
1922pub mod LOAD3 {
1923 #[doc = "Timer Load Register"]
1924 pub mod LOAD {
1925 pub const offset: u16 = 0;
1926 pub const mask: u16 = 0xffff << offset;
1927 pub mod R {}
1928 pub mod W {}
1929 pub mod RW {}
1930 }
1931}
1932#[doc = "Timer Channel Hold Register"]
1933pub mod HOLD3 {
1934 #[doc = "This read/write register stores the counter's values of specific channels whenever any of the four counters within a module is read"]
1935 pub mod HOLD {
1936 pub const offset: u16 = 0;
1937 pub const mask: u16 = 0xffff << offset;
1938 pub mod R {}
1939 pub mod W {}
1940 pub mod RW {}
1941 }
1942}
1943#[doc = "Timer Channel Counter Register"]
1944pub mod CNTR3 {
1945 #[doc = "This read/write register is the counter for the corresponding channel in a timer module."]
1946 pub mod COUNTER {
1947 pub const offset: u16 = 0;
1948 pub const mask: u16 = 0xffff << offset;
1949 pub mod R {}
1950 pub mod W {}
1951 pub mod RW {}
1952 }
1953}
1954#[doc = "Timer Channel Control Register"]
1955pub mod CTRL3 {
1956 #[doc = "Output Mode"]
1957 pub mod OUTMODE {
1958 pub const offset: u16 = 0;
1959 pub const mask: u16 = 0x07 << offset;
1960 pub mod R {}
1961 pub mod W {}
1962 pub mod RW {
1963 #[doc = "Asserted while counter is active"]
1964 pub const OUTMODE_0: u16 = 0;
1965 #[doc = "Clear OFLAG output on successful compare"]
1966 pub const OUTMODE_1: u16 = 0x01;
1967 #[doc = "Set OFLAG output on successful compare"]
1968 pub const OUTMODE_2: u16 = 0x02;
1969 #[doc = "Toggle OFLAG output on successful compare"]
1970 pub const OUTMODE_3: u16 = 0x03;
1971 #[doc = "Toggle OFLAG output using alternating compare registers"]
1972 pub const OUTMODE_4: u16 = 0x04;
1973 #[doc = "Set on compare, cleared on secondary source input edge"]
1974 pub const OUTMODE_5: u16 = 0x05;
1975 #[doc = "Set on compare, cleared on counter rollover"]
1976 pub const OUTMODE_6: u16 = 0x06;
1977 #[doc = "Enable gated clock output while counter is active"]
1978 pub const OUTMODE_7: u16 = 0x07;
1979 }
1980 }
1981 #[doc = "Co-Channel Initialization"]
1982 pub mod COINIT {
1983 pub const offset: u16 = 3;
1984 pub const mask: u16 = 0x01 << offset;
1985 pub mod R {}
1986 pub mod W {}
1987 pub mod RW {
1988 #[doc = "Co-channel counter/timers cannot force a re-initialization of this counter/timer"]
1989 pub const COINIT_0: u16 = 0;
1990 #[doc = "Co-channel counter/timers may force a re-initialization of this counter/timer"]
1991 pub const COINIT_1: u16 = 0x01;
1992 }
1993 }
1994 #[doc = "Count Direction"]
1995 pub mod DIR {
1996 pub const offset: u16 = 4;
1997 pub const mask: u16 = 0x01 << offset;
1998 pub mod R {}
1999 pub mod W {}
2000 pub mod RW {
2001 #[doc = "Count up."]
2002 pub const DIR_0: u16 = 0;
2003 #[doc = "Count down."]
2004 pub const DIR_1: u16 = 0x01;
2005 }
2006 }
2007 #[doc = "Count Length"]
2008 pub mod LENGTH {
2009 pub const offset: u16 = 5;
2010 pub const mask: u16 = 0x01 << offset;
2011 pub mod R {}
2012 pub mod W {}
2013 pub mod RW {
2014 #[doc = "Count until roll over at $FFFF and continue from $0000."]
2015 pub const LENGTH_0: u16 = 0;
2016 #[doc = "Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on."]
2017 pub const LENGTH_1: u16 = 0x01;
2018 }
2019 }
2020 #[doc = "Count Once"]
2021 pub mod ONCE {
2022 pub const offset: u16 = 6;
2023 pub const mask: u16 = 0x01 << offset;
2024 pub mod R {}
2025 pub mod W {}
2026 pub mod RW {
2027 #[doc = "Count repeatedly."]
2028 pub const ONCE_0: u16 = 0;
2029 #[doc = "Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops."]
2030 pub const ONCE_1: u16 = 0x01;
2031 }
2032 }
2033 #[doc = "Secondary Count Source"]
2034 pub mod SCS {
2035 pub const offset: u16 = 7;
2036 pub const mask: u16 = 0x03 << offset;
2037 pub mod R {}
2038 pub mod W {}
2039 pub mod RW {
2040 #[doc = "Counter 0 input pin"]
2041 pub const SCS_0: u16 = 0;
2042 #[doc = "Counter 1 input pin"]
2043 pub const SCS_1: u16 = 0x01;
2044 #[doc = "Counter 2 input pin"]
2045 pub const SCS_2: u16 = 0x02;
2046 #[doc = "Counter 3 input pin"]
2047 pub const SCS_3: u16 = 0x03;
2048 }
2049 }
2050 #[doc = "Primary Count Source"]
2051 pub mod PCS {
2052 pub const offset: u16 = 9;
2053 pub const mask: u16 = 0x0f << offset;
2054 pub mod R {}
2055 pub mod W {}
2056 pub mod RW {
2057 #[doc = "Counter 0 input pin"]
2058 pub const PCS_0: u16 = 0;
2059 #[doc = "Counter 1 input pin"]
2060 pub const PCS_1: u16 = 0x01;
2061 #[doc = "Counter 2 input pin"]
2062 pub const PCS_2: u16 = 0x02;
2063 #[doc = "Counter 3 input pin"]
2064 pub const PCS_3: u16 = 0x03;
2065 #[doc = "Counter 0 output"]
2066 pub const PCS_4: u16 = 0x04;
2067 #[doc = "Counter 1 output"]
2068 pub const PCS_5: u16 = 0x05;
2069 #[doc = "Counter 2 output"]
2070 pub const PCS_6: u16 = 0x06;
2071 #[doc = "Counter 3 output"]
2072 pub const PCS_7: u16 = 0x07;
2073 #[doc = "IP bus clock divide by 1 prescaler"]
2074 pub const PCS_8: u16 = 0x08;
2075 #[doc = "IP bus clock divide by 2 prescaler"]
2076 pub const PCS_9: u16 = 0x09;
2077 #[doc = "IP bus clock divide by 4 prescaler"]
2078 pub const PCS_10: u16 = 0x0a;
2079 #[doc = "IP bus clock divide by 8 prescaler"]
2080 pub const PCS_11: u16 = 0x0b;
2081 #[doc = "IP bus clock divide by 16 prescaler"]
2082 pub const PCS_12: u16 = 0x0c;
2083 #[doc = "IP bus clock divide by 32 prescaler"]
2084 pub const PCS_13: u16 = 0x0d;
2085 #[doc = "IP bus clock divide by 64 prescaler"]
2086 pub const PCS_14: u16 = 0x0e;
2087 #[doc = "IP bus clock divide by 128 prescaler"]
2088 pub const PCS_15: u16 = 0x0f;
2089 }
2090 }
2091 #[doc = "Count Mode"]
2092 pub mod CM {
2093 pub const offset: u16 = 13;
2094 pub const mask: u16 = 0x07 << offset;
2095 pub mod R {}
2096 pub mod W {}
2097 pub mod RW {
2098 #[doc = "No operation"]
2099 pub const CM_0: u16 = 0;
2100 #[doc = "Count rising edges of primary sourceRising edges are counted only when SCTRL\\[IPS\\] = 0. Falling edges are counted when SCTRL\\[IPS\\] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL\\[IPS\\]."]
2101 pub const CM_1: u16 = 0x01;
2102 #[doc = "Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode."]
2103 pub const CM_2: u16 = 0x02;
2104 #[doc = "Count rising edges of primary source while secondary input high active"]
2105 pub const CM_3: u16 = 0x03;
2106 #[doc = "Quadrature count mode, uses primary and secondary sources"]
2107 pub const CM_4: u16 = 0x04;
2108 #[doc = "Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL\\[IPS\\] = 0. Falling edges are counted when SCTRL\\[IPS\\] = 1."]
2109 pub const CM_5: u16 = 0x05;
2110 #[doc = "Edge of secondary source triggers primary count until compare"]
2111 pub const CM_6: u16 = 0x06;
2112 #[doc = "Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs."]
2113 pub const CM_7: u16 = 0x07;
2114 }
2115 }
2116}
2117#[doc = "Timer Channel Status and Control Register"]
2118pub mod SCTRL3 {
2119 #[doc = "Output Enable"]
2120 pub mod OEN {
2121 pub const offset: u16 = 0;
2122 pub const mask: u16 = 0x01 << offset;
2123 pub mod R {}
2124 pub mod W {}
2125 pub mod RW {
2126 #[doc = "The external pin is configured as an input."]
2127 pub const OEN_0: u16 = 0;
2128 #[doc = "The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as their input see the driven value. The polarity of the signal is determined by OPS."]
2129 pub const OEN_1: u16 = 0x01;
2130 }
2131 }
2132 #[doc = "Output Polarity Select"]
2133 pub mod OPS {
2134 pub const offset: u16 = 1;
2135 pub const mask: u16 = 0x01 << offset;
2136 pub mod R {}
2137 pub mod W {}
2138 pub mod RW {
2139 #[doc = "True polarity."]
2140 pub const OPS_0: u16 = 0;
2141 #[doc = "Inverted polarity."]
2142 pub const OPS_1: u16 = 0x01;
2143 }
2144 }
2145 #[doc = "Force OFLAG Output"]
2146 pub mod FORCE {
2147 pub const offset: u16 = 2;
2148 pub const mask: u16 = 0x01 << offset;
2149 pub mod R {}
2150 pub mod W {}
2151 pub mod RW {}
2152 }
2153 #[doc = "Forced OFLAG Value"]
2154 pub mod VAL {
2155 pub const offset: u16 = 3;
2156 pub const mask: u16 = 0x01 << offset;
2157 pub mod R {}
2158 pub mod W {}
2159 pub mod RW {}
2160 }
2161 #[doc = "Enable External OFLAG Force"]
2162 pub mod EEOF {
2163 pub const offset: u16 = 4;
2164 pub const mask: u16 = 0x01 << offset;
2165 pub mod R {}
2166 pub mod W {}
2167 pub mod RW {}
2168 }
2169 #[doc = "Master Mode"]
2170 pub mod MSTR {
2171 pub const offset: u16 = 5;
2172 pub const mask: u16 = 0x01 << offset;
2173 pub mod R {}
2174 pub mod W {}
2175 pub mod RW {}
2176 }
2177 #[doc = "Input Capture Mode"]
2178 pub mod CAPTURE_MODE {
2179 pub const offset: u16 = 6;
2180 pub const mask: u16 = 0x03 << offset;
2181 pub mod R {}
2182 pub mod W {}
2183 pub mod RW {
2184 #[doc = "Capture function is disabled"]
2185 pub const CAPTURE_MODE_0: u16 = 0;
2186 #[doc = "Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input"]
2187 pub const CAPTURE_MODE_1: u16 = 0x01;
2188 #[doc = "Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input"]
2189 pub const CAPTURE_MODE_2: u16 = 0x02;
2190 #[doc = "Load capture register on both edges of input"]
2191 pub const CAPTURE_MODE_3: u16 = 0x03;
2192 }
2193 }
2194 #[doc = "External Input Signal"]
2195 pub mod INPUT {
2196 pub const offset: u16 = 8;
2197 pub const mask: u16 = 0x01 << offset;
2198 pub mod R {}
2199 pub mod W {}
2200 pub mod RW {}
2201 }
2202 #[doc = "Input Polarity Select"]
2203 pub mod IPS {
2204 pub const offset: u16 = 9;
2205 pub const mask: u16 = 0x01 << offset;
2206 pub mod R {}
2207 pub mod W {}
2208 pub mod RW {}
2209 }
2210 #[doc = "Input Edge Flag Interrupt Enable"]
2211 pub mod IEFIE {
2212 pub const offset: u16 = 10;
2213 pub const mask: u16 = 0x01 << offset;
2214 pub mod R {}
2215 pub mod W {}
2216 pub mod RW {}
2217 }
2218 #[doc = "Input Edge Flag"]
2219 pub mod IEF {
2220 pub const offset: u16 = 11;
2221 pub const mask: u16 = 0x01 << offset;
2222 pub mod R {}
2223 pub mod W {}
2224 pub mod RW {}
2225 }
2226 #[doc = "Timer Overflow Flag Interrupt Enable"]
2227 pub mod TOFIE {
2228 pub const offset: u16 = 12;
2229 pub const mask: u16 = 0x01 << offset;
2230 pub mod R {}
2231 pub mod W {}
2232 pub mod RW {}
2233 }
2234 #[doc = "Timer Overflow Flag"]
2235 pub mod TOF {
2236 pub const offset: u16 = 13;
2237 pub const mask: u16 = 0x01 << offset;
2238 pub mod R {}
2239 pub mod W {}
2240 pub mod RW {}
2241 }
2242 #[doc = "Timer Compare Flag Interrupt Enable"]
2243 pub mod TCFIE {
2244 pub const offset: u16 = 14;
2245 pub const mask: u16 = 0x01 << offset;
2246 pub mod R {}
2247 pub mod W {}
2248 pub mod RW {}
2249 }
2250 #[doc = "Timer Compare Flag"]
2251 pub mod TCF {
2252 pub const offset: u16 = 15;
2253 pub const mask: u16 = 0x01 << offset;
2254 pub mod R {}
2255 pub mod W {}
2256 pub mod RW {}
2257 }
2258}
2259#[doc = "Timer Channel Comparator Load Register 1"]
2260pub mod CMPLD13 {
2261 #[doc = "This read/write register is the comparator 1 preload value for the COMP1 register for the corresponding channel in a timer module"]
2262 pub mod COMPARATOR_LOAD_1 {
2263 pub const offset: u16 = 0;
2264 pub const mask: u16 = 0xffff << offset;
2265 pub mod R {}
2266 pub mod W {}
2267 pub mod RW {}
2268 }
2269}
2270#[doc = "Timer Channel Comparator Load Register 2"]
2271pub mod CMPLD23 {
2272 #[doc = "This read/write register is the comparator 2 preload value for the COMP2 register for the corresponding channel in a timer module"]
2273 pub mod COMPARATOR_LOAD_2 {
2274 pub const offset: u16 = 0;
2275 pub const mask: u16 = 0xffff << offset;
2276 pub mod R {}
2277 pub mod W {}
2278 pub mod RW {}
2279 }
2280}
2281#[doc = "Timer Channel Comparator Status and Control Register"]
2282pub mod CSCTRL3 {
2283 #[doc = "Compare Load Control 1"]
2284 pub mod CL1 {
2285 pub const offset: u16 = 0;
2286 pub const mask: u16 = 0x03 << offset;
2287 pub mod R {}
2288 pub mod W {}
2289 pub mod RW {
2290 #[doc = "Never preload"]
2291 pub const CL1_0: u16 = 0;
2292 #[doc = "Load upon successful compare with the value in COMP1"]
2293 pub const CL1_1: u16 = 0x01;
2294 #[doc = "Load upon successful compare with the value in COMP2"]
2295 pub const CL1_2: u16 = 0x02;
2296 }
2297 }
2298 #[doc = "Compare Load Control 2"]
2299 pub mod CL2 {
2300 pub const offset: u16 = 2;
2301 pub const mask: u16 = 0x03 << offset;
2302 pub mod R {}
2303 pub mod W {}
2304 pub mod RW {
2305 #[doc = "Never preload"]
2306 pub const CL2_0: u16 = 0;
2307 #[doc = "Load upon successful compare with the value in COMP1"]
2308 pub const CL2_1: u16 = 0x01;
2309 #[doc = "Load upon successful compare with the value in COMP2"]
2310 pub const CL2_2: u16 = 0x02;
2311 }
2312 }
2313 #[doc = "Timer Compare 1 Interrupt Flag"]
2314 pub mod TCF1 {
2315 pub const offset: u16 = 4;
2316 pub const mask: u16 = 0x01 << offset;
2317 pub mod R {}
2318 pub mod W {}
2319 pub mod RW {}
2320 }
2321 #[doc = "Timer Compare 2 Interrupt Flag"]
2322 pub mod TCF2 {
2323 pub const offset: u16 = 5;
2324 pub const mask: u16 = 0x01 << offset;
2325 pub mod R {}
2326 pub mod W {}
2327 pub mod RW {}
2328 }
2329 #[doc = "Timer Compare 1 Interrupt Enable"]
2330 pub mod TCF1EN {
2331 pub const offset: u16 = 6;
2332 pub const mask: u16 = 0x01 << offset;
2333 pub mod R {}
2334 pub mod W {}
2335 pub mod RW {}
2336 }
2337 #[doc = "Timer Compare 2 Interrupt Enable"]
2338 pub mod TCF2EN {
2339 pub const offset: u16 = 7;
2340 pub const mask: u16 = 0x01 << offset;
2341 pub mod R {}
2342 pub mod W {}
2343 pub mod RW {}
2344 }
2345 #[doc = "Counting Direction Indicator"]
2346 pub mod UP {
2347 pub const offset: u16 = 9;
2348 pub const mask: u16 = 0x01 << offset;
2349 pub mod R {}
2350 pub mod W {}
2351 pub mod RW {
2352 #[doc = "The last count was in the DOWN direction."]
2353 pub const UP_0: u16 = 0;
2354 #[doc = "The last count was in the UP direction."]
2355 pub const UP_1: u16 = 0x01;
2356 }
2357 }
2358 #[doc = "Triggered Count Initialization Control"]
2359 pub mod TCI {
2360 pub const offset: u16 = 10;
2361 pub const mask: u16 = 0x01 << offset;
2362 pub mod R {}
2363 pub mod W {}
2364 pub mod RW {
2365 #[doc = "Stop counter upon receiving a second trigger event while still counting from the first trigger event."]
2366 pub const TCI_0: u16 = 0;
2367 #[doc = "Reload the counter upon receiving a second trigger event while still counting from the first trigger event."]
2368 pub const TCI_1: u16 = 0x01;
2369 }
2370 }
2371 #[doc = "Reload on Capture"]
2372 pub mod ROC {
2373 pub const offset: u16 = 11;
2374 pub const mask: u16 = 0x01 << offset;
2375 pub mod R {}
2376 pub mod W {}
2377 pub mod RW {
2378 #[doc = "Do not reload the counter on a capture event."]
2379 pub const ROC_0: u16 = 0;
2380 #[doc = "Reload the counter on a capture event."]
2381 pub const ROC_1: u16 = 0x01;
2382 }
2383 }
2384 #[doc = "Alternative Load Enable"]
2385 pub mod ALT_LOAD {
2386 pub const offset: u16 = 12;
2387 pub const mask: u16 = 0x01 << offset;
2388 pub mod R {}
2389 pub mod W {}
2390 pub mod RW {
2391 #[doc = "Counter can be re-initialized only with the LOAD register."]
2392 pub const ALT_LOAD_0: u16 = 0;
2393 #[doc = "Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction."]
2394 pub const ALT_LOAD_1: u16 = 0x01;
2395 }
2396 }
2397 #[doc = "Fault Enable"]
2398 pub mod FAULT {
2399 pub const offset: u16 = 13;
2400 pub const mask: u16 = 0x01 << offset;
2401 pub mod R {}
2402 pub mod W {}
2403 pub mod RW {
2404 #[doc = "Fault function disabled."]
2405 pub const FAULT_0: u16 = 0;
2406 #[doc = "Fault function enabled."]
2407 pub const FAULT_1: u16 = 0x01;
2408 }
2409 }
2410 #[doc = "Debug Actions Enable"]
2411 pub mod DBG_EN {
2412 pub const offset: u16 = 14;
2413 pub const mask: u16 = 0x03 << offset;
2414 pub mod R {}
2415 pub mod W {}
2416 pub mod RW {
2417 #[doc = "Continue with normal operation during debug mode. (default)"]
2418 pub const DBG_EN_0: u16 = 0;
2419 #[doc = "Halt TMR counter during debug mode."]
2420 pub const DBG_EN_1: u16 = 0x01;
2421 #[doc = "Force TMR output to logic 0 (prior to consideration of SCTRL\\[OPS\\])."]
2422 pub const DBG_EN_2: u16 = 0x02;
2423 #[doc = "Both halt counter and force output to 0 during debug mode."]
2424 pub const DBG_EN_3: u16 = 0x03;
2425 }
2426 }
2427}
2428#[doc = "Timer Channel Input Filter Register"]
2429pub mod FILT3 {
2430 #[doc = "Input Filter Sample Period"]
2431 pub mod FILT_PER {
2432 pub const offset: u16 = 0;
2433 pub const mask: u16 = 0xff << offset;
2434 pub mod R {}
2435 pub mod W {}
2436 pub mod RW {}
2437 }
2438 #[doc = "Input Filter Sample Count"]
2439 pub mod FILT_CNT {
2440 pub const offset: u16 = 8;
2441 pub const mask: u16 = 0x07 << offset;
2442 pub mod R {}
2443 pub mod W {}
2444 pub mod RW {}
2445 }
2446}
2447#[doc = "Timer Channel DMA Enable Register"]
2448pub mod DMA3 {
2449 #[doc = "Input Edge Flag DMA Enable"]
2450 pub mod IEFDE {
2451 pub const offset: u16 = 0;
2452 pub const mask: u16 = 0x01 << offset;
2453 pub mod R {}
2454 pub mod W {}
2455 pub mod RW {}
2456 }
2457 #[doc = "Comparator Preload Register 1 DMA Enable"]
2458 pub mod CMPLD1DE {
2459 pub const offset: u16 = 1;
2460 pub const mask: u16 = 0x01 << offset;
2461 pub mod R {}
2462 pub mod W {}
2463 pub mod RW {}
2464 }
2465 #[doc = "Comparator Preload Register 2 DMA Enable"]
2466 pub mod CMPLD2DE {
2467 pub const offset: u16 = 2;
2468 pub const mask: u16 = 0x01 << offset;
2469 pub mod R {}
2470 pub mod W {}
2471 pub mod RW {}
2472 }
2473}