imxrt_ral/blocks/imxrt1021/
usdhc.rs1#[doc = "uSDHC"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "DMA System Address"]
5 pub DS_ADDR: crate::RWRegister<u32>,
6 #[doc = "Block Attributes"]
7 pub BLK_ATT: crate::RWRegister<u32>,
8 #[doc = "Command Argument"]
9 pub CMD_ARG: crate::RWRegister<u32>,
10 #[doc = "Command Transfer Type"]
11 pub CMD_XFR_TYP: crate::RWRegister<u32>,
12 #[doc = "Command Response0"]
13 pub CMD_RSP0: crate::RORegister<u32>,
14 #[doc = "Command Response1"]
15 pub CMD_RSP1: crate::RORegister<u32>,
16 #[doc = "Command Response2"]
17 pub CMD_RSP2: crate::RORegister<u32>,
18 #[doc = "Command Response3"]
19 pub CMD_RSP3: crate::RORegister<u32>,
20 #[doc = "Data Buffer Access Port"]
21 pub DATA_BUFF_ACC_PORT: crate::RWRegister<u32>,
22 #[doc = "Present State"]
23 pub PRES_STATE: crate::RORegister<u32>,
24 #[doc = "Protocol Control"]
25 pub PROT_CTRL: crate::RWRegister<u32>,
26 #[doc = "System Control"]
27 pub SYS_CTRL: crate::RWRegister<u32>,
28 #[doc = "Interrupt Status"]
29 pub INT_STATUS: crate::RWRegister<u32>,
30 #[doc = "Interrupt Status Enable"]
31 pub INT_STATUS_EN: crate::RWRegister<u32>,
32 #[doc = "Interrupt Signal Enable"]
33 pub INT_SIGNAL_EN: crate::RWRegister<u32>,
34 #[doc = "Auto CMD12 Error Status"]
35 pub AUTOCMD12_ERR_STATUS: crate::RWRegister<u32>,
36 #[doc = "Host Controller Capabilities"]
37 pub HOST_CTRL_CAP: crate::RWRegister<u32>,
38 #[doc = "Watermark Level"]
39 pub WTMK_LVL: crate::RWRegister<u32>,
40 #[doc = "Mixer Control"]
41 pub MIX_CTRL: crate::RWRegister<u32>,
42 _reserved0: [u8; 0x04],
43 #[doc = "Force Event"]
44 pub FORCE_EVENT: crate::RWRegister<u32>,
45 #[doc = "ADMA Error Status Register"]
46 pub ADMA_ERR_STATUS: crate::RORegister<u32>,
47 #[doc = "ADMA System Address"]
48 pub ADMA_SYS_ADDR: crate::RWRegister<u32>,
49 _reserved1: [u8; 0x04],
50 #[doc = "DLL (Delay Line) Control"]
51 pub DLL_CTRL: crate::RWRegister<u32>,
52 #[doc = "DLL Status"]
53 pub DLL_STATUS: crate::RORegister<u32>,
54 #[doc = "CLK Tuning Control and Status"]
55 pub CLK_TUNE_CTRL_STATUS: crate::RWRegister<u32>,
56 _reserved2: [u8; 0x54],
57 #[doc = "Vendor Specific Register"]
58 pub VEND_SPEC: crate::RWRegister<u32>,
59 #[doc = "MMC Boot Register"]
60 pub MMC_BOOT: crate::RWRegister<u32>,
61 #[doc = "Vendor Specific 2 Register"]
62 pub VEND_SPEC2: crate::RWRegister<u32>,
63 #[doc = "Tuning Control Register"]
64 pub TUNING_CTRL: crate::RWRegister<u32>,
65}
66#[doc = "DMA System Address"]
67pub mod DS_ADDR {
68 #[doc = "DS_ADDR"]
69 pub mod DS_ADDR {
70 pub const offset: u32 = 0;
71 pub const mask: u32 = 0xffff_ffff << offset;
72 pub mod R {}
73 pub mod W {}
74 pub mod RW {}
75 }
76}
77#[doc = "Block Attributes"]
78pub mod BLK_ATT {
79 #[doc = "Block Size"]
80 pub mod BLKSIZE {
81 pub const offset: u32 = 0;
82 pub const mask: u32 = 0x1fff << offset;
83 pub mod R {}
84 pub mod W {}
85 pub mod RW {
86 #[doc = "No data transfer"]
87 pub const BLKSIZE_0: u32 = 0;
88 #[doc = "1 Byte"]
89 pub const BLKSIZE_1: u32 = 0x01;
90 #[doc = "2 Bytes"]
91 pub const BLKSIZE_2: u32 = 0x02;
92 #[doc = "3 Bytes"]
93 pub const BLKSIZE_3: u32 = 0x03;
94 #[doc = "4 Bytes"]
95 pub const BLKSIZE_4: u32 = 0x04;
96 #[doc = "511 Bytes"]
97 pub const BLKSIZE_511: u32 = 0x01ff;
98 #[doc = "512 Bytes"]
99 pub const BLKSIZE_512: u32 = 0x0200;
100 #[doc = "2048 Bytes"]
101 pub const BLKSIZE_2048: u32 = 0x0800;
102 #[doc = "4096 Bytes"]
103 pub const BLKSIZE_4096: u32 = 0x1000;
104 }
105 }
106 #[doc = "Block Count"]
107 pub mod BLKCNT {
108 pub const offset: u32 = 16;
109 pub const mask: u32 = 0xffff << offset;
110 pub mod R {}
111 pub mod W {}
112 pub mod RW {
113 #[doc = "Stop Count"]
114 pub const BLKCNT_0: u32 = 0;
115 #[doc = "1 block"]
116 pub const BLKCNT_1: u32 = 0x01;
117 #[doc = "2 blocks"]
118 pub const BLKCNT_2: u32 = 0x02;
119 #[doc = "65535 blocks"]
120 pub const BLKCNT_65535: u32 = 0xffff;
121 }
122 }
123}
124#[doc = "Command Argument"]
125pub mod CMD_ARG {
126 #[doc = "Command Argument"]
127 pub mod CMDARG {
128 pub const offset: u32 = 0;
129 pub const mask: u32 = 0xffff_ffff << offset;
130 pub mod R {}
131 pub mod W {}
132 pub mod RW {}
133 }
134}
135#[doc = "Command Transfer Type"]
136pub mod CMD_XFR_TYP {
137 #[doc = "Response Type Select"]
138 pub mod RSPTYP {
139 pub const offset: u32 = 16;
140 pub const mask: u32 = 0x03 << offset;
141 pub mod R {}
142 pub mod W {}
143 pub mod RW {
144 #[doc = "No Response"]
145 pub const RSPTYP_0: u32 = 0;
146 #[doc = "Response Length 136"]
147 pub const RSPTYP_1: u32 = 0x01;
148 #[doc = "Response Length 48"]
149 pub const RSPTYP_2: u32 = 0x02;
150 #[doc = "Response Length 48, check Busy after response"]
151 pub const RSPTYP_3: u32 = 0x03;
152 }
153 }
154 #[doc = "Command CRC Check Enable"]
155 pub mod CCCEN {
156 pub const offset: u32 = 19;
157 pub const mask: u32 = 0x01 << offset;
158 pub mod R {}
159 pub mod W {}
160 pub mod RW {
161 #[doc = "Disable"]
162 pub const CCCEN_0: u32 = 0;
163 #[doc = "Enable"]
164 pub const CCCEN_1: u32 = 0x01;
165 }
166 }
167 #[doc = "Command Index Check Enable"]
168 pub mod CICEN {
169 pub const offset: u32 = 20;
170 pub const mask: u32 = 0x01 << offset;
171 pub mod R {}
172 pub mod W {}
173 pub mod RW {
174 #[doc = "Disable"]
175 pub const CICEN_0: u32 = 0;
176 #[doc = "Enable"]
177 pub const CICEN_1: u32 = 0x01;
178 }
179 }
180 #[doc = "Data Present Select"]
181 pub mod DPSEL {
182 pub const offset: u32 = 21;
183 pub const mask: u32 = 0x01 << offset;
184 pub mod R {}
185 pub mod W {}
186 pub mod RW {
187 #[doc = "No Data Present"]
188 pub const DPSEL_0: u32 = 0;
189 #[doc = "Data Present"]
190 pub const DPSEL_1: u32 = 0x01;
191 }
192 }
193 #[doc = "Command Type"]
194 pub mod CMDTYP {
195 pub const offset: u32 = 22;
196 pub const mask: u32 = 0x03 << offset;
197 pub mod R {}
198 pub mod W {}
199 pub mod RW {
200 #[doc = "Normal Other commands"]
201 pub const CMDTYP_0: u32 = 0;
202 #[doc = "Suspend CMD52 for writing Bus Suspend in CCCR"]
203 pub const CMDTYP_1: u32 = 0x01;
204 #[doc = "Resume CMD52 for writing Function Select in CCCR"]
205 pub const CMDTYP_2: u32 = 0x02;
206 #[doc = "Abort CMD12, CMD52 for writing I/O Abort in CCCR"]
207 pub const CMDTYP_3: u32 = 0x03;
208 }
209 }
210 #[doc = "Command Index"]
211 pub mod CMDINX {
212 pub const offset: u32 = 24;
213 pub const mask: u32 = 0x3f << offset;
214 pub mod R {}
215 pub mod W {}
216 pub mod RW {}
217 }
218}
219#[doc = "Command Response0"]
220pub mod CMD_RSP0 {
221 #[doc = "Command Response 0"]
222 pub mod CMDRSP0 {
223 pub const offset: u32 = 0;
224 pub const mask: u32 = 0xffff_ffff << offset;
225 pub mod R {}
226 pub mod W {}
227 pub mod RW {}
228 }
229}
230#[doc = "Command Response1"]
231pub mod CMD_RSP1 {
232 #[doc = "Command Response 1"]
233 pub mod CMDRSP1 {
234 pub const offset: u32 = 0;
235 pub const mask: u32 = 0xffff_ffff << offset;
236 pub mod R {}
237 pub mod W {}
238 pub mod RW {}
239 }
240}
241#[doc = "Command Response2"]
242pub mod CMD_RSP2 {
243 #[doc = "Command Response 2"]
244 pub mod CMDRSP2 {
245 pub const offset: u32 = 0;
246 pub const mask: u32 = 0xffff_ffff << offset;
247 pub mod R {}
248 pub mod W {}
249 pub mod RW {}
250 }
251}
252#[doc = "Command Response3"]
253pub mod CMD_RSP3 {
254 #[doc = "Command Response 3"]
255 pub mod CMDRSP3 {
256 pub const offset: u32 = 0;
257 pub const mask: u32 = 0xffff_ffff << offset;
258 pub mod R {}
259 pub mod W {}
260 pub mod RW {}
261 }
262}
263#[doc = "Data Buffer Access Port"]
264pub mod DATA_BUFF_ACC_PORT {
265 #[doc = "Data Content"]
266 pub mod DATCONT {
267 pub const offset: u32 = 0;
268 pub const mask: u32 = 0xffff_ffff << offset;
269 pub mod R {}
270 pub mod W {}
271 pub mod RW {}
272 }
273}
274#[doc = "Present State"]
275pub mod PRES_STATE {
276 #[doc = "Command Inhibit (CMD)"]
277 pub mod CIHB {
278 pub const offset: u32 = 0;
279 pub const mask: u32 = 0x01 << offset;
280 pub mod R {}
281 pub mod W {}
282 pub mod RW {
283 #[doc = "Can issue command using only CMD line"]
284 pub const CIHB_0: u32 = 0;
285 #[doc = "Cannot issue command"]
286 pub const CIHB_1: u32 = 0x01;
287 }
288 }
289 #[doc = "Command Inhibit (DATA)"]
290 pub mod CDIHB {
291 pub const offset: u32 = 1;
292 pub const mask: u32 = 0x01 << offset;
293 pub mod R {}
294 pub mod W {}
295 pub mod RW {
296 #[doc = "Can issue command which uses the DATA line"]
297 pub const CDIHB_0: u32 = 0;
298 #[doc = "Cannot issue command which uses the DATA line"]
299 pub const CDIHB_1: u32 = 0x01;
300 }
301 }
302 #[doc = "Data Line Active"]
303 pub mod DLA {
304 pub const offset: u32 = 2;
305 pub const mask: u32 = 0x01 << offset;
306 pub mod R {}
307 pub mod W {}
308 pub mod RW {
309 #[doc = "DATA Line Inactive"]
310 pub const DLA_0: u32 = 0;
311 #[doc = "DATA Line Active"]
312 pub const DLA_1: u32 = 0x01;
313 }
314 }
315 #[doc = "SD Clock Stable"]
316 pub mod SDSTB {
317 pub const offset: u32 = 3;
318 pub const mask: u32 = 0x01 << offset;
319 pub mod R {}
320 pub mod W {}
321 pub mod RW {
322 #[doc = "Clock is changing frequency and not stable."]
323 pub const SDSTB_0: u32 = 0;
324 #[doc = "Clock is stable."]
325 pub const SDSTB_1: u32 = 0x01;
326 }
327 }
328 #[doc = "IPG_CLK Gated Off Internally"]
329 pub mod IPGOFF {
330 pub const offset: u32 = 4;
331 pub const mask: u32 = 0x01 << offset;
332 pub mod R {}
333 pub mod W {}
334 pub mod RW {
335 #[doc = "IPG_CLK is active."]
336 pub const IPGOFF_0: u32 = 0;
337 #[doc = "IPG_CLK is gated off."]
338 pub const IPGOFF_1: u32 = 0x01;
339 }
340 }
341 #[doc = "HCLK Gated Off Internally"]
342 pub mod HCKOFF {
343 pub const offset: u32 = 5;
344 pub const mask: u32 = 0x01 << offset;
345 pub mod R {}
346 pub mod W {}
347 pub mod RW {
348 #[doc = "HCLK is active."]
349 pub const HCKOFF_0: u32 = 0;
350 #[doc = "HCLK is gated off."]
351 pub const HCKOFF_1: u32 = 0x01;
352 }
353 }
354 #[doc = "IPG_PERCLK Gated Off Internally"]
355 pub mod PEROFF {
356 pub const offset: u32 = 6;
357 pub const mask: u32 = 0x01 << offset;
358 pub mod R {}
359 pub mod W {}
360 pub mod RW {
361 #[doc = "IPG_PERCLK is active."]
362 pub const PEROFF_0: u32 = 0;
363 #[doc = "IPG_PERCLK is gated off."]
364 pub const PEROFF_1: u32 = 0x01;
365 }
366 }
367 #[doc = "SD Clock Gated Off Internally"]
368 pub mod SDOFF {
369 pub const offset: u32 = 7;
370 pub const mask: u32 = 0x01 << offset;
371 pub mod R {}
372 pub mod W {}
373 pub mod RW {
374 #[doc = "SD Clock is active."]
375 pub const SDOFF_0: u32 = 0;
376 #[doc = "SD Clock is gated off."]
377 pub const SDOFF_1: u32 = 0x01;
378 }
379 }
380 #[doc = "Write Transfer Active"]
381 pub mod WTA {
382 pub const offset: u32 = 8;
383 pub const mask: u32 = 0x01 << offset;
384 pub mod R {}
385 pub mod W {}
386 pub mod RW {
387 #[doc = "No valid data"]
388 pub const WTA_0: u32 = 0;
389 #[doc = "Transferring data"]
390 pub const WTA_1: u32 = 0x01;
391 }
392 }
393 #[doc = "Read Transfer Active"]
394 pub mod RTA {
395 pub const offset: u32 = 9;
396 pub const mask: u32 = 0x01 << offset;
397 pub mod R {}
398 pub mod W {}
399 pub mod RW {
400 #[doc = "No valid data"]
401 pub const RTA_0: u32 = 0;
402 #[doc = "Transferring data"]
403 pub const RTA_1: u32 = 0x01;
404 }
405 }
406 #[doc = "Buffer Write Enable"]
407 pub mod BWEN {
408 pub const offset: u32 = 10;
409 pub const mask: u32 = 0x01 << offset;
410 pub mod R {}
411 pub mod W {}
412 pub mod RW {
413 #[doc = "Write disable"]
414 pub const BWEN_0: u32 = 0;
415 #[doc = "Write enable"]
416 pub const BWEN_1: u32 = 0x01;
417 }
418 }
419 #[doc = "Buffer Read Enable"]
420 pub mod BREN {
421 pub const offset: u32 = 11;
422 pub const mask: u32 = 0x01 << offset;
423 pub mod R {}
424 pub mod W {}
425 pub mod RW {
426 #[doc = "Read disable"]
427 pub const BREN_0: u32 = 0;
428 #[doc = "Read enable"]
429 pub const BREN_1: u32 = 0x01;
430 }
431 }
432 #[doc = "Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode)"]
433 pub mod RTR {
434 pub const offset: u32 = 12;
435 pub const mask: u32 = 0x01 << offset;
436 pub mod R {}
437 pub mod W {}
438 pub mod RW {
439 #[doc = "Fixed or well tuned sampling clock"]
440 pub const RTR_0: u32 = 0;
441 #[doc = "Sampling clock needs re-tuning"]
442 pub const RTR_1: u32 = 0x01;
443 }
444 }
445 #[doc = "Tape Select Change Done"]
446 pub mod TSCD {
447 pub const offset: u32 = 15;
448 pub const mask: u32 = 0x01 << offset;
449 pub mod R {}
450 pub mod W {}
451 pub mod RW {
452 #[doc = "Delay cell select change is not finished."]
453 pub const TSCD_0: u32 = 0;
454 #[doc = "Delay cell select change is finished."]
455 pub const TSCD_1: u32 = 0x01;
456 }
457 }
458 #[doc = "Card Inserted"]
459 pub mod CINST {
460 pub const offset: u32 = 16;
461 pub const mask: u32 = 0x01 << offset;
462 pub mod R {}
463 pub mod W {}
464 pub mod RW {
465 #[doc = "Power on Reset or No Card"]
466 pub const CINST_0: u32 = 0;
467 #[doc = "Card Inserted"]
468 pub const CINST_1: u32 = 0x01;
469 }
470 }
471 #[doc = "Card Detect Pin Level"]
472 pub mod CDPL {
473 pub const offset: u32 = 18;
474 pub const mask: u32 = 0x01 << offset;
475 pub mod R {}
476 pub mod W {}
477 pub mod RW {
478 #[doc = "No card present (CD_B = 1)"]
479 pub const CDPL_0: u32 = 0;
480 #[doc = "Card present (CD_B = 0)"]
481 pub const CDPL_1: u32 = 0x01;
482 }
483 }
484 #[doc = "Write Protect Switch Pin Level"]
485 pub mod WPSPL {
486 pub const offset: u32 = 19;
487 pub const mask: u32 = 0x01 << offset;
488 pub mod R {}
489 pub mod W {}
490 pub mod RW {
491 #[doc = "Write protected (WP = 1)"]
492 pub const WPSPL_0: u32 = 0;
493 #[doc = "Write enabled (WP = 0)"]
494 pub const WPSPL_1: u32 = 0x01;
495 }
496 }
497 #[doc = "CMD Line Signal Level"]
498 pub mod CLSL {
499 pub const offset: u32 = 23;
500 pub const mask: u32 = 0x01 << offset;
501 pub mod R {}
502 pub mod W {}
503 pub mod RW {}
504 }
505 #[doc = "DATA\\[7:0\\] Line Signal Level"]
506 pub mod DLSL {
507 pub const offset: u32 = 24;
508 pub const mask: u32 = 0xff << offset;
509 pub mod R {}
510 pub mod W {}
511 pub mod RW {
512 #[doc = "Data 0 line signal level"]
513 pub const DATA0: u32 = 0;
514 #[doc = "Data 1 line signal level"]
515 pub const DATA1: u32 = 0x01;
516 #[doc = "Data 2 line signal level"]
517 pub const DATA2: u32 = 0x02;
518 #[doc = "Data 3 line signal level"]
519 pub const DATA3: u32 = 0x03;
520 #[doc = "Data 4 line signal level"]
521 pub const DATA4: u32 = 0x04;
522 #[doc = "Data 5 line signal level"]
523 pub const DATA5: u32 = 0x05;
524 #[doc = "Data 6 line signal level"]
525 pub const DATA6: u32 = 0x06;
526 #[doc = "Data 7 line signal level"]
527 pub const DATA7: u32 = 0x07;
528 }
529 }
530}
531#[doc = "Protocol Control"]
532pub mod PROT_CTRL {
533 #[doc = "LED Control"]
534 pub mod LCTL {
535 pub const offset: u32 = 0;
536 pub const mask: u32 = 0x01 << offset;
537 pub mod R {}
538 pub mod W {}
539 pub mod RW {
540 #[doc = "LED off"]
541 pub const LCTL_0: u32 = 0;
542 #[doc = "LED on"]
543 pub const LCTL_1: u32 = 0x01;
544 }
545 }
546 #[doc = "Data Transfer Width"]
547 pub mod DTW {
548 pub const offset: u32 = 1;
549 pub const mask: u32 = 0x03 << offset;
550 pub mod R {}
551 pub mod W {}
552 pub mod RW {
553 #[doc = "1-bit mode"]
554 pub const DTW_0: u32 = 0;
555 #[doc = "4-bit mode"]
556 pub const DTW_1: u32 = 0x01;
557 #[doc = "8-bit mode"]
558 pub const DTW_2: u32 = 0x02;
559 }
560 }
561 #[doc = "DATA3 as Card Detection Pin"]
562 pub mod D3CD {
563 pub const offset: u32 = 3;
564 pub const mask: u32 = 0x01 << offset;
565 pub mod R {}
566 pub mod W {}
567 pub mod RW {
568 #[doc = "DATA3 does not monitor Card Insertion"]
569 pub const D3CD_0: u32 = 0;
570 #[doc = "DATA3 as Card Detection Pin"]
571 pub const D3CD_1: u32 = 0x01;
572 }
573 }
574 #[doc = "Endian Mode"]
575 pub mod EMODE {
576 pub const offset: u32 = 4;
577 pub const mask: u32 = 0x03 << offset;
578 pub mod R {}
579 pub mod W {}
580 pub mod RW {
581 #[doc = "Big Endian Mode"]
582 pub const EMODE_0: u32 = 0;
583 #[doc = "Half Word Big Endian Mode"]
584 pub const EMODE_1: u32 = 0x01;
585 #[doc = "Little Endian Mode"]
586 pub const EMODE_2: u32 = 0x02;
587 }
588 }
589 #[doc = "Card Detect Test Level"]
590 pub mod CDTL {
591 pub const offset: u32 = 6;
592 pub const mask: u32 = 0x01 << offset;
593 pub mod R {}
594 pub mod W {}
595 pub mod RW {
596 #[doc = "Card Detect Test Level is 0, no card inserted"]
597 pub const CDTL_0: u32 = 0;
598 #[doc = "Card Detect Test Level is 1, card inserted"]
599 pub const CDTL_1: u32 = 0x01;
600 }
601 }
602 #[doc = "Card Detect Signal Selection"]
603 pub mod CDSS {
604 pub const offset: u32 = 7;
605 pub const mask: u32 = 0x01 << offset;
606 pub mod R {}
607 pub mod W {}
608 pub mod RW {
609 #[doc = "Card Detection Level is selected (for normal purpose)."]
610 pub const CDSS_0: u32 = 0;
611 #[doc = "Card Detection Test Level is selected (for test purpose)."]
612 pub const CDSS_1: u32 = 0x01;
613 }
614 }
615 #[doc = "DMA Select"]
616 pub mod DMASEL {
617 pub const offset: u32 = 8;
618 pub const mask: u32 = 0x03 << offset;
619 pub mod R {}
620 pub mod W {}
621 pub mod RW {
622 #[doc = "No DMA or Simple DMA is selected"]
623 pub const DMASEL_0: u32 = 0;
624 #[doc = "ADMA1 is selected"]
625 pub const DMASEL_1: u32 = 0x01;
626 #[doc = "ADMA2 is selected"]
627 pub const DMASEL_2: u32 = 0x02;
628 }
629 }
630 #[doc = "Stop At Block Gap Request"]
631 pub mod SABGREQ {
632 pub const offset: u32 = 16;
633 pub const mask: u32 = 0x01 << offset;
634 pub mod R {}
635 pub mod W {}
636 pub mod RW {
637 #[doc = "Transfer"]
638 pub const SABGREQ_0: u32 = 0;
639 #[doc = "Stop"]
640 pub const SABGREQ_1: u32 = 0x01;
641 }
642 }
643 #[doc = "Continue Request"]
644 pub mod CREQ {
645 pub const offset: u32 = 17;
646 pub const mask: u32 = 0x01 << offset;
647 pub mod R {}
648 pub mod W {}
649 pub mod RW {
650 #[doc = "No effect"]
651 pub const CREQ_0: u32 = 0;
652 #[doc = "Restart"]
653 pub const CREQ_1: u32 = 0x01;
654 }
655 }
656 #[doc = "Read Wait Control"]
657 pub mod RWCTL {
658 pub const offset: u32 = 18;
659 pub const mask: u32 = 0x01 << offset;
660 pub mod R {}
661 pub mod W {}
662 pub mod RW {
663 #[doc = "Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set"]
664 pub const RWCTL_0: u32 = 0;
665 #[doc = "Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set"]
666 pub const RWCTL_1: u32 = 0x01;
667 }
668 }
669 #[doc = "Interrupt At Block Gap"]
670 pub mod IABG {
671 pub const offset: u32 = 19;
672 pub const mask: u32 = 0x01 << offset;
673 pub mod R {}
674 pub mod W {}
675 pub mod RW {
676 #[doc = "Disabled"]
677 pub const IABG_0: u32 = 0;
678 #[doc = "Enabled"]
679 pub const IABG_1: u32 = 0x01;
680 }
681 }
682 #[doc = "RD_DONE_NO_8CLK"]
683 pub mod RD_DONE_NO_8CLK {
684 pub const offset: u32 = 20;
685 pub const mask: u32 = 0x01 << offset;
686 pub mod R {}
687 pub mod W {}
688 pub mod RW {}
689 }
690 #[doc = "Wakeup Event Enable On Card Interrupt"]
691 pub mod WECINT {
692 pub const offset: u32 = 24;
693 pub const mask: u32 = 0x01 << offset;
694 pub mod R {}
695 pub mod W {}
696 pub mod RW {
697 #[doc = "Disable"]
698 pub const WECINT_0: u32 = 0;
699 #[doc = "Enable"]
700 pub const WECINT_1: u32 = 0x01;
701 }
702 }
703 #[doc = "Wakeup Event Enable On SD Card Insertion"]
704 pub mod WECINS {
705 pub const offset: u32 = 25;
706 pub const mask: u32 = 0x01 << offset;
707 pub mod R {}
708 pub mod W {}
709 pub mod RW {
710 #[doc = "Disable"]
711 pub const WECINS_0: u32 = 0;
712 #[doc = "Enable"]
713 pub const WECINS_1: u32 = 0x01;
714 }
715 }
716 #[doc = "Wakeup Event Enable On SD Card Removal"]
717 pub mod WECRM {
718 pub const offset: u32 = 26;
719 pub const mask: u32 = 0x01 << offset;
720 pub mod R {}
721 pub mod W {}
722 pub mod RW {
723 #[doc = "Disable"]
724 pub const WECRM_0: u32 = 0;
725 #[doc = "Enable"]
726 pub const WECRM_1: u32 = 0x01;
727 }
728 }
729 #[doc = "BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP"]
730 pub mod BURST_LEN_EN {
731 pub const offset: u32 = 27;
732 pub const mask: u32 = 0x07 << offset;
733 pub mod R {}
734 pub mod W {}
735 pub mod RW {
736 #[doc = "Burst length is enabled for INCR"]
737 pub const BURST_LEN_EN_1: u32 = 0x01;
738 }
739 }
740 #[doc = "NON_EXACT_BLK_RD"]
741 pub mod NON_EXACT_BLK_RD {
742 pub const offset: u32 = 30;
743 pub const mask: u32 = 0x01 << offset;
744 pub mod R {}
745 pub mod W {}
746 pub mod RW {
747 #[doc = "The block read is exact block read. Host driver doesn't need to issue abort command to terminate this multi-block read."]
748 pub const NON_EXACT_BLK_RD_0: u32 = 0;
749 #[doc = "The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read."]
750 pub const NON_EXACT_BLK_RD_1: u32 = 0x01;
751 }
752 }
753}
754#[doc = "System Control"]
755pub mod SYS_CTRL {
756 #[doc = "Divisor"]
757 pub mod DVS {
758 pub const offset: u32 = 4;
759 pub const mask: u32 = 0x0f << offset;
760 pub mod R {}
761 pub mod W {}
762 pub mod RW {
763 #[doc = "Divide-by-1"]
764 pub const DVS_0: u32 = 0;
765 #[doc = "Divide-by-2"]
766 pub const DVS_1: u32 = 0x01;
767 #[doc = "Divide-by-15"]
768 pub const DVS_14: u32 = 0x0e;
769 #[doc = "Divide-by-16"]
770 pub const DVS_15: u32 = 0x0f;
771 }
772 }
773 #[doc = "SDCLK Frequency Select"]
774 pub mod SDCLKFS {
775 pub const offset: u32 = 8;
776 pub const mask: u32 = 0xff << offset;
777 pub mod R {}
778 pub mod W {}
779 pub mod RW {}
780 }
781 #[doc = "Data Timeout Counter Value"]
782 pub mod DTOCV {
783 pub const offset: u32 = 16;
784 pub const mask: u32 = 0x0f << offset;
785 pub mod R {}
786 pub mod W {}
787 pub mod RW {
788 #[doc = "SDCLK x 2 14"]
789 pub const DTOCV_0: u32 = 0;
790 #[doc = "SDCLK x 2 15"]
791 pub const DTOCV_1: u32 = 0x01;
792 #[doc = "SDCLK x 2 27"]
793 pub const DTOCV_13: u32 = 0x0d;
794 #[doc = "SDCLK x 2 28"]
795 pub const DTOCV_14: u32 = 0x0e;
796 #[doc = "SDCLK x 2 29"]
797 pub const DTOCV_15: u32 = 0x0f;
798 }
799 }
800 #[doc = "IPP_RST_N"]
801 pub mod IPP_RST_N {
802 pub const offset: u32 = 23;
803 pub const mask: u32 = 0x01 << offset;
804 pub mod R {}
805 pub mod W {}
806 pub mod RW {}
807 }
808 #[doc = "Software Reset For ALL"]
809 pub mod RSTA {
810 pub const offset: u32 = 24;
811 pub const mask: u32 = 0x01 << offset;
812 pub mod R {}
813 pub mod W {}
814 pub mod RW {
815 #[doc = "No Reset"]
816 pub const RSTA_0: u32 = 0;
817 #[doc = "Reset"]
818 pub const RSTA_1: u32 = 0x01;
819 }
820 }
821 #[doc = "Software Reset For CMD Line"]
822 pub mod RSTC {
823 pub const offset: u32 = 25;
824 pub const mask: u32 = 0x01 << offset;
825 pub mod R {}
826 pub mod W {}
827 pub mod RW {
828 #[doc = "No Reset"]
829 pub const RSTC_0: u32 = 0;
830 #[doc = "Reset"]
831 pub const RSTC_1: u32 = 0x01;
832 }
833 }
834 #[doc = "Software Reset For DATA Line"]
835 pub mod RSTD {
836 pub const offset: u32 = 26;
837 pub const mask: u32 = 0x01 << offset;
838 pub mod R {}
839 pub mod W {}
840 pub mod RW {
841 #[doc = "No Reset"]
842 pub const RSTD_0: u32 = 0;
843 #[doc = "Reset"]
844 pub const RSTD_1: u32 = 0x01;
845 }
846 }
847 #[doc = "Initialization Active"]
848 pub mod INITA {
849 pub const offset: u32 = 27;
850 pub const mask: u32 = 0x01 << offset;
851 pub mod R {}
852 pub mod W {}
853 pub mod RW {}
854 }
855 #[doc = "Reset Tuning"]
856 pub mod RSTT {
857 pub const offset: u32 = 28;
858 pub const mask: u32 = 0x01 << offset;
859 pub mod R {}
860 pub mod W {}
861 pub mod RW {}
862 }
863}
864#[doc = "Interrupt Status"]
865pub mod INT_STATUS {
866 #[doc = "Command Complete"]
867 pub mod CC {
868 pub const offset: u32 = 0;
869 pub const mask: u32 = 0x01 << offset;
870 pub mod R {}
871 pub mod W {}
872 pub mod RW {
873 #[doc = "Command not complete"]
874 pub const CC_0: u32 = 0;
875 #[doc = "Command complete"]
876 pub const CC_1: u32 = 0x01;
877 }
878 }
879 #[doc = "Transfer Complete"]
880 pub mod TC {
881 pub const offset: u32 = 1;
882 pub const mask: u32 = 0x01 << offset;
883 pub mod R {}
884 pub mod W {}
885 pub mod RW {
886 #[doc = "Transfer not complete"]
887 pub const TC_0: u32 = 0;
888 #[doc = "Transfer complete"]
889 pub const TC_1: u32 = 0x01;
890 }
891 }
892 #[doc = "Block Gap Event"]
893 pub mod BGE {
894 pub const offset: u32 = 2;
895 pub const mask: u32 = 0x01 << offset;
896 pub mod R {}
897 pub mod W {}
898 pub mod RW {
899 #[doc = "No block gap event"]
900 pub const BGE_0: u32 = 0;
901 #[doc = "Transaction stopped at block gap"]
902 pub const BGE_1: u32 = 0x01;
903 }
904 }
905 #[doc = "DMA Interrupt"]
906 pub mod DINT {
907 pub const offset: u32 = 3;
908 pub const mask: u32 = 0x01 << offset;
909 pub mod R {}
910 pub mod W {}
911 pub mod RW {
912 #[doc = "No DMA Interrupt"]
913 pub const DINT_0: u32 = 0;
914 #[doc = "DMA Interrupt is generated"]
915 pub const DINT_1: u32 = 0x01;
916 }
917 }
918 #[doc = "Buffer Write Ready"]
919 pub mod BWR {
920 pub const offset: u32 = 4;
921 pub const mask: u32 = 0x01 << offset;
922 pub mod R {}
923 pub mod W {}
924 pub mod RW {
925 #[doc = "Not ready to write buffer"]
926 pub const BWR_0: u32 = 0;
927 #[doc = "Ready to write buffer:"]
928 pub const BWR_1: u32 = 0x01;
929 }
930 }
931 #[doc = "Buffer Read Ready"]
932 pub mod BRR {
933 pub const offset: u32 = 5;
934 pub const mask: u32 = 0x01 << offset;
935 pub mod R {}
936 pub mod W {}
937 pub mod RW {
938 #[doc = "Not ready to read buffer"]
939 pub const BRR_0: u32 = 0;
940 #[doc = "Ready to read buffer"]
941 pub const BRR_1: u32 = 0x01;
942 }
943 }
944 #[doc = "Card Insertion"]
945 pub mod CINS {
946 pub const offset: u32 = 6;
947 pub const mask: u32 = 0x01 << offset;
948 pub mod R {}
949 pub mod W {}
950 pub mod RW {
951 #[doc = "Card state unstable or removed"]
952 pub const CINS_0: u32 = 0;
953 #[doc = "Card inserted"]
954 pub const CINS_1: u32 = 0x01;
955 }
956 }
957 #[doc = "Card Removal"]
958 pub mod CRM {
959 pub const offset: u32 = 7;
960 pub const mask: u32 = 0x01 << offset;
961 pub mod R {}
962 pub mod W {}
963 pub mod RW {
964 #[doc = "Card state unstable or inserted"]
965 pub const CRM_0: u32 = 0;
966 #[doc = "Card removed"]
967 pub const CRM_1: u32 = 0x01;
968 }
969 }
970 #[doc = "Card Interrupt"]
971 pub mod CINT {
972 pub const offset: u32 = 8;
973 pub const mask: u32 = 0x01 << offset;
974 pub mod R {}
975 pub mod W {}
976 pub mod RW {
977 #[doc = "No Card Interrupt"]
978 pub const CINT_0: u32 = 0;
979 #[doc = "Generate Card Interrupt"]
980 pub const CINT_1: u32 = 0x01;
981 }
982 }
983 #[doc = "Re-Tuning Event: (only for SD3.0 SDR104 mode and EMMC HS200 mode)"]
984 pub mod RTE {
985 pub const offset: u32 = 12;
986 pub const mask: u32 = 0x01 << offset;
987 pub mod R {}
988 pub mod W {}
989 pub mod RW {
990 #[doc = "Re-Tuning is not required"]
991 pub const RTE_0: u32 = 0;
992 #[doc = "Re-Tuning should be performed"]
993 pub const RTE_1: u32 = 0x01;
994 }
995 }
996 #[doc = "Tuning Pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode)"]
997 pub mod TP {
998 pub const offset: u32 = 14;
999 pub const mask: u32 = 0x01 << offset;
1000 pub mod R {}
1001 pub mod W {}
1002 pub mod RW {}
1003 }
1004 #[doc = "Command Timeout Error"]
1005 pub mod CTOE {
1006 pub const offset: u32 = 16;
1007 pub const mask: u32 = 0x01 << offset;
1008 pub mod R {}
1009 pub mod W {}
1010 pub mod RW {
1011 #[doc = "No Error"]
1012 pub const CTOE_0: u32 = 0;
1013 #[doc = "Time out"]
1014 pub const CTOE_1: u32 = 0x01;
1015 }
1016 }
1017 #[doc = "Command CRC Error"]
1018 pub mod CCE {
1019 pub const offset: u32 = 17;
1020 pub const mask: u32 = 0x01 << offset;
1021 pub mod R {}
1022 pub mod W {}
1023 pub mod RW {
1024 #[doc = "No Error"]
1025 pub const CCE_0: u32 = 0;
1026 #[doc = "CRC Error Generated."]
1027 pub const CCE_1: u32 = 0x01;
1028 }
1029 }
1030 #[doc = "Command End Bit Error"]
1031 pub mod CEBE {
1032 pub const offset: u32 = 18;
1033 pub const mask: u32 = 0x01 << offset;
1034 pub mod R {}
1035 pub mod W {}
1036 pub mod RW {
1037 #[doc = "No Error"]
1038 pub const CEBE_0: u32 = 0;
1039 #[doc = "End Bit Error Generated"]
1040 pub const CEBE_1: u32 = 0x01;
1041 }
1042 }
1043 #[doc = "Command Index Error"]
1044 pub mod CIE {
1045 pub const offset: u32 = 19;
1046 pub const mask: u32 = 0x01 << offset;
1047 pub mod R {}
1048 pub mod W {}
1049 pub mod RW {
1050 #[doc = "No Error"]
1051 pub const CIE_0: u32 = 0;
1052 #[doc = "Error"]
1053 pub const CIE_1: u32 = 0x01;
1054 }
1055 }
1056 #[doc = "Data Timeout Error"]
1057 pub mod DTOE {
1058 pub const offset: u32 = 20;
1059 pub const mask: u32 = 0x01 << offset;
1060 pub mod R {}
1061 pub mod W {}
1062 pub mod RW {
1063 #[doc = "No Error"]
1064 pub const DTOE_0: u32 = 0;
1065 #[doc = "Time out"]
1066 pub const DTOE_1: u32 = 0x01;
1067 }
1068 }
1069 #[doc = "Data CRC Error"]
1070 pub mod DCE {
1071 pub const offset: u32 = 21;
1072 pub const mask: u32 = 0x01 << offset;
1073 pub mod R {}
1074 pub mod W {}
1075 pub mod RW {
1076 #[doc = "No Error"]
1077 pub const DCE_0: u32 = 0;
1078 #[doc = "Error"]
1079 pub const DCE_1: u32 = 0x01;
1080 }
1081 }
1082 #[doc = "Data End Bit Error"]
1083 pub mod DEBE {
1084 pub const offset: u32 = 22;
1085 pub const mask: u32 = 0x01 << offset;
1086 pub mod R {}
1087 pub mod W {}
1088 pub mod RW {
1089 #[doc = "No Error"]
1090 pub const DEBE_0: u32 = 0;
1091 #[doc = "Error"]
1092 pub const DEBE_1: u32 = 0x01;
1093 }
1094 }
1095 #[doc = "Auto CMD12 Error"]
1096 pub mod AC12E {
1097 pub const offset: u32 = 24;
1098 pub const mask: u32 = 0x01 << offset;
1099 pub mod R {}
1100 pub mod W {}
1101 pub mod RW {
1102 #[doc = "No Error"]
1103 pub const AC12E_0: u32 = 0;
1104 #[doc = "Error"]
1105 pub const AC12E_1: u32 = 0x01;
1106 }
1107 }
1108 #[doc = "Tuning Error: (only for SD3.0 SDR104 mode and EMMC HS200 mode)"]
1109 pub mod TNE {
1110 pub const offset: u32 = 26;
1111 pub const mask: u32 = 0x01 << offset;
1112 pub mod R {}
1113 pub mod W {}
1114 pub mod RW {}
1115 }
1116 #[doc = "DMA Error"]
1117 pub mod DMAE {
1118 pub const offset: u32 = 28;
1119 pub const mask: u32 = 0x01 << offset;
1120 pub mod R {}
1121 pub mod W {}
1122 pub mod RW {
1123 #[doc = "No Error"]
1124 pub const DMAE_0: u32 = 0;
1125 #[doc = "Error"]
1126 pub const DMAE_1: u32 = 0x01;
1127 }
1128 }
1129}
1130#[doc = "Interrupt Status Enable"]
1131pub mod INT_STATUS_EN {
1132 #[doc = "Command Complete Status Enable"]
1133 pub mod CCSEN {
1134 pub const offset: u32 = 0;
1135 pub const mask: u32 = 0x01 << offset;
1136 pub mod R {}
1137 pub mod W {}
1138 pub mod RW {
1139 #[doc = "Masked"]
1140 pub const CCSEN_0: u32 = 0;
1141 #[doc = "Enabled"]
1142 pub const CCSEN_1: u32 = 0x01;
1143 }
1144 }
1145 #[doc = "Transfer Complete Status Enable"]
1146 pub mod TCSEN {
1147 pub const offset: u32 = 1;
1148 pub const mask: u32 = 0x01 << offset;
1149 pub mod R {}
1150 pub mod W {}
1151 pub mod RW {
1152 #[doc = "Masked"]
1153 pub const TCSEN_0: u32 = 0;
1154 #[doc = "Enabled"]
1155 pub const TCSEN_1: u32 = 0x01;
1156 }
1157 }
1158 #[doc = "Block Gap Event Status Enable"]
1159 pub mod BGESEN {
1160 pub const offset: u32 = 2;
1161 pub const mask: u32 = 0x01 << offset;
1162 pub mod R {}
1163 pub mod W {}
1164 pub mod RW {
1165 #[doc = "Masked"]
1166 pub const BGESEN_0: u32 = 0;
1167 #[doc = "Enabled"]
1168 pub const BGESEN_1: u32 = 0x01;
1169 }
1170 }
1171 #[doc = "DMA Interrupt Status Enable"]
1172 pub mod DINTSEN {
1173 pub const offset: u32 = 3;
1174 pub const mask: u32 = 0x01 << offset;
1175 pub mod R {}
1176 pub mod W {}
1177 pub mod RW {
1178 #[doc = "Masked"]
1179 pub const DINTSEN_0: u32 = 0;
1180 #[doc = "Enabled"]
1181 pub const DINTSEN_1: u32 = 0x01;
1182 }
1183 }
1184 #[doc = "Buffer Write Ready Status Enable"]
1185 pub mod BWRSEN {
1186 pub const offset: u32 = 4;
1187 pub const mask: u32 = 0x01 << offset;
1188 pub mod R {}
1189 pub mod W {}
1190 pub mod RW {
1191 #[doc = "Masked"]
1192 pub const BWRSEN_0: u32 = 0;
1193 #[doc = "Enabled"]
1194 pub const BWRSEN_1: u32 = 0x01;
1195 }
1196 }
1197 #[doc = "Buffer Read Ready Status Enable"]
1198 pub mod BRRSEN {
1199 pub const offset: u32 = 5;
1200 pub const mask: u32 = 0x01 << offset;
1201 pub mod R {}
1202 pub mod W {}
1203 pub mod RW {
1204 #[doc = "Masked"]
1205 pub const BRRSEN_0: u32 = 0;
1206 #[doc = "Enabled"]
1207 pub const BRRSEN_1: u32 = 0x01;
1208 }
1209 }
1210 #[doc = "Card Insertion Status Enable"]
1211 pub mod CINSSEN {
1212 pub const offset: u32 = 6;
1213 pub const mask: u32 = 0x01 << offset;
1214 pub mod R {}
1215 pub mod W {}
1216 pub mod RW {
1217 #[doc = "Masked"]
1218 pub const CINSSEN_0: u32 = 0;
1219 #[doc = "Enabled"]
1220 pub const CINSSEN_1: u32 = 0x01;
1221 }
1222 }
1223 #[doc = "Card Removal Status Enable"]
1224 pub mod CRMSEN {
1225 pub const offset: u32 = 7;
1226 pub const mask: u32 = 0x01 << offset;
1227 pub mod R {}
1228 pub mod W {}
1229 pub mod RW {
1230 #[doc = "Masked"]
1231 pub const CRMSEN_0: u32 = 0;
1232 #[doc = "Enabled"]
1233 pub const CRMSEN_1: u32 = 0x01;
1234 }
1235 }
1236 #[doc = "Card Interrupt Status Enable"]
1237 pub mod CINTSEN {
1238 pub const offset: u32 = 8;
1239 pub const mask: u32 = 0x01 << offset;
1240 pub mod R {}
1241 pub mod W {}
1242 pub mod RW {
1243 #[doc = "Masked"]
1244 pub const CINTSEN_0: u32 = 0;
1245 #[doc = "Enabled"]
1246 pub const CINTSEN_1: u32 = 0x01;
1247 }
1248 }
1249 #[doc = "Re-Tuning Event Status Enable"]
1250 pub mod RTESEN {
1251 pub const offset: u32 = 12;
1252 pub const mask: u32 = 0x01 << offset;
1253 pub mod R {}
1254 pub mod W {}
1255 pub mod RW {
1256 #[doc = "Masked"]
1257 pub const RTESEN_0: u32 = 0;
1258 #[doc = "Enabled"]
1259 pub const RTESEN_1: u32 = 0x01;
1260 }
1261 }
1262 #[doc = "Tuning Pass Status Enable"]
1263 pub mod TPSEN {
1264 pub const offset: u32 = 14;
1265 pub const mask: u32 = 0x01 << offset;
1266 pub mod R {}
1267 pub mod W {}
1268 pub mod RW {
1269 #[doc = "Masked"]
1270 pub const TPSEN_0: u32 = 0;
1271 #[doc = "Enabled"]
1272 pub const TPSEN_1: u32 = 0x01;
1273 }
1274 }
1275 #[doc = "Command Timeout Error Status Enable"]
1276 pub mod CTOESEN {
1277 pub const offset: u32 = 16;
1278 pub const mask: u32 = 0x01 << offset;
1279 pub mod R {}
1280 pub mod W {}
1281 pub mod RW {
1282 #[doc = "Masked"]
1283 pub const CTOESEN_0: u32 = 0;
1284 #[doc = "Enabled"]
1285 pub const CTOESEN_1: u32 = 0x01;
1286 }
1287 }
1288 #[doc = "Command CRC Error Status Enable"]
1289 pub mod CCESEN {
1290 pub const offset: u32 = 17;
1291 pub const mask: u32 = 0x01 << offset;
1292 pub mod R {}
1293 pub mod W {}
1294 pub mod RW {
1295 #[doc = "Masked"]
1296 pub const CCESEN_0: u32 = 0;
1297 #[doc = "Enabled"]
1298 pub const CCESEN_1: u32 = 0x01;
1299 }
1300 }
1301 #[doc = "Command End Bit Error Status Enable"]
1302 pub mod CEBESEN {
1303 pub const offset: u32 = 18;
1304 pub const mask: u32 = 0x01 << offset;
1305 pub mod R {}
1306 pub mod W {}
1307 pub mod RW {
1308 #[doc = "Masked"]
1309 pub const CEBESEN_0: u32 = 0;
1310 #[doc = "Enabled"]
1311 pub const CEBESEN_1: u32 = 0x01;
1312 }
1313 }
1314 #[doc = "Command Index Error Status Enable"]
1315 pub mod CIESEN {
1316 pub const offset: u32 = 19;
1317 pub const mask: u32 = 0x01 << offset;
1318 pub mod R {}
1319 pub mod W {}
1320 pub mod RW {
1321 #[doc = "Masked"]
1322 pub const CIESEN_0: u32 = 0;
1323 #[doc = "Enabled"]
1324 pub const CIESEN_1: u32 = 0x01;
1325 }
1326 }
1327 #[doc = "Data Timeout Error Status Enable"]
1328 pub mod DTOESEN {
1329 pub const offset: u32 = 20;
1330 pub const mask: u32 = 0x01 << offset;
1331 pub mod R {}
1332 pub mod W {}
1333 pub mod RW {
1334 #[doc = "Masked"]
1335 pub const DTOESEN_0: u32 = 0;
1336 #[doc = "Enabled"]
1337 pub const DTOESEN_1: u32 = 0x01;
1338 }
1339 }
1340 #[doc = "Data CRC Error Status Enable"]
1341 pub mod DCESEN {
1342 pub const offset: u32 = 21;
1343 pub const mask: u32 = 0x01 << offset;
1344 pub mod R {}
1345 pub mod W {}
1346 pub mod RW {
1347 #[doc = "Masked"]
1348 pub const DCESEN_0: u32 = 0;
1349 #[doc = "Enabled"]
1350 pub const DCESEN_1: u32 = 0x01;
1351 }
1352 }
1353 #[doc = "Data End Bit Error Status Enable"]
1354 pub mod DEBESEN {
1355 pub const offset: u32 = 22;
1356 pub const mask: u32 = 0x01 << offset;
1357 pub mod R {}
1358 pub mod W {}
1359 pub mod RW {
1360 #[doc = "Masked"]
1361 pub const DEBESEN_0: u32 = 0;
1362 #[doc = "Enabled"]
1363 pub const DEBESEN_1: u32 = 0x01;
1364 }
1365 }
1366 #[doc = "Auto CMD12 Error Status Enable"]
1367 pub mod AC12ESEN {
1368 pub const offset: u32 = 24;
1369 pub const mask: u32 = 0x01 << offset;
1370 pub mod R {}
1371 pub mod W {}
1372 pub mod RW {
1373 #[doc = "Masked"]
1374 pub const AC12ESEN_0: u32 = 0;
1375 #[doc = "Enabled"]
1376 pub const AC12ESEN_1: u32 = 0x01;
1377 }
1378 }
1379 #[doc = "Tuning Error Status Enable"]
1380 pub mod TNESEN {
1381 pub const offset: u32 = 26;
1382 pub const mask: u32 = 0x01 << offset;
1383 pub mod R {}
1384 pub mod W {}
1385 pub mod RW {
1386 #[doc = "Masked"]
1387 pub const TNESEN_0: u32 = 0;
1388 #[doc = "Enabled"]
1389 pub const TNESEN_1: u32 = 0x01;
1390 }
1391 }
1392 #[doc = "DMA Error Status Enable"]
1393 pub mod DMAESEN {
1394 pub const offset: u32 = 28;
1395 pub const mask: u32 = 0x01 << offset;
1396 pub mod R {}
1397 pub mod W {}
1398 pub mod RW {
1399 #[doc = "Masked"]
1400 pub const DMAESEN_0: u32 = 0;
1401 #[doc = "Enabled"]
1402 pub const DMAESEN_1: u32 = 0x01;
1403 }
1404 }
1405}
1406#[doc = "Interrupt Signal Enable"]
1407pub mod INT_SIGNAL_EN {
1408 #[doc = "Command Complete Interrupt Enable"]
1409 pub mod CCIEN {
1410 pub const offset: u32 = 0;
1411 pub const mask: u32 = 0x01 << offset;
1412 pub mod R {}
1413 pub mod W {}
1414 pub mod RW {
1415 #[doc = "Masked"]
1416 pub const CCIEN_0: u32 = 0;
1417 #[doc = "Enabled"]
1418 pub const CCIEN_1: u32 = 0x01;
1419 }
1420 }
1421 #[doc = "Transfer Complete Interrupt Enable"]
1422 pub mod TCIEN {
1423 pub const offset: u32 = 1;
1424 pub const mask: u32 = 0x01 << offset;
1425 pub mod R {}
1426 pub mod W {}
1427 pub mod RW {
1428 #[doc = "Masked"]
1429 pub const TCIEN_0: u32 = 0;
1430 #[doc = "Enabled"]
1431 pub const TCIEN_1: u32 = 0x01;
1432 }
1433 }
1434 #[doc = "Block Gap Event Interrupt Enable"]
1435 pub mod BGEIEN {
1436 pub const offset: u32 = 2;
1437 pub const mask: u32 = 0x01 << offset;
1438 pub mod R {}
1439 pub mod W {}
1440 pub mod RW {
1441 #[doc = "Masked"]
1442 pub const BGEIEN_0: u32 = 0;
1443 #[doc = "Enabled"]
1444 pub const BGEIEN_1: u32 = 0x01;
1445 }
1446 }
1447 #[doc = "DMA Interrupt Enable"]
1448 pub mod DINTIEN {
1449 pub const offset: u32 = 3;
1450 pub const mask: u32 = 0x01 << offset;
1451 pub mod R {}
1452 pub mod W {}
1453 pub mod RW {
1454 #[doc = "Masked"]
1455 pub const DINTIEN_0: u32 = 0;
1456 #[doc = "Enabled"]
1457 pub const DINTIEN_1: u32 = 0x01;
1458 }
1459 }
1460 #[doc = "Buffer Write Ready Interrupt Enable"]
1461 pub mod BWRIEN {
1462 pub const offset: u32 = 4;
1463 pub const mask: u32 = 0x01 << offset;
1464 pub mod R {}
1465 pub mod W {}
1466 pub mod RW {
1467 #[doc = "Masked"]
1468 pub const BWRIEN_0: u32 = 0;
1469 #[doc = "Enabled"]
1470 pub const BWRIEN_1: u32 = 0x01;
1471 }
1472 }
1473 #[doc = "Buffer Read Ready Interrupt Enable"]
1474 pub mod BRRIEN {
1475 pub const offset: u32 = 5;
1476 pub const mask: u32 = 0x01 << offset;
1477 pub mod R {}
1478 pub mod W {}
1479 pub mod RW {
1480 #[doc = "Masked"]
1481 pub const BRRIEN_0: u32 = 0;
1482 #[doc = "Enabled"]
1483 pub const BRRIEN_1: u32 = 0x01;
1484 }
1485 }
1486 #[doc = "Card Insertion Interrupt Enable"]
1487 pub mod CINSIEN {
1488 pub const offset: u32 = 6;
1489 pub const mask: u32 = 0x01 << offset;
1490 pub mod R {}
1491 pub mod W {}
1492 pub mod RW {
1493 #[doc = "Masked"]
1494 pub const CINSIEN_0: u32 = 0;
1495 #[doc = "Enabled"]
1496 pub const CINSIEN_1: u32 = 0x01;
1497 }
1498 }
1499 #[doc = "Card Removal Interrupt Enable"]
1500 pub mod CRMIEN {
1501 pub const offset: u32 = 7;
1502 pub const mask: u32 = 0x01 << offset;
1503 pub mod R {}
1504 pub mod W {}
1505 pub mod RW {
1506 #[doc = "Masked"]
1507 pub const CRMIEN_0: u32 = 0;
1508 #[doc = "Enabled"]
1509 pub const CRMIEN_1: u32 = 0x01;
1510 }
1511 }
1512 #[doc = "Card Interrupt Interrupt Enable"]
1513 pub mod CINTIEN {
1514 pub const offset: u32 = 8;
1515 pub const mask: u32 = 0x01 << offset;
1516 pub mod R {}
1517 pub mod W {}
1518 pub mod RW {
1519 #[doc = "Masked"]
1520 pub const CINTIEN_0: u32 = 0;
1521 #[doc = "Enabled"]
1522 pub const CINTIEN_1: u32 = 0x01;
1523 }
1524 }
1525 #[doc = "Re-Tuning Event Interrupt Enable"]
1526 pub mod RTEIEN {
1527 pub const offset: u32 = 12;
1528 pub const mask: u32 = 0x01 << offset;
1529 pub mod R {}
1530 pub mod W {}
1531 pub mod RW {
1532 #[doc = "Masked"]
1533 pub const RTEIEN_0: u32 = 0;
1534 #[doc = "Enabled"]
1535 pub const RTEIEN_1: u32 = 0x01;
1536 }
1537 }
1538 #[doc = "Tuning Pass Interrupt Enable"]
1539 pub mod TPIEN {
1540 pub const offset: u32 = 14;
1541 pub const mask: u32 = 0x01 << offset;
1542 pub mod R {}
1543 pub mod W {}
1544 pub mod RW {
1545 #[doc = "Masked"]
1546 pub const TPIEN_0: u32 = 0;
1547 #[doc = "Enabled"]
1548 pub const TPIEN_1: u32 = 0x01;
1549 }
1550 }
1551 #[doc = "Command Timeout Error Interrupt Enable"]
1552 pub mod CTOEIEN {
1553 pub const offset: u32 = 16;
1554 pub const mask: u32 = 0x01 << offset;
1555 pub mod R {}
1556 pub mod W {}
1557 pub mod RW {
1558 #[doc = "Masked"]
1559 pub const CTOEIEN_0: u32 = 0;
1560 #[doc = "Enabled"]
1561 pub const CTOEIEN_1: u32 = 0x01;
1562 }
1563 }
1564 #[doc = "Command CRC Error Interrupt Enable"]
1565 pub mod CCEIEN {
1566 pub const offset: u32 = 17;
1567 pub const mask: u32 = 0x01 << offset;
1568 pub mod R {}
1569 pub mod W {}
1570 pub mod RW {
1571 #[doc = "Masked"]
1572 pub const CCEIEN_0: u32 = 0;
1573 #[doc = "Enabled"]
1574 pub const CCEIEN_1: u32 = 0x01;
1575 }
1576 }
1577 #[doc = "Command End Bit Error Interrupt Enable"]
1578 pub mod CEBEIEN {
1579 pub const offset: u32 = 18;
1580 pub const mask: u32 = 0x01 << offset;
1581 pub mod R {}
1582 pub mod W {}
1583 pub mod RW {
1584 #[doc = "Masked"]
1585 pub const CEBEIEN_0: u32 = 0;
1586 #[doc = "Enabled"]
1587 pub const CEBEIEN_1: u32 = 0x01;
1588 }
1589 }
1590 #[doc = "Command Index Error Interrupt Enable"]
1591 pub mod CIEIEN {
1592 pub const offset: u32 = 19;
1593 pub const mask: u32 = 0x01 << offset;
1594 pub mod R {}
1595 pub mod W {}
1596 pub mod RW {
1597 #[doc = "Masked"]
1598 pub const CIEIEN_0: u32 = 0;
1599 #[doc = "Enabled"]
1600 pub const CIEIEN_1: u32 = 0x01;
1601 }
1602 }
1603 #[doc = "Data Timeout Error Interrupt Enable"]
1604 pub mod DTOEIEN {
1605 pub const offset: u32 = 20;
1606 pub const mask: u32 = 0x01 << offset;
1607 pub mod R {}
1608 pub mod W {}
1609 pub mod RW {
1610 #[doc = "Masked"]
1611 pub const DTOEIEN_0: u32 = 0;
1612 #[doc = "Enabled"]
1613 pub const DTOEIEN_1: u32 = 0x01;
1614 }
1615 }
1616 #[doc = "Data CRC Error Interrupt Enable"]
1617 pub mod DCEIEN {
1618 pub const offset: u32 = 21;
1619 pub const mask: u32 = 0x01 << offset;
1620 pub mod R {}
1621 pub mod W {}
1622 pub mod RW {
1623 #[doc = "Masked"]
1624 pub const DCEIEN_0: u32 = 0;
1625 #[doc = "Enabled"]
1626 pub const DCEIEN_1: u32 = 0x01;
1627 }
1628 }
1629 #[doc = "Data End Bit Error Interrupt Enable"]
1630 pub mod DEBEIEN {
1631 pub const offset: u32 = 22;
1632 pub const mask: u32 = 0x01 << offset;
1633 pub mod R {}
1634 pub mod W {}
1635 pub mod RW {
1636 #[doc = "Masked"]
1637 pub const DEBEIEN_0: u32 = 0;
1638 #[doc = "Enabled"]
1639 pub const DEBEIEN_1: u32 = 0x01;
1640 }
1641 }
1642 #[doc = "Auto CMD12 Error Interrupt Enable"]
1643 pub mod AC12EIEN {
1644 pub const offset: u32 = 24;
1645 pub const mask: u32 = 0x01 << offset;
1646 pub mod R {}
1647 pub mod W {}
1648 pub mod RW {
1649 #[doc = "Masked"]
1650 pub const AC12EIEN_0: u32 = 0;
1651 #[doc = "Enabled"]
1652 pub const AC12EIEN_1: u32 = 0x01;
1653 }
1654 }
1655 #[doc = "Tuning Error Interrupt Enable"]
1656 pub mod TNEIEN {
1657 pub const offset: u32 = 26;
1658 pub const mask: u32 = 0x01 << offset;
1659 pub mod R {}
1660 pub mod W {}
1661 pub mod RW {
1662 #[doc = "Masked"]
1663 pub const TNEIEN_0: u32 = 0;
1664 #[doc = "Enabled"]
1665 pub const TNEIEN_1: u32 = 0x01;
1666 }
1667 }
1668 #[doc = "DMA Error Interrupt Enable"]
1669 pub mod DMAEIEN {
1670 pub const offset: u32 = 28;
1671 pub const mask: u32 = 0x01 << offset;
1672 pub mod R {}
1673 pub mod W {}
1674 pub mod RW {
1675 #[doc = "Masked"]
1676 pub const DMAEIEN_0: u32 = 0;
1677 #[doc = "Enable"]
1678 pub const DMAEIEN_1: u32 = 0x01;
1679 }
1680 }
1681}
1682#[doc = "Auto CMD12 Error Status"]
1683pub mod AUTOCMD12_ERR_STATUS {
1684 #[doc = "Auto CMD12 Not Executed"]
1685 pub mod AC12NE {
1686 pub const offset: u32 = 0;
1687 pub const mask: u32 = 0x01 << offset;
1688 pub mod R {}
1689 pub mod W {}
1690 pub mod RW {
1691 #[doc = "Executed"]
1692 pub const AC12NE_0: u32 = 0;
1693 #[doc = "Not executed"]
1694 pub const AC12NE_1: u32 = 0x01;
1695 }
1696 }
1697 #[doc = "Auto CMD12 / 23 Timeout Error"]
1698 pub mod AC12TOE {
1699 pub const offset: u32 = 1;
1700 pub const mask: u32 = 0x01 << offset;
1701 pub mod R {}
1702 pub mod W {}
1703 pub mod RW {
1704 #[doc = "No error"]
1705 pub const AC12TOE_0: u32 = 0;
1706 #[doc = "Time out"]
1707 pub const AC12TOE_1: u32 = 0x01;
1708 }
1709 }
1710 #[doc = "Auto CMD12 / 23 End Bit Error"]
1711 pub mod AC12EBE {
1712 pub const offset: u32 = 2;
1713 pub const mask: u32 = 0x01 << offset;
1714 pub mod R {}
1715 pub mod W {}
1716 pub mod RW {
1717 #[doc = "No error"]
1718 pub const AC12EBE_0: u32 = 0;
1719 #[doc = "End Bit Error Generated"]
1720 pub const AC12EBE_1: u32 = 0x01;
1721 }
1722 }
1723 #[doc = "Auto CMD12 / 23 CRC Error"]
1724 pub mod AC12CE {
1725 pub const offset: u32 = 3;
1726 pub const mask: u32 = 0x01 << offset;
1727 pub mod R {}
1728 pub mod W {}
1729 pub mod RW {
1730 #[doc = "No CRC error"]
1731 pub const AC12CE_0: u32 = 0;
1732 #[doc = "CRC Error Met in Auto CMD12/23 Response"]
1733 pub const AC12CE_1: u32 = 0x01;
1734 }
1735 }
1736 #[doc = "Auto CMD12 / 23 Index Error"]
1737 pub mod AC12IE {
1738 pub const offset: u32 = 4;
1739 pub const mask: u32 = 0x01 << offset;
1740 pub mod R {}
1741 pub mod W {}
1742 pub mod RW {
1743 #[doc = "No error"]
1744 pub const AC12IE_0: u32 = 0;
1745 #[doc = "Error, the CMD index in response is not CMD12/23"]
1746 pub const AC12IE_1: u32 = 0x01;
1747 }
1748 }
1749 #[doc = "Command Not Issued By Auto CMD12 Error"]
1750 pub mod CNIBAC12E {
1751 pub const offset: u32 = 7;
1752 pub const mask: u32 = 0x01 << offset;
1753 pub mod R {}
1754 pub mod W {}
1755 pub mod RW {
1756 #[doc = "No error"]
1757 pub const CNIBAC12E_0: u32 = 0;
1758 #[doc = "Not Issued"]
1759 pub const CNIBAC12E_1: u32 = 0x01;
1760 }
1761 }
1762 #[doc = "Execute Tuning"]
1763 pub mod EXECUTE_TUNING {
1764 pub const offset: u32 = 22;
1765 pub const mask: u32 = 0x01 << offset;
1766 pub mod R {}
1767 pub mod W {}
1768 pub mod RW {}
1769 }
1770 #[doc = "Sample Clock Select"]
1771 pub mod SMP_CLK_SEL {
1772 pub const offset: u32 = 23;
1773 pub const mask: u32 = 0x01 << offset;
1774 pub mod R {}
1775 pub mod W {}
1776 pub mod RW {
1777 #[doc = "Fixed clock is used to sample data"]
1778 pub const SMP_CLK_SEL_0: u32 = 0;
1779 #[doc = "Tuned clock is used to sample data"]
1780 pub const SMP_CLK_SEL_1: u32 = 0x01;
1781 }
1782 }
1783}
1784#[doc = "Host Controller Capabilities"]
1785pub mod HOST_CTRL_CAP {
1786 #[doc = "SDR50 support"]
1787 pub mod SDR50_SUPPORT {
1788 pub const offset: u32 = 0;
1789 pub const mask: u32 = 0x01 << offset;
1790 pub mod R {}
1791 pub mod W {}
1792 pub mod RW {}
1793 }
1794 #[doc = "SDR104 support"]
1795 pub mod SDR104_SUPPORT {
1796 pub const offset: u32 = 1;
1797 pub const mask: u32 = 0x01 << offset;
1798 pub mod R {}
1799 pub mod W {}
1800 pub mod RW {}
1801 }
1802 #[doc = "DDR50 support"]
1803 pub mod DDR50_SUPPORT {
1804 pub const offset: u32 = 2;
1805 pub const mask: u32 = 0x01 << offset;
1806 pub mod R {}
1807 pub mod W {}
1808 pub mod RW {}
1809 }
1810 #[doc = "Time Counter for Retuning"]
1811 pub mod TIME_COUNT_RETUNING {
1812 pub const offset: u32 = 8;
1813 pub const mask: u32 = 0x0f << offset;
1814 pub mod R {}
1815 pub mod W {}
1816 pub mod RW {}
1817 }
1818 #[doc = "Use Tuning for SDR50"]
1819 pub mod USE_TUNING_SDR50 {
1820 pub const offset: u32 = 13;
1821 pub const mask: u32 = 0x01 << offset;
1822 pub mod R {}
1823 pub mod W {}
1824 pub mod RW {
1825 #[doc = "SDR does not require tuning"]
1826 pub const USE_TUNING_SDR50_0: u32 = 0;
1827 #[doc = "SDR50 requires tuning"]
1828 pub const USE_TUNING_SDR50_1: u32 = 0x01;
1829 }
1830 }
1831 #[doc = "Retuning Mode"]
1832 pub mod RETUNING_MODE {
1833 pub const offset: u32 = 14;
1834 pub const mask: u32 = 0x03 << offset;
1835 pub mod R {}
1836 pub mod W {}
1837 pub mod RW {
1838 #[doc = "Mode 1"]
1839 pub const RETUNING_MODE_0: u32 = 0;
1840 #[doc = "Mode 2"]
1841 pub const RETUNING_MODE_1: u32 = 0x01;
1842 #[doc = "Mode 3"]
1843 pub const RETUNING_MODE_2: u32 = 0x02;
1844 }
1845 }
1846 #[doc = "Max Block Length"]
1847 pub mod MBL {
1848 pub const offset: u32 = 16;
1849 pub const mask: u32 = 0x07 << offset;
1850 pub mod R {}
1851 pub mod W {}
1852 pub mod RW {
1853 #[doc = "512 bytes"]
1854 pub const MBL_0: u32 = 0;
1855 #[doc = "1024 bytes"]
1856 pub const MBL_1: u32 = 0x01;
1857 #[doc = "2048 bytes"]
1858 pub const MBL_2: u32 = 0x02;
1859 #[doc = "4096 bytes"]
1860 pub const MBL_3: u32 = 0x03;
1861 }
1862 }
1863 #[doc = "ADMA Support"]
1864 pub mod ADMAS {
1865 pub const offset: u32 = 20;
1866 pub const mask: u32 = 0x01 << offset;
1867 pub mod R {}
1868 pub mod W {}
1869 pub mod RW {
1870 #[doc = "Advanced DMA Not supported"]
1871 pub const ADMAS_0: u32 = 0;
1872 #[doc = "Advanced DMA Supported"]
1873 pub const ADMAS_1: u32 = 0x01;
1874 }
1875 }
1876 #[doc = "High Speed Support"]
1877 pub mod HSS {
1878 pub const offset: u32 = 21;
1879 pub const mask: u32 = 0x01 << offset;
1880 pub mod R {}
1881 pub mod W {}
1882 pub mod RW {
1883 #[doc = "High Speed Not Supported"]
1884 pub const HSS_0: u32 = 0;
1885 #[doc = "High Speed Supported"]
1886 pub const HSS_1: u32 = 0x01;
1887 }
1888 }
1889 #[doc = "DMA Support"]
1890 pub mod DMAS {
1891 pub const offset: u32 = 22;
1892 pub const mask: u32 = 0x01 << offset;
1893 pub mod R {}
1894 pub mod W {}
1895 pub mod RW {
1896 #[doc = "DMA not supported"]
1897 pub const DMAS_0: u32 = 0;
1898 #[doc = "DMA Supported"]
1899 pub const DMAS_1: u32 = 0x01;
1900 }
1901 }
1902 #[doc = "Suspend / Resume Support"]
1903 pub mod SRS {
1904 pub const offset: u32 = 23;
1905 pub const mask: u32 = 0x01 << offset;
1906 pub mod R {}
1907 pub mod W {}
1908 pub mod RW {
1909 #[doc = "Not supported"]
1910 pub const SRS_0: u32 = 0;
1911 #[doc = "Supported"]
1912 pub const SRS_1: u32 = 0x01;
1913 }
1914 }
1915 #[doc = "Voltage Support 3.3V"]
1916 pub mod VS33 {
1917 pub const offset: u32 = 24;
1918 pub const mask: u32 = 0x01 << offset;
1919 pub mod R {}
1920 pub mod W {}
1921 pub mod RW {
1922 #[doc = "3.3V not supported"]
1923 pub const VS33_0: u32 = 0;
1924 #[doc = "3.3V supported"]
1925 pub const VS33_1: u32 = 0x01;
1926 }
1927 }
1928 #[doc = "Voltage Support 3.0 V"]
1929 pub mod VS30 {
1930 pub const offset: u32 = 25;
1931 pub const mask: u32 = 0x01 << offset;
1932 pub mod R {}
1933 pub mod W {}
1934 pub mod RW {
1935 #[doc = "3.0V not supported"]
1936 pub const VS30_0: u32 = 0;
1937 #[doc = "3.0V supported"]
1938 pub const VS30_1: u32 = 0x01;
1939 }
1940 }
1941 #[doc = "Voltage Support 1.8 V"]
1942 pub mod VS18 {
1943 pub const offset: u32 = 26;
1944 pub const mask: u32 = 0x01 << offset;
1945 pub mod R {}
1946 pub mod W {}
1947 pub mod RW {
1948 #[doc = "1.8V not supported"]
1949 pub const VS18_0: u32 = 0;
1950 #[doc = "1.8V supported"]
1951 pub const VS18_1: u32 = 0x01;
1952 }
1953 }
1954}
1955#[doc = "Watermark Level"]
1956pub mod WTMK_LVL {
1957 #[doc = "Read Watermark Level"]
1958 pub mod RD_WML {
1959 pub const offset: u32 = 0;
1960 pub const mask: u32 = 0xff << offset;
1961 pub mod R {}
1962 pub mod W {}
1963 pub mod RW {}
1964 }
1965 #[doc = "Read Burst Length Due to system restriction, the actual burst length may not exceed 16."]
1966 pub mod RD_BRST_LEN {
1967 pub const offset: u32 = 8;
1968 pub const mask: u32 = 0x1f << offset;
1969 pub mod R {}
1970 pub mod W {}
1971 pub mod RW {}
1972 }
1973 #[doc = "Write Watermark Level"]
1974 pub mod WR_WML {
1975 pub const offset: u32 = 16;
1976 pub const mask: u32 = 0xff << offset;
1977 pub mod R {}
1978 pub mod W {}
1979 pub mod RW {}
1980 }
1981 #[doc = "Write Burst Length Due to system restriction, the actual burst length may not exceed 16."]
1982 pub mod WR_BRST_LEN {
1983 pub const offset: u32 = 24;
1984 pub const mask: u32 = 0x1f << offset;
1985 pub mod R {}
1986 pub mod W {}
1987 pub mod RW {}
1988 }
1989}
1990#[doc = "Mixer Control"]
1991pub mod MIX_CTRL {
1992 #[doc = "DMA Enable"]
1993 pub mod DMAEN {
1994 pub const offset: u32 = 0;
1995 pub const mask: u32 = 0x01 << offset;
1996 pub mod R {}
1997 pub mod W {}
1998 pub mod RW {
1999 #[doc = "Disable"]
2000 pub const DMAEN_0: u32 = 0;
2001 #[doc = "Enable"]
2002 pub const DMAEN_1: u32 = 0x01;
2003 }
2004 }
2005 #[doc = "Block Count Enable"]
2006 pub mod BCEN {
2007 pub const offset: u32 = 1;
2008 pub const mask: u32 = 0x01 << offset;
2009 pub mod R {}
2010 pub mod W {}
2011 pub mod RW {
2012 #[doc = "Disable"]
2013 pub const BCEN_0: u32 = 0;
2014 #[doc = "Enable"]
2015 pub const BCEN_1: u32 = 0x01;
2016 }
2017 }
2018 #[doc = "Auto CMD12 Enable"]
2019 pub mod AC12EN {
2020 pub const offset: u32 = 2;
2021 pub const mask: u32 = 0x01 << offset;
2022 pub mod R {}
2023 pub mod W {}
2024 pub mod RW {
2025 #[doc = "Disable"]
2026 pub const AC12EN_0: u32 = 0;
2027 #[doc = "Enable"]
2028 pub const AC12EN_1: u32 = 0x01;
2029 }
2030 }
2031 #[doc = "Dual Data Rate mode selection"]
2032 pub mod DDR_EN {
2033 pub const offset: u32 = 3;
2034 pub const mask: u32 = 0x01 << offset;
2035 pub mod R {}
2036 pub mod W {}
2037 pub mod RW {}
2038 }
2039 #[doc = "Data Transfer Direction Select"]
2040 pub mod DTDSEL {
2041 pub const offset: u32 = 4;
2042 pub const mask: u32 = 0x01 << offset;
2043 pub mod R {}
2044 pub mod W {}
2045 pub mod RW {
2046 #[doc = "Write (Host to Card)"]
2047 pub const DTDSEL_0: u32 = 0;
2048 #[doc = "Read (Card to Host)"]
2049 pub const DTDSEL_1: u32 = 0x01;
2050 }
2051 }
2052 #[doc = "Multi / Single Block Select"]
2053 pub mod MSBSEL {
2054 pub const offset: u32 = 5;
2055 pub const mask: u32 = 0x01 << offset;
2056 pub mod R {}
2057 pub mod W {}
2058 pub mod RW {
2059 #[doc = "Single Block"]
2060 pub const MSBSEL_0: u32 = 0;
2061 #[doc = "Multiple Blocks"]
2062 pub const MSBSEL_1: u32 = 0x01;
2063 }
2064 }
2065 #[doc = "NIBBLE_POS"]
2066 pub mod NIBBLE_POS {
2067 pub const offset: u32 = 6;
2068 pub const mask: u32 = 0x01 << offset;
2069 pub mod R {}
2070 pub mod W {}
2071 pub mod RW {}
2072 }
2073 #[doc = "Auto CMD23 Enable"]
2074 pub mod AC23EN {
2075 pub const offset: u32 = 7;
2076 pub const mask: u32 = 0x01 << offset;
2077 pub mod R {}
2078 pub mod W {}
2079 pub mod RW {}
2080 }
2081 #[doc = "Execute Tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)"]
2082 pub mod EXE_TUNE {
2083 pub const offset: u32 = 22;
2084 pub const mask: u32 = 0x01 << offset;
2085 pub mod R {}
2086 pub mod W {}
2087 pub mod RW {
2088 #[doc = "Not Tuned or Tuning Completed"]
2089 pub const EXE_TUNE_0: u32 = 0;
2090 #[doc = "Execute Tuning"]
2091 pub const EXE_TUNE_1: u32 = 0x01;
2092 }
2093 }
2094 #[doc = "SMP_CLK_SEL"]
2095 pub mod SMP_CLK_SEL {
2096 pub const offset: u32 = 23;
2097 pub const mask: u32 = 0x01 << offset;
2098 pub mod R {}
2099 pub mod W {}
2100 pub mod RW {
2101 #[doc = "Fixed clock is used to sample data / cmd"]
2102 pub const SMP_CLK_SEL_0: u32 = 0;
2103 #[doc = "Tuned clock is used to sample data / cmd"]
2104 pub const SMP_CLK_SEL_1: u32 = 0x01;
2105 }
2106 }
2107 #[doc = "Auto Tuning Enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode)"]
2108 pub mod AUTO_TUNE_EN {
2109 pub const offset: u32 = 24;
2110 pub const mask: u32 = 0x01 << offset;
2111 pub mod R {}
2112 pub mod W {}
2113 pub mod RW {
2114 #[doc = "Disable auto tuning"]
2115 pub const AUTO_TUNE_EN_0: u32 = 0;
2116 #[doc = "Enable auto tuning"]
2117 pub const AUTO_TUNE_EN_1: u32 = 0x01;
2118 }
2119 }
2120 #[doc = "Feedback Clock Source Selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)"]
2121 pub mod FBCLK_SEL {
2122 pub const offset: u32 = 25;
2123 pub const mask: u32 = 0x01 << offset;
2124 pub mod R {}
2125 pub mod W {}
2126 pub mod RW {
2127 #[doc = "Feedback clock comes from the loopback CLK"]
2128 pub const FBCLK_SEL_0: u32 = 0;
2129 #[doc = "Feedback clock comes from the ipp_card_clk_out"]
2130 pub const FBCLK_SEL_1: u32 = 0x01;
2131 }
2132 }
2133}
2134#[doc = "Force Event"]
2135pub mod FORCE_EVENT {
2136 #[doc = "Force Event Auto Command 12 Not Executed"]
2137 pub mod FEVTAC12NE {
2138 pub const offset: u32 = 0;
2139 pub const mask: u32 = 0x01 << offset;
2140 pub mod R {}
2141 pub mod W {}
2142 pub mod RW {}
2143 }
2144 #[doc = "Force Event Auto Command 12 Time Out Error"]
2145 pub mod FEVTAC12TOE {
2146 pub const offset: u32 = 1;
2147 pub const mask: u32 = 0x01 << offset;
2148 pub mod R {}
2149 pub mod W {}
2150 pub mod RW {}
2151 }
2152 #[doc = "Force Event Auto Command 12 CRC Error"]
2153 pub mod FEVTAC12CE {
2154 pub const offset: u32 = 2;
2155 pub const mask: u32 = 0x01 << offset;
2156 pub mod R {}
2157 pub mod W {}
2158 pub mod RW {}
2159 }
2160 #[doc = "Force Event Auto Command 12 End Bit Error"]
2161 pub mod FEVTAC12EBE {
2162 pub const offset: u32 = 3;
2163 pub const mask: u32 = 0x01 << offset;
2164 pub mod R {}
2165 pub mod W {}
2166 pub mod RW {}
2167 }
2168 #[doc = "Force Event Auto Command 12 Index Error"]
2169 pub mod FEVTAC12IE {
2170 pub const offset: u32 = 4;
2171 pub const mask: u32 = 0x01 << offset;
2172 pub mod R {}
2173 pub mod W {}
2174 pub mod RW {}
2175 }
2176 #[doc = "Force Event Command Not Executed By Auto Command 12 Error"]
2177 pub mod FEVTCNIBAC12E {
2178 pub const offset: u32 = 7;
2179 pub const mask: u32 = 0x01 << offset;
2180 pub mod R {}
2181 pub mod W {}
2182 pub mod RW {}
2183 }
2184 #[doc = "Force Event Command Time Out Error"]
2185 pub mod FEVTCTOE {
2186 pub const offset: u32 = 16;
2187 pub const mask: u32 = 0x01 << offset;
2188 pub mod R {}
2189 pub mod W {}
2190 pub mod RW {}
2191 }
2192 #[doc = "Force Event Command CRC Error"]
2193 pub mod FEVTCCE {
2194 pub const offset: u32 = 17;
2195 pub const mask: u32 = 0x01 << offset;
2196 pub mod R {}
2197 pub mod W {}
2198 pub mod RW {}
2199 }
2200 #[doc = "Force Event Command End Bit Error"]
2201 pub mod FEVTCEBE {
2202 pub const offset: u32 = 18;
2203 pub const mask: u32 = 0x01 << offset;
2204 pub mod R {}
2205 pub mod W {}
2206 pub mod RW {}
2207 }
2208 #[doc = "Force Event Command Index Error"]
2209 pub mod FEVTCIE {
2210 pub const offset: u32 = 19;
2211 pub const mask: u32 = 0x01 << offset;
2212 pub mod R {}
2213 pub mod W {}
2214 pub mod RW {}
2215 }
2216 #[doc = "Force Event Data Time Out Error"]
2217 pub mod FEVTDTOE {
2218 pub const offset: u32 = 20;
2219 pub const mask: u32 = 0x01 << offset;
2220 pub mod R {}
2221 pub mod W {}
2222 pub mod RW {}
2223 }
2224 #[doc = "Force Event Data CRC Error"]
2225 pub mod FEVTDCE {
2226 pub const offset: u32 = 21;
2227 pub const mask: u32 = 0x01 << offset;
2228 pub mod R {}
2229 pub mod W {}
2230 pub mod RW {}
2231 }
2232 #[doc = "Force Event Data End Bit Error"]
2233 pub mod FEVTDEBE {
2234 pub const offset: u32 = 22;
2235 pub const mask: u32 = 0x01 << offset;
2236 pub mod R {}
2237 pub mod W {}
2238 pub mod RW {}
2239 }
2240 #[doc = "Force Event Auto Command 12 Error"]
2241 pub mod FEVTAC12E {
2242 pub const offset: u32 = 24;
2243 pub const mask: u32 = 0x01 << offset;
2244 pub mod R {}
2245 pub mod W {}
2246 pub mod RW {}
2247 }
2248 #[doc = "Force Tuning Error"]
2249 pub mod FEVTTNE {
2250 pub const offset: u32 = 26;
2251 pub const mask: u32 = 0x01 << offset;
2252 pub mod R {}
2253 pub mod W {}
2254 pub mod RW {}
2255 }
2256 #[doc = "Force Event DMA Error"]
2257 pub mod FEVTDMAE {
2258 pub const offset: u32 = 28;
2259 pub const mask: u32 = 0x01 << offset;
2260 pub mod R {}
2261 pub mod W {}
2262 pub mod RW {}
2263 }
2264 #[doc = "Force Event Card Interrupt"]
2265 pub mod FEVTCINT {
2266 pub const offset: u32 = 31;
2267 pub const mask: u32 = 0x01 << offset;
2268 pub mod R {}
2269 pub mod W {}
2270 pub mod RW {}
2271 }
2272}
2273#[doc = "ADMA Error Status Register"]
2274pub mod ADMA_ERR_STATUS {
2275 #[doc = "ADMA Error State (when ADMA Error is occurred)"]
2276 pub mod ADMAES {
2277 pub const offset: u32 = 0;
2278 pub const mask: u32 = 0x03 << offset;
2279 pub mod R {}
2280 pub mod W {}
2281 pub mod RW {}
2282 }
2283 #[doc = "ADMA Length Mismatch Error"]
2284 pub mod ADMALME {
2285 pub const offset: u32 = 2;
2286 pub const mask: u32 = 0x01 << offset;
2287 pub mod R {}
2288 pub mod W {}
2289 pub mod RW {
2290 #[doc = "No Error"]
2291 pub const ADMALME_0: u32 = 0;
2292 #[doc = "Error"]
2293 pub const ADMALME_1: u32 = 0x01;
2294 }
2295 }
2296 #[doc = "ADMA Descriptor Error"]
2297 pub mod ADMADCE {
2298 pub const offset: u32 = 3;
2299 pub const mask: u32 = 0x01 << offset;
2300 pub mod R {}
2301 pub mod W {}
2302 pub mod RW {
2303 #[doc = "No Error"]
2304 pub const ADMADCE_0: u32 = 0;
2305 #[doc = "Error"]
2306 pub const ADMADCE_1: u32 = 0x01;
2307 }
2308 }
2309}
2310#[doc = "ADMA System Address"]
2311pub mod ADMA_SYS_ADDR {
2312 #[doc = "ADMA System Address"]
2313 pub mod ADS_ADDR {
2314 pub const offset: u32 = 2;
2315 pub const mask: u32 = 0x3fff_ffff << offset;
2316 pub mod R {}
2317 pub mod W {}
2318 pub mod RW {}
2319 }
2320}
2321#[doc = "DLL (Delay Line) Control"]
2322pub mod DLL_CTRL {
2323 #[doc = "DLL_CTRL_ENABLE"]
2324 pub mod DLL_CTRL_ENABLE {
2325 pub const offset: u32 = 0;
2326 pub const mask: u32 = 0x01 << offset;
2327 pub mod R {}
2328 pub mod W {}
2329 pub mod RW {}
2330 }
2331 #[doc = "DLL_CTRL_RESET"]
2332 pub mod DLL_CTRL_RESET {
2333 pub const offset: u32 = 1;
2334 pub const mask: u32 = 0x01 << offset;
2335 pub mod R {}
2336 pub mod W {}
2337 pub mod RW {}
2338 }
2339 #[doc = "DLL_CTRL_SLV_FORCE_UPD"]
2340 pub mod DLL_CTRL_SLV_FORCE_UPD {
2341 pub const offset: u32 = 2;
2342 pub const mask: u32 = 0x01 << offset;
2343 pub mod R {}
2344 pub mod W {}
2345 pub mod RW {}
2346 }
2347 #[doc = "DLL_CTRL_SLV_DLY_TARGET0"]
2348 pub mod DLL_CTRL_SLV_DLY_TARGET0 {
2349 pub const offset: u32 = 3;
2350 pub const mask: u32 = 0x0f << offset;
2351 pub mod R {}
2352 pub mod W {}
2353 pub mod RW {}
2354 }
2355 #[doc = "DLL_CTRL_GATE_UPDATE"]
2356 pub mod DLL_CTRL_GATE_UPDATE {
2357 pub const offset: u32 = 7;
2358 pub const mask: u32 = 0x01 << offset;
2359 pub mod R {}
2360 pub mod W {}
2361 pub mod RW {}
2362 }
2363 #[doc = "DLL_CTRL_SLV_OVERRIDE"]
2364 pub mod DLL_CTRL_SLV_OVERRIDE {
2365 pub const offset: u32 = 8;
2366 pub const mask: u32 = 0x01 << offset;
2367 pub mod R {}
2368 pub mod W {}
2369 pub mod RW {}
2370 }
2371 #[doc = "DLL_CTRL_SLV_OVERRIDE_VAL"]
2372 pub mod DLL_CTRL_SLV_OVERRIDE_VAL {
2373 pub const offset: u32 = 9;
2374 pub const mask: u32 = 0x7f << offset;
2375 pub mod R {}
2376 pub mod W {}
2377 pub mod RW {}
2378 }
2379 #[doc = "DLL_CTRL_SLV_DLY_TARGET1"]
2380 pub mod DLL_CTRL_SLV_DLY_TARGET1 {
2381 pub const offset: u32 = 16;
2382 pub const mask: u32 = 0x07 << offset;
2383 pub mod R {}
2384 pub mod W {}
2385 pub mod RW {}
2386 }
2387 #[doc = "DLL_CTRL_SLV_UPDATE_INT"]
2388 pub mod DLL_CTRL_SLV_UPDATE_INT {
2389 pub const offset: u32 = 20;
2390 pub const mask: u32 = 0xff << offset;
2391 pub mod R {}
2392 pub mod W {}
2393 pub mod RW {}
2394 }
2395 #[doc = "DLL_CTRL_REF_UPDATE_INT"]
2396 pub mod DLL_CTRL_REF_UPDATE_INT {
2397 pub const offset: u32 = 28;
2398 pub const mask: u32 = 0x0f << offset;
2399 pub mod R {}
2400 pub mod W {}
2401 pub mod RW {}
2402 }
2403}
2404#[doc = "DLL Status"]
2405pub mod DLL_STATUS {
2406 #[doc = "DLL_STS_SLV_LOCK"]
2407 pub mod DLL_STS_SLV_LOCK {
2408 pub const offset: u32 = 0;
2409 pub const mask: u32 = 0x01 << offset;
2410 pub mod R {}
2411 pub mod W {}
2412 pub mod RW {}
2413 }
2414 #[doc = "DLL_STS_REF_LOCK"]
2415 pub mod DLL_STS_REF_LOCK {
2416 pub const offset: u32 = 1;
2417 pub const mask: u32 = 0x01 << offset;
2418 pub mod R {}
2419 pub mod W {}
2420 pub mod RW {}
2421 }
2422 #[doc = "DLL_STS_SLV_SEL"]
2423 pub mod DLL_STS_SLV_SEL {
2424 pub const offset: u32 = 2;
2425 pub const mask: u32 = 0x7f << offset;
2426 pub mod R {}
2427 pub mod W {}
2428 pub mod RW {}
2429 }
2430 #[doc = "DLL_STS_REF_SEL"]
2431 pub mod DLL_STS_REF_SEL {
2432 pub const offset: u32 = 9;
2433 pub const mask: u32 = 0x7f << offset;
2434 pub mod R {}
2435 pub mod W {}
2436 pub mod RW {}
2437 }
2438}
2439#[doc = "CLK Tuning Control and Status"]
2440pub mod CLK_TUNE_CTRL_STATUS {
2441 #[doc = "DLY_CELL_SET_POST"]
2442 pub mod DLY_CELL_SET_POST {
2443 pub const offset: u32 = 0;
2444 pub const mask: u32 = 0x0f << offset;
2445 pub mod R {}
2446 pub mod W {}
2447 pub mod RW {}
2448 }
2449 #[doc = "DLY_CELL_SET_OUT"]
2450 pub mod DLY_CELL_SET_OUT {
2451 pub const offset: u32 = 4;
2452 pub const mask: u32 = 0x0f << offset;
2453 pub mod R {}
2454 pub mod W {}
2455 pub mod RW {}
2456 }
2457 #[doc = "DLY_CELL_SET_PRE"]
2458 pub mod DLY_CELL_SET_PRE {
2459 pub const offset: u32 = 8;
2460 pub const mask: u32 = 0x7f << offset;
2461 pub mod R {}
2462 pub mod W {}
2463 pub mod RW {}
2464 }
2465 #[doc = "NXT_ERR"]
2466 pub mod NXT_ERR {
2467 pub const offset: u32 = 15;
2468 pub const mask: u32 = 0x01 << offset;
2469 pub mod R {}
2470 pub mod W {}
2471 pub mod RW {}
2472 }
2473 #[doc = "TAP_SEL_POST"]
2474 pub mod TAP_SEL_POST {
2475 pub const offset: u32 = 16;
2476 pub const mask: u32 = 0x0f << offset;
2477 pub mod R {}
2478 pub mod W {}
2479 pub mod RW {}
2480 }
2481 #[doc = "TAP_SEL_OUT"]
2482 pub mod TAP_SEL_OUT {
2483 pub const offset: u32 = 20;
2484 pub const mask: u32 = 0x0f << offset;
2485 pub mod R {}
2486 pub mod W {}
2487 pub mod RW {}
2488 }
2489 #[doc = "TAP_SEL_PRE"]
2490 pub mod TAP_SEL_PRE {
2491 pub const offset: u32 = 24;
2492 pub const mask: u32 = 0x7f << offset;
2493 pub mod R {}
2494 pub mod W {}
2495 pub mod RW {}
2496 }
2497 #[doc = "PRE_ERR"]
2498 pub mod PRE_ERR {
2499 pub const offset: u32 = 31;
2500 pub const mask: u32 = 0x01 << offset;
2501 pub mod R {}
2502 pub mod W {}
2503 pub mod RW {}
2504 }
2505}
2506#[doc = "Vendor Specific Register"]
2507pub mod VEND_SPEC {
2508 #[doc = "Voltage Selection"]
2509 pub mod VSELECT {
2510 pub const offset: u32 = 1;
2511 pub const mask: u32 = 0x01 << offset;
2512 pub mod R {}
2513 pub mod W {}
2514 pub mod RW {
2515 #[doc = "Change the voltage to high voltage range, around 3.0 V"]
2516 pub const VSELECT_0: u32 = 0;
2517 #[doc = "Change the voltage to low voltage range, around 1.8 V"]
2518 pub const VSELECT_1: u32 = 0x01;
2519 }
2520 }
2521 #[doc = "Conflict check enable."]
2522 pub mod CONFLICT_CHK_EN {
2523 pub const offset: u32 = 2;
2524 pub const mask: u32 = 0x01 << offset;
2525 pub mod R {}
2526 pub mod W {}
2527 pub mod RW {
2528 #[doc = "Conflict check disable"]
2529 pub const CONFLICT_CHK_EN_0: u32 = 0;
2530 #[doc = "Conflict check enable"]
2531 pub const CONFLICT_CHK_EN_1: u32 = 0x01;
2532 }
2533 }
2534 #[doc = "AC12_WR_CHKBUSY_EN"]
2535 pub mod AC12_WR_CHKBUSY_EN {
2536 pub const offset: u32 = 3;
2537 pub const mask: u32 = 0x01 << offset;
2538 pub mod R {}
2539 pub mod W {}
2540 pub mod RW {
2541 #[doc = "Do not check busy after auto CMD12 for write data packet"]
2542 pub const AC12_WR_CHKBUSY_EN_0: u32 = 0;
2543 #[doc = "Check busy after auto CMD12 for write data packet"]
2544 pub const AC12_WR_CHKBUSY_EN_1: u32 = 0x01;
2545 }
2546 }
2547 #[doc = "FRC_SDCLK_ON"]
2548 pub mod FRC_SDCLK_ON {
2549 pub const offset: u32 = 8;
2550 pub const mask: u32 = 0x01 << offset;
2551 pub mod R {}
2552 pub mod W {}
2553 pub mod RW {
2554 #[doc = "CLK active or inactive is fully controlled by the hardware."]
2555 pub const FRC_SDCLK_ON_0: u32 = 0;
2556 #[doc = "Force CLK active."]
2557 pub const FRC_SDCLK_ON_1: u32 = 0x01;
2558 }
2559 }
2560 #[doc = "CRC Check Disable"]
2561 pub mod CRC_CHK_DIS {
2562 pub const offset: u32 = 15;
2563 pub const mask: u32 = 0x01 << offset;
2564 pub mod R {}
2565 pub mod W {}
2566 pub mod RW {
2567 #[doc = "Check CRC16 for every read data packet and check CRC bits for every write data packet"]
2568 pub const CRC_CHK_DIS_0: u32 = 0;
2569 #[doc = "Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet"]
2570 pub const CRC_CHK_DIS_1: u32 = 0x01;
2571 }
2572 }
2573 #[doc = "CMD_BYTE_EN"]
2574 pub mod CMD_BYTE_EN {
2575 pub const offset: u32 = 31;
2576 pub const mask: u32 = 0x01 << offset;
2577 pub mod R {}
2578 pub mod W {}
2579 pub mod RW {
2580 #[doc = "Disable"]
2581 pub const CMD_BYTE_EN_0: u32 = 0;
2582 #[doc = "Enable"]
2583 pub const CMD_BYTE_EN_1: u32 = 0x01;
2584 }
2585 }
2586}
2587#[doc = "MMC Boot Register"]
2588pub mod MMC_BOOT {
2589 #[doc = "DTOCV_ACK"]
2590 pub mod DTOCV_ACK {
2591 pub const offset: u32 = 0;
2592 pub const mask: u32 = 0x0f << offset;
2593 pub mod R {}
2594 pub mod W {}
2595 pub mod RW {
2596 #[doc = "SDCLK x 2^14"]
2597 pub const DTOCV_ACK_0: u32 = 0;
2598 #[doc = "SDCLK x 2^15"]
2599 pub const DTOCV_ACK_1: u32 = 0x01;
2600 #[doc = "SDCLK x 2^16"]
2601 pub const DTOCV_ACK_2: u32 = 0x02;
2602 #[doc = "SDCLK x 2^17"]
2603 pub const DTOCV_ACK_3: u32 = 0x03;
2604 #[doc = "SDCLK x 2^18"]
2605 pub const DTOCV_ACK_4: u32 = 0x04;
2606 #[doc = "SDCLK x 2^19"]
2607 pub const DTOCV_ACK_5: u32 = 0x05;
2608 #[doc = "SDCLK x 2^20"]
2609 pub const DTOCV_ACK_6: u32 = 0x06;
2610 #[doc = "SDCLK x 2^21"]
2611 pub const DTOCV_ACK_7: u32 = 0x07;
2612 #[doc = "SDCLK x 2^28"]
2613 pub const DTOCV_ACK_14: u32 = 0x0e;
2614 #[doc = "SDCLK x 2^29"]
2615 pub const DTOCV_ACK_15: u32 = 0x0f;
2616 }
2617 }
2618 #[doc = "BOOT_ACK"]
2619 pub mod BOOT_ACK {
2620 pub const offset: u32 = 4;
2621 pub const mask: u32 = 0x01 << offset;
2622 pub mod R {}
2623 pub mod W {}
2624 pub mod RW {
2625 #[doc = "No ack"]
2626 pub const BOOT_ACK_0: u32 = 0;
2627 #[doc = "Ack"]
2628 pub const BOOT_ACK_1: u32 = 0x01;
2629 }
2630 }
2631 #[doc = "BOOT_MODE"]
2632 pub mod BOOT_MODE {
2633 pub const offset: u32 = 5;
2634 pub const mask: u32 = 0x01 << offset;
2635 pub mod R {}
2636 pub mod W {}
2637 pub mod RW {
2638 #[doc = "Normal boot"]
2639 pub const BOOT_MODE_0: u32 = 0;
2640 #[doc = "Alternative boot"]
2641 pub const BOOT_MODE_1: u32 = 0x01;
2642 }
2643 }
2644 #[doc = "BOOT_EN"]
2645 pub mod BOOT_EN {
2646 pub const offset: u32 = 6;
2647 pub const mask: u32 = 0x01 << offset;
2648 pub mod R {}
2649 pub mod W {}
2650 pub mod RW {
2651 #[doc = "Fast boot disable"]
2652 pub const BOOT_EN_0: u32 = 0;
2653 #[doc = "Fast boot enable"]
2654 pub const BOOT_EN_1: u32 = 0x01;
2655 }
2656 }
2657 #[doc = "AUTO_SABG_EN"]
2658 pub mod AUTO_SABG_EN {
2659 pub const offset: u32 = 7;
2660 pub const mask: u32 = 0x01 << offset;
2661 pub mod R {}
2662 pub mod W {}
2663 pub mod RW {}
2664 }
2665 #[doc = "Disable Time Out"]
2666 pub mod DISABLE_TIME_OUT {
2667 pub const offset: u32 = 8;
2668 pub const mask: u32 = 0x01 << offset;
2669 pub mod R {}
2670 pub mod W {}
2671 pub mod RW {
2672 #[doc = "Enable time out"]
2673 pub const DISABLE_TIME_OUT_0: u32 = 0;
2674 #[doc = "Disable time out"]
2675 pub const DISABLE_TIME_OUT_1: u32 = 0x01;
2676 }
2677 }
2678 #[doc = "BOOT_BLK_CNT"]
2679 pub mod BOOT_BLK_CNT {
2680 pub const offset: u32 = 16;
2681 pub const mask: u32 = 0xffff << offset;
2682 pub mod R {}
2683 pub mod W {}
2684 pub mod RW {}
2685 }
2686}
2687#[doc = "Vendor Specific 2 Register"]
2688pub mod VEND_SPEC2 {
2689 #[doc = "Card Interrupt Detection Test"]
2690 pub mod CARD_INT_D3_TEST {
2691 pub const offset: u32 = 3;
2692 pub const mask: u32 = 0x01 << offset;
2693 pub mod R {}
2694 pub mod W {}
2695 pub mod RW {
2696 #[doc = "Check the card interrupt only when DATA3 is high."]
2697 pub const CARD_INT_D3_TEST_0: u32 = 0;
2698 #[doc = "Check the card interrupt by ignoring the status of DATA3."]
2699 pub const CARD_INT_D3_TEST_1: u32 = 0x01;
2700 }
2701 }
2702 #[doc = "TUNING_8bit_EN"]
2703 pub mod TUNING_8BIT_EN {
2704 pub const offset: u32 = 4;
2705 pub const mask: u32 = 0x01 << offset;
2706 pub mod R {}
2707 pub mod W {}
2708 pub mod RW {}
2709 }
2710 #[doc = "TUNING_1bit_EN"]
2711 pub mod TUNING_1BIT_EN {
2712 pub const offset: u32 = 5;
2713 pub const mask: u32 = 0x01 << offset;
2714 pub mod R {}
2715 pub mod W {}
2716 pub mod RW {}
2717 }
2718 #[doc = "TUNING_CMD_EN"]
2719 pub mod TUNING_CMD_EN {
2720 pub const offset: u32 = 6;
2721 pub const mask: u32 = 0x01 << offset;
2722 pub mod R {}
2723 pub mod W {}
2724 pub mod RW {
2725 #[doc = "Auto tuning circuit does not check the CMD line."]
2726 pub const TUNING_CMD_EN_0: u32 = 0;
2727 #[doc = "Auto tuning circuit checks the CMD line."]
2728 pub const TUNING_CMD_EN_1: u32 = 0x01;
2729 }
2730 }
2731 #[doc = "Argument2 register enable for ACMD23"]
2732 pub mod ACMD23_ARGU2_EN {
2733 pub const offset: u32 = 12;
2734 pub const mask: u32 = 0x01 << offset;
2735 pub mod R {}
2736 pub mod W {}
2737 pub mod RW {
2738 #[doc = "Disable"]
2739 pub const ACMD23_ARGU2_EN_0: u32 = 0;
2740 #[doc = "Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enable."]
2741 pub const ACMD23_ARGU2_EN_1: u32 = 0x01;
2742 }
2743 }
2744 #[doc = "debug for part dll"]
2745 pub mod PART_DLL_DEBUG {
2746 pub const offset: u32 = 13;
2747 pub const mask: u32 = 0x01 << offset;
2748 pub mod R {}
2749 pub mod W {}
2750 pub mod RW {}
2751 }
2752 #[doc = "BUS reset"]
2753 pub mod BUS_RST {
2754 pub const offset: u32 = 14;
2755 pub const mask: u32 = 0x01 << offset;
2756 pub mod R {}
2757 pub mod W {}
2758 pub mod RW {}
2759 }
2760}
2761#[doc = "Tuning Control Register"]
2762pub mod TUNING_CTRL {
2763 #[doc = "TUNING_START_TAP"]
2764 pub mod TUNING_START_TAP {
2765 pub const offset: u32 = 0;
2766 pub const mask: u32 = 0xff << offset;
2767 pub mod R {}
2768 pub mod W {}
2769 pub mod RW {}
2770 }
2771 #[doc = "TUNING_COUNTER"]
2772 pub mod TUNING_COUNTER {
2773 pub const offset: u32 = 8;
2774 pub const mask: u32 = 0xff << offset;
2775 pub mod R {}
2776 pub mod W {}
2777 pub mod RW {}
2778 }
2779 #[doc = "TUNING_STEP"]
2780 pub mod TUNING_STEP {
2781 pub const offset: u32 = 16;
2782 pub const mask: u32 = 0x07 << offset;
2783 pub mod R {}
2784 pub mod W {}
2785 pub mod RW {}
2786 }
2787 #[doc = "TUNING_WINDOW"]
2788 pub mod TUNING_WINDOW {
2789 pub const offset: u32 = 20;
2790 pub const mask: u32 = 0x07 << offset;
2791 pub mod R {}
2792 pub mod W {}
2793 pub mod RW {}
2794 }
2795 #[doc = "STD_TUNING_EN"]
2796 pub mod STD_TUNING_EN {
2797 pub const offset: u32 = 24;
2798 pub const mask: u32 = 0x01 << offset;
2799 pub mod R {}
2800 pub mod W {}
2801 pub mod RW {}
2802 }
2803}