imxrt_ral/blocks/imxrt1051/
adc_etc.rs1#[doc = "ADC_ETC"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "ADC_ETC Global Control Register"]
5 pub CTRL: crate::RWRegister<u32>,
6 #[doc = "ETC DONE0 and DONE1 IRQ State Register"]
7 pub DONE0_1_IRQ: crate::RWRegister<u32>,
8 #[doc = "ETC DONE_2 and DONE_ERR IRQ State Register"]
9 pub DONE2_ERR_IRQ: crate::RWRegister<u32>,
10 #[doc = "ETC DMA control Register"]
11 pub DMA_CTRL: crate::RWRegister<u32>,
12 #[doc = "ETC_TRIG0 Control Register"]
13 pub TRIG0_CTRL: crate::RWRegister<u32>,
14 #[doc = "ETC_TRIG0 Counter Register"]
15 pub TRIG0_COUNTER: crate::RWRegister<u32>,
16 #[doc = "ETC_TRIG Chain 0/1 Register"]
17 pub TRIG0_CHAIN_1_0: crate::RWRegister<u32>,
18 #[doc = "ETC_TRIG Chain 2/3 Register"]
19 pub TRIG0_CHAIN_3_2: crate::RWRegister<u32>,
20 #[doc = "ETC_TRIG Chain 4/5 Register"]
21 pub TRIG0_CHAIN_5_4: crate::RWRegister<u32>,
22 #[doc = "ETC_TRIG Chain 6/7 Register"]
23 pub TRIG0_CHAIN_7_6: crate::RWRegister<u32>,
24 #[doc = "ETC_TRIG Result Data 1/0 Register"]
25 pub TRIG0_RESULT_1_0: crate::RORegister<u32>,
26 #[doc = "ETC_TRIG Result Data 3/2 Register"]
27 pub TRIG0_RESULT_3_2: crate::RORegister<u32>,
28 #[doc = "ETC_TRIG Result Data 5/4 Register"]
29 pub TRIG0_RESULT_5_4: crate::RORegister<u32>,
30 #[doc = "ETC_TRIG Result Data 7/6 Register"]
31 pub TRIG0_RESULT_7_6: crate::RORegister<u32>,
32 #[doc = "ETC_TRIG1 Control Register"]
33 pub TRIG1_CTRL: crate::RWRegister<u32>,
34 #[doc = "ETC_TRIG1 Counter Register"]
35 pub TRIG1_COUNTER: crate::RWRegister<u32>,
36 #[doc = "ETC_TRIG Chain 0/1 Register"]
37 pub TRIG1_CHAIN_1_0: crate::RWRegister<u32>,
38 #[doc = "ETC_TRIG Chain 2/3 Register"]
39 pub TRIG1_CHAIN_3_2: crate::RWRegister<u32>,
40 #[doc = "ETC_TRIG Chain 4/5 Register"]
41 pub TRIG1_CHAIN_5_4: crate::RWRegister<u32>,
42 #[doc = "ETC_TRIG Chain 6/7 Register"]
43 pub TRIG1_CHAIN_7_6: crate::RWRegister<u32>,
44 #[doc = "ETC_TRIG Result Data 1/0 Register"]
45 pub TRIG1_RESULT_1_0: crate::RORegister<u32>,
46 #[doc = "ETC_TRIG Result Data 3/2 Register"]
47 pub TRIG1_RESULT_3_2: crate::RORegister<u32>,
48 #[doc = "ETC_TRIG Result Data 5/4 Register"]
49 pub TRIG1_RESULT_5_4: crate::RORegister<u32>,
50 #[doc = "ETC_TRIG Result Data 7/6 Register"]
51 pub TRIG1_RESULT_7_6: crate::RORegister<u32>,
52 #[doc = "ETC_TRIG2 Control Register"]
53 pub TRIG2_CTRL: crate::RWRegister<u32>,
54 #[doc = "ETC_TRIG2 Counter Register"]
55 pub TRIG2_COUNTER: crate::RWRegister<u32>,
56 #[doc = "ETC_TRIG Chain 0/1 Register"]
57 pub TRIG2_CHAIN_1_0: crate::RWRegister<u32>,
58 #[doc = "ETC_TRIG Chain 2/3 Register"]
59 pub TRIG2_CHAIN_3_2: crate::RWRegister<u32>,
60 #[doc = "ETC_TRIG Chain 4/5 Register"]
61 pub TRIG2_CHAIN_5_4: crate::RWRegister<u32>,
62 #[doc = "ETC_TRIG Chain 6/7 Register"]
63 pub TRIG2_CHAIN_7_6: crate::RWRegister<u32>,
64 #[doc = "ETC_TRIG Result Data 1/0 Register"]
65 pub TRIG2_RESULT_1_0: crate::RORegister<u32>,
66 #[doc = "ETC_TRIG Result Data 3/2 Register"]
67 pub TRIG2_RESULT_3_2: crate::RORegister<u32>,
68 #[doc = "ETC_TRIG Result Data 5/4 Register"]
69 pub TRIG2_RESULT_5_4: crate::RORegister<u32>,
70 #[doc = "ETC_TRIG Result Data 7/6 Register"]
71 pub TRIG2_RESULT_7_6: crate::RORegister<u32>,
72 #[doc = "ETC_TRIG3 Control Register"]
73 pub TRIG3_CTRL: crate::RWRegister<u32>,
74 #[doc = "ETC_TRIG3 Counter Register"]
75 pub TRIG3_COUNTER: crate::RWRegister<u32>,
76 #[doc = "ETC_TRIG Chain 0/1 Register"]
77 pub TRIG3_CHAIN_1_0: crate::RWRegister<u32>,
78 #[doc = "ETC_TRIG Chain 2/3 Register"]
79 pub TRIG3_CHAIN_3_2: crate::RWRegister<u32>,
80 #[doc = "ETC_TRIG Chain 4/5 Register"]
81 pub TRIG3_CHAIN_5_4: crate::RWRegister<u32>,
82 #[doc = "ETC_TRIG Chain 6/7 Register"]
83 pub TRIG3_CHAIN_7_6: crate::RWRegister<u32>,
84 #[doc = "ETC_TRIG Result Data 1/0 Register"]
85 pub TRIG3_RESULT_1_0: crate::RORegister<u32>,
86 #[doc = "ETC_TRIG Result Data 3/2 Register"]
87 pub TRIG3_RESULT_3_2: crate::RORegister<u32>,
88 #[doc = "ETC_TRIG Result Data 5/4 Register"]
89 pub TRIG3_RESULT_5_4: crate::RORegister<u32>,
90 #[doc = "ETC_TRIG Result Data 7/6 Register"]
91 pub TRIG3_RESULT_7_6: crate::RORegister<u32>,
92 #[doc = "ETC_TRIG4 Control Register"]
93 pub TRIG4_CTRL: crate::RWRegister<u32>,
94 #[doc = "ETC_TRIG4 Counter Register"]
95 pub TRIG4_COUNTER: crate::RWRegister<u32>,
96 #[doc = "ETC_TRIG Chain 0/1 Register"]
97 pub TRIG4_CHAIN_1_0: crate::RWRegister<u32>,
98 #[doc = "ETC_TRIG Chain 2/3 Register"]
99 pub TRIG4_CHAIN_3_2: crate::RWRegister<u32>,
100 #[doc = "ETC_TRIG Chain 4/5 Register"]
101 pub TRIG4_CHAIN_5_4: crate::RWRegister<u32>,
102 #[doc = "ETC_TRIG Chain 6/7 Register"]
103 pub TRIG4_CHAIN_7_6: crate::RWRegister<u32>,
104 #[doc = "ETC_TRIG Result Data 1/0 Register"]
105 pub TRIG4_RESULT_1_0: crate::RORegister<u32>,
106 #[doc = "ETC_TRIG Result Data 3/2 Register"]
107 pub TRIG4_RESULT_3_2: crate::RORegister<u32>,
108 #[doc = "ETC_TRIG Result Data 5/4 Register"]
109 pub TRIG4_RESULT_5_4: crate::RORegister<u32>,
110 #[doc = "ETC_TRIG Result Data 7/6 Register"]
111 pub TRIG4_RESULT_7_6: crate::RORegister<u32>,
112 #[doc = "ETC_TRIG5 Control Register"]
113 pub TRIG5_CTRL: crate::RWRegister<u32>,
114 #[doc = "ETC_TRIG5 Counter Register"]
115 pub TRIG5_COUNTER: crate::RWRegister<u32>,
116 #[doc = "ETC_TRIG Chain 0/1 Register"]
117 pub TRIG5_CHAIN_1_0: crate::RWRegister<u32>,
118 #[doc = "ETC_TRIG Chain 2/3 Register"]
119 pub TRIG5_CHAIN_3_2: crate::RWRegister<u32>,
120 #[doc = "ETC_TRIG Chain 4/5 Register"]
121 pub TRIG5_CHAIN_5_4: crate::RWRegister<u32>,
122 #[doc = "ETC_TRIG Chain 6/7 Register"]
123 pub TRIG5_CHAIN_7_6: crate::RWRegister<u32>,
124 #[doc = "ETC_TRIG Result Data 1/0 Register"]
125 pub TRIG5_RESULT_1_0: crate::RORegister<u32>,
126 #[doc = "ETC_TRIG Result Data 3/2 Register"]
127 pub TRIG5_RESULT_3_2: crate::RORegister<u32>,
128 #[doc = "ETC_TRIG Result Data 5/4 Register"]
129 pub TRIG5_RESULT_5_4: crate::RORegister<u32>,
130 #[doc = "ETC_TRIG Result Data 7/6 Register"]
131 pub TRIG5_RESULT_7_6: crate::RORegister<u32>,
132 #[doc = "ETC_TRIG6 Control Register"]
133 pub TRIG6_CTRL: crate::RWRegister<u32>,
134 #[doc = "ETC_TRIG6 Counter Register"]
135 pub TRIG6_COUNTER: crate::RWRegister<u32>,
136 #[doc = "ETC_TRIG Chain 0/1 Register"]
137 pub TRIG6_CHAIN_1_0: crate::RWRegister<u32>,
138 #[doc = "ETC_TRIG Chain 2/3 Register"]
139 pub TRIG6_CHAIN_3_2: crate::RWRegister<u32>,
140 #[doc = "ETC_TRIG Chain 4/5 Register"]
141 pub TRIG6_CHAIN_5_4: crate::RWRegister<u32>,
142 #[doc = "ETC_TRIG Chain 6/7 Register"]
143 pub TRIG6_CHAIN_7_6: crate::RWRegister<u32>,
144 #[doc = "ETC_TRIG Result Data 1/0 Register"]
145 pub TRIG6_RESULT_1_0: crate::RORegister<u32>,
146 #[doc = "ETC_TRIG Result Data 3/2 Register"]
147 pub TRIG6_RESULT_3_2: crate::RORegister<u32>,
148 #[doc = "ETC_TRIG Result Data 5/4 Register"]
149 pub TRIG6_RESULT_5_4: crate::RORegister<u32>,
150 #[doc = "ETC_TRIG Result Data 7/6 Register"]
151 pub TRIG6_RESULT_7_6: crate::RORegister<u32>,
152 #[doc = "ETC_TRIG7 Control Register"]
153 pub TRIG7_CTRL: crate::RWRegister<u32>,
154 #[doc = "ETC_TRIG7 Counter Register"]
155 pub TRIG7_COUNTER: crate::RWRegister<u32>,
156 #[doc = "ETC_TRIG Chain 0/1 Register"]
157 pub TRIG7_CHAIN_1_0: crate::RWRegister<u32>,
158 #[doc = "ETC_TRIG Chain 2/3 Register"]
159 pub TRIG7_CHAIN_3_2: crate::RWRegister<u32>,
160 #[doc = "ETC_TRIG Chain 4/5 Register"]
161 pub TRIG7_CHAIN_5_4: crate::RWRegister<u32>,
162 #[doc = "ETC_TRIG Chain 6/7 Register"]
163 pub TRIG7_CHAIN_7_6: crate::RWRegister<u32>,
164 #[doc = "ETC_TRIG Result Data 1/0 Register"]
165 pub TRIG7_RESULT_1_0: crate::RORegister<u32>,
166 #[doc = "ETC_TRIG Result Data 3/2 Register"]
167 pub TRIG7_RESULT_3_2: crate::RORegister<u32>,
168 #[doc = "ETC_TRIG Result Data 5/4 Register"]
169 pub TRIG7_RESULT_5_4: crate::RORegister<u32>,
170 #[doc = "ETC_TRIG Result Data 7/6 Register"]
171 pub TRIG7_RESULT_7_6: crate::RORegister<u32>,
172}
173#[doc = "ADC_ETC Global Control Register"]
174pub mod CTRL {
175 #[doc = "TRIG enable register"]
176 pub mod TRIG_ENABLE {
177 pub const offset: u32 = 0;
178 pub const mask: u32 = 0xff << offset;
179 pub mod R {}
180 pub mod W {}
181 pub mod RW {}
182 }
183 #[doc = "TSC0 TRIG enable register. 1'b1: enable external TSC0 trigger. 1'b0: disable external TSC0 trigger."]
184 pub mod EXT0_TRIG_ENABLE {
185 pub const offset: u32 = 8;
186 pub const mask: u32 = 0x01 << offset;
187 pub mod R {}
188 pub mod W {}
189 pub mod RW {}
190 }
191 #[doc = "External TSC0 trigger priority, 7 is Highest, 0 is lowest ."]
192 pub mod EXT0_TRIG_PRIORITY {
193 pub const offset: u32 = 9;
194 pub const mask: u32 = 0x07 << offset;
195 pub mod R {}
196 pub mod W {}
197 pub mod RW {}
198 }
199 #[doc = "TSC1 TRIG enable register. 1'b1: enable external TSC1 trigger. 1'b0: disable external TSC1 trigger."]
200 pub mod EXT1_TRIG_ENABLE {
201 pub const offset: u32 = 12;
202 pub const mask: u32 = 0x01 << offset;
203 pub mod R {}
204 pub mod W {}
205 pub mod RW {}
206 }
207 #[doc = "External TSC1 trigger priority, 7 is Highest, 0 is lowest ."]
208 pub mod EXT1_TRIG_PRIORITY {
209 pub const offset: u32 = 13;
210 pub const mask: u32 = 0x07 << offset;
211 pub mod R {}
212 pub mod W {}
213 pub mod RW {}
214 }
215 #[doc = "Pre-divider for trig delay and interval ."]
216 pub mod PRE_DIVIDER {
217 pub const offset: u32 = 16;
218 pub const mask: u32 = 0xff << offset;
219 pub mod R {}
220 pub mod W {}
221 pub mod RW {}
222 }
223 #[doc = "1'b0: Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared"]
224 pub mod DMA_MODE_SEL {
225 pub const offset: u32 = 29;
226 pub const mask: u32 = 0x01 << offset;
227 pub mod R {}
228 pub mod W {}
229 pub mod RW {}
230 }
231 #[doc = "1'b1: TSC is bypassed to ADC2. 1'b0: TSC not bypassed. To use ADC2, this bit should be cleared."]
232 pub mod TSC_BYPASS {
233 pub const offset: u32 = 30;
234 pub const mask: u32 = 0x01 << offset;
235 pub mod R {}
236 pub mod W {}
237 pub mod RW {}
238 }
239 #[doc = "Software reset, high active. When write 1 ,all logical will be reset."]
240 pub mod SOFTRST {
241 pub const offset: u32 = 31;
242 pub const mask: u32 = 0x01 << offset;
243 pub mod R {}
244 pub mod W {}
245 pub mod RW {}
246 }
247}
248#[doc = "ETC DONE0 and DONE1 IRQ State Register"]
249pub mod DONE0_1_IRQ {
250 #[doc = "TRIG0 done0 interrupt detection"]
251 pub mod TRIG0_DONE0 {
252 pub const offset: u32 = 0;
253 pub const mask: u32 = 0x01 << offset;
254 pub mod R {}
255 pub mod W {}
256 pub mod RW {}
257 }
258 #[doc = "TRIG1 done0 interrupt detection"]
259 pub mod TRIG1_DONE0 {
260 pub const offset: u32 = 1;
261 pub const mask: u32 = 0x01 << offset;
262 pub mod R {}
263 pub mod W {}
264 pub mod RW {}
265 }
266 #[doc = "TRIG2 done0 interrupt detection"]
267 pub mod TRIG2_DONE0 {
268 pub const offset: u32 = 2;
269 pub const mask: u32 = 0x01 << offset;
270 pub mod R {}
271 pub mod W {}
272 pub mod RW {}
273 }
274 #[doc = "TRIG3 done0 interrupt detection"]
275 pub mod TRIG3_DONE0 {
276 pub const offset: u32 = 3;
277 pub const mask: u32 = 0x01 << offset;
278 pub mod R {}
279 pub mod W {}
280 pub mod RW {}
281 }
282 #[doc = "TRIG4 done0 interrupt detection"]
283 pub mod TRIG4_DONE0 {
284 pub const offset: u32 = 4;
285 pub const mask: u32 = 0x01 << offset;
286 pub mod R {}
287 pub mod W {}
288 pub mod RW {}
289 }
290 #[doc = "TRIG5 done0 interrupt detection"]
291 pub mod TRIG5_DONE0 {
292 pub const offset: u32 = 5;
293 pub const mask: u32 = 0x01 << offset;
294 pub mod R {}
295 pub mod W {}
296 pub mod RW {}
297 }
298 #[doc = "TRIG6 done0 interrupt detection"]
299 pub mod TRIG6_DONE0 {
300 pub const offset: u32 = 6;
301 pub const mask: u32 = 0x01 << offset;
302 pub mod R {}
303 pub mod W {}
304 pub mod RW {}
305 }
306 #[doc = "TRIG7 done0 interrupt detection"]
307 pub mod TRIG7_DONE0 {
308 pub const offset: u32 = 7;
309 pub const mask: u32 = 0x01 << offset;
310 pub mod R {}
311 pub mod W {}
312 pub mod RW {}
313 }
314 #[doc = "TRIG0 done1 interrupt detection"]
315 pub mod TRIG0_DONE1 {
316 pub const offset: u32 = 16;
317 pub const mask: u32 = 0x01 << offset;
318 pub mod R {}
319 pub mod W {}
320 pub mod RW {}
321 }
322 #[doc = "TRIG1 done1 interrupt detection"]
323 pub mod TRIG1_DONE1 {
324 pub const offset: u32 = 17;
325 pub const mask: u32 = 0x01 << offset;
326 pub mod R {}
327 pub mod W {}
328 pub mod RW {}
329 }
330 #[doc = "TRIG2 done1 interrupt detection"]
331 pub mod TRIG2_DONE1 {
332 pub const offset: u32 = 18;
333 pub const mask: u32 = 0x01 << offset;
334 pub mod R {}
335 pub mod W {}
336 pub mod RW {}
337 }
338 #[doc = "TRIG3 done1 interrupt detection"]
339 pub mod TRIG3_DONE1 {
340 pub const offset: u32 = 19;
341 pub const mask: u32 = 0x01 << offset;
342 pub mod R {}
343 pub mod W {}
344 pub mod RW {}
345 }
346 #[doc = "TRIG4 done1 interrupt detection"]
347 pub mod TRIG4_DONE1 {
348 pub const offset: u32 = 20;
349 pub const mask: u32 = 0x01 << offset;
350 pub mod R {}
351 pub mod W {}
352 pub mod RW {}
353 }
354 #[doc = "TRIG5 done1 interrupt detection"]
355 pub mod TRIG5_DONE1 {
356 pub const offset: u32 = 21;
357 pub const mask: u32 = 0x01 << offset;
358 pub mod R {}
359 pub mod W {}
360 pub mod RW {}
361 }
362 #[doc = "TRIG6 done1 interrupt detection"]
363 pub mod TRIG6_DONE1 {
364 pub const offset: u32 = 22;
365 pub const mask: u32 = 0x01 << offset;
366 pub mod R {}
367 pub mod W {}
368 pub mod RW {}
369 }
370 #[doc = "TRIG7 done1 interrupt detection"]
371 pub mod TRIG7_DONE1 {
372 pub const offset: u32 = 23;
373 pub const mask: u32 = 0x01 << offset;
374 pub mod R {}
375 pub mod W {}
376 pub mod RW {}
377 }
378}
379#[doc = "ETC DONE_2 and DONE_ERR IRQ State Register"]
380pub mod DONE2_ERR_IRQ {
381 #[doc = "TRIG0 done2 interrupt detection"]
382 pub mod TRIG0_DONE2 {
383 pub const offset: u32 = 0;
384 pub const mask: u32 = 0x01 << offset;
385 pub mod R {}
386 pub mod W {}
387 pub mod RW {}
388 }
389 #[doc = "TRIG1 done2 interrupt detection"]
390 pub mod TRIG1_DONE2 {
391 pub const offset: u32 = 1;
392 pub const mask: u32 = 0x01 << offset;
393 pub mod R {}
394 pub mod W {}
395 pub mod RW {}
396 }
397 #[doc = "TRIG2 done2 interrupt detection"]
398 pub mod TRIG2_DONE2 {
399 pub const offset: u32 = 2;
400 pub const mask: u32 = 0x01 << offset;
401 pub mod R {}
402 pub mod W {}
403 pub mod RW {}
404 }
405 #[doc = "TRIG3 done2 interrupt detection"]
406 pub mod TRIG3_DONE2 {
407 pub const offset: u32 = 3;
408 pub const mask: u32 = 0x01 << offset;
409 pub mod R {}
410 pub mod W {}
411 pub mod RW {}
412 }
413 #[doc = "TRIG4 done2 interrupt detection"]
414 pub mod TRIG4_DONE2 {
415 pub const offset: u32 = 4;
416 pub const mask: u32 = 0x01 << offset;
417 pub mod R {}
418 pub mod W {}
419 pub mod RW {}
420 }
421 #[doc = "TRIG5 done2 interrupt detection"]
422 pub mod TRIG5_DONE2 {
423 pub const offset: u32 = 5;
424 pub const mask: u32 = 0x01 << offset;
425 pub mod R {}
426 pub mod W {}
427 pub mod RW {}
428 }
429 #[doc = "TRIG6 done2 interrupt detection"]
430 pub mod TRIG6_DONE2 {
431 pub const offset: u32 = 6;
432 pub const mask: u32 = 0x01 << offset;
433 pub mod R {}
434 pub mod W {}
435 pub mod RW {}
436 }
437 #[doc = "TRIG7 done2 interrupt detection"]
438 pub mod TRIG7_DONE2 {
439 pub const offset: u32 = 7;
440 pub const mask: u32 = 0x01 << offset;
441 pub mod R {}
442 pub mod W {}
443 pub mod RW {}
444 }
445 #[doc = "TRIG0 error interrupt detection"]
446 pub mod TRIG0_ERR {
447 pub const offset: u32 = 16;
448 pub const mask: u32 = 0x01 << offset;
449 pub mod R {}
450 pub mod W {}
451 pub mod RW {}
452 }
453 #[doc = "TRIG1 error interrupt detection"]
454 pub mod TRIG1_ERR {
455 pub const offset: u32 = 17;
456 pub const mask: u32 = 0x01 << offset;
457 pub mod R {}
458 pub mod W {}
459 pub mod RW {}
460 }
461 #[doc = "TRIG2 error interrupt detection"]
462 pub mod TRIG2_ERR {
463 pub const offset: u32 = 18;
464 pub const mask: u32 = 0x01 << offset;
465 pub mod R {}
466 pub mod W {}
467 pub mod RW {}
468 }
469 #[doc = "TRIG3 error interrupt detection"]
470 pub mod TRIG3_ERR {
471 pub const offset: u32 = 19;
472 pub const mask: u32 = 0x01 << offset;
473 pub mod R {}
474 pub mod W {}
475 pub mod RW {}
476 }
477 #[doc = "TRIG4 error interrupt detection"]
478 pub mod TRIG4_ERR {
479 pub const offset: u32 = 20;
480 pub const mask: u32 = 0x01 << offset;
481 pub mod R {}
482 pub mod W {}
483 pub mod RW {}
484 }
485 #[doc = "TRIG5 error interrupt detection"]
486 pub mod TRIG5_ERR {
487 pub const offset: u32 = 21;
488 pub const mask: u32 = 0x01 << offset;
489 pub mod R {}
490 pub mod W {}
491 pub mod RW {}
492 }
493 #[doc = "TRIG6 error interrupt detection"]
494 pub mod TRIG6_ERR {
495 pub const offset: u32 = 22;
496 pub const mask: u32 = 0x01 << offset;
497 pub mod R {}
498 pub mod W {}
499 pub mod RW {}
500 }
501 #[doc = "TRIG7 error interrupt detection"]
502 pub mod TRIG7_ERR {
503 pub const offset: u32 = 23;
504 pub const mask: u32 = 0x01 << offset;
505 pub mod R {}
506 pub mod W {}
507 pub mod RW {}
508 }
509}
510#[doc = "ETC DMA control Register"]
511pub mod DMA_CTRL {
512 #[doc = "When TRIG0 done enable DMA request"]
513 pub mod TRIG0_ENABLE {
514 pub const offset: u32 = 0;
515 pub const mask: u32 = 0x01 << offset;
516 pub mod R {}
517 pub mod W {}
518 pub mod RW {}
519 }
520 #[doc = "When TRIG1 done enable DMA request"]
521 pub mod TRIG1_ENABLE {
522 pub const offset: u32 = 1;
523 pub const mask: u32 = 0x01 << offset;
524 pub mod R {}
525 pub mod W {}
526 pub mod RW {}
527 }
528 #[doc = "When TRIG2 done enable DMA request"]
529 pub mod TRIG2_ENABLE {
530 pub const offset: u32 = 2;
531 pub const mask: u32 = 0x01 << offset;
532 pub mod R {}
533 pub mod W {}
534 pub mod RW {}
535 }
536 #[doc = "When TRIG3 done enable DMA request"]
537 pub mod TRIG3_ENABLE {
538 pub const offset: u32 = 3;
539 pub const mask: u32 = 0x01 << offset;
540 pub mod R {}
541 pub mod W {}
542 pub mod RW {}
543 }
544 #[doc = "When TRIG4 done enable DMA request"]
545 pub mod TRIG4_ENABLE {
546 pub const offset: u32 = 4;
547 pub const mask: u32 = 0x01 << offset;
548 pub mod R {}
549 pub mod W {}
550 pub mod RW {}
551 }
552 #[doc = "When TRIG5 done enable DMA request"]
553 pub mod TRIG5_ENABLE {
554 pub const offset: u32 = 5;
555 pub const mask: u32 = 0x01 << offset;
556 pub mod R {}
557 pub mod W {}
558 pub mod RW {}
559 }
560 #[doc = "When TRIG6 done enable DMA request"]
561 pub mod TRIG6_ENABLE {
562 pub const offset: u32 = 6;
563 pub const mask: u32 = 0x01 << offset;
564 pub mod R {}
565 pub mod W {}
566 pub mod RW {}
567 }
568 #[doc = "When TRIG7 done enable DMA request"]
569 pub mod TRIG7_ENABLE {
570 pub const offset: u32 = 7;
571 pub const mask: u32 = 0x01 << offset;
572 pub mod R {}
573 pub mod W {}
574 pub mod RW {}
575 }
576 #[doc = "When TRIG0 done DMA request detection"]
577 pub mod TRIG0_REQ {
578 pub const offset: u32 = 16;
579 pub const mask: u32 = 0x01 << offset;
580 pub mod R {}
581 pub mod W {}
582 pub mod RW {}
583 }
584 #[doc = "When TRIG1 done DMA request detection"]
585 pub mod TRIG1_REQ {
586 pub const offset: u32 = 17;
587 pub const mask: u32 = 0x01 << offset;
588 pub mod R {}
589 pub mod W {}
590 pub mod RW {}
591 }
592 #[doc = "When TRIG2 done DMA request detection"]
593 pub mod TRIG2_REQ {
594 pub const offset: u32 = 18;
595 pub const mask: u32 = 0x01 << offset;
596 pub mod R {}
597 pub mod W {}
598 pub mod RW {}
599 }
600 #[doc = "When TRIG3 done DMA request detection"]
601 pub mod TRIG3_REQ {
602 pub const offset: u32 = 19;
603 pub const mask: u32 = 0x01 << offset;
604 pub mod R {}
605 pub mod W {}
606 pub mod RW {}
607 }
608 #[doc = "When TRIG4 done DMA request detection"]
609 pub mod TRIG4_REQ {
610 pub const offset: u32 = 20;
611 pub const mask: u32 = 0x01 << offset;
612 pub mod R {}
613 pub mod W {}
614 pub mod RW {}
615 }
616 #[doc = "When TRIG5 done DMA request detection"]
617 pub mod TRIG5_REQ {
618 pub const offset: u32 = 21;
619 pub const mask: u32 = 0x01 << offset;
620 pub mod R {}
621 pub mod W {}
622 pub mod RW {}
623 }
624 #[doc = "When TRIG6 done DMA request detection"]
625 pub mod TRIG6_REQ {
626 pub const offset: u32 = 22;
627 pub const mask: u32 = 0x01 << offset;
628 pub mod R {}
629 pub mod W {}
630 pub mod RW {}
631 }
632 #[doc = "When TRIG7 done DMA request detection"]
633 pub mod TRIG7_REQ {
634 pub const offset: u32 = 23;
635 pub const mask: u32 = 0x01 << offset;
636 pub mod R {}
637 pub mod W {}
638 pub mod RW {}
639 }
640}
641#[doc = "ETC_TRIG0 Control Register"]
642pub mod TRIG0_CTRL {
643 #[doc = "Software write 1 as the TRIGGER. This register is self-clearing."]
644 pub mod SW_TRIG {
645 pub const offset: u32 = 0;
646 pub const mask: u32 = 0x01 << offset;
647 pub mod R {}
648 pub mod W {}
649 pub mod RW {}
650 }
651 #[doc = "TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger."]
652 pub mod TRIG_MODE {
653 pub const offset: u32 = 4;
654 pub const mask: u32 = 0x01 << offset;
655 pub mod R {}
656 pub mod W {}
657 pub mod RW {}
658 }
659 #[doc = "TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;"]
660 pub mod TRIG_CHAIN {
661 pub const offset: u32 = 8;
662 pub const mask: u32 = 0x07 << offset;
663 pub mod R {}
664 pub mod W {}
665 pub mod RW {}
666 }
667 #[doc = "External trigger priority, 7 is highest, 0 is lowest ."]
668 pub mod TRIG_PRIORITY {
669 pub const offset: u32 = 12;
670 pub const mask: u32 = 0x07 << offset;
671 pub mod R {}
672 pub mod W {}
673 pub mod RW {}
674 }
675 #[doc = "TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode"]
676 pub mod SYNC_MODE {
677 pub const offset: u32 = 16;
678 pub const mask: u32 = 0x01 << offset;
679 pub mod R {}
680 pub mod W {}
681 pub mod RW {}
682 }
683}
684#[doc = "ETC_TRIG0 Counter Register"]
685pub mod TRIG0_COUNTER {
686 #[doc = "TRIGGER initial delay counter"]
687 pub mod INIT_DELAY {
688 pub const offset: u32 = 0;
689 pub const mask: u32 = 0xffff << offset;
690 pub mod R {}
691 pub mod W {}
692 pub mod RW {}
693 }
694 #[doc = "TRIGGER sampling interval counter"]
695 pub mod SAMPLE_INTERVAL {
696 pub const offset: u32 = 16;
697 pub const mask: u32 = 0xffff << offset;
698 pub mod R {}
699 pub mod W {}
700 pub mod RW {}
701 }
702}
703#[doc = "ETC_TRIG Chain 0/1 Register"]
704pub mod TRIG0_CHAIN_1_0 {
705 #[doc = "CHAIN0 CSEL ADC channel selection"]
706 pub mod CSEL0 {
707 pub const offset: u32 = 0;
708 pub const mask: u32 = 0x0f << offset;
709 pub mod R {}
710 pub mod W {}
711 pub mod RW {}
712 }
713 #[doc = "CHAIN0 HWTS ADC hardware trigger selection. For more information, see the ADC chapter."]
714 pub mod HWTS0 {
715 pub const offset: u32 = 4;
716 pub const mask: u32 = 0xff << offset;
717 pub mod R {}
718 pub mod W {}
719 pub mod RW {}
720 }
721 #[doc = "CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger"]
722 pub mod B2B0 {
723 pub const offset: u32 = 12;
724 pub const mask: u32 = 0x01 << offset;
725 pub mod R {}
726 pub mod W {}
727 pub mod RW {}
728 }
729 #[doc = "CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2"]
730 pub mod IE0 {
731 pub const offset: u32 = 13;
732 pub const mask: u32 = 0x03 << offset;
733 pub mod R {}
734 pub mod W {}
735 pub mod RW {}
736 }
737 #[doc = "CHAIN1 CSEL ADC channel selection"]
738 pub mod CSEL1 {
739 pub const offset: u32 = 16;
740 pub const mask: u32 = 0x0f << offset;
741 pub mod R {}
742 pub mod W {}
743 pub mod RW {}
744 }
745 #[doc = "CHAIN1 HWTS ADC hardware trigger selection. For more information, see the ADC chapter."]
746 pub mod HWTS1 {
747 pub const offset: u32 = 20;
748 pub const mask: u32 = 0xff << offset;
749 pub mod R {}
750 pub mod W {}
751 pub mod RW {}
752 }
753 #[doc = "CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger"]
754 pub mod B2B1 {
755 pub const offset: u32 = 28;
756 pub const mask: u32 = 0x01 << offset;
757 pub mod R {}
758 pub mod W {}
759 pub mod RW {}
760 }
761 #[doc = "CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2"]
762 pub mod IE1 {
763 pub const offset: u32 = 29;
764 pub const mask: u32 = 0x03 << offset;
765 pub mod R {}
766 pub mod W {}
767 pub mod RW {}
768 }
769}
770#[doc = "ETC_TRIG Chain 2/3 Register"]
771pub mod TRIG0_CHAIN_3_2 {
772 #[doc = "CHAIN2 CSEL"]
773 pub mod CSEL2 {
774 pub const offset: u32 = 0;
775 pub const mask: u32 = 0x0f << offset;
776 pub mod R {}
777 pub mod W {}
778 pub mod RW {}
779 }
780 #[doc = "CHAIN2 HWTS"]
781 pub mod HWTS2 {
782 pub const offset: u32 = 4;
783 pub const mask: u32 = 0xff << offset;
784 pub mod R {}
785 pub mod W {}
786 pub mod RW {}
787 }
788 #[doc = "CHAIN2 B2B"]
789 pub mod B2B2 {
790 pub const offset: u32 = 12;
791 pub const mask: u32 = 0x01 << offset;
792 pub mod R {}
793 pub mod W {}
794 pub mod RW {}
795 }
796 #[doc = "CHAIN2 IE"]
797 pub mod IE2 {
798 pub const offset: u32 = 13;
799 pub const mask: u32 = 0x03 << offset;
800 pub mod R {}
801 pub mod W {}
802 pub mod RW {}
803 }
804 #[doc = "CHAIN3 CSEL"]
805 pub mod CSEL3 {
806 pub const offset: u32 = 16;
807 pub const mask: u32 = 0x0f << offset;
808 pub mod R {}
809 pub mod W {}
810 pub mod RW {}
811 }
812 #[doc = "CHAIN3 HWTS"]
813 pub mod HWTS3 {
814 pub const offset: u32 = 20;
815 pub const mask: u32 = 0xff << offset;
816 pub mod R {}
817 pub mod W {}
818 pub mod RW {}
819 }
820 #[doc = "CHAIN3 B2B"]
821 pub mod B2B3 {
822 pub const offset: u32 = 28;
823 pub const mask: u32 = 0x01 << offset;
824 pub mod R {}
825 pub mod W {}
826 pub mod RW {}
827 }
828 #[doc = "CHAIN3 IE"]
829 pub mod IE3 {
830 pub const offset: u32 = 29;
831 pub const mask: u32 = 0x03 << offset;
832 pub mod R {}
833 pub mod W {}
834 pub mod RW {}
835 }
836}
837#[doc = "ETC_TRIG Chain 4/5 Register"]
838pub mod TRIG0_CHAIN_5_4 {
839 #[doc = "CHAIN4 CSEL"]
840 pub mod CSEL4 {
841 pub const offset: u32 = 0;
842 pub const mask: u32 = 0x0f << offset;
843 pub mod R {}
844 pub mod W {}
845 pub mod RW {}
846 }
847 #[doc = "CHAIN4 HWTS"]
848 pub mod HWTS4 {
849 pub const offset: u32 = 4;
850 pub const mask: u32 = 0xff << offset;
851 pub mod R {}
852 pub mod W {}
853 pub mod RW {}
854 }
855 #[doc = "CHAIN4 B2B"]
856 pub mod B2B4 {
857 pub const offset: u32 = 12;
858 pub const mask: u32 = 0x01 << offset;
859 pub mod R {}
860 pub mod W {}
861 pub mod RW {}
862 }
863 #[doc = "CHAIN4 IE"]
864 pub mod IE4 {
865 pub const offset: u32 = 13;
866 pub const mask: u32 = 0x03 << offset;
867 pub mod R {}
868 pub mod W {}
869 pub mod RW {}
870 }
871 #[doc = "CHAIN5 CSEL"]
872 pub mod CSEL5 {
873 pub const offset: u32 = 16;
874 pub const mask: u32 = 0x0f << offset;
875 pub mod R {}
876 pub mod W {}
877 pub mod RW {}
878 }
879 #[doc = "CHAIN5 HWTS"]
880 pub mod HWTS5 {
881 pub const offset: u32 = 20;
882 pub const mask: u32 = 0xff << offset;
883 pub mod R {}
884 pub mod W {}
885 pub mod RW {}
886 }
887 #[doc = "CHAIN5 B2B"]
888 pub mod B2B5 {
889 pub const offset: u32 = 28;
890 pub const mask: u32 = 0x01 << offset;
891 pub mod R {}
892 pub mod W {}
893 pub mod RW {}
894 }
895 #[doc = "CHAIN5 IE"]
896 pub mod IE5 {
897 pub const offset: u32 = 29;
898 pub const mask: u32 = 0x03 << offset;
899 pub mod R {}
900 pub mod W {}
901 pub mod RW {}
902 }
903}
904#[doc = "ETC_TRIG Chain 6/7 Register"]
905pub mod TRIG0_CHAIN_7_6 {
906 #[doc = "CHAIN6 CSEL"]
907 pub mod CSEL6 {
908 pub const offset: u32 = 0;
909 pub const mask: u32 = 0x0f << offset;
910 pub mod R {}
911 pub mod W {}
912 pub mod RW {}
913 }
914 #[doc = "CHAIN6 HWTS"]
915 pub mod HWTS6 {
916 pub const offset: u32 = 4;
917 pub const mask: u32 = 0xff << offset;
918 pub mod R {}
919 pub mod W {}
920 pub mod RW {}
921 }
922 #[doc = "CHAIN6 B2B"]
923 pub mod B2B6 {
924 pub const offset: u32 = 12;
925 pub const mask: u32 = 0x01 << offset;
926 pub mod R {}
927 pub mod W {}
928 pub mod RW {}
929 }
930 #[doc = "CHAIN6 IE"]
931 pub mod IE6 {
932 pub const offset: u32 = 13;
933 pub const mask: u32 = 0x03 << offset;
934 pub mod R {}
935 pub mod W {}
936 pub mod RW {}
937 }
938 #[doc = "CHAIN7 CSEL"]
939 pub mod CSEL7 {
940 pub const offset: u32 = 16;
941 pub const mask: u32 = 0x0f << offset;
942 pub mod R {}
943 pub mod W {}
944 pub mod RW {}
945 }
946 #[doc = "CHAIN7 HWTS"]
947 pub mod HWTS7 {
948 pub const offset: u32 = 20;
949 pub const mask: u32 = 0xff << offset;
950 pub mod R {}
951 pub mod W {}
952 pub mod RW {}
953 }
954 #[doc = "CHAIN7 B2B"]
955 pub mod B2B7 {
956 pub const offset: u32 = 28;
957 pub const mask: u32 = 0x01 << offset;
958 pub mod R {}
959 pub mod W {}
960 pub mod RW {}
961 }
962 #[doc = "CHAIN7 IE"]
963 pub mod IE7 {
964 pub const offset: u32 = 29;
965 pub const mask: u32 = 0x03 << offset;
966 pub mod R {}
967 pub mod W {}
968 pub mod RW {}
969 }
970}
971#[doc = "ETC_TRIG Result Data 1/0 Register"]
972pub mod TRIG0_RESULT_1_0 {
973 #[doc = "Result DATA0"]
974 pub mod DATA0 {
975 pub const offset: u32 = 0;
976 pub const mask: u32 = 0x0fff << offset;
977 pub mod R {}
978 pub mod W {}
979 pub mod RW {}
980 }
981 #[doc = "Result DATA1"]
982 pub mod DATA1 {
983 pub const offset: u32 = 16;
984 pub const mask: u32 = 0x0fff << offset;
985 pub mod R {}
986 pub mod W {}
987 pub mod RW {}
988 }
989}
990#[doc = "ETC_TRIG Result Data 3/2 Register"]
991pub mod TRIG0_RESULT_3_2 {
992 #[doc = "Result DATA2"]
993 pub mod DATA2 {
994 pub const offset: u32 = 0;
995 pub const mask: u32 = 0x0fff << offset;
996 pub mod R {}
997 pub mod W {}
998 pub mod RW {}
999 }
1000 #[doc = "Result DATA3"]
1001 pub mod DATA3 {
1002 pub const offset: u32 = 16;
1003 pub const mask: u32 = 0x0fff << offset;
1004 pub mod R {}
1005 pub mod W {}
1006 pub mod RW {}
1007 }
1008}
1009#[doc = "ETC_TRIG Result Data 5/4 Register"]
1010pub mod TRIG0_RESULT_5_4 {
1011 #[doc = "Result DATA4"]
1012 pub mod DATA4 {
1013 pub const offset: u32 = 0;
1014 pub const mask: u32 = 0x0fff << offset;
1015 pub mod R {}
1016 pub mod W {}
1017 pub mod RW {}
1018 }
1019 #[doc = "Result DATA5"]
1020 pub mod DATA5 {
1021 pub const offset: u32 = 16;
1022 pub const mask: u32 = 0x0fff << offset;
1023 pub mod R {}
1024 pub mod W {}
1025 pub mod RW {}
1026 }
1027}
1028#[doc = "ETC_TRIG Result Data 7/6 Register"]
1029pub mod TRIG0_RESULT_7_6 {
1030 #[doc = "Result DATA6"]
1031 pub mod DATA6 {
1032 pub const offset: u32 = 0;
1033 pub const mask: u32 = 0x0fff << offset;
1034 pub mod R {}
1035 pub mod W {}
1036 pub mod RW {}
1037 }
1038 #[doc = "Result DATA7"]
1039 pub mod DATA7 {
1040 pub const offset: u32 = 16;
1041 pub const mask: u32 = 0x0fff << offset;
1042 pub mod R {}
1043 pub mod W {}
1044 pub mod RW {}
1045 }
1046}
1047#[doc = "ETC_TRIG1 Control Register"]
1048pub mod TRIG1_CTRL {
1049 #[doc = "Software write 1 as the TRIGGER. This register is self-clearing."]
1050 pub mod SW_TRIG {
1051 pub const offset: u32 = 0;
1052 pub const mask: u32 = 0x01 << offset;
1053 pub mod R {}
1054 pub mod W {}
1055 pub mod RW {}
1056 }
1057 #[doc = "TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger."]
1058 pub mod TRIG_MODE {
1059 pub const offset: u32 = 4;
1060 pub const mask: u32 = 0x01 << offset;
1061 pub mod R {}
1062 pub mod W {}
1063 pub mod RW {}
1064 }
1065 #[doc = "TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;"]
1066 pub mod TRIG_CHAIN {
1067 pub const offset: u32 = 8;
1068 pub const mask: u32 = 0x07 << offset;
1069 pub mod R {}
1070 pub mod W {}
1071 pub mod RW {}
1072 }
1073 #[doc = "External trigger priority, 7 is highest, 0 is lowest ."]
1074 pub mod TRIG_PRIORITY {
1075 pub const offset: u32 = 12;
1076 pub const mask: u32 = 0x07 << offset;
1077 pub mod R {}
1078 pub mod W {}
1079 pub mod RW {}
1080 }
1081 #[doc = "TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode"]
1082 pub mod SYNC_MODE {
1083 pub const offset: u32 = 16;
1084 pub const mask: u32 = 0x01 << offset;
1085 pub mod R {}
1086 pub mod W {}
1087 pub mod RW {}
1088 }
1089}
1090#[doc = "ETC_TRIG1 Counter Register"]
1091pub mod TRIG1_COUNTER {
1092 #[doc = "TRIGGER initial delay counter"]
1093 pub mod INIT_DELAY {
1094 pub const offset: u32 = 0;
1095 pub const mask: u32 = 0xffff << offset;
1096 pub mod R {}
1097 pub mod W {}
1098 pub mod RW {}
1099 }
1100 #[doc = "TRIGGER sampling interval counter"]
1101 pub mod SAMPLE_INTERVAL {
1102 pub const offset: u32 = 16;
1103 pub const mask: u32 = 0xffff << offset;
1104 pub mod R {}
1105 pub mod W {}
1106 pub mod RW {}
1107 }
1108}
1109#[doc = "ETC_TRIG Chain 0/1 Register"]
1110pub mod TRIG1_CHAIN_1_0 {
1111 #[doc = "CHAIN0 CSEL ADC channel selection"]
1112 pub mod CSEL0 {
1113 pub const offset: u32 = 0;
1114 pub const mask: u32 = 0x0f << offset;
1115 pub mod R {}
1116 pub mod W {}
1117 pub mod RW {}
1118 }
1119 #[doc = "CHAIN0 HWTS ADC hardware trigger selection"]
1120 pub mod HWTS0 {
1121 pub const offset: u32 = 4;
1122 pub const mask: u32 = 0xff << offset;
1123 pub mod R {}
1124 pub mod W {}
1125 pub mod RW {}
1126 }
1127 #[doc = "CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger"]
1128 pub mod B2B0 {
1129 pub const offset: u32 = 12;
1130 pub const mask: u32 = 0x01 << offset;
1131 pub mod R {}
1132 pub mod W {}
1133 pub mod RW {}
1134 }
1135 #[doc = "CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2"]
1136 pub mod IE0 {
1137 pub const offset: u32 = 13;
1138 pub const mask: u32 = 0x03 << offset;
1139 pub mod R {}
1140 pub mod W {}
1141 pub mod RW {}
1142 }
1143 #[doc = "CHAIN1 CSEL ADC channel selection"]
1144 pub mod CSEL1 {
1145 pub const offset: u32 = 16;
1146 pub const mask: u32 = 0x0f << offset;
1147 pub mod R {}
1148 pub mod W {}
1149 pub mod RW {}
1150 }
1151 #[doc = "CHAIN1 HWTS ADC hardware trigger selection"]
1152 pub mod HWTS1 {
1153 pub const offset: u32 = 20;
1154 pub const mask: u32 = 0xff << offset;
1155 pub mod R {}
1156 pub mod W {}
1157 pub mod RW {}
1158 }
1159 #[doc = "CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger"]
1160 pub mod B2B1 {
1161 pub const offset: u32 = 28;
1162 pub const mask: u32 = 0x01 << offset;
1163 pub mod R {}
1164 pub mod W {}
1165 pub mod RW {}
1166 }
1167 #[doc = "CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2"]
1168 pub mod IE1 {
1169 pub const offset: u32 = 29;
1170 pub const mask: u32 = 0x03 << offset;
1171 pub mod R {}
1172 pub mod W {}
1173 pub mod RW {}
1174 }
1175}
1176#[doc = "ETC_TRIG Chain 2/3 Register"]
1177pub mod TRIG1_CHAIN_3_2 {
1178 #[doc = "CHAIN2 CSEL"]
1179 pub mod CSEL2 {
1180 pub const offset: u32 = 0;
1181 pub const mask: u32 = 0x0f << offset;
1182 pub mod R {}
1183 pub mod W {}
1184 pub mod RW {}
1185 }
1186 #[doc = "CHAIN2 HWTS"]
1187 pub mod HWTS2 {
1188 pub const offset: u32 = 4;
1189 pub const mask: u32 = 0xff << offset;
1190 pub mod R {}
1191 pub mod W {}
1192 pub mod RW {}
1193 }
1194 #[doc = "CHAIN2 B2B"]
1195 pub mod B2B2 {
1196 pub const offset: u32 = 12;
1197 pub const mask: u32 = 0x01 << offset;
1198 pub mod R {}
1199 pub mod W {}
1200 pub mod RW {}
1201 }
1202 #[doc = "CHAIN2 IE"]
1203 pub mod IE2 {
1204 pub const offset: u32 = 13;
1205 pub const mask: u32 = 0x03 << offset;
1206 pub mod R {}
1207 pub mod W {}
1208 pub mod RW {}
1209 }
1210 #[doc = "CHAIN3 CSEL"]
1211 pub mod CSEL3 {
1212 pub const offset: u32 = 16;
1213 pub const mask: u32 = 0x0f << offset;
1214 pub mod R {}
1215 pub mod W {}
1216 pub mod RW {}
1217 }
1218 #[doc = "CHAIN3 HWTS"]
1219 pub mod HWTS3 {
1220 pub const offset: u32 = 20;
1221 pub const mask: u32 = 0xff << offset;
1222 pub mod R {}
1223 pub mod W {}
1224 pub mod RW {}
1225 }
1226 #[doc = "CHAIN3 B2B"]
1227 pub mod B2B3 {
1228 pub const offset: u32 = 28;
1229 pub const mask: u32 = 0x01 << offset;
1230 pub mod R {}
1231 pub mod W {}
1232 pub mod RW {}
1233 }
1234 #[doc = "CHAIN3 IE"]
1235 pub mod IE3 {
1236 pub const offset: u32 = 29;
1237 pub const mask: u32 = 0x03 << offset;
1238 pub mod R {}
1239 pub mod W {}
1240 pub mod RW {}
1241 }
1242}
1243#[doc = "ETC_TRIG Chain 4/5 Register"]
1244pub mod TRIG1_CHAIN_5_4 {
1245 #[doc = "CHAIN4 CSEL"]
1246 pub mod CSEL4 {
1247 pub const offset: u32 = 0;
1248 pub const mask: u32 = 0x0f << offset;
1249 pub mod R {}
1250 pub mod W {}
1251 pub mod RW {}
1252 }
1253 #[doc = "CHAIN4 HWTS"]
1254 pub mod HWTS4 {
1255 pub const offset: u32 = 4;
1256 pub const mask: u32 = 0xff << offset;
1257 pub mod R {}
1258 pub mod W {}
1259 pub mod RW {}
1260 }
1261 #[doc = "CHAIN4 B2B"]
1262 pub mod B2B4 {
1263 pub const offset: u32 = 12;
1264 pub const mask: u32 = 0x01 << offset;
1265 pub mod R {}
1266 pub mod W {}
1267 pub mod RW {}
1268 }
1269 #[doc = "CHAIN4 IE"]
1270 pub mod IE4 {
1271 pub const offset: u32 = 13;
1272 pub const mask: u32 = 0x03 << offset;
1273 pub mod R {}
1274 pub mod W {}
1275 pub mod RW {}
1276 }
1277 #[doc = "CHAIN5 CSEL"]
1278 pub mod CSEL5 {
1279 pub const offset: u32 = 16;
1280 pub const mask: u32 = 0x0f << offset;
1281 pub mod R {}
1282 pub mod W {}
1283 pub mod RW {}
1284 }
1285 #[doc = "CHAIN5 HWTS"]
1286 pub mod HWTS5 {
1287 pub const offset: u32 = 20;
1288 pub const mask: u32 = 0xff << offset;
1289 pub mod R {}
1290 pub mod W {}
1291 pub mod RW {}
1292 }
1293 #[doc = "CHAIN5 B2B"]
1294 pub mod B2B5 {
1295 pub const offset: u32 = 28;
1296 pub const mask: u32 = 0x01 << offset;
1297 pub mod R {}
1298 pub mod W {}
1299 pub mod RW {}
1300 }
1301 #[doc = "CHAIN5 IE"]
1302 pub mod IE5 {
1303 pub const offset: u32 = 29;
1304 pub const mask: u32 = 0x03 << offset;
1305 pub mod R {}
1306 pub mod W {}
1307 pub mod RW {}
1308 }
1309}
1310#[doc = "ETC_TRIG Chain 6/7 Register"]
1311pub mod TRIG1_CHAIN_7_6 {
1312 #[doc = "CHAIN6 CSEL"]
1313 pub mod CSEL6 {
1314 pub const offset: u32 = 0;
1315 pub const mask: u32 = 0x0f << offset;
1316 pub mod R {}
1317 pub mod W {}
1318 pub mod RW {}
1319 }
1320 #[doc = "CHAIN6 HWTS"]
1321 pub mod HWTS6 {
1322 pub const offset: u32 = 4;
1323 pub const mask: u32 = 0xff << offset;
1324 pub mod R {}
1325 pub mod W {}
1326 pub mod RW {}
1327 }
1328 #[doc = "CHAIN6 B2B"]
1329 pub mod B2B6 {
1330 pub const offset: u32 = 12;
1331 pub const mask: u32 = 0x01 << offset;
1332 pub mod R {}
1333 pub mod W {}
1334 pub mod RW {}
1335 }
1336 #[doc = "CHAIN6 IE"]
1337 pub mod IE6 {
1338 pub const offset: u32 = 13;
1339 pub const mask: u32 = 0x03 << offset;
1340 pub mod R {}
1341 pub mod W {}
1342 pub mod RW {}
1343 }
1344 #[doc = "CHAIN7 CSEL"]
1345 pub mod CSEL7 {
1346 pub const offset: u32 = 16;
1347 pub const mask: u32 = 0x0f << offset;
1348 pub mod R {}
1349 pub mod W {}
1350 pub mod RW {}
1351 }
1352 #[doc = "CHAIN7 HWTS"]
1353 pub mod HWTS7 {
1354 pub const offset: u32 = 20;
1355 pub const mask: u32 = 0xff << offset;
1356 pub mod R {}
1357 pub mod W {}
1358 pub mod RW {}
1359 }
1360 #[doc = "CHAIN7 B2B"]
1361 pub mod B2B7 {
1362 pub const offset: u32 = 28;
1363 pub const mask: u32 = 0x01 << offset;
1364 pub mod R {}
1365 pub mod W {}
1366 pub mod RW {}
1367 }
1368 #[doc = "CHAIN7 IE"]
1369 pub mod IE7 {
1370 pub const offset: u32 = 29;
1371 pub const mask: u32 = 0x03 << offset;
1372 pub mod R {}
1373 pub mod W {}
1374 pub mod RW {}
1375 }
1376}
1377#[doc = "ETC_TRIG Result Data 1/0 Register"]
1378pub mod TRIG1_RESULT_1_0 {
1379 #[doc = "Result DATA0"]
1380 pub mod DATA0 {
1381 pub const offset: u32 = 0;
1382 pub const mask: u32 = 0x0fff << offset;
1383 pub mod R {}
1384 pub mod W {}
1385 pub mod RW {}
1386 }
1387 #[doc = "Result DATA1"]
1388 pub mod DATA1 {
1389 pub const offset: u32 = 16;
1390 pub const mask: u32 = 0x0fff << offset;
1391 pub mod R {}
1392 pub mod W {}
1393 pub mod RW {}
1394 }
1395}
1396#[doc = "ETC_TRIG Result Data 3/2 Register"]
1397pub mod TRIG1_RESULT_3_2 {
1398 #[doc = "Result DATA2"]
1399 pub mod DATA2 {
1400 pub const offset: u32 = 0;
1401 pub const mask: u32 = 0x0fff << offset;
1402 pub mod R {}
1403 pub mod W {}
1404 pub mod RW {}
1405 }
1406 #[doc = "Result DATA3"]
1407 pub mod DATA3 {
1408 pub const offset: u32 = 16;
1409 pub const mask: u32 = 0x0fff << offset;
1410 pub mod R {}
1411 pub mod W {}
1412 pub mod RW {}
1413 }
1414}
1415#[doc = "ETC_TRIG Result Data 5/4 Register"]
1416pub mod TRIG1_RESULT_5_4 {
1417 #[doc = "Result DATA4"]
1418 pub mod DATA4 {
1419 pub const offset: u32 = 0;
1420 pub const mask: u32 = 0x0fff << offset;
1421 pub mod R {}
1422 pub mod W {}
1423 pub mod RW {}
1424 }
1425 #[doc = "Result DATA5"]
1426 pub mod DATA5 {
1427 pub const offset: u32 = 16;
1428 pub const mask: u32 = 0x0fff << offset;
1429 pub mod R {}
1430 pub mod W {}
1431 pub mod RW {}
1432 }
1433}
1434#[doc = "ETC_TRIG Result Data 7/6 Register"]
1435pub mod TRIG1_RESULT_7_6 {
1436 #[doc = "Result DATA6"]
1437 pub mod DATA6 {
1438 pub const offset: u32 = 0;
1439 pub const mask: u32 = 0x0fff << offset;
1440 pub mod R {}
1441 pub mod W {}
1442 pub mod RW {}
1443 }
1444 #[doc = "Result DATA7"]
1445 pub mod DATA7 {
1446 pub const offset: u32 = 16;
1447 pub const mask: u32 = 0x0fff << offset;
1448 pub mod R {}
1449 pub mod W {}
1450 pub mod RW {}
1451 }
1452}
1453#[doc = "ETC_TRIG2 Control Register"]
1454pub mod TRIG2_CTRL {
1455 #[doc = "Software write 1 as the TRIGGER. This register is self-clearing."]
1456 pub mod SW_TRIG {
1457 pub const offset: u32 = 0;
1458 pub const mask: u32 = 0x01 << offset;
1459 pub mod R {}
1460 pub mod W {}
1461 pub mod RW {}
1462 }
1463 #[doc = "TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger."]
1464 pub mod TRIG_MODE {
1465 pub const offset: u32 = 4;
1466 pub const mask: u32 = 0x01 << offset;
1467 pub mod R {}
1468 pub mod W {}
1469 pub mod RW {}
1470 }
1471 #[doc = "TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;"]
1472 pub mod TRIG_CHAIN {
1473 pub const offset: u32 = 8;
1474 pub const mask: u32 = 0x07 << offset;
1475 pub mod R {}
1476 pub mod W {}
1477 pub mod RW {}
1478 }
1479 #[doc = "External trigger priority, 7 is highest, 0 is lowest ."]
1480 pub mod TRIG_PRIORITY {
1481 pub const offset: u32 = 12;
1482 pub const mask: u32 = 0x07 << offset;
1483 pub mod R {}
1484 pub mod W {}
1485 pub mod RW {}
1486 }
1487 #[doc = "TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode"]
1488 pub mod SYNC_MODE {
1489 pub const offset: u32 = 16;
1490 pub const mask: u32 = 0x01 << offset;
1491 pub mod R {}
1492 pub mod W {}
1493 pub mod RW {}
1494 }
1495}
1496#[doc = "ETC_TRIG2 Counter Register"]
1497pub mod TRIG2_COUNTER {
1498 #[doc = "TRIGGER initial delay counter"]
1499 pub mod INIT_DELAY {
1500 pub const offset: u32 = 0;
1501 pub const mask: u32 = 0xffff << offset;
1502 pub mod R {}
1503 pub mod W {}
1504 pub mod RW {}
1505 }
1506 #[doc = "TRIGGER sampling interval counter"]
1507 pub mod SAMPLE_INTERVAL {
1508 pub const offset: u32 = 16;
1509 pub const mask: u32 = 0xffff << offset;
1510 pub mod R {}
1511 pub mod W {}
1512 pub mod RW {}
1513 }
1514}
1515#[doc = "ETC_TRIG Chain 0/1 Register"]
1516pub mod TRIG2_CHAIN_1_0 {
1517 #[doc = "CHAIN0 CSEL ADC channel selection"]
1518 pub mod CSEL0 {
1519 pub const offset: u32 = 0;
1520 pub const mask: u32 = 0x0f << offset;
1521 pub mod R {}
1522 pub mod W {}
1523 pub mod RW {}
1524 }
1525 #[doc = "CHAIN0 HWTS ADC hardware trigger selection"]
1526 pub mod HWTS0 {
1527 pub const offset: u32 = 4;
1528 pub const mask: u32 = 0xff << offset;
1529 pub mod R {}
1530 pub mod W {}
1531 pub mod RW {}
1532 }
1533 #[doc = "CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger"]
1534 pub mod B2B0 {
1535 pub const offset: u32 = 12;
1536 pub const mask: u32 = 0x01 << offset;
1537 pub mod R {}
1538 pub mod W {}
1539 pub mod RW {}
1540 }
1541 #[doc = "CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2"]
1542 pub mod IE0 {
1543 pub const offset: u32 = 13;
1544 pub const mask: u32 = 0x03 << offset;
1545 pub mod R {}
1546 pub mod W {}
1547 pub mod RW {}
1548 }
1549 #[doc = "CHAIN1 CSEL ADC channel selection"]
1550 pub mod CSEL1 {
1551 pub const offset: u32 = 16;
1552 pub const mask: u32 = 0x0f << offset;
1553 pub mod R {}
1554 pub mod W {}
1555 pub mod RW {}
1556 }
1557 #[doc = "CHAIN1 HWTS ADC hardware trigger selection"]
1558 pub mod HWTS1 {
1559 pub const offset: u32 = 20;
1560 pub const mask: u32 = 0xff << offset;
1561 pub mod R {}
1562 pub mod W {}
1563 pub mod RW {}
1564 }
1565 #[doc = "CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger"]
1566 pub mod B2B1 {
1567 pub const offset: u32 = 28;
1568 pub const mask: u32 = 0x01 << offset;
1569 pub mod R {}
1570 pub mod W {}
1571 pub mod RW {}
1572 }
1573 #[doc = "CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2"]
1574 pub mod IE1 {
1575 pub const offset: u32 = 29;
1576 pub const mask: u32 = 0x03 << offset;
1577 pub mod R {}
1578 pub mod W {}
1579 pub mod RW {}
1580 }
1581}
1582#[doc = "ETC_TRIG Chain 2/3 Register"]
1583pub mod TRIG2_CHAIN_3_2 {
1584 #[doc = "CHAIN2 CSEL"]
1585 pub mod CSEL2 {
1586 pub const offset: u32 = 0;
1587 pub const mask: u32 = 0x0f << offset;
1588 pub mod R {}
1589 pub mod W {}
1590 pub mod RW {}
1591 }
1592 #[doc = "CHAIN2 HWTS"]
1593 pub mod HWTS2 {
1594 pub const offset: u32 = 4;
1595 pub const mask: u32 = 0xff << offset;
1596 pub mod R {}
1597 pub mod W {}
1598 pub mod RW {}
1599 }
1600 #[doc = "CHAIN2 B2B"]
1601 pub mod B2B2 {
1602 pub const offset: u32 = 12;
1603 pub const mask: u32 = 0x01 << offset;
1604 pub mod R {}
1605 pub mod W {}
1606 pub mod RW {}
1607 }
1608 #[doc = "CHAIN2 IE"]
1609 pub mod IE2 {
1610 pub const offset: u32 = 13;
1611 pub const mask: u32 = 0x03 << offset;
1612 pub mod R {}
1613 pub mod W {}
1614 pub mod RW {}
1615 }
1616 #[doc = "CHAIN3 CSEL"]
1617 pub mod CSEL3 {
1618 pub const offset: u32 = 16;
1619 pub const mask: u32 = 0x0f << offset;
1620 pub mod R {}
1621 pub mod W {}
1622 pub mod RW {}
1623 }
1624 #[doc = "CHAIN3 HWTS"]
1625 pub mod HWTS3 {
1626 pub const offset: u32 = 20;
1627 pub const mask: u32 = 0xff << offset;
1628 pub mod R {}
1629 pub mod W {}
1630 pub mod RW {}
1631 }
1632 #[doc = "CHAIN3 B2B"]
1633 pub mod B2B3 {
1634 pub const offset: u32 = 28;
1635 pub const mask: u32 = 0x01 << offset;
1636 pub mod R {}
1637 pub mod W {}
1638 pub mod RW {}
1639 }
1640 #[doc = "CHAIN3 IE"]
1641 pub mod IE3 {
1642 pub const offset: u32 = 29;
1643 pub const mask: u32 = 0x03 << offset;
1644 pub mod R {}
1645 pub mod W {}
1646 pub mod RW {}
1647 }
1648}
1649#[doc = "ETC_TRIG Chain 4/5 Register"]
1650pub mod TRIG2_CHAIN_5_4 {
1651 #[doc = "CHAIN4 CSEL"]
1652 pub mod CSEL4 {
1653 pub const offset: u32 = 0;
1654 pub const mask: u32 = 0x0f << offset;
1655 pub mod R {}
1656 pub mod W {}
1657 pub mod RW {}
1658 }
1659 #[doc = "CHAIN4 HWTS"]
1660 pub mod HWTS4 {
1661 pub const offset: u32 = 4;
1662 pub const mask: u32 = 0xff << offset;
1663 pub mod R {}
1664 pub mod W {}
1665 pub mod RW {}
1666 }
1667 #[doc = "CHAIN4 B2B"]
1668 pub mod B2B4 {
1669 pub const offset: u32 = 12;
1670 pub const mask: u32 = 0x01 << offset;
1671 pub mod R {}
1672 pub mod W {}
1673 pub mod RW {}
1674 }
1675 #[doc = "CHAIN4 IE"]
1676 pub mod IE4 {
1677 pub const offset: u32 = 13;
1678 pub const mask: u32 = 0x03 << offset;
1679 pub mod R {}
1680 pub mod W {}
1681 pub mod RW {}
1682 }
1683 #[doc = "CHAIN5 CSEL"]
1684 pub mod CSEL5 {
1685 pub const offset: u32 = 16;
1686 pub const mask: u32 = 0x0f << offset;
1687 pub mod R {}
1688 pub mod W {}
1689 pub mod RW {}
1690 }
1691 #[doc = "CHAIN5 HWTS"]
1692 pub mod HWTS5 {
1693 pub const offset: u32 = 20;
1694 pub const mask: u32 = 0xff << offset;
1695 pub mod R {}
1696 pub mod W {}
1697 pub mod RW {}
1698 }
1699 #[doc = "CHAIN5 B2B"]
1700 pub mod B2B5 {
1701 pub const offset: u32 = 28;
1702 pub const mask: u32 = 0x01 << offset;
1703 pub mod R {}
1704 pub mod W {}
1705 pub mod RW {}
1706 }
1707 #[doc = "CHAIN5 IE"]
1708 pub mod IE5 {
1709 pub const offset: u32 = 29;
1710 pub const mask: u32 = 0x03 << offset;
1711 pub mod R {}
1712 pub mod W {}
1713 pub mod RW {}
1714 }
1715}
1716#[doc = "ETC_TRIG Chain 6/7 Register"]
1717pub mod TRIG2_CHAIN_7_6 {
1718 #[doc = "CHAIN6 CSEL"]
1719 pub mod CSEL6 {
1720 pub const offset: u32 = 0;
1721 pub const mask: u32 = 0x0f << offset;
1722 pub mod R {}
1723 pub mod W {}
1724 pub mod RW {}
1725 }
1726 #[doc = "CHAIN6 HWTS"]
1727 pub mod HWTS6 {
1728 pub const offset: u32 = 4;
1729 pub const mask: u32 = 0xff << offset;
1730 pub mod R {}
1731 pub mod W {}
1732 pub mod RW {}
1733 }
1734 #[doc = "CHAIN6 B2B"]
1735 pub mod B2B6 {
1736 pub const offset: u32 = 12;
1737 pub const mask: u32 = 0x01 << offset;
1738 pub mod R {}
1739 pub mod W {}
1740 pub mod RW {}
1741 }
1742 #[doc = "CHAIN6 IE"]
1743 pub mod IE6 {
1744 pub const offset: u32 = 13;
1745 pub const mask: u32 = 0x03 << offset;
1746 pub mod R {}
1747 pub mod W {}
1748 pub mod RW {}
1749 }
1750 #[doc = "CHAIN7 CSEL"]
1751 pub mod CSEL7 {
1752 pub const offset: u32 = 16;
1753 pub const mask: u32 = 0x0f << offset;
1754 pub mod R {}
1755 pub mod W {}
1756 pub mod RW {}
1757 }
1758 #[doc = "CHAIN7 HWTS"]
1759 pub mod HWTS7 {
1760 pub const offset: u32 = 20;
1761 pub const mask: u32 = 0xff << offset;
1762 pub mod R {}
1763 pub mod W {}
1764 pub mod RW {}
1765 }
1766 #[doc = "CHAIN7 B2B"]
1767 pub mod B2B7 {
1768 pub const offset: u32 = 28;
1769 pub const mask: u32 = 0x01 << offset;
1770 pub mod R {}
1771 pub mod W {}
1772 pub mod RW {}
1773 }
1774 #[doc = "CHAIN7 IE"]
1775 pub mod IE7 {
1776 pub const offset: u32 = 29;
1777 pub const mask: u32 = 0x03 << offset;
1778 pub mod R {}
1779 pub mod W {}
1780 pub mod RW {}
1781 }
1782}
1783#[doc = "ETC_TRIG Result Data 1/0 Register"]
1784pub mod TRIG2_RESULT_1_0 {
1785 #[doc = "Result DATA0"]
1786 pub mod DATA0 {
1787 pub const offset: u32 = 0;
1788 pub const mask: u32 = 0x0fff << offset;
1789 pub mod R {}
1790 pub mod W {}
1791 pub mod RW {}
1792 }
1793 #[doc = "Result DATA1"]
1794 pub mod DATA1 {
1795 pub const offset: u32 = 16;
1796 pub const mask: u32 = 0x0fff << offset;
1797 pub mod R {}
1798 pub mod W {}
1799 pub mod RW {}
1800 }
1801}
1802#[doc = "ETC_TRIG Result Data 3/2 Register"]
1803pub mod TRIG2_RESULT_3_2 {
1804 #[doc = "Result DATA2"]
1805 pub mod DATA2 {
1806 pub const offset: u32 = 0;
1807 pub const mask: u32 = 0x0fff << offset;
1808 pub mod R {}
1809 pub mod W {}
1810 pub mod RW {}
1811 }
1812 #[doc = "Result DATA3"]
1813 pub mod DATA3 {
1814 pub const offset: u32 = 16;
1815 pub const mask: u32 = 0x0fff << offset;
1816 pub mod R {}
1817 pub mod W {}
1818 pub mod RW {}
1819 }
1820}
1821#[doc = "ETC_TRIG Result Data 5/4 Register"]
1822pub mod TRIG2_RESULT_5_4 {
1823 #[doc = "Result DATA4"]
1824 pub mod DATA4 {
1825 pub const offset: u32 = 0;
1826 pub const mask: u32 = 0x0fff << offset;
1827 pub mod R {}
1828 pub mod W {}
1829 pub mod RW {}
1830 }
1831 #[doc = "Result DATA5"]
1832 pub mod DATA5 {
1833 pub const offset: u32 = 16;
1834 pub const mask: u32 = 0x0fff << offset;
1835 pub mod R {}
1836 pub mod W {}
1837 pub mod RW {}
1838 }
1839}
1840#[doc = "ETC_TRIG Result Data 7/6 Register"]
1841pub mod TRIG2_RESULT_7_6 {
1842 #[doc = "Result DATA6"]
1843 pub mod DATA6 {
1844 pub const offset: u32 = 0;
1845 pub const mask: u32 = 0x0fff << offset;
1846 pub mod R {}
1847 pub mod W {}
1848 pub mod RW {}
1849 }
1850 #[doc = "Result DATA7"]
1851 pub mod DATA7 {
1852 pub const offset: u32 = 16;
1853 pub const mask: u32 = 0x0fff << offset;
1854 pub mod R {}
1855 pub mod W {}
1856 pub mod RW {}
1857 }
1858}
1859#[doc = "ETC_TRIG3 Control Register"]
1860pub mod TRIG3_CTRL {
1861 #[doc = "Software write 1 as the TRIGGER. This register is self-clearing."]
1862 pub mod SW_TRIG {
1863 pub const offset: u32 = 0;
1864 pub const mask: u32 = 0x01 << offset;
1865 pub mod R {}
1866 pub mod W {}
1867 pub mod RW {}
1868 }
1869 #[doc = "TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger."]
1870 pub mod TRIG_MODE {
1871 pub const offset: u32 = 4;
1872 pub const mask: u32 = 0x01 << offset;
1873 pub mod R {}
1874 pub mod W {}
1875 pub mod RW {}
1876 }
1877 #[doc = "TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;"]
1878 pub mod TRIG_CHAIN {
1879 pub const offset: u32 = 8;
1880 pub const mask: u32 = 0x07 << offset;
1881 pub mod R {}
1882 pub mod W {}
1883 pub mod RW {}
1884 }
1885 #[doc = "External trigger priority, 7 is highest, 0 is lowest ."]
1886 pub mod TRIG_PRIORITY {
1887 pub const offset: u32 = 12;
1888 pub const mask: u32 = 0x07 << offset;
1889 pub mod R {}
1890 pub mod W {}
1891 pub mod RW {}
1892 }
1893 #[doc = "TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode"]
1894 pub mod SYNC_MODE {
1895 pub const offset: u32 = 16;
1896 pub const mask: u32 = 0x01 << offset;
1897 pub mod R {}
1898 pub mod W {}
1899 pub mod RW {}
1900 }
1901}
1902#[doc = "ETC_TRIG3 Counter Register"]
1903pub mod TRIG3_COUNTER {
1904 #[doc = "TRIGGER initial delay counter"]
1905 pub mod INIT_DELAY {
1906 pub const offset: u32 = 0;
1907 pub const mask: u32 = 0xffff << offset;
1908 pub mod R {}
1909 pub mod W {}
1910 pub mod RW {}
1911 }
1912 #[doc = "TRIGGER sampling interval counter"]
1913 pub mod SAMPLE_INTERVAL {
1914 pub const offset: u32 = 16;
1915 pub const mask: u32 = 0xffff << offset;
1916 pub mod R {}
1917 pub mod W {}
1918 pub mod RW {}
1919 }
1920}
1921#[doc = "ETC_TRIG Chain 0/1 Register"]
1922pub mod TRIG3_CHAIN_1_0 {
1923 #[doc = "CHAIN0 CSEL ADC channel selection"]
1924 pub mod CSEL0 {
1925 pub const offset: u32 = 0;
1926 pub const mask: u32 = 0x0f << offset;
1927 pub mod R {}
1928 pub mod W {}
1929 pub mod RW {}
1930 }
1931 #[doc = "CHAIN0 HWTS ADC hardware trigger selection"]
1932 pub mod HWTS0 {
1933 pub const offset: u32 = 4;
1934 pub const mask: u32 = 0xff << offset;
1935 pub mod R {}
1936 pub mod W {}
1937 pub mod RW {}
1938 }
1939 #[doc = "CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger"]
1940 pub mod B2B0 {
1941 pub const offset: u32 = 12;
1942 pub const mask: u32 = 0x01 << offset;
1943 pub mod R {}
1944 pub mod W {}
1945 pub mod RW {}
1946 }
1947 #[doc = "CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2"]
1948 pub mod IE0 {
1949 pub const offset: u32 = 13;
1950 pub const mask: u32 = 0x03 << offset;
1951 pub mod R {}
1952 pub mod W {}
1953 pub mod RW {}
1954 }
1955 #[doc = "CHAIN1 CSEL ADC channel selection"]
1956 pub mod CSEL1 {
1957 pub const offset: u32 = 16;
1958 pub const mask: u32 = 0x0f << offset;
1959 pub mod R {}
1960 pub mod W {}
1961 pub mod RW {}
1962 }
1963 #[doc = "CHAIN1 HWTS ADC hardware trigger selection"]
1964 pub mod HWTS1 {
1965 pub const offset: u32 = 20;
1966 pub const mask: u32 = 0xff << offset;
1967 pub mod R {}
1968 pub mod W {}
1969 pub mod RW {}
1970 }
1971 #[doc = "CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger"]
1972 pub mod B2B1 {
1973 pub const offset: u32 = 28;
1974 pub const mask: u32 = 0x01 << offset;
1975 pub mod R {}
1976 pub mod W {}
1977 pub mod RW {}
1978 }
1979 #[doc = "CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2"]
1980 pub mod IE1 {
1981 pub const offset: u32 = 29;
1982 pub const mask: u32 = 0x03 << offset;
1983 pub mod R {}
1984 pub mod W {}
1985 pub mod RW {}
1986 }
1987}
1988#[doc = "ETC_TRIG Chain 2/3 Register"]
1989pub mod TRIG3_CHAIN_3_2 {
1990 #[doc = "CHAIN2 CSEL"]
1991 pub mod CSEL2 {
1992 pub const offset: u32 = 0;
1993 pub const mask: u32 = 0x0f << offset;
1994 pub mod R {}
1995 pub mod W {}
1996 pub mod RW {}
1997 }
1998 #[doc = "CHAIN2 HWTS"]
1999 pub mod HWTS2 {
2000 pub const offset: u32 = 4;
2001 pub const mask: u32 = 0xff << offset;
2002 pub mod R {}
2003 pub mod W {}
2004 pub mod RW {}
2005 }
2006 #[doc = "CHAIN2 B2B"]
2007 pub mod B2B2 {
2008 pub const offset: u32 = 12;
2009 pub const mask: u32 = 0x01 << offset;
2010 pub mod R {}
2011 pub mod W {}
2012 pub mod RW {}
2013 }
2014 #[doc = "CHAIN2 IE"]
2015 pub mod IE2 {
2016 pub const offset: u32 = 13;
2017 pub const mask: u32 = 0x03 << offset;
2018 pub mod R {}
2019 pub mod W {}
2020 pub mod RW {}
2021 }
2022 #[doc = "CHAIN3 CSEL"]
2023 pub mod CSEL3 {
2024 pub const offset: u32 = 16;
2025 pub const mask: u32 = 0x0f << offset;
2026 pub mod R {}
2027 pub mod W {}
2028 pub mod RW {}
2029 }
2030 #[doc = "CHAIN3 HWTS"]
2031 pub mod HWTS3 {
2032 pub const offset: u32 = 20;
2033 pub const mask: u32 = 0xff << offset;
2034 pub mod R {}
2035 pub mod W {}
2036 pub mod RW {}
2037 }
2038 #[doc = "CHAIN3 B2B"]
2039 pub mod B2B3 {
2040 pub const offset: u32 = 28;
2041 pub const mask: u32 = 0x01 << offset;
2042 pub mod R {}
2043 pub mod W {}
2044 pub mod RW {}
2045 }
2046 #[doc = "CHAIN3 IE"]
2047 pub mod IE3 {
2048 pub const offset: u32 = 29;
2049 pub const mask: u32 = 0x03 << offset;
2050 pub mod R {}
2051 pub mod W {}
2052 pub mod RW {}
2053 }
2054}
2055#[doc = "ETC_TRIG Chain 4/5 Register"]
2056pub mod TRIG3_CHAIN_5_4 {
2057 #[doc = "CHAIN4 CSEL"]
2058 pub mod CSEL4 {
2059 pub const offset: u32 = 0;
2060 pub const mask: u32 = 0x0f << offset;
2061 pub mod R {}
2062 pub mod W {}
2063 pub mod RW {}
2064 }
2065 #[doc = "CHAIN4 HWTS"]
2066 pub mod HWTS4 {
2067 pub const offset: u32 = 4;
2068 pub const mask: u32 = 0xff << offset;
2069 pub mod R {}
2070 pub mod W {}
2071 pub mod RW {}
2072 }
2073 #[doc = "CHAIN4 B2B"]
2074 pub mod B2B4 {
2075 pub const offset: u32 = 12;
2076 pub const mask: u32 = 0x01 << offset;
2077 pub mod R {}
2078 pub mod W {}
2079 pub mod RW {}
2080 }
2081 #[doc = "CHAIN4 IE"]
2082 pub mod IE4 {
2083 pub const offset: u32 = 13;
2084 pub const mask: u32 = 0x03 << offset;
2085 pub mod R {}
2086 pub mod W {}
2087 pub mod RW {}
2088 }
2089 #[doc = "CHAIN5 CSEL"]
2090 pub mod CSEL5 {
2091 pub const offset: u32 = 16;
2092 pub const mask: u32 = 0x0f << offset;
2093 pub mod R {}
2094 pub mod W {}
2095 pub mod RW {}
2096 }
2097 #[doc = "CHAIN5 HWTS"]
2098 pub mod HWTS5 {
2099 pub const offset: u32 = 20;
2100 pub const mask: u32 = 0xff << offset;
2101 pub mod R {}
2102 pub mod W {}
2103 pub mod RW {}
2104 }
2105 #[doc = "CHAIN5 B2B"]
2106 pub mod B2B5 {
2107 pub const offset: u32 = 28;
2108 pub const mask: u32 = 0x01 << offset;
2109 pub mod R {}
2110 pub mod W {}
2111 pub mod RW {}
2112 }
2113 #[doc = "CHAIN5 IE"]
2114 pub mod IE5 {
2115 pub const offset: u32 = 29;
2116 pub const mask: u32 = 0x03 << offset;
2117 pub mod R {}
2118 pub mod W {}
2119 pub mod RW {}
2120 }
2121}
2122#[doc = "ETC_TRIG Chain 6/7 Register"]
2123pub mod TRIG3_CHAIN_7_6 {
2124 #[doc = "CHAIN6 CSEL"]
2125 pub mod CSEL6 {
2126 pub const offset: u32 = 0;
2127 pub const mask: u32 = 0x0f << offset;
2128 pub mod R {}
2129 pub mod W {}
2130 pub mod RW {}
2131 }
2132 #[doc = "CHAIN6 HWTS"]
2133 pub mod HWTS6 {
2134 pub const offset: u32 = 4;
2135 pub const mask: u32 = 0xff << offset;
2136 pub mod R {}
2137 pub mod W {}
2138 pub mod RW {}
2139 }
2140 #[doc = "CHAIN6 B2B"]
2141 pub mod B2B6 {
2142 pub const offset: u32 = 12;
2143 pub const mask: u32 = 0x01 << offset;
2144 pub mod R {}
2145 pub mod W {}
2146 pub mod RW {}
2147 }
2148 #[doc = "CHAIN6 IE"]
2149 pub mod IE6 {
2150 pub const offset: u32 = 13;
2151 pub const mask: u32 = 0x03 << offset;
2152 pub mod R {}
2153 pub mod W {}
2154 pub mod RW {}
2155 }
2156 #[doc = "CHAIN7 CSEL"]
2157 pub mod CSEL7 {
2158 pub const offset: u32 = 16;
2159 pub const mask: u32 = 0x0f << offset;
2160 pub mod R {}
2161 pub mod W {}
2162 pub mod RW {}
2163 }
2164 #[doc = "CHAIN7 HWTS"]
2165 pub mod HWTS7 {
2166 pub const offset: u32 = 20;
2167 pub const mask: u32 = 0xff << offset;
2168 pub mod R {}
2169 pub mod W {}
2170 pub mod RW {}
2171 }
2172 #[doc = "CHAIN7 B2B"]
2173 pub mod B2B7 {
2174 pub const offset: u32 = 28;
2175 pub const mask: u32 = 0x01 << offset;
2176 pub mod R {}
2177 pub mod W {}
2178 pub mod RW {}
2179 }
2180 #[doc = "CHAIN7 IE"]
2181 pub mod IE7 {
2182 pub const offset: u32 = 29;
2183 pub const mask: u32 = 0x03 << offset;
2184 pub mod R {}
2185 pub mod W {}
2186 pub mod RW {}
2187 }
2188}
2189#[doc = "ETC_TRIG Result Data 1/0 Register"]
2190pub mod TRIG3_RESULT_1_0 {
2191 #[doc = "Result DATA0"]
2192 pub mod DATA0 {
2193 pub const offset: u32 = 0;
2194 pub const mask: u32 = 0x0fff << offset;
2195 pub mod R {}
2196 pub mod W {}
2197 pub mod RW {}
2198 }
2199 #[doc = "Result DATA1"]
2200 pub mod DATA1 {
2201 pub const offset: u32 = 16;
2202 pub const mask: u32 = 0x0fff << offset;
2203 pub mod R {}
2204 pub mod W {}
2205 pub mod RW {}
2206 }
2207}
2208#[doc = "ETC_TRIG Result Data 3/2 Register"]
2209pub mod TRIG3_RESULT_3_2 {
2210 #[doc = "Result DATA2"]
2211 pub mod DATA2 {
2212 pub const offset: u32 = 0;
2213 pub const mask: u32 = 0x0fff << offset;
2214 pub mod R {}
2215 pub mod W {}
2216 pub mod RW {}
2217 }
2218 #[doc = "Result DATA3"]
2219 pub mod DATA3 {
2220 pub const offset: u32 = 16;
2221 pub const mask: u32 = 0x0fff << offset;
2222 pub mod R {}
2223 pub mod W {}
2224 pub mod RW {}
2225 }
2226}
2227#[doc = "ETC_TRIG Result Data 5/4 Register"]
2228pub mod TRIG3_RESULT_5_4 {
2229 #[doc = "Result DATA4"]
2230 pub mod DATA4 {
2231 pub const offset: u32 = 0;
2232 pub const mask: u32 = 0x0fff << offset;
2233 pub mod R {}
2234 pub mod W {}
2235 pub mod RW {}
2236 }
2237 #[doc = "Result DATA5"]
2238 pub mod DATA5 {
2239 pub const offset: u32 = 16;
2240 pub const mask: u32 = 0x0fff << offset;
2241 pub mod R {}
2242 pub mod W {}
2243 pub mod RW {}
2244 }
2245}
2246#[doc = "ETC_TRIG Result Data 7/6 Register"]
2247pub mod TRIG3_RESULT_7_6 {
2248 #[doc = "Result DATA6"]
2249 pub mod DATA6 {
2250 pub const offset: u32 = 0;
2251 pub const mask: u32 = 0x0fff << offset;
2252 pub mod R {}
2253 pub mod W {}
2254 pub mod RW {}
2255 }
2256 #[doc = "Result DATA7"]
2257 pub mod DATA7 {
2258 pub const offset: u32 = 16;
2259 pub const mask: u32 = 0x0fff << offset;
2260 pub mod R {}
2261 pub mod W {}
2262 pub mod RW {}
2263 }
2264}
2265#[doc = "ETC_TRIG4 Control Register"]
2266pub mod TRIG4_CTRL {
2267 #[doc = "Software write 1 as the TRIGGER. This register is self-clearing."]
2268 pub mod SW_TRIG {
2269 pub const offset: u32 = 0;
2270 pub const mask: u32 = 0x01 << offset;
2271 pub mod R {}
2272 pub mod W {}
2273 pub mod RW {}
2274 }
2275 #[doc = "TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger."]
2276 pub mod TRIG_MODE {
2277 pub const offset: u32 = 4;
2278 pub const mask: u32 = 0x01 << offset;
2279 pub mod R {}
2280 pub mod W {}
2281 pub mod RW {}
2282 }
2283 #[doc = "TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;"]
2284 pub mod TRIG_CHAIN {
2285 pub const offset: u32 = 8;
2286 pub const mask: u32 = 0x07 << offset;
2287 pub mod R {}
2288 pub mod W {}
2289 pub mod RW {}
2290 }
2291 #[doc = "External trigger priority, 7 is highest, 0 is lowest ."]
2292 pub mod TRIG_PRIORITY {
2293 pub const offset: u32 = 12;
2294 pub const mask: u32 = 0x07 << offset;
2295 pub mod R {}
2296 pub mod W {}
2297 pub mod RW {}
2298 }
2299 #[doc = "TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode"]
2300 pub mod SYNC_MODE {
2301 pub const offset: u32 = 16;
2302 pub const mask: u32 = 0x01 << offset;
2303 pub mod R {}
2304 pub mod W {}
2305 pub mod RW {}
2306 }
2307}
2308#[doc = "ETC_TRIG4 Counter Register"]
2309pub mod TRIG4_COUNTER {
2310 #[doc = "TRIGGER initial delay counter"]
2311 pub mod INIT_DELAY {
2312 pub const offset: u32 = 0;
2313 pub const mask: u32 = 0xffff << offset;
2314 pub mod R {}
2315 pub mod W {}
2316 pub mod RW {}
2317 }
2318 #[doc = "TRIGGER sampling interval counter"]
2319 pub mod SAMPLE_INTERVAL {
2320 pub const offset: u32 = 16;
2321 pub const mask: u32 = 0xffff << offset;
2322 pub mod R {}
2323 pub mod W {}
2324 pub mod RW {}
2325 }
2326}
2327#[doc = "ETC_TRIG Chain 0/1 Register"]
2328pub mod TRIG4_CHAIN_1_0 {
2329 #[doc = "CHAIN0 CSEL ADC channel selection"]
2330 pub mod CSEL0 {
2331 pub const offset: u32 = 0;
2332 pub const mask: u32 = 0x0f << offset;
2333 pub mod R {}
2334 pub mod W {}
2335 pub mod RW {}
2336 }
2337 #[doc = "CHAIN0 HWTS ADC hardware trigger selection"]
2338 pub mod HWTS0 {
2339 pub const offset: u32 = 4;
2340 pub const mask: u32 = 0xff << offset;
2341 pub mod R {}
2342 pub mod W {}
2343 pub mod RW {}
2344 }
2345 #[doc = "CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger"]
2346 pub mod B2B0 {
2347 pub const offset: u32 = 12;
2348 pub const mask: u32 = 0x01 << offset;
2349 pub mod R {}
2350 pub mod W {}
2351 pub mod RW {}
2352 }
2353 #[doc = "CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2"]
2354 pub mod IE0 {
2355 pub const offset: u32 = 13;
2356 pub const mask: u32 = 0x03 << offset;
2357 pub mod R {}
2358 pub mod W {}
2359 pub mod RW {}
2360 }
2361 #[doc = "CHAIN1 CSEL ADC channel selection"]
2362 pub mod CSEL1 {
2363 pub const offset: u32 = 16;
2364 pub const mask: u32 = 0x0f << offset;
2365 pub mod R {}
2366 pub mod W {}
2367 pub mod RW {}
2368 }
2369 #[doc = "CHAIN1 HWTS ADC hardware trigger selection"]
2370 pub mod HWTS1 {
2371 pub const offset: u32 = 20;
2372 pub const mask: u32 = 0xff << offset;
2373 pub mod R {}
2374 pub mod W {}
2375 pub mod RW {}
2376 }
2377 #[doc = "CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger"]
2378 pub mod B2B1 {
2379 pub const offset: u32 = 28;
2380 pub const mask: u32 = 0x01 << offset;
2381 pub mod R {}
2382 pub mod W {}
2383 pub mod RW {}
2384 }
2385 #[doc = "CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2"]
2386 pub mod IE1 {
2387 pub const offset: u32 = 29;
2388 pub const mask: u32 = 0x03 << offset;
2389 pub mod R {}
2390 pub mod W {}
2391 pub mod RW {}
2392 }
2393}
2394#[doc = "ETC_TRIG Chain 2/3 Register"]
2395pub mod TRIG4_CHAIN_3_2 {
2396 #[doc = "CHAIN2 CSEL"]
2397 pub mod CSEL2 {
2398 pub const offset: u32 = 0;
2399 pub const mask: u32 = 0x0f << offset;
2400 pub mod R {}
2401 pub mod W {}
2402 pub mod RW {}
2403 }
2404 #[doc = "CHAIN2 HWTS"]
2405 pub mod HWTS2 {
2406 pub const offset: u32 = 4;
2407 pub const mask: u32 = 0xff << offset;
2408 pub mod R {}
2409 pub mod W {}
2410 pub mod RW {}
2411 }
2412 #[doc = "CHAIN2 B2B"]
2413 pub mod B2B2 {
2414 pub const offset: u32 = 12;
2415 pub const mask: u32 = 0x01 << offset;
2416 pub mod R {}
2417 pub mod W {}
2418 pub mod RW {}
2419 }
2420 #[doc = "CHAIN2 IE"]
2421 pub mod IE2 {
2422 pub const offset: u32 = 13;
2423 pub const mask: u32 = 0x03 << offset;
2424 pub mod R {}
2425 pub mod W {}
2426 pub mod RW {}
2427 }
2428 #[doc = "CHAIN3 CSEL"]
2429 pub mod CSEL3 {
2430 pub const offset: u32 = 16;
2431 pub const mask: u32 = 0x0f << offset;
2432 pub mod R {}
2433 pub mod W {}
2434 pub mod RW {}
2435 }
2436 #[doc = "CHAIN3 HWTS"]
2437 pub mod HWTS3 {
2438 pub const offset: u32 = 20;
2439 pub const mask: u32 = 0xff << offset;
2440 pub mod R {}
2441 pub mod W {}
2442 pub mod RW {}
2443 }
2444 #[doc = "CHAIN3 B2B"]
2445 pub mod B2B3 {
2446 pub const offset: u32 = 28;
2447 pub const mask: u32 = 0x01 << offset;
2448 pub mod R {}
2449 pub mod W {}
2450 pub mod RW {}
2451 }
2452 #[doc = "CHAIN3 IE"]
2453 pub mod IE3 {
2454 pub const offset: u32 = 29;
2455 pub const mask: u32 = 0x03 << offset;
2456 pub mod R {}
2457 pub mod W {}
2458 pub mod RW {}
2459 }
2460}
2461#[doc = "ETC_TRIG Chain 4/5 Register"]
2462pub mod TRIG4_CHAIN_5_4 {
2463 #[doc = "CHAIN4 CSEL"]
2464 pub mod CSEL4 {
2465 pub const offset: u32 = 0;
2466 pub const mask: u32 = 0x0f << offset;
2467 pub mod R {}
2468 pub mod W {}
2469 pub mod RW {}
2470 }
2471 #[doc = "CHAIN4 HWTS"]
2472 pub mod HWTS4 {
2473 pub const offset: u32 = 4;
2474 pub const mask: u32 = 0xff << offset;
2475 pub mod R {}
2476 pub mod W {}
2477 pub mod RW {}
2478 }
2479 #[doc = "CHAIN4 B2B"]
2480 pub mod B2B4 {
2481 pub const offset: u32 = 12;
2482 pub const mask: u32 = 0x01 << offset;
2483 pub mod R {}
2484 pub mod W {}
2485 pub mod RW {}
2486 }
2487 #[doc = "CHAIN4 IE"]
2488 pub mod IE4 {
2489 pub const offset: u32 = 13;
2490 pub const mask: u32 = 0x03 << offset;
2491 pub mod R {}
2492 pub mod W {}
2493 pub mod RW {}
2494 }
2495 #[doc = "CHAIN5 CSEL"]
2496 pub mod CSEL5 {
2497 pub const offset: u32 = 16;
2498 pub const mask: u32 = 0x0f << offset;
2499 pub mod R {}
2500 pub mod W {}
2501 pub mod RW {}
2502 }
2503 #[doc = "CHAIN5 HWTS"]
2504 pub mod HWTS5 {
2505 pub const offset: u32 = 20;
2506 pub const mask: u32 = 0xff << offset;
2507 pub mod R {}
2508 pub mod W {}
2509 pub mod RW {}
2510 }
2511 #[doc = "CHAIN5 B2B"]
2512 pub mod B2B5 {
2513 pub const offset: u32 = 28;
2514 pub const mask: u32 = 0x01 << offset;
2515 pub mod R {}
2516 pub mod W {}
2517 pub mod RW {}
2518 }
2519 #[doc = "CHAIN5 IE"]
2520 pub mod IE5 {
2521 pub const offset: u32 = 29;
2522 pub const mask: u32 = 0x03 << offset;
2523 pub mod R {}
2524 pub mod W {}
2525 pub mod RW {}
2526 }
2527}
2528#[doc = "ETC_TRIG Chain 6/7 Register"]
2529pub mod TRIG4_CHAIN_7_6 {
2530 #[doc = "CHAIN6 CSEL"]
2531 pub mod CSEL6 {
2532 pub const offset: u32 = 0;
2533 pub const mask: u32 = 0x0f << offset;
2534 pub mod R {}
2535 pub mod W {}
2536 pub mod RW {}
2537 }
2538 #[doc = "CHAIN6 HWTS"]
2539 pub mod HWTS6 {
2540 pub const offset: u32 = 4;
2541 pub const mask: u32 = 0xff << offset;
2542 pub mod R {}
2543 pub mod W {}
2544 pub mod RW {}
2545 }
2546 #[doc = "CHAIN6 B2B"]
2547 pub mod B2B6 {
2548 pub const offset: u32 = 12;
2549 pub const mask: u32 = 0x01 << offset;
2550 pub mod R {}
2551 pub mod W {}
2552 pub mod RW {}
2553 }
2554 #[doc = "CHAIN6 IE"]
2555 pub mod IE6 {
2556 pub const offset: u32 = 13;
2557 pub const mask: u32 = 0x03 << offset;
2558 pub mod R {}
2559 pub mod W {}
2560 pub mod RW {}
2561 }
2562 #[doc = "CHAIN7 CSEL"]
2563 pub mod CSEL7 {
2564 pub const offset: u32 = 16;
2565 pub const mask: u32 = 0x0f << offset;
2566 pub mod R {}
2567 pub mod W {}
2568 pub mod RW {}
2569 }
2570 #[doc = "CHAIN7 HWTS"]
2571 pub mod HWTS7 {
2572 pub const offset: u32 = 20;
2573 pub const mask: u32 = 0xff << offset;
2574 pub mod R {}
2575 pub mod W {}
2576 pub mod RW {}
2577 }
2578 #[doc = "CHAIN7 B2B"]
2579 pub mod B2B7 {
2580 pub const offset: u32 = 28;
2581 pub const mask: u32 = 0x01 << offset;
2582 pub mod R {}
2583 pub mod W {}
2584 pub mod RW {}
2585 }
2586 #[doc = "CHAIN7 IE"]
2587 pub mod IE7 {
2588 pub const offset: u32 = 29;
2589 pub const mask: u32 = 0x03 << offset;
2590 pub mod R {}
2591 pub mod W {}
2592 pub mod RW {}
2593 }
2594}
2595#[doc = "ETC_TRIG Result Data 1/0 Register"]
2596pub mod TRIG4_RESULT_1_0 {
2597 #[doc = "Result DATA0"]
2598 pub mod DATA0 {
2599 pub const offset: u32 = 0;
2600 pub const mask: u32 = 0x0fff << offset;
2601 pub mod R {}
2602 pub mod W {}
2603 pub mod RW {}
2604 }
2605 #[doc = "Result DATA1"]
2606 pub mod DATA1 {
2607 pub const offset: u32 = 16;
2608 pub const mask: u32 = 0x0fff << offset;
2609 pub mod R {}
2610 pub mod W {}
2611 pub mod RW {}
2612 }
2613}
2614#[doc = "ETC_TRIG Result Data 3/2 Register"]
2615pub mod TRIG4_RESULT_3_2 {
2616 #[doc = "Result DATA2"]
2617 pub mod DATA2 {
2618 pub const offset: u32 = 0;
2619 pub const mask: u32 = 0x0fff << offset;
2620 pub mod R {}
2621 pub mod W {}
2622 pub mod RW {}
2623 }
2624 #[doc = "Result DATA3"]
2625 pub mod DATA3 {
2626 pub const offset: u32 = 16;
2627 pub const mask: u32 = 0x0fff << offset;
2628 pub mod R {}
2629 pub mod W {}
2630 pub mod RW {}
2631 }
2632}
2633#[doc = "ETC_TRIG Result Data 5/4 Register"]
2634pub mod TRIG4_RESULT_5_4 {
2635 #[doc = "Result DATA4"]
2636 pub mod DATA4 {
2637 pub const offset: u32 = 0;
2638 pub const mask: u32 = 0x0fff << offset;
2639 pub mod R {}
2640 pub mod W {}
2641 pub mod RW {}
2642 }
2643 #[doc = "Result DATA5"]
2644 pub mod DATA5 {
2645 pub const offset: u32 = 16;
2646 pub const mask: u32 = 0x0fff << offset;
2647 pub mod R {}
2648 pub mod W {}
2649 pub mod RW {}
2650 }
2651}
2652#[doc = "ETC_TRIG Result Data 7/6 Register"]
2653pub mod TRIG4_RESULT_7_6 {
2654 #[doc = "Result DATA6"]
2655 pub mod DATA6 {
2656 pub const offset: u32 = 0;
2657 pub const mask: u32 = 0x0fff << offset;
2658 pub mod R {}
2659 pub mod W {}
2660 pub mod RW {}
2661 }
2662 #[doc = "Result DATA7"]
2663 pub mod DATA7 {
2664 pub const offset: u32 = 16;
2665 pub const mask: u32 = 0x0fff << offset;
2666 pub mod R {}
2667 pub mod W {}
2668 pub mod RW {}
2669 }
2670}
2671#[doc = "ETC_TRIG5 Control Register"]
2672pub mod TRIG5_CTRL {
2673 #[doc = "Software write 1 as the TRIGGER"]
2674 pub mod SW_TRIG {
2675 pub const offset: u32 = 0;
2676 pub const mask: u32 = 0x01 << offset;
2677 pub mod R {}
2678 pub mod W {}
2679 pub mod RW {}
2680 }
2681 #[doc = "TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger."]
2682 pub mod TRIG_MODE {
2683 pub const offset: u32 = 4;
2684 pub const mask: u32 = 0x01 << offset;
2685 pub mod R {}
2686 pub mod W {}
2687 pub mod RW {}
2688 }
2689 #[doc = "TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;"]
2690 pub mod TRIG_CHAIN {
2691 pub const offset: u32 = 8;
2692 pub const mask: u32 = 0x07 << offset;
2693 pub mod R {}
2694 pub mod W {}
2695 pub mod RW {}
2696 }
2697 #[doc = "External trigger priority, 7 is highest, 0 is lowest ."]
2698 pub mod TRIG_PRIORITY {
2699 pub const offset: u32 = 12;
2700 pub const mask: u32 = 0x07 << offset;
2701 pub mod R {}
2702 pub mod W {}
2703 pub mod RW {}
2704 }
2705 #[doc = "TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode"]
2706 pub mod SYNC_MODE {
2707 pub const offset: u32 = 16;
2708 pub const mask: u32 = 0x01 << offset;
2709 pub mod R {}
2710 pub mod W {}
2711 pub mod RW {}
2712 }
2713}
2714#[doc = "ETC_TRIG5 Counter Register"]
2715pub mod TRIG5_COUNTER {
2716 #[doc = "TRIGGER initial delay counter"]
2717 pub mod INIT_DELAY {
2718 pub const offset: u32 = 0;
2719 pub const mask: u32 = 0xffff << offset;
2720 pub mod R {}
2721 pub mod W {}
2722 pub mod RW {}
2723 }
2724 #[doc = "TRIGGER sampling interval counter"]
2725 pub mod SAMPLE_INTERVAL {
2726 pub const offset: u32 = 16;
2727 pub const mask: u32 = 0xffff << offset;
2728 pub mod R {}
2729 pub mod W {}
2730 pub mod RW {}
2731 }
2732}
2733#[doc = "ETC_TRIG Chain 0/1 Register"]
2734pub mod TRIG5_CHAIN_1_0 {
2735 #[doc = "CHAIN0 CSEL ADC channel selection"]
2736 pub mod CSEL0 {
2737 pub const offset: u32 = 0;
2738 pub const mask: u32 = 0x0f << offset;
2739 pub mod R {}
2740 pub mod W {}
2741 pub mod RW {}
2742 }
2743 #[doc = "CHAIN0 HWTS ADC hardware trigger selection"]
2744 pub mod HWTS0 {
2745 pub const offset: u32 = 4;
2746 pub const mask: u32 = 0xff << offset;
2747 pub mod R {}
2748 pub mod W {}
2749 pub mod RW {}
2750 }
2751 #[doc = "CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger"]
2752 pub mod B2B0 {
2753 pub const offset: u32 = 12;
2754 pub const mask: u32 = 0x01 << offset;
2755 pub mod R {}
2756 pub mod W {}
2757 pub mod RW {}
2758 }
2759 #[doc = "CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2"]
2760 pub mod IE0 {
2761 pub const offset: u32 = 13;
2762 pub const mask: u32 = 0x03 << offset;
2763 pub mod R {}
2764 pub mod W {}
2765 pub mod RW {}
2766 }
2767 #[doc = "CHAIN1 CSEL ADC channel selection"]
2768 pub mod CSEL1 {
2769 pub const offset: u32 = 16;
2770 pub const mask: u32 = 0x0f << offset;
2771 pub mod R {}
2772 pub mod W {}
2773 pub mod RW {}
2774 }
2775 #[doc = "CHAIN1 HWTS ADC hardware trigger selection"]
2776 pub mod HWTS1 {
2777 pub const offset: u32 = 20;
2778 pub const mask: u32 = 0xff << offset;
2779 pub mod R {}
2780 pub mod W {}
2781 pub mod RW {}
2782 }
2783 #[doc = "CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger"]
2784 pub mod B2B1 {
2785 pub const offset: u32 = 28;
2786 pub const mask: u32 = 0x01 << offset;
2787 pub mod R {}
2788 pub mod W {}
2789 pub mod RW {}
2790 }
2791 #[doc = "CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2"]
2792 pub mod IE1 {
2793 pub const offset: u32 = 29;
2794 pub const mask: u32 = 0x03 << offset;
2795 pub mod R {}
2796 pub mod W {}
2797 pub mod RW {}
2798 }
2799}
2800#[doc = "ETC_TRIG Chain 2/3 Register"]
2801pub mod TRIG5_CHAIN_3_2 {
2802 #[doc = "CHAIN2 CSEL"]
2803 pub mod CSEL2 {
2804 pub const offset: u32 = 0;
2805 pub const mask: u32 = 0x0f << offset;
2806 pub mod R {}
2807 pub mod W {}
2808 pub mod RW {}
2809 }
2810 #[doc = "CHAIN2 HWTS"]
2811 pub mod HWTS2 {
2812 pub const offset: u32 = 4;
2813 pub const mask: u32 = 0xff << offset;
2814 pub mod R {}
2815 pub mod W {}
2816 pub mod RW {}
2817 }
2818 #[doc = "CHAIN2 B2B"]
2819 pub mod B2B2 {
2820 pub const offset: u32 = 12;
2821 pub const mask: u32 = 0x01 << offset;
2822 pub mod R {}
2823 pub mod W {}
2824 pub mod RW {}
2825 }
2826 #[doc = "CHAIN2 IE"]
2827 pub mod IE2 {
2828 pub const offset: u32 = 13;
2829 pub const mask: u32 = 0x03 << offset;
2830 pub mod R {}
2831 pub mod W {}
2832 pub mod RW {}
2833 }
2834 #[doc = "CHAIN3 CSEL"]
2835 pub mod CSEL3 {
2836 pub const offset: u32 = 16;
2837 pub const mask: u32 = 0x0f << offset;
2838 pub mod R {}
2839 pub mod W {}
2840 pub mod RW {}
2841 }
2842 #[doc = "CHAIN3 HWTS"]
2843 pub mod HWTS3 {
2844 pub const offset: u32 = 20;
2845 pub const mask: u32 = 0xff << offset;
2846 pub mod R {}
2847 pub mod W {}
2848 pub mod RW {}
2849 }
2850 #[doc = "CHAIN3 B2B"]
2851 pub mod B2B3 {
2852 pub const offset: u32 = 28;
2853 pub const mask: u32 = 0x01 << offset;
2854 pub mod R {}
2855 pub mod W {}
2856 pub mod RW {}
2857 }
2858 #[doc = "CHAIN3 IE"]
2859 pub mod IE3 {
2860 pub const offset: u32 = 29;
2861 pub const mask: u32 = 0x03 << offset;
2862 pub mod R {}
2863 pub mod W {}
2864 pub mod RW {}
2865 }
2866}
2867#[doc = "ETC_TRIG Chain 4/5 Register"]
2868pub mod TRIG5_CHAIN_5_4 {
2869 #[doc = "CHAIN4 CSEL"]
2870 pub mod CSEL4 {
2871 pub const offset: u32 = 0;
2872 pub const mask: u32 = 0x0f << offset;
2873 pub mod R {}
2874 pub mod W {}
2875 pub mod RW {}
2876 }
2877 #[doc = "CHAIN4 HWTS"]
2878 pub mod HWTS4 {
2879 pub const offset: u32 = 4;
2880 pub const mask: u32 = 0xff << offset;
2881 pub mod R {}
2882 pub mod W {}
2883 pub mod RW {}
2884 }
2885 #[doc = "CHAIN4 B2B"]
2886 pub mod B2B4 {
2887 pub const offset: u32 = 12;
2888 pub const mask: u32 = 0x01 << offset;
2889 pub mod R {}
2890 pub mod W {}
2891 pub mod RW {}
2892 }
2893 #[doc = "CHAIN4 IE"]
2894 pub mod IE4 {
2895 pub const offset: u32 = 13;
2896 pub const mask: u32 = 0x03 << offset;
2897 pub mod R {}
2898 pub mod W {}
2899 pub mod RW {}
2900 }
2901 #[doc = "CHAIN5 CSEL"]
2902 pub mod CSEL5 {
2903 pub const offset: u32 = 16;
2904 pub const mask: u32 = 0x0f << offset;
2905 pub mod R {}
2906 pub mod W {}
2907 pub mod RW {}
2908 }
2909 #[doc = "CHAIN5 HWTS"]
2910 pub mod HWTS5 {
2911 pub const offset: u32 = 20;
2912 pub const mask: u32 = 0xff << offset;
2913 pub mod R {}
2914 pub mod W {}
2915 pub mod RW {}
2916 }
2917 #[doc = "CHAIN5 B2B"]
2918 pub mod B2B5 {
2919 pub const offset: u32 = 28;
2920 pub const mask: u32 = 0x01 << offset;
2921 pub mod R {}
2922 pub mod W {}
2923 pub mod RW {}
2924 }
2925 #[doc = "CHAIN5 IE"]
2926 pub mod IE5 {
2927 pub const offset: u32 = 29;
2928 pub const mask: u32 = 0x03 << offset;
2929 pub mod R {}
2930 pub mod W {}
2931 pub mod RW {}
2932 }
2933}
2934#[doc = "ETC_TRIG Chain 6/7 Register"]
2935pub mod TRIG5_CHAIN_7_6 {
2936 #[doc = "CHAIN6 CSEL"]
2937 pub mod CSEL6 {
2938 pub const offset: u32 = 0;
2939 pub const mask: u32 = 0x0f << offset;
2940 pub mod R {}
2941 pub mod W {}
2942 pub mod RW {}
2943 }
2944 #[doc = "CHAIN6 HWTS"]
2945 pub mod HWTS6 {
2946 pub const offset: u32 = 4;
2947 pub const mask: u32 = 0xff << offset;
2948 pub mod R {}
2949 pub mod W {}
2950 pub mod RW {}
2951 }
2952 #[doc = "CHAIN6 B2B"]
2953 pub mod B2B6 {
2954 pub const offset: u32 = 12;
2955 pub const mask: u32 = 0x01 << offset;
2956 pub mod R {}
2957 pub mod W {}
2958 pub mod RW {}
2959 }
2960 #[doc = "CHAIN6 IE"]
2961 pub mod IE6 {
2962 pub const offset: u32 = 13;
2963 pub const mask: u32 = 0x03 << offset;
2964 pub mod R {}
2965 pub mod W {}
2966 pub mod RW {}
2967 }
2968 #[doc = "CHAIN7 CSEL"]
2969 pub mod CSEL7 {
2970 pub const offset: u32 = 16;
2971 pub const mask: u32 = 0x0f << offset;
2972 pub mod R {}
2973 pub mod W {}
2974 pub mod RW {}
2975 }
2976 #[doc = "CHAIN7 HWTS"]
2977 pub mod HWTS7 {
2978 pub const offset: u32 = 20;
2979 pub const mask: u32 = 0xff << offset;
2980 pub mod R {}
2981 pub mod W {}
2982 pub mod RW {}
2983 }
2984 #[doc = "CHAIN7 B2B"]
2985 pub mod B2B7 {
2986 pub const offset: u32 = 28;
2987 pub const mask: u32 = 0x01 << offset;
2988 pub mod R {}
2989 pub mod W {}
2990 pub mod RW {}
2991 }
2992 #[doc = "CHAIN7 IE"]
2993 pub mod IE7 {
2994 pub const offset: u32 = 29;
2995 pub const mask: u32 = 0x03 << offset;
2996 pub mod R {}
2997 pub mod W {}
2998 pub mod RW {}
2999 }
3000}
3001#[doc = "ETC_TRIG Result Data 1/0 Register"]
3002pub mod TRIG5_RESULT_1_0 {
3003 #[doc = "Result DATA0"]
3004 pub mod DATA0 {
3005 pub const offset: u32 = 0;
3006 pub const mask: u32 = 0x0fff << offset;
3007 pub mod R {}
3008 pub mod W {}
3009 pub mod RW {}
3010 }
3011 #[doc = "Result DATA1"]
3012 pub mod DATA1 {
3013 pub const offset: u32 = 16;
3014 pub const mask: u32 = 0x0fff << offset;
3015 pub mod R {}
3016 pub mod W {}
3017 pub mod RW {}
3018 }
3019}
3020#[doc = "ETC_TRIG Result Data 3/2 Register"]
3021pub mod TRIG5_RESULT_3_2 {
3022 #[doc = "Result DATA2"]
3023 pub mod DATA2 {
3024 pub const offset: u32 = 0;
3025 pub const mask: u32 = 0x0fff << offset;
3026 pub mod R {}
3027 pub mod W {}
3028 pub mod RW {}
3029 }
3030 #[doc = "Result DATA3"]
3031 pub mod DATA3 {
3032 pub const offset: u32 = 16;
3033 pub const mask: u32 = 0x0fff << offset;
3034 pub mod R {}
3035 pub mod W {}
3036 pub mod RW {}
3037 }
3038}
3039#[doc = "ETC_TRIG Result Data 5/4 Register"]
3040pub mod TRIG5_RESULT_5_4 {
3041 #[doc = "Result DATA4"]
3042 pub mod DATA4 {
3043 pub const offset: u32 = 0;
3044 pub const mask: u32 = 0x0fff << offset;
3045 pub mod R {}
3046 pub mod W {}
3047 pub mod RW {}
3048 }
3049 #[doc = "Result DATA5"]
3050 pub mod DATA5 {
3051 pub const offset: u32 = 16;
3052 pub const mask: u32 = 0x0fff << offset;
3053 pub mod R {}
3054 pub mod W {}
3055 pub mod RW {}
3056 }
3057}
3058#[doc = "ETC_TRIG Result Data 7/6 Register"]
3059pub mod TRIG5_RESULT_7_6 {
3060 #[doc = "Result DATA6"]
3061 pub mod DATA6 {
3062 pub const offset: u32 = 0;
3063 pub const mask: u32 = 0x0fff << offset;
3064 pub mod R {}
3065 pub mod W {}
3066 pub mod RW {}
3067 }
3068 #[doc = "Result DATA7"]
3069 pub mod DATA7 {
3070 pub const offset: u32 = 16;
3071 pub const mask: u32 = 0x0fff << offset;
3072 pub mod R {}
3073 pub mod W {}
3074 pub mod RW {}
3075 }
3076}
3077#[doc = "ETC_TRIG6 Control Register"]
3078pub mod TRIG6_CTRL {
3079 #[doc = "Software write 1 as the TRIGGER. This register is self-clearing."]
3080 pub mod SW_TRIG {
3081 pub const offset: u32 = 0;
3082 pub const mask: u32 = 0x01 << offset;
3083 pub mod R {}
3084 pub mod W {}
3085 pub mod RW {}
3086 }
3087 #[doc = "TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger."]
3088 pub mod TRIG_MODE {
3089 pub const offset: u32 = 4;
3090 pub const mask: u32 = 0x01 << offset;
3091 pub mod R {}
3092 pub mod W {}
3093 pub mod RW {}
3094 }
3095 #[doc = "TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;"]
3096 pub mod TRIG_CHAIN {
3097 pub const offset: u32 = 8;
3098 pub const mask: u32 = 0x07 << offset;
3099 pub mod R {}
3100 pub mod W {}
3101 pub mod RW {}
3102 }
3103 #[doc = "External trigger priority, 7 is highest, 0 is lowest ."]
3104 pub mod TRIG_PRIORITY {
3105 pub const offset: u32 = 12;
3106 pub const mask: u32 = 0x07 << offset;
3107 pub mod R {}
3108 pub mod W {}
3109 pub mod RW {}
3110 }
3111 #[doc = "TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode"]
3112 pub mod SYNC_MODE {
3113 pub const offset: u32 = 16;
3114 pub const mask: u32 = 0x01 << offset;
3115 pub mod R {}
3116 pub mod W {}
3117 pub mod RW {}
3118 }
3119}
3120#[doc = "ETC_TRIG6 Counter Register"]
3121pub mod TRIG6_COUNTER {
3122 #[doc = "TRIGGER initial delay counter"]
3123 pub mod INIT_DELAY {
3124 pub const offset: u32 = 0;
3125 pub const mask: u32 = 0xffff << offset;
3126 pub mod R {}
3127 pub mod W {}
3128 pub mod RW {}
3129 }
3130 #[doc = "TRIGGER sampling interval counter"]
3131 pub mod SAMPLE_INTERVAL {
3132 pub const offset: u32 = 16;
3133 pub const mask: u32 = 0xffff << offset;
3134 pub mod R {}
3135 pub mod W {}
3136 pub mod RW {}
3137 }
3138}
3139#[doc = "ETC_TRIG Chain 0/1 Register"]
3140pub mod TRIG6_CHAIN_1_0 {
3141 #[doc = "CHAIN0 CSEL ADC channel selection"]
3142 pub mod CSEL0 {
3143 pub const offset: u32 = 0;
3144 pub const mask: u32 = 0x0f << offset;
3145 pub mod R {}
3146 pub mod W {}
3147 pub mod RW {}
3148 }
3149 #[doc = "CHAIN0 HWTS ADC hardware trigger selection"]
3150 pub mod HWTS0 {
3151 pub const offset: u32 = 4;
3152 pub const mask: u32 = 0xff << offset;
3153 pub mod R {}
3154 pub mod W {}
3155 pub mod RW {}
3156 }
3157 #[doc = "CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger"]
3158 pub mod B2B0 {
3159 pub const offset: u32 = 12;
3160 pub const mask: u32 = 0x01 << offset;
3161 pub mod R {}
3162 pub mod W {}
3163 pub mod RW {}
3164 }
3165 #[doc = "CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2"]
3166 pub mod IE0 {
3167 pub const offset: u32 = 13;
3168 pub const mask: u32 = 0x03 << offset;
3169 pub mod R {}
3170 pub mod W {}
3171 pub mod RW {}
3172 }
3173 #[doc = "CHAIN1 CSEL ADC channel selection"]
3174 pub mod CSEL1 {
3175 pub const offset: u32 = 16;
3176 pub const mask: u32 = 0x0f << offset;
3177 pub mod R {}
3178 pub mod W {}
3179 pub mod RW {}
3180 }
3181 #[doc = "CHAIN1 HWTS ADC hardware trigger selection"]
3182 pub mod HWTS1 {
3183 pub const offset: u32 = 20;
3184 pub const mask: u32 = 0xff << offset;
3185 pub mod R {}
3186 pub mod W {}
3187 pub mod RW {}
3188 }
3189 #[doc = "CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger"]
3190 pub mod B2B1 {
3191 pub const offset: u32 = 28;
3192 pub const mask: u32 = 0x01 << offset;
3193 pub mod R {}
3194 pub mod W {}
3195 pub mod RW {}
3196 }
3197 #[doc = "CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2"]
3198 pub mod IE1 {
3199 pub const offset: u32 = 29;
3200 pub const mask: u32 = 0x03 << offset;
3201 pub mod R {}
3202 pub mod W {}
3203 pub mod RW {}
3204 }
3205}
3206#[doc = "ETC_TRIG Chain 2/3 Register"]
3207pub mod TRIG6_CHAIN_3_2 {
3208 #[doc = "CHAIN2 CSEL"]
3209 pub mod CSEL2 {
3210 pub const offset: u32 = 0;
3211 pub const mask: u32 = 0x0f << offset;
3212 pub mod R {}
3213 pub mod W {}
3214 pub mod RW {}
3215 }
3216 #[doc = "CHAIN2 HWTS"]
3217 pub mod HWTS2 {
3218 pub const offset: u32 = 4;
3219 pub const mask: u32 = 0xff << offset;
3220 pub mod R {}
3221 pub mod W {}
3222 pub mod RW {}
3223 }
3224 #[doc = "CHAIN2 B2B"]
3225 pub mod B2B2 {
3226 pub const offset: u32 = 12;
3227 pub const mask: u32 = 0x01 << offset;
3228 pub mod R {}
3229 pub mod W {}
3230 pub mod RW {}
3231 }
3232 #[doc = "CHAIN2 IE"]
3233 pub mod IE2 {
3234 pub const offset: u32 = 13;
3235 pub const mask: u32 = 0x03 << offset;
3236 pub mod R {}
3237 pub mod W {}
3238 pub mod RW {}
3239 }
3240 #[doc = "CHAIN3 CSEL"]
3241 pub mod CSEL3 {
3242 pub const offset: u32 = 16;
3243 pub const mask: u32 = 0x0f << offset;
3244 pub mod R {}
3245 pub mod W {}
3246 pub mod RW {}
3247 }
3248 #[doc = "CHAIN3 HWTS"]
3249 pub mod HWTS3 {
3250 pub const offset: u32 = 20;
3251 pub const mask: u32 = 0xff << offset;
3252 pub mod R {}
3253 pub mod W {}
3254 pub mod RW {}
3255 }
3256 #[doc = "CHAIN3 B2B"]
3257 pub mod B2B3 {
3258 pub const offset: u32 = 28;
3259 pub const mask: u32 = 0x01 << offset;
3260 pub mod R {}
3261 pub mod W {}
3262 pub mod RW {}
3263 }
3264 #[doc = "CHAIN3 IE"]
3265 pub mod IE3 {
3266 pub const offset: u32 = 29;
3267 pub const mask: u32 = 0x03 << offset;
3268 pub mod R {}
3269 pub mod W {}
3270 pub mod RW {}
3271 }
3272}
3273#[doc = "ETC_TRIG Chain 4/5 Register"]
3274pub mod TRIG6_CHAIN_5_4 {
3275 #[doc = "CHAIN4 CSEL"]
3276 pub mod CSEL4 {
3277 pub const offset: u32 = 0;
3278 pub const mask: u32 = 0x0f << offset;
3279 pub mod R {}
3280 pub mod W {}
3281 pub mod RW {}
3282 }
3283 #[doc = "CHAIN4 HWTS"]
3284 pub mod HWTS4 {
3285 pub const offset: u32 = 4;
3286 pub const mask: u32 = 0xff << offset;
3287 pub mod R {}
3288 pub mod W {}
3289 pub mod RW {}
3290 }
3291 #[doc = "CHAIN4 B2B"]
3292 pub mod B2B4 {
3293 pub const offset: u32 = 12;
3294 pub const mask: u32 = 0x01 << offset;
3295 pub mod R {}
3296 pub mod W {}
3297 pub mod RW {}
3298 }
3299 #[doc = "CHAIN4 IE"]
3300 pub mod IE4 {
3301 pub const offset: u32 = 13;
3302 pub const mask: u32 = 0x03 << offset;
3303 pub mod R {}
3304 pub mod W {}
3305 pub mod RW {}
3306 }
3307 #[doc = "CHAIN5 CSEL"]
3308 pub mod CSEL5 {
3309 pub const offset: u32 = 16;
3310 pub const mask: u32 = 0x0f << offset;
3311 pub mod R {}
3312 pub mod W {}
3313 pub mod RW {}
3314 }
3315 #[doc = "CHAIN5 HWTS"]
3316 pub mod HWTS5 {
3317 pub const offset: u32 = 20;
3318 pub const mask: u32 = 0xff << offset;
3319 pub mod R {}
3320 pub mod W {}
3321 pub mod RW {}
3322 }
3323 #[doc = "CHAIN5 B2B"]
3324 pub mod B2B5 {
3325 pub const offset: u32 = 28;
3326 pub const mask: u32 = 0x01 << offset;
3327 pub mod R {}
3328 pub mod W {}
3329 pub mod RW {}
3330 }
3331 #[doc = "CHAIN5 IE"]
3332 pub mod IE5 {
3333 pub const offset: u32 = 29;
3334 pub const mask: u32 = 0x03 << offset;
3335 pub mod R {}
3336 pub mod W {}
3337 pub mod RW {}
3338 }
3339}
3340#[doc = "ETC_TRIG Chain 6/7 Register"]
3341pub mod TRIG6_CHAIN_7_6 {
3342 #[doc = "CHAIN6 CSEL"]
3343 pub mod CSEL6 {
3344 pub const offset: u32 = 0;
3345 pub const mask: u32 = 0x0f << offset;
3346 pub mod R {}
3347 pub mod W {}
3348 pub mod RW {}
3349 }
3350 #[doc = "CHAIN6 HWTS"]
3351 pub mod HWTS6 {
3352 pub const offset: u32 = 4;
3353 pub const mask: u32 = 0xff << offset;
3354 pub mod R {}
3355 pub mod W {}
3356 pub mod RW {}
3357 }
3358 #[doc = "CHAIN6 B2B"]
3359 pub mod B2B6 {
3360 pub const offset: u32 = 12;
3361 pub const mask: u32 = 0x01 << offset;
3362 pub mod R {}
3363 pub mod W {}
3364 pub mod RW {}
3365 }
3366 #[doc = "CHAIN6 IE"]
3367 pub mod IE6 {
3368 pub const offset: u32 = 13;
3369 pub const mask: u32 = 0x03 << offset;
3370 pub mod R {}
3371 pub mod W {}
3372 pub mod RW {}
3373 }
3374 #[doc = "CHAIN7 CSEL"]
3375 pub mod CSEL7 {
3376 pub const offset: u32 = 16;
3377 pub const mask: u32 = 0x0f << offset;
3378 pub mod R {}
3379 pub mod W {}
3380 pub mod RW {}
3381 }
3382 #[doc = "CHAIN7 HWTS"]
3383 pub mod HWTS7 {
3384 pub const offset: u32 = 20;
3385 pub const mask: u32 = 0xff << offset;
3386 pub mod R {}
3387 pub mod W {}
3388 pub mod RW {}
3389 }
3390 #[doc = "CHAIN7 B2B"]
3391 pub mod B2B7 {
3392 pub const offset: u32 = 28;
3393 pub const mask: u32 = 0x01 << offset;
3394 pub mod R {}
3395 pub mod W {}
3396 pub mod RW {}
3397 }
3398 #[doc = "CHAIN7 IE"]
3399 pub mod IE7 {
3400 pub const offset: u32 = 29;
3401 pub const mask: u32 = 0x03 << offset;
3402 pub mod R {}
3403 pub mod W {}
3404 pub mod RW {}
3405 }
3406}
3407#[doc = "ETC_TRIG Result Data 1/0 Register"]
3408pub mod TRIG6_RESULT_1_0 {
3409 #[doc = "Result DATA0"]
3410 pub mod DATA0 {
3411 pub const offset: u32 = 0;
3412 pub const mask: u32 = 0x0fff << offset;
3413 pub mod R {}
3414 pub mod W {}
3415 pub mod RW {}
3416 }
3417 #[doc = "Result DATA1"]
3418 pub mod DATA1 {
3419 pub const offset: u32 = 16;
3420 pub const mask: u32 = 0x0fff << offset;
3421 pub mod R {}
3422 pub mod W {}
3423 pub mod RW {}
3424 }
3425}
3426#[doc = "ETC_TRIG Result Data 3/2 Register"]
3427pub mod TRIG6_RESULT_3_2 {
3428 #[doc = "Result DATA2"]
3429 pub mod DATA2 {
3430 pub const offset: u32 = 0;
3431 pub const mask: u32 = 0x0fff << offset;
3432 pub mod R {}
3433 pub mod W {}
3434 pub mod RW {}
3435 }
3436 #[doc = "Result DATA3"]
3437 pub mod DATA3 {
3438 pub const offset: u32 = 16;
3439 pub const mask: u32 = 0x0fff << offset;
3440 pub mod R {}
3441 pub mod W {}
3442 pub mod RW {}
3443 }
3444}
3445#[doc = "ETC_TRIG Result Data 5/4 Register"]
3446pub mod TRIG6_RESULT_5_4 {
3447 #[doc = "Result DATA4"]
3448 pub mod DATA4 {
3449 pub const offset: u32 = 0;
3450 pub const mask: u32 = 0x0fff << offset;
3451 pub mod R {}
3452 pub mod W {}
3453 pub mod RW {}
3454 }
3455 #[doc = "Result DATA5"]
3456 pub mod DATA5 {
3457 pub const offset: u32 = 16;
3458 pub const mask: u32 = 0x0fff << offset;
3459 pub mod R {}
3460 pub mod W {}
3461 pub mod RW {}
3462 }
3463}
3464#[doc = "ETC_TRIG Result Data 7/6 Register"]
3465pub mod TRIG6_RESULT_7_6 {
3466 #[doc = "Result DATA6"]
3467 pub mod DATA6 {
3468 pub const offset: u32 = 0;
3469 pub const mask: u32 = 0x0fff << offset;
3470 pub mod R {}
3471 pub mod W {}
3472 pub mod RW {}
3473 }
3474 #[doc = "Result DATA7"]
3475 pub mod DATA7 {
3476 pub const offset: u32 = 16;
3477 pub const mask: u32 = 0x0fff << offset;
3478 pub mod R {}
3479 pub mod W {}
3480 pub mod RW {}
3481 }
3482}
3483#[doc = "ETC_TRIG7 Control Register"]
3484pub mod TRIG7_CTRL {
3485 #[doc = "Software write 1 as the TRIGGER. This register is self-clearing."]
3486 pub mod SW_TRIG {
3487 pub const offset: u32 = 0;
3488 pub const mask: u32 = 0x01 << offset;
3489 pub mod R {}
3490 pub mod W {}
3491 pub mod RW {}
3492 }
3493 #[doc = "TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger."]
3494 pub mod TRIG_MODE {
3495 pub const offset: u32 = 4;
3496 pub const mask: u32 = 0x01 << offset;
3497 pub mod R {}
3498 pub mod W {}
3499 pub mod RW {}
3500 }
3501 #[doc = "TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;"]
3502 pub mod TRIG_CHAIN {
3503 pub const offset: u32 = 8;
3504 pub const mask: u32 = 0x07 << offset;
3505 pub mod R {}
3506 pub mod W {}
3507 pub mod RW {}
3508 }
3509 #[doc = "External trigger priority, 7 is highest, 0 is lowest ."]
3510 pub mod TRIG_PRIORITY {
3511 pub const offset: u32 = 12;
3512 pub const mask: u32 = 0x07 << offset;
3513 pub mod R {}
3514 pub mod W {}
3515 pub mod RW {}
3516 }
3517 #[doc = "TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode"]
3518 pub mod SYNC_MODE {
3519 pub const offset: u32 = 16;
3520 pub const mask: u32 = 0x01 << offset;
3521 pub mod R {}
3522 pub mod W {}
3523 pub mod RW {}
3524 }
3525}
3526#[doc = "ETC_TRIG7 Counter Register"]
3527pub mod TRIG7_COUNTER {
3528 #[doc = "TRIGGER initial delay counter"]
3529 pub mod INIT_DELAY {
3530 pub const offset: u32 = 0;
3531 pub const mask: u32 = 0xffff << offset;
3532 pub mod R {}
3533 pub mod W {}
3534 pub mod RW {}
3535 }
3536 #[doc = "TRIGGER sampling interval counter"]
3537 pub mod SAMPLE_INTERVAL {
3538 pub const offset: u32 = 16;
3539 pub const mask: u32 = 0xffff << offset;
3540 pub mod R {}
3541 pub mod W {}
3542 pub mod RW {}
3543 }
3544}
3545#[doc = "ETC_TRIG Chain 0/1 Register"]
3546pub mod TRIG7_CHAIN_1_0 {
3547 #[doc = "CHAIN0 CSEL ADC channel selection"]
3548 pub mod CSEL0 {
3549 pub const offset: u32 = 0;
3550 pub const mask: u32 = 0x0f << offset;
3551 pub mod R {}
3552 pub mod W {}
3553 pub mod RW {}
3554 }
3555 #[doc = "CHAIN0 HWTS ADC hardware trigger selection"]
3556 pub mod HWTS0 {
3557 pub const offset: u32 = 4;
3558 pub const mask: u32 = 0xff << offset;
3559 pub mod R {}
3560 pub mod W {}
3561 pub mod RW {}
3562 }
3563 #[doc = "CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger"]
3564 pub mod B2B0 {
3565 pub const offset: u32 = 12;
3566 pub const mask: u32 = 0x01 << offset;
3567 pub mod R {}
3568 pub mod W {}
3569 pub mod RW {}
3570 }
3571 #[doc = "CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2"]
3572 pub mod IE0 {
3573 pub const offset: u32 = 13;
3574 pub const mask: u32 = 0x03 << offset;
3575 pub mod R {}
3576 pub mod W {}
3577 pub mod RW {}
3578 }
3579 #[doc = "CHAIN1 CSEL ADC channel selection"]
3580 pub mod CSEL1 {
3581 pub const offset: u32 = 16;
3582 pub const mask: u32 = 0x0f << offset;
3583 pub mod R {}
3584 pub mod W {}
3585 pub mod RW {}
3586 }
3587 #[doc = "CHAIN1 HWTS ADC hardware trigger selection"]
3588 pub mod HWTS1 {
3589 pub const offset: u32 = 20;
3590 pub const mask: u32 = 0xff << offset;
3591 pub mod R {}
3592 pub mod W {}
3593 pub mod RW {}
3594 }
3595 #[doc = "CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger"]
3596 pub mod B2B1 {
3597 pub const offset: u32 = 28;
3598 pub const mask: u32 = 0x01 << offset;
3599 pub mod R {}
3600 pub mod W {}
3601 pub mod RW {}
3602 }
3603 #[doc = "CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2"]
3604 pub mod IE1 {
3605 pub const offset: u32 = 29;
3606 pub const mask: u32 = 0x03 << offset;
3607 pub mod R {}
3608 pub mod W {}
3609 pub mod RW {}
3610 }
3611}
3612#[doc = "ETC_TRIG Chain 2/3 Register"]
3613pub mod TRIG7_CHAIN_3_2 {
3614 #[doc = "CHAIN2 CSEL"]
3615 pub mod CSEL2 {
3616 pub const offset: u32 = 0;
3617 pub const mask: u32 = 0x0f << offset;
3618 pub mod R {}
3619 pub mod W {}
3620 pub mod RW {}
3621 }
3622 #[doc = "CHAIN2 HWTS"]
3623 pub mod HWTS2 {
3624 pub const offset: u32 = 4;
3625 pub const mask: u32 = 0xff << offset;
3626 pub mod R {}
3627 pub mod W {}
3628 pub mod RW {}
3629 }
3630 #[doc = "CHAIN2 B2B"]
3631 pub mod B2B2 {
3632 pub const offset: u32 = 12;
3633 pub const mask: u32 = 0x01 << offset;
3634 pub mod R {}
3635 pub mod W {}
3636 pub mod RW {}
3637 }
3638 #[doc = "CHAIN2 IE"]
3639 pub mod IE2 {
3640 pub const offset: u32 = 13;
3641 pub const mask: u32 = 0x03 << offset;
3642 pub mod R {}
3643 pub mod W {}
3644 pub mod RW {}
3645 }
3646 #[doc = "CHAIN3 CSEL"]
3647 pub mod CSEL3 {
3648 pub const offset: u32 = 16;
3649 pub const mask: u32 = 0x0f << offset;
3650 pub mod R {}
3651 pub mod W {}
3652 pub mod RW {}
3653 }
3654 #[doc = "CHAIN3 HWTS"]
3655 pub mod HWTS3 {
3656 pub const offset: u32 = 20;
3657 pub const mask: u32 = 0xff << offset;
3658 pub mod R {}
3659 pub mod W {}
3660 pub mod RW {}
3661 }
3662 #[doc = "CHAIN3 B2B"]
3663 pub mod B2B3 {
3664 pub const offset: u32 = 28;
3665 pub const mask: u32 = 0x01 << offset;
3666 pub mod R {}
3667 pub mod W {}
3668 pub mod RW {}
3669 }
3670 #[doc = "CHAIN3 IE"]
3671 pub mod IE3 {
3672 pub const offset: u32 = 29;
3673 pub const mask: u32 = 0x03 << offset;
3674 pub mod R {}
3675 pub mod W {}
3676 pub mod RW {}
3677 }
3678}
3679#[doc = "ETC_TRIG Chain 4/5 Register"]
3680pub mod TRIG7_CHAIN_5_4 {
3681 #[doc = "CHAIN4 CSEL"]
3682 pub mod CSEL4 {
3683 pub const offset: u32 = 0;
3684 pub const mask: u32 = 0x0f << offset;
3685 pub mod R {}
3686 pub mod W {}
3687 pub mod RW {}
3688 }
3689 #[doc = "CHAIN4 HWTS"]
3690 pub mod HWTS4 {
3691 pub const offset: u32 = 4;
3692 pub const mask: u32 = 0xff << offset;
3693 pub mod R {}
3694 pub mod W {}
3695 pub mod RW {}
3696 }
3697 #[doc = "CHAIN4 B2B"]
3698 pub mod B2B4 {
3699 pub const offset: u32 = 12;
3700 pub const mask: u32 = 0x01 << offset;
3701 pub mod R {}
3702 pub mod W {}
3703 pub mod RW {}
3704 }
3705 #[doc = "CHAIN4 IE"]
3706 pub mod IE4 {
3707 pub const offset: u32 = 13;
3708 pub const mask: u32 = 0x03 << offset;
3709 pub mod R {}
3710 pub mod W {}
3711 pub mod RW {}
3712 }
3713 #[doc = "CHAIN5 CSEL"]
3714 pub mod CSEL5 {
3715 pub const offset: u32 = 16;
3716 pub const mask: u32 = 0x0f << offset;
3717 pub mod R {}
3718 pub mod W {}
3719 pub mod RW {}
3720 }
3721 #[doc = "CHAIN5 HWTS"]
3722 pub mod HWTS5 {
3723 pub const offset: u32 = 20;
3724 pub const mask: u32 = 0xff << offset;
3725 pub mod R {}
3726 pub mod W {}
3727 pub mod RW {}
3728 }
3729 #[doc = "CHAIN5 B2B"]
3730 pub mod B2B5 {
3731 pub const offset: u32 = 28;
3732 pub const mask: u32 = 0x01 << offset;
3733 pub mod R {}
3734 pub mod W {}
3735 pub mod RW {}
3736 }
3737 #[doc = "CHAIN5 IE"]
3738 pub mod IE5 {
3739 pub const offset: u32 = 29;
3740 pub const mask: u32 = 0x03 << offset;
3741 pub mod R {}
3742 pub mod W {}
3743 pub mod RW {}
3744 }
3745}
3746#[doc = "ETC_TRIG Chain 6/7 Register"]
3747pub mod TRIG7_CHAIN_7_6 {
3748 #[doc = "CHAIN6 CSEL"]
3749 pub mod CSEL6 {
3750 pub const offset: u32 = 0;
3751 pub const mask: u32 = 0x0f << offset;
3752 pub mod R {}
3753 pub mod W {}
3754 pub mod RW {}
3755 }
3756 #[doc = "CHAIN6 HWTS"]
3757 pub mod HWTS6 {
3758 pub const offset: u32 = 4;
3759 pub const mask: u32 = 0xff << offset;
3760 pub mod R {}
3761 pub mod W {}
3762 pub mod RW {}
3763 }
3764 #[doc = "CHAIN6 B2B"]
3765 pub mod B2B6 {
3766 pub const offset: u32 = 12;
3767 pub const mask: u32 = 0x01 << offset;
3768 pub mod R {}
3769 pub mod W {}
3770 pub mod RW {}
3771 }
3772 #[doc = "CHAIN6 IE"]
3773 pub mod IE6 {
3774 pub const offset: u32 = 13;
3775 pub const mask: u32 = 0x03 << offset;
3776 pub mod R {}
3777 pub mod W {}
3778 pub mod RW {}
3779 }
3780 #[doc = "CHAIN7 CSEL"]
3781 pub mod CSEL7 {
3782 pub const offset: u32 = 16;
3783 pub const mask: u32 = 0x0f << offset;
3784 pub mod R {}
3785 pub mod W {}
3786 pub mod RW {}
3787 }
3788 #[doc = "CHAIN7 HWTS"]
3789 pub mod HWTS7 {
3790 pub const offset: u32 = 20;
3791 pub const mask: u32 = 0xff << offset;
3792 pub mod R {}
3793 pub mod W {}
3794 pub mod RW {}
3795 }
3796 #[doc = "CHAIN7 B2B"]
3797 pub mod B2B7 {
3798 pub const offset: u32 = 28;
3799 pub const mask: u32 = 0x01 << offset;
3800 pub mod R {}
3801 pub mod W {}
3802 pub mod RW {}
3803 }
3804 #[doc = "CHAIN7 IE"]
3805 pub mod IE7 {
3806 pub const offset: u32 = 29;
3807 pub const mask: u32 = 0x03 << offset;
3808 pub mod R {}
3809 pub mod W {}
3810 pub mod RW {}
3811 }
3812}
3813#[doc = "ETC_TRIG Result Data 1/0 Register"]
3814pub mod TRIG7_RESULT_1_0 {
3815 #[doc = "Result DATA0"]
3816 pub mod DATA0 {
3817 pub const offset: u32 = 0;
3818 pub const mask: u32 = 0x0fff << offset;
3819 pub mod R {}
3820 pub mod W {}
3821 pub mod RW {}
3822 }
3823 #[doc = "Result DATA1"]
3824 pub mod DATA1 {
3825 pub const offset: u32 = 16;
3826 pub const mask: u32 = 0x0fff << offset;
3827 pub mod R {}
3828 pub mod W {}
3829 pub mod RW {}
3830 }
3831}
3832#[doc = "ETC_TRIG Result Data 3/2 Register"]
3833pub mod TRIG7_RESULT_3_2 {
3834 #[doc = "Result DATA2"]
3835 pub mod DATA2 {
3836 pub const offset: u32 = 0;
3837 pub const mask: u32 = 0x0fff << offset;
3838 pub mod R {}
3839 pub mod W {}
3840 pub mod RW {}
3841 }
3842 #[doc = "Result DATA3"]
3843 pub mod DATA3 {
3844 pub const offset: u32 = 16;
3845 pub const mask: u32 = 0x0fff << offset;
3846 pub mod R {}
3847 pub mod W {}
3848 pub mod RW {}
3849 }
3850}
3851#[doc = "ETC_TRIG Result Data 5/4 Register"]
3852pub mod TRIG7_RESULT_5_4 {
3853 #[doc = "Result DATA4"]
3854 pub mod DATA4 {
3855 pub const offset: u32 = 0;
3856 pub const mask: u32 = 0x0fff << offset;
3857 pub mod R {}
3858 pub mod W {}
3859 pub mod RW {}
3860 }
3861 #[doc = "Result DATA5"]
3862 pub mod DATA5 {
3863 pub const offset: u32 = 16;
3864 pub const mask: u32 = 0x0fff << offset;
3865 pub mod R {}
3866 pub mod W {}
3867 pub mod RW {}
3868 }
3869}
3870#[doc = "ETC_TRIG Result Data 7/6 Register"]
3871pub mod TRIG7_RESULT_7_6 {
3872 #[doc = "Result DATA6"]
3873 pub mod DATA6 {
3874 pub const offset: u32 = 0;
3875 pub const mask: u32 = 0x0fff << offset;
3876 pub mod R {}
3877 pub mod W {}
3878 pub mod RW {}
3879 }
3880 #[doc = "Result DATA7"]
3881 pub mod DATA7 {
3882 pub const offset: u32 = 16;
3883 pub const mask: u32 = 0x0fff << offset;
3884 pub mod R {}
3885 pub mod W {}
3886 pub mod RW {}
3887 }
3888}