imxrt_ral/blocks/imxrt1051/
pmu.rs1#[doc = "PMU"]
2#[repr(C)]
3pub struct RegisterBlock {
4 _reserved0: [u8; 0x0110],
5 #[doc = "Regulator 1P1 Register"]
6 pub REG_1P1: crate::RWRegister<u32>,
7 #[doc = "Regulator 1P1 Register"]
8 pub REG_1P1_SET: crate::RWRegister<u32>,
9 #[doc = "Regulator 1P1 Register"]
10 pub REG_1P1_CLR: crate::RWRegister<u32>,
11 #[doc = "Regulator 1P1 Register"]
12 pub REG_1P1_TOG: crate::RWRegister<u32>,
13 #[doc = "Regulator 3P0 Register"]
14 pub REG_3P0: crate::RWRegister<u32>,
15 #[doc = "Regulator 3P0 Register"]
16 pub REG_3P0_SET: crate::RWRegister<u32>,
17 #[doc = "Regulator 3P0 Register"]
18 pub REG_3P0_CLR: crate::RWRegister<u32>,
19 #[doc = "Regulator 3P0 Register"]
20 pub REG_3P0_TOG: crate::RWRegister<u32>,
21 #[doc = "Regulator 2P5 Register"]
22 pub REG_2P5: crate::RWRegister<u32>,
23 #[doc = "Regulator 2P5 Register"]
24 pub REG_2P5_SET: crate::RWRegister<u32>,
25 #[doc = "Regulator 2P5 Register"]
26 pub REG_2P5_CLR: crate::RWRegister<u32>,
27 #[doc = "Regulator 2P5 Register"]
28 pub REG_2P5_TOG: crate::RWRegister<u32>,
29 #[doc = "Digital Regulator Core Register"]
30 pub REG_CORE: crate::RWRegister<u32>,
31 #[doc = "Digital Regulator Core Register"]
32 pub REG_CORE_SET: crate::RWRegister<u32>,
33 #[doc = "Digital Regulator Core Register"]
34 pub REG_CORE_CLR: crate::RWRegister<u32>,
35 #[doc = "Digital Regulator Core Register"]
36 pub REG_CORE_TOG: crate::RWRegister<u32>,
37 #[doc = "Miscellaneous Register 0"]
38 pub MISC0: crate::RWRegister<u32>,
39 #[doc = "Miscellaneous Register 0"]
40 pub MISC0_SET: crate::RWRegister<u32>,
41 #[doc = "Miscellaneous Register 0"]
42 pub MISC0_CLR: crate::RWRegister<u32>,
43 #[doc = "Miscellaneous Register 0"]
44 pub MISC0_TOG: crate::RWRegister<u32>,
45 #[doc = "Miscellaneous Register 1"]
46 pub MISC1: crate::RWRegister<u32>,
47 #[doc = "Miscellaneous Register 1"]
48 pub MISC1_SET: crate::RWRegister<u32>,
49 #[doc = "Miscellaneous Register 1"]
50 pub MISC1_CLR: crate::RWRegister<u32>,
51 #[doc = "Miscellaneous Register 1"]
52 pub MISC1_TOG: crate::RWRegister<u32>,
53 #[doc = "Miscellaneous Control Register"]
54 pub MISC2: crate::RWRegister<u32>,
55 #[doc = "Miscellaneous Control Register"]
56 pub MISC2_SET: crate::RWRegister<u32>,
57 #[doc = "Miscellaneous Control Register"]
58 pub MISC2_CLR: crate::RWRegister<u32>,
59 #[doc = "Miscellaneous Control Register"]
60 pub MISC2_TOG: crate::RWRegister<u32>,
61}
62#[doc = "Regulator 1P1 Register"]
63pub mod REG_1P1 {
64 #[doc = "Control bit to enable the regulator output."]
65 pub mod ENABLE_LINREG {
66 pub const offset: u32 = 0;
67 pub const mask: u32 = 0x01 << offset;
68 pub mod R {}
69 pub mod W {}
70 pub mod RW {}
71 }
72 #[doc = "Control bit to enable the brownout circuitry in the regulator."]
73 pub mod ENABLE_BO {
74 pub const offset: u32 = 1;
75 pub const mask: u32 = 0x01 << offset;
76 pub mod R {}
77 pub mod W {}
78 pub mod RW {}
79 }
80 #[doc = "Control bit to enable the current-limit circuitry in the regulator."]
81 pub mod ENABLE_ILIMIT {
82 pub const offset: u32 = 2;
83 pub const mask: u32 = 0x01 << offset;
84 pub mod R {}
85 pub mod W {}
86 pub mod RW {}
87 }
88 #[doc = "Control bit to enable the pull-down circuitry in the regulator"]
89 pub mod ENABLE_PULLDOWN {
90 pub const offset: u32 = 3;
91 pub const mask: u32 = 0x01 << offset;
92 pub mod R {}
93 pub mod W {}
94 pub mod RW {}
95 }
96 #[doc = "Control bits to adjust the regulator brownout offset voltage in 25mV steps"]
97 pub mod BO_OFFSET {
98 pub const offset: u32 = 4;
99 pub const mask: u32 = 0x07 << offset;
100 pub mod R {}
101 pub mod W {}
102 pub mod RW {}
103 }
104 #[doc = "Control bits to adjust the regulator output voltage"]
105 pub mod OUTPUT_TRG {
106 pub const offset: u32 = 8;
107 pub const mask: u32 = 0x1f << offset;
108 pub mod R {}
109 pub mod W {}
110 pub mod RW {
111 #[doc = "0.8V"]
112 pub const OUTPUT_TRG_4: u32 = 0x04;
113 #[doc = "1.1V"]
114 pub const OUTPUT_TRG_16: u32 = 0x10;
115 }
116 }
117 #[doc = "Status bit that signals when a brownout is detected on the regulator output."]
118 pub mod BO_VDD1P1 {
119 pub const offset: u32 = 16;
120 pub const mask: u32 = 0x01 << offset;
121 pub mod R {}
122 pub mod W {}
123 pub mod RW {}
124 }
125 #[doc = "Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target"]
126 pub mod OK_VDD1P1 {
127 pub const offset: u32 = 17;
128 pub const mask: u32 = 0x01 << offset;
129 pub mod R {}
130 pub mod W {}
131 pub mod RW {}
132 }
133 #[doc = "Enables the weak 1p1 regulator"]
134 pub mod ENABLE_WEAK_LINREG {
135 pub const offset: u32 = 18;
136 pub const mask: u32 = 0x01 << offset;
137 pub mod R {}
138 pub mod W {}
139 pub mod RW {}
140 }
141 #[doc = "Selects the source for the reference voltage of the weak 1p1 regulator."]
142 pub mod SELREF_WEAK_LINREG {
143 pub const offset: u32 = 19;
144 pub const mask: u32 = 0x01 << offset;
145 pub mod R {}
146 pub mod W {}
147 pub mod RW {
148 #[doc = "Weak-linreg output tracks low-power-bandgap voltage"]
149 pub const SELREF_WEAK_LINREG_0: u32 = 0;
150 #[doc = "Weak-linreg output tracks VDD_SOC_IN voltage"]
151 pub const SELREF_WEAK_LINREG_1: u32 = 0x01;
152 }
153 }
154}
155#[doc = "Regulator 1P1 Register"]
156pub mod REG_1P1_SET {
157 #[doc = "Control bit to enable the regulator output."]
158 pub mod ENABLE_LINREG {
159 pub const offset: u32 = 0;
160 pub const mask: u32 = 0x01 << offset;
161 pub mod R {}
162 pub mod W {}
163 pub mod RW {}
164 }
165 #[doc = "Control bit to enable the brownout circuitry in the regulator."]
166 pub mod ENABLE_BO {
167 pub const offset: u32 = 1;
168 pub const mask: u32 = 0x01 << offset;
169 pub mod R {}
170 pub mod W {}
171 pub mod RW {}
172 }
173 #[doc = "Control bit to enable the current-limit circuitry in the regulator."]
174 pub mod ENABLE_ILIMIT {
175 pub const offset: u32 = 2;
176 pub const mask: u32 = 0x01 << offset;
177 pub mod R {}
178 pub mod W {}
179 pub mod RW {}
180 }
181 #[doc = "Control bit to enable the pull-down circuitry in the regulator"]
182 pub mod ENABLE_PULLDOWN {
183 pub const offset: u32 = 3;
184 pub const mask: u32 = 0x01 << offset;
185 pub mod R {}
186 pub mod W {}
187 pub mod RW {}
188 }
189 #[doc = "Control bits to adjust the regulator brownout offset voltage in 25mV steps"]
190 pub mod BO_OFFSET {
191 pub const offset: u32 = 4;
192 pub const mask: u32 = 0x07 << offset;
193 pub mod R {}
194 pub mod W {}
195 pub mod RW {}
196 }
197 #[doc = "Control bits to adjust the regulator output voltage"]
198 pub mod OUTPUT_TRG {
199 pub const offset: u32 = 8;
200 pub const mask: u32 = 0x1f << offset;
201 pub mod R {}
202 pub mod W {}
203 pub mod RW {
204 #[doc = "0.8V"]
205 pub const OUTPUT_TRG_4: u32 = 0x04;
206 #[doc = "1.1V"]
207 pub const OUTPUT_TRG_16: u32 = 0x10;
208 }
209 }
210 #[doc = "Status bit that signals when a brownout is detected on the regulator output."]
211 pub mod BO_VDD1P1 {
212 pub const offset: u32 = 16;
213 pub const mask: u32 = 0x01 << offset;
214 pub mod R {}
215 pub mod W {}
216 pub mod RW {}
217 }
218 #[doc = "Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target"]
219 pub mod OK_VDD1P1 {
220 pub const offset: u32 = 17;
221 pub const mask: u32 = 0x01 << offset;
222 pub mod R {}
223 pub mod W {}
224 pub mod RW {}
225 }
226 #[doc = "Enables the weak 1p1 regulator"]
227 pub mod ENABLE_WEAK_LINREG {
228 pub const offset: u32 = 18;
229 pub const mask: u32 = 0x01 << offset;
230 pub mod R {}
231 pub mod W {}
232 pub mod RW {}
233 }
234 #[doc = "Selects the source for the reference voltage of the weak 1p1 regulator."]
235 pub mod SELREF_WEAK_LINREG {
236 pub const offset: u32 = 19;
237 pub const mask: u32 = 0x01 << offset;
238 pub mod R {}
239 pub mod W {}
240 pub mod RW {
241 #[doc = "Weak-linreg output tracks low-power-bandgap voltage"]
242 pub const SELREF_WEAK_LINREG_0: u32 = 0;
243 #[doc = "Weak-linreg output tracks VDD_SOC_IN voltage"]
244 pub const SELREF_WEAK_LINREG_1: u32 = 0x01;
245 }
246 }
247}
248#[doc = "Regulator 1P1 Register"]
249pub mod REG_1P1_CLR {
250 #[doc = "Control bit to enable the regulator output."]
251 pub mod ENABLE_LINREG {
252 pub const offset: u32 = 0;
253 pub const mask: u32 = 0x01 << offset;
254 pub mod R {}
255 pub mod W {}
256 pub mod RW {}
257 }
258 #[doc = "Control bit to enable the brownout circuitry in the regulator."]
259 pub mod ENABLE_BO {
260 pub const offset: u32 = 1;
261 pub const mask: u32 = 0x01 << offset;
262 pub mod R {}
263 pub mod W {}
264 pub mod RW {}
265 }
266 #[doc = "Control bit to enable the current-limit circuitry in the regulator."]
267 pub mod ENABLE_ILIMIT {
268 pub const offset: u32 = 2;
269 pub const mask: u32 = 0x01 << offset;
270 pub mod R {}
271 pub mod W {}
272 pub mod RW {}
273 }
274 #[doc = "Control bit to enable the pull-down circuitry in the regulator"]
275 pub mod ENABLE_PULLDOWN {
276 pub const offset: u32 = 3;
277 pub const mask: u32 = 0x01 << offset;
278 pub mod R {}
279 pub mod W {}
280 pub mod RW {}
281 }
282 #[doc = "Control bits to adjust the regulator brownout offset voltage in 25mV steps"]
283 pub mod BO_OFFSET {
284 pub const offset: u32 = 4;
285 pub const mask: u32 = 0x07 << offset;
286 pub mod R {}
287 pub mod W {}
288 pub mod RW {}
289 }
290 #[doc = "Control bits to adjust the regulator output voltage"]
291 pub mod OUTPUT_TRG {
292 pub const offset: u32 = 8;
293 pub const mask: u32 = 0x1f << offset;
294 pub mod R {}
295 pub mod W {}
296 pub mod RW {
297 #[doc = "0.8V"]
298 pub const OUTPUT_TRG_4: u32 = 0x04;
299 #[doc = "1.1V"]
300 pub const OUTPUT_TRG_16: u32 = 0x10;
301 }
302 }
303 #[doc = "Status bit that signals when a brownout is detected on the regulator output."]
304 pub mod BO_VDD1P1 {
305 pub const offset: u32 = 16;
306 pub const mask: u32 = 0x01 << offset;
307 pub mod R {}
308 pub mod W {}
309 pub mod RW {}
310 }
311 #[doc = "Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target"]
312 pub mod OK_VDD1P1 {
313 pub const offset: u32 = 17;
314 pub const mask: u32 = 0x01 << offset;
315 pub mod R {}
316 pub mod W {}
317 pub mod RW {}
318 }
319 #[doc = "Enables the weak 1p1 regulator"]
320 pub mod ENABLE_WEAK_LINREG {
321 pub const offset: u32 = 18;
322 pub const mask: u32 = 0x01 << offset;
323 pub mod R {}
324 pub mod W {}
325 pub mod RW {}
326 }
327 #[doc = "Selects the source for the reference voltage of the weak 1p1 regulator."]
328 pub mod SELREF_WEAK_LINREG {
329 pub const offset: u32 = 19;
330 pub const mask: u32 = 0x01 << offset;
331 pub mod R {}
332 pub mod W {}
333 pub mod RW {
334 #[doc = "Weak-linreg output tracks low-power-bandgap voltage"]
335 pub const SELREF_WEAK_LINREG_0: u32 = 0;
336 #[doc = "Weak-linreg output tracks VDD_SOC_IN voltage"]
337 pub const SELREF_WEAK_LINREG_1: u32 = 0x01;
338 }
339 }
340}
341#[doc = "Regulator 1P1 Register"]
342pub mod REG_1P1_TOG {
343 #[doc = "Control bit to enable the regulator output."]
344 pub mod ENABLE_LINREG {
345 pub const offset: u32 = 0;
346 pub const mask: u32 = 0x01 << offset;
347 pub mod R {}
348 pub mod W {}
349 pub mod RW {}
350 }
351 #[doc = "Control bit to enable the brownout circuitry in the regulator."]
352 pub mod ENABLE_BO {
353 pub const offset: u32 = 1;
354 pub const mask: u32 = 0x01 << offset;
355 pub mod R {}
356 pub mod W {}
357 pub mod RW {}
358 }
359 #[doc = "Control bit to enable the current-limit circuitry in the regulator."]
360 pub mod ENABLE_ILIMIT {
361 pub const offset: u32 = 2;
362 pub const mask: u32 = 0x01 << offset;
363 pub mod R {}
364 pub mod W {}
365 pub mod RW {}
366 }
367 #[doc = "Control bit to enable the pull-down circuitry in the regulator"]
368 pub mod ENABLE_PULLDOWN {
369 pub const offset: u32 = 3;
370 pub const mask: u32 = 0x01 << offset;
371 pub mod R {}
372 pub mod W {}
373 pub mod RW {}
374 }
375 #[doc = "Control bits to adjust the regulator brownout offset voltage in 25mV steps"]
376 pub mod BO_OFFSET {
377 pub const offset: u32 = 4;
378 pub const mask: u32 = 0x07 << offset;
379 pub mod R {}
380 pub mod W {}
381 pub mod RW {}
382 }
383 #[doc = "Control bits to adjust the regulator output voltage"]
384 pub mod OUTPUT_TRG {
385 pub const offset: u32 = 8;
386 pub const mask: u32 = 0x1f << offset;
387 pub mod R {}
388 pub mod W {}
389 pub mod RW {
390 #[doc = "0.8V"]
391 pub const OUTPUT_TRG_4: u32 = 0x04;
392 #[doc = "1.1V"]
393 pub const OUTPUT_TRG_16: u32 = 0x10;
394 }
395 }
396 #[doc = "Status bit that signals when a brownout is detected on the regulator output."]
397 pub mod BO_VDD1P1 {
398 pub const offset: u32 = 16;
399 pub const mask: u32 = 0x01 << offset;
400 pub mod R {}
401 pub mod W {}
402 pub mod RW {}
403 }
404 #[doc = "Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target"]
405 pub mod OK_VDD1P1 {
406 pub const offset: u32 = 17;
407 pub const mask: u32 = 0x01 << offset;
408 pub mod R {}
409 pub mod W {}
410 pub mod RW {}
411 }
412 #[doc = "Enables the weak 1p1 regulator"]
413 pub mod ENABLE_WEAK_LINREG {
414 pub const offset: u32 = 18;
415 pub const mask: u32 = 0x01 << offset;
416 pub mod R {}
417 pub mod W {}
418 pub mod RW {}
419 }
420 #[doc = "Selects the source for the reference voltage of the weak 1p1 regulator."]
421 pub mod SELREF_WEAK_LINREG {
422 pub const offset: u32 = 19;
423 pub const mask: u32 = 0x01 << offset;
424 pub mod R {}
425 pub mod W {}
426 pub mod RW {
427 #[doc = "Weak-linreg output tracks low-power-bandgap voltage"]
428 pub const SELREF_WEAK_LINREG_0: u32 = 0;
429 #[doc = "Weak-linreg output tracks VDD_SOC_IN voltage"]
430 pub const SELREF_WEAK_LINREG_1: u32 = 0x01;
431 }
432 }
433}
434#[doc = "Regulator 3P0 Register"]
435pub mod REG_3P0 {
436 #[doc = "Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference"]
437 pub mod ENABLE_LINREG {
438 pub const offset: u32 = 0;
439 pub const mask: u32 = 0x01 << offset;
440 pub mod R {}
441 pub mod W {}
442 pub mod RW {}
443 }
444 #[doc = "Control bit to enable the brownout circuitry in the regulator."]
445 pub mod ENABLE_BO {
446 pub const offset: u32 = 1;
447 pub const mask: u32 = 0x01 << offset;
448 pub mod R {}
449 pub mod W {}
450 pub mod RW {}
451 }
452 #[doc = "Control bit to enable the current-limit circuitry in the regulator."]
453 pub mod ENABLE_ILIMIT {
454 pub const offset: u32 = 2;
455 pub const mask: u32 = 0x01 << offset;
456 pub mod R {}
457 pub mod W {}
458 pub mod RW {}
459 }
460 #[doc = "Control bits to adjust the regulator brownout offset voltage in 25mV steps"]
461 pub mod BO_OFFSET {
462 pub const offset: u32 = 4;
463 pub const mask: u32 = 0x07 << offset;
464 pub mod R {}
465 pub mod W {}
466 pub mod RW {}
467 }
468 #[doc = "Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS"]
469 pub mod VBUS_SEL {
470 pub const offset: u32 = 7;
471 pub const mask: u32 = 0x01 << offset;
472 pub mod R {}
473 pub mod W {}
474 pub mod RW {
475 #[doc = "Utilize VBUS OTG2 power"]
476 pub const USB_OTG2_VBUS: u32 = 0;
477 #[doc = "Utilize VBUS OTG1 power"]
478 pub const USB_OTG1_VBUS: u32 = 0x01;
479 }
480 }
481 #[doc = "Control bits to adjust the regulator output voltage"]
482 pub mod OUTPUT_TRG {
483 pub const offset: u32 = 8;
484 pub const mask: u32 = 0x1f << offset;
485 pub mod R {}
486 pub mod W {}
487 pub mod RW {
488 #[doc = "2.625V"]
489 pub const OUTPUT_TRG_0: u32 = 0;
490 #[doc = "3.000V"]
491 pub const OUTPUT_TRG_15: u32 = 0x0f;
492 #[doc = "3.400V"]
493 pub const OUTPUT_TRG_31: u32 = 0x1f;
494 }
495 }
496 #[doc = "Status bit that signals when a brownout is detected on the regulator output."]
497 pub mod BO_VDD3P0 {
498 pub const offset: u32 = 16;
499 pub const mask: u32 = 0x01 << offset;
500 pub mod R {}
501 pub mod W {}
502 pub mod RW {}
503 }
504 #[doc = "Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target"]
505 pub mod OK_VDD3P0 {
506 pub const offset: u32 = 17;
507 pub const mask: u32 = 0x01 << offset;
508 pub mod R {}
509 pub mod W {}
510 pub mod RW {}
511 }
512}
513#[doc = "Regulator 3P0 Register"]
514pub mod REG_3P0_SET {
515 #[doc = "Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference"]
516 pub mod ENABLE_LINREG {
517 pub const offset: u32 = 0;
518 pub const mask: u32 = 0x01 << offset;
519 pub mod R {}
520 pub mod W {}
521 pub mod RW {}
522 }
523 #[doc = "Control bit to enable the brownout circuitry in the regulator."]
524 pub mod ENABLE_BO {
525 pub const offset: u32 = 1;
526 pub const mask: u32 = 0x01 << offset;
527 pub mod R {}
528 pub mod W {}
529 pub mod RW {}
530 }
531 #[doc = "Control bit to enable the current-limit circuitry in the regulator."]
532 pub mod ENABLE_ILIMIT {
533 pub const offset: u32 = 2;
534 pub const mask: u32 = 0x01 << offset;
535 pub mod R {}
536 pub mod W {}
537 pub mod RW {}
538 }
539 #[doc = "Control bits to adjust the regulator brownout offset voltage in 25mV steps"]
540 pub mod BO_OFFSET {
541 pub const offset: u32 = 4;
542 pub const mask: u32 = 0x07 << offset;
543 pub mod R {}
544 pub mod W {}
545 pub mod RW {}
546 }
547 #[doc = "Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS"]
548 pub mod VBUS_SEL {
549 pub const offset: u32 = 7;
550 pub const mask: u32 = 0x01 << offset;
551 pub mod R {}
552 pub mod W {}
553 pub mod RW {
554 #[doc = "Utilize VBUS OTG2 power"]
555 pub const USB_OTG2_VBUS: u32 = 0;
556 #[doc = "Utilize VBUS OTG1 power"]
557 pub const USB_OTG1_VBUS: u32 = 0x01;
558 }
559 }
560 #[doc = "Control bits to adjust the regulator output voltage"]
561 pub mod OUTPUT_TRG {
562 pub const offset: u32 = 8;
563 pub const mask: u32 = 0x1f << offset;
564 pub mod R {}
565 pub mod W {}
566 pub mod RW {
567 #[doc = "2.625V"]
568 pub const OUTPUT_TRG_0: u32 = 0;
569 #[doc = "3.000V"]
570 pub const OUTPUT_TRG_15: u32 = 0x0f;
571 #[doc = "3.400V"]
572 pub const OUTPUT_TRG_31: u32 = 0x1f;
573 }
574 }
575 #[doc = "Status bit that signals when a brownout is detected on the regulator output."]
576 pub mod BO_VDD3P0 {
577 pub const offset: u32 = 16;
578 pub const mask: u32 = 0x01 << offset;
579 pub mod R {}
580 pub mod W {}
581 pub mod RW {}
582 }
583 #[doc = "Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target"]
584 pub mod OK_VDD3P0 {
585 pub const offset: u32 = 17;
586 pub const mask: u32 = 0x01 << offset;
587 pub mod R {}
588 pub mod W {}
589 pub mod RW {}
590 }
591}
592#[doc = "Regulator 3P0 Register"]
593pub mod REG_3P0_CLR {
594 #[doc = "Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference"]
595 pub mod ENABLE_LINREG {
596 pub const offset: u32 = 0;
597 pub const mask: u32 = 0x01 << offset;
598 pub mod R {}
599 pub mod W {}
600 pub mod RW {}
601 }
602 #[doc = "Control bit to enable the brownout circuitry in the regulator."]
603 pub mod ENABLE_BO {
604 pub const offset: u32 = 1;
605 pub const mask: u32 = 0x01 << offset;
606 pub mod R {}
607 pub mod W {}
608 pub mod RW {}
609 }
610 #[doc = "Control bit to enable the current-limit circuitry in the regulator."]
611 pub mod ENABLE_ILIMIT {
612 pub const offset: u32 = 2;
613 pub const mask: u32 = 0x01 << offset;
614 pub mod R {}
615 pub mod W {}
616 pub mod RW {}
617 }
618 #[doc = "Control bits to adjust the regulator brownout offset voltage in 25mV steps"]
619 pub mod BO_OFFSET {
620 pub const offset: u32 = 4;
621 pub const mask: u32 = 0x07 << offset;
622 pub mod R {}
623 pub mod W {}
624 pub mod RW {}
625 }
626 #[doc = "Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS"]
627 pub mod VBUS_SEL {
628 pub const offset: u32 = 7;
629 pub const mask: u32 = 0x01 << offset;
630 pub mod R {}
631 pub mod W {}
632 pub mod RW {
633 #[doc = "Utilize VBUS OTG2 power"]
634 pub const USB_OTG2_VBUS: u32 = 0;
635 #[doc = "Utilize VBUS OTG1 power"]
636 pub const USB_OTG1_VBUS: u32 = 0x01;
637 }
638 }
639 #[doc = "Control bits to adjust the regulator output voltage"]
640 pub mod OUTPUT_TRG {
641 pub const offset: u32 = 8;
642 pub const mask: u32 = 0x1f << offset;
643 pub mod R {}
644 pub mod W {}
645 pub mod RW {
646 #[doc = "2.625V"]
647 pub const OUTPUT_TRG_0: u32 = 0;
648 #[doc = "3.000V"]
649 pub const OUTPUT_TRG_15: u32 = 0x0f;
650 #[doc = "3.400V"]
651 pub const OUTPUT_TRG_31: u32 = 0x1f;
652 }
653 }
654 #[doc = "Status bit that signals when a brownout is detected on the regulator output."]
655 pub mod BO_VDD3P0 {
656 pub const offset: u32 = 16;
657 pub const mask: u32 = 0x01 << offset;
658 pub mod R {}
659 pub mod W {}
660 pub mod RW {}
661 }
662 #[doc = "Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target"]
663 pub mod OK_VDD3P0 {
664 pub const offset: u32 = 17;
665 pub const mask: u32 = 0x01 << offset;
666 pub mod R {}
667 pub mod W {}
668 pub mod RW {}
669 }
670}
671#[doc = "Regulator 3P0 Register"]
672pub mod REG_3P0_TOG {
673 #[doc = "Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference"]
674 pub mod ENABLE_LINREG {
675 pub const offset: u32 = 0;
676 pub const mask: u32 = 0x01 << offset;
677 pub mod R {}
678 pub mod W {}
679 pub mod RW {}
680 }
681 #[doc = "Control bit to enable the brownout circuitry in the regulator."]
682 pub mod ENABLE_BO {
683 pub const offset: u32 = 1;
684 pub const mask: u32 = 0x01 << offset;
685 pub mod R {}
686 pub mod W {}
687 pub mod RW {}
688 }
689 #[doc = "Control bit to enable the current-limit circuitry in the regulator."]
690 pub mod ENABLE_ILIMIT {
691 pub const offset: u32 = 2;
692 pub const mask: u32 = 0x01 << offset;
693 pub mod R {}
694 pub mod W {}
695 pub mod RW {}
696 }
697 #[doc = "Control bits to adjust the regulator brownout offset voltage in 25mV steps"]
698 pub mod BO_OFFSET {
699 pub const offset: u32 = 4;
700 pub const mask: u32 = 0x07 << offset;
701 pub mod R {}
702 pub mod W {}
703 pub mod RW {}
704 }
705 #[doc = "Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS"]
706 pub mod VBUS_SEL {
707 pub const offset: u32 = 7;
708 pub const mask: u32 = 0x01 << offset;
709 pub mod R {}
710 pub mod W {}
711 pub mod RW {
712 #[doc = "Utilize VBUS OTG2 power"]
713 pub const USB_OTG2_VBUS: u32 = 0;
714 #[doc = "Utilize VBUS OTG1 power"]
715 pub const USB_OTG1_VBUS: u32 = 0x01;
716 }
717 }
718 #[doc = "Control bits to adjust the regulator output voltage"]
719 pub mod OUTPUT_TRG {
720 pub const offset: u32 = 8;
721 pub const mask: u32 = 0x1f << offset;
722 pub mod R {}
723 pub mod W {}
724 pub mod RW {
725 #[doc = "2.625V"]
726 pub const OUTPUT_TRG_0: u32 = 0;
727 #[doc = "3.000V"]
728 pub const OUTPUT_TRG_15: u32 = 0x0f;
729 #[doc = "3.400V"]
730 pub const OUTPUT_TRG_31: u32 = 0x1f;
731 }
732 }
733 #[doc = "Status bit that signals when a brownout is detected on the regulator output."]
734 pub mod BO_VDD3P0 {
735 pub const offset: u32 = 16;
736 pub const mask: u32 = 0x01 << offset;
737 pub mod R {}
738 pub mod W {}
739 pub mod RW {}
740 }
741 #[doc = "Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target"]
742 pub mod OK_VDD3P0 {
743 pub const offset: u32 = 17;
744 pub const mask: u32 = 0x01 << offset;
745 pub mod R {}
746 pub mod W {}
747 pub mod RW {}
748 }
749}
750#[doc = "Regulator 2P5 Register"]
751pub mod REG_2P5 {
752 #[doc = "Control bit to enable the regulator output."]
753 pub mod ENABLE_LINREG {
754 pub const offset: u32 = 0;
755 pub const mask: u32 = 0x01 << offset;
756 pub mod R {}
757 pub mod W {}
758 pub mod RW {}
759 }
760 #[doc = "Control bit to enable the brownout circuitry in the regulator."]
761 pub mod ENABLE_BO {
762 pub const offset: u32 = 1;
763 pub const mask: u32 = 0x01 << offset;
764 pub mod R {}
765 pub mod W {}
766 pub mod RW {}
767 }
768 #[doc = "Control bit to enable the current-limit circuitry in the regulator."]
769 pub mod ENABLE_ILIMIT {
770 pub const offset: u32 = 2;
771 pub const mask: u32 = 0x01 << offset;
772 pub mod R {}
773 pub mod W {}
774 pub mod RW {}
775 }
776 #[doc = "Control bit to enable the pull-down circuitry in the regulator"]
777 pub mod ENABLE_PULLDOWN {
778 pub const offset: u32 = 3;
779 pub const mask: u32 = 0x01 << offset;
780 pub mod R {}
781 pub mod W {}
782 pub mod RW {}
783 }
784 #[doc = "Control bits to adjust the regulator brownout offset voltage in 25mV steps"]
785 pub mod BO_OFFSET {
786 pub const offset: u32 = 4;
787 pub const mask: u32 = 0x07 << offset;
788 pub mod R {}
789 pub mod W {}
790 pub mod RW {}
791 }
792 #[doc = "Control bits to adjust the regulator output voltage"]
793 pub mod OUTPUT_TRG {
794 pub const offset: u32 = 8;
795 pub const mask: u32 = 0x1f << offset;
796 pub mod R {}
797 pub mod W {}
798 pub mod RW {
799 #[doc = "2.10V"]
800 pub const OUTPUT_TRG_0: u32 = 0;
801 #[doc = "2.50V"]
802 pub const OUTPUT_TRG_16: u32 = 0x10;
803 #[doc = "2.875V"]
804 pub const OUTPUT_TRG_31: u32 = 0x1f;
805 }
806 }
807 #[doc = "Status bit that signals when a brownout is detected on the regulator output."]
808 pub mod BO_VDD2P5 {
809 pub const offset: u32 = 16;
810 pub const mask: u32 = 0x01 << offset;
811 pub mod R {}
812 pub mod W {}
813 pub mod RW {}
814 }
815 #[doc = "Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target"]
816 pub mod OK_VDD2P5 {
817 pub const offset: u32 = 17;
818 pub const mask: u32 = 0x01 << offset;
819 pub mod R {}
820 pub mod W {}
821 pub mod RW {}
822 }
823 #[doc = "Enables the weak 2p5 regulator"]
824 pub mod ENABLE_WEAK_LINREG {
825 pub const offset: u32 = 18;
826 pub const mask: u32 = 0x01 << offset;
827 pub mod R {}
828 pub mod W {}
829 pub mod RW {}
830 }
831}
832#[doc = "Regulator 2P5 Register"]
833pub mod REG_2P5_SET {
834 #[doc = "Control bit to enable the regulator output."]
835 pub mod ENABLE_LINREG {
836 pub const offset: u32 = 0;
837 pub const mask: u32 = 0x01 << offset;
838 pub mod R {}
839 pub mod W {}
840 pub mod RW {}
841 }
842 #[doc = "Control bit to enable the brownout circuitry in the regulator."]
843 pub mod ENABLE_BO {
844 pub const offset: u32 = 1;
845 pub const mask: u32 = 0x01 << offset;
846 pub mod R {}
847 pub mod W {}
848 pub mod RW {}
849 }
850 #[doc = "Control bit to enable the current-limit circuitry in the regulator."]
851 pub mod ENABLE_ILIMIT {
852 pub const offset: u32 = 2;
853 pub const mask: u32 = 0x01 << offset;
854 pub mod R {}
855 pub mod W {}
856 pub mod RW {}
857 }
858 #[doc = "Control bit to enable the pull-down circuitry in the regulator"]
859 pub mod ENABLE_PULLDOWN {
860 pub const offset: u32 = 3;
861 pub const mask: u32 = 0x01 << offset;
862 pub mod R {}
863 pub mod W {}
864 pub mod RW {}
865 }
866 #[doc = "Control bits to adjust the regulator brownout offset voltage in 25mV steps"]
867 pub mod BO_OFFSET {
868 pub const offset: u32 = 4;
869 pub const mask: u32 = 0x07 << offset;
870 pub mod R {}
871 pub mod W {}
872 pub mod RW {}
873 }
874 #[doc = "Control bits to adjust the regulator output voltage"]
875 pub mod OUTPUT_TRG {
876 pub const offset: u32 = 8;
877 pub const mask: u32 = 0x1f << offset;
878 pub mod R {}
879 pub mod W {}
880 pub mod RW {
881 #[doc = "2.10V"]
882 pub const OUTPUT_TRG_0: u32 = 0;
883 #[doc = "2.50V"]
884 pub const OUTPUT_TRG_16: u32 = 0x10;
885 #[doc = "2.875V"]
886 pub const OUTPUT_TRG_31: u32 = 0x1f;
887 }
888 }
889 #[doc = "Status bit that signals when a brownout is detected on the regulator output."]
890 pub mod BO_VDD2P5 {
891 pub const offset: u32 = 16;
892 pub const mask: u32 = 0x01 << offset;
893 pub mod R {}
894 pub mod W {}
895 pub mod RW {}
896 }
897 #[doc = "Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target"]
898 pub mod OK_VDD2P5 {
899 pub const offset: u32 = 17;
900 pub const mask: u32 = 0x01 << offset;
901 pub mod R {}
902 pub mod W {}
903 pub mod RW {}
904 }
905 #[doc = "Enables the weak 2p5 regulator"]
906 pub mod ENABLE_WEAK_LINREG {
907 pub const offset: u32 = 18;
908 pub const mask: u32 = 0x01 << offset;
909 pub mod R {}
910 pub mod W {}
911 pub mod RW {}
912 }
913}
914#[doc = "Regulator 2P5 Register"]
915pub mod REG_2P5_CLR {
916 #[doc = "Control bit to enable the regulator output."]
917 pub mod ENABLE_LINREG {
918 pub const offset: u32 = 0;
919 pub const mask: u32 = 0x01 << offset;
920 pub mod R {}
921 pub mod W {}
922 pub mod RW {}
923 }
924 #[doc = "Control bit to enable the brownout circuitry in the regulator."]
925 pub mod ENABLE_BO {
926 pub const offset: u32 = 1;
927 pub const mask: u32 = 0x01 << offset;
928 pub mod R {}
929 pub mod W {}
930 pub mod RW {}
931 }
932 #[doc = "Control bit to enable the current-limit circuitry in the regulator."]
933 pub mod ENABLE_ILIMIT {
934 pub const offset: u32 = 2;
935 pub const mask: u32 = 0x01 << offset;
936 pub mod R {}
937 pub mod W {}
938 pub mod RW {}
939 }
940 #[doc = "Control bit to enable the pull-down circuitry in the regulator"]
941 pub mod ENABLE_PULLDOWN {
942 pub const offset: u32 = 3;
943 pub const mask: u32 = 0x01 << offset;
944 pub mod R {}
945 pub mod W {}
946 pub mod RW {}
947 }
948 #[doc = "Control bits to adjust the regulator brownout offset voltage in 25mV steps"]
949 pub mod BO_OFFSET {
950 pub const offset: u32 = 4;
951 pub const mask: u32 = 0x07 << offset;
952 pub mod R {}
953 pub mod W {}
954 pub mod RW {}
955 }
956 #[doc = "Control bits to adjust the regulator output voltage"]
957 pub mod OUTPUT_TRG {
958 pub const offset: u32 = 8;
959 pub const mask: u32 = 0x1f << offset;
960 pub mod R {}
961 pub mod W {}
962 pub mod RW {
963 #[doc = "2.10V"]
964 pub const OUTPUT_TRG_0: u32 = 0;
965 #[doc = "2.50V"]
966 pub const OUTPUT_TRG_16: u32 = 0x10;
967 #[doc = "2.875V"]
968 pub const OUTPUT_TRG_31: u32 = 0x1f;
969 }
970 }
971 #[doc = "Status bit that signals when a brownout is detected on the regulator output."]
972 pub mod BO_VDD2P5 {
973 pub const offset: u32 = 16;
974 pub const mask: u32 = 0x01 << offset;
975 pub mod R {}
976 pub mod W {}
977 pub mod RW {}
978 }
979 #[doc = "Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target"]
980 pub mod OK_VDD2P5 {
981 pub const offset: u32 = 17;
982 pub const mask: u32 = 0x01 << offset;
983 pub mod R {}
984 pub mod W {}
985 pub mod RW {}
986 }
987 #[doc = "Enables the weak 2p5 regulator"]
988 pub mod ENABLE_WEAK_LINREG {
989 pub const offset: u32 = 18;
990 pub const mask: u32 = 0x01 << offset;
991 pub mod R {}
992 pub mod W {}
993 pub mod RW {}
994 }
995}
996#[doc = "Regulator 2P5 Register"]
997pub mod REG_2P5_TOG {
998 #[doc = "Control bit to enable the regulator output."]
999 pub mod ENABLE_LINREG {
1000 pub const offset: u32 = 0;
1001 pub const mask: u32 = 0x01 << offset;
1002 pub mod R {}
1003 pub mod W {}
1004 pub mod RW {}
1005 }
1006 #[doc = "Control bit to enable the brownout circuitry in the regulator."]
1007 pub mod ENABLE_BO {
1008 pub const offset: u32 = 1;
1009 pub const mask: u32 = 0x01 << offset;
1010 pub mod R {}
1011 pub mod W {}
1012 pub mod RW {}
1013 }
1014 #[doc = "Control bit to enable the current-limit circuitry in the regulator."]
1015 pub mod ENABLE_ILIMIT {
1016 pub const offset: u32 = 2;
1017 pub const mask: u32 = 0x01 << offset;
1018 pub mod R {}
1019 pub mod W {}
1020 pub mod RW {}
1021 }
1022 #[doc = "Control bit to enable the pull-down circuitry in the regulator"]
1023 pub mod ENABLE_PULLDOWN {
1024 pub const offset: u32 = 3;
1025 pub const mask: u32 = 0x01 << offset;
1026 pub mod R {}
1027 pub mod W {}
1028 pub mod RW {}
1029 }
1030 #[doc = "Control bits to adjust the regulator brownout offset voltage in 25mV steps"]
1031 pub mod BO_OFFSET {
1032 pub const offset: u32 = 4;
1033 pub const mask: u32 = 0x07 << offset;
1034 pub mod R {}
1035 pub mod W {}
1036 pub mod RW {}
1037 }
1038 #[doc = "Control bits to adjust the regulator output voltage"]
1039 pub mod OUTPUT_TRG {
1040 pub const offset: u32 = 8;
1041 pub const mask: u32 = 0x1f << offset;
1042 pub mod R {}
1043 pub mod W {}
1044 pub mod RW {
1045 #[doc = "2.10V"]
1046 pub const OUTPUT_TRG_0: u32 = 0;
1047 #[doc = "2.50V"]
1048 pub const OUTPUT_TRG_16: u32 = 0x10;
1049 #[doc = "2.875V"]
1050 pub const OUTPUT_TRG_31: u32 = 0x1f;
1051 }
1052 }
1053 #[doc = "Status bit that signals when a brownout is detected on the regulator output."]
1054 pub mod BO_VDD2P5 {
1055 pub const offset: u32 = 16;
1056 pub const mask: u32 = 0x01 << offset;
1057 pub mod R {}
1058 pub mod W {}
1059 pub mod RW {}
1060 }
1061 #[doc = "Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target"]
1062 pub mod OK_VDD2P5 {
1063 pub const offset: u32 = 17;
1064 pub const mask: u32 = 0x01 << offset;
1065 pub mod R {}
1066 pub mod W {}
1067 pub mod RW {}
1068 }
1069 #[doc = "Enables the weak 2p5 regulator"]
1070 pub mod ENABLE_WEAK_LINREG {
1071 pub const offset: u32 = 18;
1072 pub const mask: u32 = 0x01 << offset;
1073 pub mod R {}
1074 pub mod W {}
1075 pub mod RW {}
1076 }
1077}
1078#[doc = "Digital Regulator Core Register"]
1079pub mod REG_CORE {
1080 #[doc = "This field defines the target voltage for the ARM core power domain"]
1081 pub mod REG0_TARG {
1082 pub const offset: u32 = 0;
1083 pub const mask: u32 = 0x1f << offset;
1084 pub mod R {}
1085 pub mod W {}
1086 pub mod RW {
1087 #[doc = "Power gated off"]
1088 pub const REG0_TARG_0: u32 = 0;
1089 #[doc = "Target core voltage = 0.725V"]
1090 pub const REG0_TARG_1: u32 = 0x01;
1091 #[doc = "Target core voltage = 0.750V"]
1092 pub const REG0_TARG_2: u32 = 0x02;
1093 #[doc = "Target core voltage = 0.775V"]
1094 pub const REG0_TARG_3: u32 = 0x03;
1095 #[doc = "Target core voltage = 1.100V"]
1096 pub const REG0_TARG_16: u32 = 0x10;
1097 #[doc = "Target core voltage = 1.450V"]
1098 pub const REG0_TARG_30: u32 = 0x1e;
1099 #[doc = "Power FET switched full on. No regulation."]
1100 pub const REG0_TARG_31: u32 = 0x1f;
1101 }
1102 }
1103 #[doc = "This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register."]
1104 pub mod REG0_ADJ {
1105 pub const offset: u32 = 5;
1106 pub const mask: u32 = 0x0f << offset;
1107 pub mod R {}
1108 pub mod W {}
1109 pub mod RW {
1110 #[doc = "No adjustment"]
1111 pub const REG0_ADJ_0: u32 = 0;
1112 #[doc = "+ 0.25%"]
1113 pub const REG0_ADJ_1: u32 = 0x01;
1114 #[doc = "+ 0.50%"]
1115 pub const REG0_ADJ_2: u32 = 0x02;
1116 #[doc = "+ 0.75%"]
1117 pub const REG0_ADJ_3: u32 = 0x03;
1118 #[doc = "+ 1.00%"]
1119 pub const REG0_ADJ_4: u32 = 0x04;
1120 #[doc = "+ 1.25%"]
1121 pub const REG0_ADJ_5: u32 = 0x05;
1122 #[doc = "+ 1.50%"]
1123 pub const REG0_ADJ_6: u32 = 0x06;
1124 #[doc = "+ 1.75%"]
1125 pub const REG0_ADJ_7: u32 = 0x07;
1126 #[doc = "- 0.25%"]
1127 pub const REG0_ADJ_8: u32 = 0x08;
1128 #[doc = "- 0.50%"]
1129 pub const REG0_ADJ_9: u32 = 0x09;
1130 #[doc = "- 0.75%"]
1131 pub const REG0_ADJ_10: u32 = 0x0a;
1132 #[doc = "- 1.00%"]
1133 pub const REG0_ADJ_11: u32 = 0x0b;
1134 #[doc = "- 1.25%"]
1135 pub const REG0_ADJ_12: u32 = 0x0c;
1136 #[doc = "- 1.50%"]
1137 pub const REG0_ADJ_13: u32 = 0x0d;
1138 #[doc = "- 1.75%"]
1139 pub const REG0_ADJ_14: u32 = 0x0e;
1140 #[doc = "- 2.00%"]
1141 pub const REG0_ADJ_15: u32 = 0x0f;
1142 }
1143 }
1144 #[doc = "This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation."]
1145 pub mod REG1_TARG {
1146 pub const offset: u32 = 9;
1147 pub const mask: u32 = 0x1f << offset;
1148 pub mod R {}
1149 pub mod W {}
1150 pub mod RW {
1151 #[doc = "Power gated off"]
1152 pub const REG1_TARG_0: u32 = 0;
1153 #[doc = "Target core voltage = 0.725V"]
1154 pub const REG1_TARG_1: u32 = 0x01;
1155 #[doc = "Target core voltage = 0.750V"]
1156 pub const REG1_TARG_2: u32 = 0x02;
1157 #[doc = "Target core voltage = 0.775V"]
1158 pub const REG1_TARG_3: u32 = 0x03;
1159 #[doc = "Target core voltage = 1.100V"]
1160 pub const REG1_TARG_16: u32 = 0x10;
1161 #[doc = "Target core voltage = 1.450V"]
1162 pub const REG1_TARG_30: u32 = 0x1e;
1163 #[doc = "Power FET switched full on. No regulation."]
1164 pub const REG1_TARG_31: u32 = 0x1f;
1165 }
1166 }
1167 #[doc = "This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register."]
1168 pub mod REG1_ADJ {
1169 pub const offset: u32 = 14;
1170 pub const mask: u32 = 0x0f << offset;
1171 pub mod R {}
1172 pub mod W {}
1173 pub mod RW {
1174 #[doc = "No adjustment"]
1175 pub const REG1_ADJ_0: u32 = 0;
1176 #[doc = "+ 0.25%"]
1177 pub const REG1_ADJ_1: u32 = 0x01;
1178 #[doc = "+ 0.50%"]
1179 pub const REG1_ADJ_2: u32 = 0x02;
1180 #[doc = "+ 0.75%"]
1181 pub const REG1_ADJ_3: u32 = 0x03;
1182 #[doc = "+ 1.00%"]
1183 pub const REG1_ADJ_4: u32 = 0x04;
1184 #[doc = "+ 1.25%"]
1185 pub const REG1_ADJ_5: u32 = 0x05;
1186 #[doc = "+ 1.50%"]
1187 pub const REG1_ADJ_6: u32 = 0x06;
1188 #[doc = "+ 1.75%"]
1189 pub const REG1_ADJ_7: u32 = 0x07;
1190 #[doc = "- 0.25%"]
1191 pub const REG1_ADJ_8: u32 = 0x08;
1192 #[doc = "- 0.50%"]
1193 pub const REG1_ADJ_9: u32 = 0x09;
1194 #[doc = "- 0.75%"]
1195 pub const REG1_ADJ_10: u32 = 0x0a;
1196 #[doc = "- 1.00%"]
1197 pub const REG1_ADJ_11: u32 = 0x0b;
1198 #[doc = "- 1.25%"]
1199 pub const REG1_ADJ_12: u32 = 0x0c;
1200 #[doc = "- 1.50%"]
1201 pub const REG1_ADJ_13: u32 = 0x0d;
1202 #[doc = "- 1.75%"]
1203 pub const REG1_ADJ_14: u32 = 0x0e;
1204 #[doc = "- 2.00%"]
1205 pub const REG1_ADJ_15: u32 = 0x0f;
1206 }
1207 }
1208 #[doc = "This field defines the target voltage for the SOC power domain"]
1209 pub mod REG2_TARG {
1210 pub const offset: u32 = 18;
1211 pub const mask: u32 = 0x1f << offset;
1212 pub mod R {}
1213 pub mod W {}
1214 pub mod RW {
1215 #[doc = "Power gated off"]
1216 pub const REG2_TARG_0: u32 = 0;
1217 #[doc = "Target core voltage = 0.725V"]
1218 pub const REG2_TARG_1: u32 = 0x01;
1219 #[doc = "Target core voltage = 0.750V"]
1220 pub const REG2_TARG_2: u32 = 0x02;
1221 #[doc = "Target core voltage = 0.775V"]
1222 pub const REG2_TARG_3: u32 = 0x03;
1223 #[doc = "Target core voltage = 1.100V"]
1224 pub const REG2_TARG_16: u32 = 0x10;
1225 #[doc = "Target core voltage = 1.450V"]
1226 pub const REG2_TARG_30: u32 = 0x1e;
1227 #[doc = "Power FET switched full on. No regulation."]
1228 pub const REG2_TARG_31: u32 = 0x1f;
1229 }
1230 }
1231 #[doc = "This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register."]
1232 pub mod REG2_ADJ {
1233 pub const offset: u32 = 23;
1234 pub const mask: u32 = 0x0f << offset;
1235 pub mod R {}
1236 pub mod W {}
1237 pub mod RW {
1238 #[doc = "No adjustment"]
1239 pub const REG2_ADJ_0: u32 = 0;
1240 #[doc = "+ 0.25%"]
1241 pub const REG2_ADJ_1: u32 = 0x01;
1242 #[doc = "+ 0.50%"]
1243 pub const REG2_ADJ_2: u32 = 0x02;
1244 #[doc = "+ 0.75%"]
1245 pub const REG2_ADJ_3: u32 = 0x03;
1246 #[doc = "+ 1.00%"]
1247 pub const REG2_ADJ_4: u32 = 0x04;
1248 #[doc = "+ 1.25%"]
1249 pub const REG2_ADJ_5: u32 = 0x05;
1250 #[doc = "+ 1.50%"]
1251 pub const REG2_ADJ_6: u32 = 0x06;
1252 #[doc = "+ 1.75%"]
1253 pub const REG2_ADJ_7: u32 = 0x07;
1254 #[doc = "- 0.25%"]
1255 pub const REG2_ADJ_8: u32 = 0x08;
1256 #[doc = "- 0.50%"]
1257 pub const REG2_ADJ_9: u32 = 0x09;
1258 #[doc = "- 0.75%"]
1259 pub const REG2_ADJ_10: u32 = 0x0a;
1260 #[doc = "- 1.00%"]
1261 pub const REG2_ADJ_11: u32 = 0x0b;
1262 #[doc = "- 1.25%"]
1263 pub const REG2_ADJ_12: u32 = 0x0c;
1264 #[doc = "- 1.50%"]
1265 pub const REG2_ADJ_13: u32 = 0x0d;
1266 #[doc = "- 1.75%"]
1267 pub const REG2_ADJ_14: u32 = 0x0e;
1268 #[doc = "- 2.00%"]
1269 pub const REG2_ADJ_15: u32 = 0x0f;
1270 }
1271 }
1272 #[doc = "Regulator voltage ramp rate."]
1273 pub mod RAMP_RATE {
1274 pub const offset: u32 = 27;
1275 pub const mask: u32 = 0x03 << offset;
1276 pub mod R {}
1277 pub mod W {}
1278 pub mod RW {
1279 #[doc = "Fast"]
1280 pub const RAMP_RATE_0: u32 = 0;
1281 #[doc = "Medium Fast"]
1282 pub const RAMP_RATE_1: u32 = 0x01;
1283 #[doc = "Medium Slow"]
1284 pub const RAMP_RATE_2: u32 = 0x02;
1285 #[doc = "Slow"]
1286 pub const RAMP_RATE_3: u32 = 0x03;
1287 }
1288 }
1289 #[doc = "If set, increases the gate drive on power gating FETs to reduce leakage in the off state"]
1290 pub mod FET_ODRIVE {
1291 pub const offset: u32 = 29;
1292 pub const mask: u32 = 0x01 << offset;
1293 pub mod R {}
1294 pub mod W {}
1295 pub mod RW {}
1296 }
1297}
1298#[doc = "Digital Regulator Core Register"]
1299pub mod REG_CORE_SET {
1300 #[doc = "This field defines the target voltage for the ARM core power domain"]
1301 pub mod REG0_TARG {
1302 pub const offset: u32 = 0;
1303 pub const mask: u32 = 0x1f << offset;
1304 pub mod R {}
1305 pub mod W {}
1306 pub mod RW {
1307 #[doc = "Power gated off"]
1308 pub const REG0_TARG_0: u32 = 0;
1309 #[doc = "Target core voltage = 0.725V"]
1310 pub const REG0_TARG_1: u32 = 0x01;
1311 #[doc = "Target core voltage = 0.750V"]
1312 pub const REG0_TARG_2: u32 = 0x02;
1313 #[doc = "Target core voltage = 0.775V"]
1314 pub const REG0_TARG_3: u32 = 0x03;
1315 #[doc = "Target core voltage = 1.100V"]
1316 pub const REG0_TARG_16: u32 = 0x10;
1317 #[doc = "Target core voltage = 1.450V"]
1318 pub const REG0_TARG_30: u32 = 0x1e;
1319 #[doc = "Power FET switched full on. No regulation."]
1320 pub const REG0_TARG_31: u32 = 0x1f;
1321 }
1322 }
1323 #[doc = "This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register."]
1324 pub mod REG0_ADJ {
1325 pub const offset: u32 = 5;
1326 pub const mask: u32 = 0x0f << offset;
1327 pub mod R {}
1328 pub mod W {}
1329 pub mod RW {
1330 #[doc = "No adjustment"]
1331 pub const REG0_ADJ_0: u32 = 0;
1332 #[doc = "+ 0.25%"]
1333 pub const REG0_ADJ_1: u32 = 0x01;
1334 #[doc = "+ 0.50%"]
1335 pub const REG0_ADJ_2: u32 = 0x02;
1336 #[doc = "+ 0.75%"]
1337 pub const REG0_ADJ_3: u32 = 0x03;
1338 #[doc = "+ 1.00%"]
1339 pub const REG0_ADJ_4: u32 = 0x04;
1340 #[doc = "+ 1.25%"]
1341 pub const REG0_ADJ_5: u32 = 0x05;
1342 #[doc = "+ 1.50%"]
1343 pub const REG0_ADJ_6: u32 = 0x06;
1344 #[doc = "+ 1.75%"]
1345 pub const REG0_ADJ_7: u32 = 0x07;
1346 #[doc = "- 0.25%"]
1347 pub const REG0_ADJ_8: u32 = 0x08;
1348 #[doc = "- 0.50%"]
1349 pub const REG0_ADJ_9: u32 = 0x09;
1350 #[doc = "- 0.75%"]
1351 pub const REG0_ADJ_10: u32 = 0x0a;
1352 #[doc = "- 1.00%"]
1353 pub const REG0_ADJ_11: u32 = 0x0b;
1354 #[doc = "- 1.25%"]
1355 pub const REG0_ADJ_12: u32 = 0x0c;
1356 #[doc = "- 1.50%"]
1357 pub const REG0_ADJ_13: u32 = 0x0d;
1358 #[doc = "- 1.75%"]
1359 pub const REG0_ADJ_14: u32 = 0x0e;
1360 #[doc = "- 2.00%"]
1361 pub const REG0_ADJ_15: u32 = 0x0f;
1362 }
1363 }
1364 #[doc = "This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation."]
1365 pub mod REG1_TARG {
1366 pub const offset: u32 = 9;
1367 pub const mask: u32 = 0x1f << offset;
1368 pub mod R {}
1369 pub mod W {}
1370 pub mod RW {
1371 #[doc = "Power gated off"]
1372 pub const REG1_TARG_0: u32 = 0;
1373 #[doc = "Target core voltage = 0.725V"]
1374 pub const REG1_TARG_1: u32 = 0x01;
1375 #[doc = "Target core voltage = 0.750V"]
1376 pub const REG1_TARG_2: u32 = 0x02;
1377 #[doc = "Target core voltage = 0.775V"]
1378 pub const REG1_TARG_3: u32 = 0x03;
1379 #[doc = "Target core voltage = 1.100V"]
1380 pub const REG1_TARG_16: u32 = 0x10;
1381 #[doc = "Target core voltage = 1.450V"]
1382 pub const REG1_TARG_30: u32 = 0x1e;
1383 #[doc = "Power FET switched full on. No regulation."]
1384 pub const REG1_TARG_31: u32 = 0x1f;
1385 }
1386 }
1387 #[doc = "This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register."]
1388 pub mod REG1_ADJ {
1389 pub const offset: u32 = 14;
1390 pub const mask: u32 = 0x0f << offset;
1391 pub mod R {}
1392 pub mod W {}
1393 pub mod RW {
1394 #[doc = "No adjustment"]
1395 pub const REG1_ADJ_0: u32 = 0;
1396 #[doc = "+ 0.25%"]
1397 pub const REG1_ADJ_1: u32 = 0x01;
1398 #[doc = "+ 0.50%"]
1399 pub const REG1_ADJ_2: u32 = 0x02;
1400 #[doc = "+ 0.75%"]
1401 pub const REG1_ADJ_3: u32 = 0x03;
1402 #[doc = "+ 1.00%"]
1403 pub const REG1_ADJ_4: u32 = 0x04;
1404 #[doc = "+ 1.25%"]
1405 pub const REG1_ADJ_5: u32 = 0x05;
1406 #[doc = "+ 1.50%"]
1407 pub const REG1_ADJ_6: u32 = 0x06;
1408 #[doc = "+ 1.75%"]
1409 pub const REG1_ADJ_7: u32 = 0x07;
1410 #[doc = "- 0.25%"]
1411 pub const REG1_ADJ_8: u32 = 0x08;
1412 #[doc = "- 0.50%"]
1413 pub const REG1_ADJ_9: u32 = 0x09;
1414 #[doc = "- 0.75%"]
1415 pub const REG1_ADJ_10: u32 = 0x0a;
1416 #[doc = "- 1.00%"]
1417 pub const REG1_ADJ_11: u32 = 0x0b;
1418 #[doc = "- 1.25%"]
1419 pub const REG1_ADJ_12: u32 = 0x0c;
1420 #[doc = "- 1.50%"]
1421 pub const REG1_ADJ_13: u32 = 0x0d;
1422 #[doc = "- 1.75%"]
1423 pub const REG1_ADJ_14: u32 = 0x0e;
1424 #[doc = "- 2.00%"]
1425 pub const REG1_ADJ_15: u32 = 0x0f;
1426 }
1427 }
1428 #[doc = "This field defines the target voltage for the SOC power domain"]
1429 pub mod REG2_TARG {
1430 pub const offset: u32 = 18;
1431 pub const mask: u32 = 0x1f << offset;
1432 pub mod R {}
1433 pub mod W {}
1434 pub mod RW {
1435 #[doc = "Power gated off"]
1436 pub const REG2_TARG_0: u32 = 0;
1437 #[doc = "Target core voltage = 0.725V"]
1438 pub const REG2_TARG_1: u32 = 0x01;
1439 #[doc = "Target core voltage = 0.750V"]
1440 pub const REG2_TARG_2: u32 = 0x02;
1441 #[doc = "Target core voltage = 0.775V"]
1442 pub const REG2_TARG_3: u32 = 0x03;
1443 #[doc = "Target core voltage = 1.100V"]
1444 pub const REG2_TARG_16: u32 = 0x10;
1445 #[doc = "Target core voltage = 1.450V"]
1446 pub const REG2_TARG_30: u32 = 0x1e;
1447 #[doc = "Power FET switched full on. No regulation."]
1448 pub const REG2_TARG_31: u32 = 0x1f;
1449 }
1450 }
1451 #[doc = "This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register."]
1452 pub mod REG2_ADJ {
1453 pub const offset: u32 = 23;
1454 pub const mask: u32 = 0x0f << offset;
1455 pub mod R {}
1456 pub mod W {}
1457 pub mod RW {
1458 #[doc = "No adjustment"]
1459 pub const REG2_ADJ_0: u32 = 0;
1460 #[doc = "+ 0.25%"]
1461 pub const REG2_ADJ_1: u32 = 0x01;
1462 #[doc = "+ 0.50%"]
1463 pub const REG2_ADJ_2: u32 = 0x02;
1464 #[doc = "+ 0.75%"]
1465 pub const REG2_ADJ_3: u32 = 0x03;
1466 #[doc = "+ 1.00%"]
1467 pub const REG2_ADJ_4: u32 = 0x04;
1468 #[doc = "+ 1.25%"]
1469 pub const REG2_ADJ_5: u32 = 0x05;
1470 #[doc = "+ 1.50%"]
1471 pub const REG2_ADJ_6: u32 = 0x06;
1472 #[doc = "+ 1.75%"]
1473 pub const REG2_ADJ_7: u32 = 0x07;
1474 #[doc = "- 0.25%"]
1475 pub const REG2_ADJ_8: u32 = 0x08;
1476 #[doc = "- 0.50%"]
1477 pub const REG2_ADJ_9: u32 = 0x09;
1478 #[doc = "- 0.75%"]
1479 pub const REG2_ADJ_10: u32 = 0x0a;
1480 #[doc = "- 1.00%"]
1481 pub const REG2_ADJ_11: u32 = 0x0b;
1482 #[doc = "- 1.25%"]
1483 pub const REG2_ADJ_12: u32 = 0x0c;
1484 #[doc = "- 1.50%"]
1485 pub const REG2_ADJ_13: u32 = 0x0d;
1486 #[doc = "- 1.75%"]
1487 pub const REG2_ADJ_14: u32 = 0x0e;
1488 #[doc = "- 2.00%"]
1489 pub const REG2_ADJ_15: u32 = 0x0f;
1490 }
1491 }
1492 #[doc = "Regulator voltage ramp rate."]
1493 pub mod RAMP_RATE {
1494 pub const offset: u32 = 27;
1495 pub const mask: u32 = 0x03 << offset;
1496 pub mod R {}
1497 pub mod W {}
1498 pub mod RW {
1499 #[doc = "Fast"]
1500 pub const RAMP_RATE_0: u32 = 0;
1501 #[doc = "Medium Fast"]
1502 pub const RAMP_RATE_1: u32 = 0x01;
1503 #[doc = "Medium Slow"]
1504 pub const RAMP_RATE_2: u32 = 0x02;
1505 #[doc = "Slow"]
1506 pub const RAMP_RATE_3: u32 = 0x03;
1507 }
1508 }
1509 #[doc = "If set, increases the gate drive on power gating FETs to reduce leakage in the off state"]
1510 pub mod FET_ODRIVE {
1511 pub const offset: u32 = 29;
1512 pub const mask: u32 = 0x01 << offset;
1513 pub mod R {}
1514 pub mod W {}
1515 pub mod RW {}
1516 }
1517}
1518#[doc = "Digital Regulator Core Register"]
1519pub mod REG_CORE_CLR {
1520 #[doc = "This field defines the target voltage for the ARM core power domain"]
1521 pub mod REG0_TARG {
1522 pub const offset: u32 = 0;
1523 pub const mask: u32 = 0x1f << offset;
1524 pub mod R {}
1525 pub mod W {}
1526 pub mod RW {
1527 #[doc = "Power gated off"]
1528 pub const REG0_TARG_0: u32 = 0;
1529 #[doc = "Target core voltage = 0.725V"]
1530 pub const REG0_TARG_1: u32 = 0x01;
1531 #[doc = "Target core voltage = 0.750V"]
1532 pub const REG0_TARG_2: u32 = 0x02;
1533 #[doc = "Target core voltage = 0.775V"]
1534 pub const REG0_TARG_3: u32 = 0x03;
1535 #[doc = "Target core voltage = 1.100V"]
1536 pub const REG0_TARG_16: u32 = 0x10;
1537 #[doc = "Target core voltage = 1.450V"]
1538 pub const REG0_TARG_30: u32 = 0x1e;
1539 #[doc = "Power FET switched full on. No regulation."]
1540 pub const REG0_TARG_31: u32 = 0x1f;
1541 }
1542 }
1543 #[doc = "This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register."]
1544 pub mod REG0_ADJ {
1545 pub const offset: u32 = 5;
1546 pub const mask: u32 = 0x0f << offset;
1547 pub mod R {}
1548 pub mod W {}
1549 pub mod RW {
1550 #[doc = "No adjustment"]
1551 pub const REG0_ADJ_0: u32 = 0;
1552 #[doc = "+ 0.25%"]
1553 pub const REG0_ADJ_1: u32 = 0x01;
1554 #[doc = "+ 0.50%"]
1555 pub const REG0_ADJ_2: u32 = 0x02;
1556 #[doc = "+ 0.75%"]
1557 pub const REG0_ADJ_3: u32 = 0x03;
1558 #[doc = "+ 1.00%"]
1559 pub const REG0_ADJ_4: u32 = 0x04;
1560 #[doc = "+ 1.25%"]
1561 pub const REG0_ADJ_5: u32 = 0x05;
1562 #[doc = "+ 1.50%"]
1563 pub const REG0_ADJ_6: u32 = 0x06;
1564 #[doc = "+ 1.75%"]
1565 pub const REG0_ADJ_7: u32 = 0x07;
1566 #[doc = "- 0.25%"]
1567 pub const REG0_ADJ_8: u32 = 0x08;
1568 #[doc = "- 0.50%"]
1569 pub const REG0_ADJ_9: u32 = 0x09;
1570 #[doc = "- 0.75%"]
1571 pub const REG0_ADJ_10: u32 = 0x0a;
1572 #[doc = "- 1.00%"]
1573 pub const REG0_ADJ_11: u32 = 0x0b;
1574 #[doc = "- 1.25%"]
1575 pub const REG0_ADJ_12: u32 = 0x0c;
1576 #[doc = "- 1.50%"]
1577 pub const REG0_ADJ_13: u32 = 0x0d;
1578 #[doc = "- 1.75%"]
1579 pub const REG0_ADJ_14: u32 = 0x0e;
1580 #[doc = "- 2.00%"]
1581 pub const REG0_ADJ_15: u32 = 0x0f;
1582 }
1583 }
1584 #[doc = "This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation."]
1585 pub mod REG1_TARG {
1586 pub const offset: u32 = 9;
1587 pub const mask: u32 = 0x1f << offset;
1588 pub mod R {}
1589 pub mod W {}
1590 pub mod RW {
1591 #[doc = "Power gated off"]
1592 pub const REG1_TARG_0: u32 = 0;
1593 #[doc = "Target core voltage = 0.725V"]
1594 pub const REG1_TARG_1: u32 = 0x01;
1595 #[doc = "Target core voltage = 0.750V"]
1596 pub const REG1_TARG_2: u32 = 0x02;
1597 #[doc = "Target core voltage = 0.775V"]
1598 pub const REG1_TARG_3: u32 = 0x03;
1599 #[doc = "Target core voltage = 1.100V"]
1600 pub const REG1_TARG_16: u32 = 0x10;
1601 #[doc = "Target core voltage = 1.450V"]
1602 pub const REG1_TARG_30: u32 = 0x1e;
1603 #[doc = "Power FET switched full on. No regulation."]
1604 pub const REG1_TARG_31: u32 = 0x1f;
1605 }
1606 }
1607 #[doc = "This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register."]
1608 pub mod REG1_ADJ {
1609 pub const offset: u32 = 14;
1610 pub const mask: u32 = 0x0f << offset;
1611 pub mod R {}
1612 pub mod W {}
1613 pub mod RW {
1614 #[doc = "No adjustment"]
1615 pub const REG1_ADJ_0: u32 = 0;
1616 #[doc = "+ 0.25%"]
1617 pub const REG1_ADJ_1: u32 = 0x01;
1618 #[doc = "+ 0.50%"]
1619 pub const REG1_ADJ_2: u32 = 0x02;
1620 #[doc = "+ 0.75%"]
1621 pub const REG1_ADJ_3: u32 = 0x03;
1622 #[doc = "+ 1.00%"]
1623 pub const REG1_ADJ_4: u32 = 0x04;
1624 #[doc = "+ 1.25%"]
1625 pub const REG1_ADJ_5: u32 = 0x05;
1626 #[doc = "+ 1.50%"]
1627 pub const REG1_ADJ_6: u32 = 0x06;
1628 #[doc = "+ 1.75%"]
1629 pub const REG1_ADJ_7: u32 = 0x07;
1630 #[doc = "- 0.25%"]
1631 pub const REG1_ADJ_8: u32 = 0x08;
1632 #[doc = "- 0.50%"]
1633 pub const REG1_ADJ_9: u32 = 0x09;
1634 #[doc = "- 0.75%"]
1635 pub const REG1_ADJ_10: u32 = 0x0a;
1636 #[doc = "- 1.00%"]
1637 pub const REG1_ADJ_11: u32 = 0x0b;
1638 #[doc = "- 1.25%"]
1639 pub const REG1_ADJ_12: u32 = 0x0c;
1640 #[doc = "- 1.50%"]
1641 pub const REG1_ADJ_13: u32 = 0x0d;
1642 #[doc = "- 1.75%"]
1643 pub const REG1_ADJ_14: u32 = 0x0e;
1644 #[doc = "- 2.00%"]
1645 pub const REG1_ADJ_15: u32 = 0x0f;
1646 }
1647 }
1648 #[doc = "This field defines the target voltage for the SOC power domain"]
1649 pub mod REG2_TARG {
1650 pub const offset: u32 = 18;
1651 pub const mask: u32 = 0x1f << offset;
1652 pub mod R {}
1653 pub mod W {}
1654 pub mod RW {
1655 #[doc = "Power gated off"]
1656 pub const REG2_TARG_0: u32 = 0;
1657 #[doc = "Target core voltage = 0.725V"]
1658 pub const REG2_TARG_1: u32 = 0x01;
1659 #[doc = "Target core voltage = 0.750V"]
1660 pub const REG2_TARG_2: u32 = 0x02;
1661 #[doc = "Target core voltage = 0.775V"]
1662 pub const REG2_TARG_3: u32 = 0x03;
1663 #[doc = "Target core voltage = 1.100V"]
1664 pub const REG2_TARG_16: u32 = 0x10;
1665 #[doc = "Target core voltage = 1.450V"]
1666 pub const REG2_TARG_30: u32 = 0x1e;
1667 #[doc = "Power FET switched full on. No regulation."]
1668 pub const REG2_TARG_31: u32 = 0x1f;
1669 }
1670 }
1671 #[doc = "This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register."]
1672 pub mod REG2_ADJ {
1673 pub const offset: u32 = 23;
1674 pub const mask: u32 = 0x0f << offset;
1675 pub mod R {}
1676 pub mod W {}
1677 pub mod RW {
1678 #[doc = "No adjustment"]
1679 pub const REG2_ADJ_0: u32 = 0;
1680 #[doc = "+ 0.25%"]
1681 pub const REG2_ADJ_1: u32 = 0x01;
1682 #[doc = "+ 0.50%"]
1683 pub const REG2_ADJ_2: u32 = 0x02;
1684 #[doc = "+ 0.75%"]
1685 pub const REG2_ADJ_3: u32 = 0x03;
1686 #[doc = "+ 1.00%"]
1687 pub const REG2_ADJ_4: u32 = 0x04;
1688 #[doc = "+ 1.25%"]
1689 pub const REG2_ADJ_5: u32 = 0x05;
1690 #[doc = "+ 1.50%"]
1691 pub const REG2_ADJ_6: u32 = 0x06;
1692 #[doc = "+ 1.75%"]
1693 pub const REG2_ADJ_7: u32 = 0x07;
1694 #[doc = "- 0.25%"]
1695 pub const REG2_ADJ_8: u32 = 0x08;
1696 #[doc = "- 0.50%"]
1697 pub const REG2_ADJ_9: u32 = 0x09;
1698 #[doc = "- 0.75%"]
1699 pub const REG2_ADJ_10: u32 = 0x0a;
1700 #[doc = "- 1.00%"]
1701 pub const REG2_ADJ_11: u32 = 0x0b;
1702 #[doc = "- 1.25%"]
1703 pub const REG2_ADJ_12: u32 = 0x0c;
1704 #[doc = "- 1.50%"]
1705 pub const REG2_ADJ_13: u32 = 0x0d;
1706 #[doc = "- 1.75%"]
1707 pub const REG2_ADJ_14: u32 = 0x0e;
1708 #[doc = "- 2.00%"]
1709 pub const REG2_ADJ_15: u32 = 0x0f;
1710 }
1711 }
1712 #[doc = "Regulator voltage ramp rate."]
1713 pub mod RAMP_RATE {
1714 pub const offset: u32 = 27;
1715 pub const mask: u32 = 0x03 << offset;
1716 pub mod R {}
1717 pub mod W {}
1718 pub mod RW {
1719 #[doc = "Fast"]
1720 pub const RAMP_RATE_0: u32 = 0;
1721 #[doc = "Medium Fast"]
1722 pub const RAMP_RATE_1: u32 = 0x01;
1723 #[doc = "Medium Slow"]
1724 pub const RAMP_RATE_2: u32 = 0x02;
1725 #[doc = "Slow"]
1726 pub const RAMP_RATE_3: u32 = 0x03;
1727 }
1728 }
1729 #[doc = "If set, increases the gate drive on power gating FETs to reduce leakage in the off state"]
1730 pub mod FET_ODRIVE {
1731 pub const offset: u32 = 29;
1732 pub const mask: u32 = 0x01 << offset;
1733 pub mod R {}
1734 pub mod W {}
1735 pub mod RW {}
1736 }
1737}
1738#[doc = "Digital Regulator Core Register"]
1739pub mod REG_CORE_TOG {
1740 #[doc = "This field defines the target voltage for the ARM core power domain"]
1741 pub mod REG0_TARG {
1742 pub const offset: u32 = 0;
1743 pub const mask: u32 = 0x1f << offset;
1744 pub mod R {}
1745 pub mod W {}
1746 pub mod RW {
1747 #[doc = "Power gated off"]
1748 pub const REG0_TARG_0: u32 = 0;
1749 #[doc = "Target core voltage = 0.725V"]
1750 pub const REG0_TARG_1: u32 = 0x01;
1751 #[doc = "Target core voltage = 0.750V"]
1752 pub const REG0_TARG_2: u32 = 0x02;
1753 #[doc = "Target core voltage = 0.775V"]
1754 pub const REG0_TARG_3: u32 = 0x03;
1755 #[doc = "Target core voltage = 1.100V"]
1756 pub const REG0_TARG_16: u32 = 0x10;
1757 #[doc = "Target core voltage = 1.450V"]
1758 pub const REG0_TARG_30: u32 = 0x1e;
1759 #[doc = "Power FET switched full on. No regulation."]
1760 pub const REG0_TARG_31: u32 = 0x1f;
1761 }
1762 }
1763 #[doc = "This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register."]
1764 pub mod REG0_ADJ {
1765 pub const offset: u32 = 5;
1766 pub const mask: u32 = 0x0f << offset;
1767 pub mod R {}
1768 pub mod W {}
1769 pub mod RW {
1770 #[doc = "No adjustment"]
1771 pub const REG0_ADJ_0: u32 = 0;
1772 #[doc = "+ 0.25%"]
1773 pub const REG0_ADJ_1: u32 = 0x01;
1774 #[doc = "+ 0.50%"]
1775 pub const REG0_ADJ_2: u32 = 0x02;
1776 #[doc = "+ 0.75%"]
1777 pub const REG0_ADJ_3: u32 = 0x03;
1778 #[doc = "+ 1.00%"]
1779 pub const REG0_ADJ_4: u32 = 0x04;
1780 #[doc = "+ 1.25%"]
1781 pub const REG0_ADJ_5: u32 = 0x05;
1782 #[doc = "+ 1.50%"]
1783 pub const REG0_ADJ_6: u32 = 0x06;
1784 #[doc = "+ 1.75%"]
1785 pub const REG0_ADJ_7: u32 = 0x07;
1786 #[doc = "- 0.25%"]
1787 pub const REG0_ADJ_8: u32 = 0x08;
1788 #[doc = "- 0.50%"]
1789 pub const REG0_ADJ_9: u32 = 0x09;
1790 #[doc = "- 0.75%"]
1791 pub const REG0_ADJ_10: u32 = 0x0a;
1792 #[doc = "- 1.00%"]
1793 pub const REG0_ADJ_11: u32 = 0x0b;
1794 #[doc = "- 1.25%"]
1795 pub const REG0_ADJ_12: u32 = 0x0c;
1796 #[doc = "- 1.50%"]
1797 pub const REG0_ADJ_13: u32 = 0x0d;
1798 #[doc = "- 1.75%"]
1799 pub const REG0_ADJ_14: u32 = 0x0e;
1800 #[doc = "- 2.00%"]
1801 pub const REG0_ADJ_15: u32 = 0x0f;
1802 }
1803 }
1804 #[doc = "This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation."]
1805 pub mod REG1_TARG {
1806 pub const offset: u32 = 9;
1807 pub const mask: u32 = 0x1f << offset;
1808 pub mod R {}
1809 pub mod W {}
1810 pub mod RW {
1811 #[doc = "Power gated off"]
1812 pub const REG1_TARG_0: u32 = 0;
1813 #[doc = "Target core voltage = 0.725V"]
1814 pub const REG1_TARG_1: u32 = 0x01;
1815 #[doc = "Target core voltage = 0.750V"]
1816 pub const REG1_TARG_2: u32 = 0x02;
1817 #[doc = "Target core voltage = 0.775V"]
1818 pub const REG1_TARG_3: u32 = 0x03;
1819 #[doc = "Target core voltage = 1.100V"]
1820 pub const REG1_TARG_16: u32 = 0x10;
1821 #[doc = "Target core voltage = 1.450V"]
1822 pub const REG1_TARG_30: u32 = 0x1e;
1823 #[doc = "Power FET switched full on. No regulation."]
1824 pub const REG1_TARG_31: u32 = 0x1f;
1825 }
1826 }
1827 #[doc = "This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register."]
1828 pub mod REG1_ADJ {
1829 pub const offset: u32 = 14;
1830 pub const mask: u32 = 0x0f << offset;
1831 pub mod R {}
1832 pub mod W {}
1833 pub mod RW {
1834 #[doc = "No adjustment"]
1835 pub const REG1_ADJ_0: u32 = 0;
1836 #[doc = "+ 0.25%"]
1837 pub const REG1_ADJ_1: u32 = 0x01;
1838 #[doc = "+ 0.50%"]
1839 pub const REG1_ADJ_2: u32 = 0x02;
1840 #[doc = "+ 0.75%"]
1841 pub const REG1_ADJ_3: u32 = 0x03;
1842 #[doc = "+ 1.00%"]
1843 pub const REG1_ADJ_4: u32 = 0x04;
1844 #[doc = "+ 1.25%"]
1845 pub const REG1_ADJ_5: u32 = 0x05;
1846 #[doc = "+ 1.50%"]
1847 pub const REG1_ADJ_6: u32 = 0x06;
1848 #[doc = "+ 1.75%"]
1849 pub const REG1_ADJ_7: u32 = 0x07;
1850 #[doc = "- 0.25%"]
1851 pub const REG1_ADJ_8: u32 = 0x08;
1852 #[doc = "- 0.50%"]
1853 pub const REG1_ADJ_9: u32 = 0x09;
1854 #[doc = "- 0.75%"]
1855 pub const REG1_ADJ_10: u32 = 0x0a;
1856 #[doc = "- 1.00%"]
1857 pub const REG1_ADJ_11: u32 = 0x0b;
1858 #[doc = "- 1.25%"]
1859 pub const REG1_ADJ_12: u32 = 0x0c;
1860 #[doc = "- 1.50%"]
1861 pub const REG1_ADJ_13: u32 = 0x0d;
1862 #[doc = "- 1.75%"]
1863 pub const REG1_ADJ_14: u32 = 0x0e;
1864 #[doc = "- 2.00%"]
1865 pub const REG1_ADJ_15: u32 = 0x0f;
1866 }
1867 }
1868 #[doc = "This field defines the target voltage for the SOC power domain"]
1869 pub mod REG2_TARG {
1870 pub const offset: u32 = 18;
1871 pub const mask: u32 = 0x1f << offset;
1872 pub mod R {}
1873 pub mod W {}
1874 pub mod RW {
1875 #[doc = "Power gated off"]
1876 pub const REG2_TARG_0: u32 = 0;
1877 #[doc = "Target core voltage = 0.725V"]
1878 pub const REG2_TARG_1: u32 = 0x01;
1879 #[doc = "Target core voltage = 0.750V"]
1880 pub const REG2_TARG_2: u32 = 0x02;
1881 #[doc = "Target core voltage = 0.775V"]
1882 pub const REG2_TARG_3: u32 = 0x03;
1883 #[doc = "Target core voltage = 1.100V"]
1884 pub const REG2_TARG_16: u32 = 0x10;
1885 #[doc = "Target core voltage = 1.450V"]
1886 pub const REG2_TARG_30: u32 = 0x1e;
1887 #[doc = "Power FET switched full on. No regulation."]
1888 pub const REG2_TARG_31: u32 = 0x1f;
1889 }
1890 }
1891 #[doc = "This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register."]
1892 pub mod REG2_ADJ {
1893 pub const offset: u32 = 23;
1894 pub const mask: u32 = 0x0f << offset;
1895 pub mod R {}
1896 pub mod W {}
1897 pub mod RW {
1898 #[doc = "No adjustment"]
1899 pub const REG2_ADJ_0: u32 = 0;
1900 #[doc = "+ 0.25%"]
1901 pub const REG2_ADJ_1: u32 = 0x01;
1902 #[doc = "+ 0.50%"]
1903 pub const REG2_ADJ_2: u32 = 0x02;
1904 #[doc = "+ 0.75%"]
1905 pub const REG2_ADJ_3: u32 = 0x03;
1906 #[doc = "+ 1.00%"]
1907 pub const REG2_ADJ_4: u32 = 0x04;
1908 #[doc = "+ 1.25%"]
1909 pub const REG2_ADJ_5: u32 = 0x05;
1910 #[doc = "+ 1.50%"]
1911 pub const REG2_ADJ_6: u32 = 0x06;
1912 #[doc = "+ 1.75%"]
1913 pub const REG2_ADJ_7: u32 = 0x07;
1914 #[doc = "- 0.25%"]
1915 pub const REG2_ADJ_8: u32 = 0x08;
1916 #[doc = "- 0.50%"]
1917 pub const REG2_ADJ_9: u32 = 0x09;
1918 #[doc = "- 0.75%"]
1919 pub const REG2_ADJ_10: u32 = 0x0a;
1920 #[doc = "- 1.00%"]
1921 pub const REG2_ADJ_11: u32 = 0x0b;
1922 #[doc = "- 1.25%"]
1923 pub const REG2_ADJ_12: u32 = 0x0c;
1924 #[doc = "- 1.50%"]
1925 pub const REG2_ADJ_13: u32 = 0x0d;
1926 #[doc = "- 1.75%"]
1927 pub const REG2_ADJ_14: u32 = 0x0e;
1928 #[doc = "- 2.00%"]
1929 pub const REG2_ADJ_15: u32 = 0x0f;
1930 }
1931 }
1932 #[doc = "Regulator voltage ramp rate."]
1933 pub mod RAMP_RATE {
1934 pub const offset: u32 = 27;
1935 pub const mask: u32 = 0x03 << offset;
1936 pub mod R {}
1937 pub mod W {}
1938 pub mod RW {
1939 #[doc = "Fast"]
1940 pub const RAMP_RATE_0: u32 = 0;
1941 #[doc = "Medium Fast"]
1942 pub const RAMP_RATE_1: u32 = 0x01;
1943 #[doc = "Medium Slow"]
1944 pub const RAMP_RATE_2: u32 = 0x02;
1945 #[doc = "Slow"]
1946 pub const RAMP_RATE_3: u32 = 0x03;
1947 }
1948 }
1949 #[doc = "If set, increases the gate drive on power gating FETs to reduce leakage in the off state"]
1950 pub mod FET_ODRIVE {
1951 pub const offset: u32 = 29;
1952 pub const mask: u32 = 0x01 << offset;
1953 pub mod R {}
1954 pub mod W {}
1955 pub mod RW {}
1956 }
1957}
1958#[doc = "Miscellaneous Register 0"]
1959pub mod MISC0 {
1960 #[doc = "Control bit to power-down the analog bandgap reference circuitry"]
1961 pub mod REFTOP_PWD {
1962 pub const offset: u32 = 0;
1963 pub const mask: u32 = 0x01 << offset;
1964 pub mod R {}
1965 pub mod W {}
1966 pub mod RW {}
1967 }
1968 #[doc = "Control bit to disable the self-bias circuit in the analog bandgap"]
1969 pub mod REFTOP_SELFBIASOFF {
1970 pub const offset: u32 = 3;
1971 pub const mask: u32 = 0x01 << offset;
1972 pub mod R {}
1973 pub mod W {}
1974 pub mod RW {
1975 #[doc = "Uses coarse bias currents for startup"]
1976 pub const REFTOP_SELFBIASOFF_0: u32 = 0;
1977 #[doc = "Uses bandgap-based bias currents for best performance."]
1978 pub const REFTOP_SELFBIASOFF_1: u32 = 0x01;
1979 }
1980 }
1981 #[doc = "no description available"]
1982 pub mod REFTOP_VBGADJ {
1983 pub const offset: u32 = 4;
1984 pub const mask: u32 = 0x07 << offset;
1985 pub mod R {}
1986 pub mod W {}
1987 pub mod RW {
1988 #[doc = "Nominal VBG"]
1989 pub const REFTOP_VBGADJ_0: u32 = 0;
1990 #[doc = "VBG+0.78%"]
1991 pub const REFTOP_VBGADJ_1: u32 = 0x01;
1992 #[doc = "VBG+1.56%"]
1993 pub const REFTOP_VBGADJ_2: u32 = 0x02;
1994 #[doc = "VBG+2.34%"]
1995 pub const REFTOP_VBGADJ_3: u32 = 0x03;
1996 #[doc = "VBG-0.78%"]
1997 pub const REFTOP_VBGADJ_4: u32 = 0x04;
1998 #[doc = "VBG-1.56%"]
1999 pub const REFTOP_VBGADJ_5: u32 = 0x05;
2000 #[doc = "VBG-2.34%"]
2001 pub const REFTOP_VBGADJ_6: u32 = 0x06;
2002 #[doc = "VBG-3.12%"]
2003 pub const REFTOP_VBGADJ_7: u32 = 0x07;
2004 }
2005 }
2006 #[doc = "Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable."]
2007 pub mod REFTOP_VBGUP {
2008 pub const offset: u32 = 7;
2009 pub const mask: u32 = 0x01 << offset;
2010 pub mod R {}
2011 pub mod W {}
2012 pub mod RW {}
2013 }
2014 #[doc = "Configure the analog behavior in stop mode."]
2015 pub mod STOP_MODE_CONFIG {
2016 pub const offset: u32 = 10;
2017 pub const mask: u32 = 0x03 << offset;
2018 pub mod R {}
2019 pub mod W {}
2020 pub mod RW {
2021 #[doc = "SUSPEND (DSM)"]
2022 pub const STOP_MODE_CONFIG_0: u32 = 0;
2023 #[doc = "Analog regulators are ON."]
2024 pub const STANDBY: u32 = 0x01;
2025 #[doc = "STOP (lower power)"]
2026 pub const STOP_MODE_CONFIG_2: u32 = 0x02;
2027 #[doc = "STOP (very lower power)"]
2028 pub const STOP_MODE_CONFIG_3: u32 = 0x03;
2029 }
2030 }
2031 #[doc = "This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN."]
2032 pub mod DISCON_HIGH_SNVS {
2033 pub const offset: u32 = 12;
2034 pub const mask: u32 = 0x01 << offset;
2035 pub mod R {}
2036 pub mod W {}
2037 pub mod RW {
2038 #[doc = "Turn on the switch"]
2039 pub const DISCON_HIGH_SNVS_0: u32 = 0;
2040 #[doc = "Turn off the switch"]
2041 pub const DISCON_HIGH_SNVS_1: u32 = 0x01;
2042 }
2043 }
2044 #[doc = "This field determines the bias current in the 24MHz oscillator"]
2045 pub mod OSC_I {
2046 pub const offset: u32 = 13;
2047 pub const mask: u32 = 0x03 << offset;
2048 pub mod R {}
2049 pub mod W {}
2050 pub mod RW {
2051 #[doc = "Nominal"]
2052 pub const NOMINAL: u32 = 0;
2053 #[doc = "Decrease current by 12.5%"]
2054 pub const MINUS_12_5_PERCENT: u32 = 0x01;
2055 #[doc = "Decrease current by 25.0%"]
2056 pub const MINUS_25_PERCENT: u32 = 0x02;
2057 #[doc = "Decrease current by 37.5%"]
2058 pub const MINUS_37_5_PERCENT: u32 = 0x03;
2059 }
2060 }
2061 #[doc = "Status bit that signals that the output of the 24-MHz crystal oscillator is stable"]
2062 pub mod OSC_XTALOK {
2063 pub const offset: u32 = 15;
2064 pub const mask: u32 = 0x01 << offset;
2065 pub mod R {}
2066 pub mod W {}
2067 pub mod RW {}
2068 }
2069 #[doc = "This bit enables the detector that signals when the 24MHz crystal oscillator is stable"]
2070 pub mod OSC_XTALOK_EN {
2071 pub const offset: u32 = 16;
2072 pub const mask: u32 = 0x01 << offset;
2073 pub mod R {}
2074 pub mod W {}
2075 pub mod RW {}
2076 }
2077 #[doc = "This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block"]
2078 pub mod CLKGATE_CTRL {
2079 pub const offset: u32 = 25;
2080 pub const mask: u32 = 0x01 << offset;
2081 pub mod R {}
2082 pub mod W {}
2083 pub mod RW {
2084 #[doc = "Allow the logic to automatically gate the clock when the XTAL is powered down."]
2085 pub const ALLOW_AUTO_GATE: u32 = 0;
2086 #[doc = "Prevent the logic from ever gating off the clock."]
2087 pub const NO_AUTO_GATE: u32 = 0x01;
2088 }
2089 }
2090 #[doc = "This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block"]
2091 pub mod CLKGATE_DELAY {
2092 pub const offset: u32 = 26;
2093 pub const mask: u32 = 0x07 << offset;
2094 pub mod R {}
2095 pub mod W {}
2096 pub mod RW {
2097 #[doc = "0.5ms"]
2098 pub const CLKGATE_DELAY_0: u32 = 0;
2099 #[doc = "1.0ms"]
2100 pub const CLKGATE_DELAY_1: u32 = 0x01;
2101 #[doc = "2.0ms"]
2102 pub const CLKGATE_DELAY_2: u32 = 0x02;
2103 #[doc = "3.0ms"]
2104 pub const CLKGATE_DELAY_3: u32 = 0x03;
2105 #[doc = "4.0ms"]
2106 pub const CLKGATE_DELAY_4: u32 = 0x04;
2107 #[doc = "5.0ms"]
2108 pub const CLKGATE_DELAY_5: u32 = 0x05;
2109 #[doc = "6.0ms"]
2110 pub const CLKGATE_DELAY_6: u32 = 0x06;
2111 #[doc = "7.0ms"]
2112 pub const CLKGATE_DELAY_7: u32 = 0x07;
2113 }
2114 }
2115 #[doc = "This field indicates which chip source is being used for the rtc clock."]
2116 pub mod RTC_XTAL_SOURCE {
2117 pub const offset: u32 = 29;
2118 pub const mask: u32 = 0x01 << offset;
2119 pub mod R {}
2120 pub mod W {}
2121 pub mod RW {
2122 #[doc = "Internal ring oscillator"]
2123 pub const RTC_XTAL_SOURCE_0: u32 = 0;
2124 #[doc = "RTC_XTAL"]
2125 pub const RTC_XTAL_SOURCE_1: u32 = 0x01;
2126 }
2127 }
2128 #[doc = "This field powers down the 24M crystal oscillator if set true."]
2129 pub mod XTAL_24M_PWD {
2130 pub const offset: u32 = 30;
2131 pub const mask: u32 = 0x01 << offset;
2132 pub mod R {}
2133 pub mod W {}
2134 pub mod RW {}
2135 }
2136 #[doc = "Predivider for the source clock of the PLL's."]
2137 pub mod VID_PLL_PREDIV {
2138 pub const offset: u32 = 31;
2139 pub const mask: u32 = 0x01 << offset;
2140 pub mod R {}
2141 pub mod W {}
2142 pub mod RW {
2143 #[doc = "Divide by 1"]
2144 pub const VID_PLL_PREDIV_0: u32 = 0;
2145 #[doc = "Divide by 2"]
2146 pub const VID_PLL_PREDIV_1: u32 = 0x01;
2147 }
2148 }
2149}
2150#[doc = "Miscellaneous Register 0"]
2151pub mod MISC0_SET {
2152 #[doc = "Control bit to power-down the analog bandgap reference circuitry"]
2153 pub mod REFTOP_PWD {
2154 pub const offset: u32 = 0;
2155 pub const mask: u32 = 0x01 << offset;
2156 pub mod R {}
2157 pub mod W {}
2158 pub mod RW {}
2159 }
2160 #[doc = "Control bit to disable the self-bias circuit in the analog bandgap"]
2161 pub mod REFTOP_SELFBIASOFF {
2162 pub const offset: u32 = 3;
2163 pub const mask: u32 = 0x01 << offset;
2164 pub mod R {}
2165 pub mod W {}
2166 pub mod RW {
2167 #[doc = "Uses coarse bias currents for startup"]
2168 pub const REFTOP_SELFBIASOFF_0: u32 = 0;
2169 #[doc = "Uses bandgap-based bias currents for best performance."]
2170 pub const REFTOP_SELFBIASOFF_1: u32 = 0x01;
2171 }
2172 }
2173 #[doc = "no description available"]
2174 pub mod REFTOP_VBGADJ {
2175 pub const offset: u32 = 4;
2176 pub const mask: u32 = 0x07 << offset;
2177 pub mod R {}
2178 pub mod W {}
2179 pub mod RW {
2180 #[doc = "Nominal VBG"]
2181 pub const REFTOP_VBGADJ_0: u32 = 0;
2182 #[doc = "VBG+0.78%"]
2183 pub const REFTOP_VBGADJ_1: u32 = 0x01;
2184 #[doc = "VBG+1.56%"]
2185 pub const REFTOP_VBGADJ_2: u32 = 0x02;
2186 #[doc = "VBG+2.34%"]
2187 pub const REFTOP_VBGADJ_3: u32 = 0x03;
2188 #[doc = "VBG-0.78%"]
2189 pub const REFTOP_VBGADJ_4: u32 = 0x04;
2190 #[doc = "VBG-1.56%"]
2191 pub const REFTOP_VBGADJ_5: u32 = 0x05;
2192 #[doc = "VBG-2.34%"]
2193 pub const REFTOP_VBGADJ_6: u32 = 0x06;
2194 #[doc = "VBG-3.12%"]
2195 pub const REFTOP_VBGADJ_7: u32 = 0x07;
2196 }
2197 }
2198 #[doc = "Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable."]
2199 pub mod REFTOP_VBGUP {
2200 pub const offset: u32 = 7;
2201 pub const mask: u32 = 0x01 << offset;
2202 pub mod R {}
2203 pub mod W {}
2204 pub mod RW {}
2205 }
2206 #[doc = "Configure the analog behavior in stop mode."]
2207 pub mod STOP_MODE_CONFIG {
2208 pub const offset: u32 = 10;
2209 pub const mask: u32 = 0x03 << offset;
2210 pub mod R {}
2211 pub mod W {}
2212 pub mod RW {
2213 #[doc = "SUSPEND (DSM)"]
2214 pub const STOP_MODE_CONFIG_0: u32 = 0;
2215 #[doc = "Analog regulators are ON."]
2216 pub const STANDBY: u32 = 0x01;
2217 #[doc = "STOP (lower power)"]
2218 pub const STOP_MODE_CONFIG_2: u32 = 0x02;
2219 #[doc = "STOP (very lower power)"]
2220 pub const STOP_MODE_CONFIG_3: u32 = 0x03;
2221 }
2222 }
2223 #[doc = "This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN."]
2224 pub mod DISCON_HIGH_SNVS {
2225 pub const offset: u32 = 12;
2226 pub const mask: u32 = 0x01 << offset;
2227 pub mod R {}
2228 pub mod W {}
2229 pub mod RW {
2230 #[doc = "Turn on the switch"]
2231 pub const DISCON_HIGH_SNVS_0: u32 = 0;
2232 #[doc = "Turn off the switch"]
2233 pub const DISCON_HIGH_SNVS_1: u32 = 0x01;
2234 }
2235 }
2236 #[doc = "This field determines the bias current in the 24MHz oscillator"]
2237 pub mod OSC_I {
2238 pub const offset: u32 = 13;
2239 pub const mask: u32 = 0x03 << offset;
2240 pub mod R {}
2241 pub mod W {}
2242 pub mod RW {
2243 #[doc = "Nominal"]
2244 pub const NOMINAL: u32 = 0;
2245 #[doc = "Decrease current by 12.5%"]
2246 pub const MINUS_12_5_PERCENT: u32 = 0x01;
2247 #[doc = "Decrease current by 25.0%"]
2248 pub const MINUS_25_PERCENT: u32 = 0x02;
2249 #[doc = "Decrease current by 37.5%"]
2250 pub const MINUS_37_5_PERCENT: u32 = 0x03;
2251 }
2252 }
2253 #[doc = "Status bit that signals that the output of the 24-MHz crystal oscillator is stable"]
2254 pub mod OSC_XTALOK {
2255 pub const offset: u32 = 15;
2256 pub const mask: u32 = 0x01 << offset;
2257 pub mod R {}
2258 pub mod W {}
2259 pub mod RW {}
2260 }
2261 #[doc = "This bit enables the detector that signals when the 24MHz crystal oscillator is stable"]
2262 pub mod OSC_XTALOK_EN {
2263 pub const offset: u32 = 16;
2264 pub const mask: u32 = 0x01 << offset;
2265 pub mod R {}
2266 pub mod W {}
2267 pub mod RW {}
2268 }
2269 #[doc = "This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block"]
2270 pub mod CLKGATE_CTRL {
2271 pub const offset: u32 = 25;
2272 pub const mask: u32 = 0x01 << offset;
2273 pub mod R {}
2274 pub mod W {}
2275 pub mod RW {
2276 #[doc = "Allow the logic to automatically gate the clock when the XTAL is powered down."]
2277 pub const ALLOW_AUTO_GATE: u32 = 0;
2278 #[doc = "Prevent the logic from ever gating off the clock."]
2279 pub const NO_AUTO_GATE: u32 = 0x01;
2280 }
2281 }
2282 #[doc = "This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block"]
2283 pub mod CLKGATE_DELAY {
2284 pub const offset: u32 = 26;
2285 pub const mask: u32 = 0x07 << offset;
2286 pub mod R {}
2287 pub mod W {}
2288 pub mod RW {
2289 #[doc = "0.5ms"]
2290 pub const CLKGATE_DELAY_0: u32 = 0;
2291 #[doc = "1.0ms"]
2292 pub const CLKGATE_DELAY_1: u32 = 0x01;
2293 #[doc = "2.0ms"]
2294 pub const CLKGATE_DELAY_2: u32 = 0x02;
2295 #[doc = "3.0ms"]
2296 pub const CLKGATE_DELAY_3: u32 = 0x03;
2297 #[doc = "4.0ms"]
2298 pub const CLKGATE_DELAY_4: u32 = 0x04;
2299 #[doc = "5.0ms"]
2300 pub const CLKGATE_DELAY_5: u32 = 0x05;
2301 #[doc = "6.0ms"]
2302 pub const CLKGATE_DELAY_6: u32 = 0x06;
2303 #[doc = "7.0ms"]
2304 pub const CLKGATE_DELAY_7: u32 = 0x07;
2305 }
2306 }
2307 #[doc = "This field indicates which chip source is being used for the rtc clock."]
2308 pub mod RTC_XTAL_SOURCE {
2309 pub const offset: u32 = 29;
2310 pub const mask: u32 = 0x01 << offset;
2311 pub mod R {}
2312 pub mod W {}
2313 pub mod RW {
2314 #[doc = "Internal ring oscillator"]
2315 pub const RTC_XTAL_SOURCE_0: u32 = 0;
2316 #[doc = "RTC_XTAL"]
2317 pub const RTC_XTAL_SOURCE_1: u32 = 0x01;
2318 }
2319 }
2320 #[doc = "This field powers down the 24M crystal oscillator if set true."]
2321 pub mod XTAL_24M_PWD {
2322 pub const offset: u32 = 30;
2323 pub const mask: u32 = 0x01 << offset;
2324 pub mod R {}
2325 pub mod W {}
2326 pub mod RW {}
2327 }
2328 #[doc = "Predivider for the source clock of the PLL's."]
2329 pub mod VID_PLL_PREDIV {
2330 pub const offset: u32 = 31;
2331 pub const mask: u32 = 0x01 << offset;
2332 pub mod R {}
2333 pub mod W {}
2334 pub mod RW {
2335 #[doc = "Divide by 1"]
2336 pub const VID_PLL_PREDIV_0: u32 = 0;
2337 #[doc = "Divide by 2"]
2338 pub const VID_PLL_PREDIV_1: u32 = 0x01;
2339 }
2340 }
2341}
2342#[doc = "Miscellaneous Register 0"]
2343pub mod MISC0_CLR {
2344 #[doc = "Control bit to power-down the analog bandgap reference circuitry"]
2345 pub mod REFTOP_PWD {
2346 pub const offset: u32 = 0;
2347 pub const mask: u32 = 0x01 << offset;
2348 pub mod R {}
2349 pub mod W {}
2350 pub mod RW {}
2351 }
2352 #[doc = "Control bit to disable the self-bias circuit in the analog bandgap"]
2353 pub mod REFTOP_SELFBIASOFF {
2354 pub const offset: u32 = 3;
2355 pub const mask: u32 = 0x01 << offset;
2356 pub mod R {}
2357 pub mod W {}
2358 pub mod RW {
2359 #[doc = "Uses coarse bias currents for startup"]
2360 pub const REFTOP_SELFBIASOFF_0: u32 = 0;
2361 #[doc = "Uses bandgap-based bias currents for best performance."]
2362 pub const REFTOP_SELFBIASOFF_1: u32 = 0x01;
2363 }
2364 }
2365 #[doc = "no description available"]
2366 pub mod REFTOP_VBGADJ {
2367 pub const offset: u32 = 4;
2368 pub const mask: u32 = 0x07 << offset;
2369 pub mod R {}
2370 pub mod W {}
2371 pub mod RW {
2372 #[doc = "Nominal VBG"]
2373 pub const REFTOP_VBGADJ_0: u32 = 0;
2374 #[doc = "VBG+0.78%"]
2375 pub const REFTOP_VBGADJ_1: u32 = 0x01;
2376 #[doc = "VBG+1.56%"]
2377 pub const REFTOP_VBGADJ_2: u32 = 0x02;
2378 #[doc = "VBG+2.34%"]
2379 pub const REFTOP_VBGADJ_3: u32 = 0x03;
2380 #[doc = "VBG-0.78%"]
2381 pub const REFTOP_VBGADJ_4: u32 = 0x04;
2382 #[doc = "VBG-1.56%"]
2383 pub const REFTOP_VBGADJ_5: u32 = 0x05;
2384 #[doc = "VBG-2.34%"]
2385 pub const REFTOP_VBGADJ_6: u32 = 0x06;
2386 #[doc = "VBG-3.12%"]
2387 pub const REFTOP_VBGADJ_7: u32 = 0x07;
2388 }
2389 }
2390 #[doc = "Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable."]
2391 pub mod REFTOP_VBGUP {
2392 pub const offset: u32 = 7;
2393 pub const mask: u32 = 0x01 << offset;
2394 pub mod R {}
2395 pub mod W {}
2396 pub mod RW {}
2397 }
2398 #[doc = "Configure the analog behavior in stop mode."]
2399 pub mod STOP_MODE_CONFIG {
2400 pub const offset: u32 = 10;
2401 pub const mask: u32 = 0x03 << offset;
2402 pub mod R {}
2403 pub mod W {}
2404 pub mod RW {
2405 #[doc = "SUSPEND (DSM)"]
2406 pub const STOP_MODE_CONFIG_0: u32 = 0;
2407 #[doc = "Analog regulators are ON."]
2408 pub const STANDBY: u32 = 0x01;
2409 #[doc = "STOP (lower power)"]
2410 pub const STOP_MODE_CONFIG_2: u32 = 0x02;
2411 #[doc = "STOP (very lower power)"]
2412 pub const STOP_MODE_CONFIG_3: u32 = 0x03;
2413 }
2414 }
2415 #[doc = "This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN."]
2416 pub mod DISCON_HIGH_SNVS {
2417 pub const offset: u32 = 12;
2418 pub const mask: u32 = 0x01 << offset;
2419 pub mod R {}
2420 pub mod W {}
2421 pub mod RW {
2422 #[doc = "Turn on the switch"]
2423 pub const DISCON_HIGH_SNVS_0: u32 = 0;
2424 #[doc = "Turn off the switch"]
2425 pub const DISCON_HIGH_SNVS_1: u32 = 0x01;
2426 }
2427 }
2428 #[doc = "This field determines the bias current in the 24MHz oscillator"]
2429 pub mod OSC_I {
2430 pub const offset: u32 = 13;
2431 pub const mask: u32 = 0x03 << offset;
2432 pub mod R {}
2433 pub mod W {}
2434 pub mod RW {
2435 #[doc = "Nominal"]
2436 pub const NOMINAL: u32 = 0;
2437 #[doc = "Decrease current by 12.5%"]
2438 pub const MINUS_12_5_PERCENT: u32 = 0x01;
2439 #[doc = "Decrease current by 25.0%"]
2440 pub const MINUS_25_PERCENT: u32 = 0x02;
2441 #[doc = "Decrease current by 37.5%"]
2442 pub const MINUS_37_5_PERCENT: u32 = 0x03;
2443 }
2444 }
2445 #[doc = "Status bit that signals that the output of the 24-MHz crystal oscillator is stable"]
2446 pub mod OSC_XTALOK {
2447 pub const offset: u32 = 15;
2448 pub const mask: u32 = 0x01 << offset;
2449 pub mod R {}
2450 pub mod W {}
2451 pub mod RW {}
2452 }
2453 #[doc = "This bit enables the detector that signals when the 24MHz crystal oscillator is stable"]
2454 pub mod OSC_XTALOK_EN {
2455 pub const offset: u32 = 16;
2456 pub const mask: u32 = 0x01 << offset;
2457 pub mod R {}
2458 pub mod W {}
2459 pub mod RW {}
2460 }
2461 #[doc = "This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block"]
2462 pub mod CLKGATE_CTRL {
2463 pub const offset: u32 = 25;
2464 pub const mask: u32 = 0x01 << offset;
2465 pub mod R {}
2466 pub mod W {}
2467 pub mod RW {
2468 #[doc = "Allow the logic to automatically gate the clock when the XTAL is powered down."]
2469 pub const ALLOW_AUTO_GATE: u32 = 0;
2470 #[doc = "Prevent the logic from ever gating off the clock."]
2471 pub const NO_AUTO_GATE: u32 = 0x01;
2472 }
2473 }
2474 #[doc = "This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block"]
2475 pub mod CLKGATE_DELAY {
2476 pub const offset: u32 = 26;
2477 pub const mask: u32 = 0x07 << offset;
2478 pub mod R {}
2479 pub mod W {}
2480 pub mod RW {
2481 #[doc = "0.5ms"]
2482 pub const CLKGATE_DELAY_0: u32 = 0;
2483 #[doc = "1.0ms"]
2484 pub const CLKGATE_DELAY_1: u32 = 0x01;
2485 #[doc = "2.0ms"]
2486 pub const CLKGATE_DELAY_2: u32 = 0x02;
2487 #[doc = "3.0ms"]
2488 pub const CLKGATE_DELAY_3: u32 = 0x03;
2489 #[doc = "4.0ms"]
2490 pub const CLKGATE_DELAY_4: u32 = 0x04;
2491 #[doc = "5.0ms"]
2492 pub const CLKGATE_DELAY_5: u32 = 0x05;
2493 #[doc = "6.0ms"]
2494 pub const CLKGATE_DELAY_6: u32 = 0x06;
2495 #[doc = "7.0ms"]
2496 pub const CLKGATE_DELAY_7: u32 = 0x07;
2497 }
2498 }
2499 #[doc = "This field indicates which chip source is being used for the rtc clock."]
2500 pub mod RTC_XTAL_SOURCE {
2501 pub const offset: u32 = 29;
2502 pub const mask: u32 = 0x01 << offset;
2503 pub mod R {}
2504 pub mod W {}
2505 pub mod RW {
2506 #[doc = "Internal ring oscillator"]
2507 pub const RTC_XTAL_SOURCE_0: u32 = 0;
2508 #[doc = "RTC_XTAL"]
2509 pub const RTC_XTAL_SOURCE_1: u32 = 0x01;
2510 }
2511 }
2512 #[doc = "This field powers down the 24M crystal oscillator if set true."]
2513 pub mod XTAL_24M_PWD {
2514 pub const offset: u32 = 30;
2515 pub const mask: u32 = 0x01 << offset;
2516 pub mod R {}
2517 pub mod W {}
2518 pub mod RW {}
2519 }
2520 #[doc = "Predivider for the source clock of the PLL's."]
2521 pub mod VID_PLL_PREDIV {
2522 pub const offset: u32 = 31;
2523 pub const mask: u32 = 0x01 << offset;
2524 pub mod R {}
2525 pub mod W {}
2526 pub mod RW {
2527 #[doc = "Divide by 1"]
2528 pub const VID_PLL_PREDIV_0: u32 = 0;
2529 #[doc = "Divide by 2"]
2530 pub const VID_PLL_PREDIV_1: u32 = 0x01;
2531 }
2532 }
2533}
2534#[doc = "Miscellaneous Register 0"]
2535pub mod MISC0_TOG {
2536 #[doc = "Control bit to power-down the analog bandgap reference circuitry"]
2537 pub mod REFTOP_PWD {
2538 pub const offset: u32 = 0;
2539 pub const mask: u32 = 0x01 << offset;
2540 pub mod R {}
2541 pub mod W {}
2542 pub mod RW {}
2543 }
2544 #[doc = "Control bit to disable the self-bias circuit in the analog bandgap"]
2545 pub mod REFTOP_SELFBIASOFF {
2546 pub const offset: u32 = 3;
2547 pub const mask: u32 = 0x01 << offset;
2548 pub mod R {}
2549 pub mod W {}
2550 pub mod RW {
2551 #[doc = "Uses coarse bias currents for startup"]
2552 pub const REFTOP_SELFBIASOFF_0: u32 = 0;
2553 #[doc = "Uses bandgap-based bias currents for best performance."]
2554 pub const REFTOP_SELFBIASOFF_1: u32 = 0x01;
2555 }
2556 }
2557 #[doc = "no description available"]
2558 pub mod REFTOP_VBGADJ {
2559 pub const offset: u32 = 4;
2560 pub const mask: u32 = 0x07 << offset;
2561 pub mod R {}
2562 pub mod W {}
2563 pub mod RW {
2564 #[doc = "Nominal VBG"]
2565 pub const REFTOP_VBGADJ_0: u32 = 0;
2566 #[doc = "VBG+0.78%"]
2567 pub const REFTOP_VBGADJ_1: u32 = 0x01;
2568 #[doc = "VBG+1.56%"]
2569 pub const REFTOP_VBGADJ_2: u32 = 0x02;
2570 #[doc = "VBG+2.34%"]
2571 pub const REFTOP_VBGADJ_3: u32 = 0x03;
2572 #[doc = "VBG-0.78%"]
2573 pub const REFTOP_VBGADJ_4: u32 = 0x04;
2574 #[doc = "VBG-1.56%"]
2575 pub const REFTOP_VBGADJ_5: u32 = 0x05;
2576 #[doc = "VBG-2.34%"]
2577 pub const REFTOP_VBGADJ_6: u32 = 0x06;
2578 #[doc = "VBG-3.12%"]
2579 pub const REFTOP_VBGADJ_7: u32 = 0x07;
2580 }
2581 }
2582 #[doc = "Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable."]
2583 pub mod REFTOP_VBGUP {
2584 pub const offset: u32 = 7;
2585 pub const mask: u32 = 0x01 << offset;
2586 pub mod R {}
2587 pub mod W {}
2588 pub mod RW {}
2589 }
2590 #[doc = "Configure the analog behavior in stop mode."]
2591 pub mod STOP_MODE_CONFIG {
2592 pub const offset: u32 = 10;
2593 pub const mask: u32 = 0x03 << offset;
2594 pub mod R {}
2595 pub mod W {}
2596 pub mod RW {
2597 #[doc = "SUSPEND (DSM)"]
2598 pub const STOP_MODE_CONFIG_0: u32 = 0;
2599 #[doc = "Analog regulators are ON."]
2600 pub const STANDBY: u32 = 0x01;
2601 #[doc = "STOP (lower power)"]
2602 pub const STOP_MODE_CONFIG_2: u32 = 0x02;
2603 #[doc = "STOP (very lower power)"]
2604 pub const STOP_MODE_CONFIG_3: u32 = 0x03;
2605 }
2606 }
2607 #[doc = "This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN."]
2608 pub mod DISCON_HIGH_SNVS {
2609 pub const offset: u32 = 12;
2610 pub const mask: u32 = 0x01 << offset;
2611 pub mod R {}
2612 pub mod W {}
2613 pub mod RW {
2614 #[doc = "Turn on the switch"]
2615 pub const DISCON_HIGH_SNVS_0: u32 = 0;
2616 #[doc = "Turn off the switch"]
2617 pub const DISCON_HIGH_SNVS_1: u32 = 0x01;
2618 }
2619 }
2620 #[doc = "This field determines the bias current in the 24MHz oscillator"]
2621 pub mod OSC_I {
2622 pub const offset: u32 = 13;
2623 pub const mask: u32 = 0x03 << offset;
2624 pub mod R {}
2625 pub mod W {}
2626 pub mod RW {
2627 #[doc = "Nominal"]
2628 pub const NOMINAL: u32 = 0;
2629 #[doc = "Decrease current by 12.5%"]
2630 pub const MINUS_12_5_PERCENT: u32 = 0x01;
2631 #[doc = "Decrease current by 25.0%"]
2632 pub const MINUS_25_PERCENT: u32 = 0x02;
2633 #[doc = "Decrease current by 37.5%"]
2634 pub const MINUS_37_5_PERCENT: u32 = 0x03;
2635 }
2636 }
2637 #[doc = "Status bit that signals that the output of the 24-MHz crystal oscillator is stable"]
2638 pub mod OSC_XTALOK {
2639 pub const offset: u32 = 15;
2640 pub const mask: u32 = 0x01 << offset;
2641 pub mod R {}
2642 pub mod W {}
2643 pub mod RW {}
2644 }
2645 #[doc = "This bit enables the detector that signals when the 24MHz crystal oscillator is stable"]
2646 pub mod OSC_XTALOK_EN {
2647 pub const offset: u32 = 16;
2648 pub const mask: u32 = 0x01 << offset;
2649 pub mod R {}
2650 pub mod W {}
2651 pub mod RW {}
2652 }
2653 #[doc = "This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block"]
2654 pub mod CLKGATE_CTRL {
2655 pub const offset: u32 = 25;
2656 pub const mask: u32 = 0x01 << offset;
2657 pub mod R {}
2658 pub mod W {}
2659 pub mod RW {
2660 #[doc = "Allow the logic to automatically gate the clock when the XTAL is powered down."]
2661 pub const ALLOW_AUTO_GATE: u32 = 0;
2662 #[doc = "Prevent the logic from ever gating off the clock."]
2663 pub const NO_AUTO_GATE: u32 = 0x01;
2664 }
2665 }
2666 #[doc = "This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block"]
2667 pub mod CLKGATE_DELAY {
2668 pub const offset: u32 = 26;
2669 pub const mask: u32 = 0x07 << offset;
2670 pub mod R {}
2671 pub mod W {}
2672 pub mod RW {
2673 #[doc = "0.5ms"]
2674 pub const CLKGATE_DELAY_0: u32 = 0;
2675 #[doc = "1.0ms"]
2676 pub const CLKGATE_DELAY_1: u32 = 0x01;
2677 #[doc = "2.0ms"]
2678 pub const CLKGATE_DELAY_2: u32 = 0x02;
2679 #[doc = "3.0ms"]
2680 pub const CLKGATE_DELAY_3: u32 = 0x03;
2681 #[doc = "4.0ms"]
2682 pub const CLKGATE_DELAY_4: u32 = 0x04;
2683 #[doc = "5.0ms"]
2684 pub const CLKGATE_DELAY_5: u32 = 0x05;
2685 #[doc = "6.0ms"]
2686 pub const CLKGATE_DELAY_6: u32 = 0x06;
2687 #[doc = "7.0ms"]
2688 pub const CLKGATE_DELAY_7: u32 = 0x07;
2689 }
2690 }
2691 #[doc = "This field indicates which chip source is being used for the rtc clock."]
2692 pub mod RTC_XTAL_SOURCE {
2693 pub const offset: u32 = 29;
2694 pub const mask: u32 = 0x01 << offset;
2695 pub mod R {}
2696 pub mod W {}
2697 pub mod RW {
2698 #[doc = "Internal ring oscillator"]
2699 pub const RTC_XTAL_SOURCE_0: u32 = 0;
2700 #[doc = "RTC_XTAL"]
2701 pub const RTC_XTAL_SOURCE_1: u32 = 0x01;
2702 }
2703 }
2704 #[doc = "This field powers down the 24M crystal oscillator if set true."]
2705 pub mod XTAL_24M_PWD {
2706 pub const offset: u32 = 30;
2707 pub const mask: u32 = 0x01 << offset;
2708 pub mod R {}
2709 pub mod W {}
2710 pub mod RW {}
2711 }
2712 #[doc = "Predivider for the source clock of the PLL's."]
2713 pub mod VID_PLL_PREDIV {
2714 pub const offset: u32 = 31;
2715 pub const mask: u32 = 0x01 << offset;
2716 pub mod R {}
2717 pub mod W {}
2718 pub mod RW {
2719 #[doc = "Divide by 1"]
2720 pub const VID_PLL_PREDIV_0: u32 = 0;
2721 #[doc = "Divide by 2"]
2722 pub const VID_PLL_PREDIV_1: u32 = 0x01;
2723 }
2724 }
2725}
2726#[doc = "Miscellaneous Register 1"]
2727pub mod MISC1 {
2728 #[doc = "This field selects the clk to be routed to anaclk1/1b.Not related to PMU."]
2729 pub mod LVDS1_CLK_SEL {
2730 pub const offset: u32 = 0;
2731 pub const mask: u32 = 0x1f << offset;
2732 pub mod R {}
2733 pub mod W {}
2734 pub mod RW {
2735 #[doc = "Arm PLL"]
2736 pub const ARM_PLL: u32 = 0;
2737 #[doc = "System PLL"]
2738 pub const SYS_PLL: u32 = 0x01;
2739 #[doc = "ref_pfd4_clk == pll2_pfd0_clk"]
2740 pub const PFD4: u32 = 0x02;
2741 #[doc = "ref_pfd5_clk == pll2_pfd1_clk"]
2742 pub const PFD5: u32 = 0x03;
2743 #[doc = "ref_pfd6_clk == pll2_pfd2_clk"]
2744 pub const PFD6: u32 = 0x04;
2745 #[doc = "ref_pfd7_clk == pll2_pfd3_clk"]
2746 pub const PFD7: u32 = 0x05;
2747 #[doc = "Audio PLL"]
2748 pub const AUDIO_PLL: u32 = 0x06;
2749 #[doc = "Video PLL"]
2750 pub const VIDEO_PLL: u32 = 0x07;
2751 #[doc = "ethernet ref clock (ENET_PLL)"]
2752 pub const ETHERNET_REF: u32 = 0x09;
2753 #[doc = "USB1 PLL clock"]
2754 pub const USB1_PLL: u32 = 0x0c;
2755 #[doc = "USB2 PLL clock"]
2756 pub const USB2_PLL: u32 = 0x0d;
2757 #[doc = "ref_pfd0_clk == pll3_pfd0_clk"]
2758 pub const PFD0: u32 = 0x0e;
2759 #[doc = "ref_pfd1_clk == pll3_pfd1_clk"]
2760 pub const PFD1: u32 = 0x0f;
2761 #[doc = "ref_pfd2_clk == pll3_pfd2_clk"]
2762 pub const PFD2: u32 = 0x10;
2763 #[doc = "ref_pfd3_clk == pll3_pfd3_clk"]
2764 pub const PFD3: u32 = 0x11;
2765 #[doc = "xtal (24M)"]
2766 pub const XTAL: u32 = 0x12;
2767 }
2768 }
2769 #[doc = "This field selects the clk to be routed to anaclk2/2b.Not related to PMU."]
2770 pub mod LVDS2_CLK_SEL {
2771 pub const offset: u32 = 5;
2772 pub const mask: u32 = 0x1f << offset;
2773 pub mod R {}
2774 pub mod W {}
2775 pub mod RW {
2776 #[doc = "Arm PLL"]
2777 pub const ARM_PLL: u32 = 0;
2778 #[doc = "System PLL"]
2779 pub const SYS_PLL: u32 = 0x01;
2780 #[doc = "ref_pfd4_clk == pll2_pfd0_clk"]
2781 pub const PFD4: u32 = 0x02;
2782 #[doc = "ref_pfd5_clk == pll2_pfd1_clk"]
2783 pub const PFD5: u32 = 0x03;
2784 #[doc = "ref_pfd6_clk == pll2_pfd2_clk"]
2785 pub const PFD6: u32 = 0x04;
2786 #[doc = "ref_pfd7_clk == pll2_pfd3_clk"]
2787 pub const PFD7: u32 = 0x05;
2788 #[doc = "Audio PLL"]
2789 pub const AUDIO_PLL: u32 = 0x06;
2790 #[doc = "Video PLL"]
2791 pub const VIDEO_PLL: u32 = 0x07;
2792 #[doc = "MLB PLL"]
2793 pub const MLB_PLL: u32 = 0x08;
2794 #[doc = "ethernet ref clock (ENET_PLL)"]
2795 pub const ETHERNET_REF: u32 = 0x09;
2796 #[doc = "PCIe ref clock (125M)"]
2797 pub const PCIE_REF: u32 = 0x0a;
2798 #[doc = "SATA ref clock (100M)"]
2799 pub const SATA_REF: u32 = 0x0b;
2800 #[doc = "USB1 PLL clock"]
2801 pub const USB1_PLL: u32 = 0x0c;
2802 #[doc = "USB2 PLL clock"]
2803 pub const USB2_PLL: u32 = 0x0d;
2804 #[doc = "ref_pfd0_clk == pll3_pfd0_clk"]
2805 pub const PFD0: u32 = 0x0e;
2806 #[doc = "ref_pfd1_clk == pll3_pfd1_clk"]
2807 pub const PFD1: u32 = 0x0f;
2808 #[doc = "ref_pfd2_clk == pll3_pfd2_clk"]
2809 pub const PFD2: u32 = 0x10;
2810 #[doc = "ref_pfd3_clk == pll3_pfd3_clk"]
2811 pub const PFD3: u32 = 0x11;
2812 #[doc = "xtal (24M)"]
2813 pub const XTAL: u32 = 0x12;
2814 #[doc = "LVDS1 (loopback)"]
2815 pub const LVDS1: u32 = 0x13;
2816 #[doc = "LVDS2 (not useful)"]
2817 pub const LVDS2: u32 = 0x14;
2818 }
2819 }
2820 #[doc = "This enables the LVDS output buffer for anaclk1/1b"]
2821 pub mod LVDSCLK1_OBEN {
2822 pub const offset: u32 = 10;
2823 pub const mask: u32 = 0x01 << offset;
2824 pub mod R {}
2825 pub mod W {}
2826 pub mod RW {}
2827 }
2828 #[doc = "This enables the LVDS output buffer for anaclk2/2b"]
2829 pub mod LVDSCLK2_OBEN {
2830 pub const offset: u32 = 11;
2831 pub const mask: u32 = 0x01 << offset;
2832 pub mod R {}
2833 pub mod W {}
2834 pub mod RW {}
2835 }
2836 #[doc = "This enables the LVDS input buffer for anaclk1/1b"]
2837 pub mod LVDSCLK1_IBEN {
2838 pub const offset: u32 = 12;
2839 pub const mask: u32 = 0x01 << offset;
2840 pub mod R {}
2841 pub mod W {}
2842 pub mod RW {}
2843 }
2844 #[doc = "This enables the LVDS input buffer for anaclk2/2b"]
2845 pub mod LVDSCLK2_IBEN {
2846 pub const offset: u32 = 13;
2847 pub const mask: u32 = 0x01 << offset;
2848 pub mod R {}
2849 pub mod W {}
2850 pub mod RW {}
2851 }
2852 #[doc = "This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off"]
2853 pub mod PFD_480_AUTOGATE_EN {
2854 pub const offset: u32 = 16;
2855 pub const mask: u32 = 0x01 << offset;
2856 pub mod R {}
2857 pub mod W {}
2858 pub mod RW {}
2859 }
2860 #[doc = "This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off"]
2861 pub mod PFD_528_AUTOGATE_EN {
2862 pub const offset: u32 = 17;
2863 pub const mask: u32 = 0x01 << offset;
2864 pub mod R {}
2865 pub mod W {}
2866 pub mod RW {}
2867 }
2868 #[doc = "This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature"]
2869 pub mod IRQ_TEMPPANIC {
2870 pub const offset: u32 = 27;
2871 pub const mask: u32 = 0x01 << offset;
2872 pub mod R {}
2873 pub mod W {}
2874 pub mod RW {}
2875 }
2876 #[doc = "This status bit is set to one when the temperature sensor low interrupt asserts for low temperature"]
2877 pub mod IRQ_TEMPLOW {
2878 pub const offset: u32 = 28;
2879 pub const mask: u32 = 0x01 << offset;
2880 pub mod R {}
2881 pub mod W {}
2882 pub mod RW {}
2883 }
2884 #[doc = "This status bit is set to one when the temperature sensor high interrupt asserts for high temperature"]
2885 pub mod IRQ_TEMPHIGH {
2886 pub const offset: u32 = 29;
2887 pub const mask: u32 = 0x01 << offset;
2888 pub mod R {}
2889 pub mod W {}
2890 pub mod RW {}
2891 }
2892 #[doc = "This status bit is set to one when when any of the analog regulator brownout interrupts assert"]
2893 pub mod IRQ_ANA_BO {
2894 pub const offset: u32 = 30;
2895 pub const mask: u32 = 0x01 << offset;
2896 pub mod R {}
2897 pub mod W {}
2898 pub mod RW {}
2899 }
2900 #[doc = "This status bit is set to one when when any of the digital regulator brownout interrupts assert"]
2901 pub mod IRQ_DIG_BO {
2902 pub const offset: u32 = 31;
2903 pub const mask: u32 = 0x01 << offset;
2904 pub mod R {}
2905 pub mod W {}
2906 pub mod RW {}
2907 }
2908}
2909#[doc = "Miscellaneous Register 1"]
2910pub mod MISC1_SET {
2911 #[doc = "This field selects the clk to be routed to anaclk1/1b.Not related to PMU."]
2912 pub mod LVDS1_CLK_SEL {
2913 pub const offset: u32 = 0;
2914 pub const mask: u32 = 0x1f << offset;
2915 pub mod R {}
2916 pub mod W {}
2917 pub mod RW {
2918 #[doc = "Arm PLL"]
2919 pub const ARM_PLL: u32 = 0;
2920 #[doc = "System PLL"]
2921 pub const SYS_PLL: u32 = 0x01;
2922 #[doc = "ref_pfd4_clk == pll2_pfd0_clk"]
2923 pub const PFD4: u32 = 0x02;
2924 #[doc = "ref_pfd5_clk == pll2_pfd1_clk"]
2925 pub const PFD5: u32 = 0x03;
2926 #[doc = "ref_pfd6_clk == pll2_pfd2_clk"]
2927 pub const PFD6: u32 = 0x04;
2928 #[doc = "ref_pfd7_clk == pll2_pfd3_clk"]
2929 pub const PFD7: u32 = 0x05;
2930 #[doc = "Audio PLL"]
2931 pub const AUDIO_PLL: u32 = 0x06;
2932 #[doc = "Video PLL"]
2933 pub const VIDEO_PLL: u32 = 0x07;
2934 #[doc = "ethernet ref clock (ENET_PLL)"]
2935 pub const ETHERNET_REF: u32 = 0x09;
2936 #[doc = "USB1 PLL clock"]
2937 pub const USB1_PLL: u32 = 0x0c;
2938 #[doc = "USB2 PLL clock"]
2939 pub const USB2_PLL: u32 = 0x0d;
2940 #[doc = "ref_pfd0_clk == pll3_pfd0_clk"]
2941 pub const PFD0: u32 = 0x0e;
2942 #[doc = "ref_pfd1_clk == pll3_pfd1_clk"]
2943 pub const PFD1: u32 = 0x0f;
2944 #[doc = "ref_pfd2_clk == pll3_pfd2_clk"]
2945 pub const PFD2: u32 = 0x10;
2946 #[doc = "ref_pfd3_clk == pll3_pfd3_clk"]
2947 pub const PFD3: u32 = 0x11;
2948 #[doc = "xtal (24M)"]
2949 pub const XTAL: u32 = 0x12;
2950 }
2951 }
2952 #[doc = "This field selects the clk to be routed to anaclk2/2b.Not related to PMU."]
2953 pub mod LVDS2_CLK_SEL {
2954 pub const offset: u32 = 5;
2955 pub const mask: u32 = 0x1f << offset;
2956 pub mod R {}
2957 pub mod W {}
2958 pub mod RW {
2959 #[doc = "Arm PLL"]
2960 pub const ARM_PLL: u32 = 0;
2961 #[doc = "System PLL"]
2962 pub const SYS_PLL: u32 = 0x01;
2963 #[doc = "ref_pfd4_clk == pll2_pfd0_clk"]
2964 pub const PFD4: u32 = 0x02;
2965 #[doc = "ref_pfd5_clk == pll2_pfd1_clk"]
2966 pub const PFD5: u32 = 0x03;
2967 #[doc = "ref_pfd6_clk == pll2_pfd2_clk"]
2968 pub const PFD6: u32 = 0x04;
2969 #[doc = "ref_pfd7_clk == pll2_pfd3_clk"]
2970 pub const PFD7: u32 = 0x05;
2971 #[doc = "Audio PLL"]
2972 pub const AUDIO_PLL: u32 = 0x06;
2973 #[doc = "Video PLL"]
2974 pub const VIDEO_PLL: u32 = 0x07;
2975 #[doc = "MLB PLL"]
2976 pub const MLB_PLL: u32 = 0x08;
2977 #[doc = "ethernet ref clock (ENET_PLL)"]
2978 pub const ETHERNET_REF: u32 = 0x09;
2979 #[doc = "PCIe ref clock (125M)"]
2980 pub const PCIE_REF: u32 = 0x0a;
2981 #[doc = "SATA ref clock (100M)"]
2982 pub const SATA_REF: u32 = 0x0b;
2983 #[doc = "USB1 PLL clock"]
2984 pub const USB1_PLL: u32 = 0x0c;
2985 #[doc = "USB2 PLL clock"]
2986 pub const USB2_PLL: u32 = 0x0d;
2987 #[doc = "ref_pfd0_clk == pll3_pfd0_clk"]
2988 pub const PFD0: u32 = 0x0e;
2989 #[doc = "ref_pfd1_clk == pll3_pfd1_clk"]
2990 pub const PFD1: u32 = 0x0f;
2991 #[doc = "ref_pfd2_clk == pll3_pfd2_clk"]
2992 pub const PFD2: u32 = 0x10;
2993 #[doc = "ref_pfd3_clk == pll3_pfd3_clk"]
2994 pub const PFD3: u32 = 0x11;
2995 #[doc = "xtal (24M)"]
2996 pub const XTAL: u32 = 0x12;
2997 #[doc = "LVDS1 (loopback)"]
2998 pub const LVDS1: u32 = 0x13;
2999 #[doc = "LVDS2 (not useful)"]
3000 pub const LVDS2: u32 = 0x14;
3001 }
3002 }
3003 #[doc = "This enables the LVDS output buffer for anaclk1/1b"]
3004 pub mod LVDSCLK1_OBEN {
3005 pub const offset: u32 = 10;
3006 pub const mask: u32 = 0x01 << offset;
3007 pub mod R {}
3008 pub mod W {}
3009 pub mod RW {}
3010 }
3011 #[doc = "This enables the LVDS output buffer for anaclk2/2b"]
3012 pub mod LVDSCLK2_OBEN {
3013 pub const offset: u32 = 11;
3014 pub const mask: u32 = 0x01 << offset;
3015 pub mod R {}
3016 pub mod W {}
3017 pub mod RW {}
3018 }
3019 #[doc = "This enables the LVDS input buffer for anaclk1/1b"]
3020 pub mod LVDSCLK1_IBEN {
3021 pub const offset: u32 = 12;
3022 pub const mask: u32 = 0x01 << offset;
3023 pub mod R {}
3024 pub mod W {}
3025 pub mod RW {}
3026 }
3027 #[doc = "This enables the LVDS input buffer for anaclk2/2b"]
3028 pub mod LVDSCLK2_IBEN {
3029 pub const offset: u32 = 13;
3030 pub const mask: u32 = 0x01 << offset;
3031 pub mod R {}
3032 pub mod W {}
3033 pub mod RW {}
3034 }
3035 #[doc = "This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off"]
3036 pub mod PFD_480_AUTOGATE_EN {
3037 pub const offset: u32 = 16;
3038 pub const mask: u32 = 0x01 << offset;
3039 pub mod R {}
3040 pub mod W {}
3041 pub mod RW {}
3042 }
3043 #[doc = "This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off"]
3044 pub mod PFD_528_AUTOGATE_EN {
3045 pub const offset: u32 = 17;
3046 pub const mask: u32 = 0x01 << offset;
3047 pub mod R {}
3048 pub mod W {}
3049 pub mod RW {}
3050 }
3051 #[doc = "This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature"]
3052 pub mod IRQ_TEMPPANIC {
3053 pub const offset: u32 = 27;
3054 pub const mask: u32 = 0x01 << offset;
3055 pub mod R {}
3056 pub mod W {}
3057 pub mod RW {}
3058 }
3059 #[doc = "This status bit is set to one when the temperature sensor low interrupt asserts for low temperature"]
3060 pub mod IRQ_TEMPLOW {
3061 pub const offset: u32 = 28;
3062 pub const mask: u32 = 0x01 << offset;
3063 pub mod R {}
3064 pub mod W {}
3065 pub mod RW {}
3066 }
3067 #[doc = "This status bit is set to one when the temperature sensor high interrupt asserts for high temperature"]
3068 pub mod IRQ_TEMPHIGH {
3069 pub const offset: u32 = 29;
3070 pub const mask: u32 = 0x01 << offset;
3071 pub mod R {}
3072 pub mod W {}
3073 pub mod RW {}
3074 }
3075 #[doc = "This status bit is set to one when when any of the analog regulator brownout interrupts assert"]
3076 pub mod IRQ_ANA_BO {
3077 pub const offset: u32 = 30;
3078 pub const mask: u32 = 0x01 << offset;
3079 pub mod R {}
3080 pub mod W {}
3081 pub mod RW {}
3082 }
3083 #[doc = "This status bit is set to one when when any of the digital regulator brownout interrupts assert"]
3084 pub mod IRQ_DIG_BO {
3085 pub const offset: u32 = 31;
3086 pub const mask: u32 = 0x01 << offset;
3087 pub mod R {}
3088 pub mod W {}
3089 pub mod RW {}
3090 }
3091}
3092#[doc = "Miscellaneous Register 1"]
3093pub mod MISC1_CLR {
3094 #[doc = "This field selects the clk to be routed to anaclk1/1b.Not related to PMU."]
3095 pub mod LVDS1_CLK_SEL {
3096 pub const offset: u32 = 0;
3097 pub const mask: u32 = 0x1f << offset;
3098 pub mod R {}
3099 pub mod W {}
3100 pub mod RW {
3101 #[doc = "Arm PLL"]
3102 pub const ARM_PLL: u32 = 0;
3103 #[doc = "System PLL"]
3104 pub const SYS_PLL: u32 = 0x01;
3105 #[doc = "ref_pfd4_clk == pll2_pfd0_clk"]
3106 pub const PFD4: u32 = 0x02;
3107 #[doc = "ref_pfd5_clk == pll2_pfd1_clk"]
3108 pub const PFD5: u32 = 0x03;
3109 #[doc = "ref_pfd6_clk == pll2_pfd2_clk"]
3110 pub const PFD6: u32 = 0x04;
3111 #[doc = "ref_pfd7_clk == pll2_pfd3_clk"]
3112 pub const PFD7: u32 = 0x05;
3113 #[doc = "Audio PLL"]
3114 pub const AUDIO_PLL: u32 = 0x06;
3115 #[doc = "Video PLL"]
3116 pub const VIDEO_PLL: u32 = 0x07;
3117 #[doc = "ethernet ref clock (ENET_PLL)"]
3118 pub const ETHERNET_REF: u32 = 0x09;
3119 #[doc = "USB1 PLL clock"]
3120 pub const USB1_PLL: u32 = 0x0c;
3121 #[doc = "USB2 PLL clock"]
3122 pub const USB2_PLL: u32 = 0x0d;
3123 #[doc = "ref_pfd0_clk == pll3_pfd0_clk"]
3124 pub const PFD0: u32 = 0x0e;
3125 #[doc = "ref_pfd1_clk == pll3_pfd1_clk"]
3126 pub const PFD1: u32 = 0x0f;
3127 #[doc = "ref_pfd2_clk == pll3_pfd2_clk"]
3128 pub const PFD2: u32 = 0x10;
3129 #[doc = "ref_pfd3_clk == pll3_pfd3_clk"]
3130 pub const PFD3: u32 = 0x11;
3131 #[doc = "xtal (24M)"]
3132 pub const XTAL: u32 = 0x12;
3133 }
3134 }
3135 #[doc = "This field selects the clk to be routed to anaclk2/2b.Not related to PMU."]
3136 pub mod LVDS2_CLK_SEL {
3137 pub const offset: u32 = 5;
3138 pub const mask: u32 = 0x1f << offset;
3139 pub mod R {}
3140 pub mod W {}
3141 pub mod RW {
3142 #[doc = "Arm PLL"]
3143 pub const ARM_PLL: u32 = 0;
3144 #[doc = "System PLL"]
3145 pub const SYS_PLL: u32 = 0x01;
3146 #[doc = "ref_pfd4_clk == pll2_pfd0_clk"]
3147 pub const PFD4: u32 = 0x02;
3148 #[doc = "ref_pfd5_clk == pll2_pfd1_clk"]
3149 pub const PFD5: u32 = 0x03;
3150 #[doc = "ref_pfd6_clk == pll2_pfd2_clk"]
3151 pub const PFD6: u32 = 0x04;
3152 #[doc = "ref_pfd7_clk == pll2_pfd3_clk"]
3153 pub const PFD7: u32 = 0x05;
3154 #[doc = "Audio PLL"]
3155 pub const AUDIO_PLL: u32 = 0x06;
3156 #[doc = "Video PLL"]
3157 pub const VIDEO_PLL: u32 = 0x07;
3158 #[doc = "MLB PLL"]
3159 pub const MLB_PLL: u32 = 0x08;
3160 #[doc = "ethernet ref clock (ENET_PLL)"]
3161 pub const ETHERNET_REF: u32 = 0x09;
3162 #[doc = "PCIe ref clock (125M)"]
3163 pub const PCIE_REF: u32 = 0x0a;
3164 #[doc = "SATA ref clock (100M)"]
3165 pub const SATA_REF: u32 = 0x0b;
3166 #[doc = "USB1 PLL clock"]
3167 pub const USB1_PLL: u32 = 0x0c;
3168 #[doc = "USB2 PLL clock"]
3169 pub const USB2_PLL: u32 = 0x0d;
3170 #[doc = "ref_pfd0_clk == pll3_pfd0_clk"]
3171 pub const PFD0: u32 = 0x0e;
3172 #[doc = "ref_pfd1_clk == pll3_pfd1_clk"]
3173 pub const PFD1: u32 = 0x0f;
3174 #[doc = "ref_pfd2_clk == pll3_pfd2_clk"]
3175 pub const PFD2: u32 = 0x10;
3176 #[doc = "ref_pfd3_clk == pll3_pfd3_clk"]
3177 pub const PFD3: u32 = 0x11;
3178 #[doc = "xtal (24M)"]
3179 pub const XTAL: u32 = 0x12;
3180 #[doc = "LVDS1 (loopback)"]
3181 pub const LVDS1: u32 = 0x13;
3182 #[doc = "LVDS2 (not useful)"]
3183 pub const LVDS2: u32 = 0x14;
3184 }
3185 }
3186 #[doc = "This enables the LVDS output buffer for anaclk1/1b"]
3187 pub mod LVDSCLK1_OBEN {
3188 pub const offset: u32 = 10;
3189 pub const mask: u32 = 0x01 << offset;
3190 pub mod R {}
3191 pub mod W {}
3192 pub mod RW {}
3193 }
3194 #[doc = "This enables the LVDS output buffer for anaclk2/2b"]
3195 pub mod LVDSCLK2_OBEN {
3196 pub const offset: u32 = 11;
3197 pub const mask: u32 = 0x01 << offset;
3198 pub mod R {}
3199 pub mod W {}
3200 pub mod RW {}
3201 }
3202 #[doc = "This enables the LVDS input buffer for anaclk1/1b"]
3203 pub mod LVDSCLK1_IBEN {
3204 pub const offset: u32 = 12;
3205 pub const mask: u32 = 0x01 << offset;
3206 pub mod R {}
3207 pub mod W {}
3208 pub mod RW {}
3209 }
3210 #[doc = "This enables the LVDS input buffer for anaclk2/2b"]
3211 pub mod LVDSCLK2_IBEN {
3212 pub const offset: u32 = 13;
3213 pub const mask: u32 = 0x01 << offset;
3214 pub mod R {}
3215 pub mod W {}
3216 pub mod RW {}
3217 }
3218 #[doc = "This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off"]
3219 pub mod PFD_480_AUTOGATE_EN {
3220 pub const offset: u32 = 16;
3221 pub const mask: u32 = 0x01 << offset;
3222 pub mod R {}
3223 pub mod W {}
3224 pub mod RW {}
3225 }
3226 #[doc = "This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off"]
3227 pub mod PFD_528_AUTOGATE_EN {
3228 pub const offset: u32 = 17;
3229 pub const mask: u32 = 0x01 << offset;
3230 pub mod R {}
3231 pub mod W {}
3232 pub mod RW {}
3233 }
3234 #[doc = "This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature"]
3235 pub mod IRQ_TEMPPANIC {
3236 pub const offset: u32 = 27;
3237 pub const mask: u32 = 0x01 << offset;
3238 pub mod R {}
3239 pub mod W {}
3240 pub mod RW {}
3241 }
3242 #[doc = "This status bit is set to one when the temperature sensor low interrupt asserts for low temperature"]
3243 pub mod IRQ_TEMPLOW {
3244 pub const offset: u32 = 28;
3245 pub const mask: u32 = 0x01 << offset;
3246 pub mod R {}
3247 pub mod W {}
3248 pub mod RW {}
3249 }
3250 #[doc = "This status bit is set to one when the temperature sensor high interrupt asserts for high temperature"]
3251 pub mod IRQ_TEMPHIGH {
3252 pub const offset: u32 = 29;
3253 pub const mask: u32 = 0x01 << offset;
3254 pub mod R {}
3255 pub mod W {}
3256 pub mod RW {}
3257 }
3258 #[doc = "This status bit is set to one when when any of the analog regulator brownout interrupts assert"]
3259 pub mod IRQ_ANA_BO {
3260 pub const offset: u32 = 30;
3261 pub const mask: u32 = 0x01 << offset;
3262 pub mod R {}
3263 pub mod W {}
3264 pub mod RW {}
3265 }
3266 #[doc = "This status bit is set to one when when any of the digital regulator brownout interrupts assert"]
3267 pub mod IRQ_DIG_BO {
3268 pub const offset: u32 = 31;
3269 pub const mask: u32 = 0x01 << offset;
3270 pub mod R {}
3271 pub mod W {}
3272 pub mod RW {}
3273 }
3274}
3275#[doc = "Miscellaneous Register 1"]
3276pub mod MISC1_TOG {
3277 #[doc = "This field selects the clk to be routed to anaclk1/1b.Not related to PMU."]
3278 pub mod LVDS1_CLK_SEL {
3279 pub const offset: u32 = 0;
3280 pub const mask: u32 = 0x1f << offset;
3281 pub mod R {}
3282 pub mod W {}
3283 pub mod RW {
3284 #[doc = "Arm PLL"]
3285 pub const ARM_PLL: u32 = 0;
3286 #[doc = "System PLL"]
3287 pub const SYS_PLL: u32 = 0x01;
3288 #[doc = "ref_pfd4_clk == pll2_pfd0_clk"]
3289 pub const PFD4: u32 = 0x02;
3290 #[doc = "ref_pfd5_clk == pll2_pfd1_clk"]
3291 pub const PFD5: u32 = 0x03;
3292 #[doc = "ref_pfd6_clk == pll2_pfd2_clk"]
3293 pub const PFD6: u32 = 0x04;
3294 #[doc = "ref_pfd7_clk == pll2_pfd3_clk"]
3295 pub const PFD7: u32 = 0x05;
3296 #[doc = "Audio PLL"]
3297 pub const AUDIO_PLL: u32 = 0x06;
3298 #[doc = "Video PLL"]
3299 pub const VIDEO_PLL: u32 = 0x07;
3300 #[doc = "ethernet ref clock (ENET_PLL)"]
3301 pub const ETHERNET_REF: u32 = 0x09;
3302 #[doc = "USB1 PLL clock"]
3303 pub const USB1_PLL: u32 = 0x0c;
3304 #[doc = "USB2 PLL clock"]
3305 pub const USB2_PLL: u32 = 0x0d;
3306 #[doc = "ref_pfd0_clk == pll3_pfd0_clk"]
3307 pub const PFD0: u32 = 0x0e;
3308 #[doc = "ref_pfd1_clk == pll3_pfd1_clk"]
3309 pub const PFD1: u32 = 0x0f;
3310 #[doc = "ref_pfd2_clk == pll3_pfd2_clk"]
3311 pub const PFD2: u32 = 0x10;
3312 #[doc = "ref_pfd3_clk == pll3_pfd3_clk"]
3313 pub const PFD3: u32 = 0x11;
3314 #[doc = "xtal (24M)"]
3315 pub const XTAL: u32 = 0x12;
3316 }
3317 }
3318 #[doc = "This field selects the clk to be routed to anaclk2/2b.Not related to PMU."]
3319 pub mod LVDS2_CLK_SEL {
3320 pub const offset: u32 = 5;
3321 pub const mask: u32 = 0x1f << offset;
3322 pub mod R {}
3323 pub mod W {}
3324 pub mod RW {
3325 #[doc = "Arm PLL"]
3326 pub const ARM_PLL: u32 = 0;
3327 #[doc = "System PLL"]
3328 pub const SYS_PLL: u32 = 0x01;
3329 #[doc = "ref_pfd4_clk == pll2_pfd0_clk"]
3330 pub const PFD4: u32 = 0x02;
3331 #[doc = "ref_pfd5_clk == pll2_pfd1_clk"]
3332 pub const PFD5: u32 = 0x03;
3333 #[doc = "ref_pfd6_clk == pll2_pfd2_clk"]
3334 pub const PFD6: u32 = 0x04;
3335 #[doc = "ref_pfd7_clk == pll2_pfd3_clk"]
3336 pub const PFD7: u32 = 0x05;
3337 #[doc = "Audio PLL"]
3338 pub const AUDIO_PLL: u32 = 0x06;
3339 #[doc = "Video PLL"]
3340 pub const VIDEO_PLL: u32 = 0x07;
3341 #[doc = "MLB PLL"]
3342 pub const MLB_PLL: u32 = 0x08;
3343 #[doc = "ethernet ref clock (ENET_PLL)"]
3344 pub const ETHERNET_REF: u32 = 0x09;
3345 #[doc = "PCIe ref clock (125M)"]
3346 pub const PCIE_REF: u32 = 0x0a;
3347 #[doc = "SATA ref clock (100M)"]
3348 pub const SATA_REF: u32 = 0x0b;
3349 #[doc = "USB1 PLL clock"]
3350 pub const USB1_PLL: u32 = 0x0c;
3351 #[doc = "USB2 PLL clock"]
3352 pub const USB2_PLL: u32 = 0x0d;
3353 #[doc = "ref_pfd0_clk == pll3_pfd0_clk"]
3354 pub const PFD0: u32 = 0x0e;
3355 #[doc = "ref_pfd1_clk == pll3_pfd1_clk"]
3356 pub const PFD1: u32 = 0x0f;
3357 #[doc = "ref_pfd2_clk == pll3_pfd2_clk"]
3358 pub const PFD2: u32 = 0x10;
3359 #[doc = "ref_pfd3_clk == pll3_pfd3_clk"]
3360 pub const PFD3: u32 = 0x11;
3361 #[doc = "xtal (24M)"]
3362 pub const XTAL: u32 = 0x12;
3363 #[doc = "LVDS1 (loopback)"]
3364 pub const LVDS1: u32 = 0x13;
3365 #[doc = "LVDS2 (not useful)"]
3366 pub const LVDS2: u32 = 0x14;
3367 }
3368 }
3369 #[doc = "This enables the LVDS output buffer for anaclk1/1b"]
3370 pub mod LVDSCLK1_OBEN {
3371 pub const offset: u32 = 10;
3372 pub const mask: u32 = 0x01 << offset;
3373 pub mod R {}
3374 pub mod W {}
3375 pub mod RW {}
3376 }
3377 #[doc = "This enables the LVDS output buffer for anaclk2/2b"]
3378 pub mod LVDSCLK2_OBEN {
3379 pub const offset: u32 = 11;
3380 pub const mask: u32 = 0x01 << offset;
3381 pub mod R {}
3382 pub mod W {}
3383 pub mod RW {}
3384 }
3385 #[doc = "This enables the LVDS input buffer for anaclk1/1b"]
3386 pub mod LVDSCLK1_IBEN {
3387 pub const offset: u32 = 12;
3388 pub const mask: u32 = 0x01 << offset;
3389 pub mod R {}
3390 pub mod W {}
3391 pub mod RW {}
3392 }
3393 #[doc = "This enables the LVDS input buffer for anaclk2/2b"]
3394 pub mod LVDSCLK2_IBEN {
3395 pub const offset: u32 = 13;
3396 pub const mask: u32 = 0x01 << offset;
3397 pub mod R {}
3398 pub mod W {}
3399 pub mod RW {}
3400 }
3401 #[doc = "This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off"]
3402 pub mod PFD_480_AUTOGATE_EN {
3403 pub const offset: u32 = 16;
3404 pub const mask: u32 = 0x01 << offset;
3405 pub mod R {}
3406 pub mod W {}
3407 pub mod RW {}
3408 }
3409 #[doc = "This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off"]
3410 pub mod PFD_528_AUTOGATE_EN {
3411 pub const offset: u32 = 17;
3412 pub const mask: u32 = 0x01 << offset;
3413 pub mod R {}
3414 pub mod W {}
3415 pub mod RW {}
3416 }
3417 #[doc = "This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature"]
3418 pub mod IRQ_TEMPPANIC {
3419 pub const offset: u32 = 27;
3420 pub const mask: u32 = 0x01 << offset;
3421 pub mod R {}
3422 pub mod W {}
3423 pub mod RW {}
3424 }
3425 #[doc = "This status bit is set to one when the temperature sensor low interrupt asserts for low temperature"]
3426 pub mod IRQ_TEMPLOW {
3427 pub const offset: u32 = 28;
3428 pub const mask: u32 = 0x01 << offset;
3429 pub mod R {}
3430 pub mod W {}
3431 pub mod RW {}
3432 }
3433 #[doc = "This status bit is set to one when the temperature sensor high interrupt asserts for high temperature"]
3434 pub mod IRQ_TEMPHIGH {
3435 pub const offset: u32 = 29;
3436 pub const mask: u32 = 0x01 << offset;
3437 pub mod R {}
3438 pub mod W {}
3439 pub mod RW {}
3440 }
3441 #[doc = "This status bit is set to one when when any of the analog regulator brownout interrupts assert"]
3442 pub mod IRQ_ANA_BO {
3443 pub const offset: u32 = 30;
3444 pub const mask: u32 = 0x01 << offset;
3445 pub mod R {}
3446 pub mod W {}
3447 pub mod RW {}
3448 }
3449 #[doc = "This status bit is set to one when when any of the digital regulator brownout interrupts assert"]
3450 pub mod IRQ_DIG_BO {
3451 pub const offset: u32 = 31;
3452 pub const mask: u32 = 0x01 << offset;
3453 pub mod R {}
3454 pub mod W {}
3455 pub mod RW {}
3456 }
3457}
3458#[doc = "Miscellaneous Control Register"]
3459pub mod MISC2 {
3460 #[doc = "This field defines the brown out voltage offset for the CORE power domain"]
3461 pub mod REG0_BO_OFFSET {
3462 pub const offset: u32 = 0;
3463 pub const mask: u32 = 0x07 << offset;
3464 pub mod R {}
3465 pub mod W {}
3466 pub mod RW {
3467 #[doc = "Brownout offset = 0.100V"]
3468 pub const REG0_BO_OFFSET_4: u32 = 0x04;
3469 #[doc = "Brownout offset = 0.175V"]
3470 pub const REG0_BO_OFFSET_7: u32 = 0x07;
3471 }
3472 }
3473 #[doc = "Reg0 brownout status bit."]
3474 pub mod REG0_BO_STATUS {
3475 pub const offset: u32 = 3;
3476 pub const mask: u32 = 0x01 << offset;
3477 pub mod R {}
3478 pub mod W {}
3479 pub mod RW {
3480 #[doc = "Brownout, supply is below target minus brownout offset."]
3481 pub const REG0_BO_STATUS_1: u32 = 0x01;
3482 }
3483 }
3484 #[doc = "Enables the brownout detection."]
3485 pub mod REG0_ENABLE_BO {
3486 pub const offset: u32 = 5;
3487 pub const mask: u32 = 0x01 << offset;
3488 pub mod R {}
3489 pub mod W {}
3490 pub mod RW {}
3491 }
3492 #[doc = "Default value of \"0\""]
3493 pub mod PLL3_DISABLE {
3494 pub const offset: u32 = 7;
3495 pub const mask: u32 = 0x01 << offset;
3496 pub mod R {}
3497 pub mod W {}
3498 pub mod RW {}
3499 }
3500 #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
3501 pub mod REG1_BO_OFFSET {
3502 pub const offset: u32 = 8;
3503 pub const mask: u32 = 0x07 << offset;
3504 pub mod R {}
3505 pub mod W {}
3506 pub mod RW {
3507 #[doc = "Brownout offset = 0.100V"]
3508 pub const REG1_BO_OFFSET_4: u32 = 0x04;
3509 #[doc = "Brownout offset = 0.175V"]
3510 pub const REG1_BO_OFFSET_7: u32 = 0x07;
3511 }
3512 }
3513 #[doc = "Reg1 brownout status bit."]
3514 pub mod REG1_BO_STATUS {
3515 pub const offset: u32 = 11;
3516 pub const mask: u32 = 0x01 << offset;
3517 pub mod R {}
3518 pub mod W {}
3519 pub mod RW {
3520 #[doc = "Brownout, supply is below target minus brownout offset."]
3521 pub const REG1_BO_STATUS_1: u32 = 0x01;
3522 }
3523 }
3524 #[doc = "Enables the brownout detection."]
3525 pub mod REG1_ENABLE_BO {
3526 pub const offset: u32 = 13;
3527 pub const mask: u32 = 0x01 << offset;
3528 pub mod R {}
3529 pub mod W {}
3530 pub mod RW {}
3531 }
3532 #[doc = "LSB of Post-divider for Audio PLL"]
3533 pub mod AUDIO_DIV_LSB {
3534 pub const offset: u32 = 15;
3535 pub const mask: u32 = 0x01 << offset;
3536 pub mod R {}
3537 pub mod W {}
3538 pub mod RW {
3539 #[doc = "divide by 1 (Default)"]
3540 pub const AUDIO_DIV_LSB_0: u32 = 0;
3541 #[doc = "divide by 2"]
3542 pub const AUDIO_DIV_LSB_1: u32 = 0x01;
3543 }
3544 }
3545 #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
3546 pub mod REG2_BO_OFFSET {
3547 pub const offset: u32 = 16;
3548 pub const mask: u32 = 0x07 << offset;
3549 pub mod R {}
3550 pub mod W {}
3551 pub mod RW {
3552 #[doc = "Brownout offset = 0.100V"]
3553 pub const REG2_BO_OFFSET_4: u32 = 0x04;
3554 #[doc = "Brownout offset = 0.175V"]
3555 pub const REG2_BO_OFFSET_7: u32 = 0x07;
3556 }
3557 }
3558 #[doc = "Reg2 brownout status bit."]
3559 pub mod REG2_BO_STATUS {
3560 pub const offset: u32 = 19;
3561 pub const mask: u32 = 0x01 << offset;
3562 pub mod R {}
3563 pub mod W {}
3564 pub mod RW {}
3565 }
3566 #[doc = "Enables the brownout detection."]
3567 pub mod REG2_ENABLE_BO {
3568 pub const offset: u32 = 21;
3569 pub const mask: u32 = 0x01 << offset;
3570 pub mod R {}
3571 pub mod W {}
3572 pub mod RW {}
3573 }
3574 #[doc = "Signals that the voltage is above the brownout level for the SOC supply"]
3575 pub mod REG2_OK {
3576 pub const offset: u32 = 22;
3577 pub const mask: u32 = 0x01 << offset;
3578 pub mod R {}
3579 pub mod W {}
3580 pub mod RW {}
3581 }
3582 #[doc = "MSB of Post-divider for Audio PLL"]
3583 pub mod AUDIO_DIV_MSB {
3584 pub const offset: u32 = 23;
3585 pub const mask: u32 = 0x01 << offset;
3586 pub mod R {}
3587 pub mod W {}
3588 pub mod RW {
3589 #[doc = "divide by 1 (Default)"]
3590 pub const AUDIO_DIV_MSB_0: u32 = 0;
3591 #[doc = "divide by 2"]
3592 pub const AUDIO_DIV_MSB_1: u32 = 0x01;
3593 }
3594 }
3595 #[doc = "Number of clock periods (24MHz clock)."]
3596 pub mod REG0_STEP_TIME {
3597 pub const offset: u32 = 24;
3598 pub const mask: u32 = 0x03 << offset;
3599 pub mod R {}
3600 pub mod W {}
3601 pub mod RW {
3602 #[doc = "64"]
3603 pub const _64_CLOCKS: u32 = 0;
3604 #[doc = "128"]
3605 pub const _128_CLOCKS: u32 = 0x01;
3606 #[doc = "256"]
3607 pub const _256_CLOCKS: u32 = 0x02;
3608 #[doc = "512"]
3609 pub const _512_CLOCKS: u32 = 0x03;
3610 }
3611 }
3612 #[doc = "Number of clock periods (24MHz clock)."]
3613 pub mod REG1_STEP_TIME {
3614 pub const offset: u32 = 26;
3615 pub const mask: u32 = 0x03 << offset;
3616 pub mod R {}
3617 pub mod W {}
3618 pub mod RW {
3619 #[doc = "64"]
3620 pub const _64_CLOCKS: u32 = 0;
3621 #[doc = "128"]
3622 pub const _128_CLOCKS: u32 = 0x01;
3623 #[doc = "256"]
3624 pub const _256_CLOCKS: u32 = 0x02;
3625 #[doc = "512"]
3626 pub const _512_CLOCKS: u32 = 0x03;
3627 }
3628 }
3629 #[doc = "Number of clock periods (24MHz clock)."]
3630 pub mod REG2_STEP_TIME {
3631 pub const offset: u32 = 28;
3632 pub const mask: u32 = 0x03 << offset;
3633 pub mod R {}
3634 pub mod W {}
3635 pub mod RW {
3636 #[doc = "64"]
3637 pub const _64_CLOCKS: u32 = 0;
3638 #[doc = "128"]
3639 pub const _128_CLOCKS: u32 = 0x01;
3640 #[doc = "256"]
3641 pub const _256_CLOCKS: u32 = 0x02;
3642 #[doc = "512"]
3643 pub const _512_CLOCKS: u32 = 0x03;
3644 }
3645 }
3646 #[doc = "Post-divider for video"]
3647 pub mod VIDEO_DIV {
3648 pub const offset: u32 = 30;
3649 pub const mask: u32 = 0x03 << offset;
3650 pub mod R {}
3651 pub mod W {}
3652 pub mod RW {
3653 #[doc = "divide by 1 (Default)"]
3654 pub const VIDEO_DIV_0: u32 = 0;
3655 #[doc = "divide by 2"]
3656 pub const VIDEO_DIV_1: u32 = 0x01;
3657 #[doc = "divide by 1"]
3658 pub const VIDEO_DIV_2: u32 = 0x02;
3659 #[doc = "divide by 4"]
3660 pub const VIDEO_DIV_3: u32 = 0x03;
3661 }
3662 }
3663}
3664#[doc = "Miscellaneous Control Register"]
3665pub mod MISC2_SET {
3666 #[doc = "This field defines the brown out voltage offset for the CORE power domain"]
3667 pub mod REG0_BO_OFFSET {
3668 pub const offset: u32 = 0;
3669 pub const mask: u32 = 0x07 << offset;
3670 pub mod R {}
3671 pub mod W {}
3672 pub mod RW {
3673 #[doc = "Brownout offset = 0.100V"]
3674 pub const REG0_BO_OFFSET_4: u32 = 0x04;
3675 #[doc = "Brownout offset = 0.175V"]
3676 pub const REG0_BO_OFFSET_7: u32 = 0x07;
3677 }
3678 }
3679 #[doc = "Reg0 brownout status bit."]
3680 pub mod REG0_BO_STATUS {
3681 pub const offset: u32 = 3;
3682 pub const mask: u32 = 0x01 << offset;
3683 pub mod R {}
3684 pub mod W {}
3685 pub mod RW {
3686 #[doc = "Brownout, supply is below target minus brownout offset."]
3687 pub const REG0_BO_STATUS_1: u32 = 0x01;
3688 }
3689 }
3690 #[doc = "Enables the brownout detection."]
3691 pub mod REG0_ENABLE_BO {
3692 pub const offset: u32 = 5;
3693 pub const mask: u32 = 0x01 << offset;
3694 pub mod R {}
3695 pub mod W {}
3696 pub mod RW {}
3697 }
3698 #[doc = "Default value of \"0\""]
3699 pub mod PLL3_DISABLE {
3700 pub const offset: u32 = 7;
3701 pub const mask: u32 = 0x01 << offset;
3702 pub mod R {}
3703 pub mod W {}
3704 pub mod RW {}
3705 }
3706 #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
3707 pub mod REG1_BO_OFFSET {
3708 pub const offset: u32 = 8;
3709 pub const mask: u32 = 0x07 << offset;
3710 pub mod R {}
3711 pub mod W {}
3712 pub mod RW {
3713 #[doc = "Brownout offset = 0.100V"]
3714 pub const REG1_BO_OFFSET_4: u32 = 0x04;
3715 #[doc = "Brownout offset = 0.175V"]
3716 pub const REG1_BO_OFFSET_7: u32 = 0x07;
3717 }
3718 }
3719 #[doc = "Reg1 brownout status bit."]
3720 pub mod REG1_BO_STATUS {
3721 pub const offset: u32 = 11;
3722 pub const mask: u32 = 0x01 << offset;
3723 pub mod R {}
3724 pub mod W {}
3725 pub mod RW {
3726 #[doc = "Brownout, supply is below target minus brownout offset."]
3727 pub const REG1_BO_STATUS_1: u32 = 0x01;
3728 }
3729 }
3730 #[doc = "Enables the brownout detection."]
3731 pub mod REG1_ENABLE_BO {
3732 pub const offset: u32 = 13;
3733 pub const mask: u32 = 0x01 << offset;
3734 pub mod R {}
3735 pub mod W {}
3736 pub mod RW {}
3737 }
3738 #[doc = "LSB of Post-divider for Audio PLL"]
3739 pub mod AUDIO_DIV_LSB {
3740 pub const offset: u32 = 15;
3741 pub const mask: u32 = 0x01 << offset;
3742 pub mod R {}
3743 pub mod W {}
3744 pub mod RW {
3745 #[doc = "divide by 1 (Default)"]
3746 pub const AUDIO_DIV_LSB_0: u32 = 0;
3747 #[doc = "divide by 2"]
3748 pub const AUDIO_DIV_LSB_1: u32 = 0x01;
3749 }
3750 }
3751 #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
3752 pub mod REG2_BO_OFFSET {
3753 pub const offset: u32 = 16;
3754 pub const mask: u32 = 0x07 << offset;
3755 pub mod R {}
3756 pub mod W {}
3757 pub mod RW {
3758 #[doc = "Brownout offset = 0.100V"]
3759 pub const REG2_BO_OFFSET_4: u32 = 0x04;
3760 #[doc = "Brownout offset = 0.175V"]
3761 pub const REG2_BO_OFFSET_7: u32 = 0x07;
3762 }
3763 }
3764 #[doc = "Reg2 brownout status bit."]
3765 pub mod REG2_BO_STATUS {
3766 pub const offset: u32 = 19;
3767 pub const mask: u32 = 0x01 << offset;
3768 pub mod R {}
3769 pub mod W {}
3770 pub mod RW {}
3771 }
3772 #[doc = "Enables the brownout detection."]
3773 pub mod REG2_ENABLE_BO {
3774 pub const offset: u32 = 21;
3775 pub const mask: u32 = 0x01 << offset;
3776 pub mod R {}
3777 pub mod W {}
3778 pub mod RW {}
3779 }
3780 #[doc = "Signals that the voltage is above the brownout level for the SOC supply"]
3781 pub mod REG2_OK {
3782 pub const offset: u32 = 22;
3783 pub const mask: u32 = 0x01 << offset;
3784 pub mod R {}
3785 pub mod W {}
3786 pub mod RW {}
3787 }
3788 #[doc = "MSB of Post-divider for Audio PLL"]
3789 pub mod AUDIO_DIV_MSB {
3790 pub const offset: u32 = 23;
3791 pub const mask: u32 = 0x01 << offset;
3792 pub mod R {}
3793 pub mod W {}
3794 pub mod RW {
3795 #[doc = "divide by 1 (Default)"]
3796 pub const AUDIO_DIV_MSB_0: u32 = 0;
3797 #[doc = "divide by 2"]
3798 pub const AUDIO_DIV_MSB_1: u32 = 0x01;
3799 }
3800 }
3801 #[doc = "Number of clock periods (24MHz clock)."]
3802 pub mod REG0_STEP_TIME {
3803 pub const offset: u32 = 24;
3804 pub const mask: u32 = 0x03 << offset;
3805 pub mod R {}
3806 pub mod W {}
3807 pub mod RW {
3808 #[doc = "64"]
3809 pub const _64_CLOCKS: u32 = 0;
3810 #[doc = "128"]
3811 pub const _128_CLOCKS: u32 = 0x01;
3812 #[doc = "256"]
3813 pub const _256_CLOCKS: u32 = 0x02;
3814 #[doc = "512"]
3815 pub const _512_CLOCKS: u32 = 0x03;
3816 }
3817 }
3818 #[doc = "Number of clock periods (24MHz clock)."]
3819 pub mod REG1_STEP_TIME {
3820 pub const offset: u32 = 26;
3821 pub const mask: u32 = 0x03 << offset;
3822 pub mod R {}
3823 pub mod W {}
3824 pub mod RW {
3825 #[doc = "64"]
3826 pub const _64_CLOCKS: u32 = 0;
3827 #[doc = "128"]
3828 pub const _128_CLOCKS: u32 = 0x01;
3829 #[doc = "256"]
3830 pub const _256_CLOCKS: u32 = 0x02;
3831 #[doc = "512"]
3832 pub const _512_CLOCKS: u32 = 0x03;
3833 }
3834 }
3835 #[doc = "Number of clock periods (24MHz clock)."]
3836 pub mod REG2_STEP_TIME {
3837 pub const offset: u32 = 28;
3838 pub const mask: u32 = 0x03 << offset;
3839 pub mod R {}
3840 pub mod W {}
3841 pub mod RW {
3842 #[doc = "64"]
3843 pub const _64_CLOCKS: u32 = 0;
3844 #[doc = "128"]
3845 pub const _128_CLOCKS: u32 = 0x01;
3846 #[doc = "256"]
3847 pub const _256_CLOCKS: u32 = 0x02;
3848 #[doc = "512"]
3849 pub const _512_CLOCKS: u32 = 0x03;
3850 }
3851 }
3852 #[doc = "Post-divider for video"]
3853 pub mod VIDEO_DIV {
3854 pub const offset: u32 = 30;
3855 pub const mask: u32 = 0x03 << offset;
3856 pub mod R {}
3857 pub mod W {}
3858 pub mod RW {
3859 #[doc = "divide by 1 (Default)"]
3860 pub const VIDEO_DIV_0: u32 = 0;
3861 #[doc = "divide by 2"]
3862 pub const VIDEO_DIV_1: u32 = 0x01;
3863 #[doc = "divide by 1"]
3864 pub const VIDEO_DIV_2: u32 = 0x02;
3865 #[doc = "divide by 4"]
3866 pub const VIDEO_DIV_3: u32 = 0x03;
3867 }
3868 }
3869}
3870#[doc = "Miscellaneous Control Register"]
3871pub mod MISC2_CLR {
3872 #[doc = "This field defines the brown out voltage offset for the CORE power domain"]
3873 pub mod REG0_BO_OFFSET {
3874 pub const offset: u32 = 0;
3875 pub const mask: u32 = 0x07 << offset;
3876 pub mod R {}
3877 pub mod W {}
3878 pub mod RW {
3879 #[doc = "Brownout offset = 0.100V"]
3880 pub const REG0_BO_OFFSET_4: u32 = 0x04;
3881 #[doc = "Brownout offset = 0.175V"]
3882 pub const REG0_BO_OFFSET_7: u32 = 0x07;
3883 }
3884 }
3885 #[doc = "Reg0 brownout status bit."]
3886 pub mod REG0_BO_STATUS {
3887 pub const offset: u32 = 3;
3888 pub const mask: u32 = 0x01 << offset;
3889 pub mod R {}
3890 pub mod W {}
3891 pub mod RW {
3892 #[doc = "Brownout, supply is below target minus brownout offset."]
3893 pub const REG0_BO_STATUS_1: u32 = 0x01;
3894 }
3895 }
3896 #[doc = "Enables the brownout detection."]
3897 pub mod REG0_ENABLE_BO {
3898 pub const offset: u32 = 5;
3899 pub const mask: u32 = 0x01 << offset;
3900 pub mod R {}
3901 pub mod W {}
3902 pub mod RW {}
3903 }
3904 #[doc = "Default value of \"0\""]
3905 pub mod PLL3_DISABLE {
3906 pub const offset: u32 = 7;
3907 pub const mask: u32 = 0x01 << offset;
3908 pub mod R {}
3909 pub mod W {}
3910 pub mod RW {}
3911 }
3912 #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
3913 pub mod REG1_BO_OFFSET {
3914 pub const offset: u32 = 8;
3915 pub const mask: u32 = 0x07 << offset;
3916 pub mod R {}
3917 pub mod W {}
3918 pub mod RW {
3919 #[doc = "Brownout offset = 0.100V"]
3920 pub const REG1_BO_OFFSET_4: u32 = 0x04;
3921 #[doc = "Brownout offset = 0.175V"]
3922 pub const REG1_BO_OFFSET_7: u32 = 0x07;
3923 }
3924 }
3925 #[doc = "Reg1 brownout status bit."]
3926 pub mod REG1_BO_STATUS {
3927 pub const offset: u32 = 11;
3928 pub const mask: u32 = 0x01 << offset;
3929 pub mod R {}
3930 pub mod W {}
3931 pub mod RW {
3932 #[doc = "Brownout, supply is below target minus brownout offset."]
3933 pub const REG1_BO_STATUS_1: u32 = 0x01;
3934 }
3935 }
3936 #[doc = "Enables the brownout detection."]
3937 pub mod REG1_ENABLE_BO {
3938 pub const offset: u32 = 13;
3939 pub const mask: u32 = 0x01 << offset;
3940 pub mod R {}
3941 pub mod W {}
3942 pub mod RW {}
3943 }
3944 #[doc = "LSB of Post-divider for Audio PLL"]
3945 pub mod AUDIO_DIV_LSB {
3946 pub const offset: u32 = 15;
3947 pub const mask: u32 = 0x01 << offset;
3948 pub mod R {}
3949 pub mod W {}
3950 pub mod RW {
3951 #[doc = "divide by 1 (Default)"]
3952 pub const AUDIO_DIV_LSB_0: u32 = 0;
3953 #[doc = "divide by 2"]
3954 pub const AUDIO_DIV_LSB_1: u32 = 0x01;
3955 }
3956 }
3957 #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
3958 pub mod REG2_BO_OFFSET {
3959 pub const offset: u32 = 16;
3960 pub const mask: u32 = 0x07 << offset;
3961 pub mod R {}
3962 pub mod W {}
3963 pub mod RW {
3964 #[doc = "Brownout offset = 0.100V"]
3965 pub const REG2_BO_OFFSET_4: u32 = 0x04;
3966 #[doc = "Brownout offset = 0.175V"]
3967 pub const REG2_BO_OFFSET_7: u32 = 0x07;
3968 }
3969 }
3970 #[doc = "Reg2 brownout status bit."]
3971 pub mod REG2_BO_STATUS {
3972 pub const offset: u32 = 19;
3973 pub const mask: u32 = 0x01 << offset;
3974 pub mod R {}
3975 pub mod W {}
3976 pub mod RW {}
3977 }
3978 #[doc = "Enables the brownout detection."]
3979 pub mod REG2_ENABLE_BO {
3980 pub const offset: u32 = 21;
3981 pub const mask: u32 = 0x01 << offset;
3982 pub mod R {}
3983 pub mod W {}
3984 pub mod RW {}
3985 }
3986 #[doc = "Signals that the voltage is above the brownout level for the SOC supply"]
3987 pub mod REG2_OK {
3988 pub const offset: u32 = 22;
3989 pub const mask: u32 = 0x01 << offset;
3990 pub mod R {}
3991 pub mod W {}
3992 pub mod RW {}
3993 }
3994 #[doc = "MSB of Post-divider for Audio PLL"]
3995 pub mod AUDIO_DIV_MSB {
3996 pub const offset: u32 = 23;
3997 pub const mask: u32 = 0x01 << offset;
3998 pub mod R {}
3999 pub mod W {}
4000 pub mod RW {
4001 #[doc = "divide by 1 (Default)"]
4002 pub const AUDIO_DIV_MSB_0: u32 = 0;
4003 #[doc = "divide by 2"]
4004 pub const AUDIO_DIV_MSB_1: u32 = 0x01;
4005 }
4006 }
4007 #[doc = "Number of clock periods (24MHz clock)."]
4008 pub mod REG0_STEP_TIME {
4009 pub const offset: u32 = 24;
4010 pub const mask: u32 = 0x03 << offset;
4011 pub mod R {}
4012 pub mod W {}
4013 pub mod RW {
4014 #[doc = "64"]
4015 pub const _64_CLOCKS: u32 = 0;
4016 #[doc = "128"]
4017 pub const _128_CLOCKS: u32 = 0x01;
4018 #[doc = "256"]
4019 pub const _256_CLOCKS: u32 = 0x02;
4020 #[doc = "512"]
4021 pub const _512_CLOCKS: u32 = 0x03;
4022 }
4023 }
4024 #[doc = "Number of clock periods (24MHz clock)."]
4025 pub mod REG1_STEP_TIME {
4026 pub const offset: u32 = 26;
4027 pub const mask: u32 = 0x03 << offset;
4028 pub mod R {}
4029 pub mod W {}
4030 pub mod RW {
4031 #[doc = "64"]
4032 pub const _64_CLOCKS: u32 = 0;
4033 #[doc = "128"]
4034 pub const _128_CLOCKS: u32 = 0x01;
4035 #[doc = "256"]
4036 pub const _256_CLOCKS: u32 = 0x02;
4037 #[doc = "512"]
4038 pub const _512_CLOCKS: u32 = 0x03;
4039 }
4040 }
4041 #[doc = "Number of clock periods (24MHz clock)."]
4042 pub mod REG2_STEP_TIME {
4043 pub const offset: u32 = 28;
4044 pub const mask: u32 = 0x03 << offset;
4045 pub mod R {}
4046 pub mod W {}
4047 pub mod RW {
4048 #[doc = "64"]
4049 pub const _64_CLOCKS: u32 = 0;
4050 #[doc = "128"]
4051 pub const _128_CLOCKS: u32 = 0x01;
4052 #[doc = "256"]
4053 pub const _256_CLOCKS: u32 = 0x02;
4054 #[doc = "512"]
4055 pub const _512_CLOCKS: u32 = 0x03;
4056 }
4057 }
4058 #[doc = "Post-divider for video"]
4059 pub mod VIDEO_DIV {
4060 pub const offset: u32 = 30;
4061 pub const mask: u32 = 0x03 << offset;
4062 pub mod R {}
4063 pub mod W {}
4064 pub mod RW {
4065 #[doc = "divide by 1 (Default)"]
4066 pub const VIDEO_DIV_0: u32 = 0;
4067 #[doc = "divide by 2"]
4068 pub const VIDEO_DIV_1: u32 = 0x01;
4069 #[doc = "divide by 1"]
4070 pub const VIDEO_DIV_2: u32 = 0x02;
4071 #[doc = "divide by 4"]
4072 pub const VIDEO_DIV_3: u32 = 0x03;
4073 }
4074 }
4075}
4076#[doc = "Miscellaneous Control Register"]
4077pub mod MISC2_TOG {
4078 #[doc = "This field defines the brown out voltage offset for the CORE power domain"]
4079 pub mod REG0_BO_OFFSET {
4080 pub const offset: u32 = 0;
4081 pub const mask: u32 = 0x07 << offset;
4082 pub mod R {}
4083 pub mod W {}
4084 pub mod RW {
4085 #[doc = "Brownout offset = 0.100V"]
4086 pub const REG0_BO_OFFSET_4: u32 = 0x04;
4087 #[doc = "Brownout offset = 0.175V"]
4088 pub const REG0_BO_OFFSET_7: u32 = 0x07;
4089 }
4090 }
4091 #[doc = "Reg0 brownout status bit."]
4092 pub mod REG0_BO_STATUS {
4093 pub const offset: u32 = 3;
4094 pub const mask: u32 = 0x01 << offset;
4095 pub mod R {}
4096 pub mod W {}
4097 pub mod RW {
4098 #[doc = "Brownout, supply is below target minus brownout offset."]
4099 pub const REG0_BO_STATUS_1: u32 = 0x01;
4100 }
4101 }
4102 #[doc = "Enables the brownout detection."]
4103 pub mod REG0_ENABLE_BO {
4104 pub const offset: u32 = 5;
4105 pub const mask: u32 = 0x01 << offset;
4106 pub mod R {}
4107 pub mod W {}
4108 pub mod RW {}
4109 }
4110 #[doc = "Default value of \"0\""]
4111 pub mod PLL3_DISABLE {
4112 pub const offset: u32 = 7;
4113 pub const mask: u32 = 0x01 << offset;
4114 pub mod R {}
4115 pub mod W {}
4116 pub mod RW {}
4117 }
4118 #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
4119 pub mod REG1_BO_OFFSET {
4120 pub const offset: u32 = 8;
4121 pub const mask: u32 = 0x07 << offset;
4122 pub mod R {}
4123 pub mod W {}
4124 pub mod RW {
4125 #[doc = "Brownout offset = 0.100V"]
4126 pub const REG1_BO_OFFSET_4: u32 = 0x04;
4127 #[doc = "Brownout offset = 0.175V"]
4128 pub const REG1_BO_OFFSET_7: u32 = 0x07;
4129 }
4130 }
4131 #[doc = "Reg1 brownout status bit."]
4132 pub mod REG1_BO_STATUS {
4133 pub const offset: u32 = 11;
4134 pub const mask: u32 = 0x01 << offset;
4135 pub mod R {}
4136 pub mod W {}
4137 pub mod RW {
4138 #[doc = "Brownout, supply is below target minus brownout offset."]
4139 pub const REG1_BO_STATUS_1: u32 = 0x01;
4140 }
4141 }
4142 #[doc = "Enables the brownout detection."]
4143 pub mod REG1_ENABLE_BO {
4144 pub const offset: u32 = 13;
4145 pub const mask: u32 = 0x01 << offset;
4146 pub mod R {}
4147 pub mod W {}
4148 pub mod RW {}
4149 }
4150 #[doc = "LSB of Post-divider for Audio PLL"]
4151 pub mod AUDIO_DIV_LSB {
4152 pub const offset: u32 = 15;
4153 pub const mask: u32 = 0x01 << offset;
4154 pub mod R {}
4155 pub mod W {}
4156 pub mod RW {
4157 #[doc = "divide by 1 (Default)"]
4158 pub const AUDIO_DIV_LSB_0: u32 = 0;
4159 #[doc = "divide by 2"]
4160 pub const AUDIO_DIV_LSB_1: u32 = 0x01;
4161 }
4162 }
4163 #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
4164 pub mod REG2_BO_OFFSET {
4165 pub const offset: u32 = 16;
4166 pub const mask: u32 = 0x07 << offset;
4167 pub mod R {}
4168 pub mod W {}
4169 pub mod RW {
4170 #[doc = "Brownout offset = 0.100V"]
4171 pub const REG2_BO_OFFSET_4: u32 = 0x04;
4172 #[doc = "Brownout offset = 0.175V"]
4173 pub const REG2_BO_OFFSET_7: u32 = 0x07;
4174 }
4175 }
4176 #[doc = "Reg2 brownout status bit."]
4177 pub mod REG2_BO_STATUS {
4178 pub const offset: u32 = 19;
4179 pub const mask: u32 = 0x01 << offset;
4180 pub mod R {}
4181 pub mod W {}
4182 pub mod RW {}
4183 }
4184 #[doc = "Enables the brownout detection."]
4185 pub mod REG2_ENABLE_BO {
4186 pub const offset: u32 = 21;
4187 pub const mask: u32 = 0x01 << offset;
4188 pub mod R {}
4189 pub mod W {}
4190 pub mod RW {}
4191 }
4192 #[doc = "Signals that the voltage is above the brownout level for the SOC supply"]
4193 pub mod REG2_OK {
4194 pub const offset: u32 = 22;
4195 pub const mask: u32 = 0x01 << offset;
4196 pub mod R {}
4197 pub mod W {}
4198 pub mod RW {}
4199 }
4200 #[doc = "MSB of Post-divider for Audio PLL"]
4201 pub mod AUDIO_DIV_MSB {
4202 pub const offset: u32 = 23;
4203 pub const mask: u32 = 0x01 << offset;
4204 pub mod R {}
4205 pub mod W {}
4206 pub mod RW {
4207 #[doc = "divide by 1 (Default)"]
4208 pub const AUDIO_DIV_MSB_0: u32 = 0;
4209 #[doc = "divide by 2"]
4210 pub const AUDIO_DIV_MSB_1: u32 = 0x01;
4211 }
4212 }
4213 #[doc = "Number of clock periods (24MHz clock)."]
4214 pub mod REG0_STEP_TIME {
4215 pub const offset: u32 = 24;
4216 pub const mask: u32 = 0x03 << offset;
4217 pub mod R {}
4218 pub mod W {}
4219 pub mod RW {
4220 #[doc = "64"]
4221 pub const _64_CLOCKS: u32 = 0;
4222 #[doc = "128"]
4223 pub const _128_CLOCKS: u32 = 0x01;
4224 #[doc = "256"]
4225 pub const _256_CLOCKS: u32 = 0x02;
4226 #[doc = "512"]
4227 pub const _512_CLOCKS: u32 = 0x03;
4228 }
4229 }
4230 #[doc = "Number of clock periods (24MHz clock)."]
4231 pub mod REG1_STEP_TIME {
4232 pub const offset: u32 = 26;
4233 pub const mask: u32 = 0x03 << offset;
4234 pub mod R {}
4235 pub mod W {}
4236 pub mod RW {
4237 #[doc = "64"]
4238 pub const _64_CLOCKS: u32 = 0;
4239 #[doc = "128"]
4240 pub const _128_CLOCKS: u32 = 0x01;
4241 #[doc = "256"]
4242 pub const _256_CLOCKS: u32 = 0x02;
4243 #[doc = "512"]
4244 pub const _512_CLOCKS: u32 = 0x03;
4245 }
4246 }
4247 #[doc = "Number of clock periods (24MHz clock)."]
4248 pub mod REG2_STEP_TIME {
4249 pub const offset: u32 = 28;
4250 pub const mask: u32 = 0x03 << offset;
4251 pub mod R {}
4252 pub mod W {}
4253 pub mod RW {
4254 #[doc = "64"]
4255 pub const _64_CLOCKS: u32 = 0;
4256 #[doc = "128"]
4257 pub const _128_CLOCKS: u32 = 0x01;
4258 #[doc = "256"]
4259 pub const _256_CLOCKS: u32 = 0x02;
4260 #[doc = "512"]
4261 pub const _512_CLOCKS: u32 = 0x03;
4262 }
4263 }
4264 #[doc = "Post-divider for video"]
4265 pub mod VIDEO_DIV {
4266 pub const offset: u32 = 30;
4267 pub const mask: u32 = 0x03 << offset;
4268 pub mod R {}
4269 pub mod W {}
4270 pub mod RW {
4271 #[doc = "divide by 1 (Default)"]
4272 pub const VIDEO_DIV_0: u32 = 0;
4273 #[doc = "divide by 2"]
4274 pub const VIDEO_DIV_1: u32 = 0x01;
4275 #[doc = "divide by 1"]
4276 pub const VIDEO_DIV_2: u32 = 0x02;
4277 #[doc = "divide by 4"]
4278 pub const VIDEO_DIV_3: u32 = 0x03;
4279 }
4280 }
4281}