imxrt_ral/blocks/imxrt1051/
src.rs

1#[doc = "SRC"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "SRC Control Register"]
5    pub SCR: crate::RWRegister<u32>,
6    #[doc = "SRC Boot Mode Register 1"]
7    pub SBMR1: crate::RORegister<u32>,
8    #[doc = "SRC Reset Status Register"]
9    pub SRSR: crate::RWRegister<u32>,
10    _reserved0: [u8; 0x10],
11    #[doc = "SRC Boot Mode Register 2"]
12    pub SBMR2: crate::RORegister<u32>,
13    #[doc = "SRC General Purpose Register 1"]
14    pub GPR1: crate::RWRegister<u32>,
15    #[doc = "SRC General Purpose Register 2"]
16    pub GPR2: crate::RWRegister<u32>,
17    #[doc = "SRC General Purpose Register 3"]
18    pub GPR3: crate::RWRegister<u32>,
19    #[doc = "SRC General Purpose Register 4"]
20    pub GPR4: crate::RWRegister<u32>,
21    #[doc = "SRC General Purpose Register 5"]
22    pub GPR5: crate::RWRegister<u32>,
23    #[doc = "SRC General Purpose Register 6"]
24    pub GPR6: crate::RWRegister<u32>,
25    #[doc = "SRC General Purpose Register 7"]
26    pub GPR7: crate::RWRegister<u32>,
27    #[doc = "SRC General Purpose Register 8"]
28    pub GPR8: crate::RWRegister<u32>,
29    #[doc = "SRC General Purpose Register 9"]
30    pub GPR9: crate::RORegister<u32>,
31    #[doc = "SRC General Purpose Register 10"]
32    pub GPR10: crate::RWRegister<u32>,
33}
34#[doc = "SRC Control Register"]
35pub mod SCR {
36    #[doc = "Mask wdog_rst_b source"]
37    pub mod MASK_WDOG_RST {
38        pub const offset: u32 = 7;
39        pub const mask: u32 = 0x0f << offset;
40        pub mod R {}
41        pub mod W {}
42        pub mod RW {
43            #[doc = "wdog_rst_b is masked"]
44            pub const MASK_WDOG_RST_5: u32 = 0x05;
45            #[doc = "wdog_rst_b is not masked (default)"]
46            pub const MASK_WDOG_RST_10: u32 = 0x0a;
47        }
48    }
49    #[doc = "Software reset for core0 only"]
50    pub mod CORE0_RST {
51        pub const offset: u32 = 13;
52        pub const mask: u32 = 0x01 << offset;
53        pub mod R {}
54        pub mod W {}
55        pub mod RW {
56            #[doc = "do not assert core0 reset"]
57            pub const CORE0_RST_0: u32 = 0;
58            #[doc = "assert core0 reset"]
59            pub const CORE0_RST_1: u32 = 0x01;
60        }
61    }
62    #[doc = "Software reset for core0 debug only"]
63    pub mod CORE0_DBG_RST {
64        pub const offset: u32 = 17;
65        pub const mask: u32 = 0x01 << offset;
66        pub mod R {}
67        pub mod W {}
68        pub mod RW {
69            #[doc = "do not assert core0 debug reset"]
70            pub const CORE0_DBG_RST_0: u32 = 0;
71            #[doc = "assert core0 debug reset"]
72            pub const CORE0_DBG_RST_1: u32 = 0x01;
73        }
74    }
75    #[doc = "Do not assert debug resets after power gating event of core"]
76    pub mod DBG_RST_MSK_PG {
77        pub const offset: u32 = 25;
78        pub const mask: u32 = 0x01 << offset;
79        pub mod R {}
80        pub mod W {}
81        pub mod RW {
82            #[doc = "do not mask core debug resets (debug resets will be asserted after power gating event)"]
83            pub const DBG_RST_MSK_PG_0: u32 = 0;
84            #[doc = "mask core debug resets (debug resets won't be asserted after power gating event)"]
85            pub const DBG_RST_MSK_PG_1: u32 = 0x01;
86        }
87    }
88    #[doc = "Mask wdog3_rst_b source"]
89    pub mod MASK_WDOG3_RST {
90        pub const offset: u32 = 28;
91        pub const mask: u32 = 0x0f << offset;
92        pub mod R {}
93        pub mod W {}
94        pub mod RW {
95            #[doc = "wdog3_rst_b is masked"]
96            pub const MASK_WDOG3_RST_5: u32 = 0x05;
97            #[doc = "wdog3_rst_b is not masked"]
98            pub const MASK_WDOG3_RST_10: u32 = 0x0a;
99        }
100    }
101}
102#[doc = "SRC Boot Mode Register 1"]
103pub mod SBMR1 {
104    #[doc = "Refer to fusemap."]
105    pub mod BOOT_CFG1 {
106        pub const offset: u32 = 0;
107        pub const mask: u32 = 0xff << offset;
108        pub mod R {}
109        pub mod W {}
110        pub mod RW {}
111    }
112    #[doc = "Refer to fusemap."]
113    pub mod BOOT_CFG2 {
114        pub const offset: u32 = 8;
115        pub const mask: u32 = 0xff << offset;
116        pub mod R {}
117        pub mod W {}
118        pub mod RW {}
119    }
120    #[doc = "Refer to fusemap."]
121    pub mod BOOT_CFG3 {
122        pub const offset: u32 = 16;
123        pub const mask: u32 = 0xff << offset;
124        pub mod R {}
125        pub mod W {}
126        pub mod RW {}
127    }
128    #[doc = "Refer to fusemap."]
129    pub mod BOOT_CFG4 {
130        pub const offset: u32 = 24;
131        pub const mask: u32 = 0xff << offset;
132        pub mod R {}
133        pub mod W {}
134        pub mod RW {}
135    }
136}
137#[doc = "SRC Reset Status Register"]
138pub mod SRSR {
139    #[doc = "Indicates whether reset was the result of ipp_reset_b pin (Power-up sequence)"]
140    pub mod IPP_RESET_B {
141        pub const offset: u32 = 0;
142        pub const mask: u32 = 0x01 << offset;
143        pub mod R {}
144        pub mod W {}
145        pub mod RW {
146            #[doc = "Reset is not a result of ipp_reset_b pin."]
147            pub const IPP_RESET_B_0: u32 = 0;
148            #[doc = "Reset is a result of ipp_reset_b pin."]
149            pub const IPP_RESET_B_1: u32 = 0x01;
150        }
151    }
152    #[doc = "Indicates a reset has been caused by CPU lockup."]
153    pub mod LOCKUP_SYSRESETREQ {
154        pub const offset: u32 = 1;
155        pub const mask: u32 = 0x01 << offset;
156        pub mod R {}
157        pub mod W {}
158        pub mod RW {
159            #[doc = "Reset is not a result of the mentioned case."]
160            pub const LOCKUP_0: u32 = 0;
161            #[doc = "Reset is a result of the mentioned case."]
162            pub const LOCKUP_1: u32 = 0x01;
163        }
164    }
165    #[doc = "Indicates whether the reset was the result of the csu_reset_b input."]
166    pub mod CSU_RESET_B {
167        pub const offset: u32 = 2;
168        pub const mask: u32 = 0x01 << offset;
169        pub mod R {}
170        pub mod W {}
171        pub mod RW {
172            #[doc = "Reset is not a result of the csu_reset_b event."]
173            pub const CSU_RESET_B_0: u32 = 0;
174            #[doc = "Reset is a result of the csu_reset_b event."]
175            pub const CSU_RESET_B_1: u32 = 0x01;
176        }
177    }
178    #[doc = "Indicates whether the reset was the result of the ipp_user_reset_b qualified reset."]
179    pub mod IPP_USER_RESET_B {
180        pub const offset: u32 = 3;
181        pub const mask: u32 = 0x01 << offset;
182        pub mod R {}
183        pub mod W {}
184        pub mod RW {
185            #[doc = "Reset is not a result of the ipp_user_reset_b qualified as COLD reset event."]
186            pub const IPP_USER_RESET_B_0: u32 = 0;
187            #[doc = "Reset is a result of the ipp_user_reset_b qualified as COLD reset event."]
188            pub const IPP_USER_RESET_B_1: u32 = 0x01;
189        }
190    }
191    #[doc = "IC Watchdog Time-out reset"]
192    pub mod WDOG_RST_B {
193        pub const offset: u32 = 4;
194        pub const mask: u32 = 0x01 << offset;
195        pub mod R {}
196        pub mod W {}
197        pub mod RW {
198            #[doc = "Reset is not a result of the watchdog time-out event."]
199            pub const WDOG_RST_B_0: u32 = 0;
200            #[doc = "Reset is a result of the watchdog time-out event."]
201            pub const WDOG_RST_B_1: u32 = 0x01;
202        }
203    }
204    #[doc = "HIGH - Z JTAG reset. Indicates whether the reset was the result of HIGH-Z reset from JTAG."]
205    pub mod JTAG_RST_B {
206        pub const offset: u32 = 5;
207        pub const mask: u32 = 0x01 << offset;
208        pub mod R {}
209        pub mod W {}
210        pub mod RW {
211            #[doc = "Reset is not a result of HIGH-Z reset from JTAG."]
212            pub const JTAG_RST_B_0: u32 = 0;
213            #[doc = "Reset is a result of HIGH-Z reset from JTAG."]
214            pub const JTAG_RST_B_1: u32 = 0x01;
215        }
216    }
217    #[doc = "JTAG software reset"]
218    pub mod JTAG_SW_RST {
219        pub const offset: u32 = 6;
220        pub const mask: u32 = 0x01 << offset;
221        pub mod R {}
222        pub mod W {}
223        pub mod RW {
224            #[doc = "Reset is not a result of the mentioned case."]
225            pub const JTAG_SW_RST_0: u32 = 0;
226            #[doc = "Reset is not a result of the mentioned case."]
227            pub const JTAG_SW_RST_1: u32 = 0x01;
228        }
229    }
230    #[doc = "IC Watchdog3 Time-out reset"]
231    pub mod WDOG3_RST_B {
232        pub const offset: u32 = 7;
233        pub const mask: u32 = 0x01 << offset;
234        pub mod R {}
235        pub mod W {}
236        pub mod RW {
237            #[doc = "Reset is not a result of the watchdog3 time-out event."]
238            pub const WDOG3_RST_B_0: u32 = 0;
239            #[doc = "Reset is a result of the watchdog3 time-out event."]
240            pub const WDOG3_RST_B_1: u32 = 0x01;
241        }
242    }
243    #[doc = "Temper Sensor software reset"]
244    pub mod TEMPSENSE_RST_B {
245        pub const offset: u32 = 8;
246        pub const mask: u32 = 0x01 << offset;
247        pub mod R {}
248        pub mod W {}
249        pub mod RW {
250            #[doc = "Reset is not a result of software reset from Temperature Sensor."]
251            pub const TEMPSENSE_RST_B_0: u32 = 0;
252            #[doc = "Reset is a result of software reset from Temperature Sensor."]
253            pub const TEMPSENSE_RST_B_1: u32 = 0x01;
254        }
255    }
256}
257#[doc = "SRC Boot Mode Register 2"]
258pub mod SBMR2 {
259    #[doc = "SECONFIG\\[1\\] shows the state of the SECONFIG\\[1\\] fuse"]
260    pub mod SEC_CONFIG {
261        pub const offset: u32 = 0;
262        pub const mask: u32 = 0x03 << offset;
263        pub mod R {}
264        pub mod W {}
265        pub mod RW {}
266    }
267    #[doc = "DIR_BT_DIS shows the state of the DIR_BT_DIS fuse"]
268    pub mod DIR_BT_DIS {
269        pub const offset: u32 = 3;
270        pub const mask: u32 = 0x01 << offset;
271        pub mod R {}
272        pub mod W {}
273        pub mod RW {}
274    }
275    #[doc = "BT_FUSE_SEL (connected to gpio bt_fuse_sel) shows the state of the BT_FUSE_SEL fuse"]
276    pub mod BT_FUSE_SEL {
277        pub const offset: u32 = 4;
278        pub const mask: u32 = 0x01 << offset;
279        pub mod R {}
280        pub mod W {}
281        pub mod RW {}
282    }
283    #[doc = "BMOD\\[1:0\\] shows the latched state of the BOOT_MODE1 and BOOT_MODE0 signals on the rising edge of POR_B"]
284    pub mod BMOD {
285        pub const offset: u32 = 24;
286        pub const mask: u32 = 0x03 << offset;
287        pub mod R {}
288        pub mod W {}
289        pub mod RW {}
290    }
291}
292#[doc = "SRC General Purpose Register 1"]
293pub mod GPR1 {
294    #[doc = "Holds entry function for core0 for waking-up from low power mode"]
295    pub mod PERSISTENT_ENTRY0 {
296        pub const offset: u32 = 0;
297        pub const mask: u32 = 0xffff_ffff << offset;
298        pub mod R {}
299        pub mod W {}
300        pub mod RW {}
301    }
302}
303#[doc = "SRC General Purpose Register 2"]
304pub mod GPR2 {
305    #[doc = "Holds argument of entry function for core0 for waking-up from low power mode"]
306    pub mod PERSISTENT_ARG0 {
307        pub const offset: u32 = 0;
308        pub const mask: u32 = 0xffff_ffff << offset;
309        pub mod R {}
310        pub mod W {}
311        pub mod RW {}
312    }
313}