imxrt_ral/blocks/imxrt1051/
usbphy.rs1#[doc = "USBPHY Register Reference Index"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "USB PHY Power-Down Register"]
5 pub PWD: crate::RWRegister<u32>,
6 #[doc = "USB PHY Power-Down Register"]
7 pub PWD_SET: crate::RWRegister<u32>,
8 #[doc = "USB PHY Power-Down Register"]
9 pub PWD_CLR: crate::RWRegister<u32>,
10 #[doc = "USB PHY Power-Down Register"]
11 pub PWD_TOG: crate::RWRegister<u32>,
12 #[doc = "USB PHY Transmitter Control Register"]
13 pub TX: crate::RWRegister<u32>,
14 #[doc = "USB PHY Transmitter Control Register"]
15 pub TX_SET: crate::RWRegister<u32>,
16 #[doc = "USB PHY Transmitter Control Register"]
17 pub TX_CLR: crate::RWRegister<u32>,
18 #[doc = "USB PHY Transmitter Control Register"]
19 pub TX_TOG: crate::RWRegister<u32>,
20 #[doc = "USB PHY Receiver Control Register"]
21 pub RX: crate::RWRegister<u32>,
22 #[doc = "USB PHY Receiver Control Register"]
23 pub RX_SET: crate::RWRegister<u32>,
24 #[doc = "USB PHY Receiver Control Register"]
25 pub RX_CLR: crate::RWRegister<u32>,
26 #[doc = "USB PHY Receiver Control Register"]
27 pub RX_TOG: crate::RWRegister<u32>,
28 #[doc = "USB PHY General Control Register"]
29 pub CTRL: crate::RWRegister<u32>,
30 #[doc = "USB PHY General Control Register"]
31 pub CTRL_SET: crate::RWRegister<u32>,
32 #[doc = "USB PHY General Control Register"]
33 pub CTRL_CLR: crate::RWRegister<u32>,
34 #[doc = "USB PHY General Control Register"]
35 pub CTRL_TOG: crate::RWRegister<u32>,
36 #[doc = "USB PHY Status Register"]
37 pub STATUS: crate::RWRegister<u32>,
38 _reserved0: [u8; 0x0c],
39 #[doc = "USB PHY Debug Register"]
40 pub DEBUG: crate::RWRegister<u32>,
41 #[doc = "USB PHY Debug Register"]
42 pub DEBUG_SET: crate::RWRegister<u32>,
43 #[doc = "USB PHY Debug Register"]
44 pub DEBUG_CLR: crate::RWRegister<u32>,
45 #[doc = "USB PHY Debug Register"]
46 pub DEBUG_TOG: crate::RWRegister<u32>,
47 #[doc = "UTMI Debug Status Register 0"]
48 pub DEBUG0_STATUS: crate::RORegister<u32>,
49 _reserved1: [u8; 0x0c],
50 #[doc = "UTMI Debug Status Register 1"]
51 pub DEBUG1: crate::RWRegister<u32>,
52 #[doc = "UTMI Debug Status Register 1"]
53 pub DEBUG1_SET: crate::RWRegister<u32>,
54 #[doc = "UTMI Debug Status Register 1"]
55 pub DEBUG1_CLR: crate::RWRegister<u32>,
56 #[doc = "UTMI Debug Status Register 1"]
57 pub DEBUG1_TOG: crate::RWRegister<u32>,
58 #[doc = "UTMI RTL Version"]
59 pub VERSION: crate::RORegister<u32>,
60}
61#[doc = "USB PHY Power-Down Register"]
62pub mod PWD {
63 #[doc = "0 = Normal operation"]
64 pub mod TXPWDFS {
65 pub const offset: u32 = 10;
66 pub const mask: u32 = 0x01 << offset;
67 pub mod R {}
68 pub mod W {}
69 pub mod RW {}
70 }
71 #[doc = "0 = Normal operation"]
72 pub mod TXPWDIBIAS {
73 pub const offset: u32 = 11;
74 pub const mask: u32 = 0x01 << offset;
75 pub mod R {}
76 pub mod W {}
77 pub mod RW {}
78 }
79 #[doc = "0 = Normal operation"]
80 pub mod TXPWDV2I {
81 pub const offset: u32 = 12;
82 pub const mask: u32 = 0x01 << offset;
83 pub mod R {}
84 pub mod W {}
85 pub mod RW {}
86 }
87 #[doc = "0 = Normal operation"]
88 pub mod RXPWDENV {
89 pub const offset: u32 = 17;
90 pub const mask: u32 = 0x01 << offset;
91 pub mod R {}
92 pub mod W {}
93 pub mod RW {}
94 }
95 #[doc = "0 = Normal operation"]
96 pub mod RXPWD1PT1 {
97 pub const offset: u32 = 18;
98 pub const mask: u32 = 0x01 << offset;
99 pub mod R {}
100 pub mod W {}
101 pub mod RW {}
102 }
103 #[doc = "0 = Normal operation"]
104 pub mod RXPWDDIFF {
105 pub const offset: u32 = 19;
106 pub const mask: u32 = 0x01 << offset;
107 pub mod R {}
108 pub mod W {}
109 pub mod RW {}
110 }
111 #[doc = "0 = Normal operation"]
112 pub mod RXPWDRX {
113 pub const offset: u32 = 20;
114 pub const mask: u32 = 0x01 << offset;
115 pub mod R {}
116 pub mod W {}
117 pub mod RW {}
118 }
119}
120#[doc = "USB PHY Power-Down Register"]
121pub mod PWD_SET {
122 #[doc = "0 = Normal operation"]
123 pub mod TXPWDFS {
124 pub const offset: u32 = 10;
125 pub const mask: u32 = 0x01 << offset;
126 pub mod R {}
127 pub mod W {}
128 pub mod RW {}
129 }
130 #[doc = "0 = Normal operation"]
131 pub mod TXPWDIBIAS {
132 pub const offset: u32 = 11;
133 pub const mask: u32 = 0x01 << offset;
134 pub mod R {}
135 pub mod W {}
136 pub mod RW {}
137 }
138 #[doc = "0 = Normal operation"]
139 pub mod TXPWDV2I {
140 pub const offset: u32 = 12;
141 pub const mask: u32 = 0x01 << offset;
142 pub mod R {}
143 pub mod W {}
144 pub mod RW {}
145 }
146 #[doc = "0 = Normal operation"]
147 pub mod RXPWDENV {
148 pub const offset: u32 = 17;
149 pub const mask: u32 = 0x01 << offset;
150 pub mod R {}
151 pub mod W {}
152 pub mod RW {}
153 }
154 #[doc = "0 = Normal operation"]
155 pub mod RXPWD1PT1 {
156 pub const offset: u32 = 18;
157 pub const mask: u32 = 0x01 << offset;
158 pub mod R {}
159 pub mod W {}
160 pub mod RW {}
161 }
162 #[doc = "0 = Normal operation"]
163 pub mod RXPWDDIFF {
164 pub const offset: u32 = 19;
165 pub const mask: u32 = 0x01 << offset;
166 pub mod R {}
167 pub mod W {}
168 pub mod RW {}
169 }
170 #[doc = "0 = Normal operation"]
171 pub mod RXPWDRX {
172 pub const offset: u32 = 20;
173 pub const mask: u32 = 0x01 << offset;
174 pub mod R {}
175 pub mod W {}
176 pub mod RW {}
177 }
178}
179#[doc = "USB PHY Power-Down Register"]
180pub mod PWD_CLR {
181 #[doc = "0 = Normal operation"]
182 pub mod TXPWDFS {
183 pub const offset: u32 = 10;
184 pub const mask: u32 = 0x01 << offset;
185 pub mod R {}
186 pub mod W {}
187 pub mod RW {}
188 }
189 #[doc = "0 = Normal operation"]
190 pub mod TXPWDIBIAS {
191 pub const offset: u32 = 11;
192 pub const mask: u32 = 0x01 << offset;
193 pub mod R {}
194 pub mod W {}
195 pub mod RW {}
196 }
197 #[doc = "0 = Normal operation"]
198 pub mod TXPWDV2I {
199 pub const offset: u32 = 12;
200 pub const mask: u32 = 0x01 << offset;
201 pub mod R {}
202 pub mod W {}
203 pub mod RW {}
204 }
205 #[doc = "0 = Normal operation"]
206 pub mod RXPWDENV {
207 pub const offset: u32 = 17;
208 pub const mask: u32 = 0x01 << offset;
209 pub mod R {}
210 pub mod W {}
211 pub mod RW {}
212 }
213 #[doc = "0 = Normal operation"]
214 pub mod RXPWD1PT1 {
215 pub const offset: u32 = 18;
216 pub const mask: u32 = 0x01 << offset;
217 pub mod R {}
218 pub mod W {}
219 pub mod RW {}
220 }
221 #[doc = "0 = Normal operation"]
222 pub mod RXPWDDIFF {
223 pub const offset: u32 = 19;
224 pub const mask: u32 = 0x01 << offset;
225 pub mod R {}
226 pub mod W {}
227 pub mod RW {}
228 }
229 #[doc = "0 = Normal operation"]
230 pub mod RXPWDRX {
231 pub const offset: u32 = 20;
232 pub const mask: u32 = 0x01 << offset;
233 pub mod R {}
234 pub mod W {}
235 pub mod RW {}
236 }
237}
238#[doc = "USB PHY Power-Down Register"]
239pub mod PWD_TOG {
240 #[doc = "0 = Normal operation"]
241 pub mod TXPWDFS {
242 pub const offset: u32 = 10;
243 pub const mask: u32 = 0x01 << offset;
244 pub mod R {}
245 pub mod W {}
246 pub mod RW {}
247 }
248 #[doc = "0 = Normal operation"]
249 pub mod TXPWDIBIAS {
250 pub const offset: u32 = 11;
251 pub const mask: u32 = 0x01 << offset;
252 pub mod R {}
253 pub mod W {}
254 pub mod RW {}
255 }
256 #[doc = "0 = Normal operation"]
257 pub mod TXPWDV2I {
258 pub const offset: u32 = 12;
259 pub const mask: u32 = 0x01 << offset;
260 pub mod R {}
261 pub mod W {}
262 pub mod RW {}
263 }
264 #[doc = "0 = Normal operation"]
265 pub mod RXPWDENV {
266 pub const offset: u32 = 17;
267 pub const mask: u32 = 0x01 << offset;
268 pub mod R {}
269 pub mod W {}
270 pub mod RW {}
271 }
272 #[doc = "0 = Normal operation"]
273 pub mod RXPWD1PT1 {
274 pub const offset: u32 = 18;
275 pub const mask: u32 = 0x01 << offset;
276 pub mod R {}
277 pub mod W {}
278 pub mod RW {}
279 }
280 #[doc = "0 = Normal operation"]
281 pub mod RXPWDDIFF {
282 pub const offset: u32 = 19;
283 pub const mask: u32 = 0x01 << offset;
284 pub mod R {}
285 pub mod W {}
286 pub mod RW {}
287 }
288 #[doc = "0 = Normal operation"]
289 pub mod RXPWDRX {
290 pub const offset: u32 = 20;
291 pub const mask: u32 = 0x01 << offset;
292 pub mod R {}
293 pub mod W {}
294 pub mod RW {}
295 }
296}
297#[doc = "USB PHY Transmitter Control Register"]
298pub mod TX {
299 #[doc = "Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25%"]
300 pub mod D_CAL {
301 pub const offset: u32 = 0;
302 pub const mask: u32 = 0x0f << offset;
303 pub mod R {}
304 pub mod W {}
305 pub mod RW {}
306 }
307 #[doc = "Decode to select a 45-Ohm resistance to the USB_DN output pin"]
308 pub mod TXCAL45DN {
309 pub const offset: u32 = 8;
310 pub const mask: u32 = 0x0f << offset;
311 pub mod R {}
312 pub mod W {}
313 pub mod RW {}
314 }
315 #[doc = "Decode to select a 45-Ohm resistance to the USB_DP output pin"]
316 pub mod TXCAL45DP {
317 pub const offset: u32 = 16;
318 pub const mask: u32 = 0x0f << offset;
319 pub mod R {}
320 pub mod W {}
321 pub mod RW {}
322 }
323 #[doc = "Controls the edge-rate of the current sensing transistors used in HS transmit"]
324 pub mod USBPHY_TX_EDGECTRL {
325 pub const offset: u32 = 26;
326 pub const mask: u32 = 0x07 << offset;
327 pub mod R {}
328 pub mod W {}
329 pub mod RW {}
330 }
331}
332#[doc = "USB PHY Transmitter Control Register"]
333pub mod TX_SET {
334 #[doc = "Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25%"]
335 pub mod D_CAL {
336 pub const offset: u32 = 0;
337 pub const mask: u32 = 0x0f << offset;
338 pub mod R {}
339 pub mod W {}
340 pub mod RW {}
341 }
342 #[doc = "Decode to select a 45-Ohm resistance to the USB_DN output pin"]
343 pub mod TXCAL45DN {
344 pub const offset: u32 = 8;
345 pub const mask: u32 = 0x0f << offset;
346 pub mod R {}
347 pub mod W {}
348 pub mod RW {}
349 }
350 #[doc = "Decode to select a 45-Ohm resistance to the USB_DP output pin"]
351 pub mod TXCAL45DP {
352 pub const offset: u32 = 16;
353 pub const mask: u32 = 0x0f << offset;
354 pub mod R {}
355 pub mod W {}
356 pub mod RW {}
357 }
358 #[doc = "Controls the edge-rate of the current sensing transistors used in HS transmit"]
359 pub mod USBPHY_TX_EDGECTRL {
360 pub const offset: u32 = 26;
361 pub const mask: u32 = 0x07 << offset;
362 pub mod R {}
363 pub mod W {}
364 pub mod RW {}
365 }
366}
367#[doc = "USB PHY Transmitter Control Register"]
368pub mod TX_CLR {
369 #[doc = "Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25%"]
370 pub mod D_CAL {
371 pub const offset: u32 = 0;
372 pub const mask: u32 = 0x0f << offset;
373 pub mod R {}
374 pub mod W {}
375 pub mod RW {}
376 }
377 #[doc = "Decode to select a 45-Ohm resistance to the USB_DN output pin"]
378 pub mod TXCAL45DN {
379 pub const offset: u32 = 8;
380 pub const mask: u32 = 0x0f << offset;
381 pub mod R {}
382 pub mod W {}
383 pub mod RW {}
384 }
385 #[doc = "Decode to select a 45-Ohm resistance to the USB_DP output pin"]
386 pub mod TXCAL45DP {
387 pub const offset: u32 = 16;
388 pub const mask: u32 = 0x0f << offset;
389 pub mod R {}
390 pub mod W {}
391 pub mod RW {}
392 }
393 #[doc = "Controls the edge-rate of the current sensing transistors used in HS transmit"]
394 pub mod USBPHY_TX_EDGECTRL {
395 pub const offset: u32 = 26;
396 pub const mask: u32 = 0x07 << offset;
397 pub mod R {}
398 pub mod W {}
399 pub mod RW {}
400 }
401}
402#[doc = "USB PHY Transmitter Control Register"]
403pub mod TX_TOG {
404 #[doc = "Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25%"]
405 pub mod D_CAL {
406 pub const offset: u32 = 0;
407 pub const mask: u32 = 0x0f << offset;
408 pub mod R {}
409 pub mod W {}
410 pub mod RW {}
411 }
412 #[doc = "Decode to select a 45-Ohm resistance to the USB_DN output pin"]
413 pub mod TXCAL45DN {
414 pub const offset: u32 = 8;
415 pub const mask: u32 = 0x0f << offset;
416 pub mod R {}
417 pub mod W {}
418 pub mod RW {}
419 }
420 #[doc = "Decode to select a 45-Ohm resistance to the USB_DP output pin"]
421 pub mod TXCAL45DP {
422 pub const offset: u32 = 16;
423 pub const mask: u32 = 0x0f << offset;
424 pub mod R {}
425 pub mod W {}
426 pub mod RW {}
427 }
428 #[doc = "Controls the edge-rate of the current sensing transistors used in HS transmit"]
429 pub mod USBPHY_TX_EDGECTRL {
430 pub const offset: u32 = 26;
431 pub const mask: u32 = 0x07 << offset;
432 pub mod R {}
433 pub mod W {}
434 pub mod RW {}
435 }
436}
437#[doc = "USB PHY Receiver Control Register"]
438pub mod RX {
439 #[doc = "The ENVADJ field adjusts the trip point for the envelope detector"]
440 pub mod ENVADJ {
441 pub const offset: u32 = 0;
442 pub const mask: u32 = 0x07 << offset;
443 pub mod R {}
444 pub mod W {}
445 pub mod RW {}
446 }
447 #[doc = "The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0"]
448 pub mod DISCONADJ {
449 pub const offset: u32 = 4;
450 pub const mask: u32 = 0x07 << offset;
451 pub mod R {}
452 pub mod W {}
453 pub mod RW {}
454 }
455 #[doc = "0 = Normal operation"]
456 pub mod RXDBYPASS {
457 pub const offset: u32 = 22;
458 pub const mask: u32 = 0x01 << offset;
459 pub mod R {}
460 pub mod W {}
461 pub mod RW {}
462 }
463}
464#[doc = "USB PHY Receiver Control Register"]
465pub mod RX_SET {
466 #[doc = "The ENVADJ field adjusts the trip point for the envelope detector"]
467 pub mod ENVADJ {
468 pub const offset: u32 = 0;
469 pub const mask: u32 = 0x07 << offset;
470 pub mod R {}
471 pub mod W {}
472 pub mod RW {}
473 }
474 #[doc = "The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0"]
475 pub mod DISCONADJ {
476 pub const offset: u32 = 4;
477 pub const mask: u32 = 0x07 << offset;
478 pub mod R {}
479 pub mod W {}
480 pub mod RW {}
481 }
482 #[doc = "0 = Normal operation"]
483 pub mod RXDBYPASS {
484 pub const offset: u32 = 22;
485 pub const mask: u32 = 0x01 << offset;
486 pub mod R {}
487 pub mod W {}
488 pub mod RW {}
489 }
490}
491#[doc = "USB PHY Receiver Control Register"]
492pub mod RX_CLR {
493 #[doc = "The ENVADJ field adjusts the trip point for the envelope detector"]
494 pub mod ENVADJ {
495 pub const offset: u32 = 0;
496 pub const mask: u32 = 0x07 << offset;
497 pub mod R {}
498 pub mod W {}
499 pub mod RW {}
500 }
501 #[doc = "The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0"]
502 pub mod DISCONADJ {
503 pub const offset: u32 = 4;
504 pub const mask: u32 = 0x07 << offset;
505 pub mod R {}
506 pub mod W {}
507 pub mod RW {}
508 }
509 #[doc = "0 = Normal operation"]
510 pub mod RXDBYPASS {
511 pub const offset: u32 = 22;
512 pub const mask: u32 = 0x01 << offset;
513 pub mod R {}
514 pub mod W {}
515 pub mod RW {}
516 }
517}
518#[doc = "USB PHY Receiver Control Register"]
519pub mod RX_TOG {
520 #[doc = "The ENVADJ field adjusts the trip point for the envelope detector"]
521 pub mod ENVADJ {
522 pub const offset: u32 = 0;
523 pub const mask: u32 = 0x07 << offset;
524 pub mod R {}
525 pub mod W {}
526 pub mod RW {}
527 }
528 #[doc = "The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0"]
529 pub mod DISCONADJ {
530 pub const offset: u32 = 4;
531 pub const mask: u32 = 0x07 << offset;
532 pub mod R {}
533 pub mod W {}
534 pub mod RW {}
535 }
536 #[doc = "0 = Normal operation"]
537 pub mod RXDBYPASS {
538 pub const offset: u32 = 22;
539 pub const mask: u32 = 0x01 << offset;
540 pub mod R {}
541 pub mod W {}
542 pub mod RW {}
543 }
544}
545#[doc = "USB PHY General Control Register"]
546pub mod CTRL {
547 #[doc = "Enable OTG_ID_CHG_IRQ."]
548 pub mod ENOTG_ID_CHG_IRQ {
549 pub const offset: u32 = 0;
550 pub const mask: u32 = 0x01 << offset;
551 pub mod R {}
552 pub mod W {}
553 pub mod RW {}
554 }
555 #[doc = "For host mode, enables high-speed disconnect detector"]
556 pub mod ENHOSTDISCONDETECT {
557 pub const offset: u32 = 1;
558 pub const mask: u32 = 0x01 << offset;
559 pub mod R {}
560 pub mod W {}
561 pub mod RW {}
562 }
563 #[doc = "Enables interrupt for detection of disconnection to Device when in high-speed host mode"]
564 pub mod ENIRQHOSTDISCON {
565 pub const offset: u32 = 2;
566 pub const mask: u32 = 0x01 << offset;
567 pub mod R {}
568 pub mod W {}
569 pub mod RW {}
570 }
571 #[doc = "Indicates that the device has disconnected in high-speed mode"]
572 pub mod HOSTDISCONDETECT_IRQ {
573 pub const offset: u32 = 3;
574 pub const mask: u32 = 0x01 << offset;
575 pub mod R {}
576 pub mod W {}
577 pub mod RW {}
578 }
579 #[doc = "For device mode, enables 200-KOhm pullups for detecting connectivity to the host."]
580 pub mod ENDEVPLUGINDETECT {
581 pub const offset: u32 = 4;
582 pub const mask: u32 = 0x01 << offset;
583 pub mod R {}
584 pub mod W {}
585 pub mod RW {}
586 }
587 #[doc = "For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in"]
588 pub mod DEVPLUGIN_POLARITY {
589 pub const offset: u32 = 5;
590 pub const mask: u32 = 0x01 << offset;
591 pub mod R {}
592 pub mod W {}
593 pub mod RW {}
594 }
595 #[doc = "OTG ID change interrupt. Indicates the value of ID pin changed."]
596 pub mod OTG_ID_CHG_IRQ {
597 pub const offset: u32 = 6;
598 pub const mask: u32 = 0x01 << offset;
599 pub mod R {}
600 pub mod W {}
601 pub mod RW {}
602 }
603 #[doc = "Enables circuit to detect resistance of MiniAB ID pin."]
604 pub mod ENOTGIDDETECT {
605 pub const offset: u32 = 7;
606 pub const mask: u32 = 0x01 << offset;
607 pub mod R {}
608 pub mod W {}
609 pub mod RW {}
610 }
611 #[doc = "Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it"]
612 pub mod RESUMEIRQSTICKY {
613 pub const offset: u32 = 8;
614 pub const mask: u32 = 0x01 << offset;
615 pub mod R {}
616 pub mod W {}
617 pub mod RW {}
618 }
619 #[doc = "Enables interrupt for detection of a non-J state on the USB line"]
620 pub mod ENIRQRESUMEDETECT {
621 pub const offset: u32 = 9;
622 pub const mask: u32 = 0x01 << offset;
623 pub mod R {}
624 pub mod W {}
625 pub mod RW {}
626 }
627 #[doc = "Indicates that the host is sending a wake-up after suspend"]
628 pub mod RESUME_IRQ {
629 pub const offset: u32 = 10;
630 pub const mask: u32 = 0x01 << offset;
631 pub mod R {}
632 pub mod W {}
633 pub mod RW {}
634 }
635 #[doc = "Enables interrupt for the detection of connectivity to the USB line."]
636 pub mod ENIRQDEVPLUGIN {
637 pub const offset: u32 = 11;
638 pub const mask: u32 = 0x01 << offset;
639 pub mod R {}
640 pub mod W {}
641 pub mod RW {}
642 }
643 #[doc = "Indicates that the device is connected"]
644 pub mod DEVPLUGIN_IRQ {
645 pub const offset: u32 = 12;
646 pub const mask: u32 = 0x01 << offset;
647 pub mod R {}
648 pub mod W {}
649 pub mod RW {}
650 }
651 #[doc = "Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only."]
652 pub mod DATA_ON_LRADC {
653 pub const offset: u32 = 13;
654 pub const mask: u32 = 0x01 << offset;
655 pub mod R {}
656 pub mod W {}
657 pub mod RW {}
658 }
659 #[doc = "Enables UTMI+ Level2. This should be enabled if needs to support LS device"]
660 pub mod ENUTMILEVEL2 {
661 pub const offset: u32 = 14;
662 pub const mask: u32 = 0x01 << offset;
663 pub mod R {}
664 pub mod W {}
665 pub mod RW {}
666 }
667 #[doc = "Enables UTMI+ Level3"]
668 pub mod ENUTMILEVEL3 {
669 pub const offset: u32 = 15;
670 pub const mask: u32 = 0x01 << offset;
671 pub mod R {}
672 pub mod W {}
673 pub mod RW {}
674 }
675 #[doc = "Enables interrupt for the wakeup events."]
676 pub mod ENIRQWAKEUP {
677 pub const offset: u32 = 16;
678 pub const mask: u32 = 0x01 << offset;
679 pub mod R {}
680 pub mod W {}
681 pub mod RW {}
682 }
683 #[doc = "Indicates that there is a wakeup event"]
684 pub mod WAKEUP_IRQ {
685 pub const offset: u32 = 17;
686 pub const mask: u32 = 0x01 << offset;
687 pub mod R {}
688 pub mod W {}
689 pub mod RW {}
690 }
691 #[doc = "Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended"]
692 pub mod ENAUTO_PWRON_PLL {
693 pub const offset: u32 = 18;
694 pub const mask: u32 = 0x01 << offset;
695 pub mod R {}
696 pub mod W {}
697 pub mod RW {}
698 }
699 #[doc = "Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended"]
700 pub mod ENAUTOCLR_CLKGATE {
701 pub const offset: u32 = 19;
702 pub const mask: u32 = 0x01 << offset;
703 pub mod R {}
704 pub mod W {}
705 pub mod RW {}
706 }
707 #[doc = "Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended"]
708 pub mod ENAUTOCLR_PHY_PWD {
709 pub const offset: u32 = 20;
710 pub const mask: u32 = 0x01 << offset;
711 pub mod R {}
712 pub mod W {}
713 pub mod RW {}
714 }
715 #[doc = "Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended"]
716 pub mod ENDPDMCHG_WKUP {
717 pub const offset: u32 = 21;
718 pub const mask: u32 = 0x01 << offset;
719 pub mod R {}
720 pub mod W {}
721 pub mod RW {}
722 }
723 #[doc = "Enables the feature to wakeup USB if ID is toggled when USB is suspended."]
724 pub mod ENIDCHG_WKUP {
725 pub const offset: u32 = 22;
726 pub const mask: u32 = 0x01 << offset;
727 pub mod R {}
728 pub mod W {}
729 pub mod RW {}
730 }
731 #[doc = "Enables the feature to wakeup USB if VBUS is toggled when USB is suspended."]
732 pub mod ENVBUSCHG_WKUP {
733 pub const offset: u32 = 23;
734 pub const mask: u32 = 0x01 << offset;
735 pub mod R {}
736 pub mod W {}
737 pub mod RW {}
738 }
739 #[doc = "Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet."]
740 pub mod FSDLL_RST_EN {
741 pub const offset: u32 = 24;
742 pub const mask: u32 = 0x01 << offset;
743 pub mod R {}
744 pub mod W {}
745 pub mod RW {}
746 }
747 #[doc = "Almost same as OTGID_STATUS in USBPHYx_STATUS Register"]
748 pub mod OTG_ID_VALUE {
749 pub const offset: u32 = 27;
750 pub const mask: u32 = 0x01 << offset;
751 pub mod R {}
752 pub mod W {}
753 pub mod RW {}
754 }
755 #[doc = "Forces the next FS packet that is transmitted to have a EOP with LS timing"]
756 pub mod HOST_FORCE_LS_SE0 {
757 pub const offset: u32 = 28;
758 pub const mask: u32 = 0x01 << offset;
759 pub mod R {}
760 pub mod W {}
761 pub mod RW {}
762 }
763 #[doc = "Used by the PHY to indicate a powered-down state"]
764 pub mod UTMI_SUSPENDM {
765 pub const offset: u32 = 29;
766 pub const mask: u32 = 0x01 << offset;
767 pub mod R {}
768 pub mod W {}
769 pub mod RW {}
770 }
771 #[doc = "Gate UTMI Clocks"]
772 pub mod CLKGATE {
773 pub const offset: u32 = 30;
774 pub const mask: u32 = 0x01 << offset;
775 pub mod R {}
776 pub mod W {}
777 pub mod RW {}
778 }
779 #[doc = "Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers"]
780 pub mod SFTRST {
781 pub const offset: u32 = 31;
782 pub const mask: u32 = 0x01 << offset;
783 pub mod R {}
784 pub mod W {}
785 pub mod RW {}
786 }
787}
788#[doc = "USB PHY General Control Register"]
789pub mod CTRL_SET {
790 #[doc = "Enable OTG_ID_CHG_IRQ."]
791 pub mod ENOTG_ID_CHG_IRQ {
792 pub const offset: u32 = 0;
793 pub const mask: u32 = 0x01 << offset;
794 pub mod R {}
795 pub mod W {}
796 pub mod RW {}
797 }
798 #[doc = "For host mode, enables high-speed disconnect detector"]
799 pub mod ENHOSTDISCONDETECT {
800 pub const offset: u32 = 1;
801 pub const mask: u32 = 0x01 << offset;
802 pub mod R {}
803 pub mod W {}
804 pub mod RW {}
805 }
806 #[doc = "Enables interrupt for detection of disconnection to Device when in high-speed host mode"]
807 pub mod ENIRQHOSTDISCON {
808 pub const offset: u32 = 2;
809 pub const mask: u32 = 0x01 << offset;
810 pub mod R {}
811 pub mod W {}
812 pub mod RW {}
813 }
814 #[doc = "Indicates that the device has disconnected in high-speed mode"]
815 pub mod HOSTDISCONDETECT_IRQ {
816 pub const offset: u32 = 3;
817 pub const mask: u32 = 0x01 << offset;
818 pub mod R {}
819 pub mod W {}
820 pub mod RW {}
821 }
822 #[doc = "For device mode, enables 200-KOhm pullups for detecting connectivity to the host."]
823 pub mod ENDEVPLUGINDETECT {
824 pub const offset: u32 = 4;
825 pub const mask: u32 = 0x01 << offset;
826 pub mod R {}
827 pub mod W {}
828 pub mod RW {}
829 }
830 #[doc = "For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in"]
831 pub mod DEVPLUGIN_POLARITY {
832 pub const offset: u32 = 5;
833 pub const mask: u32 = 0x01 << offset;
834 pub mod R {}
835 pub mod W {}
836 pub mod RW {}
837 }
838 #[doc = "OTG ID change interrupt. Indicates the value of ID pin changed."]
839 pub mod OTG_ID_CHG_IRQ {
840 pub const offset: u32 = 6;
841 pub const mask: u32 = 0x01 << offset;
842 pub mod R {}
843 pub mod W {}
844 pub mod RW {}
845 }
846 #[doc = "Enables circuit to detect resistance of MiniAB ID pin."]
847 pub mod ENOTGIDDETECT {
848 pub const offset: u32 = 7;
849 pub const mask: u32 = 0x01 << offset;
850 pub mod R {}
851 pub mod W {}
852 pub mod RW {}
853 }
854 #[doc = "Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it"]
855 pub mod RESUMEIRQSTICKY {
856 pub const offset: u32 = 8;
857 pub const mask: u32 = 0x01 << offset;
858 pub mod R {}
859 pub mod W {}
860 pub mod RW {}
861 }
862 #[doc = "Enables interrupt for detection of a non-J state on the USB line"]
863 pub mod ENIRQRESUMEDETECT {
864 pub const offset: u32 = 9;
865 pub const mask: u32 = 0x01 << offset;
866 pub mod R {}
867 pub mod W {}
868 pub mod RW {}
869 }
870 #[doc = "Indicates that the host is sending a wake-up after suspend"]
871 pub mod RESUME_IRQ {
872 pub const offset: u32 = 10;
873 pub const mask: u32 = 0x01 << offset;
874 pub mod R {}
875 pub mod W {}
876 pub mod RW {}
877 }
878 #[doc = "Enables interrupt for the detection of connectivity to the USB line."]
879 pub mod ENIRQDEVPLUGIN {
880 pub const offset: u32 = 11;
881 pub const mask: u32 = 0x01 << offset;
882 pub mod R {}
883 pub mod W {}
884 pub mod RW {}
885 }
886 #[doc = "Indicates that the device is connected"]
887 pub mod DEVPLUGIN_IRQ {
888 pub const offset: u32 = 12;
889 pub const mask: u32 = 0x01 << offset;
890 pub mod R {}
891 pub mod W {}
892 pub mod RW {}
893 }
894 #[doc = "Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only."]
895 pub mod DATA_ON_LRADC {
896 pub const offset: u32 = 13;
897 pub const mask: u32 = 0x01 << offset;
898 pub mod R {}
899 pub mod W {}
900 pub mod RW {}
901 }
902 #[doc = "Enables UTMI+ Level2. This should be enabled if needs to support LS device"]
903 pub mod ENUTMILEVEL2 {
904 pub const offset: u32 = 14;
905 pub const mask: u32 = 0x01 << offset;
906 pub mod R {}
907 pub mod W {}
908 pub mod RW {}
909 }
910 #[doc = "Enables UTMI+ Level3"]
911 pub mod ENUTMILEVEL3 {
912 pub const offset: u32 = 15;
913 pub const mask: u32 = 0x01 << offset;
914 pub mod R {}
915 pub mod W {}
916 pub mod RW {}
917 }
918 #[doc = "Enables interrupt for the wakeup events."]
919 pub mod ENIRQWAKEUP {
920 pub const offset: u32 = 16;
921 pub const mask: u32 = 0x01 << offset;
922 pub mod R {}
923 pub mod W {}
924 pub mod RW {}
925 }
926 #[doc = "Indicates that there is a wakeup event"]
927 pub mod WAKEUP_IRQ {
928 pub const offset: u32 = 17;
929 pub const mask: u32 = 0x01 << offset;
930 pub mod R {}
931 pub mod W {}
932 pub mod RW {}
933 }
934 #[doc = "Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended"]
935 pub mod ENAUTO_PWRON_PLL {
936 pub const offset: u32 = 18;
937 pub const mask: u32 = 0x01 << offset;
938 pub mod R {}
939 pub mod W {}
940 pub mod RW {}
941 }
942 #[doc = "Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended"]
943 pub mod ENAUTOCLR_CLKGATE {
944 pub const offset: u32 = 19;
945 pub const mask: u32 = 0x01 << offset;
946 pub mod R {}
947 pub mod W {}
948 pub mod RW {}
949 }
950 #[doc = "Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended"]
951 pub mod ENAUTOCLR_PHY_PWD {
952 pub const offset: u32 = 20;
953 pub const mask: u32 = 0x01 << offset;
954 pub mod R {}
955 pub mod W {}
956 pub mod RW {}
957 }
958 #[doc = "Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended"]
959 pub mod ENDPDMCHG_WKUP {
960 pub const offset: u32 = 21;
961 pub const mask: u32 = 0x01 << offset;
962 pub mod R {}
963 pub mod W {}
964 pub mod RW {}
965 }
966 #[doc = "Enables the feature to wakeup USB if ID is toggled when USB is suspended."]
967 pub mod ENIDCHG_WKUP {
968 pub const offset: u32 = 22;
969 pub const mask: u32 = 0x01 << offset;
970 pub mod R {}
971 pub mod W {}
972 pub mod RW {}
973 }
974 #[doc = "Enables the feature to wakeup USB if VBUS is toggled when USB is suspended."]
975 pub mod ENVBUSCHG_WKUP {
976 pub const offset: u32 = 23;
977 pub const mask: u32 = 0x01 << offset;
978 pub mod R {}
979 pub mod W {}
980 pub mod RW {}
981 }
982 #[doc = "Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet."]
983 pub mod FSDLL_RST_EN {
984 pub const offset: u32 = 24;
985 pub const mask: u32 = 0x01 << offset;
986 pub mod R {}
987 pub mod W {}
988 pub mod RW {}
989 }
990 #[doc = "Almost same as OTGID_STATUS in USBPHYx_STATUS Register"]
991 pub mod OTG_ID_VALUE {
992 pub const offset: u32 = 27;
993 pub const mask: u32 = 0x01 << offset;
994 pub mod R {}
995 pub mod W {}
996 pub mod RW {}
997 }
998 #[doc = "Forces the next FS packet that is transmitted to have a EOP with LS timing"]
999 pub mod HOST_FORCE_LS_SE0 {
1000 pub const offset: u32 = 28;
1001 pub const mask: u32 = 0x01 << offset;
1002 pub mod R {}
1003 pub mod W {}
1004 pub mod RW {}
1005 }
1006 #[doc = "Used by the PHY to indicate a powered-down state"]
1007 pub mod UTMI_SUSPENDM {
1008 pub const offset: u32 = 29;
1009 pub const mask: u32 = 0x01 << offset;
1010 pub mod R {}
1011 pub mod W {}
1012 pub mod RW {}
1013 }
1014 #[doc = "Gate UTMI Clocks"]
1015 pub mod CLKGATE {
1016 pub const offset: u32 = 30;
1017 pub const mask: u32 = 0x01 << offset;
1018 pub mod R {}
1019 pub mod W {}
1020 pub mod RW {}
1021 }
1022 #[doc = "Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers"]
1023 pub mod SFTRST {
1024 pub const offset: u32 = 31;
1025 pub const mask: u32 = 0x01 << offset;
1026 pub mod R {}
1027 pub mod W {}
1028 pub mod RW {}
1029 }
1030}
1031#[doc = "USB PHY General Control Register"]
1032pub mod CTRL_CLR {
1033 #[doc = "Enable OTG_ID_CHG_IRQ."]
1034 pub mod ENOTG_ID_CHG_IRQ {
1035 pub const offset: u32 = 0;
1036 pub const mask: u32 = 0x01 << offset;
1037 pub mod R {}
1038 pub mod W {}
1039 pub mod RW {}
1040 }
1041 #[doc = "For host mode, enables high-speed disconnect detector"]
1042 pub mod ENHOSTDISCONDETECT {
1043 pub const offset: u32 = 1;
1044 pub const mask: u32 = 0x01 << offset;
1045 pub mod R {}
1046 pub mod W {}
1047 pub mod RW {}
1048 }
1049 #[doc = "Enables interrupt for detection of disconnection to Device when in high-speed host mode"]
1050 pub mod ENIRQHOSTDISCON {
1051 pub const offset: u32 = 2;
1052 pub const mask: u32 = 0x01 << offset;
1053 pub mod R {}
1054 pub mod W {}
1055 pub mod RW {}
1056 }
1057 #[doc = "Indicates that the device has disconnected in high-speed mode"]
1058 pub mod HOSTDISCONDETECT_IRQ {
1059 pub const offset: u32 = 3;
1060 pub const mask: u32 = 0x01 << offset;
1061 pub mod R {}
1062 pub mod W {}
1063 pub mod RW {}
1064 }
1065 #[doc = "For device mode, enables 200-KOhm pullups for detecting connectivity to the host."]
1066 pub mod ENDEVPLUGINDETECT {
1067 pub const offset: u32 = 4;
1068 pub const mask: u32 = 0x01 << offset;
1069 pub mod R {}
1070 pub mod W {}
1071 pub mod RW {}
1072 }
1073 #[doc = "For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in"]
1074 pub mod DEVPLUGIN_POLARITY {
1075 pub const offset: u32 = 5;
1076 pub const mask: u32 = 0x01 << offset;
1077 pub mod R {}
1078 pub mod W {}
1079 pub mod RW {}
1080 }
1081 #[doc = "OTG ID change interrupt. Indicates the value of ID pin changed."]
1082 pub mod OTG_ID_CHG_IRQ {
1083 pub const offset: u32 = 6;
1084 pub const mask: u32 = 0x01 << offset;
1085 pub mod R {}
1086 pub mod W {}
1087 pub mod RW {}
1088 }
1089 #[doc = "Enables circuit to detect resistance of MiniAB ID pin."]
1090 pub mod ENOTGIDDETECT {
1091 pub const offset: u32 = 7;
1092 pub const mask: u32 = 0x01 << offset;
1093 pub mod R {}
1094 pub mod W {}
1095 pub mod RW {}
1096 }
1097 #[doc = "Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it"]
1098 pub mod RESUMEIRQSTICKY {
1099 pub const offset: u32 = 8;
1100 pub const mask: u32 = 0x01 << offset;
1101 pub mod R {}
1102 pub mod W {}
1103 pub mod RW {}
1104 }
1105 #[doc = "Enables interrupt for detection of a non-J state on the USB line"]
1106 pub mod ENIRQRESUMEDETECT {
1107 pub const offset: u32 = 9;
1108 pub const mask: u32 = 0x01 << offset;
1109 pub mod R {}
1110 pub mod W {}
1111 pub mod RW {}
1112 }
1113 #[doc = "Indicates that the host is sending a wake-up after suspend"]
1114 pub mod RESUME_IRQ {
1115 pub const offset: u32 = 10;
1116 pub const mask: u32 = 0x01 << offset;
1117 pub mod R {}
1118 pub mod W {}
1119 pub mod RW {}
1120 }
1121 #[doc = "Enables interrupt for the detection of connectivity to the USB line."]
1122 pub mod ENIRQDEVPLUGIN {
1123 pub const offset: u32 = 11;
1124 pub const mask: u32 = 0x01 << offset;
1125 pub mod R {}
1126 pub mod W {}
1127 pub mod RW {}
1128 }
1129 #[doc = "Indicates that the device is connected"]
1130 pub mod DEVPLUGIN_IRQ {
1131 pub const offset: u32 = 12;
1132 pub const mask: u32 = 0x01 << offset;
1133 pub mod R {}
1134 pub mod W {}
1135 pub mod RW {}
1136 }
1137 #[doc = "Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only."]
1138 pub mod DATA_ON_LRADC {
1139 pub const offset: u32 = 13;
1140 pub const mask: u32 = 0x01 << offset;
1141 pub mod R {}
1142 pub mod W {}
1143 pub mod RW {}
1144 }
1145 #[doc = "Enables UTMI+ Level2. This should be enabled if needs to support LS device"]
1146 pub mod ENUTMILEVEL2 {
1147 pub const offset: u32 = 14;
1148 pub const mask: u32 = 0x01 << offset;
1149 pub mod R {}
1150 pub mod W {}
1151 pub mod RW {}
1152 }
1153 #[doc = "Enables UTMI+ Level3"]
1154 pub mod ENUTMILEVEL3 {
1155 pub const offset: u32 = 15;
1156 pub const mask: u32 = 0x01 << offset;
1157 pub mod R {}
1158 pub mod W {}
1159 pub mod RW {}
1160 }
1161 #[doc = "Enables interrupt for the wakeup events."]
1162 pub mod ENIRQWAKEUP {
1163 pub const offset: u32 = 16;
1164 pub const mask: u32 = 0x01 << offset;
1165 pub mod R {}
1166 pub mod W {}
1167 pub mod RW {}
1168 }
1169 #[doc = "Indicates that there is a wakeup event"]
1170 pub mod WAKEUP_IRQ {
1171 pub const offset: u32 = 17;
1172 pub const mask: u32 = 0x01 << offset;
1173 pub mod R {}
1174 pub mod W {}
1175 pub mod RW {}
1176 }
1177 #[doc = "Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended"]
1178 pub mod ENAUTO_PWRON_PLL {
1179 pub const offset: u32 = 18;
1180 pub const mask: u32 = 0x01 << offset;
1181 pub mod R {}
1182 pub mod W {}
1183 pub mod RW {}
1184 }
1185 #[doc = "Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended"]
1186 pub mod ENAUTOCLR_CLKGATE {
1187 pub const offset: u32 = 19;
1188 pub const mask: u32 = 0x01 << offset;
1189 pub mod R {}
1190 pub mod W {}
1191 pub mod RW {}
1192 }
1193 #[doc = "Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended"]
1194 pub mod ENAUTOCLR_PHY_PWD {
1195 pub const offset: u32 = 20;
1196 pub const mask: u32 = 0x01 << offset;
1197 pub mod R {}
1198 pub mod W {}
1199 pub mod RW {}
1200 }
1201 #[doc = "Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended"]
1202 pub mod ENDPDMCHG_WKUP {
1203 pub const offset: u32 = 21;
1204 pub const mask: u32 = 0x01 << offset;
1205 pub mod R {}
1206 pub mod W {}
1207 pub mod RW {}
1208 }
1209 #[doc = "Enables the feature to wakeup USB if ID is toggled when USB is suspended."]
1210 pub mod ENIDCHG_WKUP {
1211 pub const offset: u32 = 22;
1212 pub const mask: u32 = 0x01 << offset;
1213 pub mod R {}
1214 pub mod W {}
1215 pub mod RW {}
1216 }
1217 #[doc = "Enables the feature to wakeup USB if VBUS is toggled when USB is suspended."]
1218 pub mod ENVBUSCHG_WKUP {
1219 pub const offset: u32 = 23;
1220 pub const mask: u32 = 0x01 << offset;
1221 pub mod R {}
1222 pub mod W {}
1223 pub mod RW {}
1224 }
1225 #[doc = "Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet."]
1226 pub mod FSDLL_RST_EN {
1227 pub const offset: u32 = 24;
1228 pub const mask: u32 = 0x01 << offset;
1229 pub mod R {}
1230 pub mod W {}
1231 pub mod RW {}
1232 }
1233 #[doc = "Almost same as OTGID_STATUS in USBPHYx_STATUS Register"]
1234 pub mod OTG_ID_VALUE {
1235 pub const offset: u32 = 27;
1236 pub const mask: u32 = 0x01 << offset;
1237 pub mod R {}
1238 pub mod W {}
1239 pub mod RW {}
1240 }
1241 #[doc = "Forces the next FS packet that is transmitted to have a EOP with LS timing"]
1242 pub mod HOST_FORCE_LS_SE0 {
1243 pub const offset: u32 = 28;
1244 pub const mask: u32 = 0x01 << offset;
1245 pub mod R {}
1246 pub mod W {}
1247 pub mod RW {}
1248 }
1249 #[doc = "Used by the PHY to indicate a powered-down state"]
1250 pub mod UTMI_SUSPENDM {
1251 pub const offset: u32 = 29;
1252 pub const mask: u32 = 0x01 << offset;
1253 pub mod R {}
1254 pub mod W {}
1255 pub mod RW {}
1256 }
1257 #[doc = "Gate UTMI Clocks"]
1258 pub mod CLKGATE {
1259 pub const offset: u32 = 30;
1260 pub const mask: u32 = 0x01 << offset;
1261 pub mod R {}
1262 pub mod W {}
1263 pub mod RW {}
1264 }
1265 #[doc = "Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers"]
1266 pub mod SFTRST {
1267 pub const offset: u32 = 31;
1268 pub const mask: u32 = 0x01 << offset;
1269 pub mod R {}
1270 pub mod W {}
1271 pub mod RW {}
1272 }
1273}
1274#[doc = "USB PHY General Control Register"]
1275pub mod CTRL_TOG {
1276 #[doc = "Enable OTG_ID_CHG_IRQ."]
1277 pub mod ENOTG_ID_CHG_IRQ {
1278 pub const offset: u32 = 0;
1279 pub const mask: u32 = 0x01 << offset;
1280 pub mod R {}
1281 pub mod W {}
1282 pub mod RW {}
1283 }
1284 #[doc = "For host mode, enables high-speed disconnect detector"]
1285 pub mod ENHOSTDISCONDETECT {
1286 pub const offset: u32 = 1;
1287 pub const mask: u32 = 0x01 << offset;
1288 pub mod R {}
1289 pub mod W {}
1290 pub mod RW {}
1291 }
1292 #[doc = "Enables interrupt for detection of disconnection to Device when in high-speed host mode"]
1293 pub mod ENIRQHOSTDISCON {
1294 pub const offset: u32 = 2;
1295 pub const mask: u32 = 0x01 << offset;
1296 pub mod R {}
1297 pub mod W {}
1298 pub mod RW {}
1299 }
1300 #[doc = "Indicates that the device has disconnected in high-speed mode"]
1301 pub mod HOSTDISCONDETECT_IRQ {
1302 pub const offset: u32 = 3;
1303 pub const mask: u32 = 0x01 << offset;
1304 pub mod R {}
1305 pub mod W {}
1306 pub mod RW {}
1307 }
1308 #[doc = "For device mode, enables 200-KOhm pullups for detecting connectivity to the host."]
1309 pub mod ENDEVPLUGINDETECT {
1310 pub const offset: u32 = 4;
1311 pub const mask: u32 = 0x01 << offset;
1312 pub mod R {}
1313 pub mod W {}
1314 pub mod RW {}
1315 }
1316 #[doc = "For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in"]
1317 pub mod DEVPLUGIN_POLARITY {
1318 pub const offset: u32 = 5;
1319 pub const mask: u32 = 0x01 << offset;
1320 pub mod R {}
1321 pub mod W {}
1322 pub mod RW {}
1323 }
1324 #[doc = "OTG ID change interrupt. Indicates the value of ID pin changed."]
1325 pub mod OTG_ID_CHG_IRQ {
1326 pub const offset: u32 = 6;
1327 pub const mask: u32 = 0x01 << offset;
1328 pub mod R {}
1329 pub mod W {}
1330 pub mod RW {}
1331 }
1332 #[doc = "Enables circuit to detect resistance of MiniAB ID pin."]
1333 pub mod ENOTGIDDETECT {
1334 pub const offset: u32 = 7;
1335 pub const mask: u32 = 0x01 << offset;
1336 pub mod R {}
1337 pub mod W {}
1338 pub mod RW {}
1339 }
1340 #[doc = "Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it"]
1341 pub mod RESUMEIRQSTICKY {
1342 pub const offset: u32 = 8;
1343 pub const mask: u32 = 0x01 << offset;
1344 pub mod R {}
1345 pub mod W {}
1346 pub mod RW {}
1347 }
1348 #[doc = "Enables interrupt for detection of a non-J state on the USB line"]
1349 pub mod ENIRQRESUMEDETECT {
1350 pub const offset: u32 = 9;
1351 pub const mask: u32 = 0x01 << offset;
1352 pub mod R {}
1353 pub mod W {}
1354 pub mod RW {}
1355 }
1356 #[doc = "Indicates that the host is sending a wake-up after suspend"]
1357 pub mod RESUME_IRQ {
1358 pub const offset: u32 = 10;
1359 pub const mask: u32 = 0x01 << offset;
1360 pub mod R {}
1361 pub mod W {}
1362 pub mod RW {}
1363 }
1364 #[doc = "Enables interrupt for the detection of connectivity to the USB line."]
1365 pub mod ENIRQDEVPLUGIN {
1366 pub const offset: u32 = 11;
1367 pub const mask: u32 = 0x01 << offset;
1368 pub mod R {}
1369 pub mod W {}
1370 pub mod RW {}
1371 }
1372 #[doc = "Indicates that the device is connected"]
1373 pub mod DEVPLUGIN_IRQ {
1374 pub const offset: u32 = 12;
1375 pub const mask: u32 = 0x01 << offset;
1376 pub mod R {}
1377 pub mod W {}
1378 pub mod RW {}
1379 }
1380 #[doc = "Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only."]
1381 pub mod DATA_ON_LRADC {
1382 pub const offset: u32 = 13;
1383 pub const mask: u32 = 0x01 << offset;
1384 pub mod R {}
1385 pub mod W {}
1386 pub mod RW {}
1387 }
1388 #[doc = "Enables UTMI+ Level2. This should be enabled if needs to support LS device"]
1389 pub mod ENUTMILEVEL2 {
1390 pub const offset: u32 = 14;
1391 pub const mask: u32 = 0x01 << offset;
1392 pub mod R {}
1393 pub mod W {}
1394 pub mod RW {}
1395 }
1396 #[doc = "Enables UTMI+ Level3"]
1397 pub mod ENUTMILEVEL3 {
1398 pub const offset: u32 = 15;
1399 pub const mask: u32 = 0x01 << offset;
1400 pub mod R {}
1401 pub mod W {}
1402 pub mod RW {}
1403 }
1404 #[doc = "Enables interrupt for the wakeup events."]
1405 pub mod ENIRQWAKEUP {
1406 pub const offset: u32 = 16;
1407 pub const mask: u32 = 0x01 << offset;
1408 pub mod R {}
1409 pub mod W {}
1410 pub mod RW {}
1411 }
1412 #[doc = "Indicates that there is a wakeup event"]
1413 pub mod WAKEUP_IRQ {
1414 pub const offset: u32 = 17;
1415 pub const mask: u32 = 0x01 << offset;
1416 pub mod R {}
1417 pub mod W {}
1418 pub mod RW {}
1419 }
1420 #[doc = "Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended"]
1421 pub mod ENAUTO_PWRON_PLL {
1422 pub const offset: u32 = 18;
1423 pub const mask: u32 = 0x01 << offset;
1424 pub mod R {}
1425 pub mod W {}
1426 pub mod RW {}
1427 }
1428 #[doc = "Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended"]
1429 pub mod ENAUTOCLR_CLKGATE {
1430 pub const offset: u32 = 19;
1431 pub const mask: u32 = 0x01 << offset;
1432 pub mod R {}
1433 pub mod W {}
1434 pub mod RW {}
1435 }
1436 #[doc = "Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended"]
1437 pub mod ENAUTOCLR_PHY_PWD {
1438 pub const offset: u32 = 20;
1439 pub const mask: u32 = 0x01 << offset;
1440 pub mod R {}
1441 pub mod W {}
1442 pub mod RW {}
1443 }
1444 #[doc = "Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended"]
1445 pub mod ENDPDMCHG_WKUP {
1446 pub const offset: u32 = 21;
1447 pub const mask: u32 = 0x01 << offset;
1448 pub mod R {}
1449 pub mod W {}
1450 pub mod RW {}
1451 }
1452 #[doc = "Enables the feature to wakeup USB if ID is toggled when USB is suspended."]
1453 pub mod ENIDCHG_WKUP {
1454 pub const offset: u32 = 22;
1455 pub const mask: u32 = 0x01 << offset;
1456 pub mod R {}
1457 pub mod W {}
1458 pub mod RW {}
1459 }
1460 #[doc = "Enables the feature to wakeup USB if VBUS is toggled when USB is suspended."]
1461 pub mod ENVBUSCHG_WKUP {
1462 pub const offset: u32 = 23;
1463 pub const mask: u32 = 0x01 << offset;
1464 pub mod R {}
1465 pub mod W {}
1466 pub mod RW {}
1467 }
1468 #[doc = "Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet."]
1469 pub mod FSDLL_RST_EN {
1470 pub const offset: u32 = 24;
1471 pub const mask: u32 = 0x01 << offset;
1472 pub mod R {}
1473 pub mod W {}
1474 pub mod RW {}
1475 }
1476 #[doc = "Almost same as OTGID_STATUS in USBPHYx_STATUS Register"]
1477 pub mod OTG_ID_VALUE {
1478 pub const offset: u32 = 27;
1479 pub const mask: u32 = 0x01 << offset;
1480 pub mod R {}
1481 pub mod W {}
1482 pub mod RW {}
1483 }
1484 #[doc = "Forces the next FS packet that is transmitted to have a EOP with LS timing"]
1485 pub mod HOST_FORCE_LS_SE0 {
1486 pub const offset: u32 = 28;
1487 pub const mask: u32 = 0x01 << offset;
1488 pub mod R {}
1489 pub mod W {}
1490 pub mod RW {}
1491 }
1492 #[doc = "Used by the PHY to indicate a powered-down state"]
1493 pub mod UTMI_SUSPENDM {
1494 pub const offset: u32 = 29;
1495 pub const mask: u32 = 0x01 << offset;
1496 pub mod R {}
1497 pub mod W {}
1498 pub mod RW {}
1499 }
1500 #[doc = "Gate UTMI Clocks"]
1501 pub mod CLKGATE {
1502 pub const offset: u32 = 30;
1503 pub const mask: u32 = 0x01 << offset;
1504 pub mod R {}
1505 pub mod W {}
1506 pub mod RW {}
1507 }
1508 #[doc = "Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers"]
1509 pub mod SFTRST {
1510 pub const offset: u32 = 31;
1511 pub const mask: u32 = 0x01 << offset;
1512 pub mod R {}
1513 pub mod W {}
1514 pub mod RW {}
1515 }
1516}
1517#[doc = "USB PHY Status Register"]
1518pub mod STATUS {
1519 #[doc = "Indicates that the device has disconnected while in high-speed host mode."]
1520 pub mod HOSTDISCONDETECT_STATUS {
1521 pub const offset: u32 = 3;
1522 pub const mask: u32 = 0x01 << offset;
1523 pub mod R {}
1524 pub mod W {}
1525 pub mod RW {}
1526 }
1527 #[doc = "Indicates that the device has been connected on the USB_DP and USB_DM lines."]
1528 pub mod DEVPLUGIN_STATUS {
1529 pub const offset: u32 = 6;
1530 pub const mask: u32 = 0x01 << offset;
1531 pub mod R {}
1532 pub mod W {}
1533 pub mod RW {}
1534 }
1535 #[doc = "Indicates the results of ID pin on MiniAB plug"]
1536 pub mod OTGID_STATUS {
1537 pub const offset: u32 = 8;
1538 pub const mask: u32 = 0x01 << offset;
1539 pub mod R {}
1540 pub mod W {}
1541 pub mod RW {}
1542 }
1543 #[doc = "Indicates that the host is sending a wake-up after suspend and has triggered an interrupt."]
1544 pub mod RESUME_STATUS {
1545 pub const offset: u32 = 10;
1546 pub const mask: u32 = 0x01 << offset;
1547 pub mod R {}
1548 pub mod W {}
1549 pub mod RW {}
1550 }
1551}
1552#[doc = "USB PHY Debug Register"]
1553pub mod DEBUG {
1554 #[doc = "Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value"]
1555 pub mod OTGIDPIOLOCK {
1556 pub const offset: u32 = 0;
1557 pub const mask: u32 = 0x01 << offset;
1558 pub mod R {}
1559 pub mod W {}
1560 pub mod RW {}
1561 }
1562 #[doc = "Use holding registers to assist in timing for external UTMI interface."]
1563 pub mod DEBUG_INTERFACE_HOLD {
1564 pub const offset: u32 = 1;
1565 pub const mask: u32 = 0x01 << offset;
1566 pub mod R {}
1567 pub mod W {}
1568 pub mod RW {}
1569 }
1570 #[doc = "Set bit 3 to 1 to pull down 15-KOhm on USB_DP line"]
1571 pub mod HSTPULLDOWN {
1572 pub const offset: u32 = 2;
1573 pub const mask: u32 = 0x03 << offset;
1574 pub mod R {}
1575 pub mod W {}
1576 pub mod RW {}
1577 }
1578 #[doc = "Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown"]
1579 pub mod ENHSTPULLDOWN {
1580 pub const offset: u32 = 4;
1581 pub const mask: u32 = 0x03 << offset;
1582 pub mod R {}
1583 pub mod W {}
1584 pub mod RW {}
1585 }
1586 #[doc = "Delay in between the end of transmit to the beginning of receive"]
1587 pub mod TX2RXCOUNT {
1588 pub const offset: u32 = 8;
1589 pub const mask: u32 = 0x0f << offset;
1590 pub mod R {}
1591 pub mod W {}
1592 pub mod RW {}
1593 }
1594 #[doc = "Set this bit to allow a countdown to transition in between TX and RX."]
1595 pub mod ENTX2RXCOUNT {
1596 pub const offset: u32 = 12;
1597 pub const mask: u32 = 0x01 << offset;
1598 pub mod R {}
1599 pub mod W {}
1600 pub mod RW {}
1601 }
1602 #[doc = "Delay in between the detection of squelch to the reset of high-speed RX."]
1603 pub mod SQUELCHRESETCOUNT {
1604 pub const offset: u32 = 16;
1605 pub const mask: u32 = 0x1f << offset;
1606 pub mod R {}
1607 pub mod W {}
1608 pub mod RW {}
1609 }
1610 #[doc = "Set bit to allow squelch to reset high-speed receive."]
1611 pub mod ENSQUELCHRESET {
1612 pub const offset: u32 = 24;
1613 pub const mask: u32 = 0x01 << offset;
1614 pub mod R {}
1615 pub mod W {}
1616 pub mod RW {}
1617 }
1618 #[doc = "Duration of RESET in terms of the number of 480-MHz cycles."]
1619 pub mod SQUELCHRESETLENGTH {
1620 pub const offset: u32 = 25;
1621 pub const mask: u32 = 0x0f << offset;
1622 pub mod R {}
1623 pub mod W {}
1624 pub mod RW {}
1625 }
1626 #[doc = "Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1."]
1627 pub mod HOST_RESUME_DEBUG {
1628 pub const offset: u32 = 29;
1629 pub const mask: u32 = 0x01 << offset;
1630 pub mod R {}
1631 pub mod W {}
1632 pub mod RW {}
1633 }
1634 #[doc = "Gate Test Clocks"]
1635 pub mod CLKGATE {
1636 pub const offset: u32 = 30;
1637 pub const mask: u32 = 0x01 << offset;
1638 pub mod R {}
1639 pub mod W {}
1640 pub mod RW {}
1641 }
1642}
1643#[doc = "USB PHY Debug Register"]
1644pub mod DEBUG_SET {
1645 #[doc = "Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value"]
1646 pub mod OTGIDPIOLOCK {
1647 pub const offset: u32 = 0;
1648 pub const mask: u32 = 0x01 << offset;
1649 pub mod R {}
1650 pub mod W {}
1651 pub mod RW {}
1652 }
1653 #[doc = "Use holding registers to assist in timing for external UTMI interface."]
1654 pub mod DEBUG_INTERFACE_HOLD {
1655 pub const offset: u32 = 1;
1656 pub const mask: u32 = 0x01 << offset;
1657 pub mod R {}
1658 pub mod W {}
1659 pub mod RW {}
1660 }
1661 #[doc = "Set bit 3 to 1 to pull down 15-KOhm on USB_DP line"]
1662 pub mod HSTPULLDOWN {
1663 pub const offset: u32 = 2;
1664 pub const mask: u32 = 0x03 << offset;
1665 pub mod R {}
1666 pub mod W {}
1667 pub mod RW {}
1668 }
1669 #[doc = "Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown"]
1670 pub mod ENHSTPULLDOWN {
1671 pub const offset: u32 = 4;
1672 pub const mask: u32 = 0x03 << offset;
1673 pub mod R {}
1674 pub mod W {}
1675 pub mod RW {}
1676 }
1677 #[doc = "Delay in between the end of transmit to the beginning of receive"]
1678 pub mod TX2RXCOUNT {
1679 pub const offset: u32 = 8;
1680 pub const mask: u32 = 0x0f << offset;
1681 pub mod R {}
1682 pub mod W {}
1683 pub mod RW {}
1684 }
1685 #[doc = "Set this bit to allow a countdown to transition in between TX and RX."]
1686 pub mod ENTX2RXCOUNT {
1687 pub const offset: u32 = 12;
1688 pub const mask: u32 = 0x01 << offset;
1689 pub mod R {}
1690 pub mod W {}
1691 pub mod RW {}
1692 }
1693 #[doc = "Delay in between the detection of squelch to the reset of high-speed RX."]
1694 pub mod SQUELCHRESETCOUNT {
1695 pub const offset: u32 = 16;
1696 pub const mask: u32 = 0x1f << offset;
1697 pub mod R {}
1698 pub mod W {}
1699 pub mod RW {}
1700 }
1701 #[doc = "Set bit to allow squelch to reset high-speed receive."]
1702 pub mod ENSQUELCHRESET {
1703 pub const offset: u32 = 24;
1704 pub const mask: u32 = 0x01 << offset;
1705 pub mod R {}
1706 pub mod W {}
1707 pub mod RW {}
1708 }
1709 #[doc = "Duration of RESET in terms of the number of 480-MHz cycles."]
1710 pub mod SQUELCHRESETLENGTH {
1711 pub const offset: u32 = 25;
1712 pub const mask: u32 = 0x0f << offset;
1713 pub mod R {}
1714 pub mod W {}
1715 pub mod RW {}
1716 }
1717 #[doc = "Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1."]
1718 pub mod HOST_RESUME_DEBUG {
1719 pub const offset: u32 = 29;
1720 pub const mask: u32 = 0x01 << offset;
1721 pub mod R {}
1722 pub mod W {}
1723 pub mod RW {}
1724 }
1725 #[doc = "Gate Test Clocks"]
1726 pub mod CLKGATE {
1727 pub const offset: u32 = 30;
1728 pub const mask: u32 = 0x01 << offset;
1729 pub mod R {}
1730 pub mod W {}
1731 pub mod RW {}
1732 }
1733}
1734#[doc = "USB PHY Debug Register"]
1735pub mod DEBUG_CLR {
1736 #[doc = "Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value"]
1737 pub mod OTGIDPIOLOCK {
1738 pub const offset: u32 = 0;
1739 pub const mask: u32 = 0x01 << offset;
1740 pub mod R {}
1741 pub mod W {}
1742 pub mod RW {}
1743 }
1744 #[doc = "Use holding registers to assist in timing for external UTMI interface."]
1745 pub mod DEBUG_INTERFACE_HOLD {
1746 pub const offset: u32 = 1;
1747 pub const mask: u32 = 0x01 << offset;
1748 pub mod R {}
1749 pub mod W {}
1750 pub mod RW {}
1751 }
1752 #[doc = "Set bit 3 to 1 to pull down 15-KOhm on USB_DP line"]
1753 pub mod HSTPULLDOWN {
1754 pub const offset: u32 = 2;
1755 pub const mask: u32 = 0x03 << offset;
1756 pub mod R {}
1757 pub mod W {}
1758 pub mod RW {}
1759 }
1760 #[doc = "Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown"]
1761 pub mod ENHSTPULLDOWN {
1762 pub const offset: u32 = 4;
1763 pub const mask: u32 = 0x03 << offset;
1764 pub mod R {}
1765 pub mod W {}
1766 pub mod RW {}
1767 }
1768 #[doc = "Delay in between the end of transmit to the beginning of receive"]
1769 pub mod TX2RXCOUNT {
1770 pub const offset: u32 = 8;
1771 pub const mask: u32 = 0x0f << offset;
1772 pub mod R {}
1773 pub mod W {}
1774 pub mod RW {}
1775 }
1776 #[doc = "Set this bit to allow a countdown to transition in between TX and RX."]
1777 pub mod ENTX2RXCOUNT {
1778 pub const offset: u32 = 12;
1779 pub const mask: u32 = 0x01 << offset;
1780 pub mod R {}
1781 pub mod W {}
1782 pub mod RW {}
1783 }
1784 #[doc = "Delay in between the detection of squelch to the reset of high-speed RX."]
1785 pub mod SQUELCHRESETCOUNT {
1786 pub const offset: u32 = 16;
1787 pub const mask: u32 = 0x1f << offset;
1788 pub mod R {}
1789 pub mod W {}
1790 pub mod RW {}
1791 }
1792 #[doc = "Set bit to allow squelch to reset high-speed receive."]
1793 pub mod ENSQUELCHRESET {
1794 pub const offset: u32 = 24;
1795 pub const mask: u32 = 0x01 << offset;
1796 pub mod R {}
1797 pub mod W {}
1798 pub mod RW {}
1799 }
1800 #[doc = "Duration of RESET in terms of the number of 480-MHz cycles."]
1801 pub mod SQUELCHRESETLENGTH {
1802 pub const offset: u32 = 25;
1803 pub const mask: u32 = 0x0f << offset;
1804 pub mod R {}
1805 pub mod W {}
1806 pub mod RW {}
1807 }
1808 #[doc = "Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1."]
1809 pub mod HOST_RESUME_DEBUG {
1810 pub const offset: u32 = 29;
1811 pub const mask: u32 = 0x01 << offset;
1812 pub mod R {}
1813 pub mod W {}
1814 pub mod RW {}
1815 }
1816 #[doc = "Gate Test Clocks"]
1817 pub mod CLKGATE {
1818 pub const offset: u32 = 30;
1819 pub const mask: u32 = 0x01 << offset;
1820 pub mod R {}
1821 pub mod W {}
1822 pub mod RW {}
1823 }
1824}
1825#[doc = "USB PHY Debug Register"]
1826pub mod DEBUG_TOG {
1827 #[doc = "Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value"]
1828 pub mod OTGIDPIOLOCK {
1829 pub const offset: u32 = 0;
1830 pub const mask: u32 = 0x01 << offset;
1831 pub mod R {}
1832 pub mod W {}
1833 pub mod RW {}
1834 }
1835 #[doc = "Use holding registers to assist in timing for external UTMI interface."]
1836 pub mod DEBUG_INTERFACE_HOLD {
1837 pub const offset: u32 = 1;
1838 pub const mask: u32 = 0x01 << offset;
1839 pub mod R {}
1840 pub mod W {}
1841 pub mod RW {}
1842 }
1843 #[doc = "Set bit 3 to 1 to pull down 15-KOhm on USB_DP line"]
1844 pub mod HSTPULLDOWN {
1845 pub const offset: u32 = 2;
1846 pub const mask: u32 = 0x03 << offset;
1847 pub mod R {}
1848 pub mod W {}
1849 pub mod RW {}
1850 }
1851 #[doc = "Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown"]
1852 pub mod ENHSTPULLDOWN {
1853 pub const offset: u32 = 4;
1854 pub const mask: u32 = 0x03 << offset;
1855 pub mod R {}
1856 pub mod W {}
1857 pub mod RW {}
1858 }
1859 #[doc = "Delay in between the end of transmit to the beginning of receive"]
1860 pub mod TX2RXCOUNT {
1861 pub const offset: u32 = 8;
1862 pub const mask: u32 = 0x0f << offset;
1863 pub mod R {}
1864 pub mod W {}
1865 pub mod RW {}
1866 }
1867 #[doc = "Set this bit to allow a countdown to transition in between TX and RX."]
1868 pub mod ENTX2RXCOUNT {
1869 pub const offset: u32 = 12;
1870 pub const mask: u32 = 0x01 << offset;
1871 pub mod R {}
1872 pub mod W {}
1873 pub mod RW {}
1874 }
1875 #[doc = "Delay in between the detection of squelch to the reset of high-speed RX."]
1876 pub mod SQUELCHRESETCOUNT {
1877 pub const offset: u32 = 16;
1878 pub const mask: u32 = 0x1f << offset;
1879 pub mod R {}
1880 pub mod W {}
1881 pub mod RW {}
1882 }
1883 #[doc = "Set bit to allow squelch to reset high-speed receive."]
1884 pub mod ENSQUELCHRESET {
1885 pub const offset: u32 = 24;
1886 pub const mask: u32 = 0x01 << offset;
1887 pub mod R {}
1888 pub mod W {}
1889 pub mod RW {}
1890 }
1891 #[doc = "Duration of RESET in terms of the number of 480-MHz cycles."]
1892 pub mod SQUELCHRESETLENGTH {
1893 pub const offset: u32 = 25;
1894 pub const mask: u32 = 0x0f << offset;
1895 pub mod R {}
1896 pub mod W {}
1897 pub mod RW {}
1898 }
1899 #[doc = "Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1."]
1900 pub mod HOST_RESUME_DEBUG {
1901 pub const offset: u32 = 29;
1902 pub const mask: u32 = 0x01 << offset;
1903 pub mod R {}
1904 pub mod W {}
1905 pub mod RW {}
1906 }
1907 #[doc = "Gate Test Clocks"]
1908 pub mod CLKGATE {
1909 pub const offset: u32 = 30;
1910 pub const mask: u32 = 0x01 << offset;
1911 pub mod R {}
1912 pub mod W {}
1913 pub mod RW {}
1914 }
1915}
1916#[doc = "UTMI Debug Status Register 0"]
1917pub mod DEBUG0_STATUS {
1918 #[doc = "Running count of the failed pseudo-random generator loopback"]
1919 pub mod LOOP_BACK_FAIL_COUNT {
1920 pub const offset: u32 = 0;
1921 pub const mask: u32 = 0xffff << offset;
1922 pub mod R {}
1923 pub mod W {}
1924 pub mod RW {}
1925 }
1926 #[doc = "Running count of the UTMI_RXERROR."]
1927 pub mod UTMI_RXERROR_FAIL_COUNT {
1928 pub const offset: u32 = 16;
1929 pub const mask: u32 = 0x03ff << offset;
1930 pub mod R {}
1931 pub mod W {}
1932 pub mod RW {}
1933 }
1934 #[doc = "Running count of the squelch reset instead of normal end for HS RX."]
1935 pub mod SQUELCH_COUNT {
1936 pub const offset: u32 = 26;
1937 pub const mask: u32 = 0x3f << offset;
1938 pub mod R {}
1939 pub mod W {}
1940 pub mod RW {}
1941 }
1942}
1943#[doc = "UTMI Debug Status Register 1"]
1944pub mod DEBUG1 {
1945 #[doc = "Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%"]
1946 pub mod ENTAILADJVD {
1947 pub const offset: u32 = 13;
1948 pub const mask: u32 = 0x03 << offset;
1949 pub mod R {}
1950 pub mod W {}
1951 pub mod RW {}
1952 }
1953}
1954#[doc = "UTMI Debug Status Register 1"]
1955pub mod DEBUG1_SET {
1956 #[doc = "Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%"]
1957 pub mod ENTAILADJVD {
1958 pub const offset: u32 = 13;
1959 pub const mask: u32 = 0x03 << offset;
1960 pub mod R {}
1961 pub mod W {}
1962 pub mod RW {}
1963 }
1964}
1965#[doc = "UTMI Debug Status Register 1"]
1966pub mod DEBUG1_CLR {
1967 #[doc = "Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%"]
1968 pub mod ENTAILADJVD {
1969 pub const offset: u32 = 13;
1970 pub const mask: u32 = 0x03 << offset;
1971 pub mod R {}
1972 pub mod W {}
1973 pub mod RW {}
1974 }
1975}
1976#[doc = "UTMI Debug Status Register 1"]
1977pub mod DEBUG1_TOG {
1978 #[doc = "Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40%"]
1979 pub mod ENTAILADJVD {
1980 pub const offset: u32 = 13;
1981 pub const mask: u32 = 0x03 << offset;
1982 pub mod R {}
1983 pub mod W {}
1984 pub mod RW {}
1985 }
1986}
1987#[doc = "UTMI RTL Version"]
1988pub mod VERSION {
1989 #[doc = "Fixed read-only value reflecting the stepping of the RTL version."]
1990 pub mod STEP {
1991 pub const offset: u32 = 0;
1992 pub const mask: u32 = 0xffff << offset;
1993 pub mod R {}
1994 pub mod W {}
1995 pub mod RW {}
1996 }
1997 #[doc = "Fixed read-only value reflecting the MINOR field of the RTL version."]
1998 pub mod MINOR {
1999 pub const offset: u32 = 16;
2000 pub const mask: u32 = 0xff << offset;
2001 pub mod R {}
2002 pub mod W {}
2003 pub mod RW {}
2004 }
2005 #[doc = "Fixed read-only value reflecting the MAJOR field of the RTL version."]
2006 pub mod MAJOR {
2007 pub const offset: u32 = 24;
2008 pub const mask: u32 = 0xff << offset;
2009 pub mod R {}
2010 pub mod W {}
2011 pub mod RW {}
2012 }
2013}