imxrt_ral/blocks/imxrt1052/
csi.rs

1#[doc = "CSI"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "CSI Control Register 1"]
5    pub CSICR1: crate::RWRegister<u32>,
6    #[doc = "CSI Control Register 2"]
7    pub CSICR2: crate::RWRegister<u32>,
8    #[doc = "CSI Control Register 3"]
9    pub CSICR3: crate::RWRegister<u32>,
10    #[doc = "CSI Statistic FIFO Register"]
11    pub CSISTATFIFO: crate::RORegister<u32>,
12    #[doc = "CSI RX FIFO Register"]
13    pub CSIRFIFO: crate::RORegister<u32>,
14    #[doc = "CSI RX Count Register"]
15    pub CSIRXCNT: crate::RWRegister<u32>,
16    #[doc = "CSI Status Register"]
17    pub CSISR: crate::RWRegister<u32>,
18    _reserved0: [u8; 0x04],
19    #[doc = "CSI DMA Start Address Register - for STATFIFO"]
20    pub CSIDMASA_STATFIFO: crate::RWRegister<u32>,
21    #[doc = "CSI DMA Transfer Size Register - for STATFIFO"]
22    pub CSIDMATS_STATFIFO: crate::RWRegister<u32>,
23    #[doc = "CSI DMA Start Address Register - for Frame Buffer1"]
24    pub CSIDMASA_FB1: crate::RWRegister<u32>,
25    #[doc = "CSI DMA Transfer Size Register - for Frame Buffer2"]
26    pub CSIDMASA_FB2: crate::RWRegister<u32>,
27    #[doc = "CSI Frame Buffer Parameter Register"]
28    pub CSIFBUF_PARA: crate::RWRegister<u32>,
29    #[doc = "CSI Image Parameter Register"]
30    pub CSIIMAG_PARA: crate::RWRegister<u32>,
31    _reserved1: [u8; 0x10],
32    #[doc = "CSI Control Register 18"]
33    pub CSICR18: crate::RWRegister<u32>,
34    #[doc = "CSI Control Register 19"]
35    pub CSICR19: crate::RWRegister<u32>,
36}
37#[doc = "CSI Control Register 1"]
38pub mod CSICR1 {
39    #[doc = "Pixel Bit"]
40    pub mod PIXEL_BIT {
41        pub const offset: u32 = 0;
42        pub const mask: u32 = 0x01 << offset;
43        pub mod R {}
44        pub mod W {}
45        pub mod RW {
46            #[doc = "8-bit data for each pixel"]
47            pub const PIXEL_BIT_0: u32 = 0;
48            #[doc = "10-bit data for each pixel"]
49            pub const PIXEL_BIT_1: u32 = 0x01;
50        }
51    }
52    #[doc = "Valid Pixel Clock Edge Select"]
53    pub mod REDGE {
54        pub const offset: u32 = 1;
55        pub const mask: u32 = 0x01 << offset;
56        pub mod R {}
57        pub mod W {}
58        pub mod RW {
59            #[doc = "Pixel data is latched at the falling edge of CSI_PIXCLK"]
60            pub const REDGE_0: u32 = 0;
61            #[doc = "Pixel data is latched at the rising edge of CSI_PIXCLK"]
62            pub const REDGE_1: u32 = 0x01;
63        }
64    }
65    #[doc = "Invert Pixel Clock Input"]
66    pub mod INV_PCLK {
67        pub const offset: u32 = 2;
68        pub const mask: u32 = 0x01 << offset;
69        pub mod R {}
70        pub mod W {}
71        pub mod RW {
72            #[doc = "CSI_PIXCLK is directly applied to internal circuitry"]
73            pub const INV_PCLK_0: u32 = 0;
74            #[doc = "CSI_PIXCLK is inverted before applied to internal circuitry"]
75            pub const INV_PCLK_1: u32 = 0x01;
76        }
77    }
78    #[doc = "Invert Data Input. This bit enables or disables internal inverters on the data lines."]
79    pub mod INV_DATA {
80        pub const offset: u32 = 3;
81        pub const mask: u32 = 0x01 << offset;
82        pub mod R {}
83        pub mod W {}
84        pub mod RW {
85            #[doc = "CSI_D\\[7:0\\] data lines are directly applied to internal circuitry"]
86            pub const INV_DATA_0: u32 = 0;
87            #[doc = "CSI_D\\[7:0\\] data lines are inverted before applied to internal circuitry"]
88            pub const INV_DATA_1: u32 = 0x01;
89        }
90    }
91    #[doc = "Gated Clock Mode Enable"]
92    pub mod GCLK_MODE {
93        pub const offset: u32 = 4;
94        pub const mask: u32 = 0x01 << offset;
95        pub mod R {}
96        pub mod W {}
97        pub mod RW {
98            #[doc = "Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored."]
99            pub const GCLK_MODE_0: u32 = 0;
100            #[doc = "Gated clock mode. Pixel clock signal is valid only when HSYNC is active."]
101            pub const GCLK_MODE_1: u32 = 0x01;
102        }
103    }
104    #[doc = "Asynchronous RXFIFO Clear"]
105    pub mod CLR_RXFIFO {
106        pub const offset: u32 = 5;
107        pub const mask: u32 = 0x01 << offset;
108        pub mod R {}
109        pub mod W {}
110        pub mod RW {}
111    }
112    #[doc = "Asynchronous STATFIFO Clear"]
113    pub mod CLR_STATFIFO {
114        pub const offset: u32 = 6;
115        pub const mask: u32 = 0x01 << offset;
116        pub mod R {}
117        pub mod W {}
118        pub mod RW {}
119    }
120    #[doc = "Data Packing Direction"]
121    pub mod PACK_DIR {
122        pub const offset: u32 = 7;
123        pub const mask: u32 = 0x01 << offset;
124        pub mod R {}
125        pub mod W {}
126        pub mod RW {
127            #[doc = "Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO."]
128            pub const PACK_DIR_0: u32 = 0;
129            #[doc = "Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO."]
130            pub const PACK_DIR_1: u32 = 0x01;
131        }
132    }
133    #[doc = "FIFO Clear Control"]
134    pub mod FCC {
135        pub const offset: u32 = 8;
136        pub const mask: u32 = 0x01 << offset;
137        pub mod R {}
138        pub mod W {}
139        pub mod RW {
140            #[doc = "Asynchronous FIFO clear is selected."]
141            pub const FCC_0: u32 = 0;
142            #[doc = "Synchronous FIFO clear is selected."]
143            pub const FCC_1: u32 = 0x01;
144        }
145    }
146    #[doc = "CCIR656 Interface Enable"]
147    pub mod CCIR_EN {
148        pub const offset: u32 = 10;
149        pub const mask: u32 = 0x01 << offset;
150        pub mod R {}
151        pub mod W {}
152        pub mod RW {
153            #[doc = "Traditional interface is selected. Timing interface logic is used to latch data."]
154            pub const CCIR_EN_0: u32 = 0;
155            #[doc = "CCIR656 interface is selected."]
156            pub const CCIR_EN_1: u32 = 0x01;
157        }
158    }
159    #[doc = "HSYNC Polarity Select"]
160    pub mod HSYNC_POL {
161        pub const offset: u32 = 11;
162        pub const mask: u32 = 0x01 << offset;
163        pub mod R {}
164        pub mod W {}
165        pub mod RW {
166            #[doc = "HSYNC is active low"]
167            pub const HSYNC_POL_0: u32 = 0;
168            #[doc = "HSYNC is active high"]
169            pub const HSYNC_POL_1: u32 = 0x01;
170        }
171    }
172    #[doc = "Start Of Frame (SOF) Interrupt Enable. This bit enables the SOF interrupt."]
173    pub mod SOF_INTEN {
174        pub const offset: u32 = 16;
175        pub const mask: u32 = 0x01 << offset;
176        pub mod R {}
177        pub mod W {}
178        pub mod RW {
179            #[doc = "SOF interrupt disable"]
180            pub const SOF_INTEN_0: u32 = 0;
181            #[doc = "SOF interrupt enable"]
182            pub const SOF_INTEN_1: u32 = 0x01;
183        }
184    }
185    #[doc = "SOF Interrupt Polarity. This bit controls the condition that generates an SOF interrupt."]
186    pub mod SOF_POL {
187        pub const offset: u32 = 17;
188        pub const mask: u32 = 0x01 << offset;
189        pub mod R {}
190        pub mod W {}
191        pub mod RW {
192            #[doc = "SOF interrupt is generated on SOF falling edge"]
193            pub const SOF_POL_0: u32 = 0;
194            #[doc = "SOF interrupt is generated on SOF rising edge"]
195            pub const SOF_POL_1: u32 = 0x01;
196        }
197    }
198    #[doc = "RxFIFO Full Interrupt Enable. This bit enables the RxFIFO full interrupt."]
199    pub mod RXFF_INTEN {
200        pub const offset: u32 = 18;
201        pub const mask: u32 = 0x01 << offset;
202        pub mod R {}
203        pub mod W {}
204        pub mod RW {
205            #[doc = "RxFIFO full interrupt disable"]
206            pub const RXFF_INTEN_0: u32 = 0;
207            #[doc = "RxFIFO full interrupt enable"]
208            pub const RXFF_INTEN_1: u32 = 0x01;
209        }
210    }
211    #[doc = "Frame Buffer1 DMA Transfer Done Interrupt Enable"]
212    pub mod FB1_DMA_DONE_INTEN {
213        pub const offset: u32 = 19;
214        pub const mask: u32 = 0x01 << offset;
215        pub mod R {}
216        pub mod W {}
217        pub mod RW {
218            #[doc = "Frame Buffer1 DMA Transfer Done interrupt disable"]
219            pub const FB1_DMA_DONE_INTEN_0: u32 = 0;
220            #[doc = "Frame Buffer1 DMA Transfer Done interrupt enable"]
221            pub const FB1_DMA_DONE_INTEN_1: u32 = 0x01;
222        }
223    }
224    #[doc = "Frame Buffer2 DMA Transfer Done Interrupt Enable"]
225    pub mod FB2_DMA_DONE_INTEN {
226        pub const offset: u32 = 20;
227        pub const mask: u32 = 0x01 << offset;
228        pub mod R {}
229        pub mod W {}
230        pub mod RW {
231            #[doc = "Frame Buffer2 DMA Transfer Done interrupt disable"]
232            pub const FB2_DMA_DONE_INTEN_0: u32 = 0;
233            #[doc = "Frame Buffer2 DMA Transfer Done interrupt enable"]
234            pub const FB2_DMA_DONE_INTEN_1: u32 = 0x01;
235        }
236    }
237    #[doc = "STATFIFO Full Interrupt Enable. This bit enables the STAT FIFO interrupt."]
238    pub mod STATFF_INTEN {
239        pub const offset: u32 = 21;
240        pub const mask: u32 = 0x01 << offset;
241        pub mod R {}
242        pub mod W {}
243        pub mod RW {
244            #[doc = "STATFIFO full interrupt disable"]
245            pub const STATFF_INTEN_0: u32 = 0;
246            #[doc = "STATFIFO full interrupt enable"]
247            pub const STATFF_INTEN_1: u32 = 0x01;
248        }
249    }
250    #[doc = "STATFIFO DMA Transfer Done Interrupt Enable"]
251    pub mod SFF_DMA_DONE_INTEN {
252        pub const offset: u32 = 22;
253        pub const mask: u32 = 0x01 << offset;
254        pub mod R {}
255        pub mod W {}
256        pub mod RW {
257            #[doc = "STATFIFO DMA Transfer Done interrupt disable"]
258            pub const SFF_DMA_DONE_INTEN_0: u32 = 0;
259            #[doc = "STATFIFO DMA Transfer Done interrupt enable"]
260            pub const SFF_DMA_DONE_INTEN_1: u32 = 0x01;
261        }
262    }
263    #[doc = "RxFIFO Overrun Interrupt Enable. This bit enables the RX FIFO overrun interrupt."]
264    pub mod RF_OR_INTEN {
265        pub const offset: u32 = 24;
266        pub const mask: u32 = 0x01 << offset;
267        pub mod R {}
268        pub mod W {}
269        pub mod RW {
270            #[doc = "RxFIFO overrun interrupt is disabled"]
271            pub const RF_OR_INTEN_0: u32 = 0;
272            #[doc = "RxFIFO overrun interrupt is enabled"]
273            pub const RF_OR_INTEN_1: u32 = 0x01;
274        }
275    }
276    #[doc = "STAT FIFO Overrun Interrupt Enable. This bit enables the STATFIFO overrun interrupt."]
277    pub mod SF_OR_INTEN {
278        pub const offset: u32 = 25;
279        pub const mask: u32 = 0x01 << offset;
280        pub mod R {}
281        pub mod W {}
282        pub mod RW {
283            #[doc = "STATFIFO overrun interrupt is disabled"]
284            pub const SF_OR_INTEN_0: u32 = 0;
285            #[doc = "STATFIFO overrun interrupt is enabled"]
286            pub const SF_OR_INTEN_1: u32 = 0x01;
287        }
288    }
289    #[doc = "Change Of Image Field (COF) Interrupt Enable"]
290    pub mod COF_INT_EN {
291        pub const offset: u32 = 26;
292        pub const mask: u32 = 0x01 << offset;
293        pub mod R {}
294        pub mod W {}
295        pub mod RW {
296            #[doc = "COF interrupt is disabled"]
297            pub const COF_INT_EN_0: u32 = 0;
298            #[doc = "COF interrupt is enabled"]
299            pub const COF_INT_EN_1: u32 = 0x01;
300        }
301    }
302    #[doc = "CCIR Mode Select"]
303    pub mod CCIR_MODE {
304        pub const offset: u32 = 27;
305        pub const mask: u32 = 0x01 << offset;
306        pub mod R {}
307        pub mod W {}
308        pub mod RW {
309            #[doc = "Progressive mode is selected"]
310            pub const CCIR_MODE_0: u32 = 0;
311            #[doc = "Interlace mode is selected"]
312            pub const CCIR_MODE_1: u32 = 0x01;
313        }
314    }
315    #[doc = "CSI-PrP Interface Enable"]
316    pub mod PRP_IF_EN {
317        pub const offset: u32 = 28;
318        pub const mask: u32 = 0x01 << offset;
319        pub mod R {}
320        pub mod W {}
321        pub mod RW {
322            #[doc = "CSI to PrP bus is disabled"]
323            pub const PRP_IF_EN_0: u32 = 0;
324            #[doc = "CSI to PrP bus is enabled"]
325            pub const PRP_IF_EN_1: u32 = 0x01;
326        }
327    }
328    #[doc = "End-of-Frame Interrupt Enable. This bit enables and disables the EOF interrupt."]
329    pub mod EOF_INT_EN {
330        pub const offset: u32 = 29;
331        pub const mask: u32 = 0x01 << offset;
332        pub mod R {}
333        pub mod W {}
334        pub mod RW {
335            #[doc = "EOF interrupt is disabled."]
336            pub const EOF_INT_EN_0: u32 = 0;
337            #[doc = "EOF interrupt is generated when RX count value is reached."]
338            pub const EOF_INT_EN_1: u32 = 0x01;
339        }
340    }
341    #[doc = "External VSYNC Enable"]
342    pub mod EXT_VSYNC {
343        pub const offset: u32 = 30;
344        pub const mask: u32 = 0x01 << offset;
345        pub mod R {}
346        pub mod W {}
347        pub mod RW {
348            #[doc = "Internal VSYNC mode"]
349            pub const EXT_VSYNC_0: u32 = 0;
350            #[doc = "External VSYNC mode"]
351            pub const EXT_VSYNC_1: u32 = 0x01;
352        }
353    }
354    #[doc = "SWAP 16-Bit Enable"]
355    pub mod SWAP16_EN {
356        pub const offset: u32 = 31;
357        pub const mask: u32 = 0x01 << offset;
358        pub mod R {}
359        pub mod W {}
360        pub mod RW {
361            #[doc = "Disable swapping"]
362            pub const SWAP16_EN_0: u32 = 0;
363            #[doc = "Enable swapping"]
364            pub const SWAP16_EN_1: u32 = 0x01;
365        }
366    }
367}
368#[doc = "CSI Control Register 2"]
369pub mod CSICR2 {
370    #[doc = "Horizontal Skip Count"]
371    pub mod HSC {
372        pub const offset: u32 = 0;
373        pub const mask: u32 = 0xff << offset;
374        pub mod R {}
375        pub mod W {}
376        pub mod RW {}
377    }
378    #[doc = "Vertical Skip Count. Contains the number of rows to skip. SCE must be 1, otherwise VSC is ignored."]
379    pub mod VSC {
380        pub const offset: u32 = 8;
381        pub const mask: u32 = 0xff << offset;
382        pub mod R {}
383        pub mod W {}
384        pub mod RW {}
385    }
386    #[doc = "Live View Resolution Mode. Selects the grid size used for live view resolution."]
387    pub mod LVRM {
388        pub const offset: u32 = 16;
389        pub const mask: u32 = 0x07 << offset;
390        pub mod R {}
391        pub mod W {}
392        pub mod RW {
393            #[doc = "512 x 384"]
394            pub const LVRM_0: u32 = 0;
395            #[doc = "448 x 336"]
396            pub const LVRM_1: u32 = 0x01;
397            #[doc = "384 x 288"]
398            pub const LVRM_2: u32 = 0x02;
399            #[doc = "384 x 256"]
400            pub const LVRM_3: u32 = 0x03;
401            #[doc = "320 x 240"]
402            pub const LVRM_4: u32 = 0x04;
403            #[doc = "288 x 216"]
404            pub const LVRM_5: u32 = 0x05;
405            #[doc = "400 x 300"]
406            pub const LVRM_6: u32 = 0x06;
407        }
408    }
409    #[doc = "Bayer Tile Start. Controls the Bayer pattern starting point."]
410    pub mod BTS {
411        pub const offset: u32 = 19;
412        pub const mask: u32 = 0x03 << offset;
413        pub mod R {}
414        pub mod W {}
415        pub mod RW {
416            #[doc = "GR"]
417            pub const BTS_0: u32 = 0;
418            #[doc = "RG"]
419            pub const BTS_1: u32 = 0x01;
420            #[doc = "BG"]
421            pub const BTS_2: u32 = 0x02;
422            #[doc = "GB"]
423            pub const BTS_3: u32 = 0x03;
424        }
425    }
426    #[doc = "Skip Count Enable. Enables or disables the skip count feature."]
427    pub mod SCE {
428        pub const offset: u32 = 23;
429        pub const mask: u32 = 0x01 << offset;
430        pub mod R {}
431        pub mod W {}
432        pub mod RW {
433            #[doc = "Skip count disable"]
434            pub const SCE_0: u32 = 0;
435            #[doc = "Skip count enable"]
436            pub const SCE_1: u32 = 0x01;
437        }
438    }
439    #[doc = "Auto Focus Spread. Selects which green pixels are used for auto-focus."]
440    pub mod AFS {
441        pub const offset: u32 = 24;
442        pub const mask: u32 = 0x03 << offset;
443        pub mod R {}
444        pub mod W {}
445        pub mod RW {
446            #[doc = "Abs Diff on consecutive green pixels"]
447            pub const AFS_0: u32 = 0;
448            #[doc = "Abs Diff on every third green pixels"]
449            pub const AFS_1: u32 = 0x01;
450            #[doc = "Abs Diff on every four green pixels"]
451            pub const AFS_2: u32 = 0x02;
452        }
453    }
454    #[doc = "Double Resolution Mode. Controls size of statistics grid."]
455    pub mod DRM {
456        pub const offset: u32 = 26;
457        pub const mask: u32 = 0x01 << offset;
458        pub mod R {}
459        pub mod W {}
460        pub mod RW {
461            #[doc = "Stats grid of 8 x 6"]
462            pub const DRM_0: u32 = 0;
463            #[doc = "Stats grid of 8 x 12"]
464            pub const DRM_1: u32 = 0x01;
465        }
466    }
467    #[doc = "Burst Type of DMA Transfer from STATFIFO. Selects the burst type of DMA transfer from STATFIFO."]
468    pub mod DMA_BURST_TYPE_SFF {
469        pub const offset: u32 = 28;
470        pub const mask: u32 = 0x03 << offset;
471        pub mod R {}
472        pub mod W {}
473        pub mod RW {
474            #[doc = "INCR8"]
475            pub const DMA_BURST_TYPE_SFF_0: u32 = 0;
476            #[doc = "INCR4"]
477            pub const DMA_BURST_TYPE_SFF_1: u32 = 0x01;
478            #[doc = "INCR16"]
479            pub const DMA_BURST_TYPE_SFF_3: u32 = 0x03;
480        }
481    }
482    #[doc = "Burst Type of DMA Transfer from RxFIFO. Selects the burst type of DMA transfer from RxFIFO."]
483    pub mod DMA_BURST_TYPE_RFF {
484        pub const offset: u32 = 30;
485        pub const mask: u32 = 0x03 << offset;
486        pub mod R {}
487        pub mod W {}
488        pub mod RW {
489            #[doc = "INCR8"]
490            pub const DMA_BURST_TYPE_RFF_0: u32 = 0;
491            #[doc = "INCR4"]
492            pub const DMA_BURST_TYPE_RFF_1: u32 = 0x01;
493            #[doc = "INCR16"]
494            pub const DMA_BURST_TYPE_RFF_3: u32 = 0x03;
495        }
496    }
497}
498#[doc = "CSI Control Register 3"]
499pub mod CSICR3 {
500    #[doc = "Automatic Error Correction Enable"]
501    pub mod ECC_AUTO_EN {
502        pub const offset: u32 = 0;
503        pub const mask: u32 = 0x01 << offset;
504        pub mod R {}
505        pub mod W {}
506        pub mod RW {
507            #[doc = "Auto Error correction is disabled."]
508            pub const ECC_AUTO_EN_0: u32 = 0;
509            #[doc = "Auto Error correction is enabled."]
510            pub const ECC_AUTO_EN_1: u32 = 0x01;
511        }
512    }
513    #[doc = "Error Detection Interrupt Enable"]
514    pub mod ECC_INT_EN {
515        pub const offset: u32 = 1;
516        pub const mask: u32 = 0x01 << offset;
517        pub mod R {}
518        pub mod W {}
519        pub mod RW {
520            #[doc = "No interrupt is generated when error is detected. Only the status bit ECC_INT is set."]
521            pub const ECC_INT_EN_0: u32 = 0;
522            #[doc = "Interrupt is generated when error is detected."]
523            pub const ECC_INT_EN_1: u32 = 0x01;
524        }
525    }
526    #[doc = "Dummy Zero Packing Enable"]
527    pub mod ZERO_PACK_EN {
528        pub const offset: u32 = 2;
529        pub const mask: u32 = 0x01 << offset;
530        pub mod R {}
531        pub mod W {}
532        pub mod RW {
533            #[doc = "Zero packing disabled"]
534            pub const ZERO_PACK_EN_0: u32 = 0;
535            #[doc = "Zero packing enabled"]
536            pub const ZERO_PACK_EN_1: u32 = 0x01;
537        }
538    }
539    #[doc = "Two 8-bit Sensor Mode"]
540    pub mod TWO_8BIT_SENSOR {
541        pub const offset: u32 = 3;
542        pub const mask: u32 = 0x01 << offset;
543        pub mod R {}
544        pub mod W {}
545        pub mod RW {
546            #[doc = "Only one sensor is connected."]
547            pub const TWO_8BIT_SENSOR_0: u32 = 0;
548            #[doc = "Two 8-bit sensors are connected or one 16-bit sensor is connected."]
549            pub const TWO_8BIT_SENSOR_1: u32 = 0x01;
550        }
551    }
552    #[doc = "RxFIFO Full Level"]
553    pub mod RXFF_LEVEL {
554        pub const offset: u32 = 4;
555        pub const mask: u32 = 0x07 << offset;
556        pub mod R {}
557        pub mod W {}
558        pub mod RW {
559            #[doc = "4 Double words"]
560            pub const RXFF_LEVEL_0: u32 = 0;
561            #[doc = "8 Double words"]
562            pub const RXFF_LEVEL_1: u32 = 0x01;
563            #[doc = "16 Double words"]
564            pub const RXFF_LEVEL_2: u32 = 0x02;
565            #[doc = "24 Double words"]
566            pub const RXFF_LEVEL_3: u32 = 0x03;
567            #[doc = "32 Double words"]
568            pub const RXFF_LEVEL_4: u32 = 0x04;
569            #[doc = "48 Double words"]
570            pub const RXFF_LEVEL_5: u32 = 0x05;
571            #[doc = "64 Double words"]
572            pub const RXFF_LEVEL_6: u32 = 0x06;
573            #[doc = "96 Double words"]
574            pub const RXFF_LEVEL_7: u32 = 0x07;
575        }
576    }
577    #[doc = "Hresponse Error Enable. This bit enables the hresponse error interrupt."]
578    pub mod HRESP_ERR_EN {
579        pub const offset: u32 = 7;
580        pub const mask: u32 = 0x01 << offset;
581        pub mod R {}
582        pub mod W {}
583        pub mod RW {
584            #[doc = "Disable hresponse error interrupt"]
585            pub const HRESP_ERR_EN_0: u32 = 0;
586            #[doc = "Enable hresponse error interrupt"]
587            pub const HRESP_ERR_EN_1: u32 = 0x01;
588        }
589    }
590    #[doc = "STATFIFO Full Level"]
591    pub mod STATFF_LEVEL {
592        pub const offset: u32 = 8;
593        pub const mask: u32 = 0x07 << offset;
594        pub mod R {}
595        pub mod W {}
596        pub mod RW {
597            #[doc = "4 Double words"]
598            pub const STATFF_LEVEL_0: u32 = 0;
599            #[doc = "8 Double words"]
600            pub const STATFF_LEVEL_1: u32 = 0x01;
601            #[doc = "12 Double words"]
602            pub const STATFF_LEVEL_2: u32 = 0x02;
603            #[doc = "16 Double words"]
604            pub const STATFF_LEVEL_3: u32 = 0x03;
605            #[doc = "24 Double words"]
606            pub const STATFF_LEVEL_4: u32 = 0x04;
607            #[doc = "32 Double words"]
608            pub const STATFF_LEVEL_5: u32 = 0x05;
609            #[doc = "48 Double words"]
610            pub const STATFF_LEVEL_6: u32 = 0x06;
611            #[doc = "64 Double words"]
612            pub const STATFF_LEVEL_7: u32 = 0x07;
613        }
614    }
615    #[doc = "DMA Request Enable for STATFIFO"]
616    pub mod DMA_REQ_EN_SFF {
617        pub const offset: u32 = 11;
618        pub const mask: u32 = 0x01 << offset;
619        pub mod R {}
620        pub mod W {}
621        pub mod RW {
622            #[doc = "Disable the dma request"]
623            pub const DMA_REQ_EN_SFF_0: u32 = 0;
624            #[doc = "Enable the dma request"]
625            pub const DMA_REQ_EN_SFF_1: u32 = 0x01;
626        }
627    }
628    #[doc = "DMA Request Enable for RxFIFO"]
629    pub mod DMA_REQ_EN_RFF {
630        pub const offset: u32 = 12;
631        pub const mask: u32 = 0x01 << offset;
632        pub mod R {}
633        pub mod W {}
634        pub mod RW {
635            #[doc = "Disable the dma request"]
636            pub const DMA_REQ_EN_RFF_0: u32 = 0;
637            #[doc = "Enable the dma request"]
638            pub const DMA_REQ_EN_RFF_1: u32 = 0x01;
639        }
640    }
641    #[doc = "Reflash DMA Controller for STATFIFO"]
642    pub mod DMA_REFLASH_SFF {
643        pub const offset: u32 = 13;
644        pub const mask: u32 = 0x01 << offset;
645        pub mod R {}
646        pub mod W {}
647        pub mod RW {
648            #[doc = "No reflashing"]
649            pub const DMA_REFLASH_SFF_0: u32 = 0;
650            #[doc = "Reflash the embedded DMA controller"]
651            pub const DMA_REFLASH_SFF_1: u32 = 0x01;
652        }
653    }
654    #[doc = "Reflash DMA Controller for RxFIFO"]
655    pub mod DMA_REFLASH_RFF {
656        pub const offset: u32 = 14;
657        pub const mask: u32 = 0x01 << offset;
658        pub mod R {}
659        pub mod W {}
660        pub mod RW {
661            #[doc = "No reflashing"]
662            pub const DMA_REFLASH_RFF_0: u32 = 0;
663            #[doc = "Reflash the embedded DMA controller"]
664            pub const DMA_REFLASH_RFF_1: u32 = 0x01;
665        }
666    }
667    #[doc = "Frame Count Reset. Resets the Frame Counter. (Cleared automatically after reset is done)"]
668    pub mod FRMCNT_RST {
669        pub const offset: u32 = 15;
670        pub const mask: u32 = 0x01 << offset;
671        pub mod R {}
672        pub mod W {}
673        pub mod RW {
674            #[doc = "Do not reset"]
675            pub const FRMCNT_RST_0: u32 = 0;
676            #[doc = "Reset frame counter immediately"]
677            pub const FRMCNT_RST_1: u32 = 0x01;
678        }
679    }
680    #[doc = "Frame Counter"]
681    pub mod FRMCNT {
682        pub const offset: u32 = 16;
683        pub const mask: u32 = 0xffff << offset;
684        pub mod R {}
685        pub mod W {}
686        pub mod RW {}
687    }
688}
689#[doc = "CSI Statistic FIFO Register"]
690pub mod CSISTATFIFO {
691    #[doc = "Static data from sensor"]
692    pub mod STAT {
693        pub const offset: u32 = 0;
694        pub const mask: u32 = 0xffff_ffff << offset;
695        pub mod R {}
696        pub mod W {}
697        pub mod RW {}
698    }
699}
700#[doc = "CSI RX FIFO Register"]
701pub mod CSIRFIFO {
702    #[doc = "Received image data"]
703    pub mod IMAGE {
704        pub const offset: u32 = 0;
705        pub const mask: u32 = 0xffff_ffff << offset;
706        pub mod R {}
707        pub mod W {}
708        pub mod RW {}
709    }
710}
711#[doc = "CSI RX Count Register"]
712pub mod CSIRXCNT {
713    #[doc = "RxFIFO Count"]
714    pub mod RXCNT {
715        pub const offset: u32 = 0;
716        pub const mask: u32 = 0x003f_ffff << offset;
717        pub mod R {}
718        pub mod W {}
719        pub mod RW {}
720    }
721}
722#[doc = "CSI Status Register"]
723pub mod CSISR {
724    #[doc = "RXFIFO Data Ready"]
725    pub mod DRDY {
726        pub const offset: u32 = 0;
727        pub const mask: u32 = 0x01 << offset;
728        pub mod R {}
729        pub mod W {}
730        pub mod RW {
731            #[doc = "No data (word) is ready"]
732            pub const DRDY_0: u32 = 0;
733            #[doc = "At least 1 datum (word) is ready in RXFIFO."]
734            pub const DRDY_1: u32 = 0x01;
735        }
736    }
737    #[doc = "CCIR Error Interrupt"]
738    pub mod ECC_INT {
739        pub const offset: u32 = 1;
740        pub const mask: u32 = 0x01 << offset;
741        pub mod R {}
742        pub mod W {}
743        pub mod RW {
744            #[doc = "No error detected"]
745            pub const ECC_INT_0: u32 = 0;
746            #[doc = "Error is detected in CCIR coding"]
747            pub const ECC_INT_1: u32 = 0x01;
748        }
749    }
750    #[doc = "Hresponse Error Interrupt Status"]
751    pub mod HRESP_ERR_INT {
752        pub const offset: u32 = 7;
753        pub const mask: u32 = 0x01 << offset;
754        pub mod R {}
755        pub mod W {}
756        pub mod RW {
757            #[doc = "No hresponse error."]
758            pub const HRESP_ERR_INT_0: u32 = 0;
759            #[doc = "Hresponse error is detected."]
760            pub const HRESP_ERR_INT_1: u32 = 0x01;
761        }
762    }
763    #[doc = "Change Of Field Interrupt Status"]
764    pub mod COF_INT {
765        pub const offset: u32 = 13;
766        pub const mask: u32 = 0x01 << offset;
767        pub mod R {}
768        pub mod W {}
769        pub mod RW {
770            #[doc = "Video field has no change."]
771            pub const COF_INT_0: u32 = 0;
772            #[doc = "Change of video field is detected."]
773            pub const COF_INT_1: u32 = 0x01;
774        }
775    }
776    #[doc = "CCIR Field 1 Interrupt Status"]
777    pub mod F1_INT {
778        pub const offset: u32 = 14;
779        pub const mask: u32 = 0x01 << offset;
780        pub mod R {}
781        pub mod W {}
782        pub mod RW {
783            #[doc = "Field 1 of video is not detected."]
784            pub const F1_INT_0: u32 = 0;
785            #[doc = "Field 1 of video is about to start."]
786            pub const F1_INT_1: u32 = 0x01;
787        }
788    }
789    #[doc = "CCIR Field 2 Interrupt Status"]
790    pub mod F2_INT {
791        pub const offset: u32 = 15;
792        pub const mask: u32 = 0x01 << offset;
793        pub mod R {}
794        pub mod W {}
795        pub mod RW {
796            #[doc = "Field 2 of video is not detected"]
797            pub const F2_INT_0: u32 = 0;
798            #[doc = "Field 2 of video is about to start"]
799            pub const F2_INT_1: u32 = 0x01;
800        }
801    }
802    #[doc = "Start of Frame Interrupt Status. Indicates when SOF is detected. (Cleared by writing 1)"]
803    pub mod SOF_INT {
804        pub const offset: u32 = 16;
805        pub const mask: u32 = 0x01 << offset;
806        pub mod R {}
807        pub mod W {}
808        pub mod RW {
809            #[doc = "SOF is not detected."]
810            pub const SOF_INT_0: u32 = 0;
811            #[doc = "SOF is detected."]
812            pub const SOF_INT_1: u32 = 0x01;
813        }
814    }
815    #[doc = "End of Frame (EOF) Interrupt Status. Indicates when EOF is detected. (Cleared by writing 1)"]
816    pub mod EOF_INT {
817        pub const offset: u32 = 17;
818        pub const mask: u32 = 0x01 << offset;
819        pub mod R {}
820        pub mod W {}
821        pub mod RW {
822            #[doc = "EOF is not detected."]
823            pub const EOF_INT_0: u32 = 0;
824            #[doc = "EOF is detected."]
825            pub const EOF_INT_1: u32 = 0x01;
826        }
827    }
828    #[doc = "RXFIFO Full Interrupt Status"]
829    pub mod RXFF_INT {
830        pub const offset: u32 = 18;
831        pub const mask: u32 = 0x01 << offset;
832        pub mod R {}
833        pub mod W {}
834        pub mod RW {
835            #[doc = "RxFIFO is not full."]
836            pub const RXFF_INT_0: u32 = 0;
837            #[doc = "RxFIFO is full."]
838            pub const RXFF_INT_1: u32 = 0x01;
839        }
840    }
841    #[doc = "DMA Transfer Done in Frame Buffer1"]
842    pub mod DMA_TSF_DONE_FB1 {
843        pub const offset: u32 = 19;
844        pub const mask: u32 = 0x01 << offset;
845        pub mod R {}
846        pub mod W {}
847        pub mod RW {
848            #[doc = "DMA transfer is not completed."]
849            pub const DMA_TSF_DONE_FB1_0: u32 = 0;
850            #[doc = "DMA transfer is completed."]
851            pub const DMA_TSF_DONE_FB1_1: u32 = 0x01;
852        }
853    }
854    #[doc = "DMA Transfer Done in Frame Buffer2"]
855    pub mod DMA_TSF_DONE_FB2 {
856        pub const offset: u32 = 20;
857        pub const mask: u32 = 0x01 << offset;
858        pub mod R {}
859        pub mod W {}
860        pub mod RW {
861            #[doc = "DMA transfer is not completed."]
862            pub const DMA_TSF_DONE_FB2_0: u32 = 0;
863            #[doc = "DMA transfer is completed."]
864            pub const DMA_TSF_DONE_FB2_1: u32 = 0x01;
865        }
866    }
867    #[doc = "STATFIFO Full Interrupt Status"]
868    pub mod STATFF_INT {
869        pub const offset: u32 = 21;
870        pub const mask: u32 = 0x01 << offset;
871        pub mod R {}
872        pub mod W {}
873        pub mod RW {
874            #[doc = "STATFIFO is not full."]
875            pub const STATFF_INT_0: u32 = 0;
876            #[doc = "STATFIFO is full."]
877            pub const STATFF_INT_1: u32 = 0x01;
878        }
879    }
880    #[doc = "DMA Transfer Done from StatFIFO"]
881    pub mod DMA_TSF_DONE_SFF {
882        pub const offset: u32 = 22;
883        pub const mask: u32 = 0x01 << offset;
884        pub mod R {}
885        pub mod W {}
886        pub mod RW {
887            #[doc = "DMA transfer is not completed."]
888            pub const DMA_TSF_DONE_SFF_0: u32 = 0;
889            #[doc = "DMA transfer is completed."]
890            pub const DMA_TSF_DONE_SFF_1: u32 = 0x01;
891        }
892    }
893    #[doc = "RxFIFO Overrun Interrupt Status"]
894    pub mod RF_OR_INT {
895        pub const offset: u32 = 24;
896        pub const mask: u32 = 0x01 << offset;
897        pub mod R {}
898        pub mod W {}
899        pub mod RW {
900            #[doc = "RXFIFO has not overflowed."]
901            pub const RF_OR_INT_0: u32 = 0;
902            #[doc = "RXFIFO has overflowed."]
903            pub const RF_OR_INT_1: u32 = 0x01;
904        }
905    }
906    #[doc = "STATFIFO Overrun Interrupt Status"]
907    pub mod SF_OR_INT {
908        pub const offset: u32 = 25;
909        pub const mask: u32 = 0x01 << offset;
910        pub mod R {}
911        pub mod W {}
912        pub mod RW {
913            #[doc = "STATFIFO has not overflowed."]
914            pub const SF_OR_INT_0: u32 = 0;
915            #[doc = "STATFIFO has overflowed."]
916            pub const SF_OR_INT_1: u32 = 0x01;
917        }
918    }
919    #[doc = "When DMA field 0 is complete, this bit will be set to 1(clear by writing 1)."]
920    pub mod DMA_FIELD1_DONE {
921        pub const offset: u32 = 26;
922        pub const mask: u32 = 0x01 << offset;
923        pub mod R {}
924        pub mod W {}
925        pub mod RW {}
926    }
927    #[doc = "When DMA field 0 is complete, this bit will be set to 1(clear by writing 1)."]
928    pub mod DMA_FIELD0_DONE {
929        pub const offset: u32 = 27;
930        pub const mask: u32 = 0x01 << offset;
931        pub mod R {}
932        pub mod W {}
933        pub mod RW {}
934    }
935    #[doc = "When using base address switching enable, this bit will be 1 when switching occur before DMA complete"]
936    pub mod BASEADDR_CHHANGE_ERROR {
937        pub const offset: u32 = 28;
938        pub const mask: u32 = 0x01 << offset;
939        pub mod R {}
940        pub mod W {}
941        pub mod RW {}
942    }
943}
944#[doc = "CSI DMA Start Address Register - for STATFIFO"]
945pub mod CSIDMASA_STATFIFO {
946    #[doc = "DMA Start Address for STATFIFO"]
947    pub mod DMA_START_ADDR_SFF {
948        pub const offset: u32 = 2;
949        pub const mask: u32 = 0x3fff_ffff << offset;
950        pub mod R {}
951        pub mod W {}
952        pub mod RW {}
953    }
954}
955#[doc = "CSI DMA Transfer Size Register - for STATFIFO"]
956pub mod CSIDMATS_STATFIFO {
957    #[doc = "DMA Transfer Size for STATFIFO"]
958    pub mod DMA_TSF_SIZE_SFF {
959        pub const offset: u32 = 0;
960        pub const mask: u32 = 0xffff_ffff << offset;
961        pub mod R {}
962        pub mod W {}
963        pub mod RW {}
964    }
965}
966#[doc = "CSI DMA Start Address Register - for Frame Buffer1"]
967pub mod CSIDMASA_FB1 {
968    #[doc = "DMA Start Address in Frame Buffer1"]
969    pub mod DMA_START_ADDR_FB1 {
970        pub const offset: u32 = 2;
971        pub const mask: u32 = 0x3fff_ffff << offset;
972        pub mod R {}
973        pub mod W {}
974        pub mod RW {}
975    }
976}
977#[doc = "CSI DMA Transfer Size Register - for Frame Buffer2"]
978pub mod CSIDMASA_FB2 {
979    #[doc = "DMA Start Address in Frame Buffer2"]
980    pub mod DMA_START_ADDR_FB2 {
981        pub const offset: u32 = 2;
982        pub const mask: u32 = 0x3fff_ffff << offset;
983        pub mod R {}
984        pub mod W {}
985        pub mod RW {}
986    }
987}
988#[doc = "CSI Frame Buffer Parameter Register"]
989pub mod CSIFBUF_PARA {
990    #[doc = "Frame Buffer Parameter"]
991    pub mod FBUF_STRIDE {
992        pub const offset: u32 = 0;
993        pub const mask: u32 = 0xffff << offset;
994        pub mod R {}
995        pub mod W {}
996        pub mod RW {}
997    }
998    #[doc = "DEINTERLACE_STRIDE is only used in the deinterlace mode"]
999    pub mod DEINTERLACE_STRIDE {
1000        pub const offset: u32 = 16;
1001        pub const mask: u32 = 0xffff << offset;
1002        pub mod R {}
1003        pub mod W {}
1004        pub mod RW {}
1005    }
1006}
1007#[doc = "CSI Image Parameter Register"]
1008pub mod CSIIMAG_PARA {
1009    #[doc = "Image Height. Indicates how many pixels in a column of the image from the sensor."]
1010    pub mod IMAGE_HEIGHT {
1011        pub const offset: u32 = 0;
1012        pub const mask: u32 = 0xffff << offset;
1013        pub mod R {}
1014        pub mod W {}
1015        pub mod RW {}
1016    }
1017    #[doc = "Image Width"]
1018    pub mod IMAGE_WIDTH {
1019        pub const offset: u32 = 16;
1020        pub const mask: u32 = 0xffff << offset;
1021        pub mod R {}
1022        pub mod W {}
1023        pub mod RW {}
1024    }
1025}
1026#[doc = "CSI Control Register 18"]
1027pub mod CSICR18 {
1028    #[doc = "This bit is used to select the output method When input is standard CCIR656 video."]
1029    pub mod DEINTERLACE_EN {
1030        pub const offset: u32 = 2;
1031        pub const mask: u32 = 0x01 << offset;
1032        pub mod R {}
1033        pub mod W {}
1034        pub mod RW {
1035            #[doc = "Deinterlace disabled"]
1036            pub const DEINTERLACE_EN_0: u32 = 0;
1037            #[doc = "Deinterlace enabled"]
1038            pub const DEINTERLACE_EN_1: u32 = 0x01;
1039        }
1040    }
1041    #[doc = "When input is parallel rgb888/yuv444 24bit, this bit can be enabled."]
1042    pub mod PARALLEL24_EN {
1043        pub const offset: u32 = 3;
1044        pub const mask: u32 = 0x01 << offset;
1045        pub mod R {}
1046        pub mod W {}
1047        pub mod RW {}
1048    }
1049    #[doc = "When this bit is enabled, CSI DMA will switch the base address according to BASEADDR_SWITCH_SEL rather than atomically by DMA completed"]
1050    pub mod BASEADDR_SWITCH_EN {
1051        pub const offset: u32 = 4;
1052        pub const mask: u32 = 0x01 << offset;
1053        pub mod R {}
1054        pub mod W {}
1055        pub mod RW {}
1056    }
1057    #[doc = "CSI 2 base addresses switching method. When using this bit, BASEADDR_SWITCH_EN is 1."]
1058    pub mod BASEADDR_SWITCH_SEL {
1059        pub const offset: u32 = 5;
1060        pub const mask: u32 = 0x01 << offset;
1061        pub mod R {}
1062        pub mod W {}
1063        pub mod RW {
1064            #[doc = "Switching base address at the edge of the vsync"]
1065            pub const BASEADDR_SWITCH_SEL_0: u32 = 0;
1066            #[doc = "Switching base address at the edge of the first data of each frame"]
1067            pub const BASEADDR_SWITCH_SEL_1: u32 = 0x01;
1068        }
1069    }
1070    #[doc = "In interlace mode, fileld 0 means interrupt enabled."]
1071    pub mod FIELD0_DONE_IE {
1072        pub const offset: u32 = 6;
1073        pub const mask: u32 = 0x01 << offset;
1074        pub mod R {}
1075        pub mod W {}
1076        pub mod RW {
1077            #[doc = "Interrupt disabled"]
1078            pub const FIELD0_DONE_IE_0: u32 = 0;
1079            #[doc = "Interrupt enabled"]
1080            pub const FIELD0_DONE_IE_1: u32 = 0x01;
1081        }
1082    }
1083    #[doc = "When in interlace mode, field 1 done interrupt enable."]
1084    pub mod DMA_FIELD1_DONE_IE {
1085        pub const offset: u32 = 7;
1086        pub const mask: u32 = 0x01 << offset;
1087        pub mod R {}
1088        pub mod W {}
1089        pub mod RW {
1090            #[doc = "Interrupt disabled"]
1091            pub const DMA_FIELD1_DONE_IE_0: u32 = 0;
1092            #[doc = "Interrupt enabled"]
1093            pub const DMA_FIELD1_DONE_IE_1: u32 = 0x01;
1094        }
1095    }
1096    #[doc = "Choosing the last DMA request condition."]
1097    pub mod LAST_DMA_REQ_SEL {
1098        pub const offset: u32 = 8;
1099        pub const mask: u32 = 0x01 << offset;
1100        pub mod R {}
1101        pub mod W {}
1102        pub mod RW {
1103            #[doc = "fifo_full_level"]
1104            pub const LAST_DMA_REQ_SEL_0: u32 = 0;
1105            #[doc = "hburst_length"]
1106            pub const LAST_DMA_REQ_SEL_1: u32 = 0x01;
1107        }
1108    }
1109    #[doc = "Base address change error interrupt enable signal."]
1110    pub mod BASEADDR_CHANGE_ERROR_IE {
1111        pub const offset: u32 = 9;
1112        pub const mask: u32 = 0x01 << offset;
1113        pub mod R {}
1114        pub mod W {}
1115        pub mod RW {}
1116    }
1117    #[doc = "Output is 32-bit format."]
1118    pub mod RGB888A_FORMAT_SEL {
1119        pub const offset: u32 = 10;
1120        pub const mask: u32 = 0x01 << offset;
1121        pub mod R {}
1122        pub mod W {}
1123        pub mod RW {
1124            #[doc = "{8'h0, data\\[23:0\\]}"]
1125            pub const RGB888A_FORMAT_SEL_0: u32 = 0;
1126            #[doc = "{data\\[23:0\\], 8'h0}"]
1127            pub const RGB888A_FORMAT_SEL_1: u32 = 0x01;
1128        }
1129    }
1130    #[doc = "Hprot value in AHB bus protocol."]
1131    pub mod AHB_HPROT {
1132        pub const offset: u32 = 12;
1133        pub const mask: u32 = 0x0f << offset;
1134        pub mod R {}
1135        pub mod W {}
1136        pub mod RW {}
1137    }
1138    #[doc = "These bits used to choose the method to mask the CSI input."]
1139    pub mod MASK_OPTION {
1140        pub const offset: u32 = 18;
1141        pub const mask: u32 = 0x03 << offset;
1142        pub mod R {}
1143        pub mod W {}
1144        pub mod RW {
1145            #[doc = "Writing to memory from first completely frame, when using this option, the CSI_ENABLE should be 1."]
1146            pub const MASK_OPTION_0: u32 = 0;
1147            #[doc = "Writing to memory when CSI_ENABLE is 1."]
1148            pub const MASK_OPTION_1: u32 = 0x01;
1149            #[doc = "Writing to memory from second completely frame, when using this option, the CSI_ENABLE should be 1."]
1150            pub const MASK_OPTION_2: u32 = 0x02;
1151            #[doc = "Writing to memory when data comes in, not matter the CSI_ENABLE is 1 or 0."]
1152            pub const MASK_OPTION_3: u32 = 0x03;
1153        }
1154    }
1155    #[doc = "CSI global enable signal"]
1156    pub mod CSI_ENABLE {
1157        pub const offset: u32 = 31;
1158        pub const mask: u32 = 0x01 << offset;
1159        pub mod R {}
1160        pub mod W {}
1161        pub mod RW {}
1162    }
1163}
1164#[doc = "CSI Control Register 19"]
1165pub mod CSICR19 {
1166    #[doc = "This byte stores the highest FIFO level achieved by CSI FIFO timely and will be clear by writing 8'ff to it"]
1167    pub mod DMA_RFIFO_HIGHEST_FIFO_LEVEL {
1168        pub const offset: u32 = 0;
1169        pub const mask: u32 = 0xff << offset;
1170        pub mod R {}
1171        pub mod W {}
1172        pub mod RW {}
1173    }
1174}