imxrt_ral/blocks/imxrt1061/
can.rs

1#[doc = "FLEXCAN"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "Module Configuration Register"]
5    pub MCR: crate::RWRegister<u32>,
6    #[doc = "Control 1 Register"]
7    pub CTRL1: crate::RWRegister<u32>,
8    #[doc = "Free Running Timer Register"]
9    pub TIMER: crate::RWRegister<u32>,
10    _reserved0: [u8; 0x04],
11    #[doc = "Rx Mailboxes Global Mask Register"]
12    pub RXMGMASK: crate::RWRegister<u32>,
13    #[doc = "Rx Buffer 14 Mask Register"]
14    pub RX14MASK: crate::RWRegister<u32>,
15    #[doc = "Rx Buffer 15 Mask Register"]
16    pub RX15MASK: crate::RWRegister<u32>,
17    #[doc = "Error Counter Register"]
18    pub ECR: crate::RWRegister<u32>,
19    #[doc = "Error and Status 1 Register"]
20    pub ESR1: crate::RWRegister<u32>,
21    #[doc = "Interrupt Masks 2 Register"]
22    pub IMASK2: crate::RWRegister<u32>,
23    #[doc = "Interrupt Masks 1 Register"]
24    pub IMASK1: crate::RWRegister<u32>,
25    #[doc = "Interrupt Flags 2 Register"]
26    pub IFLAG2: crate::RWRegister<u32>,
27    #[doc = "Interrupt Flags 1 Register"]
28    pub IFLAG1: crate::RWRegister<u32>,
29    #[doc = "Control 2 Register"]
30    pub CTRL2: crate::RWRegister<u32>,
31    #[doc = "Error and Status 2 Register"]
32    pub ESR2: crate::RORegister<u32>,
33    _reserved1: [u8; 0x08],
34    #[doc = "CRC Register"]
35    pub CRCR: crate::RORegister<u32>,
36    #[doc = "Rx FIFO Global Mask Register"]
37    pub RXFGMASK: crate::RWRegister<u32>,
38    #[doc = "Rx FIFO Information Register"]
39    pub RXFIR: crate::RORegister<u32>,
40    _reserved2: [u8; 0x08],
41    #[doc = "Debug 1 register"]
42    pub DBG1: crate::RORegister<u32>,
43    #[doc = "Debug 2 register"]
44    pub DBG2: crate::RORegister<u32>,
45    _reserved3: [u8; 0x0820],
46    #[doc = "Rx Individual Mask Registers"]
47    pub RXIMR: [crate::RWRegister<u32>; 64usize],
48    _reserved4: [u8; 0x60],
49    #[doc = "Glitch Filter Width Registers"]
50    pub GFWR: crate::RWRegister<u32>,
51}
52#[doc = "Module Configuration Register"]
53pub mod MCR {
54    #[doc = "This 7-bit field defines the number of the last Message Buffers that will take part in the matching and arbitration processes"]
55    pub mod MAXMB {
56        pub const offset: u32 = 0;
57        pub const mask: u32 = 0x7f << offset;
58        pub mod R {}
59        pub mod W {}
60        pub mod RW {}
61    }
62    #[doc = "This 2-bit field identifies the format of the elements of the Rx FIFO filter table, as shown below"]
63    pub mod IDAM {
64        pub const offset: u32 = 8;
65        pub const mask: u32 = 0x03 << offset;
66        pub mod R {}
67        pub mod W {}
68        pub mod RW {
69            #[doc = "Format A One full ID (standard or extended) per ID filter Table element."]
70            pub const IDAM_0: u32 = 0;
71            #[doc = "Format B Two full standard IDs or two partial 14-bit extended IDs per ID filter Table element."]
72            pub const IDAM_1: u32 = 0x01;
73            #[doc = "Format C Four partial 8-bit IDs (standard or extended) per ID filter Table element."]
74            pub const IDAM_2: u32 = 0x02;
75            #[doc = "Format D All frames rejected."]
76            pub const IDAM_3: u32 = 0x03;
77        }
78    }
79    #[doc = "This bit is supplied for backwards compatibility reasons"]
80    pub mod AEN {
81        pub const offset: u32 = 12;
82        pub const mask: u32 = 0x01 << offset;
83        pub mod R {}
84        pub mod W {}
85        pub mod RW {
86            #[doc = "Abort disabled"]
87            pub const AEN_0: u32 = 0;
88            #[doc = "Abort enabled"]
89            pub const AEN_1: u32 = 0x01;
90        }
91    }
92    #[doc = "This bit is provided for backwards compatibility reasons"]
93    pub mod LPRIOEN {
94        pub const offset: u32 = 13;
95        pub const mask: u32 = 0x01 << offset;
96        pub mod R {}
97        pub mod W {}
98        pub mod RW {
99            #[doc = "Local Priority disabled"]
100            pub const LPRIOEN_0: u32 = 0;
101            #[doc = "Local Priority enabled"]
102            pub const LPRIOEN_1: u32 = 0x01;
103        }
104    }
105    #[doc = "This bit indicates whether Rx matching process will be based either on individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and RX15MASK, RXFGMASK"]
106    pub mod IRMQ {
107        pub const offset: u32 = 16;
108        pub const mask: u32 = 0x01 << offset;
109        pub mod R {}
110        pub mod W {}
111        pub mod RW {
112            #[doc = "Individual Rx masking and queue feature are disabled.For backward compatibility, the reading of C/S word locks the MB even if it is EMPTY."]
113            pub const IRMQ_0: u32 = 0;
114            #[doc = "Individual Rx masking and queue feature are enabled."]
115            pub const IRMQ_1: u32 = 0x01;
116        }
117    }
118    #[doc = "This bit defines whether FlexCAN is allowed to receive frames transmitted by itself"]
119    pub mod SRXDIS {
120        pub const offset: u32 = 17;
121        pub const mask: u32 = 0x01 << offset;
122        pub mod R {}
123        pub mod W {}
124        pub mod RW {
125            #[doc = "Self reception enabled"]
126            pub const SRXDIS_0: u32 = 0;
127            #[doc = "Self reception disabled"]
128            pub const SRXDIS_1: u32 = 0x01;
129        }
130    }
131    #[doc = "This bit defines whether the integrated low-pass filter is applied to protect the FLEXCAN_RX input from spurious wake up"]
132    pub mod WAKSRC {
133        pub const offset: u32 = 19;
134        pub const mask: u32 = 0x01 << offset;
135        pub mod R {}
136        pub mod W {}
137        pub mod RW {
138            #[doc = "FLEXCAN uses the unfiltered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus."]
139            pub const WAKSRC_0: u32 = 0;
140            #[doc = "FLEXCAN uses the filtered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus"]
141            pub const WAKSRC_1: u32 = 0x01;
142        }
143    }
144    #[doc = "This read-only bit indicates that FLEXCAN is either in Disable Mode or Stop Mode"]
145    pub mod LPMACK {
146        pub const offset: u32 = 20;
147        pub const mask: u32 = 0x01 << offset;
148        pub mod R {}
149        pub mod W {}
150        pub mod RW {
151            #[doc = "FLEXCAN not in any of the low power modes"]
152            pub const LPMACK_0: u32 = 0;
153            #[doc = "FLEXCAN is either in Disable Mode, or Stop mode"]
154            pub const LPMACK_1: u32 = 0x01;
155        }
156    }
157    #[doc = "When asserted, this bit enables the generation of the TWRN_INT and RWRN_INT flags in the Error and Status Register"]
158    pub mod WRNEN {
159        pub const offset: u32 = 21;
160        pub const mask: u32 = 0x01 << offset;
161        pub mod R {}
162        pub mod W {}
163        pub mod RW {
164            #[doc = "TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters."]
165            pub const WRNEN_0: u32 = 0;
166            #[doc = "TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to >= 96."]
167            pub const WRNEN_1: u32 = 0x01;
168        }
169    }
170    #[doc = "This bit enables the Self Wake Up feature when FLEXCAN is in Stop Mode"]
171    pub mod SLFWAK {
172        pub const offset: u32 = 22;
173        pub const mask: u32 = 0x01 << offset;
174        pub mod R {}
175        pub mod W {}
176        pub mod RW {
177            #[doc = "FLEXCAN Self Wake Up feature is disabled"]
178            pub const SLFWAK_0: u32 = 0;
179            #[doc = "FLEXCAN Self Wake Up feature is enabled"]
180            pub const SLFWAK_1: u32 = 0x01;
181        }
182    }
183    #[doc = "This bit configures some of the FLEXCAN registers to be either in Supervisor or User Mode"]
184    pub mod SUPV {
185        pub const offset: u32 = 23;
186        pub const mask: u32 = 0x01 << offset;
187        pub mod R {}
188        pub mod W {}
189        pub mod RW {
190            #[doc = "FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses"]
191            pub const SUPV_0: u32 = 0;
192            #[doc = "FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location"]
193            pub const SUPV_1: u32 = 0x01;
194        }
195    }
196    #[doc = "This read-only bit indicates that FLEXCAN is in Freeze Mode and its prescaler is stopped"]
197    pub mod FRZACK {
198        pub const offset: u32 = 24;
199        pub const mask: u32 = 0x01 << offset;
200        pub mod R {}
201        pub mod W {}
202        pub mod RW {
203            #[doc = "FLEXCAN not in Freeze Mode, prescaler running"]
204            pub const FRZACK_0: u32 = 0;
205            #[doc = "FLEXCAN in Freeze Mode, prescaler stopped"]
206            pub const FRZACK_1: u32 = 0x01;
207        }
208    }
209    #[doc = "When this bit is asserted, FlexCAN resets its internal state machines and some of the memory mapped registers"]
210    pub mod SOFTRST {
211        pub const offset: u32 = 25;
212        pub const mask: u32 = 0x01 << offset;
213        pub mod R {}
214        pub mod W {}
215        pub mod RW {
216            #[doc = "No reset request"]
217            pub const SOFTRST_0: u32 = 0;
218            #[doc = "Reset the registers"]
219            pub const SOFTRST_1: u32 = 0x01;
220        }
221    }
222    #[doc = "This bit enables the Wake Up Interrupt generation."]
223    pub mod WAKMSK {
224        pub const offset: u32 = 26;
225        pub const mask: u32 = 0x01 << offset;
226        pub mod R {}
227        pub mod W {}
228        pub mod RW {
229            #[doc = "Wake Up Interrupt is disabled"]
230            pub const WAKMSK_0: u32 = 0;
231            #[doc = "Wake Up Interrupt is enabled"]
232            pub const WAKMSK_1: u32 = 0x01;
233        }
234    }
235    #[doc = "This read-only bit indicates that FLEXCAN is either in Disable Mode, Stop Mode or Freeze Mode"]
236    pub mod NOTRDY {
237        pub const offset: u32 = 27;
238        pub const mask: u32 = 0x01 << offset;
239        pub mod R {}
240        pub mod W {}
241        pub mod RW {
242            #[doc = "FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode"]
243            pub const NOTRDY_0: u32 = 0;
244            #[doc = "FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode"]
245            pub const NOTRDY_1: u32 = 0x01;
246        }
247    }
248    #[doc = "Assertion of this bit puts the FLEXCAN module into Freeze Mode"]
249    pub mod HALT {
250        pub const offset: u32 = 28;
251        pub const mask: u32 = 0x01 << offset;
252        pub mod R {}
253        pub mod W {}
254        pub mod RW {
255            #[doc = "No Freeze Mode request."]
256            pub const HALT_0: u32 = 0;
257            #[doc = "Enters Freeze Mode if the FRZ bit is asserted."]
258            pub const HALT_1: u32 = 0x01;
259        }
260    }
261    #[doc = "This bit controls whether the Rx FIFO feature is enabled or not"]
262    pub mod RFEN {
263        pub const offset: u32 = 29;
264        pub const mask: u32 = 0x01 << offset;
265        pub mod R {}
266        pub mod W {}
267        pub mod RW {
268            #[doc = "FIFO not enabled"]
269            pub const RFEN_0: u32 = 0;
270            #[doc = "FIFO enabled"]
271            pub const RFEN_1: u32 = 0x01;
272        }
273    }
274    #[doc = "The FRZ bit specifies the FLEXCAN behavior when the HALT bit in the MCR Register is set or when Debug Mode is requested at Arm level"]
275    pub mod FRZ {
276        pub const offset: u32 = 30;
277        pub const mask: u32 = 0x01 << offset;
278        pub mod R {}
279        pub mod W {}
280        pub mod RW {
281            #[doc = "Not enabled to enter Freeze Mode"]
282            pub const FRZ_0: u32 = 0;
283            #[doc = "Enabled to enter Freeze Mode"]
284            pub const FRZ_1: u32 = 0x01;
285        }
286    }
287    #[doc = "This bit controls whether FLEXCAN is enabled or not"]
288    pub mod MDIS {
289        pub const offset: u32 = 31;
290        pub const mask: u32 = 0x01 << offset;
291        pub mod R {}
292        pub mod W {}
293        pub mod RW {
294            #[doc = "Enable the FLEXCAN module"]
295            pub const MDIS_0: u32 = 0;
296            #[doc = "Disable the FLEXCAN module"]
297            pub const MDIS_1: u32 = 0x01;
298        }
299    }
300}
301#[doc = "Control 1 Register"]
302pub mod CTRL1 {
303    #[doc = "This 3-bit field defines the length of the Propagation Segment in the bit time"]
304    pub mod PROPSEG {
305        pub const offset: u32 = 0;
306        pub const mask: u32 = 0x07 << offset;
307        pub mod R {}
308        pub mod W {}
309        pub mod RW {}
310    }
311    #[doc = "This bit configures FLEXCAN to operate in Listen Only Mode"]
312    pub mod LOM {
313        pub const offset: u32 = 3;
314        pub const mask: u32 = 0x01 << offset;
315        pub mod R {}
316        pub mod W {}
317        pub mod RW {
318            #[doc = "Listen Only Mode is deactivated"]
319            pub const LOM_0: u32 = 0;
320            #[doc = "FLEXCAN module operates in Listen Only Mode"]
321            pub const LOM_1: u32 = 0x01;
322        }
323    }
324    #[doc = "This bit defines the ordering mechanism for Message Buffer transmission"]
325    pub mod LBUF {
326        pub const offset: u32 = 4;
327        pub const mask: u32 = 0x01 << offset;
328        pub mod R {}
329        pub mod W {}
330        pub mod RW {
331            #[doc = "Buffer with highest priority is transmitted first"]
332            pub const LBUF_0: u32 = 0;
333            #[doc = "Lowest number buffer is transmitted first"]
334            pub const LBUF_1: u32 = 0x01;
335        }
336    }
337    #[doc = "This bit enables a mechanism that resets the free-running timer each time a message is received in Message Buffer 0"]
338    pub mod TSYN {
339        pub const offset: u32 = 5;
340        pub const mask: u32 = 0x01 << offset;
341        pub mod R {}
342        pub mod W {}
343        pub mod RW {
344            #[doc = "Timer Sync feature disabled"]
345            pub const TSYN_0: u32 = 0;
346            #[doc = "Timer Sync feature enabled"]
347            pub const TSYN_1: u32 = 0x01;
348        }
349    }
350    #[doc = "This bit defines how FLEXCAN recovers from Bus Off state"]
351    pub mod BOFFREC {
352        pub const offset: u32 = 6;
353        pub const mask: u32 = 0x01 << offset;
354        pub mod R {}
355        pub mod W {}
356        pub mod RW {
357            #[doc = "Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B"]
358            pub const BOFFREC_0: u32 = 0;
359            #[doc = "Automatic recovering from Bus Off state disabled"]
360            pub const BOFFREC_1: u32 = 0x01;
361        }
362    }
363    #[doc = "This bit defines the sampling mode of CAN bits at the FLEXCAN_RX"]
364    pub mod SMP {
365        pub const offset: u32 = 7;
366        pub const mask: u32 = 0x01 << offset;
367        pub mod R {}
368        pub mod W {}
369        pub mod RW {
370            #[doc = "Just one sample is used to determine the bit value"]
371            pub const SMP_0: u32 = 0;
372            #[doc = "Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples, a majority rule is used"]
373            pub const SMP_1: u32 = 0x01;
374        }
375    }
376    #[doc = "This bit provides a mask for the Rx Warning Interrupt associated with the RWRN_INT flag in the Error and Status Register"]
377    pub mod RWRNMSK {
378        pub const offset: u32 = 10;
379        pub const mask: u32 = 0x01 << offset;
380        pub mod R {}
381        pub mod W {}
382        pub mod RW {
383            #[doc = "Rx Warning Interrupt disabled"]
384            pub const RWRNMSK_0: u32 = 0;
385            #[doc = "Rx Warning Interrupt enabled"]
386            pub const RWRNMSK_1: u32 = 0x01;
387        }
388    }
389    #[doc = "This bit provides a mask for the Tx Warning Interrupt associated with the TWRN_INT flag in the Error and Status Register"]
390    pub mod TWRNMSK {
391        pub const offset: u32 = 11;
392        pub const mask: u32 = 0x01 << offset;
393        pub mod R {}
394        pub mod W {}
395        pub mod RW {
396            #[doc = "Tx Warning Interrupt disabled"]
397            pub const TWRNMSK_0: u32 = 0;
398            #[doc = "Tx Warning Interrupt enabled"]
399            pub const TWRNMSK_1: u32 = 0x01;
400        }
401    }
402    #[doc = "This bit configures FlexCAN to operate in Loop-Back Mode"]
403    pub mod LPB {
404        pub const offset: u32 = 12;
405        pub const mask: u32 = 0x01 << offset;
406        pub mod R {}
407        pub mod W {}
408        pub mod RW {
409            #[doc = "Loop Back disabled"]
410            pub const LPB_0: u32 = 0;
411            #[doc = "Loop Back enabled"]
412            pub const LPB_1: u32 = 0x01;
413        }
414    }
415    #[doc = "This bit provides a mask for the Error Interrupt."]
416    pub mod ERRMSK {
417        pub const offset: u32 = 14;
418        pub const mask: u32 = 0x01 << offset;
419        pub mod R {}
420        pub mod W {}
421        pub mod RW {
422            #[doc = "Error interrupt disabled"]
423            pub const ERRMSK_0: u32 = 0;
424            #[doc = "Error interrupt enabled"]
425            pub const ERRMSK_1: u32 = 0x01;
426        }
427    }
428    #[doc = "This bit provides a mask for the Bus Off Interrupt."]
429    pub mod BOFFMSK {
430        pub const offset: u32 = 15;
431        pub const mask: u32 = 0x01 << offset;
432        pub mod R {}
433        pub mod W {}
434        pub mod RW {
435            #[doc = "Bus Off interrupt disabled"]
436            pub const BOFFMSK_0: u32 = 0;
437            #[doc = "Bus Off interrupt enabled"]
438            pub const BOFFMSK_1: u32 = 0x01;
439        }
440    }
441    #[doc = "This 3-bit field defines the length of Phase Buffer Segment 2 in the bit time"]
442    pub mod PSEG2 {
443        pub const offset: u32 = 16;
444        pub const mask: u32 = 0x07 << offset;
445        pub mod R {}
446        pub mod W {}
447        pub mod RW {}
448    }
449    #[doc = "This 3-bit field defines the length of Phase Buffer Segment 1 in the bit time"]
450    pub mod PSEG1 {
451        pub const offset: u32 = 19;
452        pub const mask: u32 = 0x07 << offset;
453        pub mod R {}
454        pub mod W {}
455        pub mod RW {}
456    }
457    #[doc = "This 2-bit field defines the maximum number of time quanta One time quantum is equal to the Sclock period"]
458    pub mod RJW {
459        pub const offset: u32 = 22;
460        pub const mask: u32 = 0x03 << offset;
461        pub mod R {}
462        pub mod W {}
463        pub mod RW {}
464    }
465    #[doc = "This 8-bit field defines the ratio between the PE clock frequency and the Serial Clock (Sclock) frequency"]
466    pub mod PRESDIV {
467        pub const offset: u32 = 24;
468        pub const mask: u32 = 0xff << offset;
469        pub mod R {}
470        pub mod W {}
471        pub mod RW {}
472    }
473}
474#[doc = "Free Running Timer Register"]
475pub mod TIMER {
476    #[doc = "TIMER"]
477    pub mod TIMER {
478        pub const offset: u32 = 0;
479        pub const mask: u32 = 0xffff << offset;
480        pub mod R {}
481        pub mod W {}
482        pub mod RW {}
483    }
484}
485#[doc = "Rx Mailboxes Global Mask Register"]
486pub mod RXMGMASK {
487    #[doc = "These bits mask the Mailbox filter bits as shown in the figure above"]
488    pub mod MG {
489        pub const offset: u32 = 0;
490        pub const mask: u32 = 0xffff_ffff << offset;
491        pub mod R {}
492        pub mod W {}
493        pub mod RW {
494            #[doc = "the corresponding bit in the filter is \"don't care\""]
495            pub const MG_0: u32 = 0;
496            #[doc = "The corresponding bit in the filter is checked against the one received"]
497            pub const MG_1: u32 = 0x01;
498        }
499    }
500}
501#[doc = "Rx Buffer 14 Mask Register"]
502pub mod RX14MASK {
503    #[doc = "These bits mask Mailbox 14 filter bits in the same fashion as RXMGMASK masks other Mailboxes filters (see RXMGMASKRx Mailboxes Global Mask Register )"]
504    pub mod RX14M {
505        pub const offset: u32 = 0;
506        pub const mask: u32 = 0xffff_ffff << offset;
507        pub mod R {}
508        pub mod W {}
509        pub mod RW {
510            #[doc = "the corresponding bit in the filter is \"don't care\""]
511            pub const RX14M_0: u32 = 0;
512            #[doc = "The corresponding bit in the filter is checked"]
513            pub const RX14M_1: u32 = 0x01;
514        }
515    }
516}
517#[doc = "Rx Buffer 15 Mask Register"]
518pub mod RX15MASK {
519    #[doc = "These bits mask Mailbox 15 filter bits in the same fashion as RXMGMASK masks other Mailboxes filters (see RXMGMASKRx Mailboxes Global Mask Register )"]
520    pub mod RX15M {
521        pub const offset: u32 = 0;
522        pub const mask: u32 = 0xffff_ffff << offset;
523        pub mod R {}
524        pub mod W {}
525        pub mod RW {
526            #[doc = "the corresponding bit in the filter is \"don't care\""]
527            pub const RX15M_0: u32 = 0;
528            #[doc = "The corresponding bit in the filter is checked"]
529            pub const RX15M_1: u32 = 0x01;
530        }
531    }
532}
533#[doc = "Error Counter Register"]
534pub mod ECR {
535    #[doc = "Tx_Err_Counter"]
536    pub mod TX_ERR_COUNTER {
537        pub const offset: u32 = 0;
538        pub const mask: u32 = 0xff << offset;
539        pub mod R {}
540        pub mod W {}
541        pub mod RW {}
542    }
543    #[doc = "Rx_Err_Counter"]
544    pub mod RX_ERR_COUNTER {
545        pub const offset: u32 = 8;
546        pub const mask: u32 = 0xff << offset;
547        pub mod R {}
548        pub mod W {}
549        pub mod RW {}
550    }
551}
552#[doc = "Error and Status 1 Register"]
553pub mod ESR1 {
554    #[doc = "When FLEXCAN is Stop Mode and a recessive to dominant transition is detected on the CAN bus and if the WAK_MSK bit in the MCR Register is set, an interrupt is generated to the Arm"]
555    pub mod WAKINT {
556        pub const offset: u32 = 0;
557        pub const mask: u32 = 0x01 << offset;
558        pub mod R {}
559        pub mod W {}
560        pub mod RW {
561            #[doc = "No such occurrence"]
562            pub const WAKINT_0: u32 = 0;
563            #[doc = "Indicates a recessive to dominant transition received on the CAN bus when the FLEXCAN module is in Stop Mode"]
564            pub const WAKINT_1: u32 = 0x01;
565        }
566    }
567    #[doc = "This bit indicates that at least one of the Error Bits (bits 15-10) is set"]
568    pub mod ERRINT {
569        pub const offset: u32 = 1;
570        pub const mask: u32 = 0x01 << offset;
571        pub mod R {}
572        pub mod W {}
573        pub mod RW {
574            #[doc = "No such occurrence"]
575            pub const ERRINT_0: u32 = 0;
576            #[doc = "Indicates setting of any Error Bit in the Error and Status Register"]
577            pub const ERRINT_1: u32 = 0x01;
578        }
579    }
580    #[doc = "This bit is set when FLEXCAN enters 'Bus Off' state"]
581    pub mod BOFFINT {
582        pub const offset: u32 = 2;
583        pub const mask: u32 = 0x01 << offset;
584        pub mod R {}
585        pub mod W {}
586        pub mod RW {
587            #[doc = "No such occurrence"]
588            pub const BOFFINT_0: u32 = 0;
589            #[doc = "FLEXCAN module entered 'Bus Off' state"]
590            pub const BOFFINT_1: u32 = 0x01;
591        }
592    }
593    #[doc = "This bit indicates if FlexCAN is receiving a message. Refer to ."]
594    pub mod RX {
595        pub const offset: u32 = 3;
596        pub const mask: u32 = 0x01 << offset;
597        pub mod R {}
598        pub mod W {}
599        pub mod RW {
600            #[doc = "FLEXCAN is receiving a message"]
601            pub const RX_0: u32 = 0;
602            #[doc = "FLEXCAN is transmitting a message"]
603            pub const RX_1: u32 = 0x01;
604        }
605    }
606    #[doc = "If the LOM bit in the Control Register is asserted, after some delay that depends on the CAN bit timing the FLT_CONF field will indicate \"Error Passive\""]
607    pub mod FLTCONF {
608        pub const offset: u32 = 4;
609        pub const mask: u32 = 0x03 << offset;
610        pub mod R {}
611        pub mod W {}
612        pub mod RW {
613            #[doc = "Error Active"]
614            pub const FLTCONF_0: u32 = 0;
615            #[doc = "Error Passive"]
616            pub const FLTCONF_1: u32 = 0x01;
617            #[doc = "Bus off"]
618            pub const FLTCONF_2: u32 = 0x02;
619        }
620    }
621    #[doc = "This bit indicates if FLEXCAN is transmitting a message.Refer to ."]
622    pub mod TX {
623        pub const offset: u32 = 6;
624        pub const mask: u32 = 0x01 << offset;
625        pub mod R {}
626        pub mod W {}
627        pub mod RW {
628            #[doc = "FLEXCAN is receiving a message"]
629            pub const TX_0: u32 = 0;
630            #[doc = "FLEXCAN is transmitting a message"]
631            pub const TX_1: u32 = 0x01;
632        }
633    }
634    #[doc = "This bit indicates when CAN bus is in IDLE state.Refer to ."]
635    pub mod IDLE {
636        pub const offset: u32 = 7;
637        pub const mask: u32 = 0x01 << offset;
638        pub mod R {}
639        pub mod W {}
640        pub mod RW {
641            #[doc = "No such occurrence"]
642            pub const IDLE_0: u32 = 0;
643            #[doc = "CAN bus is now IDLE"]
644            pub const IDLE_1: u32 = 0x01;
645        }
646    }
647    #[doc = "This bit indicates when repetitive errors are occurring during message reception."]
648    pub mod RXWRN {
649        pub const offset: u32 = 8;
650        pub const mask: u32 = 0x01 << offset;
651        pub mod R {}
652        pub mod W {}
653        pub mod RW {
654            #[doc = "No such occurrence"]
655            pub const RXWRN_0: u32 = 0;
656            #[doc = "Rx_Err_Counter >= 96"]
657            pub const RXWRN_1: u32 = 0x01;
658        }
659    }
660    #[doc = "This bit indicates when repetitive errors are occurring during message transmission."]
661    pub mod TXWRN {
662        pub const offset: u32 = 9;
663        pub const mask: u32 = 0x01 << offset;
664        pub mod R {}
665        pub mod W {}
666        pub mod RW {
667            #[doc = "No such occurrence"]
668            pub const TXWRN_0: u32 = 0;
669            #[doc = "TX_Err_Counter >= 96"]
670            pub const TXWRN_1: u32 = 0x01;
671        }
672    }
673    #[doc = "This bit indicates that a Stuffing Error has been detected."]
674    pub mod STFERR {
675        pub const offset: u32 = 10;
676        pub const mask: u32 = 0x01 << offset;
677        pub mod R {}
678        pub mod W {}
679        pub mod RW {
680            #[doc = "No such occurrence."]
681            pub const STFERR_0: u32 = 0;
682            #[doc = "A Stuffing Error occurred since last read of this register."]
683            pub const STFERR_1: u32 = 0x01;
684        }
685    }
686    #[doc = "This bit indicates that a Form Error has been detected by the receiver node, i"]
687    pub mod FRMERR {
688        pub const offset: u32 = 11;
689        pub const mask: u32 = 0x01 << offset;
690        pub mod R {}
691        pub mod W {}
692        pub mod RW {
693            #[doc = "No such occurrence"]
694            pub const FRMERR_0: u32 = 0;
695            #[doc = "A Form Error occurred since last read of this register"]
696            pub const FRMERR_1: u32 = 0x01;
697        }
698    }
699    #[doc = "This bit indicates that a CRC Error has been detected by the receiver node, i"]
700    pub mod CRCERR {
701        pub const offset: u32 = 12;
702        pub const mask: u32 = 0x01 << offset;
703        pub mod R {}
704        pub mod W {}
705        pub mod RW {
706            #[doc = "No such occurrence"]
707            pub const CRCERR_0: u32 = 0;
708            #[doc = "A CRC error occurred since last read of this register."]
709            pub const CRCERR_1: u32 = 0x01;
710        }
711    }
712    #[doc = "This bit indicates that an Acknowledge Error has been detected by the transmitter node, i"]
713    pub mod ACKERR {
714        pub const offset: u32 = 13;
715        pub const mask: u32 = 0x01 << offset;
716        pub mod R {}
717        pub mod W {}
718        pub mod RW {
719            #[doc = "No such occurrence"]
720            pub const ACKERR_0: u32 = 0;
721            #[doc = "An ACK error occurred since last read of this register"]
722            pub const ACKERR_1: u32 = 0x01;
723        }
724    }
725    #[doc = "This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message"]
726    pub mod BIT0ERR {
727        pub const offset: u32 = 14;
728        pub const mask: u32 = 0x01 << offset;
729        pub mod R {}
730        pub mod W {}
731        pub mod RW {
732            #[doc = "No such occurrence"]
733            pub const BIT0ERR_0: u32 = 0;
734            #[doc = "At least one bit sent as dominant is received as recessive"]
735            pub const BIT0ERR_1: u32 = 0x01;
736        }
737    }
738    #[doc = "This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message"]
739    pub mod BIT1ERR {
740        pub const offset: u32 = 15;
741        pub const mask: u32 = 0x01 << offset;
742        pub mod R {}
743        pub mod W {}
744        pub mod RW {
745            #[doc = "No such occurrence"]
746            pub const BIT1ERR_0: u32 = 0;
747            #[doc = "At least one bit sent as recessive is received as dominant"]
748            pub const BIT1ERR_1: u32 = 0x01;
749        }
750    }
751    #[doc = "If the WRN_EN bit in MCR is asserted, the RWRN_INT bit is set when the RX_WRN flag transition from '0' to '1', meaning that the Rx error counters reached 96"]
752    pub mod RWRNINT {
753        pub const offset: u32 = 16;
754        pub const mask: u32 = 0x01 << offset;
755        pub mod R {}
756        pub mod W {}
757        pub mod RW {
758            #[doc = "No such occurrence"]
759            pub const RWRNINT_0: u32 = 0;
760            #[doc = "The Rx error counter transition from < 96 to >= 96"]
761            pub const RWRNINT_1: u32 = 0x01;
762        }
763    }
764    #[doc = "If the WRN_EN bit in MCR is asserted, the TWRN_INT bit is set when the TX_WRN flag transition from '0' to '1', meaning that the Tx error counter reached 96"]
765    pub mod TWRNINT {
766        pub const offset: u32 = 17;
767        pub const mask: u32 = 0x01 << offset;
768        pub mod R {}
769        pub mod W {}
770        pub mod RW {
771            #[doc = "No such occurrence"]
772            pub const TWRNINT_0: u32 = 0;
773            #[doc = "The Tx error counter transition from < 96 to >= 96"]
774            pub const TWRNINT_1: u32 = 0x01;
775        }
776    }
777    #[doc = "This read-only flag indicates whether the FlexCAN is synchronized to the CAN bus and able to participate in the communication process"]
778    pub mod SYNCH {
779        pub const offset: u32 = 18;
780        pub const mask: u32 = 0x01 << offset;
781        pub mod R {}
782        pub mod W {}
783        pub mod RW {
784            #[doc = "FlexCAN is not synchronized to the CAN bus"]
785            pub const SYNCH_0: u32 = 0;
786            #[doc = "FlexCAN is synchronized to the CAN bus"]
787            pub const SYNCH_1: u32 = 0x01;
788        }
789    }
790}
791#[doc = "Interrupt Masks 2 Register"]
792pub mod IMASK2 {
793    #[doc = "Each bit enables or disables the respective FLEXCAN Message Buffer (MB32 to MB63) Interrupt"]
794    pub mod BUFHM {
795        pub const offset: u32 = 0;
796        pub const mask: u32 = 0xffff_ffff << offset;
797        pub mod R {}
798        pub mod W {}
799        pub mod RW {
800            #[doc = "The corresponding buffer Interrupt is disabled"]
801            pub const BUFHM_0: u32 = 0;
802            #[doc = "The corresponding buffer Interrupt is enabled"]
803            pub const BUFHM_1: u32 = 0x01;
804        }
805    }
806}
807#[doc = "Interrupt Masks 1 Register"]
808pub mod IMASK1 {
809    #[doc = "Each bit enables or disables the respective FLEXCAN Message Buffer (MB0 to MB31) Interrupt"]
810    pub mod BUFLM {
811        pub const offset: u32 = 0;
812        pub const mask: u32 = 0xffff_ffff << offset;
813        pub mod R {}
814        pub mod W {}
815        pub mod RW {
816            #[doc = "The corresponding buffer Interrupt is disabled"]
817            pub const BUFLM_0: u32 = 0;
818            #[doc = "The corresponding buffer Interrupt is enabled"]
819            pub const BUFLM_1: u32 = 0x01;
820        }
821    }
822}
823#[doc = "Interrupt Flags 2 Register"]
824pub mod IFLAG2 {
825    #[doc = "Each bit flags the respective FLEXCAN Message Buffer (MB32 to MB63) interrupt."]
826    pub mod BUFHI {
827        pub const offset: u32 = 0;
828        pub const mask: u32 = 0xffff_ffff << offset;
829        pub mod R {}
830        pub mod W {}
831        pub mod RW {
832            #[doc = "No such occurrence"]
833            pub const BUFHI_0: u32 = 0;
834            #[doc = "The corresponding buffer has successfully completed transmission or reception"]
835            pub const BUFHI_1: u32 = 0x01;
836        }
837    }
838}
839#[doc = "Interrupt Flags 1 Register"]
840pub mod IFLAG1 {
841    #[doc = "If the Rx FIFO is not enabled, these bits flag the interrupts for MB0 to MB4"]
842    pub mod BUF4TO0I {
843        pub const offset: u32 = 0;
844        pub const mask: u32 = 0x1f << offset;
845        pub mod R {}
846        pub mod W {}
847        pub mod RW {
848            #[doc = "No such occurrence"]
849            pub const BUF4TO0I_0: u32 = 0;
850            #[doc = "Corresponding MB completed transmission/reception"]
851            pub const BUF4TO0I_1: u32 = 0x01;
852        }
853    }
854    #[doc = "If the Rx FIFO is not enabled, this bit flags the interrupt for MB5"]
855    pub mod BUF5I {
856        pub const offset: u32 = 5;
857        pub const mask: u32 = 0x01 << offset;
858        pub mod R {}
859        pub mod W {}
860        pub mod RW {
861            #[doc = "No such occurrence"]
862            pub const BUF5I_0: u32 = 0;
863            #[doc = "MB5 completed transmission/reception or frames available in the FIFO"]
864            pub const BUF5I_1: u32 = 0x01;
865        }
866    }
867    #[doc = "If the Rx FIFO is not enabled, this bit flags the interrupt for MB6"]
868    pub mod BUF6I {
869        pub const offset: u32 = 6;
870        pub const mask: u32 = 0x01 << offset;
871        pub mod R {}
872        pub mod W {}
873        pub mod RW {
874            #[doc = "No such occurrence"]
875            pub const BUF6I_0: u32 = 0;
876            #[doc = "MB6 completed transmission/reception or FIFO almost full"]
877            pub const BUF6I_1: u32 = 0x01;
878        }
879    }
880    #[doc = "If the Rx FIFO is not enabled, this bit flags the interrupt for MB7"]
881    pub mod BUF7I {
882        pub const offset: u32 = 7;
883        pub const mask: u32 = 0x01 << offset;
884        pub mod R {}
885        pub mod W {}
886        pub mod RW {
887            #[doc = "No such occurrence"]
888            pub const BUF7I_0: u32 = 0;
889            #[doc = "MB7 completed transmission/reception or FIFO overflow"]
890            pub const BUF7I_1: u32 = 0x01;
891        }
892    }
893    #[doc = "Each bit flags the respective FLEXCAN Message Buffer (MB8 to MB31) interrupt."]
894    pub mod BUF31TO8I {
895        pub const offset: u32 = 8;
896        pub const mask: u32 = 0x00ff_ffff << offset;
897        pub mod R {}
898        pub mod W {}
899        pub mod RW {
900            #[doc = "No such occurrence"]
901            pub const BUF31TO8I_0: u32 = 0;
902            #[doc = "The corresponding MB has successfully completed transmission or reception"]
903            pub const BUF31TO8I_1: u32 = 0x01;
904        }
905    }
906}
907#[doc = "Control 2 Register"]
908pub mod CTRL2 {
909    #[doc = "This bit controls the comparison of IDE and RTR bits within Rx Mailboxes filters with their corresponding bits in the incoming frame by the matching process"]
910    pub mod EACEN {
911        pub const offset: u32 = 16;
912        pub const mask: u32 = 0x01 << offset;
913        pub mod R {}
914        pub mod W {}
915        pub mod RW {
916            #[doc = "Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits."]
917            pub const EACEN_0: u32 = 0;
918            #[doc = "Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply."]
919            pub const EACEN_1: u32 = 0x01;
920        }
921    }
922    #[doc = "If this bit is asserted Remote Request Frame is submitted to a matching process and stored in the corresponding Message Buffer in the same fashion of a Data Frame"]
923    pub mod RRS {
924        pub const offset: u32 = 17;
925        pub const mask: u32 = 0x01 << offset;
926        pub mod R {}
927        pub mod W {}
928        pub mod RW {
929            #[doc = "Remote Response Frame is generated"]
930            pub const RRS_0: u32 = 0;
931            #[doc = "Remote Request Frame is stored"]
932            pub const RRS_1: u32 = 0x01;
933        }
934    }
935    #[doc = "If this bit is set the matching process starts from the Mailboxes and if no match occurs the matching continues on the Rx FIFO"]
936    pub mod MRP {
937        pub const offset: u32 = 18;
938        pub const mask: u32 = 0x01 << offset;
939        pub mod R {}
940        pub mod W {}
941        pub mod RW {
942            #[doc = "Matching starts from Rx FIFO and continues on Mailboxes"]
943            pub const MRP_0: u32 = 0;
944            #[doc = "Matching starts from Mailboxes and continues on Rx FIFO"]
945            pub const MRP_1: u32 = 0x01;
946        }
947    }
948    #[doc = "This 5-bit field indicates how many CAN bits the Tx arbitration process start point can be delayed from the first bit of CRC field on CAN bus"]
949    pub mod TASD {
950        pub const offset: u32 = 19;
951        pub const mask: u32 = 0x1f << offset;
952        pub mod R {}
953        pub mod W {}
954        pub mod RW {}
955    }
956    #[doc = "This 4-bit field defines the number of Rx FIFO filters according to"]
957    pub mod RFFN {
958        pub const offset: u32 = 24;
959        pub const mask: u32 = 0x0f << offset;
960        pub mod R {}
961        pub mod W {}
962        pub mod RW {}
963    }
964    #[doc = "Enable unrestricted write access to FlexCAN memory in Freeze mode"]
965    pub mod WRMFRZ {
966        pub const offset: u32 = 28;
967        pub const mask: u32 = 0x01 << offset;
968        pub mod R {}
969        pub mod W {}
970        pub mod RW {
971            #[doc = "Keep the write access restricted in some regions of FlexCAN memory"]
972            pub const WRMFRZ_0: u32 = 0;
973            #[doc = "Enable unrestricted write access to FlexCAN memory"]
974            pub const WRMFRZ_1: u32 = 0x01;
975        }
976    }
977}
978#[doc = "Error and Status 2 Register"]
979pub mod ESR2 {
980    #[doc = "If ESR2\\[VPS\\] is asserted, this bit indicates whether there is any inactive Mailbox (CODE field is either 0b1000 or 0b0000)"]
981    pub mod IMB {
982        pub const offset: u32 = 13;
983        pub const mask: u32 = 0x01 << offset;
984        pub mod R {}
985        pub mod W {}
986        pub mod RW {
987            #[doc = "If ESR2\\[VPS\\] is asserted, the ESR2\\[LPTM\\] is not an inactive Mailbox."]
988            pub const IMB_0: u32 = 0;
989            #[doc = "If ESR2\\[VPS\\] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one."]
990            pub const IMB_1: u32 = 0x01;
991        }
992    }
993    #[doc = "This bit indicates whether IMB and LPTM contents are currently valid or not"]
994    pub mod VPS {
995        pub const offset: u32 = 14;
996        pub const mask: u32 = 0x01 << offset;
997        pub mod R {}
998        pub mod W {}
999        pub mod RW {
1000            #[doc = "Contents of IMB and LPTM are invalid"]
1001            pub const VPS_0: u32 = 0;
1002            #[doc = "Contents of IMB and LPTM are valid"]
1003            pub const VPS_1: u32 = 0x01;
1004        }
1005    }
1006    #[doc = "If ESR2\\[VPS\\] is asserted, his 7-bit field indicates the lowest number inactive Mailbox (refer to IMB bit description)"]
1007    pub mod LPTM {
1008        pub const offset: u32 = 16;
1009        pub const mask: u32 = 0x7f << offset;
1010        pub mod R {}
1011        pub mod W {}
1012        pub mod RW {}
1013    }
1014}
1015#[doc = "CRC Register"]
1016pub mod CRCR {
1017    #[doc = "This field indicates the CRC value of the last message transmitted"]
1018    pub mod TXCRC {
1019        pub const offset: u32 = 0;
1020        pub const mask: u32 = 0x7fff << offset;
1021        pub mod R {}
1022        pub mod W {}
1023        pub mod RW {}
1024    }
1025    #[doc = "This field indicates the number of the Mailbox corresponding to the value in TXCRC field."]
1026    pub mod MBCRC {
1027        pub const offset: u32 = 16;
1028        pub const mask: u32 = 0x7f << offset;
1029        pub mod R {}
1030        pub mod W {}
1031        pub mod RW {}
1032    }
1033}
1034#[doc = "Rx FIFO Global Mask Register"]
1035pub mod RXFGMASK {
1036    #[doc = "These bits mask the ID Filter Table elements bits in a perfect alignment"]
1037    pub mod FGM {
1038        pub const offset: u32 = 0;
1039        pub const mask: u32 = 0xffff_ffff << offset;
1040        pub mod R {}
1041        pub mod W {}
1042        pub mod RW {
1043            #[doc = "The corresponding bit in the filter is \"don't care\""]
1044            pub const FGM_0: u32 = 0;
1045            #[doc = "The corresponding bit in the filter is checked"]
1046            pub const FGM_1: u32 = 0x01;
1047        }
1048    }
1049}
1050#[doc = "Rx FIFO Information Register"]
1051pub mod RXFIR {
1052    #[doc = "This 9-bit field indicates which Identifier Acceptance Filter (see Rx FIFO Structure) was hit by the received message that is in the output of the Rx FIFO"]
1053    pub mod IDHIT {
1054        pub const offset: u32 = 0;
1055        pub const mask: u32 = 0x01ff << offset;
1056        pub mod R {}
1057        pub mod W {}
1058        pub mod RW {}
1059    }
1060}
1061#[doc = "Debug 1 register"]
1062pub mod DBG1 {
1063    #[doc = "CAN Finite State Machine"]
1064    pub mod CFSM {
1065        pub const offset: u32 = 0;
1066        pub const mask: u32 = 0x3f << offset;
1067        pub mod R {}
1068        pub mod W {}
1069        pub mod RW {}
1070    }
1071    #[doc = "CAN Bit Number"]
1072    pub mod CBN {
1073        pub const offset: u32 = 24;
1074        pub const mask: u32 = 0x1f << offset;
1075        pub mod R {}
1076        pub mod W {}
1077        pub mod RW {}
1078    }
1079}
1080#[doc = "Debug 2 register"]
1081pub mod DBG2 {
1082    #[doc = "Rx Matching Pointer"]
1083    pub mod RMP {
1084        pub const offset: u32 = 0;
1085        pub const mask: u32 = 0x7f << offset;
1086        pub mod R {}
1087        pub mod W {}
1088        pub mod RW {}
1089    }
1090    #[doc = "Matching Process in Progress"]
1091    pub mod MPP {
1092        pub const offset: u32 = 7;
1093        pub const mask: u32 = 0x01 << offset;
1094        pub mod R {}
1095        pub mod W {}
1096        pub mod RW {
1097            #[doc = "No matching process ongoing."]
1098            pub const MPP_0: u32 = 0;
1099            #[doc = "Matching process is in progress."]
1100            pub const MPP_1: u32 = 0x01;
1101        }
1102    }
1103    #[doc = "Tx Arbitration Pointer"]
1104    pub mod TAP {
1105        pub const offset: u32 = 8;
1106        pub const mask: u32 = 0x7f << offset;
1107        pub mod R {}
1108        pub mod W {}
1109        pub mod RW {}
1110    }
1111    #[doc = "Arbitration Process in Progress"]
1112    pub mod APP {
1113        pub const offset: u32 = 15;
1114        pub const mask: u32 = 0x01 << offset;
1115        pub mod R {}
1116        pub mod W {}
1117        pub mod RW {
1118            #[doc = "No matching process ongoing."]
1119            pub const APP_0: u32 = 0;
1120            #[doc = "Matching process is in progress."]
1121            pub const APP_1: u32 = 0x01;
1122        }
1123    }
1124}
1125#[doc = "Rx Individual Mask Registers"]
1126pub mod RXIMR {
1127    #[doc = "These bits mask both Mailbox filter and Rx FIFO ID Filter Table element in distinct ways"]
1128    pub mod MI {
1129        pub const offset: u32 = 0;
1130        pub const mask: u32 = 0xffff_ffff << offset;
1131        pub mod R {}
1132        pub mod W {}
1133        pub mod RW {
1134            #[doc = "the corresponding bit in the filter is \"don't care\""]
1135            pub const MI_0: u32 = 0;
1136            #[doc = "The corresponding bit in the filter is checked"]
1137            pub const MI_1: u32 = 0x01;
1138        }
1139    }
1140}
1141#[doc = "Glitch Filter Width Registers"]
1142pub mod GFWR {
1143    #[doc = "It determines the Glitch Filter Width"]
1144    pub mod GFWR {
1145        pub const offset: u32 = 0;
1146        pub const mask: u32 = 0xff << offset;
1147        pub mod R {}
1148        pub mod W {}
1149        pub mod RW {}
1150    }
1151}