1#[doc = "CAN"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "Module Configuration Register"]
5 pub MCR: crate::RWRegister<u32>,
6 #[doc = "Control 1 register"]
7 pub CTRL1: crate::RWRegister<u32>,
8 #[doc = "Free Running Timer"]
9 pub TIMER: crate::RWRegister<u32>,
10 _reserved0: [u8; 0x04],
11 #[doc = "Rx Mailboxes Global Mask Register"]
12 pub RXMGMASK: crate::RWRegister<u32>,
13 #[doc = "Rx 14 Mask register"]
14 pub RX14MASK: crate::RWRegister<u32>,
15 #[doc = "Rx 15 Mask register"]
16 pub RX15MASK: crate::RWRegister<u32>,
17 #[doc = "Error Counter"]
18 pub ECR: crate::RWRegister<u32>,
19 #[doc = "Error and Status 1 register"]
20 pub ESR1: crate::RWRegister<u32>,
21 #[doc = "Interrupt Masks 2 register"]
22 pub IMASK2: crate::RWRegister<u32>,
23 #[doc = "Interrupt Masks 1 register"]
24 pub IMASK1: crate::RWRegister<u32>,
25 #[doc = "Interrupt Flags 2 register"]
26 pub IFLAG2: crate::RWRegister<u32>,
27 #[doc = "Interrupt Flags 1 register"]
28 pub IFLAG1: crate::RWRegister<u32>,
29 #[doc = "Control 2 register"]
30 pub CTRL2: crate::RWRegister<u32>,
31 #[doc = "Error and Status 2 register"]
32 pub ESR2: crate::RORegister<u32>,
33 _reserved1: [u8; 0x08],
34 #[doc = "CRC Register"]
35 pub CRCR: crate::RORegister<u32>,
36 #[doc = "Legacy Rx FIFO Global Mask register"]
37 pub RXFGMASK: crate::RWRegister<u32>,
38 #[doc = "Legacy Rx FIFO Information Register"]
39 pub RXFIR: crate::RORegister<u32>,
40 #[doc = "CAN Bit Timing Register"]
41 pub CBT: crate::RWRegister<u32>,
42 _reserved2: [u8; 0x2c],
43 #[doc = "Message Buffer 0 CS Register"]
44 pub CS0: crate::RWRegister<u32>,
45 #[doc = "Message Buffer 0 ID Register"]
46 pub ID0: crate::RWRegister<u32>,
47 #[doc = "Message Buffer 0 WORD_16B Register"]
48 pub MB0_16B_WORD0: crate::RWRegister<u32>,
49 #[doc = "Message Buffer 0 WORD_16B Register"]
50 pub MB0_16B_WORD1: crate::RWRegister<u32>,
51 #[doc = "Message Buffer 1 CS Register"]
52 pub CS1: crate::RWRegister<u32>,
53 #[doc = "Message Buffer 1 ID Register"]
54 pub ID1: crate::RWRegister<u32>,
55 #[doc = "Message Buffer 0 WORD_32B Register"]
56 pub MB0_32B_WORD4: crate::RWRegister<u32>,
57 #[doc = "Message Buffer 0 WORD_32B Register"]
58 pub MB0_32B_WORD5: crate::RWRegister<u32>,
59 #[doc = "Message Buffer 2 CS Register"]
60 pub CS2: crate::RWRegister<u32>,
61 #[doc = "Message Buffer 2 ID Register"]
62 pub ID2: crate::RWRegister<u32>,
63 #[doc = "Message Buffer 0 WORD_64B Register"]
64 pub MB0_64B_WORD8: crate::RWRegister<u32>,
65 #[doc = "Message Buffer 0 WORD_64B Register"]
66 pub MB0_64B_WORD9: crate::RWRegister<u32>,
67 #[doc = "Message Buffer 3 CS Register"]
68 pub CS3: crate::RWRegister<u32>,
69 #[doc = "Message Buffer 3 ID Register"]
70 pub ID3: crate::RWRegister<u32>,
71 #[doc = "Message Buffer 0 WORD_64B Register"]
72 pub MB0_64B_WORD12: crate::RWRegister<u32>,
73 #[doc = "Message Buffer 0 WORD_64B Register"]
74 pub MB0_64B_WORD13: crate::RWRegister<u32>,
75 #[doc = "Message Buffer 4 CS Register"]
76 pub CS4: crate::RWRegister<u32>,
77 #[doc = "Message Buffer 4 ID Register"]
78 pub ID4: crate::RWRegister<u32>,
79 #[doc = "Message Buffer 1 WORD_32B Register"]
80 pub MB1_32B_WORD6: crate::RWRegister<u32>,
81 #[doc = "Message Buffer 1 WORD_32B Register"]
82 pub MB1_32B_WORD7: crate::RWRegister<u32>,
83 #[doc = "Message Buffer 5 CS Register"]
84 pub CS5: crate::RWRegister<u32>,
85 #[doc = "Message Buffer 5 ID Register"]
86 pub ID5: crate::RWRegister<u32>,
87 #[doc = "Message Buffer 1 WORD_64B Register"]
88 pub MB1_64B_WORD2: crate::RWRegister<u32>,
89 #[doc = "Message Buffer 1 WORD_64B Register"]
90 pub MB1_64B_WORD3: crate::RWRegister<u32>,
91 #[doc = "Message Buffer 6 CS Register"]
92 pub CS6: crate::RWRegister<u32>,
93 #[doc = "Message Buffer 6 ID Register"]
94 pub ID6: crate::RWRegister<u32>,
95 #[doc = "Message Buffer 1 WORD_64B Register"]
96 pub MB1_64B_WORD6: crate::RWRegister<u32>,
97 #[doc = "Message Buffer 1 WORD_64B Register"]
98 pub MB1_64B_WORD7: crate::RWRegister<u32>,
99 #[doc = "Message Buffer 7 CS Register"]
100 pub CS7: crate::RWRegister<u32>,
101 #[doc = "Message Buffer 7 ID Register"]
102 pub ID7: crate::RWRegister<u32>,
103 #[doc = "Message Buffer 1 WORD_64B Register"]
104 pub MB1_64B_WORD10: crate::RWRegister<u32>,
105 #[doc = "Message Buffer 1 WORD_64B Register"]
106 pub MB1_64B_WORD11: crate::RWRegister<u32>,
107 #[doc = "Message Buffer 8 CS Register"]
108 pub CS8: crate::RWRegister<u32>,
109 #[doc = "Message Buffer 8 ID Register"]
110 pub ID8: crate::RWRegister<u32>,
111 #[doc = "Message Buffer 1 WORD_64B Register"]
112 pub MB1_64B_WORD14: crate::RWRegister<u32>,
113 #[doc = "Message Buffer 1 WORD_64B Register"]
114 pub MB1_64B_WORD15: crate::RWRegister<u32>,
115 #[doc = "Message Buffer 9 CS Register"]
116 pub CS9: crate::RWRegister<u32>,
117 #[doc = "Message Buffer 9 ID Register"]
118 pub ID9: crate::RWRegister<u32>,
119 #[doc = "Message Buffer 2 WORD_64B Register"]
120 pub MB2_64B_WORD0: crate::RWRegister<u32>,
121 #[doc = "Message Buffer 2 WORD_64B Register"]
122 pub MB2_64B_WORD1: crate::RWRegister<u32>,
123 #[doc = "Message Buffer 10 CS Register"]
124 pub CS10: crate::RWRegister<u32>,
125 #[doc = "Message Buffer 10 ID Register"]
126 pub ID10: crate::RWRegister<u32>,
127 #[doc = "Message Buffer 10 WORD_8B Register"]
128 pub MB10_8B_WORD0: crate::RWRegister<u32>,
129 #[doc = "Message Buffer 10 WORD_8B Register"]
130 pub MB10_8B_WORD1: crate::RWRegister<u32>,
131 #[doc = "Message Buffer 11 CS Register"]
132 pub CS11: crate::RWRegister<u32>,
133 #[doc = "Message Buffer 11 ID Register"]
134 pub ID11: crate::RWRegister<u32>,
135 #[doc = "Message Buffer 11 WORD_8B Register"]
136 pub MB11_8B_WORD0: crate::RWRegister<u32>,
137 #[doc = "Message Buffer 11 WORD_8B Register"]
138 pub MB11_8B_WORD1: crate::RWRegister<u32>,
139 #[doc = "Message Buffer 12 CS Register"]
140 pub CS12: crate::RWRegister<u32>,
141 #[doc = "Message Buffer 12 ID Register"]
142 pub ID12: crate::RWRegister<u32>,
143 #[doc = "Message Buffer 12 WORD_8B Register"]
144 pub MB12_8B_WORD0: crate::RWRegister<u32>,
145 #[doc = "Message Buffer 12 WORD_8B Register"]
146 pub MB12_8B_WORD1: crate::RWRegister<u32>,
147 #[doc = "Message Buffer 13 CS Register"]
148 pub CS13: crate::RWRegister<u32>,
149 #[doc = "Message Buffer 13 ID Register"]
150 pub ID13: crate::RWRegister<u32>,
151 #[doc = "Message Buffer 13 WORD_8B Register"]
152 pub MB13_8B_WORD0: crate::RWRegister<u32>,
153 #[doc = "Message Buffer 13 WORD_8B Register"]
154 pub MB13_8B_WORD1: crate::RWRegister<u32>,
155 #[doc = "Message Buffer 14 CS Register"]
156 pub CS14: crate::RWRegister<u32>,
157 #[doc = "Message Buffer 14 ID Register"]
158 pub ID14: crate::RWRegister<u32>,
159 #[doc = "Message Buffer 14 WORD_8B Register"]
160 pub MB14_8B_WORD0: crate::RWRegister<u32>,
161 #[doc = "Message Buffer 14 WORD_8B Register"]
162 pub MB14_8B_WORD1: crate::RWRegister<u32>,
163 #[doc = "Message Buffer 15 CS Register"]
164 pub CS15: crate::RWRegister<u32>,
165 #[doc = "Message Buffer 15 ID Register"]
166 pub ID15: crate::RWRegister<u32>,
167 #[doc = "Message Buffer 10 WORD_16B Register"]
168 pub MB10_16B_WORD0: crate::RWRegister<u32>,
169 #[doc = "Message Buffer 10 WORD_16B Register"]
170 pub MB10_16B_WORD1: crate::RWRegister<u32>,
171 #[doc = "Message Buffer 16 CS Register"]
172 pub CS16: crate::RWRegister<u32>,
173 #[doc = "Message Buffer 16 ID Register"]
174 pub ID16: crate::RWRegister<u32>,
175 #[doc = "Message Buffer 11 CS Register"]
176 pub MB11_16B_CS: crate::RWRegister<u32>,
177 #[doc = "Message Buffer 11 ID Register"]
178 pub MB11_16B_ID: crate::RWRegister<u32>,
179 #[doc = "Message Buffer 17 CS Register"]
180 pub CS17: crate::RWRegister<u32>,
181 #[doc = "Message Buffer 17 ID Register"]
182 pub ID17: crate::RWRegister<u32>,
183 #[doc = "Message Buffer 11 WORD_16B Register"]
184 pub MB11_16B_WORD2: crate::RWRegister<u32>,
185 #[doc = "Message Buffer 11 WORD_16B Register"]
186 pub MB11_16B_WORD3: crate::RWRegister<u32>,
187 #[doc = "Message Buffer 18 CS Register"]
188 pub CS18: crate::RWRegister<u32>,
189 #[doc = "Message Buffer 18 ID Register"]
190 pub ID18: crate::RWRegister<u32>,
191 #[doc = "Message Buffer 12 WORD_16B Register"]
192 pub MB12_16B_WORD0: crate::RWRegister<u32>,
193 #[doc = "Message Buffer 12 WORD_16B Register"]
194 pub MB12_16B_WORD1: crate::RWRegister<u32>,
195 #[doc = "Message Buffer 19 CS Register"]
196 pub CS19: crate::RWRegister<u32>,
197 #[doc = "Message Buffer 19 ID Register"]
198 pub ID19: crate::RWRegister<u32>,
199 #[doc = "Message Buffer 13 CS Register"]
200 pub MB13_16B_CS: crate::RWRegister<u32>,
201 #[doc = "Message Buffer 13 ID Register"]
202 pub MB13_16B_ID: crate::RWRegister<u32>,
203 #[doc = "Message Buffer 20 CS Register"]
204 pub CS20: crate::RWRegister<u32>,
205 #[doc = "Message Buffer 20 ID Register"]
206 pub ID20: crate::RWRegister<u32>,
207 #[doc = "Message Buffer 13 WORD_16B Register"]
208 pub MB13_16B_WORD2: crate::RWRegister<u32>,
209 #[doc = "Message Buffer 13 WORD_16B Register"]
210 pub MB13_16B_WORD3: crate::RWRegister<u32>,
211 #[doc = "Message Buffer 21 CS Register"]
212 pub CS21: crate::RWRegister<u32>,
213 #[doc = "Message Buffer 21 ID Register"]
214 pub ID21: crate::RWRegister<u32>,
215 #[doc = "Message Buffer 14 WORD_16B Register"]
216 pub MB14_16B_WORD0: crate::RWRegister<u32>,
217 #[doc = "Message Buffer 14 WORD_16B Register"]
218 pub MB14_16B_WORD1: crate::RWRegister<u32>,
219 #[doc = "Message Buffer 22 CS Register"]
220 pub CS22: crate::RWRegister<u32>,
221 #[doc = "Message Buffer 22 ID Register"]
222 pub ID22: crate::RWRegister<u32>,
223 #[doc = "Message Buffer 15 CS Register"]
224 pub MB15_16B_CS: crate::RWRegister<u32>,
225 #[doc = "Message Buffer 15 ID Register"]
226 pub MB15_16B_ID: crate::RWRegister<u32>,
227 #[doc = "Message Buffer 23 CS Register"]
228 pub CS23: crate::RWRegister<u32>,
229 #[doc = "Message Buffer 23 ID Register"]
230 pub ID23: crate::RWRegister<u32>,
231 #[doc = "Message Buffer 15 WORD_16B Register"]
232 pub MB15_16B_WORD2: crate::RWRegister<u32>,
233 #[doc = "Message Buffer 15 WORD_16B Register"]
234 pub MB15_16B_WORD3: crate::RWRegister<u32>,
235 #[doc = "Message Buffer 24 CS Register"]
236 pub CS24: crate::RWRegister<u32>,
237 #[doc = "Message Buffer 24 ID Register"]
238 pub ID24: crate::RWRegister<u32>,
239 #[doc = "Message Buffer 16 WORD_16B Register"]
240 pub MB16_16B_WORD0: crate::RWRegister<u32>,
241 #[doc = "Message Buffer 16 WORD_16B Register"]
242 pub MB16_16B_WORD1: crate::RWRegister<u32>,
243 #[doc = "Message Buffer 25 CS Register"]
244 pub CS25: crate::RWRegister<u32>,
245 #[doc = "Message Buffer 25 ID Register"]
246 pub ID25: crate::RWRegister<u32>,
247 #[doc = "Message Buffer 10 WORD_32B Register"]
248 pub MB10_32B_WORD0: crate::RWRegister<u32>,
249 #[doc = "Message Buffer 10 WORD_32B Register"]
250 pub MB10_32B_WORD1: crate::RWRegister<u32>,
251 #[doc = "Message Buffer 26 CS Register"]
252 pub CS26: crate::RWRegister<u32>,
253 #[doc = "Message Buffer 26 ID Register"]
254 pub ID26: crate::RWRegister<u32>,
255 #[doc = "Message Buffer 10 WORD_32B Register"]
256 pub MB10_32B_WORD4: crate::RWRegister<u32>,
257 #[doc = "Message Buffer 10 WORD_32B Register"]
258 pub MB10_32B_WORD5: crate::RWRegister<u32>,
259 #[doc = "Message Buffer 27 CS Register"]
260 pub CS27: crate::RWRegister<u32>,
261 #[doc = "Message Buffer 27 ID Register"]
262 pub ID27: crate::RWRegister<u32>,
263 #[doc = "Message Buffer 11 CS Register"]
264 pub MB11_32B_CS: crate::RWRegister<u32>,
265 #[doc = "Message Buffer 11 ID Register"]
266 pub MB11_32B_ID: crate::RWRegister<u32>,
267 #[doc = "Message Buffer 28 CS Register"]
268 pub CS28: crate::RWRegister<u32>,
269 #[doc = "Message Buffer 28 ID Register"]
270 pub ID28: crate::RWRegister<u32>,
271 #[doc = "Message Buffer 11 WORD_32B Register"]
272 pub MB11_32B_WORD2: crate::RWRegister<u32>,
273 #[doc = "Message Buffer 11 WORD_32B Register"]
274 pub MB11_32B_WORD3: crate::RWRegister<u32>,
275 #[doc = "Message Buffer 29 CS Register"]
276 pub CS29: crate::RWRegister<u32>,
277 #[doc = "Message Buffer 29 ID Register"]
278 pub ID29: crate::RWRegister<u32>,
279 #[doc = "Message Buffer 11 WORD_32B Register"]
280 pub MB11_32B_WORD6: crate::RWRegister<u32>,
281 #[doc = "Message Buffer 11 WORD_32B Register"]
282 pub MB11_32B_WORD7: crate::RWRegister<u32>,
283 #[doc = "Message Buffer 30 CS Register"]
284 pub CS30: crate::RWRegister<u32>,
285 #[doc = "Message Buffer 30 ID Register"]
286 pub ID30: crate::RWRegister<u32>,
287 #[doc = "Message Buffer 12 WORD_32B Register"]
288 pub MB12_32B_WORD0: crate::RWRegister<u32>,
289 #[doc = "Message Buffer 12 WORD_32B Register"]
290 pub MB12_32B_WORD1: crate::RWRegister<u32>,
291 #[doc = "Message Buffer 31 CS Register"]
292 pub CS31: crate::RWRegister<u32>,
293 #[doc = "Message Buffer 31 ID Register"]
294 pub ID31: crate::RWRegister<u32>,
295 #[doc = "Message Buffer 12 WORD_32B Register"]
296 pub MB12_32B_WORD4: crate::RWRegister<u32>,
297 #[doc = "Message Buffer 12 WORD_32B Register"]
298 pub MB12_32B_WORD5: crate::RWRegister<u32>,
299 #[doc = "Message Buffer 32 CS Register"]
300 pub CS32: crate::RWRegister<u32>,
301 #[doc = "Message Buffer 32 ID Register"]
302 pub ID32: crate::RWRegister<u32>,
303 #[doc = "Message Buffer 13 CS Register"]
304 pub MB13_32B_CS: crate::RWRegister<u32>,
305 #[doc = "Message Buffer 13 ID Register"]
306 pub MB13_32B_ID: crate::RWRegister<u32>,
307 #[doc = "Message Buffer 33 CS Register"]
308 pub CS33: crate::RWRegister<u32>,
309 #[doc = "Message Buffer 33 ID Register"]
310 pub ID33: crate::RWRegister<u32>,
311 #[doc = "Message Buffer 13 WORD_32B Register"]
312 pub MB13_32B_WORD2: crate::RWRegister<u32>,
313 #[doc = "Message Buffer 13 WORD_32B Register"]
314 pub MB13_32B_WORD3: crate::RWRegister<u32>,
315 #[doc = "Message Buffer 34 CS Register"]
316 pub CS34: crate::RWRegister<u32>,
317 #[doc = "Message Buffer 34 ID Register"]
318 pub ID34: crate::RWRegister<u32>,
319 #[doc = "Message Buffer 13 WORD_32B Register"]
320 pub MB13_32B_WORD6: crate::RWRegister<u32>,
321 #[doc = "Message Buffer 13 WORD_32B Register"]
322 pub MB13_32B_WORD7: crate::RWRegister<u32>,
323 #[doc = "Message Buffer 35 CS Register"]
324 pub CS35: crate::RWRegister<u32>,
325 #[doc = "Message Buffer 35 ID Register"]
326 pub ID35: crate::RWRegister<u32>,
327 #[doc = "Message Buffer 14 WORD_32B Register"]
328 pub MB14_32B_WORD0: crate::RWRegister<u32>,
329 #[doc = "Message Buffer 14 WORD_32B Register"]
330 pub MB14_32B_WORD1: crate::RWRegister<u32>,
331 #[doc = "Message Buffer 36 CS Register"]
332 pub CS36: crate::RWRegister<u32>,
333 #[doc = "Message Buffer 36 ID Register"]
334 pub ID36: crate::RWRegister<u32>,
335 #[doc = "Message Buffer 14 WORD_32B Register"]
336 pub MB14_32B_WORD4: crate::RWRegister<u32>,
337 #[doc = "Message Buffer 14 WORD_32B Register"]
338 pub MB14_32B_WORD5: crate::RWRegister<u32>,
339 #[doc = "Message Buffer 37 CS Register"]
340 pub CS37: crate::RWRegister<u32>,
341 #[doc = "Message Buffer 37 ID Register"]
342 pub ID37: crate::RWRegister<u32>,
343 #[doc = "Message Buffer 15 CS Register"]
344 pub MB15_32B_CS: crate::RWRegister<u32>,
345 #[doc = "Message Buffer 15 ID Register"]
346 pub MB15_32B_ID: crate::RWRegister<u32>,
347 #[doc = "Message Buffer 38 CS Register"]
348 pub CS38: crate::RWRegister<u32>,
349 #[doc = "Message Buffer 38 ID Register"]
350 pub ID38: crate::RWRegister<u32>,
351 #[doc = "Message Buffer 15 WORD_32B Register"]
352 pub MB15_32B_WORD2: crate::RWRegister<u32>,
353 #[doc = "Message Buffer 15 WORD_32B Register"]
354 pub MB15_32B_WORD3: crate::RWRegister<u32>,
355 #[doc = "Message Buffer 39 CS Register"]
356 pub CS39: crate::RWRegister<u32>,
357 #[doc = "Message Buffer 39 ID Register"]
358 pub ID39: crate::RWRegister<u32>,
359 #[doc = "Message Buffer 15 WORD_32B Register"]
360 pub MB15_32B_WORD6: crate::RWRegister<u32>,
361 #[doc = "Message Buffer 15 WORD_32B Register"]
362 pub MB15_32B_WORD7: crate::RWRegister<u32>,
363 #[doc = "Message Buffer 40 CS Register"]
364 pub CS40: crate::RWRegister<u32>,
365 #[doc = "Message Buffer 40 ID Register"]
366 pub ID40: crate::RWRegister<u32>,
367 #[doc = "Message Buffer 16 WORD_32B Register"]
368 pub MB16_32B_WORD0: crate::RWRegister<u32>,
369 #[doc = "Message Buffer 16 WORD_32B Register"]
370 pub MB16_32B_WORD1: crate::RWRegister<u32>,
371 #[doc = "Message Buffer 41 CS Register"]
372 pub CS41: crate::RWRegister<u32>,
373 #[doc = "Message Buffer 41 ID Register"]
374 pub ID41: crate::RWRegister<u32>,
375 #[doc = "Message Buffer 16 WORD_32B Register"]
376 pub MB16_32B_WORD4: crate::RWRegister<u32>,
377 #[doc = "Message Buffer 16 WORD_32B Register"]
378 pub MB16_32B_WORD5: crate::RWRegister<u32>,
379 #[doc = "Message Buffer 42 CS Register"]
380 pub CS42: crate::RWRegister<u32>,
381 #[doc = "Message Buffer 42 ID Register"]
382 pub ID42: crate::RWRegister<u32>,
383 #[doc = "Message Buffer 17 CS Register"]
384 pub MB17_32B_CS: crate::RWRegister<u32>,
385 #[doc = "Message Buffer 17 ID Register"]
386 pub MB17_32B_ID: crate::RWRegister<u32>,
387 #[doc = "Message Buffer 43 CS Register"]
388 pub CS43: crate::RWRegister<u32>,
389 #[doc = "Message Buffer 43 ID Register"]
390 pub ID43: crate::RWRegister<u32>,
391 #[doc = "Message Buffer 17 WORD_32B Register"]
392 pub MB17_32B_WORD2: crate::RWRegister<u32>,
393 #[doc = "Message Buffer 17 WORD_32B Register"]
394 pub MB17_32B_WORD3: crate::RWRegister<u32>,
395 #[doc = "Message Buffer 44 CS Register"]
396 pub CS44: crate::RWRegister<u32>,
397 #[doc = "Message Buffer 44 ID Register"]
398 pub ID44: crate::RWRegister<u32>,
399 #[doc = "Message Buffer 17 WORD_32B Register"]
400 pub MB17_32B_WORD6: crate::RWRegister<u32>,
401 #[doc = "Message Buffer 17 WORD_32B Register"]
402 pub MB17_32B_WORD7: crate::RWRegister<u32>,
403 #[doc = "Message Buffer 45 CS Register"]
404 pub CS45: crate::RWRegister<u32>,
405 #[doc = "Message Buffer 45 ID Register"]
406 pub ID45: crate::RWRegister<u32>,
407 #[doc = "Message Buffer 10 WORD_64B Register"]
408 pub MB10_64B_WORD0: crate::RWRegister<u32>,
409 #[doc = "Message Buffer 10 WORD_64B Register"]
410 pub MB10_64B_WORD1: crate::RWRegister<u32>,
411 #[doc = "Message Buffer 46 CS Register"]
412 pub CS46: crate::RWRegister<u32>,
413 #[doc = "Message Buffer 46 ID Register"]
414 pub ID46: crate::RWRegister<u32>,
415 #[doc = "Message Buffer 10 WORD_64B Register"]
416 pub MB10_64B_WORD4: crate::RWRegister<u32>,
417 #[doc = "Message Buffer 10 WORD_64B Register"]
418 pub MB10_64B_WORD5: crate::RWRegister<u32>,
419 #[doc = "Message Buffer 47 CS Register"]
420 pub CS47: crate::RWRegister<u32>,
421 #[doc = "Message Buffer 47 ID Register"]
422 pub ID47: crate::RWRegister<u32>,
423 #[doc = "Message Buffer 10 WORD_64B Register"]
424 pub MB10_64B_WORD8: crate::RWRegister<u32>,
425 #[doc = "Message Buffer 10 WORD_64B Register"]
426 pub MB10_64B_WORD9: crate::RWRegister<u32>,
427 #[doc = "Message Buffer 48 CS Register"]
428 pub CS48: crate::RWRegister<u32>,
429 #[doc = "Message Buffer 48 ID Register"]
430 pub ID48: crate::RWRegister<u32>,
431 #[doc = "Message Buffer 10 WORD_64B Register"]
432 pub MB10_64B_WORD12: crate::RWRegister<u32>,
433 #[doc = "Message Buffer 10 WORD_64B Register"]
434 pub MB10_64B_WORD13: crate::RWRegister<u32>,
435 #[doc = "Message Buffer 49 CS Register"]
436 pub CS49: crate::RWRegister<u32>,
437 #[doc = "Message Buffer 49 ID Register"]
438 pub ID49: crate::RWRegister<u32>,
439 #[doc = "Message Buffer 11 CS Register"]
440 pub MB11_64B_CS: crate::RWRegister<u32>,
441 #[doc = "Message Buffer 11 ID Register"]
442 pub MB11_64B_ID: crate::RWRegister<u32>,
443 #[doc = "Message Buffer 50 CS Register"]
444 pub CS50: crate::RWRegister<u32>,
445 #[doc = "Message Buffer 50 ID Register"]
446 pub ID50: crate::RWRegister<u32>,
447 #[doc = "Message Buffer 11 WORD_64B Register"]
448 pub MB11_64B_WORD2: crate::RWRegister<u32>,
449 #[doc = "Message Buffer 11 WORD_64B Register"]
450 pub MB11_64B_WORD3: crate::RWRegister<u32>,
451 #[doc = "Message Buffer 51 CS Register"]
452 pub CS51: crate::RWRegister<u32>,
453 #[doc = "Message Buffer 51 ID Register"]
454 pub ID51: crate::RWRegister<u32>,
455 #[doc = "Message Buffer 11 WORD_64B Register"]
456 pub MB11_64B_WORD6: crate::RWRegister<u32>,
457 #[doc = "Message Buffer 11 WORD_64B Register"]
458 pub MB11_64B_WORD7: crate::RWRegister<u32>,
459 #[doc = "Message Buffer 52 CS Register"]
460 pub CS52: crate::RWRegister<u32>,
461 #[doc = "Message Buffer 52 ID Register"]
462 pub ID52: crate::RWRegister<u32>,
463 #[doc = "Message Buffer 11 WORD_64B Register"]
464 pub MB11_64B_WORD10: crate::RWRegister<u32>,
465 #[doc = "Message Buffer 11 WORD_64B Register"]
466 pub MB11_64B_WORD11: crate::RWRegister<u32>,
467 #[doc = "Message Buffer 53 CS Register"]
468 pub CS53: crate::RWRegister<u32>,
469 #[doc = "Message Buffer 53 ID Register"]
470 pub ID53: crate::RWRegister<u32>,
471 #[doc = "Message Buffer 11 WORD_64B Register"]
472 pub MB11_64B_WORD14: crate::RWRegister<u32>,
473 #[doc = "Message Buffer 11 WORD_64B Register"]
474 pub MB11_64B_WORD15: crate::RWRegister<u32>,
475 #[doc = "Message Buffer 54 CS Register"]
476 pub CS54: crate::RWRegister<u32>,
477 #[doc = "Message Buffer 54 ID Register"]
478 pub ID54: crate::RWRegister<u32>,
479 #[doc = "Message Buffer 12 WORD_64B Register"]
480 pub MB12_64B_WORD0: crate::RWRegister<u32>,
481 #[doc = "Message Buffer 12 WORD_64B Register"]
482 pub MB12_64B_WORD1: crate::RWRegister<u32>,
483 #[doc = "Message Buffer 55 CS Register"]
484 pub CS55: crate::RWRegister<u32>,
485 #[doc = "Message Buffer 55 ID Register"]
486 pub ID55: crate::RWRegister<u32>,
487 #[doc = "Message Buffer 12 WORD_64B Register"]
488 pub MB12_64B_WORD4: crate::RWRegister<u32>,
489 #[doc = "Message Buffer 12 WORD_64B Register"]
490 pub MB12_64B_WORD5: crate::RWRegister<u32>,
491 #[doc = "Message Buffer 56 CS Register"]
492 pub CS56: crate::RWRegister<u32>,
493 #[doc = "Message Buffer 56 ID Register"]
494 pub ID56: crate::RWRegister<u32>,
495 #[doc = "Message Buffer 12 WORD_64B Register"]
496 pub MB12_64B_WORD8: crate::RWRegister<u32>,
497 #[doc = "Message Buffer 12 WORD_64B Register"]
498 pub MB12_64B_WORD9: crate::RWRegister<u32>,
499 #[doc = "Message Buffer 57 CS Register"]
500 pub CS57: crate::RWRegister<u32>,
501 #[doc = "Message Buffer 57 ID Register"]
502 pub ID57: crate::RWRegister<u32>,
503 #[doc = "Message Buffer 12 WORD_64B Register"]
504 pub MB12_64B_WORD12: crate::RWRegister<u32>,
505 #[doc = "Message Buffer 12 WORD_64B Register"]
506 pub MB12_64B_WORD13: crate::RWRegister<u32>,
507 #[doc = "Message Buffer 58 CS Register"]
508 pub CS58: crate::RWRegister<u32>,
509 #[doc = "Message Buffer 58 ID Register"]
510 pub ID58: crate::RWRegister<u32>,
511 #[doc = "Message Buffer 13 CS Register"]
512 pub MB13_64B_CS: crate::RWRegister<u32>,
513 #[doc = "Message Buffer 13 ID Register"]
514 pub MB13_64B_ID: crate::RWRegister<u32>,
515 #[doc = "Message Buffer 59 CS Register"]
516 pub CS59: crate::RWRegister<u32>,
517 #[doc = "Message Buffer 59 ID Register"]
518 pub ID59: crate::RWRegister<u32>,
519 #[doc = "Message Buffer 13 WORD_64B Register"]
520 pub MB13_64B_WORD2: crate::RWRegister<u32>,
521 #[doc = "Message Buffer 13 WORD_64B Register"]
522 pub MB13_64B_WORD3: crate::RWRegister<u32>,
523 #[doc = "Message Buffer 60 CS Register"]
524 pub CS60: crate::RWRegister<u32>,
525 #[doc = "Message Buffer 60 ID Register"]
526 pub ID60: crate::RWRegister<u32>,
527 #[doc = "Message Buffer 13 WORD_64B Register"]
528 pub MB13_64B_WORD6: crate::RWRegister<u32>,
529 #[doc = "Message Buffer 13 WORD_64B Register"]
530 pub MB13_64B_WORD7: crate::RWRegister<u32>,
531 #[doc = "Message Buffer 61 CS Register"]
532 pub CS61: crate::RWRegister<u32>,
533 #[doc = "Message Buffer 61 ID Register"]
534 pub ID61: crate::RWRegister<u32>,
535 #[doc = "Message Buffer 13 WORD_64B Register"]
536 pub MB13_64B_WORD10: crate::RWRegister<u32>,
537 #[doc = "Message Buffer 13 WORD_64B Register"]
538 pub MB13_64B_WORD11: crate::RWRegister<u32>,
539 #[doc = "Message Buffer 62 CS Register"]
540 pub CS62: crate::RWRegister<u32>,
541 #[doc = "Message Buffer 62 ID Register"]
542 pub ID62: crate::RWRegister<u32>,
543 #[doc = "Message Buffer 13 WORD_64B Register"]
544 pub MB13_64B_WORD14: crate::RWRegister<u32>,
545 #[doc = "Message Buffer 13 WORD_64B Register"]
546 pub MB13_64B_WORD15: crate::RWRegister<u32>,
547 #[doc = "Message Buffer 63 CS Register"]
548 pub CS63: crate::RWRegister<u32>,
549 #[doc = "Message Buffer 63 ID Register"]
550 pub ID63: crate::RWRegister<u32>,
551 #[doc = "Message Buffer 63 WORD_8B Register"]
552 pub MB63_8B_WORD0: crate::RWRegister<u32>,
553 #[doc = "Message Buffer 63 WORD_8B Register"]
554 pub MB63_8B_WORD1: crate::RWRegister<u32>,
555 _reserved3: [u8; 0x0400],
556 #[doc = "Rx Individual Mask Registers"]
557 pub RXIMR: [crate::RWRegister<u32>; 64usize],
558 _reserved4: [u8; 0x0270],
559 #[doc = "Enhanced CAN Bit Timing Prescalers"]
560 pub EPRS: crate::RWRegister<u32>,
561 #[doc = "Enhanced Nominal CAN Bit Timing"]
562 pub ENCBT: crate::RWRegister<u32>,
563 #[doc = "Enhanced Data Phase CAN bit Timing"]
564 pub EDCBT: crate::RWRegister<u32>,
565 #[doc = "Enhanced Transceiver Delay Compensation"]
566 pub ETDC: crate::RWRegister<u32>,
567 #[doc = "CAN FD Control Register"]
568 pub FDCTRL: crate::RWRegister<u32>,
569 #[doc = "CAN FD Bit Timing Register"]
570 pub FDCBT: crate::RWRegister<u32>,
571 #[doc = "CAN FD CRC Register"]
572 pub FDCRC: crate::RORegister<u32>,
573 #[doc = "Enhanced Rx FIFO Control Register"]
574 pub ERFCR: crate::RWRegister<u32>,
575 #[doc = "Enhanced Rx FIFO Interrupt Enable register"]
576 pub ERFIER: crate::RWRegister<u32>,
577 #[doc = "Enhanced Rx FIFO Status Register"]
578 pub ERFSR: crate::RWRegister<u32>,
579 _reserved5: [u8; 0x18],
580 #[doc = "High Resolution Time Stamp"]
581 pub HR_TIME_STAMP: [crate::RORegister<u32>; 64usize],
582 _reserved6: [u8; 0x22d0],
583 #[doc = "Enhanced Rx FIFO Filter Element"]
584 pub ERFFEL: [crate::RWRegister<u32>; 128usize],
585}
586#[doc = "Module Configuration Register"]
587pub mod MCR {
588 #[doc = "Number Of The Last Message Buffer"]
589 pub mod MAXMB {
590 pub const offset: u32 = 0;
591 pub const mask: u32 = 0x7f << offset;
592 pub mod R {}
593 pub mod W {}
594 pub mod RW {}
595 }
596 #[doc = "ID Acceptance Mode"]
597 pub mod IDAM {
598 pub const offset: u32 = 8;
599 pub const mask: u32 = 0x03 << offset;
600 pub mod R {}
601 pub mod W {}
602 pub mod RW {
603 #[doc = "Format A: One full ID (standard and extended) per ID Filter Table element."]
604 pub const IDAM_0: u32 = 0;
605 #[doc = "Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element."]
606 pub const IDAM_1: u32 = 0x01;
607 #[doc = "Format C: Four partial 8-bit Standard IDs per ID Filter Table element."]
608 pub const IDAM_2: u32 = 0x02;
609 #[doc = "Format D: All frames rejected."]
610 pub const IDAM_3: u32 = 0x03;
611 }
612 }
613 #[doc = "CAN FD operation enable"]
614 pub mod FDEN {
615 pub const offset: u32 = 11;
616 pub const mask: u32 = 0x01 << offset;
617 pub mod R {}
618 pub mod W {}
619 pub mod RW {
620 #[doc = "CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format."]
621 pub const FDEN_0: u32 = 0;
622 #[doc = "CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats."]
623 pub const FDEN_1: u32 = 0x01;
624 }
625 }
626 #[doc = "Abort Enable"]
627 pub mod AEN {
628 pub const offset: u32 = 12;
629 pub const mask: u32 = 0x01 << offset;
630 pub mod R {}
631 pub mod W {}
632 pub mod RW {
633 #[doc = "Abort disabled."]
634 pub const AEN_0: u32 = 0;
635 #[doc = "Abort enabled."]
636 pub const AEN_1: u32 = 0x01;
637 }
638 }
639 #[doc = "Local Priority Enable"]
640 pub mod LPRIOEN {
641 pub const offset: u32 = 13;
642 pub const mask: u32 = 0x01 << offset;
643 pub mod R {}
644 pub mod W {}
645 pub mod RW {
646 #[doc = "Local Priority disabled."]
647 pub const LPRIOEN_0: u32 = 0;
648 #[doc = "Local Priority enabled."]
649 pub const LPRIOEN_1: u32 = 0x01;
650 }
651 }
652 #[doc = "DMA Enable"]
653 pub mod DMA {
654 pub const offset: u32 = 15;
655 pub const mask: u32 = 0x01 << offset;
656 pub mod R {}
657 pub mod W {}
658 pub mod RW {
659 #[doc = "DMA feature for Legacy RX FIFO or Enhanced Rx FIFO are disabled."]
660 pub const DMA_0: u32 = 0;
661 #[doc = "DMA feature for Legacy RX FIFO or Enhanced Rx FIFO are enabled."]
662 pub const DMA_1: u32 = 0x01;
663 }
664 }
665 #[doc = "Individual Rx Masking And Queue Enable"]
666 pub mod IRMQ {
667 pub const offset: u32 = 16;
668 pub const mask: u32 = 0x01 << offset;
669 pub mod R {}
670 pub mod W {}
671 pub mod RW {
672 #[doc = "Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY."]
673 pub const IRMQ_0: u32 = 0;
674 #[doc = "Individual Rx masking and queue feature are enabled."]
675 pub const IRMQ_1: u32 = 0x01;
676 }
677 }
678 #[doc = "Self Reception Disable"]
679 pub mod SRXDIS {
680 pub const offset: u32 = 17;
681 pub const mask: u32 = 0x01 << offset;
682 pub mod R {}
683 pub mod W {}
684 pub mod RW {
685 #[doc = "Self reception enabled."]
686 pub const SRXDIS_0: u32 = 0;
687 #[doc = "Self reception disabled."]
688 pub const SRXDIS_1: u32 = 0x01;
689 }
690 }
691 #[doc = "Doze Mode Enable"]
692 pub mod DOZE {
693 pub const offset: u32 = 18;
694 pub const mask: u32 = 0x01 << offset;
695 pub mod R {}
696 pub mod W {}
697 pub mod RW {
698 #[doc = "FlexCAN is not enabled to enter low-power mode when Doze mode is requested."]
699 pub const DOZE_0: u32 = 0;
700 #[doc = "FlexCAN is enabled to enter low-power mode when Doze mode is requested."]
701 pub const DOZE_1: u32 = 0x01;
702 }
703 }
704 #[doc = "Wake Up Source"]
705 pub mod WAKSRC {
706 pub const offset: u32 = 19;
707 pub const mask: u32 = 0x01 << offset;
708 pub mod R {}
709 pub mod W {}
710 pub mod RW {
711 #[doc = "FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus."]
712 pub const WAKSRC_0: u32 = 0;
713 #[doc = "FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus."]
714 pub const WAKSRC_1: u32 = 0x01;
715 }
716 }
717 #[doc = "Low-Power Mode Acknowledge"]
718 pub mod LPMACK {
719 pub const offset: u32 = 20;
720 pub const mask: u32 = 0x01 << offset;
721 pub mod R {}
722 pub mod W {}
723 pub mod RW {
724 #[doc = "FlexCAN is not in a low-power mode."]
725 pub const LPMACK_0: u32 = 0;
726 #[doc = "FlexCAN is in a low-power mode."]
727 pub const LPMACK_1: u32 = 0x01;
728 }
729 }
730 #[doc = "Warning Interrupt Enable"]
731 pub mod WRNEN {
732 pub const offset: u32 = 21;
733 pub const mask: u32 = 0x01 << offset;
734 pub mod R {}
735 pub mod W {}
736 pub mod RW {
737 #[doc = "TWRNINT and RWRNINT bits are zero, independent of the values in the error counters."]
738 pub const WRNEN_0: u32 = 0;
739 #[doc = "TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96."]
740 pub const WRNEN_1: u32 = 0x01;
741 }
742 }
743 #[doc = "Self Wake Up"]
744 pub mod SLFWAK {
745 pub const offset: u32 = 22;
746 pub const mask: u32 = 0x01 << offset;
747 pub mod R {}
748 pub mod W {}
749 pub mod RW {
750 #[doc = "FlexCAN Self Wake Up feature is disabled."]
751 pub const SLFWAK_0: u32 = 0;
752 #[doc = "FlexCAN Self Wake Up feature is enabled."]
753 pub const SLFWAK_1: u32 = 0x01;
754 }
755 }
756 #[doc = "Supervisor Mode"]
757 pub mod SUPV {
758 pub const offset: u32 = 23;
759 pub const mask: u32 = 0x01 << offset;
760 pub mod R {}
761 pub mod W {}
762 pub mod RW {
763 #[doc = "FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses."]
764 pub const SUPV_0: u32 = 0;
765 #[doc = "FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location."]
766 pub const SUPV_1: u32 = 0x01;
767 }
768 }
769 #[doc = "Freeze Mode Acknowledge"]
770 pub mod FRZACK {
771 pub const offset: u32 = 24;
772 pub const mask: u32 = 0x01 << offset;
773 pub mod R {}
774 pub mod W {}
775 pub mod RW {
776 #[doc = "FlexCAN not in Freeze mode, prescaler running."]
777 pub const FRZACK_0: u32 = 0;
778 #[doc = "FlexCAN in Freeze mode, prescaler stopped."]
779 pub const FRZACK_1: u32 = 0x01;
780 }
781 }
782 #[doc = "Soft Reset"]
783 pub mod SOFTRST {
784 pub const offset: u32 = 25;
785 pub const mask: u32 = 0x01 << offset;
786 pub mod R {}
787 pub mod W {}
788 pub mod RW {
789 #[doc = "No reset request."]
790 pub const SOFTRST_0: u32 = 0;
791 #[doc = "Resets the registers affected by soft reset."]
792 pub const SOFTRST_1: u32 = 0x01;
793 }
794 }
795 #[doc = "Wake Up Interrupt Mask"]
796 pub mod WAKMSK {
797 pub const offset: u32 = 26;
798 pub const mask: u32 = 0x01 << offset;
799 pub mod R {}
800 pub mod W {}
801 pub mod RW {
802 #[doc = "Wake Up Interrupt is disabled."]
803 pub const WAKMSK_0: u32 = 0;
804 #[doc = "Wake Up Interrupt is enabled."]
805 pub const WAKMSK_1: u32 = 0x01;
806 }
807 }
808 #[doc = "FlexCAN Not Ready"]
809 pub mod NOTRDY {
810 pub const offset: u32 = 27;
811 pub const mask: u32 = 0x01 << offset;
812 pub mod R {}
813 pub mod W {}
814 pub mod RW {
815 #[doc = "FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode."]
816 pub const NOTRDY_0: u32 = 0;
817 #[doc = "FlexCAN module is either in Disable mode, Doze mode , Stop mode or Freeze mode."]
818 pub const NOTRDY_1: u32 = 0x01;
819 }
820 }
821 #[doc = "Halt FlexCAN"]
822 pub mod HALT {
823 pub const offset: u32 = 28;
824 pub const mask: u32 = 0x01 << offset;
825 pub mod R {}
826 pub mod W {}
827 pub mod RW {
828 #[doc = "No Freeze mode request."]
829 pub const HALT_0: u32 = 0;
830 #[doc = "Enters Freeze mode if the FRZ bit is asserted."]
831 pub const HALT_1: u32 = 0x01;
832 }
833 }
834 #[doc = "Legacy Rx FIFO Enable"]
835 pub mod RFEN {
836 pub const offset: u32 = 29;
837 pub const mask: u32 = 0x01 << offset;
838 pub mod R {}
839 pub mod W {}
840 pub mod RW {
841 #[doc = "Legacy Rx FIFO not enabled."]
842 pub const RFEN_0: u32 = 0;
843 #[doc = "Legacy Rx FIFO enabled."]
844 pub const RFEN_1: u32 = 0x01;
845 }
846 }
847 #[doc = "Freeze Enable"]
848 pub mod FRZ {
849 pub const offset: u32 = 30;
850 pub const mask: u32 = 0x01 << offset;
851 pub mod R {}
852 pub mod W {}
853 pub mod RW {
854 #[doc = "Not enabled to enter Freeze mode."]
855 pub const FRZ_0: u32 = 0;
856 #[doc = "Enabled to enter Freeze mode."]
857 pub const FRZ_1: u32 = 0x01;
858 }
859 }
860 #[doc = "Module Disable"]
861 pub mod MDIS {
862 pub const offset: u32 = 31;
863 pub const mask: u32 = 0x01 << offset;
864 pub mod R {}
865 pub mod W {}
866 pub mod RW {
867 #[doc = "Enable the FlexCAN module."]
868 pub const MDIS_0: u32 = 0;
869 #[doc = "Disable the FlexCAN module."]
870 pub const MDIS_1: u32 = 0x01;
871 }
872 }
873}
874#[doc = "Control 1 register"]
875pub mod CTRL1 {
876 #[doc = "Propagation Segment"]
877 pub mod PROPSEG {
878 pub const offset: u32 = 0;
879 pub const mask: u32 = 0x07 << offset;
880 pub mod R {}
881 pub mod W {}
882 pub mod RW {}
883 }
884 #[doc = "Listen-Only Mode"]
885 pub mod LOM {
886 pub const offset: u32 = 3;
887 pub const mask: u32 = 0x01 << offset;
888 pub mod R {}
889 pub mod W {}
890 pub mod RW {
891 #[doc = "Listen-Only mode is deactivated."]
892 pub const LOM_0: u32 = 0;
893 #[doc = "FlexCAN module operates in Listen-Only mode."]
894 pub const LOM_1: u32 = 0x01;
895 }
896 }
897 #[doc = "Lowest Buffer Transmitted First"]
898 pub mod LBUF {
899 pub const offset: u32 = 4;
900 pub const mask: u32 = 0x01 << offset;
901 pub mod R {}
902 pub mod W {}
903 pub mod RW {
904 #[doc = "Buffer with highest priority is transmitted first."]
905 pub const LBUF_0: u32 = 0;
906 #[doc = "Lowest number buffer is transmitted first."]
907 pub const LBUF_1: u32 = 0x01;
908 }
909 }
910 #[doc = "Timer Sync"]
911 pub mod TSYN {
912 pub const offset: u32 = 5;
913 pub const mask: u32 = 0x01 << offset;
914 pub mod R {}
915 pub mod W {}
916 pub mod RW {
917 #[doc = "Timer Sync feature disabled"]
918 pub const TSYN_0: u32 = 0;
919 #[doc = "Timer Sync feature enabled"]
920 pub const TSYN_1: u32 = 0x01;
921 }
922 }
923 #[doc = "Bus Off Recovery"]
924 pub mod BOFFREC {
925 pub const offset: u32 = 6;
926 pub const mask: u32 = 0x01 << offset;
927 pub mod R {}
928 pub mod W {}
929 pub mod RW {
930 #[doc = "Automatic recovering from Bus Off state enabled."]
931 pub const BOFFREC_0: u32 = 0;
932 #[doc = "Automatic recovering from Bus Off state disabled."]
933 pub const BOFFREC_1: u32 = 0x01;
934 }
935 }
936 #[doc = "CAN Bit Sampling"]
937 pub mod SMP {
938 pub const offset: u32 = 7;
939 pub const mask: u32 = 0x01 << offset;
940 pub mod R {}
941 pub mod W {}
942 pub mod RW {
943 #[doc = "Just one sample is used to determine the bit value."]
944 pub const SMP_0: u32 = 0;
945 #[doc = "Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used."]
946 pub const SMP_1: u32 = 0x01;
947 }
948 }
949 #[doc = "Rx Warning Interrupt Mask"]
950 pub mod RWRNMSK {
951 pub const offset: u32 = 10;
952 pub const mask: u32 = 0x01 << offset;
953 pub mod R {}
954 pub mod W {}
955 pub mod RW {
956 #[doc = "Rx Warning Interrupt disabled."]
957 pub const RWRNMSK_0: u32 = 0;
958 #[doc = "Rx Warning Interrupt enabled."]
959 pub const RWRNMSK_1: u32 = 0x01;
960 }
961 }
962 #[doc = "Tx Warning Interrupt Mask"]
963 pub mod TWRNMSK {
964 pub const offset: u32 = 11;
965 pub const mask: u32 = 0x01 << offset;
966 pub mod R {}
967 pub mod W {}
968 pub mod RW {
969 #[doc = "Tx Warning Interrupt disabled."]
970 pub const TWRNMSK_0: u32 = 0;
971 #[doc = "Tx Warning Interrupt enabled."]
972 pub const TWRNMSK_1: u32 = 0x01;
973 }
974 }
975 #[doc = "Loop Back Mode"]
976 pub mod LPB {
977 pub const offset: u32 = 12;
978 pub const mask: u32 = 0x01 << offset;
979 pub mod R {}
980 pub mod W {}
981 pub mod RW {
982 #[doc = "Loop Back disabled."]
983 pub const LPB_0: u32 = 0;
984 #[doc = "Loop Back enabled."]
985 pub const LPB_1: u32 = 0x01;
986 }
987 }
988 #[doc = "CAN Engine Clock Source"]
989 pub mod CLKSRC {
990 pub const offset: u32 = 13;
991 pub const mask: u32 = 0x01 << offset;
992 pub mod R {}
993 pub mod W {}
994 pub mod RW {
995 #[doc = "The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock."]
996 pub const CLKSRC_0: u32 = 0;
997 #[doc = "The CAN engine clock source is the peripheral clock."]
998 pub const CLKSRC_1: u32 = 0x01;
999 }
1000 }
1001 #[doc = "Error Interrupt Mask"]
1002 pub mod ERRMSK {
1003 pub const offset: u32 = 14;
1004 pub const mask: u32 = 0x01 << offset;
1005 pub mod R {}
1006 pub mod W {}
1007 pub mod RW {
1008 #[doc = "Error interrupt disabled."]
1009 pub const ERRMSK_0: u32 = 0;
1010 #[doc = "Error interrupt enabled."]
1011 pub const ERRMSK_1: u32 = 0x01;
1012 }
1013 }
1014 #[doc = "Bus Off Interrupt Mask"]
1015 pub mod BOFFMSK {
1016 pub const offset: u32 = 15;
1017 pub const mask: u32 = 0x01 << offset;
1018 pub mod R {}
1019 pub mod W {}
1020 pub mod RW {
1021 #[doc = "Bus Off interrupt disabled."]
1022 pub const BOFFMSK_0: u32 = 0;
1023 #[doc = "Bus Off interrupt enabled."]
1024 pub const BOFFMSK_1: u32 = 0x01;
1025 }
1026 }
1027 #[doc = "Phase Segment 2"]
1028 pub mod PSEG2 {
1029 pub const offset: u32 = 16;
1030 pub const mask: u32 = 0x07 << offset;
1031 pub mod R {}
1032 pub mod W {}
1033 pub mod RW {}
1034 }
1035 #[doc = "Phase Segment 1"]
1036 pub mod PSEG1 {
1037 pub const offset: u32 = 19;
1038 pub const mask: u32 = 0x07 << offset;
1039 pub mod R {}
1040 pub mod W {}
1041 pub mod RW {}
1042 }
1043 #[doc = "Resync Jump Width"]
1044 pub mod RJW {
1045 pub const offset: u32 = 22;
1046 pub const mask: u32 = 0x03 << offset;
1047 pub mod R {}
1048 pub mod W {}
1049 pub mod RW {}
1050 }
1051 #[doc = "Prescaler Division Factor"]
1052 pub mod PRESDIV {
1053 pub const offset: u32 = 24;
1054 pub const mask: u32 = 0xff << offset;
1055 pub mod R {}
1056 pub mod W {}
1057 pub mod RW {}
1058 }
1059}
1060#[doc = "Free Running Timer"]
1061pub mod TIMER {
1062 #[doc = "Timer Value"]
1063 pub mod TIMER {
1064 pub const offset: u32 = 0;
1065 pub const mask: u32 = 0xffff << offset;
1066 pub mod R {}
1067 pub mod W {}
1068 pub mod RW {}
1069 }
1070}
1071#[doc = "Rx Mailboxes Global Mask Register"]
1072pub mod RXMGMASK {
1073 #[doc = "Rx Mailboxes Global Mask Bits"]
1074 pub mod MG {
1075 pub const offset: u32 = 0;
1076 pub const mask: u32 = 0xffff_ffff << offset;
1077 pub mod R {}
1078 pub mod W {}
1079 pub mod RW {}
1080 }
1081}
1082#[doc = "Rx 14 Mask register"]
1083pub mod RX14MASK {
1084 #[doc = "Rx Buffer 14 Mask Bits"]
1085 pub mod RX14M {
1086 pub const offset: u32 = 0;
1087 pub const mask: u32 = 0xffff_ffff << offset;
1088 pub mod R {}
1089 pub mod W {}
1090 pub mod RW {}
1091 }
1092}
1093#[doc = "Rx 15 Mask register"]
1094pub mod RX15MASK {
1095 #[doc = "Rx Buffer 15 Mask Bits"]
1096 pub mod RX15M {
1097 pub const offset: u32 = 0;
1098 pub const mask: u32 = 0xffff_ffff << offset;
1099 pub mod R {}
1100 pub mod W {}
1101 pub mod RW {}
1102 }
1103}
1104#[doc = "Error Counter"]
1105pub mod ECR {
1106 #[doc = "Transmit Error Counter"]
1107 pub mod TXERRCNT {
1108 pub const offset: u32 = 0;
1109 pub const mask: u32 = 0xff << offset;
1110 pub mod R {}
1111 pub mod W {}
1112 pub mod RW {}
1113 }
1114 #[doc = "Receive Error Counter"]
1115 pub mod RXERRCNT {
1116 pub const offset: u32 = 8;
1117 pub const mask: u32 = 0xff << offset;
1118 pub mod R {}
1119 pub mod W {}
1120 pub mod RW {}
1121 }
1122 #[doc = "Transmit Error Counter for fast bits"]
1123 pub mod TXERRCNT_FAST {
1124 pub const offset: u32 = 16;
1125 pub const mask: u32 = 0xff << offset;
1126 pub mod R {}
1127 pub mod W {}
1128 pub mod RW {}
1129 }
1130 #[doc = "Receive Error Counter for fast bits"]
1131 pub mod RXERRCNT_FAST {
1132 pub const offset: u32 = 24;
1133 pub const mask: u32 = 0xff << offset;
1134 pub mod R {}
1135 pub mod W {}
1136 pub mod RW {}
1137 }
1138}
1139#[doc = "Error and Status 1 register"]
1140pub mod ESR1 {
1141 #[doc = "Wake-Up Interrupt"]
1142 pub mod WAKINT {
1143 pub const offset: u32 = 0;
1144 pub const mask: u32 = 0x01 << offset;
1145 pub mod R {}
1146 pub mod W {}
1147 pub mod RW {
1148 #[doc = "No such occurrence."]
1149 pub const WAKINT_0: u32 = 0;
1150 #[doc = "Indicates a recessive to dominant transition was received on the CAN bus."]
1151 pub const WAKINT_1: u32 = 0x01;
1152 }
1153 }
1154 #[doc = "Error Interrupt"]
1155 pub mod ERRINT {
1156 pub const offset: u32 = 1;
1157 pub const mask: u32 = 0x01 << offset;
1158 pub mod R {}
1159 pub mod W {}
1160 pub mod RW {
1161 #[doc = "No such occurrence."]
1162 pub const ERRINT_0: u32 = 0;
1163 #[doc = "Indicates setting of any Error Bit in the Error and Status Register."]
1164 pub const ERRINT_1: u32 = 0x01;
1165 }
1166 }
1167 #[doc = "Bus Off Interrupt"]
1168 pub mod BOFFINT {
1169 pub const offset: u32 = 2;
1170 pub const mask: u32 = 0x01 << offset;
1171 pub mod R {}
1172 pub mod W {}
1173 pub mod RW {
1174 #[doc = "No such occurrence."]
1175 pub const BOFFINT_0: u32 = 0;
1176 #[doc = "FlexCAN module entered Bus Off state."]
1177 pub const BOFFINT_1: u32 = 0x01;
1178 }
1179 }
1180 #[doc = "FlexCAN In Reception"]
1181 pub mod RX {
1182 pub const offset: u32 = 3;
1183 pub const mask: u32 = 0x01 << offset;
1184 pub mod R {}
1185 pub mod W {}
1186 pub mod RW {
1187 #[doc = "FlexCAN is not receiving a message."]
1188 pub const RX_0: u32 = 0;
1189 #[doc = "FlexCAN is receiving a message."]
1190 pub const RX_1: u32 = 0x01;
1191 }
1192 }
1193 #[doc = "Fault Confinement State"]
1194 pub mod FLTCONF {
1195 pub const offset: u32 = 4;
1196 pub const mask: u32 = 0x03 << offset;
1197 pub mod R {}
1198 pub mod W {}
1199 pub mod RW {
1200 #[doc = "Error Active"]
1201 pub const FLTCONF_0: u32 = 0;
1202 #[doc = "Error Passive"]
1203 pub const FLTCONF_1: u32 = 0x01;
1204 #[doc = "Bus Off"]
1205 pub const FLTCONF_2: u32 = 0x02;
1206 }
1207 }
1208 #[doc = "FlexCAN In Transmission"]
1209 pub mod TX {
1210 pub const offset: u32 = 6;
1211 pub const mask: u32 = 0x01 << offset;
1212 pub mod R {}
1213 pub mod W {}
1214 pub mod RW {
1215 #[doc = "FlexCAN is not transmitting a message."]
1216 pub const TX_0: u32 = 0;
1217 #[doc = "FlexCAN is transmitting a message."]
1218 pub const TX_1: u32 = 0x01;
1219 }
1220 }
1221 #[doc = "IDLE"]
1222 pub mod IDLE {
1223 pub const offset: u32 = 7;
1224 pub const mask: u32 = 0x01 << offset;
1225 pub mod R {}
1226 pub mod W {}
1227 pub mod RW {
1228 #[doc = "No such occurrence."]
1229 pub const IDLE_0: u32 = 0;
1230 #[doc = "CAN bus is now IDLE."]
1231 pub const IDLE_1: u32 = 0x01;
1232 }
1233 }
1234 #[doc = "Rx Error Warning"]
1235 pub mod RXWRN {
1236 pub const offset: u32 = 8;
1237 pub const mask: u32 = 0x01 << offset;
1238 pub mod R {}
1239 pub mod W {}
1240 pub mod RW {
1241 #[doc = "No such occurrence."]
1242 pub const RXWRN_0: u32 = 0;
1243 #[doc = "RXERRCNT is greater than or equal to 96."]
1244 pub const RXWRN_1: u32 = 0x01;
1245 }
1246 }
1247 #[doc = "TX Error Warning"]
1248 pub mod TXWRN {
1249 pub const offset: u32 = 9;
1250 pub const mask: u32 = 0x01 << offset;
1251 pub mod R {}
1252 pub mod W {}
1253 pub mod RW {
1254 #[doc = "No such occurrence."]
1255 pub const TXWRN_0: u32 = 0;
1256 #[doc = "TXERRCNT is greater than or equal to 96."]
1257 pub const TXWRN_1: u32 = 0x01;
1258 }
1259 }
1260 #[doc = "Stuffing Error"]
1261 pub mod STFERR {
1262 pub const offset: u32 = 10;
1263 pub const mask: u32 = 0x01 << offset;
1264 pub mod R {}
1265 pub mod W {}
1266 pub mod RW {
1267 #[doc = "No such occurrence."]
1268 pub const STFERR_0: u32 = 0;
1269 #[doc = "A Stuffing Error occurred since last read of this register."]
1270 pub const STFERR_1: u32 = 0x01;
1271 }
1272 }
1273 #[doc = "Form Error"]
1274 pub mod FRMERR {
1275 pub const offset: u32 = 11;
1276 pub const mask: u32 = 0x01 << offset;
1277 pub mod R {}
1278 pub mod W {}
1279 pub mod RW {
1280 #[doc = "No such occurrence."]
1281 pub const FRMERR_0: u32 = 0;
1282 #[doc = "A Form Error occurred since last read of this register."]
1283 pub const FRMERR_1: u32 = 0x01;
1284 }
1285 }
1286 #[doc = "Cyclic Redundancy Check Error"]
1287 pub mod CRCERR {
1288 pub const offset: u32 = 12;
1289 pub const mask: u32 = 0x01 << offset;
1290 pub mod R {}
1291 pub mod W {}
1292 pub mod RW {
1293 #[doc = "No such occurrence."]
1294 pub const CRCERR_0: u32 = 0;
1295 #[doc = "A CRC error occurred since last read of this register."]
1296 pub const CRCERR_1: u32 = 0x01;
1297 }
1298 }
1299 #[doc = "Acknowledge Error"]
1300 pub mod ACKERR {
1301 pub const offset: u32 = 13;
1302 pub const mask: u32 = 0x01 << offset;
1303 pub mod R {}
1304 pub mod W {}
1305 pub mod RW {
1306 #[doc = "No such occurrence."]
1307 pub const ACKERR_0: u32 = 0;
1308 #[doc = "An ACK error occurred since last read of this register."]
1309 pub const ACKERR_1: u32 = 0x01;
1310 }
1311 }
1312 #[doc = "Bit0 Error"]
1313 pub mod BIT0ERR {
1314 pub const offset: u32 = 14;
1315 pub const mask: u32 = 0x01 << offset;
1316 pub mod R {}
1317 pub mod W {}
1318 pub mod RW {
1319 #[doc = "No such occurrence."]
1320 pub const BIT0ERR_0: u32 = 0;
1321 #[doc = "At least one bit sent as dominant is received as recessive."]
1322 pub const BIT0ERR_1: u32 = 0x01;
1323 }
1324 }
1325 #[doc = "Bit1 Error"]
1326 pub mod BIT1ERR {
1327 pub const offset: u32 = 15;
1328 pub const mask: u32 = 0x01 << offset;
1329 pub mod R {}
1330 pub mod W {}
1331 pub mod RW {
1332 #[doc = "No such occurrence."]
1333 pub const BIT1ERR_0: u32 = 0;
1334 #[doc = "At least one bit sent as recessive is received as dominant."]
1335 pub const BIT1ERR_1: u32 = 0x01;
1336 }
1337 }
1338 #[doc = "Rx Warning Interrupt Flag"]
1339 pub mod RWRNINT {
1340 pub const offset: u32 = 16;
1341 pub const mask: u32 = 0x01 << offset;
1342 pub mod R {}
1343 pub mod W {}
1344 pub mod RW {
1345 #[doc = "No such occurrence."]
1346 pub const RWRNINT_0: u32 = 0;
1347 #[doc = "The Rx error counter transitioned from less than 96 to greater than or equal to 96."]
1348 pub const RWRNINT_1: u32 = 0x01;
1349 }
1350 }
1351 #[doc = "Tx Warning Interrupt Flag"]
1352 pub mod TWRNINT {
1353 pub const offset: u32 = 17;
1354 pub const mask: u32 = 0x01 << offset;
1355 pub mod R {}
1356 pub mod W {}
1357 pub mod RW {
1358 #[doc = "No such occurrence."]
1359 pub const TWRNINT_0: u32 = 0;
1360 #[doc = "The Tx error counter transitioned from less than 96 to greater than or equal to 96."]
1361 pub const TWRNINT_1: u32 = 0x01;
1362 }
1363 }
1364 #[doc = "CAN Synchronization Status"]
1365 pub mod SYNCH {
1366 pub const offset: u32 = 18;
1367 pub const mask: u32 = 0x01 << offset;
1368 pub mod R {}
1369 pub mod W {}
1370 pub mod RW {
1371 #[doc = "FlexCAN is not synchronized to the CAN bus."]
1372 pub const SYNCH_0: u32 = 0;
1373 #[doc = "FlexCAN is synchronized to the CAN bus."]
1374 pub const SYNCH_1: u32 = 0x01;
1375 }
1376 }
1377 #[doc = "Bus Off Done Interrupt"]
1378 pub mod BOFFDONEINT {
1379 pub const offset: u32 = 19;
1380 pub const mask: u32 = 0x01 << offset;
1381 pub mod R {}
1382 pub mod W {}
1383 pub mod RW {
1384 #[doc = "No such occurrence."]
1385 pub const BOFFDONEINT_0: u32 = 0;
1386 #[doc = "FlexCAN module has completed Bus Off process."]
1387 pub const BOFFDONEINT_1: u32 = 0x01;
1388 }
1389 }
1390 #[doc = "Error Interrupt for errors detected in the Data Phase of CAN FD frames with the BRS bit set"]
1391 pub mod ERRINT_FAST {
1392 pub const offset: u32 = 20;
1393 pub const mask: u32 = 0x01 << offset;
1394 pub mod R {}
1395 pub mod W {}
1396 pub mod RW {
1397 #[doc = "No such occurrence."]
1398 pub const ERRINT_FAST_0: u32 = 0;
1399 #[doc = "Indicates setting of any Error Bit detected in the Data Phase of CAN FD frames with the BRS bit set."]
1400 pub const ERRINT_FAST_1: u32 = 0x01;
1401 }
1402 }
1403 #[doc = "Error Overrun bit"]
1404 pub mod ERROVR {
1405 pub const offset: u32 = 21;
1406 pub const mask: u32 = 0x01 << offset;
1407 pub mod R {}
1408 pub mod W {}
1409 pub mod RW {
1410 #[doc = "Overrun has not occurred."]
1411 pub const ERROVR_0: u32 = 0;
1412 #[doc = "Overrun has occurred."]
1413 pub const ERROVR_1: u32 = 0x01;
1414 }
1415 }
1416 #[doc = "Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set"]
1417 pub mod STFERR_FAST {
1418 pub const offset: u32 = 26;
1419 pub const mask: u32 = 0x01 << offset;
1420 pub mod R {}
1421 pub mod W {}
1422 pub mod RW {
1423 #[doc = "No such occurrence."]
1424 pub const STFERR_FAST_0: u32 = 0;
1425 #[doc = "A Stuffing Error occurred since last read of this register."]
1426 pub const STFERR_FAST_1: u32 = 0x01;
1427 }
1428 }
1429 #[doc = "Form Error in the Data Phase of CAN FD frames with the BRS bit set"]
1430 pub mod FRMERR_FAST {
1431 pub const offset: u32 = 27;
1432 pub const mask: u32 = 0x01 << offset;
1433 pub mod R {}
1434 pub mod W {}
1435 pub mod RW {
1436 #[doc = "No such occurrence."]
1437 pub const FRMERR_FAST_0: u32 = 0;
1438 #[doc = "A Form Error occurred since last read of this register."]
1439 pub const FRMERR_FAST_1: u32 = 0x01;
1440 }
1441 }
1442 #[doc = "Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set"]
1443 pub mod CRCERR_FAST {
1444 pub const offset: u32 = 28;
1445 pub const mask: u32 = 0x01 << offset;
1446 pub mod R {}
1447 pub mod W {}
1448 pub mod RW {
1449 #[doc = "No such occurrence."]
1450 pub const CRCERR_FAST_0: u32 = 0;
1451 #[doc = "A CRC error occurred since last read of this register."]
1452 pub const CRCERR_FAST_1: u32 = 0x01;
1453 }
1454 }
1455 #[doc = "Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set"]
1456 pub mod BIT0ERR_FAST {
1457 pub const offset: u32 = 30;
1458 pub const mask: u32 = 0x01 << offset;
1459 pub mod R {}
1460 pub mod W {}
1461 pub mod RW {
1462 #[doc = "No such occurrence."]
1463 pub const BIT0ERR_FAST_0: u32 = 0;
1464 #[doc = "At least one bit sent as dominant is received as recessive."]
1465 pub const BIT0ERR_FAST_1: u32 = 0x01;
1466 }
1467 }
1468 #[doc = "Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set"]
1469 pub mod BIT1ERR_FAST {
1470 pub const offset: u32 = 31;
1471 pub const mask: u32 = 0x01 << offset;
1472 pub mod R {}
1473 pub mod W {}
1474 pub mod RW {
1475 #[doc = "No such occurrence."]
1476 pub const BIT1ERR_FAST_0: u32 = 0;
1477 #[doc = "At least one bit sent as recessive is received as dominant."]
1478 pub const BIT1ERR_FAST_1: u32 = 0x01;
1479 }
1480 }
1481}
1482#[doc = "Interrupt Masks 2 register"]
1483pub mod IMASK2 {
1484 #[doc = "Buffer MB i Mask"]
1485 pub mod BUF63TO32M {
1486 pub const offset: u32 = 0;
1487 pub const mask: u32 = 0xffff_ffff << offset;
1488 pub mod R {}
1489 pub mod W {}
1490 pub mod RW {}
1491 }
1492}
1493#[doc = "Interrupt Masks 1 register"]
1494pub mod IMASK1 {
1495 #[doc = "Buffer MB i Mask"]
1496 pub mod BUF31TO0M {
1497 pub const offset: u32 = 0;
1498 pub const mask: u32 = 0xffff_ffff << offset;
1499 pub mod R {}
1500 pub mod W {}
1501 pub mod RW {}
1502 }
1503}
1504#[doc = "Interrupt Flags 2 register"]
1505pub mod IFLAG2 {
1506 #[doc = "Buffer MB i Interrupt"]
1507 pub mod BUF63TO32I {
1508 pub const offset: u32 = 0;
1509 pub const mask: u32 = 0xffff_ffff << offset;
1510 pub mod R {}
1511 pub mod W {}
1512 pub mod RW {}
1513 }
1514}
1515#[doc = "Interrupt Flags 1 register"]
1516pub mod IFLAG1 {
1517 #[doc = "Buffer MB0 Interrupt Or Clear Legacy FIFO bit"]
1518 pub mod BUF0I {
1519 pub const offset: u32 = 0;
1520 pub const mask: u32 = 0x01 << offset;
1521 pub mod R {}
1522 pub mod W {}
1523 pub mod RW {
1524 #[doc = "The corresponding buffer has no occurrence of successfully completed transmission or reception when CAN_MCR\\[RFEN\\]=0."]
1525 pub const BUF0I_0: u32 = 0;
1526 #[doc = "The corresponding buffer has successfully completed transmission or reception when CAN_MCR\\[RFEN\\]=0."]
1527 pub const BUF0I_1: u32 = 0x01;
1528 }
1529 }
1530 #[doc = "Buffer MB i Interrupt Or \"reserved\""]
1531 pub mod BUF4TO1I {
1532 pub const offset: u32 = 1;
1533 pub const mask: u32 = 0x0f << offset;
1534 pub mod R {}
1535 pub mod W {}
1536 pub mod RW {}
1537 }
1538 #[doc = "Buffer MB5 Interrupt Or \"Frames available in Legacy Rx FIFO\""]
1539 pub mod BUF5I {
1540 pub const offset: u32 = 5;
1541 pub const mask: u32 = 0x01 << offset;
1542 pub mod R {}
1543 pub mod W {}
1544 pub mod RW {
1545 #[doc = "No occurrence of MB5 completing transmission/reception when CAN_MCR\\[RFEN\\]=0, or of frame(s) available in the Legacy FIFO, when CAN_MCR\\[RFEN\\]=1"]
1546 pub const BUF5I_0: u32 = 0;
1547 #[doc = "MB5 completed transmission/reception when CAN_MCR\\[RFEN\\]=0, or frame(s) available in the Legacy Rx FIFO when CAN_MCR\\[RFEN\\]=1. It generates a DMA request in case of CAN_MCR\\[RFEN\\] and CAN_MCR\\[DMA\\] are enabled."]
1548 pub const BUF5I_1: u32 = 0x01;
1549 }
1550 }
1551 #[doc = "Buffer MB6 Interrupt Or \"Legacy Rx FIFO Warning\""]
1552 pub mod BUF6I {
1553 pub const offset: u32 = 6;
1554 pub const mask: u32 = 0x01 << offset;
1555 pub mod R {}
1556 pub mod W {}
1557 pub mod RW {
1558 #[doc = "No occurrence of MB6 completing transmission/reception when CAN_MCR\\[RFEN\\]=0, or of Legacy Rx FIFO almost full when CAN_MCR\\[RFEN\\]=1"]
1559 pub const BUF6I_0: u32 = 0;
1560 #[doc = "MB6 completed transmission/reception when CAN_MCR\\[RFEN\\]=0, or Legacy Rx FIFO almost full when CAN_MCR\\[RFEN\\]=1"]
1561 pub const BUF6I_1: u32 = 0x01;
1562 }
1563 }
1564 #[doc = "Buffer MB7 Interrupt Or \"Legacy Rx FIFO Overflow\""]
1565 pub mod BUF7I {
1566 pub const offset: u32 = 7;
1567 pub const mask: u32 = 0x01 << offset;
1568 pub mod R {}
1569 pub mod W {}
1570 pub mod RW {
1571 #[doc = "No occurrence of MB7 completing transmission/reception when CAN_MCR\\[RFEN\\]=0, or of Legacy Rx FIFO overflow when CAN_MCR\\[RFEN\\]=1"]
1572 pub const BUF7I_0: u32 = 0;
1573 #[doc = "MB7 completed transmission/reception when CAN_MCR\\[RFEN\\]=0, or Legacy Rx FIFO overflow when CAN_MCR\\[RFEN\\]=1"]
1574 pub const BUF7I_1: u32 = 0x01;
1575 }
1576 }
1577 #[doc = "Buffer MBi Interrupt"]
1578 pub mod BUF31TO8I {
1579 pub const offset: u32 = 8;
1580 pub const mask: u32 = 0x00ff_ffff << offset;
1581 pub mod R {}
1582 pub mod W {}
1583 pub mod RW {}
1584 }
1585}
1586#[doc = "Control 2 register"]
1587pub mod CTRL2 {
1588 #[doc = "Time Stamp Capture Point"]
1589 pub mod TSTAMPCAP {
1590 pub const offset: u32 = 6;
1591 pub const mask: u32 = 0x03 << offset;
1592 pub mod R {}
1593 pub mod W {}
1594 pub mod RW {
1595 #[doc = "The high resolution time stamp capture is disabled"]
1596 pub const TSTAMPCAP_0: u32 = 0;
1597 #[doc = "The high resolution time stamp is captured in the end of the CAN frame"]
1598 pub const TSTAMPCAP_1: u32 = 0x01;
1599 #[doc = "The high resolution time stamp is captured in the start of the CAN frame"]
1600 pub const TSTAMPCAP_2: u32 = 0x02;
1601 #[doc = "The high resolution time stamp is captured in the start of frame for classical CAN frames and in res bit for CAN FD frames"]
1602 pub const TSTAMPCAP_3: u32 = 0x03;
1603 }
1604 }
1605 #[doc = "Message Buffer Time Stamp Base"]
1606 pub mod MBTSBASE {
1607 pub const offset: u32 = 8;
1608 pub const mask: u32 = 0x03 << offset;
1609 pub mod R {}
1610 pub mod W {}
1611 pub mod RW {
1612 #[doc = "Message Buffer Time Stamp base is CAN_TIMER"]
1613 pub const MBTSBASE_0: u32 = 0;
1614 #[doc = "Message Buffer Time Stamp base is lower 16-bits of high resolution timer"]
1615 pub const MBTSBASE_1: u32 = 0x01;
1616 #[doc = "Message Buffer Time Stamp base is upper 16-bits of high resolution timerT"]
1617 pub const MBTSBASE_2: u32 = 0x02;
1618 }
1619 }
1620 #[doc = "Edge Filter Disable"]
1621 pub mod EDFLTDIS {
1622 pub const offset: u32 = 11;
1623 pub const mask: u32 = 0x01 << offset;
1624 pub mod R {}
1625 pub mod W {}
1626 pub mod RW {
1627 #[doc = "Edge Filter is enabled"]
1628 pub const EDFLTDIS_0: u32 = 0;
1629 #[doc = "Edge Filter is disabled"]
1630 pub const EDFLTDIS_1: u32 = 0x01;
1631 }
1632 }
1633 #[doc = "ISO CAN FD Enable"]
1634 pub mod ISOCANFDEN {
1635 pub const offset: u32 = 12;
1636 pub const mask: u32 = 0x01 << offset;
1637 pub mod R {}
1638 pub mod W {}
1639 pub mod RW {
1640 #[doc = "FlexCAN operates using the non-ISO CAN FD protocol."]
1641 pub const ISOCANFDEN_0: u32 = 0;
1642 #[doc = "FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1)."]
1643 pub const ISOCANFDEN_1: u32 = 0x01;
1644 }
1645 }
1646 #[doc = "Bit Timing Expansion enable"]
1647 pub mod BTE {
1648 pub const offset: u32 = 13;
1649 pub const mask: u32 = 0x01 << offset;
1650 pub mod R {}
1651 pub mod W {}
1652 pub mod RW {
1653 #[doc = "CAN Bit timing expansion is disabled."]
1654 pub const BTE_0: u32 = 0;
1655 #[doc = "CAN bit timing expansion is enabled."]
1656 pub const BTE_1: u32 = 0x01;
1657 }
1658 }
1659 #[doc = "Protocol Exception Enable"]
1660 pub mod PREXCEN {
1661 pub const offset: u32 = 14;
1662 pub const mask: u32 = 0x01 << offset;
1663 pub mod R {}
1664 pub mod W {}
1665 pub mod RW {
1666 #[doc = "Protocol Exception is disabled."]
1667 pub const PREXCEN_0: u32 = 0;
1668 #[doc = "Protocol Exception is enabled."]
1669 pub const PREXCEN_1: u32 = 0x01;
1670 }
1671 }
1672 #[doc = "Timer Source"]
1673 pub mod TIMER_SRC {
1674 pub const offset: u32 = 15;
1675 pub const mask: u32 = 0x01 << offset;
1676 pub mod R {}
1677 pub mod W {}
1678 pub mod RW {
1679 #[doc = "The Free Running Timer is clocked by the CAN bit clock, which defines the baud rate on the CAN bus."]
1680 pub const TIMER_SRC_0: u32 = 0;
1681 #[doc = "The Free Running Timer is clocked by an external time tick. The period can be either adjusted to be equal to the baud rate on the CAN bus, or a different value as required. See the device specific section for details about the external time tick."]
1682 pub const TIMER_SRC_1: u32 = 0x01;
1683 }
1684 }
1685 #[doc = "Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes"]
1686 pub mod EACEN {
1687 pub const offset: u32 = 16;
1688 pub const mask: u32 = 0x01 << offset;
1689 pub mod R {}
1690 pub mod W {}
1691 pub mod RW {
1692 #[doc = "Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits."]
1693 pub const EACEN_0: u32 = 0;
1694 #[doc = "Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply."]
1695 pub const EACEN_1: u32 = 0x01;
1696 }
1697 }
1698 #[doc = "Remote Request Storing"]
1699 pub mod RRS {
1700 pub const offset: u32 = 17;
1701 pub const mask: u32 = 0x01 << offset;
1702 pub mod R {}
1703 pub mod W {}
1704 pub mod RW {
1705 #[doc = "Remote Response Frame is generated."]
1706 pub const RRS_0: u32 = 0;
1707 #[doc = "Remote Request Frame is stored."]
1708 pub const RRS_1: u32 = 0x01;
1709 }
1710 }
1711 #[doc = "Mailboxes Reception Priority"]
1712 pub mod MRP {
1713 pub const offset: u32 = 18;
1714 pub const mask: u32 = 0x01 << offset;
1715 pub mod R {}
1716 pub mod W {}
1717 pub mod RW {
1718 #[doc = "Matching starts from Legacy Rx FIFO or Enhanced Rx FIFO and continues on Mailboxes."]
1719 pub const MRP_0: u32 = 0;
1720 #[doc = "Matching starts from Mailboxes and continues on Legacy Rx FIFO or Enhanced Rx FIFO ."]
1721 pub const MRP_1: u32 = 0x01;
1722 }
1723 }
1724 #[doc = "Tx Arbitration Start Delay"]
1725 pub mod TASD {
1726 pub const offset: u32 = 19;
1727 pub const mask: u32 = 0x1f << offset;
1728 pub mod R {}
1729 pub mod W {}
1730 pub mod RW {}
1731 }
1732 #[doc = "Number Of Legacy Rx FIFO Filters"]
1733 pub mod RFFN {
1734 pub const offset: u32 = 24;
1735 pub const mask: u32 = 0x0f << offset;
1736 pub mod R {}
1737 pub mod W {}
1738 pub mod RW {}
1739 }
1740 #[doc = "Bus Off Done Interrupt Mask"]
1741 pub mod BOFFDONEMSK {
1742 pub const offset: u32 = 30;
1743 pub const mask: u32 = 0x01 << offset;
1744 pub mod R {}
1745 pub mod W {}
1746 pub mod RW {
1747 #[doc = "Bus Off Done interrupt disabled."]
1748 pub const BOFFDONEMSK_0: u32 = 0;
1749 #[doc = "Bus Off Done interrupt enabled."]
1750 pub const BOFFDONEMSK_1: u32 = 0x01;
1751 }
1752 }
1753 #[doc = "Error Interrupt Mask for errors detected in the Data Phase of fast CAN FD frames"]
1754 pub mod ERRMSK_FAST {
1755 pub const offset: u32 = 31;
1756 pub const mask: u32 = 0x01 << offset;
1757 pub mod R {}
1758 pub mod W {}
1759 pub mod RW {
1760 #[doc = "ERRINT_FAST Error interrupt disabled."]
1761 pub const ERRMSK_FAST_0: u32 = 0;
1762 #[doc = "ERRINT_FAST Error interrupt enabled."]
1763 pub const ERRMSK_FAST_1: u32 = 0x01;
1764 }
1765 }
1766}
1767#[doc = "Error and Status 2 register"]
1768pub mod ESR2 {
1769 #[doc = "Inactive Mailbox"]
1770 pub mod IMB {
1771 pub const offset: u32 = 13;
1772 pub const mask: u32 = 0x01 << offset;
1773 pub mod R {}
1774 pub mod W {}
1775 pub mod RW {
1776 #[doc = "If CAN_ESR2\\[VPS\\] is asserted, the CAN_ESR2\\[LPTM\\] is not an inactive Mailbox."]
1777 pub const IMB_0: u32 = 0;
1778 #[doc = "If CAN_ESR2\\[VPS\\] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one."]
1779 pub const IMB_1: u32 = 0x01;
1780 }
1781 }
1782 #[doc = "Valid Priority Status"]
1783 pub mod VPS {
1784 pub const offset: u32 = 14;
1785 pub const mask: u32 = 0x01 << offset;
1786 pub mod R {}
1787 pub mod W {}
1788 pub mod RW {
1789 #[doc = "Contents of IMB and LPTM are invalid."]
1790 pub const VPS_0: u32 = 0;
1791 #[doc = "Contents of IMB and LPTM are valid."]
1792 pub const VPS_1: u32 = 0x01;
1793 }
1794 }
1795 #[doc = "Lowest Priority Tx Mailbox"]
1796 pub mod LPTM {
1797 pub const offset: u32 = 16;
1798 pub const mask: u32 = 0x7f << offset;
1799 pub mod R {}
1800 pub mod W {}
1801 pub mod RW {}
1802 }
1803}
1804#[doc = "CRC Register"]
1805pub mod CRCR {
1806 #[doc = "Transmitted CRC value"]
1807 pub mod TXCRC {
1808 pub const offset: u32 = 0;
1809 pub const mask: u32 = 0x7fff << offset;
1810 pub mod R {}
1811 pub mod W {}
1812 pub mod RW {}
1813 }
1814 #[doc = "CRC Mailbox"]
1815 pub mod MBCRC {
1816 pub const offset: u32 = 16;
1817 pub const mask: u32 = 0x7f << offset;
1818 pub mod R {}
1819 pub mod W {}
1820 pub mod RW {}
1821 }
1822}
1823#[doc = "Legacy Rx FIFO Global Mask register"]
1824pub mod RXFGMASK {
1825 #[doc = "Legacy Rx FIFO Global Mask Bits"]
1826 pub mod FGM {
1827 pub const offset: u32 = 0;
1828 pub const mask: u32 = 0xffff_ffff << offset;
1829 pub mod R {}
1830 pub mod W {}
1831 pub mod RW {}
1832 }
1833}
1834#[doc = "Legacy Rx FIFO Information Register"]
1835pub mod RXFIR {
1836 #[doc = "Identifier Acceptance Filter Hit Indicator"]
1837 pub mod IDHIT {
1838 pub const offset: u32 = 0;
1839 pub const mask: u32 = 0x01ff << offset;
1840 pub mod R {}
1841 pub mod W {}
1842 pub mod RW {}
1843 }
1844}
1845#[doc = "CAN Bit Timing Register"]
1846pub mod CBT {
1847 #[doc = "Extended Phase Segment 2"]
1848 pub mod EPSEG2 {
1849 pub const offset: u32 = 0;
1850 pub const mask: u32 = 0x1f << offset;
1851 pub mod R {}
1852 pub mod W {}
1853 pub mod RW {}
1854 }
1855 #[doc = "Extended Phase Segment 1"]
1856 pub mod EPSEG1 {
1857 pub const offset: u32 = 5;
1858 pub const mask: u32 = 0x1f << offset;
1859 pub mod R {}
1860 pub mod W {}
1861 pub mod RW {}
1862 }
1863 #[doc = "Extended Propagation Segment"]
1864 pub mod EPROPSEG {
1865 pub const offset: u32 = 10;
1866 pub const mask: u32 = 0x3f << offset;
1867 pub mod R {}
1868 pub mod W {}
1869 pub mod RW {}
1870 }
1871 #[doc = "Extended Resync Jump Width"]
1872 pub mod ERJW {
1873 pub const offset: u32 = 16;
1874 pub const mask: u32 = 0x1f << offset;
1875 pub mod R {}
1876 pub mod W {}
1877 pub mod RW {}
1878 }
1879 #[doc = "Extended Prescaler Division Factor"]
1880 pub mod EPRESDIV {
1881 pub const offset: u32 = 21;
1882 pub const mask: u32 = 0x03ff << offset;
1883 pub mod R {}
1884 pub mod W {}
1885 pub mod RW {}
1886 }
1887 #[doc = "Bit Timing Format Enable"]
1888 pub mod BTF {
1889 pub const offset: u32 = 31;
1890 pub const mask: u32 = 0x01 << offset;
1891 pub mod R {}
1892 pub mod W {}
1893 pub mod RW {
1894 #[doc = "Extended bit time definitions disabled."]
1895 pub const BTF_0: u32 = 0;
1896 #[doc = "Extended bit time definitions enabled."]
1897 pub const BTF_1: u32 = 0x01;
1898 }
1899 }
1900}
1901#[doc = "Message Buffer 0 CS Register"]
1902pub mod CS0 {
1903 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
1904 pub mod TIME_STAMP {
1905 pub const offset: u32 = 0;
1906 pub const mask: u32 = 0xffff << offset;
1907 pub mod R {}
1908 pub mod W {}
1909 pub mod RW {}
1910 }
1911 #[doc = "Length of the data to be stored/transmitted."]
1912 pub mod DLC {
1913 pub const offset: u32 = 16;
1914 pub const mask: u32 = 0x0f << offset;
1915 pub mod R {}
1916 pub mod W {}
1917 pub mod RW {}
1918 }
1919 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
1920 pub mod RTR {
1921 pub const offset: u32 = 20;
1922 pub const mask: u32 = 0x01 << offset;
1923 pub mod R {}
1924 pub mod W {}
1925 pub mod RW {}
1926 }
1927 #[doc = "ID Extended. One/zero for extended/standard format frame."]
1928 pub mod IDE {
1929 pub const offset: u32 = 21;
1930 pub const mask: u32 = 0x01 << offset;
1931 pub mod R {}
1932 pub mod W {}
1933 pub mod RW {}
1934 }
1935 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
1936 pub mod SRR {
1937 pub const offset: u32 = 22;
1938 pub const mask: u32 = 0x01 << offset;
1939 pub mod R {}
1940 pub mod W {}
1941 pub mod RW {}
1942 }
1943 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
1944 pub mod CODE {
1945 pub const offset: u32 = 24;
1946 pub const mask: u32 = 0x0f << offset;
1947 pub mod R {}
1948 pub mod W {}
1949 pub mod RW {}
1950 }
1951 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
1952 pub mod ESI {
1953 pub const offset: u32 = 29;
1954 pub const mask: u32 = 0x01 << offset;
1955 pub mod R {}
1956 pub mod W {}
1957 pub mod RW {}
1958 }
1959 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
1960 pub mod BRS {
1961 pub const offset: u32 = 30;
1962 pub const mask: u32 = 0x01 << offset;
1963 pub mod R {}
1964 pub mod W {}
1965 pub mod RW {}
1966 }
1967 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
1968 pub mod EDL {
1969 pub const offset: u32 = 31;
1970 pub const mask: u32 = 0x01 << offset;
1971 pub mod R {}
1972 pub mod W {}
1973 pub mod RW {}
1974 }
1975}
1976#[doc = "Message Buffer 0 ID Register"]
1977pub mod ID0 {
1978 #[doc = "Contains extended (LOW word) identifier of message buffer."]
1979 pub mod EXT {
1980 pub const offset: u32 = 0;
1981 pub const mask: u32 = 0x0003_ffff << offset;
1982 pub mod R {}
1983 pub mod W {}
1984 pub mod RW {}
1985 }
1986 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
1987 pub mod STD {
1988 pub const offset: u32 = 18;
1989 pub const mask: u32 = 0x07ff << offset;
1990 pub mod R {}
1991 pub mod W {}
1992 pub mod RW {}
1993 }
1994 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
1995 pub mod PRIO {
1996 pub const offset: u32 = 29;
1997 pub const mask: u32 = 0x07 << offset;
1998 pub mod R {}
1999 pub mod W {}
2000 pub mod RW {}
2001 }
2002}
2003#[doc = "Message Buffer 0 WORD_16B Register"]
2004pub mod MB0_16B_WORD0 {
2005 #[doc = "Data byte 0 of Rx/Tx frame."]
2006 pub mod DATA_BYTE_3 {
2007 pub const offset: u32 = 0;
2008 pub const mask: u32 = 0xff << offset;
2009 pub mod R {}
2010 pub mod W {}
2011 pub mod RW {}
2012 }
2013 #[doc = "Data byte 1 of Rx/Tx frame."]
2014 pub mod DATA_BYTE_2 {
2015 pub const offset: u32 = 8;
2016 pub const mask: u32 = 0xff << offset;
2017 pub mod R {}
2018 pub mod W {}
2019 pub mod RW {}
2020 }
2021 #[doc = "Data byte 2 of Rx/Tx frame."]
2022 pub mod DATA_BYTE_1 {
2023 pub const offset: u32 = 16;
2024 pub const mask: u32 = 0xff << offset;
2025 pub mod R {}
2026 pub mod W {}
2027 pub mod RW {}
2028 }
2029 #[doc = "Data byte 3 of Rx/Tx frame."]
2030 pub mod DATA_BYTE_0 {
2031 pub const offset: u32 = 24;
2032 pub const mask: u32 = 0xff << offset;
2033 pub mod R {}
2034 pub mod W {}
2035 pub mod RW {}
2036 }
2037}
2038#[doc = "Message Buffer 0 WORD_16B Register"]
2039pub mod MB0_16B_WORD1 {
2040 #[doc = "Data byte 0 of Rx/Tx frame."]
2041 pub mod DATA_BYTE_7 {
2042 pub const offset: u32 = 0;
2043 pub const mask: u32 = 0xff << offset;
2044 pub mod R {}
2045 pub mod W {}
2046 pub mod RW {}
2047 }
2048 #[doc = "Data byte 1 of Rx/Tx frame."]
2049 pub mod DATA_BYTE_6 {
2050 pub const offset: u32 = 8;
2051 pub const mask: u32 = 0xff << offset;
2052 pub mod R {}
2053 pub mod W {}
2054 pub mod RW {}
2055 }
2056 #[doc = "Data byte 2 of Rx/Tx frame."]
2057 pub mod DATA_BYTE_5 {
2058 pub const offset: u32 = 16;
2059 pub const mask: u32 = 0xff << offset;
2060 pub mod R {}
2061 pub mod W {}
2062 pub mod RW {}
2063 }
2064 #[doc = "Data byte 3 of Rx/Tx frame."]
2065 pub mod DATA_BYTE_4 {
2066 pub const offset: u32 = 24;
2067 pub const mask: u32 = 0xff << offset;
2068 pub mod R {}
2069 pub mod W {}
2070 pub mod RW {}
2071 }
2072}
2073#[doc = "Message Buffer 1 CS Register"]
2074pub mod CS1 {
2075 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
2076 pub mod TIME_STAMP {
2077 pub const offset: u32 = 0;
2078 pub const mask: u32 = 0xffff << offset;
2079 pub mod R {}
2080 pub mod W {}
2081 pub mod RW {}
2082 }
2083 #[doc = "Length of the data to be stored/transmitted."]
2084 pub mod DLC {
2085 pub const offset: u32 = 16;
2086 pub const mask: u32 = 0x0f << offset;
2087 pub mod R {}
2088 pub mod W {}
2089 pub mod RW {}
2090 }
2091 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
2092 pub mod RTR {
2093 pub const offset: u32 = 20;
2094 pub const mask: u32 = 0x01 << offset;
2095 pub mod R {}
2096 pub mod W {}
2097 pub mod RW {}
2098 }
2099 #[doc = "ID Extended. One/zero for extended/standard format frame."]
2100 pub mod IDE {
2101 pub const offset: u32 = 21;
2102 pub const mask: u32 = 0x01 << offset;
2103 pub mod R {}
2104 pub mod W {}
2105 pub mod RW {}
2106 }
2107 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
2108 pub mod SRR {
2109 pub const offset: u32 = 22;
2110 pub const mask: u32 = 0x01 << offset;
2111 pub mod R {}
2112 pub mod W {}
2113 pub mod RW {}
2114 }
2115 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
2116 pub mod CODE {
2117 pub const offset: u32 = 24;
2118 pub const mask: u32 = 0x0f << offset;
2119 pub mod R {}
2120 pub mod W {}
2121 pub mod RW {}
2122 }
2123 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
2124 pub mod ESI {
2125 pub const offset: u32 = 29;
2126 pub const mask: u32 = 0x01 << offset;
2127 pub mod R {}
2128 pub mod W {}
2129 pub mod RW {}
2130 }
2131 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
2132 pub mod BRS {
2133 pub const offset: u32 = 30;
2134 pub const mask: u32 = 0x01 << offset;
2135 pub mod R {}
2136 pub mod W {}
2137 pub mod RW {}
2138 }
2139 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
2140 pub mod EDL {
2141 pub const offset: u32 = 31;
2142 pub const mask: u32 = 0x01 << offset;
2143 pub mod R {}
2144 pub mod W {}
2145 pub mod RW {}
2146 }
2147}
2148#[doc = "Message Buffer 1 ID Register"]
2149pub mod ID1 {
2150 #[doc = "Contains extended (LOW word) identifier of message buffer."]
2151 pub mod EXT {
2152 pub const offset: u32 = 0;
2153 pub const mask: u32 = 0x0003_ffff << offset;
2154 pub mod R {}
2155 pub mod W {}
2156 pub mod RW {}
2157 }
2158 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
2159 pub mod STD {
2160 pub const offset: u32 = 18;
2161 pub const mask: u32 = 0x07ff << offset;
2162 pub mod R {}
2163 pub mod W {}
2164 pub mod RW {}
2165 }
2166 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
2167 pub mod PRIO {
2168 pub const offset: u32 = 29;
2169 pub const mask: u32 = 0x07 << offset;
2170 pub mod R {}
2171 pub mod W {}
2172 pub mod RW {}
2173 }
2174}
2175#[doc = "Message Buffer 0 WORD_32B Register"]
2176pub mod MB0_32B_WORD4 {
2177 #[doc = "Data byte 0 of Rx/Tx frame."]
2178 pub mod DATA_BYTE_19 {
2179 pub const offset: u32 = 0;
2180 pub const mask: u32 = 0xff << offset;
2181 pub mod R {}
2182 pub mod W {}
2183 pub mod RW {}
2184 }
2185 #[doc = "Data byte 1 of Rx/Tx frame."]
2186 pub mod DATA_BYTE_18 {
2187 pub const offset: u32 = 8;
2188 pub const mask: u32 = 0xff << offset;
2189 pub mod R {}
2190 pub mod W {}
2191 pub mod RW {}
2192 }
2193 #[doc = "Data byte 2 of Rx/Tx frame."]
2194 pub mod DATA_BYTE_17 {
2195 pub const offset: u32 = 16;
2196 pub const mask: u32 = 0xff << offset;
2197 pub mod R {}
2198 pub mod W {}
2199 pub mod RW {}
2200 }
2201 #[doc = "Data byte 3 of Rx/Tx frame."]
2202 pub mod DATA_BYTE_16 {
2203 pub const offset: u32 = 24;
2204 pub const mask: u32 = 0xff << offset;
2205 pub mod R {}
2206 pub mod W {}
2207 pub mod RW {}
2208 }
2209}
2210#[doc = "Message Buffer 0 WORD_32B Register"]
2211pub mod MB0_32B_WORD5 {
2212 #[doc = "Data byte 0 of Rx/Tx frame."]
2213 pub mod DATA_BYTE_23 {
2214 pub const offset: u32 = 0;
2215 pub const mask: u32 = 0xff << offset;
2216 pub mod R {}
2217 pub mod W {}
2218 pub mod RW {}
2219 }
2220 #[doc = "Data byte 1 of Rx/Tx frame."]
2221 pub mod DATA_BYTE_22 {
2222 pub const offset: u32 = 8;
2223 pub const mask: u32 = 0xff << offset;
2224 pub mod R {}
2225 pub mod W {}
2226 pub mod RW {}
2227 }
2228 #[doc = "Data byte 2 of Rx/Tx frame."]
2229 pub mod DATA_BYTE_21 {
2230 pub const offset: u32 = 16;
2231 pub const mask: u32 = 0xff << offset;
2232 pub mod R {}
2233 pub mod W {}
2234 pub mod RW {}
2235 }
2236 #[doc = "Data byte 3 of Rx/Tx frame."]
2237 pub mod DATA_BYTE_20 {
2238 pub const offset: u32 = 24;
2239 pub const mask: u32 = 0xff << offset;
2240 pub mod R {}
2241 pub mod W {}
2242 pub mod RW {}
2243 }
2244}
2245#[doc = "Message Buffer 2 CS Register"]
2246pub mod CS2 {
2247 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
2248 pub mod TIME_STAMP {
2249 pub const offset: u32 = 0;
2250 pub const mask: u32 = 0xffff << offset;
2251 pub mod R {}
2252 pub mod W {}
2253 pub mod RW {}
2254 }
2255 #[doc = "Length of the data to be stored/transmitted."]
2256 pub mod DLC {
2257 pub const offset: u32 = 16;
2258 pub const mask: u32 = 0x0f << offset;
2259 pub mod R {}
2260 pub mod W {}
2261 pub mod RW {}
2262 }
2263 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
2264 pub mod RTR {
2265 pub const offset: u32 = 20;
2266 pub const mask: u32 = 0x01 << offset;
2267 pub mod R {}
2268 pub mod W {}
2269 pub mod RW {}
2270 }
2271 #[doc = "ID Extended. One/zero for extended/standard format frame."]
2272 pub mod IDE {
2273 pub const offset: u32 = 21;
2274 pub const mask: u32 = 0x01 << offset;
2275 pub mod R {}
2276 pub mod W {}
2277 pub mod RW {}
2278 }
2279 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
2280 pub mod SRR {
2281 pub const offset: u32 = 22;
2282 pub const mask: u32 = 0x01 << offset;
2283 pub mod R {}
2284 pub mod W {}
2285 pub mod RW {}
2286 }
2287 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
2288 pub mod CODE {
2289 pub const offset: u32 = 24;
2290 pub const mask: u32 = 0x0f << offset;
2291 pub mod R {}
2292 pub mod W {}
2293 pub mod RW {}
2294 }
2295 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
2296 pub mod ESI {
2297 pub const offset: u32 = 29;
2298 pub const mask: u32 = 0x01 << offset;
2299 pub mod R {}
2300 pub mod W {}
2301 pub mod RW {}
2302 }
2303 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
2304 pub mod BRS {
2305 pub const offset: u32 = 30;
2306 pub const mask: u32 = 0x01 << offset;
2307 pub mod R {}
2308 pub mod W {}
2309 pub mod RW {}
2310 }
2311 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
2312 pub mod EDL {
2313 pub const offset: u32 = 31;
2314 pub const mask: u32 = 0x01 << offset;
2315 pub mod R {}
2316 pub mod W {}
2317 pub mod RW {}
2318 }
2319}
2320#[doc = "Message Buffer 2 ID Register"]
2321pub mod ID2 {
2322 #[doc = "Contains extended (LOW word) identifier of message buffer."]
2323 pub mod EXT {
2324 pub const offset: u32 = 0;
2325 pub const mask: u32 = 0x0003_ffff << offset;
2326 pub mod R {}
2327 pub mod W {}
2328 pub mod RW {}
2329 }
2330 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
2331 pub mod STD {
2332 pub const offset: u32 = 18;
2333 pub const mask: u32 = 0x07ff << offset;
2334 pub mod R {}
2335 pub mod W {}
2336 pub mod RW {}
2337 }
2338 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
2339 pub mod PRIO {
2340 pub const offset: u32 = 29;
2341 pub const mask: u32 = 0x07 << offset;
2342 pub mod R {}
2343 pub mod W {}
2344 pub mod RW {}
2345 }
2346}
2347#[doc = "Message Buffer 0 WORD_64B Register"]
2348pub mod MB0_64B_WORD8 {
2349 #[doc = "Data byte 0 of Rx/Tx frame."]
2350 pub mod DATA_BYTE_35 {
2351 pub const offset: u32 = 0;
2352 pub const mask: u32 = 0xff << offset;
2353 pub mod R {}
2354 pub mod W {}
2355 pub mod RW {}
2356 }
2357 #[doc = "Data byte 1 of Rx/Tx frame."]
2358 pub mod DATA_BYTE_34 {
2359 pub const offset: u32 = 8;
2360 pub const mask: u32 = 0xff << offset;
2361 pub mod R {}
2362 pub mod W {}
2363 pub mod RW {}
2364 }
2365 #[doc = "Data byte 2 of Rx/Tx frame."]
2366 pub mod DATA_BYTE_33 {
2367 pub const offset: u32 = 16;
2368 pub const mask: u32 = 0xff << offset;
2369 pub mod R {}
2370 pub mod W {}
2371 pub mod RW {}
2372 }
2373 #[doc = "Data byte 3 of Rx/Tx frame."]
2374 pub mod DATA_BYTE_32 {
2375 pub const offset: u32 = 24;
2376 pub const mask: u32 = 0xff << offset;
2377 pub mod R {}
2378 pub mod W {}
2379 pub mod RW {}
2380 }
2381}
2382#[doc = "Message Buffer 0 WORD_64B Register"]
2383pub mod MB0_64B_WORD9 {
2384 #[doc = "Data byte 0 of Rx/Tx frame."]
2385 pub mod DATA_BYTE_39 {
2386 pub const offset: u32 = 0;
2387 pub const mask: u32 = 0xff << offset;
2388 pub mod R {}
2389 pub mod W {}
2390 pub mod RW {}
2391 }
2392 #[doc = "Data byte 1 of Rx/Tx frame."]
2393 pub mod DATA_BYTE_38 {
2394 pub const offset: u32 = 8;
2395 pub const mask: u32 = 0xff << offset;
2396 pub mod R {}
2397 pub mod W {}
2398 pub mod RW {}
2399 }
2400 #[doc = "Data byte 2 of Rx/Tx frame."]
2401 pub mod DATA_BYTE_37 {
2402 pub const offset: u32 = 16;
2403 pub const mask: u32 = 0xff << offset;
2404 pub mod R {}
2405 pub mod W {}
2406 pub mod RW {}
2407 }
2408 #[doc = "Data byte 3 of Rx/Tx frame."]
2409 pub mod DATA_BYTE_36 {
2410 pub const offset: u32 = 24;
2411 pub const mask: u32 = 0xff << offset;
2412 pub mod R {}
2413 pub mod W {}
2414 pub mod RW {}
2415 }
2416}
2417#[doc = "Message Buffer 3 CS Register"]
2418pub mod CS3 {
2419 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
2420 pub mod TIME_STAMP {
2421 pub const offset: u32 = 0;
2422 pub const mask: u32 = 0xffff << offset;
2423 pub mod R {}
2424 pub mod W {}
2425 pub mod RW {}
2426 }
2427 #[doc = "Length of the data to be stored/transmitted."]
2428 pub mod DLC {
2429 pub const offset: u32 = 16;
2430 pub const mask: u32 = 0x0f << offset;
2431 pub mod R {}
2432 pub mod W {}
2433 pub mod RW {}
2434 }
2435 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
2436 pub mod RTR {
2437 pub const offset: u32 = 20;
2438 pub const mask: u32 = 0x01 << offset;
2439 pub mod R {}
2440 pub mod W {}
2441 pub mod RW {}
2442 }
2443 #[doc = "ID Extended. One/zero for extended/standard format frame."]
2444 pub mod IDE {
2445 pub const offset: u32 = 21;
2446 pub const mask: u32 = 0x01 << offset;
2447 pub mod R {}
2448 pub mod W {}
2449 pub mod RW {}
2450 }
2451 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
2452 pub mod SRR {
2453 pub const offset: u32 = 22;
2454 pub const mask: u32 = 0x01 << offset;
2455 pub mod R {}
2456 pub mod W {}
2457 pub mod RW {}
2458 }
2459 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
2460 pub mod CODE {
2461 pub const offset: u32 = 24;
2462 pub const mask: u32 = 0x0f << offset;
2463 pub mod R {}
2464 pub mod W {}
2465 pub mod RW {}
2466 }
2467 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
2468 pub mod ESI {
2469 pub const offset: u32 = 29;
2470 pub const mask: u32 = 0x01 << offset;
2471 pub mod R {}
2472 pub mod W {}
2473 pub mod RW {}
2474 }
2475 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
2476 pub mod BRS {
2477 pub const offset: u32 = 30;
2478 pub const mask: u32 = 0x01 << offset;
2479 pub mod R {}
2480 pub mod W {}
2481 pub mod RW {}
2482 }
2483 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
2484 pub mod EDL {
2485 pub const offset: u32 = 31;
2486 pub const mask: u32 = 0x01 << offset;
2487 pub mod R {}
2488 pub mod W {}
2489 pub mod RW {}
2490 }
2491}
2492#[doc = "Message Buffer 3 ID Register"]
2493pub mod ID3 {
2494 #[doc = "Contains extended (LOW word) identifier of message buffer."]
2495 pub mod EXT {
2496 pub const offset: u32 = 0;
2497 pub const mask: u32 = 0x0003_ffff << offset;
2498 pub mod R {}
2499 pub mod W {}
2500 pub mod RW {}
2501 }
2502 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
2503 pub mod STD {
2504 pub const offset: u32 = 18;
2505 pub const mask: u32 = 0x07ff << offset;
2506 pub mod R {}
2507 pub mod W {}
2508 pub mod RW {}
2509 }
2510 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
2511 pub mod PRIO {
2512 pub const offset: u32 = 29;
2513 pub const mask: u32 = 0x07 << offset;
2514 pub mod R {}
2515 pub mod W {}
2516 pub mod RW {}
2517 }
2518}
2519#[doc = "Message Buffer 0 WORD_64B Register"]
2520pub mod MB0_64B_WORD12 {
2521 #[doc = "Data byte 0 of Rx/Tx frame."]
2522 pub mod DATA_BYTE_51 {
2523 pub const offset: u32 = 0;
2524 pub const mask: u32 = 0xff << offset;
2525 pub mod R {}
2526 pub mod W {}
2527 pub mod RW {}
2528 }
2529 #[doc = "Data byte 1 of Rx/Tx frame."]
2530 pub mod DATA_BYTE_50 {
2531 pub const offset: u32 = 8;
2532 pub const mask: u32 = 0xff << offset;
2533 pub mod R {}
2534 pub mod W {}
2535 pub mod RW {}
2536 }
2537 #[doc = "Data byte 2 of Rx/Tx frame."]
2538 pub mod DATA_BYTE_49 {
2539 pub const offset: u32 = 16;
2540 pub const mask: u32 = 0xff << offset;
2541 pub mod R {}
2542 pub mod W {}
2543 pub mod RW {}
2544 }
2545 #[doc = "Data byte 3 of Rx/Tx frame."]
2546 pub mod DATA_BYTE_48 {
2547 pub const offset: u32 = 24;
2548 pub const mask: u32 = 0xff << offset;
2549 pub mod R {}
2550 pub mod W {}
2551 pub mod RW {}
2552 }
2553}
2554#[doc = "Message Buffer 0 WORD_64B Register"]
2555pub mod MB0_64B_WORD13 {
2556 #[doc = "Data byte 0 of Rx/Tx frame."]
2557 pub mod DATA_BYTE_55 {
2558 pub const offset: u32 = 0;
2559 pub const mask: u32 = 0xff << offset;
2560 pub mod R {}
2561 pub mod W {}
2562 pub mod RW {}
2563 }
2564 #[doc = "Data byte 1 of Rx/Tx frame."]
2565 pub mod DATA_BYTE_54 {
2566 pub const offset: u32 = 8;
2567 pub const mask: u32 = 0xff << offset;
2568 pub mod R {}
2569 pub mod W {}
2570 pub mod RW {}
2571 }
2572 #[doc = "Data byte 2 of Rx/Tx frame."]
2573 pub mod DATA_BYTE_53 {
2574 pub const offset: u32 = 16;
2575 pub const mask: u32 = 0xff << offset;
2576 pub mod R {}
2577 pub mod W {}
2578 pub mod RW {}
2579 }
2580 #[doc = "Data byte 3 of Rx/Tx frame."]
2581 pub mod DATA_BYTE_52 {
2582 pub const offset: u32 = 24;
2583 pub const mask: u32 = 0xff << offset;
2584 pub mod R {}
2585 pub mod W {}
2586 pub mod RW {}
2587 }
2588}
2589#[doc = "Message Buffer 4 CS Register"]
2590pub mod CS4 {
2591 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
2592 pub mod TIME_STAMP {
2593 pub const offset: u32 = 0;
2594 pub const mask: u32 = 0xffff << offset;
2595 pub mod R {}
2596 pub mod W {}
2597 pub mod RW {}
2598 }
2599 #[doc = "Length of the data to be stored/transmitted."]
2600 pub mod DLC {
2601 pub const offset: u32 = 16;
2602 pub const mask: u32 = 0x0f << offset;
2603 pub mod R {}
2604 pub mod W {}
2605 pub mod RW {}
2606 }
2607 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
2608 pub mod RTR {
2609 pub const offset: u32 = 20;
2610 pub const mask: u32 = 0x01 << offset;
2611 pub mod R {}
2612 pub mod W {}
2613 pub mod RW {}
2614 }
2615 #[doc = "ID Extended. One/zero for extended/standard format frame."]
2616 pub mod IDE {
2617 pub const offset: u32 = 21;
2618 pub const mask: u32 = 0x01 << offset;
2619 pub mod R {}
2620 pub mod W {}
2621 pub mod RW {}
2622 }
2623 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
2624 pub mod SRR {
2625 pub const offset: u32 = 22;
2626 pub const mask: u32 = 0x01 << offset;
2627 pub mod R {}
2628 pub mod W {}
2629 pub mod RW {}
2630 }
2631 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
2632 pub mod CODE {
2633 pub const offset: u32 = 24;
2634 pub const mask: u32 = 0x0f << offset;
2635 pub mod R {}
2636 pub mod W {}
2637 pub mod RW {}
2638 }
2639 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
2640 pub mod ESI {
2641 pub const offset: u32 = 29;
2642 pub const mask: u32 = 0x01 << offset;
2643 pub mod R {}
2644 pub mod W {}
2645 pub mod RW {}
2646 }
2647 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
2648 pub mod BRS {
2649 pub const offset: u32 = 30;
2650 pub const mask: u32 = 0x01 << offset;
2651 pub mod R {}
2652 pub mod W {}
2653 pub mod RW {}
2654 }
2655 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
2656 pub mod EDL {
2657 pub const offset: u32 = 31;
2658 pub const mask: u32 = 0x01 << offset;
2659 pub mod R {}
2660 pub mod W {}
2661 pub mod RW {}
2662 }
2663}
2664#[doc = "Message Buffer 4 ID Register"]
2665pub mod ID4 {
2666 #[doc = "Contains extended (LOW word) identifier of message buffer."]
2667 pub mod EXT {
2668 pub const offset: u32 = 0;
2669 pub const mask: u32 = 0x0003_ffff << offset;
2670 pub mod R {}
2671 pub mod W {}
2672 pub mod RW {}
2673 }
2674 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
2675 pub mod STD {
2676 pub const offset: u32 = 18;
2677 pub const mask: u32 = 0x07ff << offset;
2678 pub mod R {}
2679 pub mod W {}
2680 pub mod RW {}
2681 }
2682 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
2683 pub mod PRIO {
2684 pub const offset: u32 = 29;
2685 pub const mask: u32 = 0x07 << offset;
2686 pub mod R {}
2687 pub mod W {}
2688 pub mod RW {}
2689 }
2690}
2691#[doc = "Message Buffer 1 WORD_32B Register"]
2692pub mod MB1_32B_WORD6 {
2693 #[doc = "Data byte 0 of Rx/Tx frame."]
2694 pub mod DATA_BYTE_27 {
2695 pub const offset: u32 = 0;
2696 pub const mask: u32 = 0xff << offset;
2697 pub mod R {}
2698 pub mod W {}
2699 pub mod RW {}
2700 }
2701 #[doc = "Data byte 1 of Rx/Tx frame."]
2702 pub mod DATA_BYTE_26 {
2703 pub const offset: u32 = 8;
2704 pub const mask: u32 = 0xff << offset;
2705 pub mod R {}
2706 pub mod W {}
2707 pub mod RW {}
2708 }
2709 #[doc = "Data byte 2 of Rx/Tx frame."]
2710 pub mod DATA_BYTE_25 {
2711 pub const offset: u32 = 16;
2712 pub const mask: u32 = 0xff << offset;
2713 pub mod R {}
2714 pub mod W {}
2715 pub mod RW {}
2716 }
2717 #[doc = "Data byte 3 of Rx/Tx frame."]
2718 pub mod DATA_BYTE_24 {
2719 pub const offset: u32 = 24;
2720 pub const mask: u32 = 0xff << offset;
2721 pub mod R {}
2722 pub mod W {}
2723 pub mod RW {}
2724 }
2725}
2726#[doc = "Message Buffer 1 WORD_32B Register"]
2727pub mod MB1_32B_WORD7 {
2728 #[doc = "Data byte 0 of Rx/Tx frame."]
2729 pub mod DATA_BYTE_31 {
2730 pub const offset: u32 = 0;
2731 pub const mask: u32 = 0xff << offset;
2732 pub mod R {}
2733 pub mod W {}
2734 pub mod RW {}
2735 }
2736 #[doc = "Data byte 1 of Rx/Tx frame."]
2737 pub mod DATA_BYTE_30 {
2738 pub const offset: u32 = 8;
2739 pub const mask: u32 = 0xff << offset;
2740 pub mod R {}
2741 pub mod W {}
2742 pub mod RW {}
2743 }
2744 #[doc = "Data byte 2 of Rx/Tx frame."]
2745 pub mod DATA_BYTE_29 {
2746 pub const offset: u32 = 16;
2747 pub const mask: u32 = 0xff << offset;
2748 pub mod R {}
2749 pub mod W {}
2750 pub mod RW {}
2751 }
2752 #[doc = "Data byte 3 of Rx/Tx frame."]
2753 pub mod DATA_BYTE_28 {
2754 pub const offset: u32 = 24;
2755 pub const mask: u32 = 0xff << offset;
2756 pub mod R {}
2757 pub mod W {}
2758 pub mod RW {}
2759 }
2760}
2761#[doc = "Message Buffer 5 CS Register"]
2762pub mod CS5 {
2763 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
2764 pub mod TIME_STAMP {
2765 pub const offset: u32 = 0;
2766 pub const mask: u32 = 0xffff << offset;
2767 pub mod R {}
2768 pub mod W {}
2769 pub mod RW {}
2770 }
2771 #[doc = "Length of the data to be stored/transmitted."]
2772 pub mod DLC {
2773 pub const offset: u32 = 16;
2774 pub const mask: u32 = 0x0f << offset;
2775 pub mod R {}
2776 pub mod W {}
2777 pub mod RW {}
2778 }
2779 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
2780 pub mod RTR {
2781 pub const offset: u32 = 20;
2782 pub const mask: u32 = 0x01 << offset;
2783 pub mod R {}
2784 pub mod W {}
2785 pub mod RW {}
2786 }
2787 #[doc = "ID Extended. One/zero for extended/standard format frame."]
2788 pub mod IDE {
2789 pub const offset: u32 = 21;
2790 pub const mask: u32 = 0x01 << offset;
2791 pub mod R {}
2792 pub mod W {}
2793 pub mod RW {}
2794 }
2795 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
2796 pub mod SRR {
2797 pub const offset: u32 = 22;
2798 pub const mask: u32 = 0x01 << offset;
2799 pub mod R {}
2800 pub mod W {}
2801 pub mod RW {}
2802 }
2803 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
2804 pub mod CODE {
2805 pub const offset: u32 = 24;
2806 pub const mask: u32 = 0x0f << offset;
2807 pub mod R {}
2808 pub mod W {}
2809 pub mod RW {}
2810 }
2811 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
2812 pub mod ESI {
2813 pub const offset: u32 = 29;
2814 pub const mask: u32 = 0x01 << offset;
2815 pub mod R {}
2816 pub mod W {}
2817 pub mod RW {}
2818 }
2819 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
2820 pub mod BRS {
2821 pub const offset: u32 = 30;
2822 pub const mask: u32 = 0x01 << offset;
2823 pub mod R {}
2824 pub mod W {}
2825 pub mod RW {}
2826 }
2827 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
2828 pub mod EDL {
2829 pub const offset: u32 = 31;
2830 pub const mask: u32 = 0x01 << offset;
2831 pub mod R {}
2832 pub mod W {}
2833 pub mod RW {}
2834 }
2835}
2836#[doc = "Message Buffer 5 ID Register"]
2837pub mod ID5 {
2838 #[doc = "Contains extended (LOW word) identifier of message buffer."]
2839 pub mod EXT {
2840 pub const offset: u32 = 0;
2841 pub const mask: u32 = 0x0003_ffff << offset;
2842 pub mod R {}
2843 pub mod W {}
2844 pub mod RW {}
2845 }
2846 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
2847 pub mod STD {
2848 pub const offset: u32 = 18;
2849 pub const mask: u32 = 0x07ff << offset;
2850 pub mod R {}
2851 pub mod W {}
2852 pub mod RW {}
2853 }
2854 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
2855 pub mod PRIO {
2856 pub const offset: u32 = 29;
2857 pub const mask: u32 = 0x07 << offset;
2858 pub mod R {}
2859 pub mod W {}
2860 pub mod RW {}
2861 }
2862}
2863#[doc = "Message Buffer 1 WORD_64B Register"]
2864pub mod MB1_64B_WORD2 {
2865 #[doc = "Data byte 0 of Rx/Tx frame."]
2866 pub mod DATA_BYTE_11 {
2867 pub const offset: u32 = 0;
2868 pub const mask: u32 = 0xff << offset;
2869 pub mod R {}
2870 pub mod W {}
2871 pub mod RW {}
2872 }
2873 #[doc = "Data byte 1 of Rx/Tx frame."]
2874 pub mod DATA_BYTE_10 {
2875 pub const offset: u32 = 8;
2876 pub const mask: u32 = 0xff << offset;
2877 pub mod R {}
2878 pub mod W {}
2879 pub mod RW {}
2880 }
2881 #[doc = "Data byte 2 of Rx/Tx frame."]
2882 pub mod DATA_BYTE_9 {
2883 pub const offset: u32 = 16;
2884 pub const mask: u32 = 0xff << offset;
2885 pub mod R {}
2886 pub mod W {}
2887 pub mod RW {}
2888 }
2889 #[doc = "Data byte 3 of Rx/Tx frame."]
2890 pub mod DATA_BYTE_8 {
2891 pub const offset: u32 = 24;
2892 pub const mask: u32 = 0xff << offset;
2893 pub mod R {}
2894 pub mod W {}
2895 pub mod RW {}
2896 }
2897}
2898#[doc = "Message Buffer 1 WORD_64B Register"]
2899pub mod MB1_64B_WORD3 {
2900 #[doc = "Data byte 0 of Rx/Tx frame."]
2901 pub mod DATA_BYTE_15 {
2902 pub const offset: u32 = 0;
2903 pub const mask: u32 = 0xff << offset;
2904 pub mod R {}
2905 pub mod W {}
2906 pub mod RW {}
2907 }
2908 #[doc = "Data byte 1 of Rx/Tx frame."]
2909 pub mod DATA_BYTE_14 {
2910 pub const offset: u32 = 8;
2911 pub const mask: u32 = 0xff << offset;
2912 pub mod R {}
2913 pub mod W {}
2914 pub mod RW {}
2915 }
2916 #[doc = "Data byte 2 of Rx/Tx frame."]
2917 pub mod DATA_BYTE_13 {
2918 pub const offset: u32 = 16;
2919 pub const mask: u32 = 0xff << offset;
2920 pub mod R {}
2921 pub mod W {}
2922 pub mod RW {}
2923 }
2924 #[doc = "Data byte 3 of Rx/Tx frame."]
2925 pub mod DATA_BYTE_12 {
2926 pub const offset: u32 = 24;
2927 pub const mask: u32 = 0xff << offset;
2928 pub mod R {}
2929 pub mod W {}
2930 pub mod RW {}
2931 }
2932}
2933#[doc = "Message Buffer 6 CS Register"]
2934pub mod CS6 {
2935 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
2936 pub mod TIME_STAMP {
2937 pub const offset: u32 = 0;
2938 pub const mask: u32 = 0xffff << offset;
2939 pub mod R {}
2940 pub mod W {}
2941 pub mod RW {}
2942 }
2943 #[doc = "Length of the data to be stored/transmitted."]
2944 pub mod DLC {
2945 pub const offset: u32 = 16;
2946 pub const mask: u32 = 0x0f << offset;
2947 pub mod R {}
2948 pub mod W {}
2949 pub mod RW {}
2950 }
2951 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
2952 pub mod RTR {
2953 pub const offset: u32 = 20;
2954 pub const mask: u32 = 0x01 << offset;
2955 pub mod R {}
2956 pub mod W {}
2957 pub mod RW {}
2958 }
2959 #[doc = "ID Extended. One/zero for extended/standard format frame."]
2960 pub mod IDE {
2961 pub const offset: u32 = 21;
2962 pub const mask: u32 = 0x01 << offset;
2963 pub mod R {}
2964 pub mod W {}
2965 pub mod RW {}
2966 }
2967 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
2968 pub mod SRR {
2969 pub const offset: u32 = 22;
2970 pub const mask: u32 = 0x01 << offset;
2971 pub mod R {}
2972 pub mod W {}
2973 pub mod RW {}
2974 }
2975 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
2976 pub mod CODE {
2977 pub const offset: u32 = 24;
2978 pub const mask: u32 = 0x0f << offset;
2979 pub mod R {}
2980 pub mod W {}
2981 pub mod RW {}
2982 }
2983 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
2984 pub mod ESI {
2985 pub const offset: u32 = 29;
2986 pub const mask: u32 = 0x01 << offset;
2987 pub mod R {}
2988 pub mod W {}
2989 pub mod RW {}
2990 }
2991 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
2992 pub mod BRS {
2993 pub const offset: u32 = 30;
2994 pub const mask: u32 = 0x01 << offset;
2995 pub mod R {}
2996 pub mod W {}
2997 pub mod RW {}
2998 }
2999 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
3000 pub mod EDL {
3001 pub const offset: u32 = 31;
3002 pub const mask: u32 = 0x01 << offset;
3003 pub mod R {}
3004 pub mod W {}
3005 pub mod RW {}
3006 }
3007}
3008#[doc = "Message Buffer 6 ID Register"]
3009pub mod ID6 {
3010 #[doc = "Contains extended (LOW word) identifier of message buffer."]
3011 pub mod EXT {
3012 pub const offset: u32 = 0;
3013 pub const mask: u32 = 0x0003_ffff << offset;
3014 pub mod R {}
3015 pub mod W {}
3016 pub mod RW {}
3017 }
3018 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
3019 pub mod STD {
3020 pub const offset: u32 = 18;
3021 pub const mask: u32 = 0x07ff << offset;
3022 pub mod R {}
3023 pub mod W {}
3024 pub mod RW {}
3025 }
3026 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
3027 pub mod PRIO {
3028 pub const offset: u32 = 29;
3029 pub const mask: u32 = 0x07 << offset;
3030 pub mod R {}
3031 pub mod W {}
3032 pub mod RW {}
3033 }
3034}
3035#[doc = "Message Buffer 1 WORD_64B Register"]
3036pub mod MB1_64B_WORD6 {
3037 #[doc = "Data byte 0 of Rx/Tx frame."]
3038 pub mod DATA_BYTE_27 {
3039 pub const offset: u32 = 0;
3040 pub const mask: u32 = 0xff << offset;
3041 pub mod R {}
3042 pub mod W {}
3043 pub mod RW {}
3044 }
3045 #[doc = "Data byte 1 of Rx/Tx frame."]
3046 pub mod DATA_BYTE_26 {
3047 pub const offset: u32 = 8;
3048 pub const mask: u32 = 0xff << offset;
3049 pub mod R {}
3050 pub mod W {}
3051 pub mod RW {}
3052 }
3053 #[doc = "Data byte 2 of Rx/Tx frame."]
3054 pub mod DATA_BYTE_25 {
3055 pub const offset: u32 = 16;
3056 pub const mask: u32 = 0xff << offset;
3057 pub mod R {}
3058 pub mod W {}
3059 pub mod RW {}
3060 }
3061 #[doc = "Data byte 3 of Rx/Tx frame."]
3062 pub mod DATA_BYTE_24 {
3063 pub const offset: u32 = 24;
3064 pub const mask: u32 = 0xff << offset;
3065 pub mod R {}
3066 pub mod W {}
3067 pub mod RW {}
3068 }
3069}
3070#[doc = "Message Buffer 1 WORD_64B Register"]
3071pub mod MB1_64B_WORD7 {
3072 #[doc = "Data byte 0 of Rx/Tx frame."]
3073 pub mod DATA_BYTE_31 {
3074 pub const offset: u32 = 0;
3075 pub const mask: u32 = 0xff << offset;
3076 pub mod R {}
3077 pub mod W {}
3078 pub mod RW {}
3079 }
3080 #[doc = "Data byte 1 of Rx/Tx frame."]
3081 pub mod DATA_BYTE_30 {
3082 pub const offset: u32 = 8;
3083 pub const mask: u32 = 0xff << offset;
3084 pub mod R {}
3085 pub mod W {}
3086 pub mod RW {}
3087 }
3088 #[doc = "Data byte 2 of Rx/Tx frame."]
3089 pub mod DATA_BYTE_29 {
3090 pub const offset: u32 = 16;
3091 pub const mask: u32 = 0xff << offset;
3092 pub mod R {}
3093 pub mod W {}
3094 pub mod RW {}
3095 }
3096 #[doc = "Data byte 3 of Rx/Tx frame."]
3097 pub mod DATA_BYTE_28 {
3098 pub const offset: u32 = 24;
3099 pub const mask: u32 = 0xff << offset;
3100 pub mod R {}
3101 pub mod W {}
3102 pub mod RW {}
3103 }
3104}
3105#[doc = "Message Buffer 7 CS Register"]
3106pub mod CS7 {
3107 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
3108 pub mod TIME_STAMP {
3109 pub const offset: u32 = 0;
3110 pub const mask: u32 = 0xffff << offset;
3111 pub mod R {}
3112 pub mod W {}
3113 pub mod RW {}
3114 }
3115 #[doc = "Length of the data to be stored/transmitted."]
3116 pub mod DLC {
3117 pub const offset: u32 = 16;
3118 pub const mask: u32 = 0x0f << offset;
3119 pub mod R {}
3120 pub mod W {}
3121 pub mod RW {}
3122 }
3123 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
3124 pub mod RTR {
3125 pub const offset: u32 = 20;
3126 pub const mask: u32 = 0x01 << offset;
3127 pub mod R {}
3128 pub mod W {}
3129 pub mod RW {}
3130 }
3131 #[doc = "ID Extended. One/zero for extended/standard format frame."]
3132 pub mod IDE {
3133 pub const offset: u32 = 21;
3134 pub const mask: u32 = 0x01 << offset;
3135 pub mod R {}
3136 pub mod W {}
3137 pub mod RW {}
3138 }
3139 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
3140 pub mod SRR {
3141 pub const offset: u32 = 22;
3142 pub const mask: u32 = 0x01 << offset;
3143 pub mod R {}
3144 pub mod W {}
3145 pub mod RW {}
3146 }
3147 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
3148 pub mod CODE {
3149 pub const offset: u32 = 24;
3150 pub const mask: u32 = 0x0f << offset;
3151 pub mod R {}
3152 pub mod W {}
3153 pub mod RW {}
3154 }
3155 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
3156 pub mod ESI {
3157 pub const offset: u32 = 29;
3158 pub const mask: u32 = 0x01 << offset;
3159 pub mod R {}
3160 pub mod W {}
3161 pub mod RW {}
3162 }
3163 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
3164 pub mod BRS {
3165 pub const offset: u32 = 30;
3166 pub const mask: u32 = 0x01 << offset;
3167 pub mod R {}
3168 pub mod W {}
3169 pub mod RW {}
3170 }
3171 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
3172 pub mod EDL {
3173 pub const offset: u32 = 31;
3174 pub const mask: u32 = 0x01 << offset;
3175 pub mod R {}
3176 pub mod W {}
3177 pub mod RW {}
3178 }
3179}
3180#[doc = "Message Buffer 7 ID Register"]
3181pub mod ID7 {
3182 #[doc = "Contains extended (LOW word) identifier of message buffer."]
3183 pub mod EXT {
3184 pub const offset: u32 = 0;
3185 pub const mask: u32 = 0x0003_ffff << offset;
3186 pub mod R {}
3187 pub mod W {}
3188 pub mod RW {}
3189 }
3190 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
3191 pub mod STD {
3192 pub const offset: u32 = 18;
3193 pub const mask: u32 = 0x07ff << offset;
3194 pub mod R {}
3195 pub mod W {}
3196 pub mod RW {}
3197 }
3198 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
3199 pub mod PRIO {
3200 pub const offset: u32 = 29;
3201 pub const mask: u32 = 0x07 << offset;
3202 pub mod R {}
3203 pub mod W {}
3204 pub mod RW {}
3205 }
3206}
3207#[doc = "Message Buffer 1 WORD_64B Register"]
3208pub mod MB1_64B_WORD10 {
3209 #[doc = "Data byte 0 of Rx/Tx frame."]
3210 pub mod DATA_BYTE_43 {
3211 pub const offset: u32 = 0;
3212 pub const mask: u32 = 0xff << offset;
3213 pub mod R {}
3214 pub mod W {}
3215 pub mod RW {}
3216 }
3217 #[doc = "Data byte 1 of Rx/Tx frame."]
3218 pub mod DATA_BYTE_42 {
3219 pub const offset: u32 = 8;
3220 pub const mask: u32 = 0xff << offset;
3221 pub mod R {}
3222 pub mod W {}
3223 pub mod RW {}
3224 }
3225 #[doc = "Data byte 2 of Rx/Tx frame."]
3226 pub mod DATA_BYTE_41 {
3227 pub const offset: u32 = 16;
3228 pub const mask: u32 = 0xff << offset;
3229 pub mod R {}
3230 pub mod W {}
3231 pub mod RW {}
3232 }
3233 #[doc = "Data byte 3 of Rx/Tx frame."]
3234 pub mod DATA_BYTE_40 {
3235 pub const offset: u32 = 24;
3236 pub const mask: u32 = 0xff << offset;
3237 pub mod R {}
3238 pub mod W {}
3239 pub mod RW {}
3240 }
3241}
3242#[doc = "Message Buffer 1 WORD_64B Register"]
3243pub mod MB1_64B_WORD11 {
3244 #[doc = "Data byte 0 of Rx/Tx frame."]
3245 pub mod DATA_BYTE_47 {
3246 pub const offset: u32 = 0;
3247 pub const mask: u32 = 0xff << offset;
3248 pub mod R {}
3249 pub mod W {}
3250 pub mod RW {}
3251 }
3252 #[doc = "Data byte 1 of Rx/Tx frame."]
3253 pub mod DATA_BYTE_46 {
3254 pub const offset: u32 = 8;
3255 pub const mask: u32 = 0xff << offset;
3256 pub mod R {}
3257 pub mod W {}
3258 pub mod RW {}
3259 }
3260 #[doc = "Data byte 2 of Rx/Tx frame."]
3261 pub mod DATA_BYTE_45 {
3262 pub const offset: u32 = 16;
3263 pub const mask: u32 = 0xff << offset;
3264 pub mod R {}
3265 pub mod W {}
3266 pub mod RW {}
3267 }
3268 #[doc = "Data byte 3 of Rx/Tx frame."]
3269 pub mod DATA_BYTE_44 {
3270 pub const offset: u32 = 24;
3271 pub const mask: u32 = 0xff << offset;
3272 pub mod R {}
3273 pub mod W {}
3274 pub mod RW {}
3275 }
3276}
3277#[doc = "Message Buffer 8 CS Register"]
3278pub mod CS8 {
3279 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
3280 pub mod TIME_STAMP {
3281 pub const offset: u32 = 0;
3282 pub const mask: u32 = 0xffff << offset;
3283 pub mod R {}
3284 pub mod W {}
3285 pub mod RW {}
3286 }
3287 #[doc = "Length of the data to be stored/transmitted."]
3288 pub mod DLC {
3289 pub const offset: u32 = 16;
3290 pub const mask: u32 = 0x0f << offset;
3291 pub mod R {}
3292 pub mod W {}
3293 pub mod RW {}
3294 }
3295 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
3296 pub mod RTR {
3297 pub const offset: u32 = 20;
3298 pub const mask: u32 = 0x01 << offset;
3299 pub mod R {}
3300 pub mod W {}
3301 pub mod RW {}
3302 }
3303 #[doc = "ID Extended. One/zero for extended/standard format frame."]
3304 pub mod IDE {
3305 pub const offset: u32 = 21;
3306 pub const mask: u32 = 0x01 << offset;
3307 pub mod R {}
3308 pub mod W {}
3309 pub mod RW {}
3310 }
3311 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
3312 pub mod SRR {
3313 pub const offset: u32 = 22;
3314 pub const mask: u32 = 0x01 << offset;
3315 pub mod R {}
3316 pub mod W {}
3317 pub mod RW {}
3318 }
3319 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
3320 pub mod CODE {
3321 pub const offset: u32 = 24;
3322 pub const mask: u32 = 0x0f << offset;
3323 pub mod R {}
3324 pub mod W {}
3325 pub mod RW {}
3326 }
3327 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
3328 pub mod ESI {
3329 pub const offset: u32 = 29;
3330 pub const mask: u32 = 0x01 << offset;
3331 pub mod R {}
3332 pub mod W {}
3333 pub mod RW {}
3334 }
3335 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
3336 pub mod BRS {
3337 pub const offset: u32 = 30;
3338 pub const mask: u32 = 0x01 << offset;
3339 pub mod R {}
3340 pub mod W {}
3341 pub mod RW {}
3342 }
3343 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
3344 pub mod EDL {
3345 pub const offset: u32 = 31;
3346 pub const mask: u32 = 0x01 << offset;
3347 pub mod R {}
3348 pub mod W {}
3349 pub mod RW {}
3350 }
3351}
3352#[doc = "Message Buffer 8 ID Register"]
3353pub mod ID8 {
3354 #[doc = "Contains extended (LOW word) identifier of message buffer."]
3355 pub mod EXT {
3356 pub const offset: u32 = 0;
3357 pub const mask: u32 = 0x0003_ffff << offset;
3358 pub mod R {}
3359 pub mod W {}
3360 pub mod RW {}
3361 }
3362 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
3363 pub mod STD {
3364 pub const offset: u32 = 18;
3365 pub const mask: u32 = 0x07ff << offset;
3366 pub mod R {}
3367 pub mod W {}
3368 pub mod RW {}
3369 }
3370 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
3371 pub mod PRIO {
3372 pub const offset: u32 = 29;
3373 pub const mask: u32 = 0x07 << offset;
3374 pub mod R {}
3375 pub mod W {}
3376 pub mod RW {}
3377 }
3378}
3379#[doc = "Message Buffer 1 WORD_64B Register"]
3380pub mod MB1_64B_WORD14 {
3381 #[doc = "Data byte 0 of Rx/Tx frame."]
3382 pub mod DATA_BYTE_59 {
3383 pub const offset: u32 = 0;
3384 pub const mask: u32 = 0xff << offset;
3385 pub mod R {}
3386 pub mod W {}
3387 pub mod RW {}
3388 }
3389 #[doc = "Data byte 1 of Rx/Tx frame."]
3390 pub mod DATA_BYTE_58 {
3391 pub const offset: u32 = 8;
3392 pub const mask: u32 = 0xff << offset;
3393 pub mod R {}
3394 pub mod W {}
3395 pub mod RW {}
3396 }
3397 #[doc = "Data byte 2 of Rx/Tx frame."]
3398 pub mod DATA_BYTE_57 {
3399 pub const offset: u32 = 16;
3400 pub const mask: u32 = 0xff << offset;
3401 pub mod R {}
3402 pub mod W {}
3403 pub mod RW {}
3404 }
3405 #[doc = "Data byte 3 of Rx/Tx frame."]
3406 pub mod DATA_BYTE_56 {
3407 pub const offset: u32 = 24;
3408 pub const mask: u32 = 0xff << offset;
3409 pub mod R {}
3410 pub mod W {}
3411 pub mod RW {}
3412 }
3413}
3414#[doc = "Message Buffer 1 WORD_64B Register"]
3415pub mod MB1_64B_WORD15 {
3416 #[doc = "Data byte 0 of Rx/Tx frame."]
3417 pub mod DATA_BYTE_63 {
3418 pub const offset: u32 = 0;
3419 pub const mask: u32 = 0xff << offset;
3420 pub mod R {}
3421 pub mod W {}
3422 pub mod RW {}
3423 }
3424 #[doc = "Data byte 1 of Rx/Tx frame."]
3425 pub mod DATA_BYTE_62 {
3426 pub const offset: u32 = 8;
3427 pub const mask: u32 = 0xff << offset;
3428 pub mod R {}
3429 pub mod W {}
3430 pub mod RW {}
3431 }
3432 #[doc = "Data byte 2 of Rx/Tx frame."]
3433 pub mod DATA_BYTE_61 {
3434 pub const offset: u32 = 16;
3435 pub const mask: u32 = 0xff << offset;
3436 pub mod R {}
3437 pub mod W {}
3438 pub mod RW {}
3439 }
3440 #[doc = "Data byte 3 of Rx/Tx frame."]
3441 pub mod DATA_BYTE_60 {
3442 pub const offset: u32 = 24;
3443 pub const mask: u32 = 0xff << offset;
3444 pub mod R {}
3445 pub mod W {}
3446 pub mod RW {}
3447 }
3448}
3449#[doc = "Message Buffer 9 CS Register"]
3450pub mod CS9 {
3451 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
3452 pub mod TIME_STAMP {
3453 pub const offset: u32 = 0;
3454 pub const mask: u32 = 0xffff << offset;
3455 pub mod R {}
3456 pub mod W {}
3457 pub mod RW {}
3458 }
3459 #[doc = "Length of the data to be stored/transmitted."]
3460 pub mod DLC {
3461 pub const offset: u32 = 16;
3462 pub const mask: u32 = 0x0f << offset;
3463 pub mod R {}
3464 pub mod W {}
3465 pub mod RW {}
3466 }
3467 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
3468 pub mod RTR {
3469 pub const offset: u32 = 20;
3470 pub const mask: u32 = 0x01 << offset;
3471 pub mod R {}
3472 pub mod W {}
3473 pub mod RW {}
3474 }
3475 #[doc = "ID Extended. One/zero for extended/standard format frame."]
3476 pub mod IDE {
3477 pub const offset: u32 = 21;
3478 pub const mask: u32 = 0x01 << offset;
3479 pub mod R {}
3480 pub mod W {}
3481 pub mod RW {}
3482 }
3483 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
3484 pub mod SRR {
3485 pub const offset: u32 = 22;
3486 pub const mask: u32 = 0x01 << offset;
3487 pub mod R {}
3488 pub mod W {}
3489 pub mod RW {}
3490 }
3491 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
3492 pub mod CODE {
3493 pub const offset: u32 = 24;
3494 pub const mask: u32 = 0x0f << offset;
3495 pub mod R {}
3496 pub mod W {}
3497 pub mod RW {}
3498 }
3499 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
3500 pub mod ESI {
3501 pub const offset: u32 = 29;
3502 pub const mask: u32 = 0x01 << offset;
3503 pub mod R {}
3504 pub mod W {}
3505 pub mod RW {}
3506 }
3507 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
3508 pub mod BRS {
3509 pub const offset: u32 = 30;
3510 pub const mask: u32 = 0x01 << offset;
3511 pub mod R {}
3512 pub mod W {}
3513 pub mod RW {}
3514 }
3515 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
3516 pub mod EDL {
3517 pub const offset: u32 = 31;
3518 pub const mask: u32 = 0x01 << offset;
3519 pub mod R {}
3520 pub mod W {}
3521 pub mod RW {}
3522 }
3523}
3524#[doc = "Message Buffer 9 ID Register"]
3525pub mod ID9 {
3526 #[doc = "Contains extended (LOW word) identifier of message buffer."]
3527 pub mod EXT {
3528 pub const offset: u32 = 0;
3529 pub const mask: u32 = 0x0003_ffff << offset;
3530 pub mod R {}
3531 pub mod W {}
3532 pub mod RW {}
3533 }
3534 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
3535 pub mod STD {
3536 pub const offset: u32 = 18;
3537 pub const mask: u32 = 0x07ff << offset;
3538 pub mod R {}
3539 pub mod W {}
3540 pub mod RW {}
3541 }
3542 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
3543 pub mod PRIO {
3544 pub const offset: u32 = 29;
3545 pub const mask: u32 = 0x07 << offset;
3546 pub mod R {}
3547 pub mod W {}
3548 pub mod RW {}
3549 }
3550}
3551#[doc = "Message Buffer 2 WORD_64B Register"]
3552pub mod MB2_64B_WORD0 {
3553 #[doc = "Data byte 0 of Rx/Tx frame."]
3554 pub mod DATA_BYTE_3 {
3555 pub const offset: u32 = 0;
3556 pub const mask: u32 = 0xff << offset;
3557 pub mod R {}
3558 pub mod W {}
3559 pub mod RW {}
3560 }
3561 #[doc = "Data byte 1 of Rx/Tx frame."]
3562 pub mod DATA_BYTE_2 {
3563 pub const offset: u32 = 8;
3564 pub const mask: u32 = 0xff << offset;
3565 pub mod R {}
3566 pub mod W {}
3567 pub mod RW {}
3568 }
3569 #[doc = "Data byte 2 of Rx/Tx frame."]
3570 pub mod DATA_BYTE_1 {
3571 pub const offset: u32 = 16;
3572 pub const mask: u32 = 0xff << offset;
3573 pub mod R {}
3574 pub mod W {}
3575 pub mod RW {}
3576 }
3577 #[doc = "Data byte 3 of Rx/Tx frame."]
3578 pub mod DATA_BYTE_0 {
3579 pub const offset: u32 = 24;
3580 pub const mask: u32 = 0xff << offset;
3581 pub mod R {}
3582 pub mod W {}
3583 pub mod RW {}
3584 }
3585}
3586#[doc = "Message Buffer 2 WORD_64B Register"]
3587pub mod MB2_64B_WORD1 {
3588 #[doc = "Data byte 0 of Rx/Tx frame."]
3589 pub mod DATA_BYTE_7 {
3590 pub const offset: u32 = 0;
3591 pub const mask: u32 = 0xff << offset;
3592 pub mod R {}
3593 pub mod W {}
3594 pub mod RW {}
3595 }
3596 #[doc = "Data byte 1 of Rx/Tx frame."]
3597 pub mod DATA_BYTE_6 {
3598 pub const offset: u32 = 8;
3599 pub const mask: u32 = 0xff << offset;
3600 pub mod R {}
3601 pub mod W {}
3602 pub mod RW {}
3603 }
3604 #[doc = "Data byte 2 of Rx/Tx frame."]
3605 pub mod DATA_BYTE_5 {
3606 pub const offset: u32 = 16;
3607 pub const mask: u32 = 0xff << offset;
3608 pub mod R {}
3609 pub mod W {}
3610 pub mod RW {}
3611 }
3612 #[doc = "Data byte 3 of Rx/Tx frame."]
3613 pub mod DATA_BYTE_4 {
3614 pub const offset: u32 = 24;
3615 pub const mask: u32 = 0xff << offset;
3616 pub mod R {}
3617 pub mod W {}
3618 pub mod RW {}
3619 }
3620}
3621#[doc = "Message Buffer 10 CS Register"]
3622pub mod CS10 {
3623 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
3624 pub mod TIME_STAMP {
3625 pub const offset: u32 = 0;
3626 pub const mask: u32 = 0xffff << offset;
3627 pub mod R {}
3628 pub mod W {}
3629 pub mod RW {}
3630 }
3631 #[doc = "Length of the data to be stored/transmitted."]
3632 pub mod DLC {
3633 pub const offset: u32 = 16;
3634 pub const mask: u32 = 0x0f << offset;
3635 pub mod R {}
3636 pub mod W {}
3637 pub mod RW {}
3638 }
3639 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
3640 pub mod RTR {
3641 pub const offset: u32 = 20;
3642 pub const mask: u32 = 0x01 << offset;
3643 pub mod R {}
3644 pub mod W {}
3645 pub mod RW {}
3646 }
3647 #[doc = "ID Extended. One/zero for extended/standard format frame."]
3648 pub mod IDE {
3649 pub const offset: u32 = 21;
3650 pub const mask: u32 = 0x01 << offset;
3651 pub mod R {}
3652 pub mod W {}
3653 pub mod RW {}
3654 }
3655 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
3656 pub mod SRR {
3657 pub const offset: u32 = 22;
3658 pub const mask: u32 = 0x01 << offset;
3659 pub mod R {}
3660 pub mod W {}
3661 pub mod RW {}
3662 }
3663 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
3664 pub mod CODE {
3665 pub const offset: u32 = 24;
3666 pub const mask: u32 = 0x0f << offset;
3667 pub mod R {}
3668 pub mod W {}
3669 pub mod RW {}
3670 }
3671 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
3672 pub mod ESI {
3673 pub const offset: u32 = 29;
3674 pub const mask: u32 = 0x01 << offset;
3675 pub mod R {}
3676 pub mod W {}
3677 pub mod RW {}
3678 }
3679 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
3680 pub mod BRS {
3681 pub const offset: u32 = 30;
3682 pub const mask: u32 = 0x01 << offset;
3683 pub mod R {}
3684 pub mod W {}
3685 pub mod RW {}
3686 }
3687 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
3688 pub mod EDL {
3689 pub const offset: u32 = 31;
3690 pub const mask: u32 = 0x01 << offset;
3691 pub mod R {}
3692 pub mod W {}
3693 pub mod RW {}
3694 }
3695}
3696#[doc = "Message Buffer 10 ID Register"]
3697pub mod ID10 {
3698 #[doc = "Contains extended (LOW word) identifier of message buffer."]
3699 pub mod EXT {
3700 pub const offset: u32 = 0;
3701 pub const mask: u32 = 0x0003_ffff << offset;
3702 pub mod R {}
3703 pub mod W {}
3704 pub mod RW {}
3705 }
3706 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
3707 pub mod STD {
3708 pub const offset: u32 = 18;
3709 pub const mask: u32 = 0x07ff << offset;
3710 pub mod R {}
3711 pub mod W {}
3712 pub mod RW {}
3713 }
3714 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
3715 pub mod PRIO {
3716 pub const offset: u32 = 29;
3717 pub const mask: u32 = 0x07 << offset;
3718 pub mod R {}
3719 pub mod W {}
3720 pub mod RW {}
3721 }
3722}
3723#[doc = "Message Buffer 10 WORD_8B Register"]
3724pub mod MB10_8B_WORD0 {
3725 #[doc = "Data byte 0 of Rx/Tx frame."]
3726 pub mod DATA_BYTE_3 {
3727 pub const offset: u32 = 0;
3728 pub const mask: u32 = 0xff << offset;
3729 pub mod R {}
3730 pub mod W {}
3731 pub mod RW {}
3732 }
3733 #[doc = "Data byte 1 of Rx/Tx frame."]
3734 pub mod DATA_BYTE_2 {
3735 pub const offset: u32 = 8;
3736 pub const mask: u32 = 0xff << offset;
3737 pub mod R {}
3738 pub mod W {}
3739 pub mod RW {}
3740 }
3741 #[doc = "Data byte 2 of Rx/Tx frame."]
3742 pub mod DATA_BYTE_1 {
3743 pub const offset: u32 = 16;
3744 pub const mask: u32 = 0xff << offset;
3745 pub mod R {}
3746 pub mod W {}
3747 pub mod RW {}
3748 }
3749 #[doc = "Data byte 3 of Rx/Tx frame."]
3750 pub mod DATA_BYTE_0 {
3751 pub const offset: u32 = 24;
3752 pub const mask: u32 = 0xff << offset;
3753 pub mod R {}
3754 pub mod W {}
3755 pub mod RW {}
3756 }
3757}
3758#[doc = "Message Buffer 10 WORD_8B Register"]
3759pub mod MB10_8B_WORD1 {
3760 #[doc = "Data byte 0 of Rx/Tx frame."]
3761 pub mod DATA_BYTE_7 {
3762 pub const offset: u32 = 0;
3763 pub const mask: u32 = 0xff << offset;
3764 pub mod R {}
3765 pub mod W {}
3766 pub mod RW {}
3767 }
3768 #[doc = "Data byte 1 of Rx/Tx frame."]
3769 pub mod DATA_BYTE_6 {
3770 pub const offset: u32 = 8;
3771 pub const mask: u32 = 0xff << offset;
3772 pub mod R {}
3773 pub mod W {}
3774 pub mod RW {}
3775 }
3776 #[doc = "Data byte 2 of Rx/Tx frame."]
3777 pub mod DATA_BYTE_5 {
3778 pub const offset: u32 = 16;
3779 pub const mask: u32 = 0xff << offset;
3780 pub mod R {}
3781 pub mod W {}
3782 pub mod RW {}
3783 }
3784 #[doc = "Data byte 3 of Rx/Tx frame."]
3785 pub mod DATA_BYTE_4 {
3786 pub const offset: u32 = 24;
3787 pub const mask: u32 = 0xff << offset;
3788 pub mod R {}
3789 pub mod W {}
3790 pub mod RW {}
3791 }
3792}
3793#[doc = "Message Buffer 11 CS Register"]
3794pub mod CS11 {
3795 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
3796 pub mod TIME_STAMP {
3797 pub const offset: u32 = 0;
3798 pub const mask: u32 = 0xffff << offset;
3799 pub mod R {}
3800 pub mod W {}
3801 pub mod RW {}
3802 }
3803 #[doc = "Length of the data to be stored/transmitted."]
3804 pub mod DLC {
3805 pub const offset: u32 = 16;
3806 pub const mask: u32 = 0x0f << offset;
3807 pub mod R {}
3808 pub mod W {}
3809 pub mod RW {}
3810 }
3811 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
3812 pub mod RTR {
3813 pub const offset: u32 = 20;
3814 pub const mask: u32 = 0x01 << offset;
3815 pub mod R {}
3816 pub mod W {}
3817 pub mod RW {}
3818 }
3819 #[doc = "ID Extended. One/zero for extended/standard format frame."]
3820 pub mod IDE {
3821 pub const offset: u32 = 21;
3822 pub const mask: u32 = 0x01 << offset;
3823 pub mod R {}
3824 pub mod W {}
3825 pub mod RW {}
3826 }
3827 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
3828 pub mod SRR {
3829 pub const offset: u32 = 22;
3830 pub const mask: u32 = 0x01 << offset;
3831 pub mod R {}
3832 pub mod W {}
3833 pub mod RW {}
3834 }
3835 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
3836 pub mod CODE {
3837 pub const offset: u32 = 24;
3838 pub const mask: u32 = 0x0f << offset;
3839 pub mod R {}
3840 pub mod W {}
3841 pub mod RW {}
3842 }
3843 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
3844 pub mod ESI {
3845 pub const offset: u32 = 29;
3846 pub const mask: u32 = 0x01 << offset;
3847 pub mod R {}
3848 pub mod W {}
3849 pub mod RW {}
3850 }
3851 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
3852 pub mod BRS {
3853 pub const offset: u32 = 30;
3854 pub const mask: u32 = 0x01 << offset;
3855 pub mod R {}
3856 pub mod W {}
3857 pub mod RW {}
3858 }
3859 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
3860 pub mod EDL {
3861 pub const offset: u32 = 31;
3862 pub const mask: u32 = 0x01 << offset;
3863 pub mod R {}
3864 pub mod W {}
3865 pub mod RW {}
3866 }
3867}
3868#[doc = "Message Buffer 11 ID Register"]
3869pub mod ID11 {
3870 #[doc = "Contains extended (LOW word) identifier of message buffer."]
3871 pub mod EXT {
3872 pub const offset: u32 = 0;
3873 pub const mask: u32 = 0x0003_ffff << offset;
3874 pub mod R {}
3875 pub mod W {}
3876 pub mod RW {}
3877 }
3878 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
3879 pub mod STD {
3880 pub const offset: u32 = 18;
3881 pub const mask: u32 = 0x07ff << offset;
3882 pub mod R {}
3883 pub mod W {}
3884 pub mod RW {}
3885 }
3886 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
3887 pub mod PRIO {
3888 pub const offset: u32 = 29;
3889 pub const mask: u32 = 0x07 << offset;
3890 pub mod R {}
3891 pub mod W {}
3892 pub mod RW {}
3893 }
3894}
3895#[doc = "Message Buffer 11 WORD_8B Register"]
3896pub mod MB11_8B_WORD0 {
3897 #[doc = "Data byte 0 of Rx/Tx frame."]
3898 pub mod DATA_BYTE_3 {
3899 pub const offset: u32 = 0;
3900 pub const mask: u32 = 0xff << offset;
3901 pub mod R {}
3902 pub mod W {}
3903 pub mod RW {}
3904 }
3905 #[doc = "Data byte 1 of Rx/Tx frame."]
3906 pub mod DATA_BYTE_2 {
3907 pub const offset: u32 = 8;
3908 pub const mask: u32 = 0xff << offset;
3909 pub mod R {}
3910 pub mod W {}
3911 pub mod RW {}
3912 }
3913 #[doc = "Data byte 2 of Rx/Tx frame."]
3914 pub mod DATA_BYTE_1 {
3915 pub const offset: u32 = 16;
3916 pub const mask: u32 = 0xff << offset;
3917 pub mod R {}
3918 pub mod W {}
3919 pub mod RW {}
3920 }
3921 #[doc = "Data byte 3 of Rx/Tx frame."]
3922 pub mod DATA_BYTE_0 {
3923 pub const offset: u32 = 24;
3924 pub const mask: u32 = 0xff << offset;
3925 pub mod R {}
3926 pub mod W {}
3927 pub mod RW {}
3928 }
3929}
3930#[doc = "Message Buffer 11 WORD_8B Register"]
3931pub mod MB11_8B_WORD1 {
3932 #[doc = "Data byte 0 of Rx/Tx frame."]
3933 pub mod DATA_BYTE_7 {
3934 pub const offset: u32 = 0;
3935 pub const mask: u32 = 0xff << offset;
3936 pub mod R {}
3937 pub mod W {}
3938 pub mod RW {}
3939 }
3940 #[doc = "Data byte 1 of Rx/Tx frame."]
3941 pub mod DATA_BYTE_6 {
3942 pub const offset: u32 = 8;
3943 pub const mask: u32 = 0xff << offset;
3944 pub mod R {}
3945 pub mod W {}
3946 pub mod RW {}
3947 }
3948 #[doc = "Data byte 2 of Rx/Tx frame."]
3949 pub mod DATA_BYTE_5 {
3950 pub const offset: u32 = 16;
3951 pub const mask: u32 = 0xff << offset;
3952 pub mod R {}
3953 pub mod W {}
3954 pub mod RW {}
3955 }
3956 #[doc = "Data byte 3 of Rx/Tx frame."]
3957 pub mod DATA_BYTE_4 {
3958 pub const offset: u32 = 24;
3959 pub const mask: u32 = 0xff << offset;
3960 pub mod R {}
3961 pub mod W {}
3962 pub mod RW {}
3963 }
3964}
3965#[doc = "Message Buffer 12 CS Register"]
3966pub mod CS12 {
3967 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
3968 pub mod TIME_STAMP {
3969 pub const offset: u32 = 0;
3970 pub const mask: u32 = 0xffff << offset;
3971 pub mod R {}
3972 pub mod W {}
3973 pub mod RW {}
3974 }
3975 #[doc = "Length of the data to be stored/transmitted."]
3976 pub mod DLC {
3977 pub const offset: u32 = 16;
3978 pub const mask: u32 = 0x0f << offset;
3979 pub mod R {}
3980 pub mod W {}
3981 pub mod RW {}
3982 }
3983 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
3984 pub mod RTR {
3985 pub const offset: u32 = 20;
3986 pub const mask: u32 = 0x01 << offset;
3987 pub mod R {}
3988 pub mod W {}
3989 pub mod RW {}
3990 }
3991 #[doc = "ID Extended. One/zero for extended/standard format frame."]
3992 pub mod IDE {
3993 pub const offset: u32 = 21;
3994 pub const mask: u32 = 0x01 << offset;
3995 pub mod R {}
3996 pub mod W {}
3997 pub mod RW {}
3998 }
3999 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
4000 pub mod SRR {
4001 pub const offset: u32 = 22;
4002 pub const mask: u32 = 0x01 << offset;
4003 pub mod R {}
4004 pub mod W {}
4005 pub mod RW {}
4006 }
4007 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
4008 pub mod CODE {
4009 pub const offset: u32 = 24;
4010 pub const mask: u32 = 0x0f << offset;
4011 pub mod R {}
4012 pub mod W {}
4013 pub mod RW {}
4014 }
4015 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
4016 pub mod ESI {
4017 pub const offset: u32 = 29;
4018 pub const mask: u32 = 0x01 << offset;
4019 pub mod R {}
4020 pub mod W {}
4021 pub mod RW {}
4022 }
4023 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
4024 pub mod BRS {
4025 pub const offset: u32 = 30;
4026 pub const mask: u32 = 0x01 << offset;
4027 pub mod R {}
4028 pub mod W {}
4029 pub mod RW {}
4030 }
4031 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
4032 pub mod EDL {
4033 pub const offset: u32 = 31;
4034 pub const mask: u32 = 0x01 << offset;
4035 pub mod R {}
4036 pub mod W {}
4037 pub mod RW {}
4038 }
4039}
4040#[doc = "Message Buffer 12 ID Register"]
4041pub mod ID12 {
4042 #[doc = "Contains extended (LOW word) identifier of message buffer."]
4043 pub mod EXT {
4044 pub const offset: u32 = 0;
4045 pub const mask: u32 = 0x0003_ffff << offset;
4046 pub mod R {}
4047 pub mod W {}
4048 pub mod RW {}
4049 }
4050 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
4051 pub mod STD {
4052 pub const offset: u32 = 18;
4053 pub const mask: u32 = 0x07ff << offset;
4054 pub mod R {}
4055 pub mod W {}
4056 pub mod RW {}
4057 }
4058 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
4059 pub mod PRIO {
4060 pub const offset: u32 = 29;
4061 pub const mask: u32 = 0x07 << offset;
4062 pub mod R {}
4063 pub mod W {}
4064 pub mod RW {}
4065 }
4066}
4067#[doc = "Message Buffer 12 WORD_8B Register"]
4068pub mod MB12_8B_WORD0 {
4069 #[doc = "Data byte 0 of Rx/Tx frame."]
4070 pub mod DATA_BYTE_3 {
4071 pub const offset: u32 = 0;
4072 pub const mask: u32 = 0xff << offset;
4073 pub mod R {}
4074 pub mod W {}
4075 pub mod RW {}
4076 }
4077 #[doc = "Data byte 1 of Rx/Tx frame."]
4078 pub mod DATA_BYTE_2 {
4079 pub const offset: u32 = 8;
4080 pub const mask: u32 = 0xff << offset;
4081 pub mod R {}
4082 pub mod W {}
4083 pub mod RW {}
4084 }
4085 #[doc = "Data byte 2 of Rx/Tx frame."]
4086 pub mod DATA_BYTE_1 {
4087 pub const offset: u32 = 16;
4088 pub const mask: u32 = 0xff << offset;
4089 pub mod R {}
4090 pub mod W {}
4091 pub mod RW {}
4092 }
4093 #[doc = "Data byte 3 of Rx/Tx frame."]
4094 pub mod DATA_BYTE_0 {
4095 pub const offset: u32 = 24;
4096 pub const mask: u32 = 0xff << offset;
4097 pub mod R {}
4098 pub mod W {}
4099 pub mod RW {}
4100 }
4101}
4102#[doc = "Message Buffer 12 WORD_8B Register"]
4103pub mod MB12_8B_WORD1 {
4104 #[doc = "Data byte 0 of Rx/Tx frame."]
4105 pub mod DATA_BYTE_7 {
4106 pub const offset: u32 = 0;
4107 pub const mask: u32 = 0xff << offset;
4108 pub mod R {}
4109 pub mod W {}
4110 pub mod RW {}
4111 }
4112 #[doc = "Data byte 1 of Rx/Tx frame."]
4113 pub mod DATA_BYTE_6 {
4114 pub const offset: u32 = 8;
4115 pub const mask: u32 = 0xff << offset;
4116 pub mod R {}
4117 pub mod W {}
4118 pub mod RW {}
4119 }
4120 #[doc = "Data byte 2 of Rx/Tx frame."]
4121 pub mod DATA_BYTE_5 {
4122 pub const offset: u32 = 16;
4123 pub const mask: u32 = 0xff << offset;
4124 pub mod R {}
4125 pub mod W {}
4126 pub mod RW {}
4127 }
4128 #[doc = "Data byte 3 of Rx/Tx frame."]
4129 pub mod DATA_BYTE_4 {
4130 pub const offset: u32 = 24;
4131 pub const mask: u32 = 0xff << offset;
4132 pub mod R {}
4133 pub mod W {}
4134 pub mod RW {}
4135 }
4136}
4137#[doc = "Message Buffer 13 CS Register"]
4138pub mod CS13 {
4139 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
4140 pub mod TIME_STAMP {
4141 pub const offset: u32 = 0;
4142 pub const mask: u32 = 0xffff << offset;
4143 pub mod R {}
4144 pub mod W {}
4145 pub mod RW {}
4146 }
4147 #[doc = "Length of the data to be stored/transmitted."]
4148 pub mod DLC {
4149 pub const offset: u32 = 16;
4150 pub const mask: u32 = 0x0f << offset;
4151 pub mod R {}
4152 pub mod W {}
4153 pub mod RW {}
4154 }
4155 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
4156 pub mod RTR {
4157 pub const offset: u32 = 20;
4158 pub const mask: u32 = 0x01 << offset;
4159 pub mod R {}
4160 pub mod W {}
4161 pub mod RW {}
4162 }
4163 #[doc = "ID Extended. One/zero for extended/standard format frame."]
4164 pub mod IDE {
4165 pub const offset: u32 = 21;
4166 pub const mask: u32 = 0x01 << offset;
4167 pub mod R {}
4168 pub mod W {}
4169 pub mod RW {}
4170 }
4171 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
4172 pub mod SRR {
4173 pub const offset: u32 = 22;
4174 pub const mask: u32 = 0x01 << offset;
4175 pub mod R {}
4176 pub mod W {}
4177 pub mod RW {}
4178 }
4179 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
4180 pub mod CODE {
4181 pub const offset: u32 = 24;
4182 pub const mask: u32 = 0x0f << offset;
4183 pub mod R {}
4184 pub mod W {}
4185 pub mod RW {}
4186 }
4187 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
4188 pub mod ESI {
4189 pub const offset: u32 = 29;
4190 pub const mask: u32 = 0x01 << offset;
4191 pub mod R {}
4192 pub mod W {}
4193 pub mod RW {}
4194 }
4195 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
4196 pub mod BRS {
4197 pub const offset: u32 = 30;
4198 pub const mask: u32 = 0x01 << offset;
4199 pub mod R {}
4200 pub mod W {}
4201 pub mod RW {}
4202 }
4203 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
4204 pub mod EDL {
4205 pub const offset: u32 = 31;
4206 pub const mask: u32 = 0x01 << offset;
4207 pub mod R {}
4208 pub mod W {}
4209 pub mod RW {}
4210 }
4211}
4212#[doc = "Message Buffer 13 ID Register"]
4213pub mod ID13 {
4214 #[doc = "Contains extended (LOW word) identifier of message buffer."]
4215 pub mod EXT {
4216 pub const offset: u32 = 0;
4217 pub const mask: u32 = 0x0003_ffff << offset;
4218 pub mod R {}
4219 pub mod W {}
4220 pub mod RW {}
4221 }
4222 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
4223 pub mod STD {
4224 pub const offset: u32 = 18;
4225 pub const mask: u32 = 0x07ff << offset;
4226 pub mod R {}
4227 pub mod W {}
4228 pub mod RW {}
4229 }
4230 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
4231 pub mod PRIO {
4232 pub const offset: u32 = 29;
4233 pub const mask: u32 = 0x07 << offset;
4234 pub mod R {}
4235 pub mod W {}
4236 pub mod RW {}
4237 }
4238}
4239#[doc = "Message Buffer 13 WORD_8B Register"]
4240pub mod MB13_8B_WORD0 {
4241 #[doc = "Data byte 0 of Rx/Tx frame."]
4242 pub mod DATA_BYTE_3 {
4243 pub const offset: u32 = 0;
4244 pub const mask: u32 = 0xff << offset;
4245 pub mod R {}
4246 pub mod W {}
4247 pub mod RW {}
4248 }
4249 #[doc = "Data byte 1 of Rx/Tx frame."]
4250 pub mod DATA_BYTE_2 {
4251 pub const offset: u32 = 8;
4252 pub const mask: u32 = 0xff << offset;
4253 pub mod R {}
4254 pub mod W {}
4255 pub mod RW {}
4256 }
4257 #[doc = "Data byte 2 of Rx/Tx frame."]
4258 pub mod DATA_BYTE_1 {
4259 pub const offset: u32 = 16;
4260 pub const mask: u32 = 0xff << offset;
4261 pub mod R {}
4262 pub mod W {}
4263 pub mod RW {}
4264 }
4265 #[doc = "Data byte 3 of Rx/Tx frame."]
4266 pub mod DATA_BYTE_0 {
4267 pub const offset: u32 = 24;
4268 pub const mask: u32 = 0xff << offset;
4269 pub mod R {}
4270 pub mod W {}
4271 pub mod RW {}
4272 }
4273}
4274#[doc = "Message Buffer 13 WORD_8B Register"]
4275pub mod MB13_8B_WORD1 {
4276 #[doc = "Data byte 0 of Rx/Tx frame."]
4277 pub mod DATA_BYTE_7 {
4278 pub const offset: u32 = 0;
4279 pub const mask: u32 = 0xff << offset;
4280 pub mod R {}
4281 pub mod W {}
4282 pub mod RW {}
4283 }
4284 #[doc = "Data byte 1 of Rx/Tx frame."]
4285 pub mod DATA_BYTE_6 {
4286 pub const offset: u32 = 8;
4287 pub const mask: u32 = 0xff << offset;
4288 pub mod R {}
4289 pub mod W {}
4290 pub mod RW {}
4291 }
4292 #[doc = "Data byte 2 of Rx/Tx frame."]
4293 pub mod DATA_BYTE_5 {
4294 pub const offset: u32 = 16;
4295 pub const mask: u32 = 0xff << offset;
4296 pub mod R {}
4297 pub mod W {}
4298 pub mod RW {}
4299 }
4300 #[doc = "Data byte 3 of Rx/Tx frame."]
4301 pub mod DATA_BYTE_4 {
4302 pub const offset: u32 = 24;
4303 pub const mask: u32 = 0xff << offset;
4304 pub mod R {}
4305 pub mod W {}
4306 pub mod RW {}
4307 }
4308}
4309#[doc = "Message Buffer 14 CS Register"]
4310pub mod CS14 {
4311 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
4312 pub mod TIME_STAMP {
4313 pub const offset: u32 = 0;
4314 pub const mask: u32 = 0xffff << offset;
4315 pub mod R {}
4316 pub mod W {}
4317 pub mod RW {}
4318 }
4319 #[doc = "Length of the data to be stored/transmitted."]
4320 pub mod DLC {
4321 pub const offset: u32 = 16;
4322 pub const mask: u32 = 0x0f << offset;
4323 pub mod R {}
4324 pub mod W {}
4325 pub mod RW {}
4326 }
4327 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
4328 pub mod RTR {
4329 pub const offset: u32 = 20;
4330 pub const mask: u32 = 0x01 << offset;
4331 pub mod R {}
4332 pub mod W {}
4333 pub mod RW {}
4334 }
4335 #[doc = "ID Extended. One/zero for extended/standard format frame."]
4336 pub mod IDE {
4337 pub const offset: u32 = 21;
4338 pub const mask: u32 = 0x01 << offset;
4339 pub mod R {}
4340 pub mod W {}
4341 pub mod RW {}
4342 }
4343 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
4344 pub mod SRR {
4345 pub const offset: u32 = 22;
4346 pub const mask: u32 = 0x01 << offset;
4347 pub mod R {}
4348 pub mod W {}
4349 pub mod RW {}
4350 }
4351 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
4352 pub mod CODE {
4353 pub const offset: u32 = 24;
4354 pub const mask: u32 = 0x0f << offset;
4355 pub mod R {}
4356 pub mod W {}
4357 pub mod RW {}
4358 }
4359 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
4360 pub mod ESI {
4361 pub const offset: u32 = 29;
4362 pub const mask: u32 = 0x01 << offset;
4363 pub mod R {}
4364 pub mod W {}
4365 pub mod RW {}
4366 }
4367 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
4368 pub mod BRS {
4369 pub const offset: u32 = 30;
4370 pub const mask: u32 = 0x01 << offset;
4371 pub mod R {}
4372 pub mod W {}
4373 pub mod RW {}
4374 }
4375 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
4376 pub mod EDL {
4377 pub const offset: u32 = 31;
4378 pub const mask: u32 = 0x01 << offset;
4379 pub mod R {}
4380 pub mod W {}
4381 pub mod RW {}
4382 }
4383}
4384#[doc = "Message Buffer 14 ID Register"]
4385pub mod ID14 {
4386 #[doc = "Contains extended (LOW word) identifier of message buffer."]
4387 pub mod EXT {
4388 pub const offset: u32 = 0;
4389 pub const mask: u32 = 0x0003_ffff << offset;
4390 pub mod R {}
4391 pub mod W {}
4392 pub mod RW {}
4393 }
4394 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
4395 pub mod STD {
4396 pub const offset: u32 = 18;
4397 pub const mask: u32 = 0x07ff << offset;
4398 pub mod R {}
4399 pub mod W {}
4400 pub mod RW {}
4401 }
4402 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
4403 pub mod PRIO {
4404 pub const offset: u32 = 29;
4405 pub const mask: u32 = 0x07 << offset;
4406 pub mod R {}
4407 pub mod W {}
4408 pub mod RW {}
4409 }
4410}
4411#[doc = "Message Buffer 14 WORD_8B Register"]
4412pub mod MB14_8B_WORD0 {
4413 #[doc = "Data byte 0 of Rx/Tx frame."]
4414 pub mod DATA_BYTE_3 {
4415 pub const offset: u32 = 0;
4416 pub const mask: u32 = 0xff << offset;
4417 pub mod R {}
4418 pub mod W {}
4419 pub mod RW {}
4420 }
4421 #[doc = "Data byte 1 of Rx/Tx frame."]
4422 pub mod DATA_BYTE_2 {
4423 pub const offset: u32 = 8;
4424 pub const mask: u32 = 0xff << offset;
4425 pub mod R {}
4426 pub mod W {}
4427 pub mod RW {}
4428 }
4429 #[doc = "Data byte 2 of Rx/Tx frame."]
4430 pub mod DATA_BYTE_1 {
4431 pub const offset: u32 = 16;
4432 pub const mask: u32 = 0xff << offset;
4433 pub mod R {}
4434 pub mod W {}
4435 pub mod RW {}
4436 }
4437 #[doc = "Data byte 3 of Rx/Tx frame."]
4438 pub mod DATA_BYTE_0 {
4439 pub const offset: u32 = 24;
4440 pub const mask: u32 = 0xff << offset;
4441 pub mod R {}
4442 pub mod W {}
4443 pub mod RW {}
4444 }
4445}
4446#[doc = "Message Buffer 14 WORD_8B Register"]
4447pub mod MB14_8B_WORD1 {
4448 #[doc = "Data byte 0 of Rx/Tx frame."]
4449 pub mod DATA_BYTE_7 {
4450 pub const offset: u32 = 0;
4451 pub const mask: u32 = 0xff << offset;
4452 pub mod R {}
4453 pub mod W {}
4454 pub mod RW {}
4455 }
4456 #[doc = "Data byte 1 of Rx/Tx frame."]
4457 pub mod DATA_BYTE_6 {
4458 pub const offset: u32 = 8;
4459 pub const mask: u32 = 0xff << offset;
4460 pub mod R {}
4461 pub mod W {}
4462 pub mod RW {}
4463 }
4464 #[doc = "Data byte 2 of Rx/Tx frame."]
4465 pub mod DATA_BYTE_5 {
4466 pub const offset: u32 = 16;
4467 pub const mask: u32 = 0xff << offset;
4468 pub mod R {}
4469 pub mod W {}
4470 pub mod RW {}
4471 }
4472 #[doc = "Data byte 3 of Rx/Tx frame."]
4473 pub mod DATA_BYTE_4 {
4474 pub const offset: u32 = 24;
4475 pub const mask: u32 = 0xff << offset;
4476 pub mod R {}
4477 pub mod W {}
4478 pub mod RW {}
4479 }
4480}
4481#[doc = "Message Buffer 15 CS Register"]
4482pub mod CS15 {
4483 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
4484 pub mod TIME_STAMP {
4485 pub const offset: u32 = 0;
4486 pub const mask: u32 = 0xffff << offset;
4487 pub mod R {}
4488 pub mod W {}
4489 pub mod RW {}
4490 }
4491 #[doc = "Length of the data to be stored/transmitted."]
4492 pub mod DLC {
4493 pub const offset: u32 = 16;
4494 pub const mask: u32 = 0x0f << offset;
4495 pub mod R {}
4496 pub mod W {}
4497 pub mod RW {}
4498 }
4499 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
4500 pub mod RTR {
4501 pub const offset: u32 = 20;
4502 pub const mask: u32 = 0x01 << offset;
4503 pub mod R {}
4504 pub mod W {}
4505 pub mod RW {}
4506 }
4507 #[doc = "ID Extended. One/zero for extended/standard format frame."]
4508 pub mod IDE {
4509 pub const offset: u32 = 21;
4510 pub const mask: u32 = 0x01 << offset;
4511 pub mod R {}
4512 pub mod W {}
4513 pub mod RW {}
4514 }
4515 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
4516 pub mod SRR {
4517 pub const offset: u32 = 22;
4518 pub const mask: u32 = 0x01 << offset;
4519 pub mod R {}
4520 pub mod W {}
4521 pub mod RW {}
4522 }
4523 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
4524 pub mod CODE {
4525 pub const offset: u32 = 24;
4526 pub const mask: u32 = 0x0f << offset;
4527 pub mod R {}
4528 pub mod W {}
4529 pub mod RW {}
4530 }
4531 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
4532 pub mod ESI {
4533 pub const offset: u32 = 29;
4534 pub const mask: u32 = 0x01 << offset;
4535 pub mod R {}
4536 pub mod W {}
4537 pub mod RW {}
4538 }
4539 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
4540 pub mod BRS {
4541 pub const offset: u32 = 30;
4542 pub const mask: u32 = 0x01 << offset;
4543 pub mod R {}
4544 pub mod W {}
4545 pub mod RW {}
4546 }
4547 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
4548 pub mod EDL {
4549 pub const offset: u32 = 31;
4550 pub const mask: u32 = 0x01 << offset;
4551 pub mod R {}
4552 pub mod W {}
4553 pub mod RW {}
4554 }
4555}
4556#[doc = "Message Buffer 15 ID Register"]
4557pub mod ID15 {
4558 #[doc = "Contains extended (LOW word) identifier of message buffer."]
4559 pub mod EXT {
4560 pub const offset: u32 = 0;
4561 pub const mask: u32 = 0x0003_ffff << offset;
4562 pub mod R {}
4563 pub mod W {}
4564 pub mod RW {}
4565 }
4566 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
4567 pub mod STD {
4568 pub const offset: u32 = 18;
4569 pub const mask: u32 = 0x07ff << offset;
4570 pub mod R {}
4571 pub mod W {}
4572 pub mod RW {}
4573 }
4574 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
4575 pub mod PRIO {
4576 pub const offset: u32 = 29;
4577 pub const mask: u32 = 0x07 << offset;
4578 pub mod R {}
4579 pub mod W {}
4580 pub mod RW {}
4581 }
4582}
4583#[doc = "Message Buffer 10 WORD_16B Register"]
4584pub mod MB10_16B_WORD0 {
4585 #[doc = "Data byte 0 of Rx/Tx frame."]
4586 pub mod DATA_BYTE_3 {
4587 pub const offset: u32 = 0;
4588 pub const mask: u32 = 0xff << offset;
4589 pub mod R {}
4590 pub mod W {}
4591 pub mod RW {}
4592 }
4593 #[doc = "Data byte 1 of Rx/Tx frame."]
4594 pub mod DATA_BYTE_2 {
4595 pub const offset: u32 = 8;
4596 pub const mask: u32 = 0xff << offset;
4597 pub mod R {}
4598 pub mod W {}
4599 pub mod RW {}
4600 }
4601 #[doc = "Data byte 2 of Rx/Tx frame."]
4602 pub mod DATA_BYTE_1 {
4603 pub const offset: u32 = 16;
4604 pub const mask: u32 = 0xff << offset;
4605 pub mod R {}
4606 pub mod W {}
4607 pub mod RW {}
4608 }
4609 #[doc = "Data byte 3 of Rx/Tx frame."]
4610 pub mod DATA_BYTE_0 {
4611 pub const offset: u32 = 24;
4612 pub const mask: u32 = 0xff << offset;
4613 pub mod R {}
4614 pub mod W {}
4615 pub mod RW {}
4616 }
4617}
4618#[doc = "Message Buffer 10 WORD_16B Register"]
4619pub mod MB10_16B_WORD1 {
4620 #[doc = "Data byte 0 of Rx/Tx frame."]
4621 pub mod DATA_BYTE_7 {
4622 pub const offset: u32 = 0;
4623 pub const mask: u32 = 0xff << offset;
4624 pub mod R {}
4625 pub mod W {}
4626 pub mod RW {}
4627 }
4628 #[doc = "Data byte 1 of Rx/Tx frame."]
4629 pub mod DATA_BYTE_6 {
4630 pub const offset: u32 = 8;
4631 pub const mask: u32 = 0xff << offset;
4632 pub mod R {}
4633 pub mod W {}
4634 pub mod RW {}
4635 }
4636 #[doc = "Data byte 2 of Rx/Tx frame."]
4637 pub mod DATA_BYTE_5 {
4638 pub const offset: u32 = 16;
4639 pub const mask: u32 = 0xff << offset;
4640 pub mod R {}
4641 pub mod W {}
4642 pub mod RW {}
4643 }
4644 #[doc = "Data byte 3 of Rx/Tx frame."]
4645 pub mod DATA_BYTE_4 {
4646 pub const offset: u32 = 24;
4647 pub const mask: u32 = 0xff << offset;
4648 pub mod R {}
4649 pub mod W {}
4650 pub mod RW {}
4651 }
4652}
4653#[doc = "Message Buffer 16 CS Register"]
4654pub mod CS16 {
4655 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
4656 pub mod TIME_STAMP {
4657 pub const offset: u32 = 0;
4658 pub const mask: u32 = 0xffff << offset;
4659 pub mod R {}
4660 pub mod W {}
4661 pub mod RW {}
4662 }
4663 #[doc = "Length of the data to be stored/transmitted."]
4664 pub mod DLC {
4665 pub const offset: u32 = 16;
4666 pub const mask: u32 = 0x0f << offset;
4667 pub mod R {}
4668 pub mod W {}
4669 pub mod RW {}
4670 }
4671 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
4672 pub mod RTR {
4673 pub const offset: u32 = 20;
4674 pub const mask: u32 = 0x01 << offset;
4675 pub mod R {}
4676 pub mod W {}
4677 pub mod RW {}
4678 }
4679 #[doc = "ID Extended. One/zero for extended/standard format frame."]
4680 pub mod IDE {
4681 pub const offset: u32 = 21;
4682 pub const mask: u32 = 0x01 << offset;
4683 pub mod R {}
4684 pub mod W {}
4685 pub mod RW {}
4686 }
4687 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
4688 pub mod SRR {
4689 pub const offset: u32 = 22;
4690 pub const mask: u32 = 0x01 << offset;
4691 pub mod R {}
4692 pub mod W {}
4693 pub mod RW {}
4694 }
4695 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
4696 pub mod CODE {
4697 pub const offset: u32 = 24;
4698 pub const mask: u32 = 0x0f << offset;
4699 pub mod R {}
4700 pub mod W {}
4701 pub mod RW {}
4702 }
4703 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
4704 pub mod ESI {
4705 pub const offset: u32 = 29;
4706 pub const mask: u32 = 0x01 << offset;
4707 pub mod R {}
4708 pub mod W {}
4709 pub mod RW {}
4710 }
4711 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
4712 pub mod BRS {
4713 pub const offset: u32 = 30;
4714 pub const mask: u32 = 0x01 << offset;
4715 pub mod R {}
4716 pub mod W {}
4717 pub mod RW {}
4718 }
4719 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
4720 pub mod EDL {
4721 pub const offset: u32 = 31;
4722 pub const mask: u32 = 0x01 << offset;
4723 pub mod R {}
4724 pub mod W {}
4725 pub mod RW {}
4726 }
4727}
4728#[doc = "Message Buffer 16 ID Register"]
4729pub mod ID16 {
4730 #[doc = "Contains extended (LOW word) identifier of message buffer."]
4731 pub mod EXT {
4732 pub const offset: u32 = 0;
4733 pub const mask: u32 = 0x0003_ffff << offset;
4734 pub mod R {}
4735 pub mod W {}
4736 pub mod RW {}
4737 }
4738 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
4739 pub mod STD {
4740 pub const offset: u32 = 18;
4741 pub const mask: u32 = 0x07ff << offset;
4742 pub mod R {}
4743 pub mod W {}
4744 pub mod RW {}
4745 }
4746 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
4747 pub mod PRIO {
4748 pub const offset: u32 = 29;
4749 pub const mask: u32 = 0x07 << offset;
4750 pub mod R {}
4751 pub mod W {}
4752 pub mod RW {}
4753 }
4754}
4755#[doc = "Message Buffer 11 CS Register"]
4756pub mod MB11_16B_CS {
4757 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
4758 pub mod TIME_STAMP {
4759 pub const offset: u32 = 0;
4760 pub const mask: u32 = 0xffff << offset;
4761 pub mod R {}
4762 pub mod W {}
4763 pub mod RW {}
4764 }
4765 #[doc = "Length of the data to be stored/transmitted."]
4766 pub mod DLC {
4767 pub const offset: u32 = 16;
4768 pub const mask: u32 = 0x0f << offset;
4769 pub mod R {}
4770 pub mod W {}
4771 pub mod RW {}
4772 }
4773 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
4774 pub mod RTR {
4775 pub const offset: u32 = 20;
4776 pub const mask: u32 = 0x01 << offset;
4777 pub mod R {}
4778 pub mod W {}
4779 pub mod RW {}
4780 }
4781 #[doc = "ID Extended. One/zero for extended/standard format frame."]
4782 pub mod IDE {
4783 pub const offset: u32 = 21;
4784 pub const mask: u32 = 0x01 << offset;
4785 pub mod R {}
4786 pub mod W {}
4787 pub mod RW {}
4788 }
4789 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
4790 pub mod SRR {
4791 pub const offset: u32 = 22;
4792 pub const mask: u32 = 0x01 << offset;
4793 pub mod R {}
4794 pub mod W {}
4795 pub mod RW {}
4796 }
4797 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
4798 pub mod CODE {
4799 pub const offset: u32 = 24;
4800 pub const mask: u32 = 0x0f << offset;
4801 pub mod R {}
4802 pub mod W {}
4803 pub mod RW {}
4804 }
4805 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
4806 pub mod ESI {
4807 pub const offset: u32 = 29;
4808 pub const mask: u32 = 0x01 << offset;
4809 pub mod R {}
4810 pub mod W {}
4811 pub mod RW {}
4812 }
4813 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
4814 pub mod BRS {
4815 pub const offset: u32 = 30;
4816 pub const mask: u32 = 0x01 << offset;
4817 pub mod R {}
4818 pub mod W {}
4819 pub mod RW {}
4820 }
4821 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
4822 pub mod EDL {
4823 pub const offset: u32 = 31;
4824 pub const mask: u32 = 0x01 << offset;
4825 pub mod R {}
4826 pub mod W {}
4827 pub mod RW {}
4828 }
4829}
4830#[doc = "Message Buffer 11 ID Register"]
4831pub mod MB11_16B_ID {
4832 #[doc = "Contains extended (LOW word) identifier of message buffer."]
4833 pub mod EXT {
4834 pub const offset: u32 = 0;
4835 pub const mask: u32 = 0x0003_ffff << offset;
4836 pub mod R {}
4837 pub mod W {}
4838 pub mod RW {}
4839 }
4840 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
4841 pub mod STD {
4842 pub const offset: u32 = 18;
4843 pub const mask: u32 = 0x07ff << offset;
4844 pub mod R {}
4845 pub mod W {}
4846 pub mod RW {}
4847 }
4848 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
4849 pub mod PRIO {
4850 pub const offset: u32 = 29;
4851 pub const mask: u32 = 0x07 << offset;
4852 pub mod R {}
4853 pub mod W {}
4854 pub mod RW {}
4855 }
4856}
4857#[doc = "Message Buffer 17 CS Register"]
4858pub mod CS17 {
4859 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
4860 pub mod TIME_STAMP {
4861 pub const offset: u32 = 0;
4862 pub const mask: u32 = 0xffff << offset;
4863 pub mod R {}
4864 pub mod W {}
4865 pub mod RW {}
4866 }
4867 #[doc = "Length of the data to be stored/transmitted."]
4868 pub mod DLC {
4869 pub const offset: u32 = 16;
4870 pub const mask: u32 = 0x0f << offset;
4871 pub mod R {}
4872 pub mod W {}
4873 pub mod RW {}
4874 }
4875 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
4876 pub mod RTR {
4877 pub const offset: u32 = 20;
4878 pub const mask: u32 = 0x01 << offset;
4879 pub mod R {}
4880 pub mod W {}
4881 pub mod RW {}
4882 }
4883 #[doc = "ID Extended. One/zero for extended/standard format frame."]
4884 pub mod IDE {
4885 pub const offset: u32 = 21;
4886 pub const mask: u32 = 0x01 << offset;
4887 pub mod R {}
4888 pub mod W {}
4889 pub mod RW {}
4890 }
4891 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
4892 pub mod SRR {
4893 pub const offset: u32 = 22;
4894 pub const mask: u32 = 0x01 << offset;
4895 pub mod R {}
4896 pub mod W {}
4897 pub mod RW {}
4898 }
4899 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
4900 pub mod CODE {
4901 pub const offset: u32 = 24;
4902 pub const mask: u32 = 0x0f << offset;
4903 pub mod R {}
4904 pub mod W {}
4905 pub mod RW {}
4906 }
4907 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
4908 pub mod ESI {
4909 pub const offset: u32 = 29;
4910 pub const mask: u32 = 0x01 << offset;
4911 pub mod R {}
4912 pub mod W {}
4913 pub mod RW {}
4914 }
4915 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
4916 pub mod BRS {
4917 pub const offset: u32 = 30;
4918 pub const mask: u32 = 0x01 << offset;
4919 pub mod R {}
4920 pub mod W {}
4921 pub mod RW {}
4922 }
4923 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
4924 pub mod EDL {
4925 pub const offset: u32 = 31;
4926 pub const mask: u32 = 0x01 << offset;
4927 pub mod R {}
4928 pub mod W {}
4929 pub mod RW {}
4930 }
4931}
4932#[doc = "Message Buffer 17 ID Register"]
4933pub mod ID17 {
4934 #[doc = "Contains extended (LOW word) identifier of message buffer."]
4935 pub mod EXT {
4936 pub const offset: u32 = 0;
4937 pub const mask: u32 = 0x0003_ffff << offset;
4938 pub mod R {}
4939 pub mod W {}
4940 pub mod RW {}
4941 }
4942 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
4943 pub mod STD {
4944 pub const offset: u32 = 18;
4945 pub const mask: u32 = 0x07ff << offset;
4946 pub mod R {}
4947 pub mod W {}
4948 pub mod RW {}
4949 }
4950 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
4951 pub mod PRIO {
4952 pub const offset: u32 = 29;
4953 pub const mask: u32 = 0x07 << offset;
4954 pub mod R {}
4955 pub mod W {}
4956 pub mod RW {}
4957 }
4958}
4959#[doc = "Message Buffer 11 WORD_16B Register"]
4960pub mod MB11_16B_WORD2 {
4961 #[doc = "Data byte 0 of Rx/Tx frame."]
4962 pub mod DATA_BYTE_11 {
4963 pub const offset: u32 = 0;
4964 pub const mask: u32 = 0xff << offset;
4965 pub mod R {}
4966 pub mod W {}
4967 pub mod RW {}
4968 }
4969 #[doc = "Data byte 1 of Rx/Tx frame."]
4970 pub mod DATA_BYTE_10 {
4971 pub const offset: u32 = 8;
4972 pub const mask: u32 = 0xff << offset;
4973 pub mod R {}
4974 pub mod W {}
4975 pub mod RW {}
4976 }
4977 #[doc = "Data byte 2 of Rx/Tx frame."]
4978 pub mod DATA_BYTE_9 {
4979 pub const offset: u32 = 16;
4980 pub const mask: u32 = 0xff << offset;
4981 pub mod R {}
4982 pub mod W {}
4983 pub mod RW {}
4984 }
4985 #[doc = "Data byte 3 of Rx/Tx frame."]
4986 pub mod DATA_BYTE_8 {
4987 pub const offset: u32 = 24;
4988 pub const mask: u32 = 0xff << offset;
4989 pub mod R {}
4990 pub mod W {}
4991 pub mod RW {}
4992 }
4993}
4994#[doc = "Message Buffer 11 WORD_16B Register"]
4995pub mod MB11_16B_WORD3 {
4996 #[doc = "Data byte 0 of Rx/Tx frame."]
4997 pub mod DATA_BYTE_15 {
4998 pub const offset: u32 = 0;
4999 pub const mask: u32 = 0xff << offset;
5000 pub mod R {}
5001 pub mod W {}
5002 pub mod RW {}
5003 }
5004 #[doc = "Data byte 1 of Rx/Tx frame."]
5005 pub mod DATA_BYTE_14 {
5006 pub const offset: u32 = 8;
5007 pub const mask: u32 = 0xff << offset;
5008 pub mod R {}
5009 pub mod W {}
5010 pub mod RW {}
5011 }
5012 #[doc = "Data byte 2 of Rx/Tx frame."]
5013 pub mod DATA_BYTE_13 {
5014 pub const offset: u32 = 16;
5015 pub const mask: u32 = 0xff << offset;
5016 pub mod R {}
5017 pub mod W {}
5018 pub mod RW {}
5019 }
5020 #[doc = "Data byte 3 of Rx/Tx frame."]
5021 pub mod DATA_BYTE_12 {
5022 pub const offset: u32 = 24;
5023 pub const mask: u32 = 0xff << offset;
5024 pub mod R {}
5025 pub mod W {}
5026 pub mod RW {}
5027 }
5028}
5029#[doc = "Message Buffer 18 CS Register"]
5030pub mod CS18 {
5031 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
5032 pub mod TIME_STAMP {
5033 pub const offset: u32 = 0;
5034 pub const mask: u32 = 0xffff << offset;
5035 pub mod R {}
5036 pub mod W {}
5037 pub mod RW {}
5038 }
5039 #[doc = "Length of the data to be stored/transmitted."]
5040 pub mod DLC {
5041 pub const offset: u32 = 16;
5042 pub const mask: u32 = 0x0f << offset;
5043 pub mod R {}
5044 pub mod W {}
5045 pub mod RW {}
5046 }
5047 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
5048 pub mod RTR {
5049 pub const offset: u32 = 20;
5050 pub const mask: u32 = 0x01 << offset;
5051 pub mod R {}
5052 pub mod W {}
5053 pub mod RW {}
5054 }
5055 #[doc = "ID Extended. One/zero for extended/standard format frame."]
5056 pub mod IDE {
5057 pub const offset: u32 = 21;
5058 pub const mask: u32 = 0x01 << offset;
5059 pub mod R {}
5060 pub mod W {}
5061 pub mod RW {}
5062 }
5063 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
5064 pub mod SRR {
5065 pub const offset: u32 = 22;
5066 pub const mask: u32 = 0x01 << offset;
5067 pub mod R {}
5068 pub mod W {}
5069 pub mod RW {}
5070 }
5071 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
5072 pub mod CODE {
5073 pub const offset: u32 = 24;
5074 pub const mask: u32 = 0x0f << offset;
5075 pub mod R {}
5076 pub mod W {}
5077 pub mod RW {}
5078 }
5079 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
5080 pub mod ESI {
5081 pub const offset: u32 = 29;
5082 pub const mask: u32 = 0x01 << offset;
5083 pub mod R {}
5084 pub mod W {}
5085 pub mod RW {}
5086 }
5087 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
5088 pub mod BRS {
5089 pub const offset: u32 = 30;
5090 pub const mask: u32 = 0x01 << offset;
5091 pub mod R {}
5092 pub mod W {}
5093 pub mod RW {}
5094 }
5095 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
5096 pub mod EDL {
5097 pub const offset: u32 = 31;
5098 pub const mask: u32 = 0x01 << offset;
5099 pub mod R {}
5100 pub mod W {}
5101 pub mod RW {}
5102 }
5103}
5104#[doc = "Message Buffer 18 ID Register"]
5105pub mod ID18 {
5106 #[doc = "Contains extended (LOW word) identifier of message buffer."]
5107 pub mod EXT {
5108 pub const offset: u32 = 0;
5109 pub const mask: u32 = 0x0003_ffff << offset;
5110 pub mod R {}
5111 pub mod W {}
5112 pub mod RW {}
5113 }
5114 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
5115 pub mod STD {
5116 pub const offset: u32 = 18;
5117 pub const mask: u32 = 0x07ff << offset;
5118 pub mod R {}
5119 pub mod W {}
5120 pub mod RW {}
5121 }
5122 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
5123 pub mod PRIO {
5124 pub const offset: u32 = 29;
5125 pub const mask: u32 = 0x07 << offset;
5126 pub mod R {}
5127 pub mod W {}
5128 pub mod RW {}
5129 }
5130}
5131#[doc = "Message Buffer 12 WORD_16B Register"]
5132pub mod MB12_16B_WORD0 {
5133 #[doc = "Data byte 0 of Rx/Tx frame."]
5134 pub mod DATA_BYTE_3 {
5135 pub const offset: u32 = 0;
5136 pub const mask: u32 = 0xff << offset;
5137 pub mod R {}
5138 pub mod W {}
5139 pub mod RW {}
5140 }
5141 #[doc = "Data byte 1 of Rx/Tx frame."]
5142 pub mod DATA_BYTE_2 {
5143 pub const offset: u32 = 8;
5144 pub const mask: u32 = 0xff << offset;
5145 pub mod R {}
5146 pub mod W {}
5147 pub mod RW {}
5148 }
5149 #[doc = "Data byte 2 of Rx/Tx frame."]
5150 pub mod DATA_BYTE_1 {
5151 pub const offset: u32 = 16;
5152 pub const mask: u32 = 0xff << offset;
5153 pub mod R {}
5154 pub mod W {}
5155 pub mod RW {}
5156 }
5157 #[doc = "Data byte 3 of Rx/Tx frame."]
5158 pub mod DATA_BYTE_0 {
5159 pub const offset: u32 = 24;
5160 pub const mask: u32 = 0xff << offset;
5161 pub mod R {}
5162 pub mod W {}
5163 pub mod RW {}
5164 }
5165}
5166#[doc = "Message Buffer 12 WORD_16B Register"]
5167pub mod MB12_16B_WORD1 {
5168 #[doc = "Data byte 0 of Rx/Tx frame."]
5169 pub mod DATA_BYTE_7 {
5170 pub const offset: u32 = 0;
5171 pub const mask: u32 = 0xff << offset;
5172 pub mod R {}
5173 pub mod W {}
5174 pub mod RW {}
5175 }
5176 #[doc = "Data byte 1 of Rx/Tx frame."]
5177 pub mod DATA_BYTE_6 {
5178 pub const offset: u32 = 8;
5179 pub const mask: u32 = 0xff << offset;
5180 pub mod R {}
5181 pub mod W {}
5182 pub mod RW {}
5183 }
5184 #[doc = "Data byte 2 of Rx/Tx frame."]
5185 pub mod DATA_BYTE_5 {
5186 pub const offset: u32 = 16;
5187 pub const mask: u32 = 0xff << offset;
5188 pub mod R {}
5189 pub mod W {}
5190 pub mod RW {}
5191 }
5192 #[doc = "Data byte 3 of Rx/Tx frame."]
5193 pub mod DATA_BYTE_4 {
5194 pub const offset: u32 = 24;
5195 pub const mask: u32 = 0xff << offset;
5196 pub mod R {}
5197 pub mod W {}
5198 pub mod RW {}
5199 }
5200}
5201#[doc = "Message Buffer 19 CS Register"]
5202pub mod CS19 {
5203 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
5204 pub mod TIME_STAMP {
5205 pub const offset: u32 = 0;
5206 pub const mask: u32 = 0xffff << offset;
5207 pub mod R {}
5208 pub mod W {}
5209 pub mod RW {}
5210 }
5211 #[doc = "Length of the data to be stored/transmitted."]
5212 pub mod DLC {
5213 pub const offset: u32 = 16;
5214 pub const mask: u32 = 0x0f << offset;
5215 pub mod R {}
5216 pub mod W {}
5217 pub mod RW {}
5218 }
5219 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
5220 pub mod RTR {
5221 pub const offset: u32 = 20;
5222 pub const mask: u32 = 0x01 << offset;
5223 pub mod R {}
5224 pub mod W {}
5225 pub mod RW {}
5226 }
5227 #[doc = "ID Extended. One/zero for extended/standard format frame."]
5228 pub mod IDE {
5229 pub const offset: u32 = 21;
5230 pub const mask: u32 = 0x01 << offset;
5231 pub mod R {}
5232 pub mod W {}
5233 pub mod RW {}
5234 }
5235 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
5236 pub mod SRR {
5237 pub const offset: u32 = 22;
5238 pub const mask: u32 = 0x01 << offset;
5239 pub mod R {}
5240 pub mod W {}
5241 pub mod RW {}
5242 }
5243 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
5244 pub mod CODE {
5245 pub const offset: u32 = 24;
5246 pub const mask: u32 = 0x0f << offset;
5247 pub mod R {}
5248 pub mod W {}
5249 pub mod RW {}
5250 }
5251 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
5252 pub mod ESI {
5253 pub const offset: u32 = 29;
5254 pub const mask: u32 = 0x01 << offset;
5255 pub mod R {}
5256 pub mod W {}
5257 pub mod RW {}
5258 }
5259 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
5260 pub mod BRS {
5261 pub const offset: u32 = 30;
5262 pub const mask: u32 = 0x01 << offset;
5263 pub mod R {}
5264 pub mod W {}
5265 pub mod RW {}
5266 }
5267 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
5268 pub mod EDL {
5269 pub const offset: u32 = 31;
5270 pub const mask: u32 = 0x01 << offset;
5271 pub mod R {}
5272 pub mod W {}
5273 pub mod RW {}
5274 }
5275}
5276#[doc = "Message Buffer 19 ID Register"]
5277pub mod ID19 {
5278 #[doc = "Contains extended (LOW word) identifier of message buffer."]
5279 pub mod EXT {
5280 pub const offset: u32 = 0;
5281 pub const mask: u32 = 0x0003_ffff << offset;
5282 pub mod R {}
5283 pub mod W {}
5284 pub mod RW {}
5285 }
5286 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
5287 pub mod STD {
5288 pub const offset: u32 = 18;
5289 pub const mask: u32 = 0x07ff << offset;
5290 pub mod R {}
5291 pub mod W {}
5292 pub mod RW {}
5293 }
5294 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
5295 pub mod PRIO {
5296 pub const offset: u32 = 29;
5297 pub const mask: u32 = 0x07 << offset;
5298 pub mod R {}
5299 pub mod W {}
5300 pub mod RW {}
5301 }
5302}
5303#[doc = "Message Buffer 13 CS Register"]
5304pub mod MB13_16B_CS {
5305 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
5306 pub mod TIME_STAMP {
5307 pub const offset: u32 = 0;
5308 pub const mask: u32 = 0xffff << offset;
5309 pub mod R {}
5310 pub mod W {}
5311 pub mod RW {}
5312 }
5313 #[doc = "Length of the data to be stored/transmitted."]
5314 pub mod DLC {
5315 pub const offset: u32 = 16;
5316 pub const mask: u32 = 0x0f << offset;
5317 pub mod R {}
5318 pub mod W {}
5319 pub mod RW {}
5320 }
5321 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
5322 pub mod RTR {
5323 pub const offset: u32 = 20;
5324 pub const mask: u32 = 0x01 << offset;
5325 pub mod R {}
5326 pub mod W {}
5327 pub mod RW {}
5328 }
5329 #[doc = "ID Extended. One/zero for extended/standard format frame."]
5330 pub mod IDE {
5331 pub const offset: u32 = 21;
5332 pub const mask: u32 = 0x01 << offset;
5333 pub mod R {}
5334 pub mod W {}
5335 pub mod RW {}
5336 }
5337 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
5338 pub mod SRR {
5339 pub const offset: u32 = 22;
5340 pub const mask: u32 = 0x01 << offset;
5341 pub mod R {}
5342 pub mod W {}
5343 pub mod RW {}
5344 }
5345 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
5346 pub mod CODE {
5347 pub const offset: u32 = 24;
5348 pub const mask: u32 = 0x0f << offset;
5349 pub mod R {}
5350 pub mod W {}
5351 pub mod RW {}
5352 }
5353 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
5354 pub mod ESI {
5355 pub const offset: u32 = 29;
5356 pub const mask: u32 = 0x01 << offset;
5357 pub mod R {}
5358 pub mod W {}
5359 pub mod RW {}
5360 }
5361 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
5362 pub mod BRS {
5363 pub const offset: u32 = 30;
5364 pub const mask: u32 = 0x01 << offset;
5365 pub mod R {}
5366 pub mod W {}
5367 pub mod RW {}
5368 }
5369 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
5370 pub mod EDL {
5371 pub const offset: u32 = 31;
5372 pub const mask: u32 = 0x01 << offset;
5373 pub mod R {}
5374 pub mod W {}
5375 pub mod RW {}
5376 }
5377}
5378#[doc = "Message Buffer 13 ID Register"]
5379pub mod MB13_16B_ID {
5380 #[doc = "Contains extended (LOW word) identifier of message buffer."]
5381 pub mod EXT {
5382 pub const offset: u32 = 0;
5383 pub const mask: u32 = 0x0003_ffff << offset;
5384 pub mod R {}
5385 pub mod W {}
5386 pub mod RW {}
5387 }
5388 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
5389 pub mod STD {
5390 pub const offset: u32 = 18;
5391 pub const mask: u32 = 0x07ff << offset;
5392 pub mod R {}
5393 pub mod W {}
5394 pub mod RW {}
5395 }
5396 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
5397 pub mod PRIO {
5398 pub const offset: u32 = 29;
5399 pub const mask: u32 = 0x07 << offset;
5400 pub mod R {}
5401 pub mod W {}
5402 pub mod RW {}
5403 }
5404}
5405#[doc = "Message Buffer 20 CS Register"]
5406pub mod CS20 {
5407 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
5408 pub mod TIME_STAMP {
5409 pub const offset: u32 = 0;
5410 pub const mask: u32 = 0xffff << offset;
5411 pub mod R {}
5412 pub mod W {}
5413 pub mod RW {}
5414 }
5415 #[doc = "Length of the data to be stored/transmitted."]
5416 pub mod DLC {
5417 pub const offset: u32 = 16;
5418 pub const mask: u32 = 0x0f << offset;
5419 pub mod R {}
5420 pub mod W {}
5421 pub mod RW {}
5422 }
5423 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
5424 pub mod RTR {
5425 pub const offset: u32 = 20;
5426 pub const mask: u32 = 0x01 << offset;
5427 pub mod R {}
5428 pub mod W {}
5429 pub mod RW {}
5430 }
5431 #[doc = "ID Extended. One/zero for extended/standard format frame."]
5432 pub mod IDE {
5433 pub const offset: u32 = 21;
5434 pub const mask: u32 = 0x01 << offset;
5435 pub mod R {}
5436 pub mod W {}
5437 pub mod RW {}
5438 }
5439 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
5440 pub mod SRR {
5441 pub const offset: u32 = 22;
5442 pub const mask: u32 = 0x01 << offset;
5443 pub mod R {}
5444 pub mod W {}
5445 pub mod RW {}
5446 }
5447 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
5448 pub mod CODE {
5449 pub const offset: u32 = 24;
5450 pub const mask: u32 = 0x0f << offset;
5451 pub mod R {}
5452 pub mod W {}
5453 pub mod RW {}
5454 }
5455 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
5456 pub mod ESI {
5457 pub const offset: u32 = 29;
5458 pub const mask: u32 = 0x01 << offset;
5459 pub mod R {}
5460 pub mod W {}
5461 pub mod RW {}
5462 }
5463 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
5464 pub mod BRS {
5465 pub const offset: u32 = 30;
5466 pub const mask: u32 = 0x01 << offset;
5467 pub mod R {}
5468 pub mod W {}
5469 pub mod RW {}
5470 }
5471 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
5472 pub mod EDL {
5473 pub const offset: u32 = 31;
5474 pub const mask: u32 = 0x01 << offset;
5475 pub mod R {}
5476 pub mod W {}
5477 pub mod RW {}
5478 }
5479}
5480#[doc = "Message Buffer 20 ID Register"]
5481pub mod ID20 {
5482 #[doc = "Contains extended (LOW word) identifier of message buffer."]
5483 pub mod EXT {
5484 pub const offset: u32 = 0;
5485 pub const mask: u32 = 0x0003_ffff << offset;
5486 pub mod R {}
5487 pub mod W {}
5488 pub mod RW {}
5489 }
5490 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
5491 pub mod STD {
5492 pub const offset: u32 = 18;
5493 pub const mask: u32 = 0x07ff << offset;
5494 pub mod R {}
5495 pub mod W {}
5496 pub mod RW {}
5497 }
5498 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
5499 pub mod PRIO {
5500 pub const offset: u32 = 29;
5501 pub const mask: u32 = 0x07 << offset;
5502 pub mod R {}
5503 pub mod W {}
5504 pub mod RW {}
5505 }
5506}
5507#[doc = "Message Buffer 13 WORD_16B Register"]
5508pub mod MB13_16B_WORD2 {
5509 #[doc = "Data byte 0 of Rx/Tx frame."]
5510 pub mod DATA_BYTE_11 {
5511 pub const offset: u32 = 0;
5512 pub const mask: u32 = 0xff << offset;
5513 pub mod R {}
5514 pub mod W {}
5515 pub mod RW {}
5516 }
5517 #[doc = "Data byte 1 of Rx/Tx frame."]
5518 pub mod DATA_BYTE_10 {
5519 pub const offset: u32 = 8;
5520 pub const mask: u32 = 0xff << offset;
5521 pub mod R {}
5522 pub mod W {}
5523 pub mod RW {}
5524 }
5525 #[doc = "Data byte 2 of Rx/Tx frame."]
5526 pub mod DATA_BYTE_9 {
5527 pub const offset: u32 = 16;
5528 pub const mask: u32 = 0xff << offset;
5529 pub mod R {}
5530 pub mod W {}
5531 pub mod RW {}
5532 }
5533 #[doc = "Data byte 3 of Rx/Tx frame."]
5534 pub mod DATA_BYTE_8 {
5535 pub const offset: u32 = 24;
5536 pub const mask: u32 = 0xff << offset;
5537 pub mod R {}
5538 pub mod W {}
5539 pub mod RW {}
5540 }
5541}
5542#[doc = "Message Buffer 13 WORD_16B Register"]
5543pub mod MB13_16B_WORD3 {
5544 #[doc = "Data byte 0 of Rx/Tx frame."]
5545 pub mod DATA_BYTE_15 {
5546 pub const offset: u32 = 0;
5547 pub const mask: u32 = 0xff << offset;
5548 pub mod R {}
5549 pub mod W {}
5550 pub mod RW {}
5551 }
5552 #[doc = "Data byte 1 of Rx/Tx frame."]
5553 pub mod DATA_BYTE_14 {
5554 pub const offset: u32 = 8;
5555 pub const mask: u32 = 0xff << offset;
5556 pub mod R {}
5557 pub mod W {}
5558 pub mod RW {}
5559 }
5560 #[doc = "Data byte 2 of Rx/Tx frame."]
5561 pub mod DATA_BYTE_13 {
5562 pub const offset: u32 = 16;
5563 pub const mask: u32 = 0xff << offset;
5564 pub mod R {}
5565 pub mod W {}
5566 pub mod RW {}
5567 }
5568 #[doc = "Data byte 3 of Rx/Tx frame."]
5569 pub mod DATA_BYTE_12 {
5570 pub const offset: u32 = 24;
5571 pub const mask: u32 = 0xff << offset;
5572 pub mod R {}
5573 pub mod W {}
5574 pub mod RW {}
5575 }
5576}
5577#[doc = "Message Buffer 21 CS Register"]
5578pub mod CS21 {
5579 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
5580 pub mod TIME_STAMP {
5581 pub const offset: u32 = 0;
5582 pub const mask: u32 = 0xffff << offset;
5583 pub mod R {}
5584 pub mod W {}
5585 pub mod RW {}
5586 }
5587 #[doc = "Length of the data to be stored/transmitted."]
5588 pub mod DLC {
5589 pub const offset: u32 = 16;
5590 pub const mask: u32 = 0x0f << offset;
5591 pub mod R {}
5592 pub mod W {}
5593 pub mod RW {}
5594 }
5595 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
5596 pub mod RTR {
5597 pub const offset: u32 = 20;
5598 pub const mask: u32 = 0x01 << offset;
5599 pub mod R {}
5600 pub mod W {}
5601 pub mod RW {}
5602 }
5603 #[doc = "ID Extended. One/zero for extended/standard format frame."]
5604 pub mod IDE {
5605 pub const offset: u32 = 21;
5606 pub const mask: u32 = 0x01 << offset;
5607 pub mod R {}
5608 pub mod W {}
5609 pub mod RW {}
5610 }
5611 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
5612 pub mod SRR {
5613 pub const offset: u32 = 22;
5614 pub const mask: u32 = 0x01 << offset;
5615 pub mod R {}
5616 pub mod W {}
5617 pub mod RW {}
5618 }
5619 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
5620 pub mod CODE {
5621 pub const offset: u32 = 24;
5622 pub const mask: u32 = 0x0f << offset;
5623 pub mod R {}
5624 pub mod W {}
5625 pub mod RW {}
5626 }
5627 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
5628 pub mod ESI {
5629 pub const offset: u32 = 29;
5630 pub const mask: u32 = 0x01 << offset;
5631 pub mod R {}
5632 pub mod W {}
5633 pub mod RW {}
5634 }
5635 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
5636 pub mod BRS {
5637 pub const offset: u32 = 30;
5638 pub const mask: u32 = 0x01 << offset;
5639 pub mod R {}
5640 pub mod W {}
5641 pub mod RW {}
5642 }
5643 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
5644 pub mod EDL {
5645 pub const offset: u32 = 31;
5646 pub const mask: u32 = 0x01 << offset;
5647 pub mod R {}
5648 pub mod W {}
5649 pub mod RW {}
5650 }
5651}
5652#[doc = "Message Buffer 21 ID Register"]
5653pub mod ID21 {
5654 #[doc = "Contains extended (LOW word) identifier of message buffer."]
5655 pub mod EXT {
5656 pub const offset: u32 = 0;
5657 pub const mask: u32 = 0x0003_ffff << offset;
5658 pub mod R {}
5659 pub mod W {}
5660 pub mod RW {}
5661 }
5662 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
5663 pub mod STD {
5664 pub const offset: u32 = 18;
5665 pub const mask: u32 = 0x07ff << offset;
5666 pub mod R {}
5667 pub mod W {}
5668 pub mod RW {}
5669 }
5670 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
5671 pub mod PRIO {
5672 pub const offset: u32 = 29;
5673 pub const mask: u32 = 0x07 << offset;
5674 pub mod R {}
5675 pub mod W {}
5676 pub mod RW {}
5677 }
5678}
5679#[doc = "Message Buffer 14 WORD_16B Register"]
5680pub mod MB14_16B_WORD0 {
5681 #[doc = "Data byte 0 of Rx/Tx frame."]
5682 pub mod DATA_BYTE_3 {
5683 pub const offset: u32 = 0;
5684 pub const mask: u32 = 0xff << offset;
5685 pub mod R {}
5686 pub mod W {}
5687 pub mod RW {}
5688 }
5689 #[doc = "Data byte 1 of Rx/Tx frame."]
5690 pub mod DATA_BYTE_2 {
5691 pub const offset: u32 = 8;
5692 pub const mask: u32 = 0xff << offset;
5693 pub mod R {}
5694 pub mod W {}
5695 pub mod RW {}
5696 }
5697 #[doc = "Data byte 2 of Rx/Tx frame."]
5698 pub mod DATA_BYTE_1 {
5699 pub const offset: u32 = 16;
5700 pub const mask: u32 = 0xff << offset;
5701 pub mod R {}
5702 pub mod W {}
5703 pub mod RW {}
5704 }
5705 #[doc = "Data byte 3 of Rx/Tx frame."]
5706 pub mod DATA_BYTE_0 {
5707 pub const offset: u32 = 24;
5708 pub const mask: u32 = 0xff << offset;
5709 pub mod R {}
5710 pub mod W {}
5711 pub mod RW {}
5712 }
5713}
5714#[doc = "Message Buffer 14 WORD_16B Register"]
5715pub mod MB14_16B_WORD1 {
5716 #[doc = "Data byte 0 of Rx/Tx frame."]
5717 pub mod DATA_BYTE_7 {
5718 pub const offset: u32 = 0;
5719 pub const mask: u32 = 0xff << offset;
5720 pub mod R {}
5721 pub mod W {}
5722 pub mod RW {}
5723 }
5724 #[doc = "Data byte 1 of Rx/Tx frame."]
5725 pub mod DATA_BYTE_6 {
5726 pub const offset: u32 = 8;
5727 pub const mask: u32 = 0xff << offset;
5728 pub mod R {}
5729 pub mod W {}
5730 pub mod RW {}
5731 }
5732 #[doc = "Data byte 2 of Rx/Tx frame."]
5733 pub mod DATA_BYTE_5 {
5734 pub const offset: u32 = 16;
5735 pub const mask: u32 = 0xff << offset;
5736 pub mod R {}
5737 pub mod W {}
5738 pub mod RW {}
5739 }
5740 #[doc = "Data byte 3 of Rx/Tx frame."]
5741 pub mod DATA_BYTE_4 {
5742 pub const offset: u32 = 24;
5743 pub const mask: u32 = 0xff << offset;
5744 pub mod R {}
5745 pub mod W {}
5746 pub mod RW {}
5747 }
5748}
5749#[doc = "Message Buffer 22 CS Register"]
5750pub mod CS22 {
5751 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
5752 pub mod TIME_STAMP {
5753 pub const offset: u32 = 0;
5754 pub const mask: u32 = 0xffff << offset;
5755 pub mod R {}
5756 pub mod W {}
5757 pub mod RW {}
5758 }
5759 #[doc = "Length of the data to be stored/transmitted."]
5760 pub mod DLC {
5761 pub const offset: u32 = 16;
5762 pub const mask: u32 = 0x0f << offset;
5763 pub mod R {}
5764 pub mod W {}
5765 pub mod RW {}
5766 }
5767 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
5768 pub mod RTR {
5769 pub const offset: u32 = 20;
5770 pub const mask: u32 = 0x01 << offset;
5771 pub mod R {}
5772 pub mod W {}
5773 pub mod RW {}
5774 }
5775 #[doc = "ID Extended. One/zero for extended/standard format frame."]
5776 pub mod IDE {
5777 pub const offset: u32 = 21;
5778 pub const mask: u32 = 0x01 << offset;
5779 pub mod R {}
5780 pub mod W {}
5781 pub mod RW {}
5782 }
5783 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
5784 pub mod SRR {
5785 pub const offset: u32 = 22;
5786 pub const mask: u32 = 0x01 << offset;
5787 pub mod R {}
5788 pub mod W {}
5789 pub mod RW {}
5790 }
5791 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
5792 pub mod CODE {
5793 pub const offset: u32 = 24;
5794 pub const mask: u32 = 0x0f << offset;
5795 pub mod R {}
5796 pub mod W {}
5797 pub mod RW {}
5798 }
5799 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
5800 pub mod ESI {
5801 pub const offset: u32 = 29;
5802 pub const mask: u32 = 0x01 << offset;
5803 pub mod R {}
5804 pub mod W {}
5805 pub mod RW {}
5806 }
5807 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
5808 pub mod BRS {
5809 pub const offset: u32 = 30;
5810 pub const mask: u32 = 0x01 << offset;
5811 pub mod R {}
5812 pub mod W {}
5813 pub mod RW {}
5814 }
5815 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
5816 pub mod EDL {
5817 pub const offset: u32 = 31;
5818 pub const mask: u32 = 0x01 << offset;
5819 pub mod R {}
5820 pub mod W {}
5821 pub mod RW {}
5822 }
5823}
5824#[doc = "Message Buffer 22 ID Register"]
5825pub mod ID22 {
5826 #[doc = "Contains extended (LOW word) identifier of message buffer."]
5827 pub mod EXT {
5828 pub const offset: u32 = 0;
5829 pub const mask: u32 = 0x0003_ffff << offset;
5830 pub mod R {}
5831 pub mod W {}
5832 pub mod RW {}
5833 }
5834 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
5835 pub mod STD {
5836 pub const offset: u32 = 18;
5837 pub const mask: u32 = 0x07ff << offset;
5838 pub mod R {}
5839 pub mod W {}
5840 pub mod RW {}
5841 }
5842 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
5843 pub mod PRIO {
5844 pub const offset: u32 = 29;
5845 pub const mask: u32 = 0x07 << offset;
5846 pub mod R {}
5847 pub mod W {}
5848 pub mod RW {}
5849 }
5850}
5851#[doc = "Message Buffer 15 CS Register"]
5852pub mod MB15_16B_CS {
5853 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
5854 pub mod TIME_STAMP {
5855 pub const offset: u32 = 0;
5856 pub const mask: u32 = 0xffff << offset;
5857 pub mod R {}
5858 pub mod W {}
5859 pub mod RW {}
5860 }
5861 #[doc = "Length of the data to be stored/transmitted."]
5862 pub mod DLC {
5863 pub const offset: u32 = 16;
5864 pub const mask: u32 = 0x0f << offset;
5865 pub mod R {}
5866 pub mod W {}
5867 pub mod RW {}
5868 }
5869 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
5870 pub mod RTR {
5871 pub const offset: u32 = 20;
5872 pub const mask: u32 = 0x01 << offset;
5873 pub mod R {}
5874 pub mod W {}
5875 pub mod RW {}
5876 }
5877 #[doc = "ID Extended. One/zero for extended/standard format frame."]
5878 pub mod IDE {
5879 pub const offset: u32 = 21;
5880 pub const mask: u32 = 0x01 << offset;
5881 pub mod R {}
5882 pub mod W {}
5883 pub mod RW {}
5884 }
5885 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
5886 pub mod SRR {
5887 pub const offset: u32 = 22;
5888 pub const mask: u32 = 0x01 << offset;
5889 pub mod R {}
5890 pub mod W {}
5891 pub mod RW {}
5892 }
5893 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
5894 pub mod CODE {
5895 pub const offset: u32 = 24;
5896 pub const mask: u32 = 0x0f << offset;
5897 pub mod R {}
5898 pub mod W {}
5899 pub mod RW {}
5900 }
5901 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
5902 pub mod ESI {
5903 pub const offset: u32 = 29;
5904 pub const mask: u32 = 0x01 << offset;
5905 pub mod R {}
5906 pub mod W {}
5907 pub mod RW {}
5908 }
5909 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
5910 pub mod BRS {
5911 pub const offset: u32 = 30;
5912 pub const mask: u32 = 0x01 << offset;
5913 pub mod R {}
5914 pub mod W {}
5915 pub mod RW {}
5916 }
5917 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
5918 pub mod EDL {
5919 pub const offset: u32 = 31;
5920 pub const mask: u32 = 0x01 << offset;
5921 pub mod R {}
5922 pub mod W {}
5923 pub mod RW {}
5924 }
5925}
5926#[doc = "Message Buffer 15 ID Register"]
5927pub mod MB15_16B_ID {
5928 #[doc = "Contains extended (LOW word) identifier of message buffer."]
5929 pub mod EXT {
5930 pub const offset: u32 = 0;
5931 pub const mask: u32 = 0x0003_ffff << offset;
5932 pub mod R {}
5933 pub mod W {}
5934 pub mod RW {}
5935 }
5936 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
5937 pub mod STD {
5938 pub const offset: u32 = 18;
5939 pub const mask: u32 = 0x07ff << offset;
5940 pub mod R {}
5941 pub mod W {}
5942 pub mod RW {}
5943 }
5944 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
5945 pub mod PRIO {
5946 pub const offset: u32 = 29;
5947 pub const mask: u32 = 0x07 << offset;
5948 pub mod R {}
5949 pub mod W {}
5950 pub mod RW {}
5951 }
5952}
5953#[doc = "Message Buffer 23 CS Register"]
5954pub mod CS23 {
5955 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
5956 pub mod TIME_STAMP {
5957 pub const offset: u32 = 0;
5958 pub const mask: u32 = 0xffff << offset;
5959 pub mod R {}
5960 pub mod W {}
5961 pub mod RW {}
5962 }
5963 #[doc = "Length of the data to be stored/transmitted."]
5964 pub mod DLC {
5965 pub const offset: u32 = 16;
5966 pub const mask: u32 = 0x0f << offset;
5967 pub mod R {}
5968 pub mod W {}
5969 pub mod RW {}
5970 }
5971 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
5972 pub mod RTR {
5973 pub const offset: u32 = 20;
5974 pub const mask: u32 = 0x01 << offset;
5975 pub mod R {}
5976 pub mod W {}
5977 pub mod RW {}
5978 }
5979 #[doc = "ID Extended. One/zero for extended/standard format frame."]
5980 pub mod IDE {
5981 pub const offset: u32 = 21;
5982 pub const mask: u32 = 0x01 << offset;
5983 pub mod R {}
5984 pub mod W {}
5985 pub mod RW {}
5986 }
5987 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
5988 pub mod SRR {
5989 pub const offset: u32 = 22;
5990 pub const mask: u32 = 0x01 << offset;
5991 pub mod R {}
5992 pub mod W {}
5993 pub mod RW {}
5994 }
5995 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
5996 pub mod CODE {
5997 pub const offset: u32 = 24;
5998 pub const mask: u32 = 0x0f << offset;
5999 pub mod R {}
6000 pub mod W {}
6001 pub mod RW {}
6002 }
6003 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
6004 pub mod ESI {
6005 pub const offset: u32 = 29;
6006 pub const mask: u32 = 0x01 << offset;
6007 pub mod R {}
6008 pub mod W {}
6009 pub mod RW {}
6010 }
6011 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
6012 pub mod BRS {
6013 pub const offset: u32 = 30;
6014 pub const mask: u32 = 0x01 << offset;
6015 pub mod R {}
6016 pub mod W {}
6017 pub mod RW {}
6018 }
6019 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
6020 pub mod EDL {
6021 pub const offset: u32 = 31;
6022 pub const mask: u32 = 0x01 << offset;
6023 pub mod R {}
6024 pub mod W {}
6025 pub mod RW {}
6026 }
6027}
6028#[doc = "Message Buffer 23 ID Register"]
6029pub mod ID23 {
6030 #[doc = "Contains extended (LOW word) identifier of message buffer."]
6031 pub mod EXT {
6032 pub const offset: u32 = 0;
6033 pub const mask: u32 = 0x0003_ffff << offset;
6034 pub mod R {}
6035 pub mod W {}
6036 pub mod RW {}
6037 }
6038 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
6039 pub mod STD {
6040 pub const offset: u32 = 18;
6041 pub const mask: u32 = 0x07ff << offset;
6042 pub mod R {}
6043 pub mod W {}
6044 pub mod RW {}
6045 }
6046 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
6047 pub mod PRIO {
6048 pub const offset: u32 = 29;
6049 pub const mask: u32 = 0x07 << offset;
6050 pub mod R {}
6051 pub mod W {}
6052 pub mod RW {}
6053 }
6054}
6055#[doc = "Message Buffer 15 WORD_16B Register"]
6056pub mod MB15_16B_WORD2 {
6057 #[doc = "Data byte 0 of Rx/Tx frame."]
6058 pub mod DATA_BYTE_11 {
6059 pub const offset: u32 = 0;
6060 pub const mask: u32 = 0xff << offset;
6061 pub mod R {}
6062 pub mod W {}
6063 pub mod RW {}
6064 }
6065 #[doc = "Data byte 1 of Rx/Tx frame."]
6066 pub mod DATA_BYTE_10 {
6067 pub const offset: u32 = 8;
6068 pub const mask: u32 = 0xff << offset;
6069 pub mod R {}
6070 pub mod W {}
6071 pub mod RW {}
6072 }
6073 #[doc = "Data byte 2 of Rx/Tx frame."]
6074 pub mod DATA_BYTE_9 {
6075 pub const offset: u32 = 16;
6076 pub const mask: u32 = 0xff << offset;
6077 pub mod R {}
6078 pub mod W {}
6079 pub mod RW {}
6080 }
6081 #[doc = "Data byte 3 of Rx/Tx frame."]
6082 pub mod DATA_BYTE_8 {
6083 pub const offset: u32 = 24;
6084 pub const mask: u32 = 0xff << offset;
6085 pub mod R {}
6086 pub mod W {}
6087 pub mod RW {}
6088 }
6089}
6090#[doc = "Message Buffer 15 WORD_16B Register"]
6091pub mod MB15_16B_WORD3 {
6092 #[doc = "Data byte 0 of Rx/Tx frame."]
6093 pub mod DATA_BYTE_15 {
6094 pub const offset: u32 = 0;
6095 pub const mask: u32 = 0xff << offset;
6096 pub mod R {}
6097 pub mod W {}
6098 pub mod RW {}
6099 }
6100 #[doc = "Data byte 1 of Rx/Tx frame."]
6101 pub mod DATA_BYTE_14 {
6102 pub const offset: u32 = 8;
6103 pub const mask: u32 = 0xff << offset;
6104 pub mod R {}
6105 pub mod W {}
6106 pub mod RW {}
6107 }
6108 #[doc = "Data byte 2 of Rx/Tx frame."]
6109 pub mod DATA_BYTE_13 {
6110 pub const offset: u32 = 16;
6111 pub const mask: u32 = 0xff << offset;
6112 pub mod R {}
6113 pub mod W {}
6114 pub mod RW {}
6115 }
6116 #[doc = "Data byte 3 of Rx/Tx frame."]
6117 pub mod DATA_BYTE_12 {
6118 pub const offset: u32 = 24;
6119 pub const mask: u32 = 0xff << offset;
6120 pub mod R {}
6121 pub mod W {}
6122 pub mod RW {}
6123 }
6124}
6125#[doc = "Message Buffer 24 CS Register"]
6126pub mod CS24 {
6127 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
6128 pub mod TIME_STAMP {
6129 pub const offset: u32 = 0;
6130 pub const mask: u32 = 0xffff << offset;
6131 pub mod R {}
6132 pub mod W {}
6133 pub mod RW {}
6134 }
6135 #[doc = "Length of the data to be stored/transmitted."]
6136 pub mod DLC {
6137 pub const offset: u32 = 16;
6138 pub const mask: u32 = 0x0f << offset;
6139 pub mod R {}
6140 pub mod W {}
6141 pub mod RW {}
6142 }
6143 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
6144 pub mod RTR {
6145 pub const offset: u32 = 20;
6146 pub const mask: u32 = 0x01 << offset;
6147 pub mod R {}
6148 pub mod W {}
6149 pub mod RW {}
6150 }
6151 #[doc = "ID Extended. One/zero for extended/standard format frame."]
6152 pub mod IDE {
6153 pub const offset: u32 = 21;
6154 pub const mask: u32 = 0x01 << offset;
6155 pub mod R {}
6156 pub mod W {}
6157 pub mod RW {}
6158 }
6159 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
6160 pub mod SRR {
6161 pub const offset: u32 = 22;
6162 pub const mask: u32 = 0x01 << offset;
6163 pub mod R {}
6164 pub mod W {}
6165 pub mod RW {}
6166 }
6167 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
6168 pub mod CODE {
6169 pub const offset: u32 = 24;
6170 pub const mask: u32 = 0x0f << offset;
6171 pub mod R {}
6172 pub mod W {}
6173 pub mod RW {}
6174 }
6175 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
6176 pub mod ESI {
6177 pub const offset: u32 = 29;
6178 pub const mask: u32 = 0x01 << offset;
6179 pub mod R {}
6180 pub mod W {}
6181 pub mod RW {}
6182 }
6183 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
6184 pub mod BRS {
6185 pub const offset: u32 = 30;
6186 pub const mask: u32 = 0x01 << offset;
6187 pub mod R {}
6188 pub mod W {}
6189 pub mod RW {}
6190 }
6191 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
6192 pub mod EDL {
6193 pub const offset: u32 = 31;
6194 pub const mask: u32 = 0x01 << offset;
6195 pub mod R {}
6196 pub mod W {}
6197 pub mod RW {}
6198 }
6199}
6200#[doc = "Message Buffer 24 ID Register"]
6201pub mod ID24 {
6202 #[doc = "Contains extended (LOW word) identifier of message buffer."]
6203 pub mod EXT {
6204 pub const offset: u32 = 0;
6205 pub const mask: u32 = 0x0003_ffff << offset;
6206 pub mod R {}
6207 pub mod W {}
6208 pub mod RW {}
6209 }
6210 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
6211 pub mod STD {
6212 pub const offset: u32 = 18;
6213 pub const mask: u32 = 0x07ff << offset;
6214 pub mod R {}
6215 pub mod W {}
6216 pub mod RW {}
6217 }
6218 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
6219 pub mod PRIO {
6220 pub const offset: u32 = 29;
6221 pub const mask: u32 = 0x07 << offset;
6222 pub mod R {}
6223 pub mod W {}
6224 pub mod RW {}
6225 }
6226}
6227#[doc = "Message Buffer 16 WORD_16B Register"]
6228pub mod MB16_16B_WORD0 {
6229 #[doc = "Data byte 0 of Rx/Tx frame."]
6230 pub mod DATA_BYTE_3 {
6231 pub const offset: u32 = 0;
6232 pub const mask: u32 = 0xff << offset;
6233 pub mod R {}
6234 pub mod W {}
6235 pub mod RW {}
6236 }
6237 #[doc = "Data byte 1 of Rx/Tx frame."]
6238 pub mod DATA_BYTE_2 {
6239 pub const offset: u32 = 8;
6240 pub const mask: u32 = 0xff << offset;
6241 pub mod R {}
6242 pub mod W {}
6243 pub mod RW {}
6244 }
6245 #[doc = "Data byte 2 of Rx/Tx frame."]
6246 pub mod DATA_BYTE_1 {
6247 pub const offset: u32 = 16;
6248 pub const mask: u32 = 0xff << offset;
6249 pub mod R {}
6250 pub mod W {}
6251 pub mod RW {}
6252 }
6253 #[doc = "Data byte 3 of Rx/Tx frame."]
6254 pub mod DATA_BYTE_0 {
6255 pub const offset: u32 = 24;
6256 pub const mask: u32 = 0xff << offset;
6257 pub mod R {}
6258 pub mod W {}
6259 pub mod RW {}
6260 }
6261}
6262#[doc = "Message Buffer 16 WORD_16B Register"]
6263pub mod MB16_16B_WORD1 {
6264 #[doc = "Data byte 0 of Rx/Tx frame."]
6265 pub mod DATA_BYTE_7 {
6266 pub const offset: u32 = 0;
6267 pub const mask: u32 = 0xff << offset;
6268 pub mod R {}
6269 pub mod W {}
6270 pub mod RW {}
6271 }
6272 #[doc = "Data byte 1 of Rx/Tx frame."]
6273 pub mod DATA_BYTE_6 {
6274 pub const offset: u32 = 8;
6275 pub const mask: u32 = 0xff << offset;
6276 pub mod R {}
6277 pub mod W {}
6278 pub mod RW {}
6279 }
6280 #[doc = "Data byte 2 of Rx/Tx frame."]
6281 pub mod DATA_BYTE_5 {
6282 pub const offset: u32 = 16;
6283 pub const mask: u32 = 0xff << offset;
6284 pub mod R {}
6285 pub mod W {}
6286 pub mod RW {}
6287 }
6288 #[doc = "Data byte 3 of Rx/Tx frame."]
6289 pub mod DATA_BYTE_4 {
6290 pub const offset: u32 = 24;
6291 pub const mask: u32 = 0xff << offset;
6292 pub mod R {}
6293 pub mod W {}
6294 pub mod RW {}
6295 }
6296}
6297#[doc = "Message Buffer 25 CS Register"]
6298pub mod CS25 {
6299 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
6300 pub mod TIME_STAMP {
6301 pub const offset: u32 = 0;
6302 pub const mask: u32 = 0xffff << offset;
6303 pub mod R {}
6304 pub mod W {}
6305 pub mod RW {}
6306 }
6307 #[doc = "Length of the data to be stored/transmitted."]
6308 pub mod DLC {
6309 pub const offset: u32 = 16;
6310 pub const mask: u32 = 0x0f << offset;
6311 pub mod R {}
6312 pub mod W {}
6313 pub mod RW {}
6314 }
6315 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
6316 pub mod RTR {
6317 pub const offset: u32 = 20;
6318 pub const mask: u32 = 0x01 << offset;
6319 pub mod R {}
6320 pub mod W {}
6321 pub mod RW {}
6322 }
6323 #[doc = "ID Extended. One/zero for extended/standard format frame."]
6324 pub mod IDE {
6325 pub const offset: u32 = 21;
6326 pub const mask: u32 = 0x01 << offset;
6327 pub mod R {}
6328 pub mod W {}
6329 pub mod RW {}
6330 }
6331 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
6332 pub mod SRR {
6333 pub const offset: u32 = 22;
6334 pub const mask: u32 = 0x01 << offset;
6335 pub mod R {}
6336 pub mod W {}
6337 pub mod RW {}
6338 }
6339 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
6340 pub mod CODE {
6341 pub const offset: u32 = 24;
6342 pub const mask: u32 = 0x0f << offset;
6343 pub mod R {}
6344 pub mod W {}
6345 pub mod RW {}
6346 }
6347 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
6348 pub mod ESI {
6349 pub const offset: u32 = 29;
6350 pub const mask: u32 = 0x01 << offset;
6351 pub mod R {}
6352 pub mod W {}
6353 pub mod RW {}
6354 }
6355 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
6356 pub mod BRS {
6357 pub const offset: u32 = 30;
6358 pub const mask: u32 = 0x01 << offset;
6359 pub mod R {}
6360 pub mod W {}
6361 pub mod RW {}
6362 }
6363 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
6364 pub mod EDL {
6365 pub const offset: u32 = 31;
6366 pub const mask: u32 = 0x01 << offset;
6367 pub mod R {}
6368 pub mod W {}
6369 pub mod RW {}
6370 }
6371}
6372#[doc = "Message Buffer 25 ID Register"]
6373pub mod ID25 {
6374 #[doc = "Contains extended (LOW word) identifier of message buffer."]
6375 pub mod EXT {
6376 pub const offset: u32 = 0;
6377 pub const mask: u32 = 0x0003_ffff << offset;
6378 pub mod R {}
6379 pub mod W {}
6380 pub mod RW {}
6381 }
6382 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
6383 pub mod STD {
6384 pub const offset: u32 = 18;
6385 pub const mask: u32 = 0x07ff << offset;
6386 pub mod R {}
6387 pub mod W {}
6388 pub mod RW {}
6389 }
6390 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
6391 pub mod PRIO {
6392 pub const offset: u32 = 29;
6393 pub const mask: u32 = 0x07 << offset;
6394 pub mod R {}
6395 pub mod W {}
6396 pub mod RW {}
6397 }
6398}
6399#[doc = "Message Buffer 10 WORD_32B Register"]
6400pub mod MB10_32B_WORD0 {
6401 #[doc = "Data byte 0 of Rx/Tx frame."]
6402 pub mod DATA_BYTE_3 {
6403 pub const offset: u32 = 0;
6404 pub const mask: u32 = 0xff << offset;
6405 pub mod R {}
6406 pub mod W {}
6407 pub mod RW {}
6408 }
6409 #[doc = "Data byte 1 of Rx/Tx frame."]
6410 pub mod DATA_BYTE_2 {
6411 pub const offset: u32 = 8;
6412 pub const mask: u32 = 0xff << offset;
6413 pub mod R {}
6414 pub mod W {}
6415 pub mod RW {}
6416 }
6417 #[doc = "Data byte 2 of Rx/Tx frame."]
6418 pub mod DATA_BYTE_1 {
6419 pub const offset: u32 = 16;
6420 pub const mask: u32 = 0xff << offset;
6421 pub mod R {}
6422 pub mod W {}
6423 pub mod RW {}
6424 }
6425 #[doc = "Data byte 3 of Rx/Tx frame."]
6426 pub mod DATA_BYTE_0 {
6427 pub const offset: u32 = 24;
6428 pub const mask: u32 = 0xff << offset;
6429 pub mod R {}
6430 pub mod W {}
6431 pub mod RW {}
6432 }
6433}
6434#[doc = "Message Buffer 10 WORD_32B Register"]
6435pub mod MB10_32B_WORD1 {
6436 #[doc = "Data byte 0 of Rx/Tx frame."]
6437 pub mod DATA_BYTE_7 {
6438 pub const offset: u32 = 0;
6439 pub const mask: u32 = 0xff << offset;
6440 pub mod R {}
6441 pub mod W {}
6442 pub mod RW {}
6443 }
6444 #[doc = "Data byte 1 of Rx/Tx frame."]
6445 pub mod DATA_BYTE_6 {
6446 pub const offset: u32 = 8;
6447 pub const mask: u32 = 0xff << offset;
6448 pub mod R {}
6449 pub mod W {}
6450 pub mod RW {}
6451 }
6452 #[doc = "Data byte 2 of Rx/Tx frame."]
6453 pub mod DATA_BYTE_5 {
6454 pub const offset: u32 = 16;
6455 pub const mask: u32 = 0xff << offset;
6456 pub mod R {}
6457 pub mod W {}
6458 pub mod RW {}
6459 }
6460 #[doc = "Data byte 3 of Rx/Tx frame."]
6461 pub mod DATA_BYTE_4 {
6462 pub const offset: u32 = 24;
6463 pub const mask: u32 = 0xff << offset;
6464 pub mod R {}
6465 pub mod W {}
6466 pub mod RW {}
6467 }
6468}
6469#[doc = "Message Buffer 26 CS Register"]
6470pub mod CS26 {
6471 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
6472 pub mod TIME_STAMP {
6473 pub const offset: u32 = 0;
6474 pub const mask: u32 = 0xffff << offset;
6475 pub mod R {}
6476 pub mod W {}
6477 pub mod RW {}
6478 }
6479 #[doc = "Length of the data to be stored/transmitted."]
6480 pub mod DLC {
6481 pub const offset: u32 = 16;
6482 pub const mask: u32 = 0x0f << offset;
6483 pub mod R {}
6484 pub mod W {}
6485 pub mod RW {}
6486 }
6487 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
6488 pub mod RTR {
6489 pub const offset: u32 = 20;
6490 pub const mask: u32 = 0x01 << offset;
6491 pub mod R {}
6492 pub mod W {}
6493 pub mod RW {}
6494 }
6495 #[doc = "ID Extended. One/zero for extended/standard format frame."]
6496 pub mod IDE {
6497 pub const offset: u32 = 21;
6498 pub const mask: u32 = 0x01 << offset;
6499 pub mod R {}
6500 pub mod W {}
6501 pub mod RW {}
6502 }
6503 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
6504 pub mod SRR {
6505 pub const offset: u32 = 22;
6506 pub const mask: u32 = 0x01 << offset;
6507 pub mod R {}
6508 pub mod W {}
6509 pub mod RW {}
6510 }
6511 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
6512 pub mod CODE {
6513 pub const offset: u32 = 24;
6514 pub const mask: u32 = 0x0f << offset;
6515 pub mod R {}
6516 pub mod W {}
6517 pub mod RW {}
6518 }
6519 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
6520 pub mod ESI {
6521 pub const offset: u32 = 29;
6522 pub const mask: u32 = 0x01 << offset;
6523 pub mod R {}
6524 pub mod W {}
6525 pub mod RW {}
6526 }
6527 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
6528 pub mod BRS {
6529 pub const offset: u32 = 30;
6530 pub const mask: u32 = 0x01 << offset;
6531 pub mod R {}
6532 pub mod W {}
6533 pub mod RW {}
6534 }
6535 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
6536 pub mod EDL {
6537 pub const offset: u32 = 31;
6538 pub const mask: u32 = 0x01 << offset;
6539 pub mod R {}
6540 pub mod W {}
6541 pub mod RW {}
6542 }
6543}
6544#[doc = "Message Buffer 26 ID Register"]
6545pub mod ID26 {
6546 #[doc = "Contains extended (LOW word) identifier of message buffer."]
6547 pub mod EXT {
6548 pub const offset: u32 = 0;
6549 pub const mask: u32 = 0x0003_ffff << offset;
6550 pub mod R {}
6551 pub mod W {}
6552 pub mod RW {}
6553 }
6554 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
6555 pub mod STD {
6556 pub const offset: u32 = 18;
6557 pub const mask: u32 = 0x07ff << offset;
6558 pub mod R {}
6559 pub mod W {}
6560 pub mod RW {}
6561 }
6562 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
6563 pub mod PRIO {
6564 pub const offset: u32 = 29;
6565 pub const mask: u32 = 0x07 << offset;
6566 pub mod R {}
6567 pub mod W {}
6568 pub mod RW {}
6569 }
6570}
6571#[doc = "Message Buffer 10 WORD_32B Register"]
6572pub mod MB10_32B_WORD4 {
6573 #[doc = "Data byte 0 of Rx/Tx frame."]
6574 pub mod DATA_BYTE_19 {
6575 pub const offset: u32 = 0;
6576 pub const mask: u32 = 0xff << offset;
6577 pub mod R {}
6578 pub mod W {}
6579 pub mod RW {}
6580 }
6581 #[doc = "Data byte 1 of Rx/Tx frame."]
6582 pub mod DATA_BYTE_18 {
6583 pub const offset: u32 = 8;
6584 pub const mask: u32 = 0xff << offset;
6585 pub mod R {}
6586 pub mod W {}
6587 pub mod RW {}
6588 }
6589 #[doc = "Data byte 2 of Rx/Tx frame."]
6590 pub mod DATA_BYTE_17 {
6591 pub const offset: u32 = 16;
6592 pub const mask: u32 = 0xff << offset;
6593 pub mod R {}
6594 pub mod W {}
6595 pub mod RW {}
6596 }
6597 #[doc = "Data byte 3 of Rx/Tx frame."]
6598 pub mod DATA_BYTE_16 {
6599 pub const offset: u32 = 24;
6600 pub const mask: u32 = 0xff << offset;
6601 pub mod R {}
6602 pub mod W {}
6603 pub mod RW {}
6604 }
6605}
6606#[doc = "Message Buffer 10 WORD_32B Register"]
6607pub mod MB10_32B_WORD5 {
6608 #[doc = "Data byte 0 of Rx/Tx frame."]
6609 pub mod DATA_BYTE_23 {
6610 pub const offset: u32 = 0;
6611 pub const mask: u32 = 0xff << offset;
6612 pub mod R {}
6613 pub mod W {}
6614 pub mod RW {}
6615 }
6616 #[doc = "Data byte 1 of Rx/Tx frame."]
6617 pub mod DATA_BYTE_22 {
6618 pub const offset: u32 = 8;
6619 pub const mask: u32 = 0xff << offset;
6620 pub mod R {}
6621 pub mod W {}
6622 pub mod RW {}
6623 }
6624 #[doc = "Data byte 2 of Rx/Tx frame."]
6625 pub mod DATA_BYTE_21 {
6626 pub const offset: u32 = 16;
6627 pub const mask: u32 = 0xff << offset;
6628 pub mod R {}
6629 pub mod W {}
6630 pub mod RW {}
6631 }
6632 #[doc = "Data byte 3 of Rx/Tx frame."]
6633 pub mod DATA_BYTE_20 {
6634 pub const offset: u32 = 24;
6635 pub const mask: u32 = 0xff << offset;
6636 pub mod R {}
6637 pub mod W {}
6638 pub mod RW {}
6639 }
6640}
6641#[doc = "Message Buffer 27 CS Register"]
6642pub mod CS27 {
6643 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
6644 pub mod TIME_STAMP {
6645 pub const offset: u32 = 0;
6646 pub const mask: u32 = 0xffff << offset;
6647 pub mod R {}
6648 pub mod W {}
6649 pub mod RW {}
6650 }
6651 #[doc = "Length of the data to be stored/transmitted."]
6652 pub mod DLC {
6653 pub const offset: u32 = 16;
6654 pub const mask: u32 = 0x0f << offset;
6655 pub mod R {}
6656 pub mod W {}
6657 pub mod RW {}
6658 }
6659 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
6660 pub mod RTR {
6661 pub const offset: u32 = 20;
6662 pub const mask: u32 = 0x01 << offset;
6663 pub mod R {}
6664 pub mod W {}
6665 pub mod RW {}
6666 }
6667 #[doc = "ID Extended. One/zero for extended/standard format frame."]
6668 pub mod IDE {
6669 pub const offset: u32 = 21;
6670 pub const mask: u32 = 0x01 << offset;
6671 pub mod R {}
6672 pub mod W {}
6673 pub mod RW {}
6674 }
6675 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
6676 pub mod SRR {
6677 pub const offset: u32 = 22;
6678 pub const mask: u32 = 0x01 << offset;
6679 pub mod R {}
6680 pub mod W {}
6681 pub mod RW {}
6682 }
6683 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
6684 pub mod CODE {
6685 pub const offset: u32 = 24;
6686 pub const mask: u32 = 0x0f << offset;
6687 pub mod R {}
6688 pub mod W {}
6689 pub mod RW {}
6690 }
6691 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
6692 pub mod ESI {
6693 pub const offset: u32 = 29;
6694 pub const mask: u32 = 0x01 << offset;
6695 pub mod R {}
6696 pub mod W {}
6697 pub mod RW {}
6698 }
6699 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
6700 pub mod BRS {
6701 pub const offset: u32 = 30;
6702 pub const mask: u32 = 0x01 << offset;
6703 pub mod R {}
6704 pub mod W {}
6705 pub mod RW {}
6706 }
6707 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
6708 pub mod EDL {
6709 pub const offset: u32 = 31;
6710 pub const mask: u32 = 0x01 << offset;
6711 pub mod R {}
6712 pub mod W {}
6713 pub mod RW {}
6714 }
6715}
6716#[doc = "Message Buffer 27 ID Register"]
6717pub mod ID27 {
6718 #[doc = "Contains extended (LOW word) identifier of message buffer."]
6719 pub mod EXT {
6720 pub const offset: u32 = 0;
6721 pub const mask: u32 = 0x0003_ffff << offset;
6722 pub mod R {}
6723 pub mod W {}
6724 pub mod RW {}
6725 }
6726 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
6727 pub mod STD {
6728 pub const offset: u32 = 18;
6729 pub const mask: u32 = 0x07ff << offset;
6730 pub mod R {}
6731 pub mod W {}
6732 pub mod RW {}
6733 }
6734 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
6735 pub mod PRIO {
6736 pub const offset: u32 = 29;
6737 pub const mask: u32 = 0x07 << offset;
6738 pub mod R {}
6739 pub mod W {}
6740 pub mod RW {}
6741 }
6742}
6743#[doc = "Message Buffer 11 CS Register"]
6744pub mod MB11_32B_CS {
6745 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
6746 pub mod TIME_STAMP {
6747 pub const offset: u32 = 0;
6748 pub const mask: u32 = 0xffff << offset;
6749 pub mod R {}
6750 pub mod W {}
6751 pub mod RW {}
6752 }
6753 #[doc = "Length of the data to be stored/transmitted."]
6754 pub mod DLC {
6755 pub const offset: u32 = 16;
6756 pub const mask: u32 = 0x0f << offset;
6757 pub mod R {}
6758 pub mod W {}
6759 pub mod RW {}
6760 }
6761 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
6762 pub mod RTR {
6763 pub const offset: u32 = 20;
6764 pub const mask: u32 = 0x01 << offset;
6765 pub mod R {}
6766 pub mod W {}
6767 pub mod RW {}
6768 }
6769 #[doc = "ID Extended. One/zero for extended/standard format frame."]
6770 pub mod IDE {
6771 pub const offset: u32 = 21;
6772 pub const mask: u32 = 0x01 << offset;
6773 pub mod R {}
6774 pub mod W {}
6775 pub mod RW {}
6776 }
6777 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
6778 pub mod SRR {
6779 pub const offset: u32 = 22;
6780 pub const mask: u32 = 0x01 << offset;
6781 pub mod R {}
6782 pub mod W {}
6783 pub mod RW {}
6784 }
6785 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
6786 pub mod CODE {
6787 pub const offset: u32 = 24;
6788 pub const mask: u32 = 0x0f << offset;
6789 pub mod R {}
6790 pub mod W {}
6791 pub mod RW {}
6792 }
6793 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
6794 pub mod ESI {
6795 pub const offset: u32 = 29;
6796 pub const mask: u32 = 0x01 << offset;
6797 pub mod R {}
6798 pub mod W {}
6799 pub mod RW {}
6800 }
6801 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
6802 pub mod BRS {
6803 pub const offset: u32 = 30;
6804 pub const mask: u32 = 0x01 << offset;
6805 pub mod R {}
6806 pub mod W {}
6807 pub mod RW {}
6808 }
6809 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
6810 pub mod EDL {
6811 pub const offset: u32 = 31;
6812 pub const mask: u32 = 0x01 << offset;
6813 pub mod R {}
6814 pub mod W {}
6815 pub mod RW {}
6816 }
6817}
6818#[doc = "Message Buffer 11 ID Register"]
6819pub mod MB11_32B_ID {
6820 #[doc = "Contains extended (LOW word) identifier of message buffer."]
6821 pub mod EXT {
6822 pub const offset: u32 = 0;
6823 pub const mask: u32 = 0x0003_ffff << offset;
6824 pub mod R {}
6825 pub mod W {}
6826 pub mod RW {}
6827 }
6828 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
6829 pub mod STD {
6830 pub const offset: u32 = 18;
6831 pub const mask: u32 = 0x07ff << offset;
6832 pub mod R {}
6833 pub mod W {}
6834 pub mod RW {}
6835 }
6836 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
6837 pub mod PRIO {
6838 pub const offset: u32 = 29;
6839 pub const mask: u32 = 0x07 << offset;
6840 pub mod R {}
6841 pub mod W {}
6842 pub mod RW {}
6843 }
6844}
6845#[doc = "Message Buffer 28 CS Register"]
6846pub mod CS28 {
6847 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
6848 pub mod TIME_STAMP {
6849 pub const offset: u32 = 0;
6850 pub const mask: u32 = 0xffff << offset;
6851 pub mod R {}
6852 pub mod W {}
6853 pub mod RW {}
6854 }
6855 #[doc = "Length of the data to be stored/transmitted."]
6856 pub mod DLC {
6857 pub const offset: u32 = 16;
6858 pub const mask: u32 = 0x0f << offset;
6859 pub mod R {}
6860 pub mod W {}
6861 pub mod RW {}
6862 }
6863 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
6864 pub mod RTR {
6865 pub const offset: u32 = 20;
6866 pub const mask: u32 = 0x01 << offset;
6867 pub mod R {}
6868 pub mod W {}
6869 pub mod RW {}
6870 }
6871 #[doc = "ID Extended. One/zero for extended/standard format frame."]
6872 pub mod IDE {
6873 pub const offset: u32 = 21;
6874 pub const mask: u32 = 0x01 << offset;
6875 pub mod R {}
6876 pub mod W {}
6877 pub mod RW {}
6878 }
6879 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
6880 pub mod SRR {
6881 pub const offset: u32 = 22;
6882 pub const mask: u32 = 0x01 << offset;
6883 pub mod R {}
6884 pub mod W {}
6885 pub mod RW {}
6886 }
6887 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
6888 pub mod CODE {
6889 pub const offset: u32 = 24;
6890 pub const mask: u32 = 0x0f << offset;
6891 pub mod R {}
6892 pub mod W {}
6893 pub mod RW {}
6894 }
6895 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
6896 pub mod ESI {
6897 pub const offset: u32 = 29;
6898 pub const mask: u32 = 0x01 << offset;
6899 pub mod R {}
6900 pub mod W {}
6901 pub mod RW {}
6902 }
6903 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
6904 pub mod BRS {
6905 pub const offset: u32 = 30;
6906 pub const mask: u32 = 0x01 << offset;
6907 pub mod R {}
6908 pub mod W {}
6909 pub mod RW {}
6910 }
6911 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
6912 pub mod EDL {
6913 pub const offset: u32 = 31;
6914 pub const mask: u32 = 0x01 << offset;
6915 pub mod R {}
6916 pub mod W {}
6917 pub mod RW {}
6918 }
6919}
6920#[doc = "Message Buffer 28 ID Register"]
6921pub mod ID28 {
6922 #[doc = "Contains extended (LOW word) identifier of message buffer."]
6923 pub mod EXT {
6924 pub const offset: u32 = 0;
6925 pub const mask: u32 = 0x0003_ffff << offset;
6926 pub mod R {}
6927 pub mod W {}
6928 pub mod RW {}
6929 }
6930 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
6931 pub mod STD {
6932 pub const offset: u32 = 18;
6933 pub const mask: u32 = 0x07ff << offset;
6934 pub mod R {}
6935 pub mod W {}
6936 pub mod RW {}
6937 }
6938 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
6939 pub mod PRIO {
6940 pub const offset: u32 = 29;
6941 pub const mask: u32 = 0x07 << offset;
6942 pub mod R {}
6943 pub mod W {}
6944 pub mod RW {}
6945 }
6946}
6947#[doc = "Message Buffer 11 WORD_32B Register"]
6948pub mod MB11_32B_WORD2 {
6949 #[doc = "Data byte 0 of Rx/Tx frame."]
6950 pub mod DATA_BYTE_11 {
6951 pub const offset: u32 = 0;
6952 pub const mask: u32 = 0xff << offset;
6953 pub mod R {}
6954 pub mod W {}
6955 pub mod RW {}
6956 }
6957 #[doc = "Data byte 1 of Rx/Tx frame."]
6958 pub mod DATA_BYTE_10 {
6959 pub const offset: u32 = 8;
6960 pub const mask: u32 = 0xff << offset;
6961 pub mod R {}
6962 pub mod W {}
6963 pub mod RW {}
6964 }
6965 #[doc = "Data byte 2 of Rx/Tx frame."]
6966 pub mod DATA_BYTE_9 {
6967 pub const offset: u32 = 16;
6968 pub const mask: u32 = 0xff << offset;
6969 pub mod R {}
6970 pub mod W {}
6971 pub mod RW {}
6972 }
6973 #[doc = "Data byte 3 of Rx/Tx frame."]
6974 pub mod DATA_BYTE_8 {
6975 pub const offset: u32 = 24;
6976 pub const mask: u32 = 0xff << offset;
6977 pub mod R {}
6978 pub mod W {}
6979 pub mod RW {}
6980 }
6981}
6982#[doc = "Message Buffer 11 WORD_32B Register"]
6983pub mod MB11_32B_WORD3 {
6984 #[doc = "Data byte 0 of Rx/Tx frame."]
6985 pub mod DATA_BYTE_15 {
6986 pub const offset: u32 = 0;
6987 pub const mask: u32 = 0xff << offset;
6988 pub mod R {}
6989 pub mod W {}
6990 pub mod RW {}
6991 }
6992 #[doc = "Data byte 1 of Rx/Tx frame."]
6993 pub mod DATA_BYTE_14 {
6994 pub const offset: u32 = 8;
6995 pub const mask: u32 = 0xff << offset;
6996 pub mod R {}
6997 pub mod W {}
6998 pub mod RW {}
6999 }
7000 #[doc = "Data byte 2 of Rx/Tx frame."]
7001 pub mod DATA_BYTE_13 {
7002 pub const offset: u32 = 16;
7003 pub const mask: u32 = 0xff << offset;
7004 pub mod R {}
7005 pub mod W {}
7006 pub mod RW {}
7007 }
7008 #[doc = "Data byte 3 of Rx/Tx frame."]
7009 pub mod DATA_BYTE_12 {
7010 pub const offset: u32 = 24;
7011 pub const mask: u32 = 0xff << offset;
7012 pub mod R {}
7013 pub mod W {}
7014 pub mod RW {}
7015 }
7016}
7017#[doc = "Message Buffer 29 CS Register"]
7018pub mod CS29 {
7019 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
7020 pub mod TIME_STAMP {
7021 pub const offset: u32 = 0;
7022 pub const mask: u32 = 0xffff << offset;
7023 pub mod R {}
7024 pub mod W {}
7025 pub mod RW {}
7026 }
7027 #[doc = "Length of the data to be stored/transmitted."]
7028 pub mod DLC {
7029 pub const offset: u32 = 16;
7030 pub const mask: u32 = 0x0f << offset;
7031 pub mod R {}
7032 pub mod W {}
7033 pub mod RW {}
7034 }
7035 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
7036 pub mod RTR {
7037 pub const offset: u32 = 20;
7038 pub const mask: u32 = 0x01 << offset;
7039 pub mod R {}
7040 pub mod W {}
7041 pub mod RW {}
7042 }
7043 #[doc = "ID Extended. One/zero for extended/standard format frame."]
7044 pub mod IDE {
7045 pub const offset: u32 = 21;
7046 pub const mask: u32 = 0x01 << offset;
7047 pub mod R {}
7048 pub mod W {}
7049 pub mod RW {}
7050 }
7051 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
7052 pub mod SRR {
7053 pub const offset: u32 = 22;
7054 pub const mask: u32 = 0x01 << offset;
7055 pub mod R {}
7056 pub mod W {}
7057 pub mod RW {}
7058 }
7059 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
7060 pub mod CODE {
7061 pub const offset: u32 = 24;
7062 pub const mask: u32 = 0x0f << offset;
7063 pub mod R {}
7064 pub mod W {}
7065 pub mod RW {}
7066 }
7067 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
7068 pub mod ESI {
7069 pub const offset: u32 = 29;
7070 pub const mask: u32 = 0x01 << offset;
7071 pub mod R {}
7072 pub mod W {}
7073 pub mod RW {}
7074 }
7075 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
7076 pub mod BRS {
7077 pub const offset: u32 = 30;
7078 pub const mask: u32 = 0x01 << offset;
7079 pub mod R {}
7080 pub mod W {}
7081 pub mod RW {}
7082 }
7083 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
7084 pub mod EDL {
7085 pub const offset: u32 = 31;
7086 pub const mask: u32 = 0x01 << offset;
7087 pub mod R {}
7088 pub mod W {}
7089 pub mod RW {}
7090 }
7091}
7092#[doc = "Message Buffer 29 ID Register"]
7093pub mod ID29 {
7094 #[doc = "Contains extended (LOW word) identifier of message buffer."]
7095 pub mod EXT {
7096 pub const offset: u32 = 0;
7097 pub const mask: u32 = 0x0003_ffff << offset;
7098 pub mod R {}
7099 pub mod W {}
7100 pub mod RW {}
7101 }
7102 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
7103 pub mod STD {
7104 pub const offset: u32 = 18;
7105 pub const mask: u32 = 0x07ff << offset;
7106 pub mod R {}
7107 pub mod W {}
7108 pub mod RW {}
7109 }
7110 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
7111 pub mod PRIO {
7112 pub const offset: u32 = 29;
7113 pub const mask: u32 = 0x07 << offset;
7114 pub mod R {}
7115 pub mod W {}
7116 pub mod RW {}
7117 }
7118}
7119#[doc = "Message Buffer 11 WORD_32B Register"]
7120pub mod MB11_32B_WORD6 {
7121 #[doc = "Data byte 0 of Rx/Tx frame."]
7122 pub mod DATA_BYTE_27 {
7123 pub const offset: u32 = 0;
7124 pub const mask: u32 = 0xff << offset;
7125 pub mod R {}
7126 pub mod W {}
7127 pub mod RW {}
7128 }
7129 #[doc = "Data byte 1 of Rx/Tx frame."]
7130 pub mod DATA_BYTE_26 {
7131 pub const offset: u32 = 8;
7132 pub const mask: u32 = 0xff << offset;
7133 pub mod R {}
7134 pub mod W {}
7135 pub mod RW {}
7136 }
7137 #[doc = "Data byte 2 of Rx/Tx frame."]
7138 pub mod DATA_BYTE_25 {
7139 pub const offset: u32 = 16;
7140 pub const mask: u32 = 0xff << offset;
7141 pub mod R {}
7142 pub mod W {}
7143 pub mod RW {}
7144 }
7145 #[doc = "Data byte 3 of Rx/Tx frame."]
7146 pub mod DATA_BYTE_24 {
7147 pub const offset: u32 = 24;
7148 pub const mask: u32 = 0xff << offset;
7149 pub mod R {}
7150 pub mod W {}
7151 pub mod RW {}
7152 }
7153}
7154#[doc = "Message Buffer 11 WORD_32B Register"]
7155pub mod MB11_32B_WORD7 {
7156 #[doc = "Data byte 0 of Rx/Tx frame."]
7157 pub mod DATA_BYTE_31 {
7158 pub const offset: u32 = 0;
7159 pub const mask: u32 = 0xff << offset;
7160 pub mod R {}
7161 pub mod W {}
7162 pub mod RW {}
7163 }
7164 #[doc = "Data byte 1 of Rx/Tx frame."]
7165 pub mod DATA_BYTE_30 {
7166 pub const offset: u32 = 8;
7167 pub const mask: u32 = 0xff << offset;
7168 pub mod R {}
7169 pub mod W {}
7170 pub mod RW {}
7171 }
7172 #[doc = "Data byte 2 of Rx/Tx frame."]
7173 pub mod DATA_BYTE_29 {
7174 pub const offset: u32 = 16;
7175 pub const mask: u32 = 0xff << offset;
7176 pub mod R {}
7177 pub mod W {}
7178 pub mod RW {}
7179 }
7180 #[doc = "Data byte 3 of Rx/Tx frame."]
7181 pub mod DATA_BYTE_28 {
7182 pub const offset: u32 = 24;
7183 pub const mask: u32 = 0xff << offset;
7184 pub mod R {}
7185 pub mod W {}
7186 pub mod RW {}
7187 }
7188}
7189#[doc = "Message Buffer 30 CS Register"]
7190pub mod CS30 {
7191 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
7192 pub mod TIME_STAMP {
7193 pub const offset: u32 = 0;
7194 pub const mask: u32 = 0xffff << offset;
7195 pub mod R {}
7196 pub mod W {}
7197 pub mod RW {}
7198 }
7199 #[doc = "Length of the data to be stored/transmitted."]
7200 pub mod DLC {
7201 pub const offset: u32 = 16;
7202 pub const mask: u32 = 0x0f << offset;
7203 pub mod R {}
7204 pub mod W {}
7205 pub mod RW {}
7206 }
7207 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
7208 pub mod RTR {
7209 pub const offset: u32 = 20;
7210 pub const mask: u32 = 0x01 << offset;
7211 pub mod R {}
7212 pub mod W {}
7213 pub mod RW {}
7214 }
7215 #[doc = "ID Extended. One/zero for extended/standard format frame."]
7216 pub mod IDE {
7217 pub const offset: u32 = 21;
7218 pub const mask: u32 = 0x01 << offset;
7219 pub mod R {}
7220 pub mod W {}
7221 pub mod RW {}
7222 }
7223 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
7224 pub mod SRR {
7225 pub const offset: u32 = 22;
7226 pub const mask: u32 = 0x01 << offset;
7227 pub mod R {}
7228 pub mod W {}
7229 pub mod RW {}
7230 }
7231 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
7232 pub mod CODE {
7233 pub const offset: u32 = 24;
7234 pub const mask: u32 = 0x0f << offset;
7235 pub mod R {}
7236 pub mod W {}
7237 pub mod RW {}
7238 }
7239 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
7240 pub mod ESI {
7241 pub const offset: u32 = 29;
7242 pub const mask: u32 = 0x01 << offset;
7243 pub mod R {}
7244 pub mod W {}
7245 pub mod RW {}
7246 }
7247 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
7248 pub mod BRS {
7249 pub const offset: u32 = 30;
7250 pub const mask: u32 = 0x01 << offset;
7251 pub mod R {}
7252 pub mod W {}
7253 pub mod RW {}
7254 }
7255 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
7256 pub mod EDL {
7257 pub const offset: u32 = 31;
7258 pub const mask: u32 = 0x01 << offset;
7259 pub mod R {}
7260 pub mod W {}
7261 pub mod RW {}
7262 }
7263}
7264#[doc = "Message Buffer 30 ID Register"]
7265pub mod ID30 {
7266 #[doc = "Contains extended (LOW word) identifier of message buffer."]
7267 pub mod EXT {
7268 pub const offset: u32 = 0;
7269 pub const mask: u32 = 0x0003_ffff << offset;
7270 pub mod R {}
7271 pub mod W {}
7272 pub mod RW {}
7273 }
7274 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
7275 pub mod STD {
7276 pub const offset: u32 = 18;
7277 pub const mask: u32 = 0x07ff << offset;
7278 pub mod R {}
7279 pub mod W {}
7280 pub mod RW {}
7281 }
7282 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
7283 pub mod PRIO {
7284 pub const offset: u32 = 29;
7285 pub const mask: u32 = 0x07 << offset;
7286 pub mod R {}
7287 pub mod W {}
7288 pub mod RW {}
7289 }
7290}
7291#[doc = "Message Buffer 12 WORD_32B Register"]
7292pub mod MB12_32B_WORD0 {
7293 #[doc = "Data byte 0 of Rx/Tx frame."]
7294 pub mod DATA_BYTE_3 {
7295 pub const offset: u32 = 0;
7296 pub const mask: u32 = 0xff << offset;
7297 pub mod R {}
7298 pub mod W {}
7299 pub mod RW {}
7300 }
7301 #[doc = "Data byte 1 of Rx/Tx frame."]
7302 pub mod DATA_BYTE_2 {
7303 pub const offset: u32 = 8;
7304 pub const mask: u32 = 0xff << offset;
7305 pub mod R {}
7306 pub mod W {}
7307 pub mod RW {}
7308 }
7309 #[doc = "Data byte 2 of Rx/Tx frame."]
7310 pub mod DATA_BYTE_1 {
7311 pub const offset: u32 = 16;
7312 pub const mask: u32 = 0xff << offset;
7313 pub mod R {}
7314 pub mod W {}
7315 pub mod RW {}
7316 }
7317 #[doc = "Data byte 3 of Rx/Tx frame."]
7318 pub mod DATA_BYTE_0 {
7319 pub const offset: u32 = 24;
7320 pub const mask: u32 = 0xff << offset;
7321 pub mod R {}
7322 pub mod W {}
7323 pub mod RW {}
7324 }
7325}
7326#[doc = "Message Buffer 12 WORD_32B Register"]
7327pub mod MB12_32B_WORD1 {
7328 #[doc = "Data byte 0 of Rx/Tx frame."]
7329 pub mod DATA_BYTE_7 {
7330 pub const offset: u32 = 0;
7331 pub const mask: u32 = 0xff << offset;
7332 pub mod R {}
7333 pub mod W {}
7334 pub mod RW {}
7335 }
7336 #[doc = "Data byte 1 of Rx/Tx frame."]
7337 pub mod DATA_BYTE_6 {
7338 pub const offset: u32 = 8;
7339 pub const mask: u32 = 0xff << offset;
7340 pub mod R {}
7341 pub mod W {}
7342 pub mod RW {}
7343 }
7344 #[doc = "Data byte 2 of Rx/Tx frame."]
7345 pub mod DATA_BYTE_5 {
7346 pub const offset: u32 = 16;
7347 pub const mask: u32 = 0xff << offset;
7348 pub mod R {}
7349 pub mod W {}
7350 pub mod RW {}
7351 }
7352 #[doc = "Data byte 3 of Rx/Tx frame."]
7353 pub mod DATA_BYTE_4 {
7354 pub const offset: u32 = 24;
7355 pub const mask: u32 = 0xff << offset;
7356 pub mod R {}
7357 pub mod W {}
7358 pub mod RW {}
7359 }
7360}
7361#[doc = "Message Buffer 31 CS Register"]
7362pub mod CS31 {
7363 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
7364 pub mod TIME_STAMP {
7365 pub const offset: u32 = 0;
7366 pub const mask: u32 = 0xffff << offset;
7367 pub mod R {}
7368 pub mod W {}
7369 pub mod RW {}
7370 }
7371 #[doc = "Length of the data to be stored/transmitted."]
7372 pub mod DLC {
7373 pub const offset: u32 = 16;
7374 pub const mask: u32 = 0x0f << offset;
7375 pub mod R {}
7376 pub mod W {}
7377 pub mod RW {}
7378 }
7379 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
7380 pub mod RTR {
7381 pub const offset: u32 = 20;
7382 pub const mask: u32 = 0x01 << offset;
7383 pub mod R {}
7384 pub mod W {}
7385 pub mod RW {}
7386 }
7387 #[doc = "ID Extended. One/zero for extended/standard format frame."]
7388 pub mod IDE {
7389 pub const offset: u32 = 21;
7390 pub const mask: u32 = 0x01 << offset;
7391 pub mod R {}
7392 pub mod W {}
7393 pub mod RW {}
7394 }
7395 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
7396 pub mod SRR {
7397 pub const offset: u32 = 22;
7398 pub const mask: u32 = 0x01 << offset;
7399 pub mod R {}
7400 pub mod W {}
7401 pub mod RW {}
7402 }
7403 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
7404 pub mod CODE {
7405 pub const offset: u32 = 24;
7406 pub const mask: u32 = 0x0f << offset;
7407 pub mod R {}
7408 pub mod W {}
7409 pub mod RW {}
7410 }
7411 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
7412 pub mod ESI {
7413 pub const offset: u32 = 29;
7414 pub const mask: u32 = 0x01 << offset;
7415 pub mod R {}
7416 pub mod W {}
7417 pub mod RW {}
7418 }
7419 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
7420 pub mod BRS {
7421 pub const offset: u32 = 30;
7422 pub const mask: u32 = 0x01 << offset;
7423 pub mod R {}
7424 pub mod W {}
7425 pub mod RW {}
7426 }
7427 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
7428 pub mod EDL {
7429 pub const offset: u32 = 31;
7430 pub const mask: u32 = 0x01 << offset;
7431 pub mod R {}
7432 pub mod W {}
7433 pub mod RW {}
7434 }
7435}
7436#[doc = "Message Buffer 31 ID Register"]
7437pub mod ID31 {
7438 #[doc = "Contains extended (LOW word) identifier of message buffer."]
7439 pub mod EXT {
7440 pub const offset: u32 = 0;
7441 pub const mask: u32 = 0x0003_ffff << offset;
7442 pub mod R {}
7443 pub mod W {}
7444 pub mod RW {}
7445 }
7446 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
7447 pub mod STD {
7448 pub const offset: u32 = 18;
7449 pub const mask: u32 = 0x07ff << offset;
7450 pub mod R {}
7451 pub mod W {}
7452 pub mod RW {}
7453 }
7454 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
7455 pub mod PRIO {
7456 pub const offset: u32 = 29;
7457 pub const mask: u32 = 0x07 << offset;
7458 pub mod R {}
7459 pub mod W {}
7460 pub mod RW {}
7461 }
7462}
7463#[doc = "Message Buffer 12 WORD_32B Register"]
7464pub mod MB12_32B_WORD4 {
7465 #[doc = "Data byte 0 of Rx/Tx frame."]
7466 pub mod DATA_BYTE_19 {
7467 pub const offset: u32 = 0;
7468 pub const mask: u32 = 0xff << offset;
7469 pub mod R {}
7470 pub mod W {}
7471 pub mod RW {}
7472 }
7473 #[doc = "Data byte 1 of Rx/Tx frame."]
7474 pub mod DATA_BYTE_18 {
7475 pub const offset: u32 = 8;
7476 pub const mask: u32 = 0xff << offset;
7477 pub mod R {}
7478 pub mod W {}
7479 pub mod RW {}
7480 }
7481 #[doc = "Data byte 2 of Rx/Tx frame."]
7482 pub mod DATA_BYTE_17 {
7483 pub const offset: u32 = 16;
7484 pub const mask: u32 = 0xff << offset;
7485 pub mod R {}
7486 pub mod W {}
7487 pub mod RW {}
7488 }
7489 #[doc = "Data byte 3 of Rx/Tx frame."]
7490 pub mod DATA_BYTE_16 {
7491 pub const offset: u32 = 24;
7492 pub const mask: u32 = 0xff << offset;
7493 pub mod R {}
7494 pub mod W {}
7495 pub mod RW {}
7496 }
7497}
7498#[doc = "Message Buffer 12 WORD_32B Register"]
7499pub mod MB12_32B_WORD5 {
7500 #[doc = "Data byte 0 of Rx/Tx frame."]
7501 pub mod DATA_BYTE_23 {
7502 pub const offset: u32 = 0;
7503 pub const mask: u32 = 0xff << offset;
7504 pub mod R {}
7505 pub mod W {}
7506 pub mod RW {}
7507 }
7508 #[doc = "Data byte 1 of Rx/Tx frame."]
7509 pub mod DATA_BYTE_22 {
7510 pub const offset: u32 = 8;
7511 pub const mask: u32 = 0xff << offset;
7512 pub mod R {}
7513 pub mod W {}
7514 pub mod RW {}
7515 }
7516 #[doc = "Data byte 2 of Rx/Tx frame."]
7517 pub mod DATA_BYTE_21 {
7518 pub const offset: u32 = 16;
7519 pub const mask: u32 = 0xff << offset;
7520 pub mod R {}
7521 pub mod W {}
7522 pub mod RW {}
7523 }
7524 #[doc = "Data byte 3 of Rx/Tx frame."]
7525 pub mod DATA_BYTE_20 {
7526 pub const offset: u32 = 24;
7527 pub const mask: u32 = 0xff << offset;
7528 pub mod R {}
7529 pub mod W {}
7530 pub mod RW {}
7531 }
7532}
7533#[doc = "Message Buffer 32 CS Register"]
7534pub mod CS32 {
7535 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
7536 pub mod TIME_STAMP {
7537 pub const offset: u32 = 0;
7538 pub const mask: u32 = 0xffff << offset;
7539 pub mod R {}
7540 pub mod W {}
7541 pub mod RW {}
7542 }
7543 #[doc = "Length of the data to be stored/transmitted."]
7544 pub mod DLC {
7545 pub const offset: u32 = 16;
7546 pub const mask: u32 = 0x0f << offset;
7547 pub mod R {}
7548 pub mod W {}
7549 pub mod RW {}
7550 }
7551 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
7552 pub mod RTR {
7553 pub const offset: u32 = 20;
7554 pub const mask: u32 = 0x01 << offset;
7555 pub mod R {}
7556 pub mod W {}
7557 pub mod RW {}
7558 }
7559 #[doc = "ID Extended. One/zero for extended/standard format frame."]
7560 pub mod IDE {
7561 pub const offset: u32 = 21;
7562 pub const mask: u32 = 0x01 << offset;
7563 pub mod R {}
7564 pub mod W {}
7565 pub mod RW {}
7566 }
7567 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
7568 pub mod SRR {
7569 pub const offset: u32 = 22;
7570 pub const mask: u32 = 0x01 << offset;
7571 pub mod R {}
7572 pub mod W {}
7573 pub mod RW {}
7574 }
7575 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
7576 pub mod CODE {
7577 pub const offset: u32 = 24;
7578 pub const mask: u32 = 0x0f << offset;
7579 pub mod R {}
7580 pub mod W {}
7581 pub mod RW {}
7582 }
7583 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
7584 pub mod ESI {
7585 pub const offset: u32 = 29;
7586 pub const mask: u32 = 0x01 << offset;
7587 pub mod R {}
7588 pub mod W {}
7589 pub mod RW {}
7590 }
7591 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
7592 pub mod BRS {
7593 pub const offset: u32 = 30;
7594 pub const mask: u32 = 0x01 << offset;
7595 pub mod R {}
7596 pub mod W {}
7597 pub mod RW {}
7598 }
7599 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
7600 pub mod EDL {
7601 pub const offset: u32 = 31;
7602 pub const mask: u32 = 0x01 << offset;
7603 pub mod R {}
7604 pub mod W {}
7605 pub mod RW {}
7606 }
7607}
7608#[doc = "Message Buffer 32 ID Register"]
7609pub mod ID32 {
7610 #[doc = "Contains extended (LOW word) identifier of message buffer."]
7611 pub mod EXT {
7612 pub const offset: u32 = 0;
7613 pub const mask: u32 = 0x0003_ffff << offset;
7614 pub mod R {}
7615 pub mod W {}
7616 pub mod RW {}
7617 }
7618 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
7619 pub mod STD {
7620 pub const offset: u32 = 18;
7621 pub const mask: u32 = 0x07ff << offset;
7622 pub mod R {}
7623 pub mod W {}
7624 pub mod RW {}
7625 }
7626 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
7627 pub mod PRIO {
7628 pub const offset: u32 = 29;
7629 pub const mask: u32 = 0x07 << offset;
7630 pub mod R {}
7631 pub mod W {}
7632 pub mod RW {}
7633 }
7634}
7635#[doc = "Message Buffer 13 CS Register"]
7636pub mod MB13_32B_CS {
7637 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
7638 pub mod TIME_STAMP {
7639 pub const offset: u32 = 0;
7640 pub const mask: u32 = 0xffff << offset;
7641 pub mod R {}
7642 pub mod W {}
7643 pub mod RW {}
7644 }
7645 #[doc = "Length of the data to be stored/transmitted."]
7646 pub mod DLC {
7647 pub const offset: u32 = 16;
7648 pub const mask: u32 = 0x0f << offset;
7649 pub mod R {}
7650 pub mod W {}
7651 pub mod RW {}
7652 }
7653 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
7654 pub mod RTR {
7655 pub const offset: u32 = 20;
7656 pub const mask: u32 = 0x01 << offset;
7657 pub mod R {}
7658 pub mod W {}
7659 pub mod RW {}
7660 }
7661 #[doc = "ID Extended. One/zero for extended/standard format frame."]
7662 pub mod IDE {
7663 pub const offset: u32 = 21;
7664 pub const mask: u32 = 0x01 << offset;
7665 pub mod R {}
7666 pub mod W {}
7667 pub mod RW {}
7668 }
7669 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
7670 pub mod SRR {
7671 pub const offset: u32 = 22;
7672 pub const mask: u32 = 0x01 << offset;
7673 pub mod R {}
7674 pub mod W {}
7675 pub mod RW {}
7676 }
7677 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
7678 pub mod CODE {
7679 pub const offset: u32 = 24;
7680 pub const mask: u32 = 0x0f << offset;
7681 pub mod R {}
7682 pub mod W {}
7683 pub mod RW {}
7684 }
7685 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
7686 pub mod ESI {
7687 pub const offset: u32 = 29;
7688 pub const mask: u32 = 0x01 << offset;
7689 pub mod R {}
7690 pub mod W {}
7691 pub mod RW {}
7692 }
7693 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
7694 pub mod BRS {
7695 pub const offset: u32 = 30;
7696 pub const mask: u32 = 0x01 << offset;
7697 pub mod R {}
7698 pub mod W {}
7699 pub mod RW {}
7700 }
7701 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
7702 pub mod EDL {
7703 pub const offset: u32 = 31;
7704 pub const mask: u32 = 0x01 << offset;
7705 pub mod R {}
7706 pub mod W {}
7707 pub mod RW {}
7708 }
7709}
7710#[doc = "Message Buffer 13 ID Register"]
7711pub mod MB13_32B_ID {
7712 #[doc = "Contains extended (LOW word) identifier of message buffer."]
7713 pub mod EXT {
7714 pub const offset: u32 = 0;
7715 pub const mask: u32 = 0x0003_ffff << offset;
7716 pub mod R {}
7717 pub mod W {}
7718 pub mod RW {}
7719 }
7720 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
7721 pub mod STD {
7722 pub const offset: u32 = 18;
7723 pub const mask: u32 = 0x07ff << offset;
7724 pub mod R {}
7725 pub mod W {}
7726 pub mod RW {}
7727 }
7728 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
7729 pub mod PRIO {
7730 pub const offset: u32 = 29;
7731 pub const mask: u32 = 0x07 << offset;
7732 pub mod R {}
7733 pub mod W {}
7734 pub mod RW {}
7735 }
7736}
7737#[doc = "Message Buffer 33 CS Register"]
7738pub mod CS33 {
7739 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
7740 pub mod TIME_STAMP {
7741 pub const offset: u32 = 0;
7742 pub const mask: u32 = 0xffff << offset;
7743 pub mod R {}
7744 pub mod W {}
7745 pub mod RW {}
7746 }
7747 #[doc = "Length of the data to be stored/transmitted."]
7748 pub mod DLC {
7749 pub const offset: u32 = 16;
7750 pub const mask: u32 = 0x0f << offset;
7751 pub mod R {}
7752 pub mod W {}
7753 pub mod RW {}
7754 }
7755 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
7756 pub mod RTR {
7757 pub const offset: u32 = 20;
7758 pub const mask: u32 = 0x01 << offset;
7759 pub mod R {}
7760 pub mod W {}
7761 pub mod RW {}
7762 }
7763 #[doc = "ID Extended. One/zero for extended/standard format frame."]
7764 pub mod IDE {
7765 pub const offset: u32 = 21;
7766 pub const mask: u32 = 0x01 << offset;
7767 pub mod R {}
7768 pub mod W {}
7769 pub mod RW {}
7770 }
7771 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
7772 pub mod SRR {
7773 pub const offset: u32 = 22;
7774 pub const mask: u32 = 0x01 << offset;
7775 pub mod R {}
7776 pub mod W {}
7777 pub mod RW {}
7778 }
7779 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
7780 pub mod CODE {
7781 pub const offset: u32 = 24;
7782 pub const mask: u32 = 0x0f << offset;
7783 pub mod R {}
7784 pub mod W {}
7785 pub mod RW {}
7786 }
7787 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
7788 pub mod ESI {
7789 pub const offset: u32 = 29;
7790 pub const mask: u32 = 0x01 << offset;
7791 pub mod R {}
7792 pub mod W {}
7793 pub mod RW {}
7794 }
7795 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
7796 pub mod BRS {
7797 pub const offset: u32 = 30;
7798 pub const mask: u32 = 0x01 << offset;
7799 pub mod R {}
7800 pub mod W {}
7801 pub mod RW {}
7802 }
7803 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
7804 pub mod EDL {
7805 pub const offset: u32 = 31;
7806 pub const mask: u32 = 0x01 << offset;
7807 pub mod R {}
7808 pub mod W {}
7809 pub mod RW {}
7810 }
7811}
7812#[doc = "Message Buffer 33 ID Register"]
7813pub mod ID33 {
7814 #[doc = "Contains extended (LOW word) identifier of message buffer."]
7815 pub mod EXT {
7816 pub const offset: u32 = 0;
7817 pub const mask: u32 = 0x0003_ffff << offset;
7818 pub mod R {}
7819 pub mod W {}
7820 pub mod RW {}
7821 }
7822 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
7823 pub mod STD {
7824 pub const offset: u32 = 18;
7825 pub const mask: u32 = 0x07ff << offset;
7826 pub mod R {}
7827 pub mod W {}
7828 pub mod RW {}
7829 }
7830 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
7831 pub mod PRIO {
7832 pub const offset: u32 = 29;
7833 pub const mask: u32 = 0x07 << offset;
7834 pub mod R {}
7835 pub mod W {}
7836 pub mod RW {}
7837 }
7838}
7839#[doc = "Message Buffer 13 WORD_32B Register"]
7840pub mod MB13_32B_WORD2 {
7841 #[doc = "Data byte 0 of Rx/Tx frame."]
7842 pub mod DATA_BYTE_11 {
7843 pub const offset: u32 = 0;
7844 pub const mask: u32 = 0xff << offset;
7845 pub mod R {}
7846 pub mod W {}
7847 pub mod RW {}
7848 }
7849 #[doc = "Data byte 1 of Rx/Tx frame."]
7850 pub mod DATA_BYTE_10 {
7851 pub const offset: u32 = 8;
7852 pub const mask: u32 = 0xff << offset;
7853 pub mod R {}
7854 pub mod W {}
7855 pub mod RW {}
7856 }
7857 #[doc = "Data byte 2 of Rx/Tx frame."]
7858 pub mod DATA_BYTE_9 {
7859 pub const offset: u32 = 16;
7860 pub const mask: u32 = 0xff << offset;
7861 pub mod R {}
7862 pub mod W {}
7863 pub mod RW {}
7864 }
7865 #[doc = "Data byte 3 of Rx/Tx frame."]
7866 pub mod DATA_BYTE_8 {
7867 pub const offset: u32 = 24;
7868 pub const mask: u32 = 0xff << offset;
7869 pub mod R {}
7870 pub mod W {}
7871 pub mod RW {}
7872 }
7873}
7874#[doc = "Message Buffer 13 WORD_32B Register"]
7875pub mod MB13_32B_WORD3 {
7876 #[doc = "Data byte 0 of Rx/Tx frame."]
7877 pub mod DATA_BYTE_15 {
7878 pub const offset: u32 = 0;
7879 pub const mask: u32 = 0xff << offset;
7880 pub mod R {}
7881 pub mod W {}
7882 pub mod RW {}
7883 }
7884 #[doc = "Data byte 1 of Rx/Tx frame."]
7885 pub mod DATA_BYTE_14 {
7886 pub const offset: u32 = 8;
7887 pub const mask: u32 = 0xff << offset;
7888 pub mod R {}
7889 pub mod W {}
7890 pub mod RW {}
7891 }
7892 #[doc = "Data byte 2 of Rx/Tx frame."]
7893 pub mod DATA_BYTE_13 {
7894 pub const offset: u32 = 16;
7895 pub const mask: u32 = 0xff << offset;
7896 pub mod R {}
7897 pub mod W {}
7898 pub mod RW {}
7899 }
7900 #[doc = "Data byte 3 of Rx/Tx frame."]
7901 pub mod DATA_BYTE_12 {
7902 pub const offset: u32 = 24;
7903 pub const mask: u32 = 0xff << offset;
7904 pub mod R {}
7905 pub mod W {}
7906 pub mod RW {}
7907 }
7908}
7909#[doc = "Message Buffer 34 CS Register"]
7910pub mod CS34 {
7911 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
7912 pub mod TIME_STAMP {
7913 pub const offset: u32 = 0;
7914 pub const mask: u32 = 0xffff << offset;
7915 pub mod R {}
7916 pub mod W {}
7917 pub mod RW {}
7918 }
7919 #[doc = "Length of the data to be stored/transmitted."]
7920 pub mod DLC {
7921 pub const offset: u32 = 16;
7922 pub const mask: u32 = 0x0f << offset;
7923 pub mod R {}
7924 pub mod W {}
7925 pub mod RW {}
7926 }
7927 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
7928 pub mod RTR {
7929 pub const offset: u32 = 20;
7930 pub const mask: u32 = 0x01 << offset;
7931 pub mod R {}
7932 pub mod W {}
7933 pub mod RW {}
7934 }
7935 #[doc = "ID Extended. One/zero for extended/standard format frame."]
7936 pub mod IDE {
7937 pub const offset: u32 = 21;
7938 pub const mask: u32 = 0x01 << offset;
7939 pub mod R {}
7940 pub mod W {}
7941 pub mod RW {}
7942 }
7943 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
7944 pub mod SRR {
7945 pub const offset: u32 = 22;
7946 pub const mask: u32 = 0x01 << offset;
7947 pub mod R {}
7948 pub mod W {}
7949 pub mod RW {}
7950 }
7951 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
7952 pub mod CODE {
7953 pub const offset: u32 = 24;
7954 pub const mask: u32 = 0x0f << offset;
7955 pub mod R {}
7956 pub mod W {}
7957 pub mod RW {}
7958 }
7959 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
7960 pub mod ESI {
7961 pub const offset: u32 = 29;
7962 pub const mask: u32 = 0x01 << offset;
7963 pub mod R {}
7964 pub mod W {}
7965 pub mod RW {}
7966 }
7967 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
7968 pub mod BRS {
7969 pub const offset: u32 = 30;
7970 pub const mask: u32 = 0x01 << offset;
7971 pub mod R {}
7972 pub mod W {}
7973 pub mod RW {}
7974 }
7975 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
7976 pub mod EDL {
7977 pub const offset: u32 = 31;
7978 pub const mask: u32 = 0x01 << offset;
7979 pub mod R {}
7980 pub mod W {}
7981 pub mod RW {}
7982 }
7983}
7984#[doc = "Message Buffer 34 ID Register"]
7985pub mod ID34 {
7986 #[doc = "Contains extended (LOW word) identifier of message buffer."]
7987 pub mod EXT {
7988 pub const offset: u32 = 0;
7989 pub const mask: u32 = 0x0003_ffff << offset;
7990 pub mod R {}
7991 pub mod W {}
7992 pub mod RW {}
7993 }
7994 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
7995 pub mod STD {
7996 pub const offset: u32 = 18;
7997 pub const mask: u32 = 0x07ff << offset;
7998 pub mod R {}
7999 pub mod W {}
8000 pub mod RW {}
8001 }
8002 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
8003 pub mod PRIO {
8004 pub const offset: u32 = 29;
8005 pub const mask: u32 = 0x07 << offset;
8006 pub mod R {}
8007 pub mod W {}
8008 pub mod RW {}
8009 }
8010}
8011#[doc = "Message Buffer 13 WORD_32B Register"]
8012pub mod MB13_32B_WORD6 {
8013 #[doc = "Data byte 0 of Rx/Tx frame."]
8014 pub mod DATA_BYTE_27 {
8015 pub const offset: u32 = 0;
8016 pub const mask: u32 = 0xff << offset;
8017 pub mod R {}
8018 pub mod W {}
8019 pub mod RW {}
8020 }
8021 #[doc = "Data byte 1 of Rx/Tx frame."]
8022 pub mod DATA_BYTE_26 {
8023 pub const offset: u32 = 8;
8024 pub const mask: u32 = 0xff << offset;
8025 pub mod R {}
8026 pub mod W {}
8027 pub mod RW {}
8028 }
8029 #[doc = "Data byte 2 of Rx/Tx frame."]
8030 pub mod DATA_BYTE_25 {
8031 pub const offset: u32 = 16;
8032 pub const mask: u32 = 0xff << offset;
8033 pub mod R {}
8034 pub mod W {}
8035 pub mod RW {}
8036 }
8037 #[doc = "Data byte 3 of Rx/Tx frame."]
8038 pub mod DATA_BYTE_24 {
8039 pub const offset: u32 = 24;
8040 pub const mask: u32 = 0xff << offset;
8041 pub mod R {}
8042 pub mod W {}
8043 pub mod RW {}
8044 }
8045}
8046#[doc = "Message Buffer 13 WORD_32B Register"]
8047pub mod MB13_32B_WORD7 {
8048 #[doc = "Data byte 0 of Rx/Tx frame."]
8049 pub mod DATA_BYTE_31 {
8050 pub const offset: u32 = 0;
8051 pub const mask: u32 = 0xff << offset;
8052 pub mod R {}
8053 pub mod W {}
8054 pub mod RW {}
8055 }
8056 #[doc = "Data byte 1 of Rx/Tx frame."]
8057 pub mod DATA_BYTE_30 {
8058 pub const offset: u32 = 8;
8059 pub const mask: u32 = 0xff << offset;
8060 pub mod R {}
8061 pub mod W {}
8062 pub mod RW {}
8063 }
8064 #[doc = "Data byte 2 of Rx/Tx frame."]
8065 pub mod DATA_BYTE_29 {
8066 pub const offset: u32 = 16;
8067 pub const mask: u32 = 0xff << offset;
8068 pub mod R {}
8069 pub mod W {}
8070 pub mod RW {}
8071 }
8072 #[doc = "Data byte 3 of Rx/Tx frame."]
8073 pub mod DATA_BYTE_28 {
8074 pub const offset: u32 = 24;
8075 pub const mask: u32 = 0xff << offset;
8076 pub mod R {}
8077 pub mod W {}
8078 pub mod RW {}
8079 }
8080}
8081#[doc = "Message Buffer 35 CS Register"]
8082pub mod CS35 {
8083 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
8084 pub mod TIME_STAMP {
8085 pub const offset: u32 = 0;
8086 pub const mask: u32 = 0xffff << offset;
8087 pub mod R {}
8088 pub mod W {}
8089 pub mod RW {}
8090 }
8091 #[doc = "Length of the data to be stored/transmitted."]
8092 pub mod DLC {
8093 pub const offset: u32 = 16;
8094 pub const mask: u32 = 0x0f << offset;
8095 pub mod R {}
8096 pub mod W {}
8097 pub mod RW {}
8098 }
8099 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
8100 pub mod RTR {
8101 pub const offset: u32 = 20;
8102 pub const mask: u32 = 0x01 << offset;
8103 pub mod R {}
8104 pub mod W {}
8105 pub mod RW {}
8106 }
8107 #[doc = "ID Extended. One/zero for extended/standard format frame."]
8108 pub mod IDE {
8109 pub const offset: u32 = 21;
8110 pub const mask: u32 = 0x01 << offset;
8111 pub mod R {}
8112 pub mod W {}
8113 pub mod RW {}
8114 }
8115 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
8116 pub mod SRR {
8117 pub const offset: u32 = 22;
8118 pub const mask: u32 = 0x01 << offset;
8119 pub mod R {}
8120 pub mod W {}
8121 pub mod RW {}
8122 }
8123 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
8124 pub mod CODE {
8125 pub const offset: u32 = 24;
8126 pub const mask: u32 = 0x0f << offset;
8127 pub mod R {}
8128 pub mod W {}
8129 pub mod RW {}
8130 }
8131 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
8132 pub mod ESI {
8133 pub const offset: u32 = 29;
8134 pub const mask: u32 = 0x01 << offset;
8135 pub mod R {}
8136 pub mod W {}
8137 pub mod RW {}
8138 }
8139 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
8140 pub mod BRS {
8141 pub const offset: u32 = 30;
8142 pub const mask: u32 = 0x01 << offset;
8143 pub mod R {}
8144 pub mod W {}
8145 pub mod RW {}
8146 }
8147 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
8148 pub mod EDL {
8149 pub const offset: u32 = 31;
8150 pub const mask: u32 = 0x01 << offset;
8151 pub mod R {}
8152 pub mod W {}
8153 pub mod RW {}
8154 }
8155}
8156#[doc = "Message Buffer 35 ID Register"]
8157pub mod ID35 {
8158 #[doc = "Contains extended (LOW word) identifier of message buffer."]
8159 pub mod EXT {
8160 pub const offset: u32 = 0;
8161 pub const mask: u32 = 0x0003_ffff << offset;
8162 pub mod R {}
8163 pub mod W {}
8164 pub mod RW {}
8165 }
8166 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
8167 pub mod STD {
8168 pub const offset: u32 = 18;
8169 pub const mask: u32 = 0x07ff << offset;
8170 pub mod R {}
8171 pub mod W {}
8172 pub mod RW {}
8173 }
8174 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
8175 pub mod PRIO {
8176 pub const offset: u32 = 29;
8177 pub const mask: u32 = 0x07 << offset;
8178 pub mod R {}
8179 pub mod W {}
8180 pub mod RW {}
8181 }
8182}
8183#[doc = "Message Buffer 14 WORD_32B Register"]
8184pub mod MB14_32B_WORD0 {
8185 #[doc = "Data byte 0 of Rx/Tx frame."]
8186 pub mod DATA_BYTE_3 {
8187 pub const offset: u32 = 0;
8188 pub const mask: u32 = 0xff << offset;
8189 pub mod R {}
8190 pub mod W {}
8191 pub mod RW {}
8192 }
8193 #[doc = "Data byte 1 of Rx/Tx frame."]
8194 pub mod DATA_BYTE_2 {
8195 pub const offset: u32 = 8;
8196 pub const mask: u32 = 0xff << offset;
8197 pub mod R {}
8198 pub mod W {}
8199 pub mod RW {}
8200 }
8201 #[doc = "Data byte 2 of Rx/Tx frame."]
8202 pub mod DATA_BYTE_1 {
8203 pub const offset: u32 = 16;
8204 pub const mask: u32 = 0xff << offset;
8205 pub mod R {}
8206 pub mod W {}
8207 pub mod RW {}
8208 }
8209 #[doc = "Data byte 3 of Rx/Tx frame."]
8210 pub mod DATA_BYTE_0 {
8211 pub const offset: u32 = 24;
8212 pub const mask: u32 = 0xff << offset;
8213 pub mod R {}
8214 pub mod W {}
8215 pub mod RW {}
8216 }
8217}
8218#[doc = "Message Buffer 14 WORD_32B Register"]
8219pub mod MB14_32B_WORD1 {
8220 #[doc = "Data byte 0 of Rx/Tx frame."]
8221 pub mod DATA_BYTE_7 {
8222 pub const offset: u32 = 0;
8223 pub const mask: u32 = 0xff << offset;
8224 pub mod R {}
8225 pub mod W {}
8226 pub mod RW {}
8227 }
8228 #[doc = "Data byte 1 of Rx/Tx frame."]
8229 pub mod DATA_BYTE_6 {
8230 pub const offset: u32 = 8;
8231 pub const mask: u32 = 0xff << offset;
8232 pub mod R {}
8233 pub mod W {}
8234 pub mod RW {}
8235 }
8236 #[doc = "Data byte 2 of Rx/Tx frame."]
8237 pub mod DATA_BYTE_5 {
8238 pub const offset: u32 = 16;
8239 pub const mask: u32 = 0xff << offset;
8240 pub mod R {}
8241 pub mod W {}
8242 pub mod RW {}
8243 }
8244 #[doc = "Data byte 3 of Rx/Tx frame."]
8245 pub mod DATA_BYTE_4 {
8246 pub const offset: u32 = 24;
8247 pub const mask: u32 = 0xff << offset;
8248 pub mod R {}
8249 pub mod W {}
8250 pub mod RW {}
8251 }
8252}
8253#[doc = "Message Buffer 36 CS Register"]
8254pub mod CS36 {
8255 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
8256 pub mod TIME_STAMP {
8257 pub const offset: u32 = 0;
8258 pub const mask: u32 = 0xffff << offset;
8259 pub mod R {}
8260 pub mod W {}
8261 pub mod RW {}
8262 }
8263 #[doc = "Length of the data to be stored/transmitted."]
8264 pub mod DLC {
8265 pub const offset: u32 = 16;
8266 pub const mask: u32 = 0x0f << offset;
8267 pub mod R {}
8268 pub mod W {}
8269 pub mod RW {}
8270 }
8271 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
8272 pub mod RTR {
8273 pub const offset: u32 = 20;
8274 pub const mask: u32 = 0x01 << offset;
8275 pub mod R {}
8276 pub mod W {}
8277 pub mod RW {}
8278 }
8279 #[doc = "ID Extended. One/zero for extended/standard format frame."]
8280 pub mod IDE {
8281 pub const offset: u32 = 21;
8282 pub const mask: u32 = 0x01 << offset;
8283 pub mod R {}
8284 pub mod W {}
8285 pub mod RW {}
8286 }
8287 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
8288 pub mod SRR {
8289 pub const offset: u32 = 22;
8290 pub const mask: u32 = 0x01 << offset;
8291 pub mod R {}
8292 pub mod W {}
8293 pub mod RW {}
8294 }
8295 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
8296 pub mod CODE {
8297 pub const offset: u32 = 24;
8298 pub const mask: u32 = 0x0f << offset;
8299 pub mod R {}
8300 pub mod W {}
8301 pub mod RW {}
8302 }
8303 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
8304 pub mod ESI {
8305 pub const offset: u32 = 29;
8306 pub const mask: u32 = 0x01 << offset;
8307 pub mod R {}
8308 pub mod W {}
8309 pub mod RW {}
8310 }
8311 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
8312 pub mod BRS {
8313 pub const offset: u32 = 30;
8314 pub const mask: u32 = 0x01 << offset;
8315 pub mod R {}
8316 pub mod W {}
8317 pub mod RW {}
8318 }
8319 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
8320 pub mod EDL {
8321 pub const offset: u32 = 31;
8322 pub const mask: u32 = 0x01 << offset;
8323 pub mod R {}
8324 pub mod W {}
8325 pub mod RW {}
8326 }
8327}
8328#[doc = "Message Buffer 36 ID Register"]
8329pub mod ID36 {
8330 #[doc = "Contains extended (LOW word) identifier of message buffer."]
8331 pub mod EXT {
8332 pub const offset: u32 = 0;
8333 pub const mask: u32 = 0x0003_ffff << offset;
8334 pub mod R {}
8335 pub mod W {}
8336 pub mod RW {}
8337 }
8338 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
8339 pub mod STD {
8340 pub const offset: u32 = 18;
8341 pub const mask: u32 = 0x07ff << offset;
8342 pub mod R {}
8343 pub mod W {}
8344 pub mod RW {}
8345 }
8346 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
8347 pub mod PRIO {
8348 pub const offset: u32 = 29;
8349 pub const mask: u32 = 0x07 << offset;
8350 pub mod R {}
8351 pub mod W {}
8352 pub mod RW {}
8353 }
8354}
8355#[doc = "Message Buffer 14 WORD_32B Register"]
8356pub mod MB14_32B_WORD4 {
8357 #[doc = "Data byte 0 of Rx/Tx frame."]
8358 pub mod DATA_BYTE_19 {
8359 pub const offset: u32 = 0;
8360 pub const mask: u32 = 0xff << offset;
8361 pub mod R {}
8362 pub mod W {}
8363 pub mod RW {}
8364 }
8365 #[doc = "Data byte 1 of Rx/Tx frame."]
8366 pub mod DATA_BYTE_18 {
8367 pub const offset: u32 = 8;
8368 pub const mask: u32 = 0xff << offset;
8369 pub mod R {}
8370 pub mod W {}
8371 pub mod RW {}
8372 }
8373 #[doc = "Data byte 2 of Rx/Tx frame."]
8374 pub mod DATA_BYTE_17 {
8375 pub const offset: u32 = 16;
8376 pub const mask: u32 = 0xff << offset;
8377 pub mod R {}
8378 pub mod W {}
8379 pub mod RW {}
8380 }
8381 #[doc = "Data byte 3 of Rx/Tx frame."]
8382 pub mod DATA_BYTE_16 {
8383 pub const offset: u32 = 24;
8384 pub const mask: u32 = 0xff << offset;
8385 pub mod R {}
8386 pub mod W {}
8387 pub mod RW {}
8388 }
8389}
8390#[doc = "Message Buffer 14 WORD_32B Register"]
8391pub mod MB14_32B_WORD5 {
8392 #[doc = "Data byte 0 of Rx/Tx frame."]
8393 pub mod DATA_BYTE_23 {
8394 pub const offset: u32 = 0;
8395 pub const mask: u32 = 0xff << offset;
8396 pub mod R {}
8397 pub mod W {}
8398 pub mod RW {}
8399 }
8400 #[doc = "Data byte 1 of Rx/Tx frame."]
8401 pub mod DATA_BYTE_22 {
8402 pub const offset: u32 = 8;
8403 pub const mask: u32 = 0xff << offset;
8404 pub mod R {}
8405 pub mod W {}
8406 pub mod RW {}
8407 }
8408 #[doc = "Data byte 2 of Rx/Tx frame."]
8409 pub mod DATA_BYTE_21 {
8410 pub const offset: u32 = 16;
8411 pub const mask: u32 = 0xff << offset;
8412 pub mod R {}
8413 pub mod W {}
8414 pub mod RW {}
8415 }
8416 #[doc = "Data byte 3 of Rx/Tx frame."]
8417 pub mod DATA_BYTE_20 {
8418 pub const offset: u32 = 24;
8419 pub const mask: u32 = 0xff << offset;
8420 pub mod R {}
8421 pub mod W {}
8422 pub mod RW {}
8423 }
8424}
8425#[doc = "Message Buffer 37 CS Register"]
8426pub mod CS37 {
8427 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
8428 pub mod TIME_STAMP {
8429 pub const offset: u32 = 0;
8430 pub const mask: u32 = 0xffff << offset;
8431 pub mod R {}
8432 pub mod W {}
8433 pub mod RW {}
8434 }
8435 #[doc = "Length of the data to be stored/transmitted."]
8436 pub mod DLC {
8437 pub const offset: u32 = 16;
8438 pub const mask: u32 = 0x0f << offset;
8439 pub mod R {}
8440 pub mod W {}
8441 pub mod RW {}
8442 }
8443 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
8444 pub mod RTR {
8445 pub const offset: u32 = 20;
8446 pub const mask: u32 = 0x01 << offset;
8447 pub mod R {}
8448 pub mod W {}
8449 pub mod RW {}
8450 }
8451 #[doc = "ID Extended. One/zero for extended/standard format frame."]
8452 pub mod IDE {
8453 pub const offset: u32 = 21;
8454 pub const mask: u32 = 0x01 << offset;
8455 pub mod R {}
8456 pub mod W {}
8457 pub mod RW {}
8458 }
8459 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
8460 pub mod SRR {
8461 pub const offset: u32 = 22;
8462 pub const mask: u32 = 0x01 << offset;
8463 pub mod R {}
8464 pub mod W {}
8465 pub mod RW {}
8466 }
8467 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
8468 pub mod CODE {
8469 pub const offset: u32 = 24;
8470 pub const mask: u32 = 0x0f << offset;
8471 pub mod R {}
8472 pub mod W {}
8473 pub mod RW {}
8474 }
8475 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
8476 pub mod ESI {
8477 pub const offset: u32 = 29;
8478 pub const mask: u32 = 0x01 << offset;
8479 pub mod R {}
8480 pub mod W {}
8481 pub mod RW {}
8482 }
8483 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
8484 pub mod BRS {
8485 pub const offset: u32 = 30;
8486 pub const mask: u32 = 0x01 << offset;
8487 pub mod R {}
8488 pub mod W {}
8489 pub mod RW {}
8490 }
8491 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
8492 pub mod EDL {
8493 pub const offset: u32 = 31;
8494 pub const mask: u32 = 0x01 << offset;
8495 pub mod R {}
8496 pub mod W {}
8497 pub mod RW {}
8498 }
8499}
8500#[doc = "Message Buffer 37 ID Register"]
8501pub mod ID37 {
8502 #[doc = "Contains extended (LOW word) identifier of message buffer."]
8503 pub mod EXT {
8504 pub const offset: u32 = 0;
8505 pub const mask: u32 = 0x0003_ffff << offset;
8506 pub mod R {}
8507 pub mod W {}
8508 pub mod RW {}
8509 }
8510 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
8511 pub mod STD {
8512 pub const offset: u32 = 18;
8513 pub const mask: u32 = 0x07ff << offset;
8514 pub mod R {}
8515 pub mod W {}
8516 pub mod RW {}
8517 }
8518 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
8519 pub mod PRIO {
8520 pub const offset: u32 = 29;
8521 pub const mask: u32 = 0x07 << offset;
8522 pub mod R {}
8523 pub mod W {}
8524 pub mod RW {}
8525 }
8526}
8527#[doc = "Message Buffer 15 CS Register"]
8528pub mod MB15_32B_CS {
8529 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
8530 pub mod TIME_STAMP {
8531 pub const offset: u32 = 0;
8532 pub const mask: u32 = 0xffff << offset;
8533 pub mod R {}
8534 pub mod W {}
8535 pub mod RW {}
8536 }
8537 #[doc = "Length of the data to be stored/transmitted."]
8538 pub mod DLC {
8539 pub const offset: u32 = 16;
8540 pub const mask: u32 = 0x0f << offset;
8541 pub mod R {}
8542 pub mod W {}
8543 pub mod RW {}
8544 }
8545 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
8546 pub mod RTR {
8547 pub const offset: u32 = 20;
8548 pub const mask: u32 = 0x01 << offset;
8549 pub mod R {}
8550 pub mod W {}
8551 pub mod RW {}
8552 }
8553 #[doc = "ID Extended. One/zero for extended/standard format frame."]
8554 pub mod IDE {
8555 pub const offset: u32 = 21;
8556 pub const mask: u32 = 0x01 << offset;
8557 pub mod R {}
8558 pub mod W {}
8559 pub mod RW {}
8560 }
8561 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
8562 pub mod SRR {
8563 pub const offset: u32 = 22;
8564 pub const mask: u32 = 0x01 << offset;
8565 pub mod R {}
8566 pub mod W {}
8567 pub mod RW {}
8568 }
8569 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
8570 pub mod CODE {
8571 pub const offset: u32 = 24;
8572 pub const mask: u32 = 0x0f << offset;
8573 pub mod R {}
8574 pub mod W {}
8575 pub mod RW {}
8576 }
8577 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
8578 pub mod ESI {
8579 pub const offset: u32 = 29;
8580 pub const mask: u32 = 0x01 << offset;
8581 pub mod R {}
8582 pub mod W {}
8583 pub mod RW {}
8584 }
8585 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
8586 pub mod BRS {
8587 pub const offset: u32 = 30;
8588 pub const mask: u32 = 0x01 << offset;
8589 pub mod R {}
8590 pub mod W {}
8591 pub mod RW {}
8592 }
8593 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
8594 pub mod EDL {
8595 pub const offset: u32 = 31;
8596 pub const mask: u32 = 0x01 << offset;
8597 pub mod R {}
8598 pub mod W {}
8599 pub mod RW {}
8600 }
8601}
8602#[doc = "Message Buffer 15 ID Register"]
8603pub mod MB15_32B_ID {
8604 #[doc = "Contains extended (LOW word) identifier of message buffer."]
8605 pub mod EXT {
8606 pub const offset: u32 = 0;
8607 pub const mask: u32 = 0x0003_ffff << offset;
8608 pub mod R {}
8609 pub mod W {}
8610 pub mod RW {}
8611 }
8612 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
8613 pub mod STD {
8614 pub const offset: u32 = 18;
8615 pub const mask: u32 = 0x07ff << offset;
8616 pub mod R {}
8617 pub mod W {}
8618 pub mod RW {}
8619 }
8620 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
8621 pub mod PRIO {
8622 pub const offset: u32 = 29;
8623 pub const mask: u32 = 0x07 << offset;
8624 pub mod R {}
8625 pub mod W {}
8626 pub mod RW {}
8627 }
8628}
8629#[doc = "Message Buffer 38 CS Register"]
8630pub mod CS38 {
8631 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
8632 pub mod TIME_STAMP {
8633 pub const offset: u32 = 0;
8634 pub const mask: u32 = 0xffff << offset;
8635 pub mod R {}
8636 pub mod W {}
8637 pub mod RW {}
8638 }
8639 #[doc = "Length of the data to be stored/transmitted."]
8640 pub mod DLC {
8641 pub const offset: u32 = 16;
8642 pub const mask: u32 = 0x0f << offset;
8643 pub mod R {}
8644 pub mod W {}
8645 pub mod RW {}
8646 }
8647 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
8648 pub mod RTR {
8649 pub const offset: u32 = 20;
8650 pub const mask: u32 = 0x01 << offset;
8651 pub mod R {}
8652 pub mod W {}
8653 pub mod RW {}
8654 }
8655 #[doc = "ID Extended. One/zero for extended/standard format frame."]
8656 pub mod IDE {
8657 pub const offset: u32 = 21;
8658 pub const mask: u32 = 0x01 << offset;
8659 pub mod R {}
8660 pub mod W {}
8661 pub mod RW {}
8662 }
8663 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
8664 pub mod SRR {
8665 pub const offset: u32 = 22;
8666 pub const mask: u32 = 0x01 << offset;
8667 pub mod R {}
8668 pub mod W {}
8669 pub mod RW {}
8670 }
8671 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
8672 pub mod CODE {
8673 pub const offset: u32 = 24;
8674 pub const mask: u32 = 0x0f << offset;
8675 pub mod R {}
8676 pub mod W {}
8677 pub mod RW {}
8678 }
8679 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
8680 pub mod ESI {
8681 pub const offset: u32 = 29;
8682 pub const mask: u32 = 0x01 << offset;
8683 pub mod R {}
8684 pub mod W {}
8685 pub mod RW {}
8686 }
8687 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
8688 pub mod BRS {
8689 pub const offset: u32 = 30;
8690 pub const mask: u32 = 0x01 << offset;
8691 pub mod R {}
8692 pub mod W {}
8693 pub mod RW {}
8694 }
8695 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
8696 pub mod EDL {
8697 pub const offset: u32 = 31;
8698 pub const mask: u32 = 0x01 << offset;
8699 pub mod R {}
8700 pub mod W {}
8701 pub mod RW {}
8702 }
8703}
8704#[doc = "Message Buffer 38 ID Register"]
8705pub mod ID38 {
8706 #[doc = "Contains extended (LOW word) identifier of message buffer."]
8707 pub mod EXT {
8708 pub const offset: u32 = 0;
8709 pub const mask: u32 = 0x0003_ffff << offset;
8710 pub mod R {}
8711 pub mod W {}
8712 pub mod RW {}
8713 }
8714 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
8715 pub mod STD {
8716 pub const offset: u32 = 18;
8717 pub const mask: u32 = 0x07ff << offset;
8718 pub mod R {}
8719 pub mod W {}
8720 pub mod RW {}
8721 }
8722 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
8723 pub mod PRIO {
8724 pub const offset: u32 = 29;
8725 pub const mask: u32 = 0x07 << offset;
8726 pub mod R {}
8727 pub mod W {}
8728 pub mod RW {}
8729 }
8730}
8731#[doc = "Message Buffer 15 WORD_32B Register"]
8732pub mod MB15_32B_WORD2 {
8733 #[doc = "Data byte 0 of Rx/Tx frame."]
8734 pub mod DATA_BYTE_11 {
8735 pub const offset: u32 = 0;
8736 pub const mask: u32 = 0xff << offset;
8737 pub mod R {}
8738 pub mod W {}
8739 pub mod RW {}
8740 }
8741 #[doc = "Data byte 1 of Rx/Tx frame."]
8742 pub mod DATA_BYTE_10 {
8743 pub const offset: u32 = 8;
8744 pub const mask: u32 = 0xff << offset;
8745 pub mod R {}
8746 pub mod W {}
8747 pub mod RW {}
8748 }
8749 #[doc = "Data byte 2 of Rx/Tx frame."]
8750 pub mod DATA_BYTE_9 {
8751 pub const offset: u32 = 16;
8752 pub const mask: u32 = 0xff << offset;
8753 pub mod R {}
8754 pub mod W {}
8755 pub mod RW {}
8756 }
8757 #[doc = "Data byte 3 of Rx/Tx frame."]
8758 pub mod DATA_BYTE_8 {
8759 pub const offset: u32 = 24;
8760 pub const mask: u32 = 0xff << offset;
8761 pub mod R {}
8762 pub mod W {}
8763 pub mod RW {}
8764 }
8765}
8766#[doc = "Message Buffer 15 WORD_32B Register"]
8767pub mod MB15_32B_WORD3 {
8768 #[doc = "Data byte 0 of Rx/Tx frame."]
8769 pub mod DATA_BYTE_15 {
8770 pub const offset: u32 = 0;
8771 pub const mask: u32 = 0xff << offset;
8772 pub mod R {}
8773 pub mod W {}
8774 pub mod RW {}
8775 }
8776 #[doc = "Data byte 1 of Rx/Tx frame."]
8777 pub mod DATA_BYTE_14 {
8778 pub const offset: u32 = 8;
8779 pub const mask: u32 = 0xff << offset;
8780 pub mod R {}
8781 pub mod W {}
8782 pub mod RW {}
8783 }
8784 #[doc = "Data byte 2 of Rx/Tx frame."]
8785 pub mod DATA_BYTE_13 {
8786 pub const offset: u32 = 16;
8787 pub const mask: u32 = 0xff << offset;
8788 pub mod R {}
8789 pub mod W {}
8790 pub mod RW {}
8791 }
8792 #[doc = "Data byte 3 of Rx/Tx frame."]
8793 pub mod DATA_BYTE_12 {
8794 pub const offset: u32 = 24;
8795 pub const mask: u32 = 0xff << offset;
8796 pub mod R {}
8797 pub mod W {}
8798 pub mod RW {}
8799 }
8800}
8801#[doc = "Message Buffer 39 CS Register"]
8802pub mod CS39 {
8803 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
8804 pub mod TIME_STAMP {
8805 pub const offset: u32 = 0;
8806 pub const mask: u32 = 0xffff << offset;
8807 pub mod R {}
8808 pub mod W {}
8809 pub mod RW {}
8810 }
8811 #[doc = "Length of the data to be stored/transmitted."]
8812 pub mod DLC {
8813 pub const offset: u32 = 16;
8814 pub const mask: u32 = 0x0f << offset;
8815 pub mod R {}
8816 pub mod W {}
8817 pub mod RW {}
8818 }
8819 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
8820 pub mod RTR {
8821 pub const offset: u32 = 20;
8822 pub const mask: u32 = 0x01 << offset;
8823 pub mod R {}
8824 pub mod W {}
8825 pub mod RW {}
8826 }
8827 #[doc = "ID Extended. One/zero for extended/standard format frame."]
8828 pub mod IDE {
8829 pub const offset: u32 = 21;
8830 pub const mask: u32 = 0x01 << offset;
8831 pub mod R {}
8832 pub mod W {}
8833 pub mod RW {}
8834 }
8835 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
8836 pub mod SRR {
8837 pub const offset: u32 = 22;
8838 pub const mask: u32 = 0x01 << offset;
8839 pub mod R {}
8840 pub mod W {}
8841 pub mod RW {}
8842 }
8843 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
8844 pub mod CODE {
8845 pub const offset: u32 = 24;
8846 pub const mask: u32 = 0x0f << offset;
8847 pub mod R {}
8848 pub mod W {}
8849 pub mod RW {}
8850 }
8851 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
8852 pub mod ESI {
8853 pub const offset: u32 = 29;
8854 pub const mask: u32 = 0x01 << offset;
8855 pub mod R {}
8856 pub mod W {}
8857 pub mod RW {}
8858 }
8859 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
8860 pub mod BRS {
8861 pub const offset: u32 = 30;
8862 pub const mask: u32 = 0x01 << offset;
8863 pub mod R {}
8864 pub mod W {}
8865 pub mod RW {}
8866 }
8867 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
8868 pub mod EDL {
8869 pub const offset: u32 = 31;
8870 pub const mask: u32 = 0x01 << offset;
8871 pub mod R {}
8872 pub mod W {}
8873 pub mod RW {}
8874 }
8875}
8876#[doc = "Message Buffer 39 ID Register"]
8877pub mod ID39 {
8878 #[doc = "Contains extended (LOW word) identifier of message buffer."]
8879 pub mod EXT {
8880 pub const offset: u32 = 0;
8881 pub const mask: u32 = 0x0003_ffff << offset;
8882 pub mod R {}
8883 pub mod W {}
8884 pub mod RW {}
8885 }
8886 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
8887 pub mod STD {
8888 pub const offset: u32 = 18;
8889 pub const mask: u32 = 0x07ff << offset;
8890 pub mod R {}
8891 pub mod W {}
8892 pub mod RW {}
8893 }
8894 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
8895 pub mod PRIO {
8896 pub const offset: u32 = 29;
8897 pub const mask: u32 = 0x07 << offset;
8898 pub mod R {}
8899 pub mod W {}
8900 pub mod RW {}
8901 }
8902}
8903#[doc = "Message Buffer 15 WORD_32B Register"]
8904pub mod MB15_32B_WORD6 {
8905 #[doc = "Data byte 0 of Rx/Tx frame."]
8906 pub mod DATA_BYTE_27 {
8907 pub const offset: u32 = 0;
8908 pub const mask: u32 = 0xff << offset;
8909 pub mod R {}
8910 pub mod W {}
8911 pub mod RW {}
8912 }
8913 #[doc = "Data byte 1 of Rx/Tx frame."]
8914 pub mod DATA_BYTE_26 {
8915 pub const offset: u32 = 8;
8916 pub const mask: u32 = 0xff << offset;
8917 pub mod R {}
8918 pub mod W {}
8919 pub mod RW {}
8920 }
8921 #[doc = "Data byte 2 of Rx/Tx frame."]
8922 pub mod DATA_BYTE_25 {
8923 pub const offset: u32 = 16;
8924 pub const mask: u32 = 0xff << offset;
8925 pub mod R {}
8926 pub mod W {}
8927 pub mod RW {}
8928 }
8929 #[doc = "Data byte 3 of Rx/Tx frame."]
8930 pub mod DATA_BYTE_24 {
8931 pub const offset: u32 = 24;
8932 pub const mask: u32 = 0xff << offset;
8933 pub mod R {}
8934 pub mod W {}
8935 pub mod RW {}
8936 }
8937}
8938#[doc = "Message Buffer 15 WORD_32B Register"]
8939pub mod MB15_32B_WORD7 {
8940 #[doc = "Data byte 0 of Rx/Tx frame."]
8941 pub mod DATA_BYTE_31 {
8942 pub const offset: u32 = 0;
8943 pub const mask: u32 = 0xff << offset;
8944 pub mod R {}
8945 pub mod W {}
8946 pub mod RW {}
8947 }
8948 #[doc = "Data byte 1 of Rx/Tx frame."]
8949 pub mod DATA_BYTE_30 {
8950 pub const offset: u32 = 8;
8951 pub const mask: u32 = 0xff << offset;
8952 pub mod R {}
8953 pub mod W {}
8954 pub mod RW {}
8955 }
8956 #[doc = "Data byte 2 of Rx/Tx frame."]
8957 pub mod DATA_BYTE_29 {
8958 pub const offset: u32 = 16;
8959 pub const mask: u32 = 0xff << offset;
8960 pub mod R {}
8961 pub mod W {}
8962 pub mod RW {}
8963 }
8964 #[doc = "Data byte 3 of Rx/Tx frame."]
8965 pub mod DATA_BYTE_28 {
8966 pub const offset: u32 = 24;
8967 pub const mask: u32 = 0xff << offset;
8968 pub mod R {}
8969 pub mod W {}
8970 pub mod RW {}
8971 }
8972}
8973#[doc = "Message Buffer 40 CS Register"]
8974pub mod CS40 {
8975 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
8976 pub mod TIME_STAMP {
8977 pub const offset: u32 = 0;
8978 pub const mask: u32 = 0xffff << offset;
8979 pub mod R {}
8980 pub mod W {}
8981 pub mod RW {}
8982 }
8983 #[doc = "Length of the data to be stored/transmitted."]
8984 pub mod DLC {
8985 pub const offset: u32 = 16;
8986 pub const mask: u32 = 0x0f << offset;
8987 pub mod R {}
8988 pub mod W {}
8989 pub mod RW {}
8990 }
8991 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
8992 pub mod RTR {
8993 pub const offset: u32 = 20;
8994 pub const mask: u32 = 0x01 << offset;
8995 pub mod R {}
8996 pub mod W {}
8997 pub mod RW {}
8998 }
8999 #[doc = "ID Extended. One/zero for extended/standard format frame."]
9000 pub mod IDE {
9001 pub const offset: u32 = 21;
9002 pub const mask: u32 = 0x01 << offset;
9003 pub mod R {}
9004 pub mod W {}
9005 pub mod RW {}
9006 }
9007 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
9008 pub mod SRR {
9009 pub const offset: u32 = 22;
9010 pub const mask: u32 = 0x01 << offset;
9011 pub mod R {}
9012 pub mod W {}
9013 pub mod RW {}
9014 }
9015 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
9016 pub mod CODE {
9017 pub const offset: u32 = 24;
9018 pub const mask: u32 = 0x0f << offset;
9019 pub mod R {}
9020 pub mod W {}
9021 pub mod RW {}
9022 }
9023 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
9024 pub mod ESI {
9025 pub const offset: u32 = 29;
9026 pub const mask: u32 = 0x01 << offset;
9027 pub mod R {}
9028 pub mod W {}
9029 pub mod RW {}
9030 }
9031 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
9032 pub mod BRS {
9033 pub const offset: u32 = 30;
9034 pub const mask: u32 = 0x01 << offset;
9035 pub mod R {}
9036 pub mod W {}
9037 pub mod RW {}
9038 }
9039 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
9040 pub mod EDL {
9041 pub const offset: u32 = 31;
9042 pub const mask: u32 = 0x01 << offset;
9043 pub mod R {}
9044 pub mod W {}
9045 pub mod RW {}
9046 }
9047}
9048#[doc = "Message Buffer 40 ID Register"]
9049pub mod ID40 {
9050 #[doc = "Contains extended (LOW word) identifier of message buffer."]
9051 pub mod EXT {
9052 pub const offset: u32 = 0;
9053 pub const mask: u32 = 0x0003_ffff << offset;
9054 pub mod R {}
9055 pub mod W {}
9056 pub mod RW {}
9057 }
9058 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
9059 pub mod STD {
9060 pub const offset: u32 = 18;
9061 pub const mask: u32 = 0x07ff << offset;
9062 pub mod R {}
9063 pub mod W {}
9064 pub mod RW {}
9065 }
9066 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
9067 pub mod PRIO {
9068 pub const offset: u32 = 29;
9069 pub const mask: u32 = 0x07 << offset;
9070 pub mod R {}
9071 pub mod W {}
9072 pub mod RW {}
9073 }
9074}
9075#[doc = "Message Buffer 16 WORD_32B Register"]
9076pub mod MB16_32B_WORD0 {
9077 #[doc = "Data byte 0 of Rx/Tx frame."]
9078 pub mod DATA_BYTE_3 {
9079 pub const offset: u32 = 0;
9080 pub const mask: u32 = 0xff << offset;
9081 pub mod R {}
9082 pub mod W {}
9083 pub mod RW {}
9084 }
9085 #[doc = "Data byte 1 of Rx/Tx frame."]
9086 pub mod DATA_BYTE_2 {
9087 pub const offset: u32 = 8;
9088 pub const mask: u32 = 0xff << offset;
9089 pub mod R {}
9090 pub mod W {}
9091 pub mod RW {}
9092 }
9093 #[doc = "Data byte 2 of Rx/Tx frame."]
9094 pub mod DATA_BYTE_1 {
9095 pub const offset: u32 = 16;
9096 pub const mask: u32 = 0xff << offset;
9097 pub mod R {}
9098 pub mod W {}
9099 pub mod RW {}
9100 }
9101 #[doc = "Data byte 3 of Rx/Tx frame."]
9102 pub mod DATA_BYTE_0 {
9103 pub const offset: u32 = 24;
9104 pub const mask: u32 = 0xff << offset;
9105 pub mod R {}
9106 pub mod W {}
9107 pub mod RW {}
9108 }
9109}
9110#[doc = "Message Buffer 16 WORD_32B Register"]
9111pub mod MB16_32B_WORD1 {
9112 #[doc = "Data byte 0 of Rx/Tx frame."]
9113 pub mod DATA_BYTE_7 {
9114 pub const offset: u32 = 0;
9115 pub const mask: u32 = 0xff << offset;
9116 pub mod R {}
9117 pub mod W {}
9118 pub mod RW {}
9119 }
9120 #[doc = "Data byte 1 of Rx/Tx frame."]
9121 pub mod DATA_BYTE_6 {
9122 pub const offset: u32 = 8;
9123 pub const mask: u32 = 0xff << offset;
9124 pub mod R {}
9125 pub mod W {}
9126 pub mod RW {}
9127 }
9128 #[doc = "Data byte 2 of Rx/Tx frame."]
9129 pub mod DATA_BYTE_5 {
9130 pub const offset: u32 = 16;
9131 pub const mask: u32 = 0xff << offset;
9132 pub mod R {}
9133 pub mod W {}
9134 pub mod RW {}
9135 }
9136 #[doc = "Data byte 3 of Rx/Tx frame."]
9137 pub mod DATA_BYTE_4 {
9138 pub const offset: u32 = 24;
9139 pub const mask: u32 = 0xff << offset;
9140 pub mod R {}
9141 pub mod W {}
9142 pub mod RW {}
9143 }
9144}
9145#[doc = "Message Buffer 41 CS Register"]
9146pub mod CS41 {
9147 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
9148 pub mod TIME_STAMP {
9149 pub const offset: u32 = 0;
9150 pub const mask: u32 = 0xffff << offset;
9151 pub mod R {}
9152 pub mod W {}
9153 pub mod RW {}
9154 }
9155 #[doc = "Length of the data to be stored/transmitted."]
9156 pub mod DLC {
9157 pub const offset: u32 = 16;
9158 pub const mask: u32 = 0x0f << offset;
9159 pub mod R {}
9160 pub mod W {}
9161 pub mod RW {}
9162 }
9163 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
9164 pub mod RTR {
9165 pub const offset: u32 = 20;
9166 pub const mask: u32 = 0x01 << offset;
9167 pub mod R {}
9168 pub mod W {}
9169 pub mod RW {}
9170 }
9171 #[doc = "ID Extended. One/zero for extended/standard format frame."]
9172 pub mod IDE {
9173 pub const offset: u32 = 21;
9174 pub const mask: u32 = 0x01 << offset;
9175 pub mod R {}
9176 pub mod W {}
9177 pub mod RW {}
9178 }
9179 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
9180 pub mod SRR {
9181 pub const offset: u32 = 22;
9182 pub const mask: u32 = 0x01 << offset;
9183 pub mod R {}
9184 pub mod W {}
9185 pub mod RW {}
9186 }
9187 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
9188 pub mod CODE {
9189 pub const offset: u32 = 24;
9190 pub const mask: u32 = 0x0f << offset;
9191 pub mod R {}
9192 pub mod W {}
9193 pub mod RW {}
9194 }
9195 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
9196 pub mod ESI {
9197 pub const offset: u32 = 29;
9198 pub const mask: u32 = 0x01 << offset;
9199 pub mod R {}
9200 pub mod W {}
9201 pub mod RW {}
9202 }
9203 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
9204 pub mod BRS {
9205 pub const offset: u32 = 30;
9206 pub const mask: u32 = 0x01 << offset;
9207 pub mod R {}
9208 pub mod W {}
9209 pub mod RW {}
9210 }
9211 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
9212 pub mod EDL {
9213 pub const offset: u32 = 31;
9214 pub const mask: u32 = 0x01 << offset;
9215 pub mod R {}
9216 pub mod W {}
9217 pub mod RW {}
9218 }
9219}
9220#[doc = "Message Buffer 41 ID Register"]
9221pub mod ID41 {
9222 #[doc = "Contains extended (LOW word) identifier of message buffer."]
9223 pub mod EXT {
9224 pub const offset: u32 = 0;
9225 pub const mask: u32 = 0x0003_ffff << offset;
9226 pub mod R {}
9227 pub mod W {}
9228 pub mod RW {}
9229 }
9230 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
9231 pub mod STD {
9232 pub const offset: u32 = 18;
9233 pub const mask: u32 = 0x07ff << offset;
9234 pub mod R {}
9235 pub mod W {}
9236 pub mod RW {}
9237 }
9238 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
9239 pub mod PRIO {
9240 pub const offset: u32 = 29;
9241 pub const mask: u32 = 0x07 << offset;
9242 pub mod R {}
9243 pub mod W {}
9244 pub mod RW {}
9245 }
9246}
9247#[doc = "Message Buffer 16 WORD_32B Register"]
9248pub mod MB16_32B_WORD4 {
9249 #[doc = "Data byte 0 of Rx/Tx frame."]
9250 pub mod DATA_BYTE_19 {
9251 pub const offset: u32 = 0;
9252 pub const mask: u32 = 0xff << offset;
9253 pub mod R {}
9254 pub mod W {}
9255 pub mod RW {}
9256 }
9257 #[doc = "Data byte 1 of Rx/Tx frame."]
9258 pub mod DATA_BYTE_18 {
9259 pub const offset: u32 = 8;
9260 pub const mask: u32 = 0xff << offset;
9261 pub mod R {}
9262 pub mod W {}
9263 pub mod RW {}
9264 }
9265 #[doc = "Data byte 2 of Rx/Tx frame."]
9266 pub mod DATA_BYTE_17 {
9267 pub const offset: u32 = 16;
9268 pub const mask: u32 = 0xff << offset;
9269 pub mod R {}
9270 pub mod W {}
9271 pub mod RW {}
9272 }
9273 #[doc = "Data byte 3 of Rx/Tx frame."]
9274 pub mod DATA_BYTE_16 {
9275 pub const offset: u32 = 24;
9276 pub const mask: u32 = 0xff << offset;
9277 pub mod R {}
9278 pub mod W {}
9279 pub mod RW {}
9280 }
9281}
9282#[doc = "Message Buffer 16 WORD_32B Register"]
9283pub mod MB16_32B_WORD5 {
9284 #[doc = "Data byte 0 of Rx/Tx frame."]
9285 pub mod DATA_BYTE_23 {
9286 pub const offset: u32 = 0;
9287 pub const mask: u32 = 0xff << offset;
9288 pub mod R {}
9289 pub mod W {}
9290 pub mod RW {}
9291 }
9292 #[doc = "Data byte 1 of Rx/Tx frame."]
9293 pub mod DATA_BYTE_22 {
9294 pub const offset: u32 = 8;
9295 pub const mask: u32 = 0xff << offset;
9296 pub mod R {}
9297 pub mod W {}
9298 pub mod RW {}
9299 }
9300 #[doc = "Data byte 2 of Rx/Tx frame."]
9301 pub mod DATA_BYTE_21 {
9302 pub const offset: u32 = 16;
9303 pub const mask: u32 = 0xff << offset;
9304 pub mod R {}
9305 pub mod W {}
9306 pub mod RW {}
9307 }
9308 #[doc = "Data byte 3 of Rx/Tx frame."]
9309 pub mod DATA_BYTE_20 {
9310 pub const offset: u32 = 24;
9311 pub const mask: u32 = 0xff << offset;
9312 pub mod R {}
9313 pub mod W {}
9314 pub mod RW {}
9315 }
9316}
9317#[doc = "Message Buffer 42 CS Register"]
9318pub mod CS42 {
9319 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
9320 pub mod TIME_STAMP {
9321 pub const offset: u32 = 0;
9322 pub const mask: u32 = 0xffff << offset;
9323 pub mod R {}
9324 pub mod W {}
9325 pub mod RW {}
9326 }
9327 #[doc = "Length of the data to be stored/transmitted."]
9328 pub mod DLC {
9329 pub const offset: u32 = 16;
9330 pub const mask: u32 = 0x0f << offset;
9331 pub mod R {}
9332 pub mod W {}
9333 pub mod RW {}
9334 }
9335 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
9336 pub mod RTR {
9337 pub const offset: u32 = 20;
9338 pub const mask: u32 = 0x01 << offset;
9339 pub mod R {}
9340 pub mod W {}
9341 pub mod RW {}
9342 }
9343 #[doc = "ID Extended. One/zero for extended/standard format frame."]
9344 pub mod IDE {
9345 pub const offset: u32 = 21;
9346 pub const mask: u32 = 0x01 << offset;
9347 pub mod R {}
9348 pub mod W {}
9349 pub mod RW {}
9350 }
9351 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
9352 pub mod SRR {
9353 pub const offset: u32 = 22;
9354 pub const mask: u32 = 0x01 << offset;
9355 pub mod R {}
9356 pub mod W {}
9357 pub mod RW {}
9358 }
9359 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
9360 pub mod CODE {
9361 pub const offset: u32 = 24;
9362 pub const mask: u32 = 0x0f << offset;
9363 pub mod R {}
9364 pub mod W {}
9365 pub mod RW {}
9366 }
9367 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
9368 pub mod ESI {
9369 pub const offset: u32 = 29;
9370 pub const mask: u32 = 0x01 << offset;
9371 pub mod R {}
9372 pub mod W {}
9373 pub mod RW {}
9374 }
9375 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
9376 pub mod BRS {
9377 pub const offset: u32 = 30;
9378 pub const mask: u32 = 0x01 << offset;
9379 pub mod R {}
9380 pub mod W {}
9381 pub mod RW {}
9382 }
9383 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
9384 pub mod EDL {
9385 pub const offset: u32 = 31;
9386 pub const mask: u32 = 0x01 << offset;
9387 pub mod R {}
9388 pub mod W {}
9389 pub mod RW {}
9390 }
9391}
9392#[doc = "Message Buffer 42 ID Register"]
9393pub mod ID42 {
9394 #[doc = "Contains extended (LOW word) identifier of message buffer."]
9395 pub mod EXT {
9396 pub const offset: u32 = 0;
9397 pub const mask: u32 = 0x0003_ffff << offset;
9398 pub mod R {}
9399 pub mod W {}
9400 pub mod RW {}
9401 }
9402 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
9403 pub mod STD {
9404 pub const offset: u32 = 18;
9405 pub const mask: u32 = 0x07ff << offset;
9406 pub mod R {}
9407 pub mod W {}
9408 pub mod RW {}
9409 }
9410 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
9411 pub mod PRIO {
9412 pub const offset: u32 = 29;
9413 pub const mask: u32 = 0x07 << offset;
9414 pub mod R {}
9415 pub mod W {}
9416 pub mod RW {}
9417 }
9418}
9419#[doc = "Message Buffer 17 CS Register"]
9420pub mod MB17_32B_CS {
9421 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
9422 pub mod TIME_STAMP {
9423 pub const offset: u32 = 0;
9424 pub const mask: u32 = 0xffff << offset;
9425 pub mod R {}
9426 pub mod W {}
9427 pub mod RW {}
9428 }
9429 #[doc = "Length of the data to be stored/transmitted."]
9430 pub mod DLC {
9431 pub const offset: u32 = 16;
9432 pub const mask: u32 = 0x0f << offset;
9433 pub mod R {}
9434 pub mod W {}
9435 pub mod RW {}
9436 }
9437 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
9438 pub mod RTR {
9439 pub const offset: u32 = 20;
9440 pub const mask: u32 = 0x01 << offset;
9441 pub mod R {}
9442 pub mod W {}
9443 pub mod RW {}
9444 }
9445 #[doc = "ID Extended. One/zero for extended/standard format frame."]
9446 pub mod IDE {
9447 pub const offset: u32 = 21;
9448 pub const mask: u32 = 0x01 << offset;
9449 pub mod R {}
9450 pub mod W {}
9451 pub mod RW {}
9452 }
9453 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
9454 pub mod SRR {
9455 pub const offset: u32 = 22;
9456 pub const mask: u32 = 0x01 << offset;
9457 pub mod R {}
9458 pub mod W {}
9459 pub mod RW {}
9460 }
9461 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
9462 pub mod CODE {
9463 pub const offset: u32 = 24;
9464 pub const mask: u32 = 0x0f << offset;
9465 pub mod R {}
9466 pub mod W {}
9467 pub mod RW {}
9468 }
9469 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
9470 pub mod ESI {
9471 pub const offset: u32 = 29;
9472 pub const mask: u32 = 0x01 << offset;
9473 pub mod R {}
9474 pub mod W {}
9475 pub mod RW {}
9476 }
9477 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
9478 pub mod BRS {
9479 pub const offset: u32 = 30;
9480 pub const mask: u32 = 0x01 << offset;
9481 pub mod R {}
9482 pub mod W {}
9483 pub mod RW {}
9484 }
9485 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
9486 pub mod EDL {
9487 pub const offset: u32 = 31;
9488 pub const mask: u32 = 0x01 << offset;
9489 pub mod R {}
9490 pub mod W {}
9491 pub mod RW {}
9492 }
9493}
9494#[doc = "Message Buffer 17 ID Register"]
9495pub mod MB17_32B_ID {
9496 #[doc = "Contains extended (LOW word) identifier of message buffer."]
9497 pub mod EXT {
9498 pub const offset: u32 = 0;
9499 pub const mask: u32 = 0x0003_ffff << offset;
9500 pub mod R {}
9501 pub mod W {}
9502 pub mod RW {}
9503 }
9504 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
9505 pub mod STD {
9506 pub const offset: u32 = 18;
9507 pub const mask: u32 = 0x07ff << offset;
9508 pub mod R {}
9509 pub mod W {}
9510 pub mod RW {}
9511 }
9512 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
9513 pub mod PRIO {
9514 pub const offset: u32 = 29;
9515 pub const mask: u32 = 0x07 << offset;
9516 pub mod R {}
9517 pub mod W {}
9518 pub mod RW {}
9519 }
9520}
9521#[doc = "Message Buffer 43 CS Register"]
9522pub mod CS43 {
9523 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
9524 pub mod TIME_STAMP {
9525 pub const offset: u32 = 0;
9526 pub const mask: u32 = 0xffff << offset;
9527 pub mod R {}
9528 pub mod W {}
9529 pub mod RW {}
9530 }
9531 #[doc = "Length of the data to be stored/transmitted."]
9532 pub mod DLC {
9533 pub const offset: u32 = 16;
9534 pub const mask: u32 = 0x0f << offset;
9535 pub mod R {}
9536 pub mod W {}
9537 pub mod RW {}
9538 }
9539 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
9540 pub mod RTR {
9541 pub const offset: u32 = 20;
9542 pub const mask: u32 = 0x01 << offset;
9543 pub mod R {}
9544 pub mod W {}
9545 pub mod RW {}
9546 }
9547 #[doc = "ID Extended. One/zero for extended/standard format frame."]
9548 pub mod IDE {
9549 pub const offset: u32 = 21;
9550 pub const mask: u32 = 0x01 << offset;
9551 pub mod R {}
9552 pub mod W {}
9553 pub mod RW {}
9554 }
9555 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
9556 pub mod SRR {
9557 pub const offset: u32 = 22;
9558 pub const mask: u32 = 0x01 << offset;
9559 pub mod R {}
9560 pub mod W {}
9561 pub mod RW {}
9562 }
9563 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
9564 pub mod CODE {
9565 pub const offset: u32 = 24;
9566 pub const mask: u32 = 0x0f << offset;
9567 pub mod R {}
9568 pub mod W {}
9569 pub mod RW {}
9570 }
9571 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
9572 pub mod ESI {
9573 pub const offset: u32 = 29;
9574 pub const mask: u32 = 0x01 << offset;
9575 pub mod R {}
9576 pub mod W {}
9577 pub mod RW {}
9578 }
9579 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
9580 pub mod BRS {
9581 pub const offset: u32 = 30;
9582 pub const mask: u32 = 0x01 << offset;
9583 pub mod R {}
9584 pub mod W {}
9585 pub mod RW {}
9586 }
9587 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
9588 pub mod EDL {
9589 pub const offset: u32 = 31;
9590 pub const mask: u32 = 0x01 << offset;
9591 pub mod R {}
9592 pub mod W {}
9593 pub mod RW {}
9594 }
9595}
9596#[doc = "Message Buffer 43 ID Register"]
9597pub mod ID43 {
9598 #[doc = "Contains extended (LOW word) identifier of message buffer."]
9599 pub mod EXT {
9600 pub const offset: u32 = 0;
9601 pub const mask: u32 = 0x0003_ffff << offset;
9602 pub mod R {}
9603 pub mod W {}
9604 pub mod RW {}
9605 }
9606 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
9607 pub mod STD {
9608 pub const offset: u32 = 18;
9609 pub const mask: u32 = 0x07ff << offset;
9610 pub mod R {}
9611 pub mod W {}
9612 pub mod RW {}
9613 }
9614 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
9615 pub mod PRIO {
9616 pub const offset: u32 = 29;
9617 pub const mask: u32 = 0x07 << offset;
9618 pub mod R {}
9619 pub mod W {}
9620 pub mod RW {}
9621 }
9622}
9623#[doc = "Message Buffer 17 WORD_32B Register"]
9624pub mod MB17_32B_WORD2 {
9625 #[doc = "Data byte 0 of Rx/Tx frame."]
9626 pub mod DATA_BYTE_11 {
9627 pub const offset: u32 = 0;
9628 pub const mask: u32 = 0xff << offset;
9629 pub mod R {}
9630 pub mod W {}
9631 pub mod RW {}
9632 }
9633 #[doc = "Data byte 1 of Rx/Tx frame."]
9634 pub mod DATA_BYTE_10 {
9635 pub const offset: u32 = 8;
9636 pub const mask: u32 = 0xff << offset;
9637 pub mod R {}
9638 pub mod W {}
9639 pub mod RW {}
9640 }
9641 #[doc = "Data byte 2 of Rx/Tx frame."]
9642 pub mod DATA_BYTE_9 {
9643 pub const offset: u32 = 16;
9644 pub const mask: u32 = 0xff << offset;
9645 pub mod R {}
9646 pub mod W {}
9647 pub mod RW {}
9648 }
9649 #[doc = "Data byte 3 of Rx/Tx frame."]
9650 pub mod DATA_BYTE_8 {
9651 pub const offset: u32 = 24;
9652 pub const mask: u32 = 0xff << offset;
9653 pub mod R {}
9654 pub mod W {}
9655 pub mod RW {}
9656 }
9657}
9658#[doc = "Message Buffer 17 WORD_32B Register"]
9659pub mod MB17_32B_WORD3 {
9660 #[doc = "Data byte 0 of Rx/Tx frame."]
9661 pub mod DATA_BYTE_15 {
9662 pub const offset: u32 = 0;
9663 pub const mask: u32 = 0xff << offset;
9664 pub mod R {}
9665 pub mod W {}
9666 pub mod RW {}
9667 }
9668 #[doc = "Data byte 1 of Rx/Tx frame."]
9669 pub mod DATA_BYTE_14 {
9670 pub const offset: u32 = 8;
9671 pub const mask: u32 = 0xff << offset;
9672 pub mod R {}
9673 pub mod W {}
9674 pub mod RW {}
9675 }
9676 #[doc = "Data byte 2 of Rx/Tx frame."]
9677 pub mod DATA_BYTE_13 {
9678 pub const offset: u32 = 16;
9679 pub const mask: u32 = 0xff << offset;
9680 pub mod R {}
9681 pub mod W {}
9682 pub mod RW {}
9683 }
9684 #[doc = "Data byte 3 of Rx/Tx frame."]
9685 pub mod DATA_BYTE_12 {
9686 pub const offset: u32 = 24;
9687 pub const mask: u32 = 0xff << offset;
9688 pub mod R {}
9689 pub mod W {}
9690 pub mod RW {}
9691 }
9692}
9693#[doc = "Message Buffer 44 CS Register"]
9694pub mod CS44 {
9695 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
9696 pub mod TIME_STAMP {
9697 pub const offset: u32 = 0;
9698 pub const mask: u32 = 0xffff << offset;
9699 pub mod R {}
9700 pub mod W {}
9701 pub mod RW {}
9702 }
9703 #[doc = "Length of the data to be stored/transmitted."]
9704 pub mod DLC {
9705 pub const offset: u32 = 16;
9706 pub const mask: u32 = 0x0f << offset;
9707 pub mod R {}
9708 pub mod W {}
9709 pub mod RW {}
9710 }
9711 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
9712 pub mod RTR {
9713 pub const offset: u32 = 20;
9714 pub const mask: u32 = 0x01 << offset;
9715 pub mod R {}
9716 pub mod W {}
9717 pub mod RW {}
9718 }
9719 #[doc = "ID Extended. One/zero for extended/standard format frame."]
9720 pub mod IDE {
9721 pub const offset: u32 = 21;
9722 pub const mask: u32 = 0x01 << offset;
9723 pub mod R {}
9724 pub mod W {}
9725 pub mod RW {}
9726 }
9727 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
9728 pub mod SRR {
9729 pub const offset: u32 = 22;
9730 pub const mask: u32 = 0x01 << offset;
9731 pub mod R {}
9732 pub mod W {}
9733 pub mod RW {}
9734 }
9735 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
9736 pub mod CODE {
9737 pub const offset: u32 = 24;
9738 pub const mask: u32 = 0x0f << offset;
9739 pub mod R {}
9740 pub mod W {}
9741 pub mod RW {}
9742 }
9743 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
9744 pub mod ESI {
9745 pub const offset: u32 = 29;
9746 pub const mask: u32 = 0x01 << offset;
9747 pub mod R {}
9748 pub mod W {}
9749 pub mod RW {}
9750 }
9751 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
9752 pub mod BRS {
9753 pub const offset: u32 = 30;
9754 pub const mask: u32 = 0x01 << offset;
9755 pub mod R {}
9756 pub mod W {}
9757 pub mod RW {}
9758 }
9759 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
9760 pub mod EDL {
9761 pub const offset: u32 = 31;
9762 pub const mask: u32 = 0x01 << offset;
9763 pub mod R {}
9764 pub mod W {}
9765 pub mod RW {}
9766 }
9767}
9768#[doc = "Message Buffer 44 ID Register"]
9769pub mod ID44 {
9770 #[doc = "Contains extended (LOW word) identifier of message buffer."]
9771 pub mod EXT {
9772 pub const offset: u32 = 0;
9773 pub const mask: u32 = 0x0003_ffff << offset;
9774 pub mod R {}
9775 pub mod W {}
9776 pub mod RW {}
9777 }
9778 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
9779 pub mod STD {
9780 pub const offset: u32 = 18;
9781 pub const mask: u32 = 0x07ff << offset;
9782 pub mod R {}
9783 pub mod W {}
9784 pub mod RW {}
9785 }
9786 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
9787 pub mod PRIO {
9788 pub const offset: u32 = 29;
9789 pub const mask: u32 = 0x07 << offset;
9790 pub mod R {}
9791 pub mod W {}
9792 pub mod RW {}
9793 }
9794}
9795#[doc = "Message Buffer 17 WORD_32B Register"]
9796pub mod MB17_32B_WORD6 {
9797 #[doc = "Data byte 0 of Rx/Tx frame."]
9798 pub mod DATA_BYTE_27 {
9799 pub const offset: u32 = 0;
9800 pub const mask: u32 = 0xff << offset;
9801 pub mod R {}
9802 pub mod W {}
9803 pub mod RW {}
9804 }
9805 #[doc = "Data byte 1 of Rx/Tx frame."]
9806 pub mod DATA_BYTE_26 {
9807 pub const offset: u32 = 8;
9808 pub const mask: u32 = 0xff << offset;
9809 pub mod R {}
9810 pub mod W {}
9811 pub mod RW {}
9812 }
9813 #[doc = "Data byte 2 of Rx/Tx frame."]
9814 pub mod DATA_BYTE_25 {
9815 pub const offset: u32 = 16;
9816 pub const mask: u32 = 0xff << offset;
9817 pub mod R {}
9818 pub mod W {}
9819 pub mod RW {}
9820 }
9821 #[doc = "Data byte 3 of Rx/Tx frame."]
9822 pub mod DATA_BYTE_24 {
9823 pub const offset: u32 = 24;
9824 pub const mask: u32 = 0xff << offset;
9825 pub mod R {}
9826 pub mod W {}
9827 pub mod RW {}
9828 }
9829}
9830#[doc = "Message Buffer 17 WORD_32B Register"]
9831pub mod MB17_32B_WORD7 {
9832 #[doc = "Data byte 0 of Rx/Tx frame."]
9833 pub mod DATA_BYTE_31 {
9834 pub const offset: u32 = 0;
9835 pub const mask: u32 = 0xff << offset;
9836 pub mod R {}
9837 pub mod W {}
9838 pub mod RW {}
9839 }
9840 #[doc = "Data byte 1 of Rx/Tx frame."]
9841 pub mod DATA_BYTE_30 {
9842 pub const offset: u32 = 8;
9843 pub const mask: u32 = 0xff << offset;
9844 pub mod R {}
9845 pub mod W {}
9846 pub mod RW {}
9847 }
9848 #[doc = "Data byte 2 of Rx/Tx frame."]
9849 pub mod DATA_BYTE_29 {
9850 pub const offset: u32 = 16;
9851 pub const mask: u32 = 0xff << offset;
9852 pub mod R {}
9853 pub mod W {}
9854 pub mod RW {}
9855 }
9856 #[doc = "Data byte 3 of Rx/Tx frame."]
9857 pub mod DATA_BYTE_28 {
9858 pub const offset: u32 = 24;
9859 pub const mask: u32 = 0xff << offset;
9860 pub mod R {}
9861 pub mod W {}
9862 pub mod RW {}
9863 }
9864}
9865#[doc = "Message Buffer 45 CS Register"]
9866pub mod CS45 {
9867 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
9868 pub mod TIME_STAMP {
9869 pub const offset: u32 = 0;
9870 pub const mask: u32 = 0xffff << offset;
9871 pub mod R {}
9872 pub mod W {}
9873 pub mod RW {}
9874 }
9875 #[doc = "Length of the data to be stored/transmitted."]
9876 pub mod DLC {
9877 pub const offset: u32 = 16;
9878 pub const mask: u32 = 0x0f << offset;
9879 pub mod R {}
9880 pub mod W {}
9881 pub mod RW {}
9882 }
9883 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
9884 pub mod RTR {
9885 pub const offset: u32 = 20;
9886 pub const mask: u32 = 0x01 << offset;
9887 pub mod R {}
9888 pub mod W {}
9889 pub mod RW {}
9890 }
9891 #[doc = "ID Extended. One/zero for extended/standard format frame."]
9892 pub mod IDE {
9893 pub const offset: u32 = 21;
9894 pub const mask: u32 = 0x01 << offset;
9895 pub mod R {}
9896 pub mod W {}
9897 pub mod RW {}
9898 }
9899 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
9900 pub mod SRR {
9901 pub const offset: u32 = 22;
9902 pub const mask: u32 = 0x01 << offset;
9903 pub mod R {}
9904 pub mod W {}
9905 pub mod RW {}
9906 }
9907 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
9908 pub mod CODE {
9909 pub const offset: u32 = 24;
9910 pub const mask: u32 = 0x0f << offset;
9911 pub mod R {}
9912 pub mod W {}
9913 pub mod RW {}
9914 }
9915 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
9916 pub mod ESI {
9917 pub const offset: u32 = 29;
9918 pub const mask: u32 = 0x01 << offset;
9919 pub mod R {}
9920 pub mod W {}
9921 pub mod RW {}
9922 }
9923 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
9924 pub mod BRS {
9925 pub const offset: u32 = 30;
9926 pub const mask: u32 = 0x01 << offset;
9927 pub mod R {}
9928 pub mod W {}
9929 pub mod RW {}
9930 }
9931 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
9932 pub mod EDL {
9933 pub const offset: u32 = 31;
9934 pub const mask: u32 = 0x01 << offset;
9935 pub mod R {}
9936 pub mod W {}
9937 pub mod RW {}
9938 }
9939}
9940#[doc = "Message Buffer 45 ID Register"]
9941pub mod ID45 {
9942 #[doc = "Contains extended (LOW word) identifier of message buffer."]
9943 pub mod EXT {
9944 pub const offset: u32 = 0;
9945 pub const mask: u32 = 0x0003_ffff << offset;
9946 pub mod R {}
9947 pub mod W {}
9948 pub mod RW {}
9949 }
9950 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
9951 pub mod STD {
9952 pub const offset: u32 = 18;
9953 pub const mask: u32 = 0x07ff << offset;
9954 pub mod R {}
9955 pub mod W {}
9956 pub mod RW {}
9957 }
9958 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
9959 pub mod PRIO {
9960 pub const offset: u32 = 29;
9961 pub const mask: u32 = 0x07 << offset;
9962 pub mod R {}
9963 pub mod W {}
9964 pub mod RW {}
9965 }
9966}
9967#[doc = "Message Buffer 10 WORD_64B Register"]
9968pub mod MB10_64B_WORD0 {
9969 #[doc = "Data byte 0 of Rx/Tx frame."]
9970 pub mod DATA_BYTE_3 {
9971 pub const offset: u32 = 0;
9972 pub const mask: u32 = 0xff << offset;
9973 pub mod R {}
9974 pub mod W {}
9975 pub mod RW {}
9976 }
9977 #[doc = "Data byte 1 of Rx/Tx frame."]
9978 pub mod DATA_BYTE_2 {
9979 pub const offset: u32 = 8;
9980 pub const mask: u32 = 0xff << offset;
9981 pub mod R {}
9982 pub mod W {}
9983 pub mod RW {}
9984 }
9985 #[doc = "Data byte 2 of Rx/Tx frame."]
9986 pub mod DATA_BYTE_1 {
9987 pub const offset: u32 = 16;
9988 pub const mask: u32 = 0xff << offset;
9989 pub mod R {}
9990 pub mod W {}
9991 pub mod RW {}
9992 }
9993 #[doc = "Data byte 3 of Rx/Tx frame."]
9994 pub mod DATA_BYTE_0 {
9995 pub const offset: u32 = 24;
9996 pub const mask: u32 = 0xff << offset;
9997 pub mod R {}
9998 pub mod W {}
9999 pub mod RW {}
10000 }
10001}
10002#[doc = "Message Buffer 10 WORD_64B Register"]
10003pub mod MB10_64B_WORD1 {
10004 #[doc = "Data byte 0 of Rx/Tx frame."]
10005 pub mod DATA_BYTE_7 {
10006 pub const offset: u32 = 0;
10007 pub const mask: u32 = 0xff << offset;
10008 pub mod R {}
10009 pub mod W {}
10010 pub mod RW {}
10011 }
10012 #[doc = "Data byte 1 of Rx/Tx frame."]
10013 pub mod DATA_BYTE_6 {
10014 pub const offset: u32 = 8;
10015 pub const mask: u32 = 0xff << offset;
10016 pub mod R {}
10017 pub mod W {}
10018 pub mod RW {}
10019 }
10020 #[doc = "Data byte 2 of Rx/Tx frame."]
10021 pub mod DATA_BYTE_5 {
10022 pub const offset: u32 = 16;
10023 pub const mask: u32 = 0xff << offset;
10024 pub mod R {}
10025 pub mod W {}
10026 pub mod RW {}
10027 }
10028 #[doc = "Data byte 3 of Rx/Tx frame."]
10029 pub mod DATA_BYTE_4 {
10030 pub const offset: u32 = 24;
10031 pub const mask: u32 = 0xff << offset;
10032 pub mod R {}
10033 pub mod W {}
10034 pub mod RW {}
10035 }
10036}
10037#[doc = "Message Buffer 46 CS Register"]
10038pub mod CS46 {
10039 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
10040 pub mod TIME_STAMP {
10041 pub const offset: u32 = 0;
10042 pub const mask: u32 = 0xffff << offset;
10043 pub mod R {}
10044 pub mod W {}
10045 pub mod RW {}
10046 }
10047 #[doc = "Length of the data to be stored/transmitted."]
10048 pub mod DLC {
10049 pub const offset: u32 = 16;
10050 pub const mask: u32 = 0x0f << offset;
10051 pub mod R {}
10052 pub mod W {}
10053 pub mod RW {}
10054 }
10055 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
10056 pub mod RTR {
10057 pub const offset: u32 = 20;
10058 pub const mask: u32 = 0x01 << offset;
10059 pub mod R {}
10060 pub mod W {}
10061 pub mod RW {}
10062 }
10063 #[doc = "ID Extended. One/zero for extended/standard format frame."]
10064 pub mod IDE {
10065 pub const offset: u32 = 21;
10066 pub const mask: u32 = 0x01 << offset;
10067 pub mod R {}
10068 pub mod W {}
10069 pub mod RW {}
10070 }
10071 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
10072 pub mod SRR {
10073 pub const offset: u32 = 22;
10074 pub const mask: u32 = 0x01 << offset;
10075 pub mod R {}
10076 pub mod W {}
10077 pub mod RW {}
10078 }
10079 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
10080 pub mod CODE {
10081 pub const offset: u32 = 24;
10082 pub const mask: u32 = 0x0f << offset;
10083 pub mod R {}
10084 pub mod W {}
10085 pub mod RW {}
10086 }
10087 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
10088 pub mod ESI {
10089 pub const offset: u32 = 29;
10090 pub const mask: u32 = 0x01 << offset;
10091 pub mod R {}
10092 pub mod W {}
10093 pub mod RW {}
10094 }
10095 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
10096 pub mod BRS {
10097 pub const offset: u32 = 30;
10098 pub const mask: u32 = 0x01 << offset;
10099 pub mod R {}
10100 pub mod W {}
10101 pub mod RW {}
10102 }
10103 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
10104 pub mod EDL {
10105 pub const offset: u32 = 31;
10106 pub const mask: u32 = 0x01 << offset;
10107 pub mod R {}
10108 pub mod W {}
10109 pub mod RW {}
10110 }
10111}
10112#[doc = "Message Buffer 46 ID Register"]
10113pub mod ID46 {
10114 #[doc = "Contains extended (LOW word) identifier of message buffer."]
10115 pub mod EXT {
10116 pub const offset: u32 = 0;
10117 pub const mask: u32 = 0x0003_ffff << offset;
10118 pub mod R {}
10119 pub mod W {}
10120 pub mod RW {}
10121 }
10122 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
10123 pub mod STD {
10124 pub const offset: u32 = 18;
10125 pub const mask: u32 = 0x07ff << offset;
10126 pub mod R {}
10127 pub mod W {}
10128 pub mod RW {}
10129 }
10130 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
10131 pub mod PRIO {
10132 pub const offset: u32 = 29;
10133 pub const mask: u32 = 0x07 << offset;
10134 pub mod R {}
10135 pub mod W {}
10136 pub mod RW {}
10137 }
10138}
10139#[doc = "Message Buffer 10 WORD_64B Register"]
10140pub mod MB10_64B_WORD4 {
10141 #[doc = "Data byte 0 of Rx/Tx frame."]
10142 pub mod DATA_BYTE_19 {
10143 pub const offset: u32 = 0;
10144 pub const mask: u32 = 0xff << offset;
10145 pub mod R {}
10146 pub mod W {}
10147 pub mod RW {}
10148 }
10149 #[doc = "Data byte 1 of Rx/Tx frame."]
10150 pub mod DATA_BYTE_18 {
10151 pub const offset: u32 = 8;
10152 pub const mask: u32 = 0xff << offset;
10153 pub mod R {}
10154 pub mod W {}
10155 pub mod RW {}
10156 }
10157 #[doc = "Data byte 2 of Rx/Tx frame."]
10158 pub mod DATA_BYTE_17 {
10159 pub const offset: u32 = 16;
10160 pub const mask: u32 = 0xff << offset;
10161 pub mod R {}
10162 pub mod W {}
10163 pub mod RW {}
10164 }
10165 #[doc = "Data byte 3 of Rx/Tx frame."]
10166 pub mod DATA_BYTE_16 {
10167 pub const offset: u32 = 24;
10168 pub const mask: u32 = 0xff << offset;
10169 pub mod R {}
10170 pub mod W {}
10171 pub mod RW {}
10172 }
10173}
10174#[doc = "Message Buffer 10 WORD_64B Register"]
10175pub mod MB10_64B_WORD5 {
10176 #[doc = "Data byte 0 of Rx/Tx frame."]
10177 pub mod DATA_BYTE_23 {
10178 pub const offset: u32 = 0;
10179 pub const mask: u32 = 0xff << offset;
10180 pub mod R {}
10181 pub mod W {}
10182 pub mod RW {}
10183 }
10184 #[doc = "Data byte 1 of Rx/Tx frame."]
10185 pub mod DATA_BYTE_22 {
10186 pub const offset: u32 = 8;
10187 pub const mask: u32 = 0xff << offset;
10188 pub mod R {}
10189 pub mod W {}
10190 pub mod RW {}
10191 }
10192 #[doc = "Data byte 2 of Rx/Tx frame."]
10193 pub mod DATA_BYTE_21 {
10194 pub const offset: u32 = 16;
10195 pub const mask: u32 = 0xff << offset;
10196 pub mod R {}
10197 pub mod W {}
10198 pub mod RW {}
10199 }
10200 #[doc = "Data byte 3 of Rx/Tx frame."]
10201 pub mod DATA_BYTE_20 {
10202 pub const offset: u32 = 24;
10203 pub const mask: u32 = 0xff << offset;
10204 pub mod R {}
10205 pub mod W {}
10206 pub mod RW {}
10207 }
10208}
10209#[doc = "Message Buffer 47 CS Register"]
10210pub mod CS47 {
10211 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
10212 pub mod TIME_STAMP {
10213 pub const offset: u32 = 0;
10214 pub const mask: u32 = 0xffff << offset;
10215 pub mod R {}
10216 pub mod W {}
10217 pub mod RW {}
10218 }
10219 #[doc = "Length of the data to be stored/transmitted."]
10220 pub mod DLC {
10221 pub const offset: u32 = 16;
10222 pub const mask: u32 = 0x0f << offset;
10223 pub mod R {}
10224 pub mod W {}
10225 pub mod RW {}
10226 }
10227 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
10228 pub mod RTR {
10229 pub const offset: u32 = 20;
10230 pub const mask: u32 = 0x01 << offset;
10231 pub mod R {}
10232 pub mod W {}
10233 pub mod RW {}
10234 }
10235 #[doc = "ID Extended. One/zero for extended/standard format frame."]
10236 pub mod IDE {
10237 pub const offset: u32 = 21;
10238 pub const mask: u32 = 0x01 << offset;
10239 pub mod R {}
10240 pub mod W {}
10241 pub mod RW {}
10242 }
10243 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
10244 pub mod SRR {
10245 pub const offset: u32 = 22;
10246 pub const mask: u32 = 0x01 << offset;
10247 pub mod R {}
10248 pub mod W {}
10249 pub mod RW {}
10250 }
10251 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
10252 pub mod CODE {
10253 pub const offset: u32 = 24;
10254 pub const mask: u32 = 0x0f << offset;
10255 pub mod R {}
10256 pub mod W {}
10257 pub mod RW {}
10258 }
10259 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
10260 pub mod ESI {
10261 pub const offset: u32 = 29;
10262 pub const mask: u32 = 0x01 << offset;
10263 pub mod R {}
10264 pub mod W {}
10265 pub mod RW {}
10266 }
10267 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
10268 pub mod BRS {
10269 pub const offset: u32 = 30;
10270 pub const mask: u32 = 0x01 << offset;
10271 pub mod R {}
10272 pub mod W {}
10273 pub mod RW {}
10274 }
10275 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
10276 pub mod EDL {
10277 pub const offset: u32 = 31;
10278 pub const mask: u32 = 0x01 << offset;
10279 pub mod R {}
10280 pub mod W {}
10281 pub mod RW {}
10282 }
10283}
10284#[doc = "Message Buffer 47 ID Register"]
10285pub mod ID47 {
10286 #[doc = "Contains extended (LOW word) identifier of message buffer."]
10287 pub mod EXT {
10288 pub const offset: u32 = 0;
10289 pub const mask: u32 = 0x0003_ffff << offset;
10290 pub mod R {}
10291 pub mod W {}
10292 pub mod RW {}
10293 }
10294 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
10295 pub mod STD {
10296 pub const offset: u32 = 18;
10297 pub const mask: u32 = 0x07ff << offset;
10298 pub mod R {}
10299 pub mod W {}
10300 pub mod RW {}
10301 }
10302 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
10303 pub mod PRIO {
10304 pub const offset: u32 = 29;
10305 pub const mask: u32 = 0x07 << offset;
10306 pub mod R {}
10307 pub mod W {}
10308 pub mod RW {}
10309 }
10310}
10311#[doc = "Message Buffer 10 WORD_64B Register"]
10312pub mod MB10_64B_WORD8 {
10313 #[doc = "Data byte 0 of Rx/Tx frame."]
10314 pub mod DATA_BYTE_35 {
10315 pub const offset: u32 = 0;
10316 pub const mask: u32 = 0xff << offset;
10317 pub mod R {}
10318 pub mod W {}
10319 pub mod RW {}
10320 }
10321 #[doc = "Data byte 1 of Rx/Tx frame."]
10322 pub mod DATA_BYTE_34 {
10323 pub const offset: u32 = 8;
10324 pub const mask: u32 = 0xff << offset;
10325 pub mod R {}
10326 pub mod W {}
10327 pub mod RW {}
10328 }
10329 #[doc = "Data byte 2 of Rx/Tx frame."]
10330 pub mod DATA_BYTE_33 {
10331 pub const offset: u32 = 16;
10332 pub const mask: u32 = 0xff << offset;
10333 pub mod R {}
10334 pub mod W {}
10335 pub mod RW {}
10336 }
10337 #[doc = "Data byte 3 of Rx/Tx frame."]
10338 pub mod DATA_BYTE_32 {
10339 pub const offset: u32 = 24;
10340 pub const mask: u32 = 0xff << offset;
10341 pub mod R {}
10342 pub mod W {}
10343 pub mod RW {}
10344 }
10345}
10346#[doc = "Message Buffer 10 WORD_64B Register"]
10347pub mod MB10_64B_WORD9 {
10348 #[doc = "Data byte 0 of Rx/Tx frame."]
10349 pub mod DATA_BYTE_39 {
10350 pub const offset: u32 = 0;
10351 pub const mask: u32 = 0xff << offset;
10352 pub mod R {}
10353 pub mod W {}
10354 pub mod RW {}
10355 }
10356 #[doc = "Data byte 1 of Rx/Tx frame."]
10357 pub mod DATA_BYTE_38 {
10358 pub const offset: u32 = 8;
10359 pub const mask: u32 = 0xff << offset;
10360 pub mod R {}
10361 pub mod W {}
10362 pub mod RW {}
10363 }
10364 #[doc = "Data byte 2 of Rx/Tx frame."]
10365 pub mod DATA_BYTE_37 {
10366 pub const offset: u32 = 16;
10367 pub const mask: u32 = 0xff << offset;
10368 pub mod R {}
10369 pub mod W {}
10370 pub mod RW {}
10371 }
10372 #[doc = "Data byte 3 of Rx/Tx frame."]
10373 pub mod DATA_BYTE_36 {
10374 pub const offset: u32 = 24;
10375 pub const mask: u32 = 0xff << offset;
10376 pub mod R {}
10377 pub mod W {}
10378 pub mod RW {}
10379 }
10380}
10381#[doc = "Message Buffer 48 CS Register"]
10382pub mod CS48 {
10383 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
10384 pub mod TIME_STAMP {
10385 pub const offset: u32 = 0;
10386 pub const mask: u32 = 0xffff << offset;
10387 pub mod R {}
10388 pub mod W {}
10389 pub mod RW {}
10390 }
10391 #[doc = "Length of the data to be stored/transmitted."]
10392 pub mod DLC {
10393 pub const offset: u32 = 16;
10394 pub const mask: u32 = 0x0f << offset;
10395 pub mod R {}
10396 pub mod W {}
10397 pub mod RW {}
10398 }
10399 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
10400 pub mod RTR {
10401 pub const offset: u32 = 20;
10402 pub const mask: u32 = 0x01 << offset;
10403 pub mod R {}
10404 pub mod W {}
10405 pub mod RW {}
10406 }
10407 #[doc = "ID Extended. One/zero for extended/standard format frame."]
10408 pub mod IDE {
10409 pub const offset: u32 = 21;
10410 pub const mask: u32 = 0x01 << offset;
10411 pub mod R {}
10412 pub mod W {}
10413 pub mod RW {}
10414 }
10415 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
10416 pub mod SRR {
10417 pub const offset: u32 = 22;
10418 pub const mask: u32 = 0x01 << offset;
10419 pub mod R {}
10420 pub mod W {}
10421 pub mod RW {}
10422 }
10423 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
10424 pub mod CODE {
10425 pub const offset: u32 = 24;
10426 pub const mask: u32 = 0x0f << offset;
10427 pub mod R {}
10428 pub mod W {}
10429 pub mod RW {}
10430 }
10431 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
10432 pub mod ESI {
10433 pub const offset: u32 = 29;
10434 pub const mask: u32 = 0x01 << offset;
10435 pub mod R {}
10436 pub mod W {}
10437 pub mod RW {}
10438 }
10439 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
10440 pub mod BRS {
10441 pub const offset: u32 = 30;
10442 pub const mask: u32 = 0x01 << offset;
10443 pub mod R {}
10444 pub mod W {}
10445 pub mod RW {}
10446 }
10447 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
10448 pub mod EDL {
10449 pub const offset: u32 = 31;
10450 pub const mask: u32 = 0x01 << offset;
10451 pub mod R {}
10452 pub mod W {}
10453 pub mod RW {}
10454 }
10455}
10456#[doc = "Message Buffer 48 ID Register"]
10457pub mod ID48 {
10458 #[doc = "Contains extended (LOW word) identifier of message buffer."]
10459 pub mod EXT {
10460 pub const offset: u32 = 0;
10461 pub const mask: u32 = 0x0003_ffff << offset;
10462 pub mod R {}
10463 pub mod W {}
10464 pub mod RW {}
10465 }
10466 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
10467 pub mod STD {
10468 pub const offset: u32 = 18;
10469 pub const mask: u32 = 0x07ff << offset;
10470 pub mod R {}
10471 pub mod W {}
10472 pub mod RW {}
10473 }
10474 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
10475 pub mod PRIO {
10476 pub const offset: u32 = 29;
10477 pub const mask: u32 = 0x07 << offset;
10478 pub mod R {}
10479 pub mod W {}
10480 pub mod RW {}
10481 }
10482}
10483#[doc = "Message Buffer 10 WORD_64B Register"]
10484pub mod MB10_64B_WORD12 {
10485 #[doc = "Data byte 0 of Rx/Tx frame."]
10486 pub mod DATA_BYTE_51 {
10487 pub const offset: u32 = 0;
10488 pub const mask: u32 = 0xff << offset;
10489 pub mod R {}
10490 pub mod W {}
10491 pub mod RW {}
10492 }
10493 #[doc = "Data byte 1 of Rx/Tx frame."]
10494 pub mod DATA_BYTE_50 {
10495 pub const offset: u32 = 8;
10496 pub const mask: u32 = 0xff << offset;
10497 pub mod R {}
10498 pub mod W {}
10499 pub mod RW {}
10500 }
10501 #[doc = "Data byte 2 of Rx/Tx frame."]
10502 pub mod DATA_BYTE_49 {
10503 pub const offset: u32 = 16;
10504 pub const mask: u32 = 0xff << offset;
10505 pub mod R {}
10506 pub mod W {}
10507 pub mod RW {}
10508 }
10509 #[doc = "Data byte 3 of Rx/Tx frame."]
10510 pub mod DATA_BYTE_48 {
10511 pub const offset: u32 = 24;
10512 pub const mask: u32 = 0xff << offset;
10513 pub mod R {}
10514 pub mod W {}
10515 pub mod RW {}
10516 }
10517}
10518#[doc = "Message Buffer 10 WORD_64B Register"]
10519pub mod MB10_64B_WORD13 {
10520 #[doc = "Data byte 0 of Rx/Tx frame."]
10521 pub mod DATA_BYTE_55 {
10522 pub const offset: u32 = 0;
10523 pub const mask: u32 = 0xff << offset;
10524 pub mod R {}
10525 pub mod W {}
10526 pub mod RW {}
10527 }
10528 #[doc = "Data byte 1 of Rx/Tx frame."]
10529 pub mod DATA_BYTE_54 {
10530 pub const offset: u32 = 8;
10531 pub const mask: u32 = 0xff << offset;
10532 pub mod R {}
10533 pub mod W {}
10534 pub mod RW {}
10535 }
10536 #[doc = "Data byte 2 of Rx/Tx frame."]
10537 pub mod DATA_BYTE_53 {
10538 pub const offset: u32 = 16;
10539 pub const mask: u32 = 0xff << offset;
10540 pub mod R {}
10541 pub mod W {}
10542 pub mod RW {}
10543 }
10544 #[doc = "Data byte 3 of Rx/Tx frame."]
10545 pub mod DATA_BYTE_52 {
10546 pub const offset: u32 = 24;
10547 pub const mask: u32 = 0xff << offset;
10548 pub mod R {}
10549 pub mod W {}
10550 pub mod RW {}
10551 }
10552}
10553#[doc = "Message Buffer 49 CS Register"]
10554pub mod CS49 {
10555 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
10556 pub mod TIME_STAMP {
10557 pub const offset: u32 = 0;
10558 pub const mask: u32 = 0xffff << offset;
10559 pub mod R {}
10560 pub mod W {}
10561 pub mod RW {}
10562 }
10563 #[doc = "Length of the data to be stored/transmitted."]
10564 pub mod DLC {
10565 pub const offset: u32 = 16;
10566 pub const mask: u32 = 0x0f << offset;
10567 pub mod R {}
10568 pub mod W {}
10569 pub mod RW {}
10570 }
10571 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
10572 pub mod RTR {
10573 pub const offset: u32 = 20;
10574 pub const mask: u32 = 0x01 << offset;
10575 pub mod R {}
10576 pub mod W {}
10577 pub mod RW {}
10578 }
10579 #[doc = "ID Extended. One/zero for extended/standard format frame."]
10580 pub mod IDE {
10581 pub const offset: u32 = 21;
10582 pub const mask: u32 = 0x01 << offset;
10583 pub mod R {}
10584 pub mod W {}
10585 pub mod RW {}
10586 }
10587 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
10588 pub mod SRR {
10589 pub const offset: u32 = 22;
10590 pub const mask: u32 = 0x01 << offset;
10591 pub mod R {}
10592 pub mod W {}
10593 pub mod RW {}
10594 }
10595 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
10596 pub mod CODE {
10597 pub const offset: u32 = 24;
10598 pub const mask: u32 = 0x0f << offset;
10599 pub mod R {}
10600 pub mod W {}
10601 pub mod RW {}
10602 }
10603 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
10604 pub mod ESI {
10605 pub const offset: u32 = 29;
10606 pub const mask: u32 = 0x01 << offset;
10607 pub mod R {}
10608 pub mod W {}
10609 pub mod RW {}
10610 }
10611 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
10612 pub mod BRS {
10613 pub const offset: u32 = 30;
10614 pub const mask: u32 = 0x01 << offset;
10615 pub mod R {}
10616 pub mod W {}
10617 pub mod RW {}
10618 }
10619 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
10620 pub mod EDL {
10621 pub const offset: u32 = 31;
10622 pub const mask: u32 = 0x01 << offset;
10623 pub mod R {}
10624 pub mod W {}
10625 pub mod RW {}
10626 }
10627}
10628#[doc = "Message Buffer 49 ID Register"]
10629pub mod ID49 {
10630 #[doc = "Contains extended (LOW word) identifier of message buffer."]
10631 pub mod EXT {
10632 pub const offset: u32 = 0;
10633 pub const mask: u32 = 0x0003_ffff << offset;
10634 pub mod R {}
10635 pub mod W {}
10636 pub mod RW {}
10637 }
10638 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
10639 pub mod STD {
10640 pub const offset: u32 = 18;
10641 pub const mask: u32 = 0x07ff << offset;
10642 pub mod R {}
10643 pub mod W {}
10644 pub mod RW {}
10645 }
10646 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
10647 pub mod PRIO {
10648 pub const offset: u32 = 29;
10649 pub const mask: u32 = 0x07 << offset;
10650 pub mod R {}
10651 pub mod W {}
10652 pub mod RW {}
10653 }
10654}
10655#[doc = "Message Buffer 11 CS Register"]
10656pub mod MB11_64B_CS {
10657 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
10658 pub mod TIME_STAMP {
10659 pub const offset: u32 = 0;
10660 pub const mask: u32 = 0xffff << offset;
10661 pub mod R {}
10662 pub mod W {}
10663 pub mod RW {}
10664 }
10665 #[doc = "Length of the data to be stored/transmitted."]
10666 pub mod DLC {
10667 pub const offset: u32 = 16;
10668 pub const mask: u32 = 0x0f << offset;
10669 pub mod R {}
10670 pub mod W {}
10671 pub mod RW {}
10672 }
10673 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
10674 pub mod RTR {
10675 pub const offset: u32 = 20;
10676 pub const mask: u32 = 0x01 << offset;
10677 pub mod R {}
10678 pub mod W {}
10679 pub mod RW {}
10680 }
10681 #[doc = "ID Extended. One/zero for extended/standard format frame."]
10682 pub mod IDE {
10683 pub const offset: u32 = 21;
10684 pub const mask: u32 = 0x01 << offset;
10685 pub mod R {}
10686 pub mod W {}
10687 pub mod RW {}
10688 }
10689 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
10690 pub mod SRR {
10691 pub const offset: u32 = 22;
10692 pub const mask: u32 = 0x01 << offset;
10693 pub mod R {}
10694 pub mod W {}
10695 pub mod RW {}
10696 }
10697 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
10698 pub mod CODE {
10699 pub const offset: u32 = 24;
10700 pub const mask: u32 = 0x0f << offset;
10701 pub mod R {}
10702 pub mod W {}
10703 pub mod RW {}
10704 }
10705 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
10706 pub mod ESI {
10707 pub const offset: u32 = 29;
10708 pub const mask: u32 = 0x01 << offset;
10709 pub mod R {}
10710 pub mod W {}
10711 pub mod RW {}
10712 }
10713 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
10714 pub mod BRS {
10715 pub const offset: u32 = 30;
10716 pub const mask: u32 = 0x01 << offset;
10717 pub mod R {}
10718 pub mod W {}
10719 pub mod RW {}
10720 }
10721 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
10722 pub mod EDL {
10723 pub const offset: u32 = 31;
10724 pub const mask: u32 = 0x01 << offset;
10725 pub mod R {}
10726 pub mod W {}
10727 pub mod RW {}
10728 }
10729}
10730#[doc = "Message Buffer 11 ID Register"]
10731pub mod MB11_64B_ID {
10732 #[doc = "Contains extended (LOW word) identifier of message buffer."]
10733 pub mod EXT {
10734 pub const offset: u32 = 0;
10735 pub const mask: u32 = 0x0003_ffff << offset;
10736 pub mod R {}
10737 pub mod W {}
10738 pub mod RW {}
10739 }
10740 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
10741 pub mod STD {
10742 pub const offset: u32 = 18;
10743 pub const mask: u32 = 0x07ff << offset;
10744 pub mod R {}
10745 pub mod W {}
10746 pub mod RW {}
10747 }
10748 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
10749 pub mod PRIO {
10750 pub const offset: u32 = 29;
10751 pub const mask: u32 = 0x07 << offset;
10752 pub mod R {}
10753 pub mod W {}
10754 pub mod RW {}
10755 }
10756}
10757#[doc = "Message Buffer 50 CS Register"]
10758pub mod CS50 {
10759 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
10760 pub mod TIME_STAMP {
10761 pub const offset: u32 = 0;
10762 pub const mask: u32 = 0xffff << offset;
10763 pub mod R {}
10764 pub mod W {}
10765 pub mod RW {}
10766 }
10767 #[doc = "Length of the data to be stored/transmitted."]
10768 pub mod DLC {
10769 pub const offset: u32 = 16;
10770 pub const mask: u32 = 0x0f << offset;
10771 pub mod R {}
10772 pub mod W {}
10773 pub mod RW {}
10774 }
10775 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
10776 pub mod RTR {
10777 pub const offset: u32 = 20;
10778 pub const mask: u32 = 0x01 << offset;
10779 pub mod R {}
10780 pub mod W {}
10781 pub mod RW {}
10782 }
10783 #[doc = "ID Extended. One/zero for extended/standard format frame."]
10784 pub mod IDE {
10785 pub const offset: u32 = 21;
10786 pub const mask: u32 = 0x01 << offset;
10787 pub mod R {}
10788 pub mod W {}
10789 pub mod RW {}
10790 }
10791 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
10792 pub mod SRR {
10793 pub const offset: u32 = 22;
10794 pub const mask: u32 = 0x01 << offset;
10795 pub mod R {}
10796 pub mod W {}
10797 pub mod RW {}
10798 }
10799 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
10800 pub mod CODE {
10801 pub const offset: u32 = 24;
10802 pub const mask: u32 = 0x0f << offset;
10803 pub mod R {}
10804 pub mod W {}
10805 pub mod RW {}
10806 }
10807 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
10808 pub mod ESI {
10809 pub const offset: u32 = 29;
10810 pub const mask: u32 = 0x01 << offset;
10811 pub mod R {}
10812 pub mod W {}
10813 pub mod RW {}
10814 }
10815 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
10816 pub mod BRS {
10817 pub const offset: u32 = 30;
10818 pub const mask: u32 = 0x01 << offset;
10819 pub mod R {}
10820 pub mod W {}
10821 pub mod RW {}
10822 }
10823 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
10824 pub mod EDL {
10825 pub const offset: u32 = 31;
10826 pub const mask: u32 = 0x01 << offset;
10827 pub mod R {}
10828 pub mod W {}
10829 pub mod RW {}
10830 }
10831}
10832#[doc = "Message Buffer 50 ID Register"]
10833pub mod ID50 {
10834 #[doc = "Contains extended (LOW word) identifier of message buffer."]
10835 pub mod EXT {
10836 pub const offset: u32 = 0;
10837 pub const mask: u32 = 0x0003_ffff << offset;
10838 pub mod R {}
10839 pub mod W {}
10840 pub mod RW {}
10841 }
10842 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
10843 pub mod STD {
10844 pub const offset: u32 = 18;
10845 pub const mask: u32 = 0x07ff << offset;
10846 pub mod R {}
10847 pub mod W {}
10848 pub mod RW {}
10849 }
10850 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
10851 pub mod PRIO {
10852 pub const offset: u32 = 29;
10853 pub const mask: u32 = 0x07 << offset;
10854 pub mod R {}
10855 pub mod W {}
10856 pub mod RW {}
10857 }
10858}
10859#[doc = "Message Buffer 11 WORD_64B Register"]
10860pub mod MB11_64B_WORD2 {
10861 #[doc = "Data byte 0 of Rx/Tx frame."]
10862 pub mod DATA_BYTE_11 {
10863 pub const offset: u32 = 0;
10864 pub const mask: u32 = 0xff << offset;
10865 pub mod R {}
10866 pub mod W {}
10867 pub mod RW {}
10868 }
10869 #[doc = "Data byte 1 of Rx/Tx frame."]
10870 pub mod DATA_BYTE_10 {
10871 pub const offset: u32 = 8;
10872 pub const mask: u32 = 0xff << offset;
10873 pub mod R {}
10874 pub mod W {}
10875 pub mod RW {}
10876 }
10877 #[doc = "Data byte 2 of Rx/Tx frame."]
10878 pub mod DATA_BYTE_9 {
10879 pub const offset: u32 = 16;
10880 pub const mask: u32 = 0xff << offset;
10881 pub mod R {}
10882 pub mod W {}
10883 pub mod RW {}
10884 }
10885 #[doc = "Data byte 3 of Rx/Tx frame."]
10886 pub mod DATA_BYTE_8 {
10887 pub const offset: u32 = 24;
10888 pub const mask: u32 = 0xff << offset;
10889 pub mod R {}
10890 pub mod W {}
10891 pub mod RW {}
10892 }
10893}
10894#[doc = "Message Buffer 11 WORD_64B Register"]
10895pub mod MB11_64B_WORD3 {
10896 #[doc = "Data byte 0 of Rx/Tx frame."]
10897 pub mod DATA_BYTE_15 {
10898 pub const offset: u32 = 0;
10899 pub const mask: u32 = 0xff << offset;
10900 pub mod R {}
10901 pub mod W {}
10902 pub mod RW {}
10903 }
10904 #[doc = "Data byte 1 of Rx/Tx frame."]
10905 pub mod DATA_BYTE_14 {
10906 pub const offset: u32 = 8;
10907 pub const mask: u32 = 0xff << offset;
10908 pub mod R {}
10909 pub mod W {}
10910 pub mod RW {}
10911 }
10912 #[doc = "Data byte 2 of Rx/Tx frame."]
10913 pub mod DATA_BYTE_13 {
10914 pub const offset: u32 = 16;
10915 pub const mask: u32 = 0xff << offset;
10916 pub mod R {}
10917 pub mod W {}
10918 pub mod RW {}
10919 }
10920 #[doc = "Data byte 3 of Rx/Tx frame."]
10921 pub mod DATA_BYTE_12 {
10922 pub const offset: u32 = 24;
10923 pub const mask: u32 = 0xff << offset;
10924 pub mod R {}
10925 pub mod W {}
10926 pub mod RW {}
10927 }
10928}
10929#[doc = "Message Buffer 51 CS Register"]
10930pub mod CS51 {
10931 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
10932 pub mod TIME_STAMP {
10933 pub const offset: u32 = 0;
10934 pub const mask: u32 = 0xffff << offset;
10935 pub mod R {}
10936 pub mod W {}
10937 pub mod RW {}
10938 }
10939 #[doc = "Length of the data to be stored/transmitted."]
10940 pub mod DLC {
10941 pub const offset: u32 = 16;
10942 pub const mask: u32 = 0x0f << offset;
10943 pub mod R {}
10944 pub mod W {}
10945 pub mod RW {}
10946 }
10947 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
10948 pub mod RTR {
10949 pub const offset: u32 = 20;
10950 pub const mask: u32 = 0x01 << offset;
10951 pub mod R {}
10952 pub mod W {}
10953 pub mod RW {}
10954 }
10955 #[doc = "ID Extended. One/zero for extended/standard format frame."]
10956 pub mod IDE {
10957 pub const offset: u32 = 21;
10958 pub const mask: u32 = 0x01 << offset;
10959 pub mod R {}
10960 pub mod W {}
10961 pub mod RW {}
10962 }
10963 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
10964 pub mod SRR {
10965 pub const offset: u32 = 22;
10966 pub const mask: u32 = 0x01 << offset;
10967 pub mod R {}
10968 pub mod W {}
10969 pub mod RW {}
10970 }
10971 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
10972 pub mod CODE {
10973 pub const offset: u32 = 24;
10974 pub const mask: u32 = 0x0f << offset;
10975 pub mod R {}
10976 pub mod W {}
10977 pub mod RW {}
10978 }
10979 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
10980 pub mod ESI {
10981 pub const offset: u32 = 29;
10982 pub const mask: u32 = 0x01 << offset;
10983 pub mod R {}
10984 pub mod W {}
10985 pub mod RW {}
10986 }
10987 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
10988 pub mod BRS {
10989 pub const offset: u32 = 30;
10990 pub const mask: u32 = 0x01 << offset;
10991 pub mod R {}
10992 pub mod W {}
10993 pub mod RW {}
10994 }
10995 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
10996 pub mod EDL {
10997 pub const offset: u32 = 31;
10998 pub const mask: u32 = 0x01 << offset;
10999 pub mod R {}
11000 pub mod W {}
11001 pub mod RW {}
11002 }
11003}
11004#[doc = "Message Buffer 51 ID Register"]
11005pub mod ID51 {
11006 #[doc = "Contains extended (LOW word) identifier of message buffer."]
11007 pub mod EXT {
11008 pub const offset: u32 = 0;
11009 pub const mask: u32 = 0x0003_ffff << offset;
11010 pub mod R {}
11011 pub mod W {}
11012 pub mod RW {}
11013 }
11014 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
11015 pub mod STD {
11016 pub const offset: u32 = 18;
11017 pub const mask: u32 = 0x07ff << offset;
11018 pub mod R {}
11019 pub mod W {}
11020 pub mod RW {}
11021 }
11022 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
11023 pub mod PRIO {
11024 pub const offset: u32 = 29;
11025 pub const mask: u32 = 0x07 << offset;
11026 pub mod R {}
11027 pub mod W {}
11028 pub mod RW {}
11029 }
11030}
11031#[doc = "Message Buffer 11 WORD_64B Register"]
11032pub mod MB11_64B_WORD6 {
11033 #[doc = "Data byte 0 of Rx/Tx frame."]
11034 pub mod DATA_BYTE_27 {
11035 pub const offset: u32 = 0;
11036 pub const mask: u32 = 0xff << offset;
11037 pub mod R {}
11038 pub mod W {}
11039 pub mod RW {}
11040 }
11041 #[doc = "Data byte 1 of Rx/Tx frame."]
11042 pub mod DATA_BYTE_26 {
11043 pub const offset: u32 = 8;
11044 pub const mask: u32 = 0xff << offset;
11045 pub mod R {}
11046 pub mod W {}
11047 pub mod RW {}
11048 }
11049 #[doc = "Data byte 2 of Rx/Tx frame."]
11050 pub mod DATA_BYTE_25 {
11051 pub const offset: u32 = 16;
11052 pub const mask: u32 = 0xff << offset;
11053 pub mod R {}
11054 pub mod W {}
11055 pub mod RW {}
11056 }
11057 #[doc = "Data byte 3 of Rx/Tx frame."]
11058 pub mod DATA_BYTE_24 {
11059 pub const offset: u32 = 24;
11060 pub const mask: u32 = 0xff << offset;
11061 pub mod R {}
11062 pub mod W {}
11063 pub mod RW {}
11064 }
11065}
11066#[doc = "Message Buffer 11 WORD_64B Register"]
11067pub mod MB11_64B_WORD7 {
11068 #[doc = "Data byte 0 of Rx/Tx frame."]
11069 pub mod DATA_BYTE_31 {
11070 pub const offset: u32 = 0;
11071 pub const mask: u32 = 0xff << offset;
11072 pub mod R {}
11073 pub mod W {}
11074 pub mod RW {}
11075 }
11076 #[doc = "Data byte 1 of Rx/Tx frame."]
11077 pub mod DATA_BYTE_30 {
11078 pub const offset: u32 = 8;
11079 pub const mask: u32 = 0xff << offset;
11080 pub mod R {}
11081 pub mod W {}
11082 pub mod RW {}
11083 }
11084 #[doc = "Data byte 2 of Rx/Tx frame."]
11085 pub mod DATA_BYTE_29 {
11086 pub const offset: u32 = 16;
11087 pub const mask: u32 = 0xff << offset;
11088 pub mod R {}
11089 pub mod W {}
11090 pub mod RW {}
11091 }
11092 #[doc = "Data byte 3 of Rx/Tx frame."]
11093 pub mod DATA_BYTE_28 {
11094 pub const offset: u32 = 24;
11095 pub const mask: u32 = 0xff << offset;
11096 pub mod R {}
11097 pub mod W {}
11098 pub mod RW {}
11099 }
11100}
11101#[doc = "Message Buffer 52 CS Register"]
11102pub mod CS52 {
11103 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
11104 pub mod TIME_STAMP {
11105 pub const offset: u32 = 0;
11106 pub const mask: u32 = 0xffff << offset;
11107 pub mod R {}
11108 pub mod W {}
11109 pub mod RW {}
11110 }
11111 #[doc = "Length of the data to be stored/transmitted."]
11112 pub mod DLC {
11113 pub const offset: u32 = 16;
11114 pub const mask: u32 = 0x0f << offset;
11115 pub mod R {}
11116 pub mod W {}
11117 pub mod RW {}
11118 }
11119 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
11120 pub mod RTR {
11121 pub const offset: u32 = 20;
11122 pub const mask: u32 = 0x01 << offset;
11123 pub mod R {}
11124 pub mod W {}
11125 pub mod RW {}
11126 }
11127 #[doc = "ID Extended. One/zero for extended/standard format frame."]
11128 pub mod IDE {
11129 pub const offset: u32 = 21;
11130 pub const mask: u32 = 0x01 << offset;
11131 pub mod R {}
11132 pub mod W {}
11133 pub mod RW {}
11134 }
11135 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
11136 pub mod SRR {
11137 pub const offset: u32 = 22;
11138 pub const mask: u32 = 0x01 << offset;
11139 pub mod R {}
11140 pub mod W {}
11141 pub mod RW {}
11142 }
11143 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
11144 pub mod CODE {
11145 pub const offset: u32 = 24;
11146 pub const mask: u32 = 0x0f << offset;
11147 pub mod R {}
11148 pub mod W {}
11149 pub mod RW {}
11150 }
11151 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
11152 pub mod ESI {
11153 pub const offset: u32 = 29;
11154 pub const mask: u32 = 0x01 << offset;
11155 pub mod R {}
11156 pub mod W {}
11157 pub mod RW {}
11158 }
11159 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
11160 pub mod BRS {
11161 pub const offset: u32 = 30;
11162 pub const mask: u32 = 0x01 << offset;
11163 pub mod R {}
11164 pub mod W {}
11165 pub mod RW {}
11166 }
11167 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
11168 pub mod EDL {
11169 pub const offset: u32 = 31;
11170 pub const mask: u32 = 0x01 << offset;
11171 pub mod R {}
11172 pub mod W {}
11173 pub mod RW {}
11174 }
11175}
11176#[doc = "Message Buffer 52 ID Register"]
11177pub mod ID52 {
11178 #[doc = "Contains extended (LOW word) identifier of message buffer."]
11179 pub mod EXT {
11180 pub const offset: u32 = 0;
11181 pub const mask: u32 = 0x0003_ffff << offset;
11182 pub mod R {}
11183 pub mod W {}
11184 pub mod RW {}
11185 }
11186 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
11187 pub mod STD {
11188 pub const offset: u32 = 18;
11189 pub const mask: u32 = 0x07ff << offset;
11190 pub mod R {}
11191 pub mod W {}
11192 pub mod RW {}
11193 }
11194 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
11195 pub mod PRIO {
11196 pub const offset: u32 = 29;
11197 pub const mask: u32 = 0x07 << offset;
11198 pub mod R {}
11199 pub mod W {}
11200 pub mod RW {}
11201 }
11202}
11203#[doc = "Message Buffer 11 WORD_64B Register"]
11204pub mod MB11_64B_WORD10 {
11205 #[doc = "Data byte 0 of Rx/Tx frame."]
11206 pub mod DATA_BYTE_43 {
11207 pub const offset: u32 = 0;
11208 pub const mask: u32 = 0xff << offset;
11209 pub mod R {}
11210 pub mod W {}
11211 pub mod RW {}
11212 }
11213 #[doc = "Data byte 1 of Rx/Tx frame."]
11214 pub mod DATA_BYTE_42 {
11215 pub const offset: u32 = 8;
11216 pub const mask: u32 = 0xff << offset;
11217 pub mod R {}
11218 pub mod W {}
11219 pub mod RW {}
11220 }
11221 #[doc = "Data byte 2 of Rx/Tx frame."]
11222 pub mod DATA_BYTE_41 {
11223 pub const offset: u32 = 16;
11224 pub const mask: u32 = 0xff << offset;
11225 pub mod R {}
11226 pub mod W {}
11227 pub mod RW {}
11228 }
11229 #[doc = "Data byte 3 of Rx/Tx frame."]
11230 pub mod DATA_BYTE_40 {
11231 pub const offset: u32 = 24;
11232 pub const mask: u32 = 0xff << offset;
11233 pub mod R {}
11234 pub mod W {}
11235 pub mod RW {}
11236 }
11237}
11238#[doc = "Message Buffer 11 WORD_64B Register"]
11239pub mod MB11_64B_WORD11 {
11240 #[doc = "Data byte 0 of Rx/Tx frame."]
11241 pub mod DATA_BYTE_47 {
11242 pub const offset: u32 = 0;
11243 pub const mask: u32 = 0xff << offset;
11244 pub mod R {}
11245 pub mod W {}
11246 pub mod RW {}
11247 }
11248 #[doc = "Data byte 1 of Rx/Tx frame."]
11249 pub mod DATA_BYTE_46 {
11250 pub const offset: u32 = 8;
11251 pub const mask: u32 = 0xff << offset;
11252 pub mod R {}
11253 pub mod W {}
11254 pub mod RW {}
11255 }
11256 #[doc = "Data byte 2 of Rx/Tx frame."]
11257 pub mod DATA_BYTE_45 {
11258 pub const offset: u32 = 16;
11259 pub const mask: u32 = 0xff << offset;
11260 pub mod R {}
11261 pub mod W {}
11262 pub mod RW {}
11263 }
11264 #[doc = "Data byte 3 of Rx/Tx frame."]
11265 pub mod DATA_BYTE_44 {
11266 pub const offset: u32 = 24;
11267 pub const mask: u32 = 0xff << offset;
11268 pub mod R {}
11269 pub mod W {}
11270 pub mod RW {}
11271 }
11272}
11273#[doc = "Message Buffer 53 CS Register"]
11274pub mod CS53 {
11275 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
11276 pub mod TIME_STAMP {
11277 pub const offset: u32 = 0;
11278 pub const mask: u32 = 0xffff << offset;
11279 pub mod R {}
11280 pub mod W {}
11281 pub mod RW {}
11282 }
11283 #[doc = "Length of the data to be stored/transmitted."]
11284 pub mod DLC {
11285 pub const offset: u32 = 16;
11286 pub const mask: u32 = 0x0f << offset;
11287 pub mod R {}
11288 pub mod W {}
11289 pub mod RW {}
11290 }
11291 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
11292 pub mod RTR {
11293 pub const offset: u32 = 20;
11294 pub const mask: u32 = 0x01 << offset;
11295 pub mod R {}
11296 pub mod W {}
11297 pub mod RW {}
11298 }
11299 #[doc = "ID Extended. One/zero for extended/standard format frame."]
11300 pub mod IDE {
11301 pub const offset: u32 = 21;
11302 pub const mask: u32 = 0x01 << offset;
11303 pub mod R {}
11304 pub mod W {}
11305 pub mod RW {}
11306 }
11307 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
11308 pub mod SRR {
11309 pub const offset: u32 = 22;
11310 pub const mask: u32 = 0x01 << offset;
11311 pub mod R {}
11312 pub mod W {}
11313 pub mod RW {}
11314 }
11315 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
11316 pub mod CODE {
11317 pub const offset: u32 = 24;
11318 pub const mask: u32 = 0x0f << offset;
11319 pub mod R {}
11320 pub mod W {}
11321 pub mod RW {}
11322 }
11323 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
11324 pub mod ESI {
11325 pub const offset: u32 = 29;
11326 pub const mask: u32 = 0x01 << offset;
11327 pub mod R {}
11328 pub mod W {}
11329 pub mod RW {}
11330 }
11331 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
11332 pub mod BRS {
11333 pub const offset: u32 = 30;
11334 pub const mask: u32 = 0x01 << offset;
11335 pub mod R {}
11336 pub mod W {}
11337 pub mod RW {}
11338 }
11339 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
11340 pub mod EDL {
11341 pub const offset: u32 = 31;
11342 pub const mask: u32 = 0x01 << offset;
11343 pub mod R {}
11344 pub mod W {}
11345 pub mod RW {}
11346 }
11347}
11348#[doc = "Message Buffer 53 ID Register"]
11349pub mod ID53 {
11350 #[doc = "Contains extended (LOW word) identifier of message buffer."]
11351 pub mod EXT {
11352 pub const offset: u32 = 0;
11353 pub const mask: u32 = 0x0003_ffff << offset;
11354 pub mod R {}
11355 pub mod W {}
11356 pub mod RW {}
11357 }
11358 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
11359 pub mod STD {
11360 pub const offset: u32 = 18;
11361 pub const mask: u32 = 0x07ff << offset;
11362 pub mod R {}
11363 pub mod W {}
11364 pub mod RW {}
11365 }
11366 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
11367 pub mod PRIO {
11368 pub const offset: u32 = 29;
11369 pub const mask: u32 = 0x07 << offset;
11370 pub mod R {}
11371 pub mod W {}
11372 pub mod RW {}
11373 }
11374}
11375#[doc = "Message Buffer 11 WORD_64B Register"]
11376pub mod MB11_64B_WORD14 {
11377 #[doc = "Data byte 0 of Rx/Tx frame."]
11378 pub mod DATA_BYTE_59 {
11379 pub const offset: u32 = 0;
11380 pub const mask: u32 = 0xff << offset;
11381 pub mod R {}
11382 pub mod W {}
11383 pub mod RW {}
11384 }
11385 #[doc = "Data byte 1 of Rx/Tx frame."]
11386 pub mod DATA_BYTE_58 {
11387 pub const offset: u32 = 8;
11388 pub const mask: u32 = 0xff << offset;
11389 pub mod R {}
11390 pub mod W {}
11391 pub mod RW {}
11392 }
11393 #[doc = "Data byte 2 of Rx/Tx frame."]
11394 pub mod DATA_BYTE_57 {
11395 pub const offset: u32 = 16;
11396 pub const mask: u32 = 0xff << offset;
11397 pub mod R {}
11398 pub mod W {}
11399 pub mod RW {}
11400 }
11401 #[doc = "Data byte 3 of Rx/Tx frame."]
11402 pub mod DATA_BYTE_56 {
11403 pub const offset: u32 = 24;
11404 pub const mask: u32 = 0xff << offset;
11405 pub mod R {}
11406 pub mod W {}
11407 pub mod RW {}
11408 }
11409}
11410#[doc = "Message Buffer 11 WORD_64B Register"]
11411pub mod MB11_64B_WORD15 {
11412 #[doc = "Data byte 0 of Rx/Tx frame."]
11413 pub mod DATA_BYTE_63 {
11414 pub const offset: u32 = 0;
11415 pub const mask: u32 = 0xff << offset;
11416 pub mod R {}
11417 pub mod W {}
11418 pub mod RW {}
11419 }
11420 #[doc = "Data byte 1 of Rx/Tx frame."]
11421 pub mod DATA_BYTE_62 {
11422 pub const offset: u32 = 8;
11423 pub const mask: u32 = 0xff << offset;
11424 pub mod R {}
11425 pub mod W {}
11426 pub mod RW {}
11427 }
11428 #[doc = "Data byte 2 of Rx/Tx frame."]
11429 pub mod DATA_BYTE_61 {
11430 pub const offset: u32 = 16;
11431 pub const mask: u32 = 0xff << offset;
11432 pub mod R {}
11433 pub mod W {}
11434 pub mod RW {}
11435 }
11436 #[doc = "Data byte 3 of Rx/Tx frame."]
11437 pub mod DATA_BYTE_60 {
11438 pub const offset: u32 = 24;
11439 pub const mask: u32 = 0xff << offset;
11440 pub mod R {}
11441 pub mod W {}
11442 pub mod RW {}
11443 }
11444}
11445#[doc = "Message Buffer 54 CS Register"]
11446pub mod CS54 {
11447 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
11448 pub mod TIME_STAMP {
11449 pub const offset: u32 = 0;
11450 pub const mask: u32 = 0xffff << offset;
11451 pub mod R {}
11452 pub mod W {}
11453 pub mod RW {}
11454 }
11455 #[doc = "Length of the data to be stored/transmitted."]
11456 pub mod DLC {
11457 pub const offset: u32 = 16;
11458 pub const mask: u32 = 0x0f << offset;
11459 pub mod R {}
11460 pub mod W {}
11461 pub mod RW {}
11462 }
11463 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
11464 pub mod RTR {
11465 pub const offset: u32 = 20;
11466 pub const mask: u32 = 0x01 << offset;
11467 pub mod R {}
11468 pub mod W {}
11469 pub mod RW {}
11470 }
11471 #[doc = "ID Extended. One/zero for extended/standard format frame."]
11472 pub mod IDE {
11473 pub const offset: u32 = 21;
11474 pub const mask: u32 = 0x01 << offset;
11475 pub mod R {}
11476 pub mod W {}
11477 pub mod RW {}
11478 }
11479 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
11480 pub mod SRR {
11481 pub const offset: u32 = 22;
11482 pub const mask: u32 = 0x01 << offset;
11483 pub mod R {}
11484 pub mod W {}
11485 pub mod RW {}
11486 }
11487 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
11488 pub mod CODE {
11489 pub const offset: u32 = 24;
11490 pub const mask: u32 = 0x0f << offset;
11491 pub mod R {}
11492 pub mod W {}
11493 pub mod RW {}
11494 }
11495 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
11496 pub mod ESI {
11497 pub const offset: u32 = 29;
11498 pub const mask: u32 = 0x01 << offset;
11499 pub mod R {}
11500 pub mod W {}
11501 pub mod RW {}
11502 }
11503 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
11504 pub mod BRS {
11505 pub const offset: u32 = 30;
11506 pub const mask: u32 = 0x01 << offset;
11507 pub mod R {}
11508 pub mod W {}
11509 pub mod RW {}
11510 }
11511 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
11512 pub mod EDL {
11513 pub const offset: u32 = 31;
11514 pub const mask: u32 = 0x01 << offset;
11515 pub mod R {}
11516 pub mod W {}
11517 pub mod RW {}
11518 }
11519}
11520#[doc = "Message Buffer 54 ID Register"]
11521pub mod ID54 {
11522 #[doc = "Contains extended (LOW word) identifier of message buffer."]
11523 pub mod EXT {
11524 pub const offset: u32 = 0;
11525 pub const mask: u32 = 0x0003_ffff << offset;
11526 pub mod R {}
11527 pub mod W {}
11528 pub mod RW {}
11529 }
11530 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
11531 pub mod STD {
11532 pub const offset: u32 = 18;
11533 pub const mask: u32 = 0x07ff << offset;
11534 pub mod R {}
11535 pub mod W {}
11536 pub mod RW {}
11537 }
11538 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
11539 pub mod PRIO {
11540 pub const offset: u32 = 29;
11541 pub const mask: u32 = 0x07 << offset;
11542 pub mod R {}
11543 pub mod W {}
11544 pub mod RW {}
11545 }
11546}
11547#[doc = "Message Buffer 12 WORD_64B Register"]
11548pub mod MB12_64B_WORD0 {
11549 #[doc = "Data byte 0 of Rx/Tx frame."]
11550 pub mod DATA_BYTE_3 {
11551 pub const offset: u32 = 0;
11552 pub const mask: u32 = 0xff << offset;
11553 pub mod R {}
11554 pub mod W {}
11555 pub mod RW {}
11556 }
11557 #[doc = "Data byte 1 of Rx/Tx frame."]
11558 pub mod DATA_BYTE_2 {
11559 pub const offset: u32 = 8;
11560 pub const mask: u32 = 0xff << offset;
11561 pub mod R {}
11562 pub mod W {}
11563 pub mod RW {}
11564 }
11565 #[doc = "Data byte 2 of Rx/Tx frame."]
11566 pub mod DATA_BYTE_1 {
11567 pub const offset: u32 = 16;
11568 pub const mask: u32 = 0xff << offset;
11569 pub mod R {}
11570 pub mod W {}
11571 pub mod RW {}
11572 }
11573 #[doc = "Data byte 3 of Rx/Tx frame."]
11574 pub mod DATA_BYTE_0 {
11575 pub const offset: u32 = 24;
11576 pub const mask: u32 = 0xff << offset;
11577 pub mod R {}
11578 pub mod W {}
11579 pub mod RW {}
11580 }
11581}
11582#[doc = "Message Buffer 12 WORD_64B Register"]
11583pub mod MB12_64B_WORD1 {
11584 #[doc = "Data byte 0 of Rx/Tx frame."]
11585 pub mod DATA_BYTE_7 {
11586 pub const offset: u32 = 0;
11587 pub const mask: u32 = 0xff << offset;
11588 pub mod R {}
11589 pub mod W {}
11590 pub mod RW {}
11591 }
11592 #[doc = "Data byte 1 of Rx/Tx frame."]
11593 pub mod DATA_BYTE_6 {
11594 pub const offset: u32 = 8;
11595 pub const mask: u32 = 0xff << offset;
11596 pub mod R {}
11597 pub mod W {}
11598 pub mod RW {}
11599 }
11600 #[doc = "Data byte 2 of Rx/Tx frame."]
11601 pub mod DATA_BYTE_5 {
11602 pub const offset: u32 = 16;
11603 pub const mask: u32 = 0xff << offset;
11604 pub mod R {}
11605 pub mod W {}
11606 pub mod RW {}
11607 }
11608 #[doc = "Data byte 3 of Rx/Tx frame."]
11609 pub mod DATA_BYTE_4 {
11610 pub const offset: u32 = 24;
11611 pub const mask: u32 = 0xff << offset;
11612 pub mod R {}
11613 pub mod W {}
11614 pub mod RW {}
11615 }
11616}
11617#[doc = "Message Buffer 55 CS Register"]
11618pub mod CS55 {
11619 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
11620 pub mod TIME_STAMP {
11621 pub const offset: u32 = 0;
11622 pub const mask: u32 = 0xffff << offset;
11623 pub mod R {}
11624 pub mod W {}
11625 pub mod RW {}
11626 }
11627 #[doc = "Length of the data to be stored/transmitted."]
11628 pub mod DLC {
11629 pub const offset: u32 = 16;
11630 pub const mask: u32 = 0x0f << offset;
11631 pub mod R {}
11632 pub mod W {}
11633 pub mod RW {}
11634 }
11635 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
11636 pub mod RTR {
11637 pub const offset: u32 = 20;
11638 pub const mask: u32 = 0x01 << offset;
11639 pub mod R {}
11640 pub mod W {}
11641 pub mod RW {}
11642 }
11643 #[doc = "ID Extended. One/zero for extended/standard format frame."]
11644 pub mod IDE {
11645 pub const offset: u32 = 21;
11646 pub const mask: u32 = 0x01 << offset;
11647 pub mod R {}
11648 pub mod W {}
11649 pub mod RW {}
11650 }
11651 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
11652 pub mod SRR {
11653 pub const offset: u32 = 22;
11654 pub const mask: u32 = 0x01 << offset;
11655 pub mod R {}
11656 pub mod W {}
11657 pub mod RW {}
11658 }
11659 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
11660 pub mod CODE {
11661 pub const offset: u32 = 24;
11662 pub const mask: u32 = 0x0f << offset;
11663 pub mod R {}
11664 pub mod W {}
11665 pub mod RW {}
11666 }
11667 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
11668 pub mod ESI {
11669 pub const offset: u32 = 29;
11670 pub const mask: u32 = 0x01 << offset;
11671 pub mod R {}
11672 pub mod W {}
11673 pub mod RW {}
11674 }
11675 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
11676 pub mod BRS {
11677 pub const offset: u32 = 30;
11678 pub const mask: u32 = 0x01 << offset;
11679 pub mod R {}
11680 pub mod W {}
11681 pub mod RW {}
11682 }
11683 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
11684 pub mod EDL {
11685 pub const offset: u32 = 31;
11686 pub const mask: u32 = 0x01 << offset;
11687 pub mod R {}
11688 pub mod W {}
11689 pub mod RW {}
11690 }
11691}
11692#[doc = "Message Buffer 55 ID Register"]
11693pub mod ID55 {
11694 #[doc = "Contains extended (LOW word) identifier of message buffer."]
11695 pub mod EXT {
11696 pub const offset: u32 = 0;
11697 pub const mask: u32 = 0x0003_ffff << offset;
11698 pub mod R {}
11699 pub mod W {}
11700 pub mod RW {}
11701 }
11702 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
11703 pub mod STD {
11704 pub const offset: u32 = 18;
11705 pub const mask: u32 = 0x07ff << offset;
11706 pub mod R {}
11707 pub mod W {}
11708 pub mod RW {}
11709 }
11710 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
11711 pub mod PRIO {
11712 pub const offset: u32 = 29;
11713 pub const mask: u32 = 0x07 << offset;
11714 pub mod R {}
11715 pub mod W {}
11716 pub mod RW {}
11717 }
11718}
11719#[doc = "Message Buffer 12 WORD_64B Register"]
11720pub mod MB12_64B_WORD4 {
11721 #[doc = "Data byte 0 of Rx/Tx frame."]
11722 pub mod DATA_BYTE_19 {
11723 pub const offset: u32 = 0;
11724 pub const mask: u32 = 0xff << offset;
11725 pub mod R {}
11726 pub mod W {}
11727 pub mod RW {}
11728 }
11729 #[doc = "Data byte 1 of Rx/Tx frame."]
11730 pub mod DATA_BYTE_18 {
11731 pub const offset: u32 = 8;
11732 pub const mask: u32 = 0xff << offset;
11733 pub mod R {}
11734 pub mod W {}
11735 pub mod RW {}
11736 }
11737 #[doc = "Data byte 2 of Rx/Tx frame."]
11738 pub mod DATA_BYTE_17 {
11739 pub const offset: u32 = 16;
11740 pub const mask: u32 = 0xff << offset;
11741 pub mod R {}
11742 pub mod W {}
11743 pub mod RW {}
11744 }
11745 #[doc = "Data byte 3 of Rx/Tx frame."]
11746 pub mod DATA_BYTE_16 {
11747 pub const offset: u32 = 24;
11748 pub const mask: u32 = 0xff << offset;
11749 pub mod R {}
11750 pub mod W {}
11751 pub mod RW {}
11752 }
11753}
11754#[doc = "Message Buffer 12 WORD_64B Register"]
11755pub mod MB12_64B_WORD5 {
11756 #[doc = "Data byte 0 of Rx/Tx frame."]
11757 pub mod DATA_BYTE_23 {
11758 pub const offset: u32 = 0;
11759 pub const mask: u32 = 0xff << offset;
11760 pub mod R {}
11761 pub mod W {}
11762 pub mod RW {}
11763 }
11764 #[doc = "Data byte 1 of Rx/Tx frame."]
11765 pub mod DATA_BYTE_22 {
11766 pub const offset: u32 = 8;
11767 pub const mask: u32 = 0xff << offset;
11768 pub mod R {}
11769 pub mod W {}
11770 pub mod RW {}
11771 }
11772 #[doc = "Data byte 2 of Rx/Tx frame."]
11773 pub mod DATA_BYTE_21 {
11774 pub const offset: u32 = 16;
11775 pub const mask: u32 = 0xff << offset;
11776 pub mod R {}
11777 pub mod W {}
11778 pub mod RW {}
11779 }
11780 #[doc = "Data byte 3 of Rx/Tx frame."]
11781 pub mod DATA_BYTE_20 {
11782 pub const offset: u32 = 24;
11783 pub const mask: u32 = 0xff << offset;
11784 pub mod R {}
11785 pub mod W {}
11786 pub mod RW {}
11787 }
11788}
11789#[doc = "Message Buffer 56 CS Register"]
11790pub mod CS56 {
11791 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
11792 pub mod TIME_STAMP {
11793 pub const offset: u32 = 0;
11794 pub const mask: u32 = 0xffff << offset;
11795 pub mod R {}
11796 pub mod W {}
11797 pub mod RW {}
11798 }
11799 #[doc = "Length of the data to be stored/transmitted."]
11800 pub mod DLC {
11801 pub const offset: u32 = 16;
11802 pub const mask: u32 = 0x0f << offset;
11803 pub mod R {}
11804 pub mod W {}
11805 pub mod RW {}
11806 }
11807 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
11808 pub mod RTR {
11809 pub const offset: u32 = 20;
11810 pub const mask: u32 = 0x01 << offset;
11811 pub mod R {}
11812 pub mod W {}
11813 pub mod RW {}
11814 }
11815 #[doc = "ID Extended. One/zero for extended/standard format frame."]
11816 pub mod IDE {
11817 pub const offset: u32 = 21;
11818 pub const mask: u32 = 0x01 << offset;
11819 pub mod R {}
11820 pub mod W {}
11821 pub mod RW {}
11822 }
11823 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
11824 pub mod SRR {
11825 pub const offset: u32 = 22;
11826 pub const mask: u32 = 0x01 << offset;
11827 pub mod R {}
11828 pub mod W {}
11829 pub mod RW {}
11830 }
11831 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
11832 pub mod CODE {
11833 pub const offset: u32 = 24;
11834 pub const mask: u32 = 0x0f << offset;
11835 pub mod R {}
11836 pub mod W {}
11837 pub mod RW {}
11838 }
11839 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
11840 pub mod ESI {
11841 pub const offset: u32 = 29;
11842 pub const mask: u32 = 0x01 << offset;
11843 pub mod R {}
11844 pub mod W {}
11845 pub mod RW {}
11846 }
11847 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
11848 pub mod BRS {
11849 pub const offset: u32 = 30;
11850 pub const mask: u32 = 0x01 << offset;
11851 pub mod R {}
11852 pub mod W {}
11853 pub mod RW {}
11854 }
11855 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
11856 pub mod EDL {
11857 pub const offset: u32 = 31;
11858 pub const mask: u32 = 0x01 << offset;
11859 pub mod R {}
11860 pub mod W {}
11861 pub mod RW {}
11862 }
11863}
11864#[doc = "Message Buffer 56 ID Register"]
11865pub mod ID56 {
11866 #[doc = "Contains extended (LOW word) identifier of message buffer."]
11867 pub mod EXT {
11868 pub const offset: u32 = 0;
11869 pub const mask: u32 = 0x0003_ffff << offset;
11870 pub mod R {}
11871 pub mod W {}
11872 pub mod RW {}
11873 }
11874 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
11875 pub mod STD {
11876 pub const offset: u32 = 18;
11877 pub const mask: u32 = 0x07ff << offset;
11878 pub mod R {}
11879 pub mod W {}
11880 pub mod RW {}
11881 }
11882 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
11883 pub mod PRIO {
11884 pub const offset: u32 = 29;
11885 pub const mask: u32 = 0x07 << offset;
11886 pub mod R {}
11887 pub mod W {}
11888 pub mod RW {}
11889 }
11890}
11891#[doc = "Message Buffer 12 WORD_64B Register"]
11892pub mod MB12_64B_WORD8 {
11893 #[doc = "Data byte 0 of Rx/Tx frame."]
11894 pub mod DATA_BYTE_35 {
11895 pub const offset: u32 = 0;
11896 pub const mask: u32 = 0xff << offset;
11897 pub mod R {}
11898 pub mod W {}
11899 pub mod RW {}
11900 }
11901 #[doc = "Data byte 1 of Rx/Tx frame."]
11902 pub mod DATA_BYTE_34 {
11903 pub const offset: u32 = 8;
11904 pub const mask: u32 = 0xff << offset;
11905 pub mod R {}
11906 pub mod W {}
11907 pub mod RW {}
11908 }
11909 #[doc = "Data byte 2 of Rx/Tx frame."]
11910 pub mod DATA_BYTE_33 {
11911 pub const offset: u32 = 16;
11912 pub const mask: u32 = 0xff << offset;
11913 pub mod R {}
11914 pub mod W {}
11915 pub mod RW {}
11916 }
11917 #[doc = "Data byte 3 of Rx/Tx frame."]
11918 pub mod DATA_BYTE_32 {
11919 pub const offset: u32 = 24;
11920 pub const mask: u32 = 0xff << offset;
11921 pub mod R {}
11922 pub mod W {}
11923 pub mod RW {}
11924 }
11925}
11926#[doc = "Message Buffer 12 WORD_64B Register"]
11927pub mod MB12_64B_WORD9 {
11928 #[doc = "Data byte 0 of Rx/Tx frame."]
11929 pub mod DATA_BYTE_39 {
11930 pub const offset: u32 = 0;
11931 pub const mask: u32 = 0xff << offset;
11932 pub mod R {}
11933 pub mod W {}
11934 pub mod RW {}
11935 }
11936 #[doc = "Data byte 1 of Rx/Tx frame."]
11937 pub mod DATA_BYTE_38 {
11938 pub const offset: u32 = 8;
11939 pub const mask: u32 = 0xff << offset;
11940 pub mod R {}
11941 pub mod W {}
11942 pub mod RW {}
11943 }
11944 #[doc = "Data byte 2 of Rx/Tx frame."]
11945 pub mod DATA_BYTE_37 {
11946 pub const offset: u32 = 16;
11947 pub const mask: u32 = 0xff << offset;
11948 pub mod R {}
11949 pub mod W {}
11950 pub mod RW {}
11951 }
11952 #[doc = "Data byte 3 of Rx/Tx frame."]
11953 pub mod DATA_BYTE_36 {
11954 pub const offset: u32 = 24;
11955 pub const mask: u32 = 0xff << offset;
11956 pub mod R {}
11957 pub mod W {}
11958 pub mod RW {}
11959 }
11960}
11961#[doc = "Message Buffer 57 CS Register"]
11962pub mod CS57 {
11963 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
11964 pub mod TIME_STAMP {
11965 pub const offset: u32 = 0;
11966 pub const mask: u32 = 0xffff << offset;
11967 pub mod R {}
11968 pub mod W {}
11969 pub mod RW {}
11970 }
11971 #[doc = "Length of the data to be stored/transmitted."]
11972 pub mod DLC {
11973 pub const offset: u32 = 16;
11974 pub const mask: u32 = 0x0f << offset;
11975 pub mod R {}
11976 pub mod W {}
11977 pub mod RW {}
11978 }
11979 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
11980 pub mod RTR {
11981 pub const offset: u32 = 20;
11982 pub const mask: u32 = 0x01 << offset;
11983 pub mod R {}
11984 pub mod W {}
11985 pub mod RW {}
11986 }
11987 #[doc = "ID Extended. One/zero for extended/standard format frame."]
11988 pub mod IDE {
11989 pub const offset: u32 = 21;
11990 pub const mask: u32 = 0x01 << offset;
11991 pub mod R {}
11992 pub mod W {}
11993 pub mod RW {}
11994 }
11995 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
11996 pub mod SRR {
11997 pub const offset: u32 = 22;
11998 pub const mask: u32 = 0x01 << offset;
11999 pub mod R {}
12000 pub mod W {}
12001 pub mod RW {}
12002 }
12003 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
12004 pub mod CODE {
12005 pub const offset: u32 = 24;
12006 pub const mask: u32 = 0x0f << offset;
12007 pub mod R {}
12008 pub mod W {}
12009 pub mod RW {}
12010 }
12011 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
12012 pub mod ESI {
12013 pub const offset: u32 = 29;
12014 pub const mask: u32 = 0x01 << offset;
12015 pub mod R {}
12016 pub mod W {}
12017 pub mod RW {}
12018 }
12019 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
12020 pub mod BRS {
12021 pub const offset: u32 = 30;
12022 pub const mask: u32 = 0x01 << offset;
12023 pub mod R {}
12024 pub mod W {}
12025 pub mod RW {}
12026 }
12027 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
12028 pub mod EDL {
12029 pub const offset: u32 = 31;
12030 pub const mask: u32 = 0x01 << offset;
12031 pub mod R {}
12032 pub mod W {}
12033 pub mod RW {}
12034 }
12035}
12036#[doc = "Message Buffer 57 ID Register"]
12037pub mod ID57 {
12038 #[doc = "Contains extended (LOW word) identifier of message buffer."]
12039 pub mod EXT {
12040 pub const offset: u32 = 0;
12041 pub const mask: u32 = 0x0003_ffff << offset;
12042 pub mod R {}
12043 pub mod W {}
12044 pub mod RW {}
12045 }
12046 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
12047 pub mod STD {
12048 pub const offset: u32 = 18;
12049 pub const mask: u32 = 0x07ff << offset;
12050 pub mod R {}
12051 pub mod W {}
12052 pub mod RW {}
12053 }
12054 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
12055 pub mod PRIO {
12056 pub const offset: u32 = 29;
12057 pub const mask: u32 = 0x07 << offset;
12058 pub mod R {}
12059 pub mod W {}
12060 pub mod RW {}
12061 }
12062}
12063#[doc = "Message Buffer 12 WORD_64B Register"]
12064pub mod MB12_64B_WORD12 {
12065 #[doc = "Data byte 0 of Rx/Tx frame."]
12066 pub mod DATA_BYTE_51 {
12067 pub const offset: u32 = 0;
12068 pub const mask: u32 = 0xff << offset;
12069 pub mod R {}
12070 pub mod W {}
12071 pub mod RW {}
12072 }
12073 #[doc = "Data byte 1 of Rx/Tx frame."]
12074 pub mod DATA_BYTE_50 {
12075 pub const offset: u32 = 8;
12076 pub const mask: u32 = 0xff << offset;
12077 pub mod R {}
12078 pub mod W {}
12079 pub mod RW {}
12080 }
12081 #[doc = "Data byte 2 of Rx/Tx frame."]
12082 pub mod DATA_BYTE_49 {
12083 pub const offset: u32 = 16;
12084 pub const mask: u32 = 0xff << offset;
12085 pub mod R {}
12086 pub mod W {}
12087 pub mod RW {}
12088 }
12089 #[doc = "Data byte 3 of Rx/Tx frame."]
12090 pub mod DATA_BYTE_48 {
12091 pub const offset: u32 = 24;
12092 pub const mask: u32 = 0xff << offset;
12093 pub mod R {}
12094 pub mod W {}
12095 pub mod RW {}
12096 }
12097}
12098#[doc = "Message Buffer 12 WORD_64B Register"]
12099pub mod MB12_64B_WORD13 {
12100 #[doc = "Data byte 0 of Rx/Tx frame."]
12101 pub mod DATA_BYTE_55 {
12102 pub const offset: u32 = 0;
12103 pub const mask: u32 = 0xff << offset;
12104 pub mod R {}
12105 pub mod W {}
12106 pub mod RW {}
12107 }
12108 #[doc = "Data byte 1 of Rx/Tx frame."]
12109 pub mod DATA_BYTE_54 {
12110 pub const offset: u32 = 8;
12111 pub const mask: u32 = 0xff << offset;
12112 pub mod R {}
12113 pub mod W {}
12114 pub mod RW {}
12115 }
12116 #[doc = "Data byte 2 of Rx/Tx frame."]
12117 pub mod DATA_BYTE_53 {
12118 pub const offset: u32 = 16;
12119 pub const mask: u32 = 0xff << offset;
12120 pub mod R {}
12121 pub mod W {}
12122 pub mod RW {}
12123 }
12124 #[doc = "Data byte 3 of Rx/Tx frame."]
12125 pub mod DATA_BYTE_52 {
12126 pub const offset: u32 = 24;
12127 pub const mask: u32 = 0xff << offset;
12128 pub mod R {}
12129 pub mod W {}
12130 pub mod RW {}
12131 }
12132}
12133#[doc = "Message Buffer 58 CS Register"]
12134pub mod CS58 {
12135 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
12136 pub mod TIME_STAMP {
12137 pub const offset: u32 = 0;
12138 pub const mask: u32 = 0xffff << offset;
12139 pub mod R {}
12140 pub mod W {}
12141 pub mod RW {}
12142 }
12143 #[doc = "Length of the data to be stored/transmitted."]
12144 pub mod DLC {
12145 pub const offset: u32 = 16;
12146 pub const mask: u32 = 0x0f << offset;
12147 pub mod R {}
12148 pub mod W {}
12149 pub mod RW {}
12150 }
12151 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
12152 pub mod RTR {
12153 pub const offset: u32 = 20;
12154 pub const mask: u32 = 0x01 << offset;
12155 pub mod R {}
12156 pub mod W {}
12157 pub mod RW {}
12158 }
12159 #[doc = "ID Extended. One/zero for extended/standard format frame."]
12160 pub mod IDE {
12161 pub const offset: u32 = 21;
12162 pub const mask: u32 = 0x01 << offset;
12163 pub mod R {}
12164 pub mod W {}
12165 pub mod RW {}
12166 }
12167 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
12168 pub mod SRR {
12169 pub const offset: u32 = 22;
12170 pub const mask: u32 = 0x01 << offset;
12171 pub mod R {}
12172 pub mod W {}
12173 pub mod RW {}
12174 }
12175 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
12176 pub mod CODE {
12177 pub const offset: u32 = 24;
12178 pub const mask: u32 = 0x0f << offset;
12179 pub mod R {}
12180 pub mod W {}
12181 pub mod RW {}
12182 }
12183 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
12184 pub mod ESI {
12185 pub const offset: u32 = 29;
12186 pub const mask: u32 = 0x01 << offset;
12187 pub mod R {}
12188 pub mod W {}
12189 pub mod RW {}
12190 }
12191 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
12192 pub mod BRS {
12193 pub const offset: u32 = 30;
12194 pub const mask: u32 = 0x01 << offset;
12195 pub mod R {}
12196 pub mod W {}
12197 pub mod RW {}
12198 }
12199 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
12200 pub mod EDL {
12201 pub const offset: u32 = 31;
12202 pub const mask: u32 = 0x01 << offset;
12203 pub mod R {}
12204 pub mod W {}
12205 pub mod RW {}
12206 }
12207}
12208#[doc = "Message Buffer 58 ID Register"]
12209pub mod ID58 {
12210 #[doc = "Contains extended (LOW word) identifier of message buffer."]
12211 pub mod EXT {
12212 pub const offset: u32 = 0;
12213 pub const mask: u32 = 0x0003_ffff << offset;
12214 pub mod R {}
12215 pub mod W {}
12216 pub mod RW {}
12217 }
12218 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
12219 pub mod STD {
12220 pub const offset: u32 = 18;
12221 pub const mask: u32 = 0x07ff << offset;
12222 pub mod R {}
12223 pub mod W {}
12224 pub mod RW {}
12225 }
12226 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
12227 pub mod PRIO {
12228 pub const offset: u32 = 29;
12229 pub const mask: u32 = 0x07 << offset;
12230 pub mod R {}
12231 pub mod W {}
12232 pub mod RW {}
12233 }
12234}
12235#[doc = "Message Buffer 13 CS Register"]
12236pub mod MB13_64B_CS {
12237 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
12238 pub mod TIME_STAMP {
12239 pub const offset: u32 = 0;
12240 pub const mask: u32 = 0xffff << offset;
12241 pub mod R {}
12242 pub mod W {}
12243 pub mod RW {}
12244 }
12245 #[doc = "Length of the data to be stored/transmitted."]
12246 pub mod DLC {
12247 pub const offset: u32 = 16;
12248 pub const mask: u32 = 0x0f << offset;
12249 pub mod R {}
12250 pub mod W {}
12251 pub mod RW {}
12252 }
12253 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
12254 pub mod RTR {
12255 pub const offset: u32 = 20;
12256 pub const mask: u32 = 0x01 << offset;
12257 pub mod R {}
12258 pub mod W {}
12259 pub mod RW {}
12260 }
12261 #[doc = "ID Extended. One/zero for extended/standard format frame."]
12262 pub mod IDE {
12263 pub const offset: u32 = 21;
12264 pub const mask: u32 = 0x01 << offset;
12265 pub mod R {}
12266 pub mod W {}
12267 pub mod RW {}
12268 }
12269 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
12270 pub mod SRR {
12271 pub const offset: u32 = 22;
12272 pub const mask: u32 = 0x01 << offset;
12273 pub mod R {}
12274 pub mod W {}
12275 pub mod RW {}
12276 }
12277 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
12278 pub mod CODE {
12279 pub const offset: u32 = 24;
12280 pub const mask: u32 = 0x0f << offset;
12281 pub mod R {}
12282 pub mod W {}
12283 pub mod RW {}
12284 }
12285 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
12286 pub mod ESI {
12287 pub const offset: u32 = 29;
12288 pub const mask: u32 = 0x01 << offset;
12289 pub mod R {}
12290 pub mod W {}
12291 pub mod RW {}
12292 }
12293 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
12294 pub mod BRS {
12295 pub const offset: u32 = 30;
12296 pub const mask: u32 = 0x01 << offset;
12297 pub mod R {}
12298 pub mod W {}
12299 pub mod RW {}
12300 }
12301 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
12302 pub mod EDL {
12303 pub const offset: u32 = 31;
12304 pub const mask: u32 = 0x01 << offset;
12305 pub mod R {}
12306 pub mod W {}
12307 pub mod RW {}
12308 }
12309}
12310#[doc = "Message Buffer 13 ID Register"]
12311pub mod MB13_64B_ID {
12312 #[doc = "Contains extended (LOW word) identifier of message buffer."]
12313 pub mod EXT {
12314 pub const offset: u32 = 0;
12315 pub const mask: u32 = 0x0003_ffff << offset;
12316 pub mod R {}
12317 pub mod W {}
12318 pub mod RW {}
12319 }
12320 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
12321 pub mod STD {
12322 pub const offset: u32 = 18;
12323 pub const mask: u32 = 0x07ff << offset;
12324 pub mod R {}
12325 pub mod W {}
12326 pub mod RW {}
12327 }
12328 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
12329 pub mod PRIO {
12330 pub const offset: u32 = 29;
12331 pub const mask: u32 = 0x07 << offset;
12332 pub mod R {}
12333 pub mod W {}
12334 pub mod RW {}
12335 }
12336}
12337#[doc = "Message Buffer 59 CS Register"]
12338pub mod CS59 {
12339 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
12340 pub mod TIME_STAMP {
12341 pub const offset: u32 = 0;
12342 pub const mask: u32 = 0xffff << offset;
12343 pub mod R {}
12344 pub mod W {}
12345 pub mod RW {}
12346 }
12347 #[doc = "Length of the data to be stored/transmitted."]
12348 pub mod DLC {
12349 pub const offset: u32 = 16;
12350 pub const mask: u32 = 0x0f << offset;
12351 pub mod R {}
12352 pub mod W {}
12353 pub mod RW {}
12354 }
12355 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
12356 pub mod RTR {
12357 pub const offset: u32 = 20;
12358 pub const mask: u32 = 0x01 << offset;
12359 pub mod R {}
12360 pub mod W {}
12361 pub mod RW {}
12362 }
12363 #[doc = "ID Extended. One/zero for extended/standard format frame."]
12364 pub mod IDE {
12365 pub const offset: u32 = 21;
12366 pub const mask: u32 = 0x01 << offset;
12367 pub mod R {}
12368 pub mod W {}
12369 pub mod RW {}
12370 }
12371 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
12372 pub mod SRR {
12373 pub const offset: u32 = 22;
12374 pub const mask: u32 = 0x01 << offset;
12375 pub mod R {}
12376 pub mod W {}
12377 pub mod RW {}
12378 }
12379 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
12380 pub mod CODE {
12381 pub const offset: u32 = 24;
12382 pub const mask: u32 = 0x0f << offset;
12383 pub mod R {}
12384 pub mod W {}
12385 pub mod RW {}
12386 }
12387 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
12388 pub mod ESI {
12389 pub const offset: u32 = 29;
12390 pub const mask: u32 = 0x01 << offset;
12391 pub mod R {}
12392 pub mod W {}
12393 pub mod RW {}
12394 }
12395 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
12396 pub mod BRS {
12397 pub const offset: u32 = 30;
12398 pub const mask: u32 = 0x01 << offset;
12399 pub mod R {}
12400 pub mod W {}
12401 pub mod RW {}
12402 }
12403 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
12404 pub mod EDL {
12405 pub const offset: u32 = 31;
12406 pub const mask: u32 = 0x01 << offset;
12407 pub mod R {}
12408 pub mod W {}
12409 pub mod RW {}
12410 }
12411}
12412#[doc = "Message Buffer 59 ID Register"]
12413pub mod ID59 {
12414 #[doc = "Contains extended (LOW word) identifier of message buffer."]
12415 pub mod EXT {
12416 pub const offset: u32 = 0;
12417 pub const mask: u32 = 0x0003_ffff << offset;
12418 pub mod R {}
12419 pub mod W {}
12420 pub mod RW {}
12421 }
12422 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
12423 pub mod STD {
12424 pub const offset: u32 = 18;
12425 pub const mask: u32 = 0x07ff << offset;
12426 pub mod R {}
12427 pub mod W {}
12428 pub mod RW {}
12429 }
12430 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
12431 pub mod PRIO {
12432 pub const offset: u32 = 29;
12433 pub const mask: u32 = 0x07 << offset;
12434 pub mod R {}
12435 pub mod W {}
12436 pub mod RW {}
12437 }
12438}
12439#[doc = "Message Buffer 13 WORD_64B Register"]
12440pub mod MB13_64B_WORD2 {
12441 #[doc = "Data byte 0 of Rx/Tx frame."]
12442 pub mod DATA_BYTE_11 {
12443 pub const offset: u32 = 0;
12444 pub const mask: u32 = 0xff << offset;
12445 pub mod R {}
12446 pub mod W {}
12447 pub mod RW {}
12448 }
12449 #[doc = "Data byte 1 of Rx/Tx frame."]
12450 pub mod DATA_BYTE_10 {
12451 pub const offset: u32 = 8;
12452 pub const mask: u32 = 0xff << offset;
12453 pub mod R {}
12454 pub mod W {}
12455 pub mod RW {}
12456 }
12457 #[doc = "Data byte 2 of Rx/Tx frame."]
12458 pub mod DATA_BYTE_9 {
12459 pub const offset: u32 = 16;
12460 pub const mask: u32 = 0xff << offset;
12461 pub mod R {}
12462 pub mod W {}
12463 pub mod RW {}
12464 }
12465 #[doc = "Data byte 3 of Rx/Tx frame."]
12466 pub mod DATA_BYTE_8 {
12467 pub const offset: u32 = 24;
12468 pub const mask: u32 = 0xff << offset;
12469 pub mod R {}
12470 pub mod W {}
12471 pub mod RW {}
12472 }
12473}
12474#[doc = "Message Buffer 13 WORD_64B Register"]
12475pub mod MB13_64B_WORD3 {
12476 #[doc = "Data byte 0 of Rx/Tx frame."]
12477 pub mod DATA_BYTE_15 {
12478 pub const offset: u32 = 0;
12479 pub const mask: u32 = 0xff << offset;
12480 pub mod R {}
12481 pub mod W {}
12482 pub mod RW {}
12483 }
12484 #[doc = "Data byte 1 of Rx/Tx frame."]
12485 pub mod DATA_BYTE_14 {
12486 pub const offset: u32 = 8;
12487 pub const mask: u32 = 0xff << offset;
12488 pub mod R {}
12489 pub mod W {}
12490 pub mod RW {}
12491 }
12492 #[doc = "Data byte 2 of Rx/Tx frame."]
12493 pub mod DATA_BYTE_13 {
12494 pub const offset: u32 = 16;
12495 pub const mask: u32 = 0xff << offset;
12496 pub mod R {}
12497 pub mod W {}
12498 pub mod RW {}
12499 }
12500 #[doc = "Data byte 3 of Rx/Tx frame."]
12501 pub mod DATA_BYTE_12 {
12502 pub const offset: u32 = 24;
12503 pub const mask: u32 = 0xff << offset;
12504 pub mod R {}
12505 pub mod W {}
12506 pub mod RW {}
12507 }
12508}
12509#[doc = "Message Buffer 60 CS Register"]
12510pub mod CS60 {
12511 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
12512 pub mod TIME_STAMP {
12513 pub const offset: u32 = 0;
12514 pub const mask: u32 = 0xffff << offset;
12515 pub mod R {}
12516 pub mod W {}
12517 pub mod RW {}
12518 }
12519 #[doc = "Length of the data to be stored/transmitted."]
12520 pub mod DLC {
12521 pub const offset: u32 = 16;
12522 pub const mask: u32 = 0x0f << offset;
12523 pub mod R {}
12524 pub mod W {}
12525 pub mod RW {}
12526 }
12527 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
12528 pub mod RTR {
12529 pub const offset: u32 = 20;
12530 pub const mask: u32 = 0x01 << offset;
12531 pub mod R {}
12532 pub mod W {}
12533 pub mod RW {}
12534 }
12535 #[doc = "ID Extended. One/zero for extended/standard format frame."]
12536 pub mod IDE {
12537 pub const offset: u32 = 21;
12538 pub const mask: u32 = 0x01 << offset;
12539 pub mod R {}
12540 pub mod W {}
12541 pub mod RW {}
12542 }
12543 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
12544 pub mod SRR {
12545 pub const offset: u32 = 22;
12546 pub const mask: u32 = 0x01 << offset;
12547 pub mod R {}
12548 pub mod W {}
12549 pub mod RW {}
12550 }
12551 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
12552 pub mod CODE {
12553 pub const offset: u32 = 24;
12554 pub const mask: u32 = 0x0f << offset;
12555 pub mod R {}
12556 pub mod W {}
12557 pub mod RW {}
12558 }
12559 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
12560 pub mod ESI {
12561 pub const offset: u32 = 29;
12562 pub const mask: u32 = 0x01 << offset;
12563 pub mod R {}
12564 pub mod W {}
12565 pub mod RW {}
12566 }
12567 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
12568 pub mod BRS {
12569 pub const offset: u32 = 30;
12570 pub const mask: u32 = 0x01 << offset;
12571 pub mod R {}
12572 pub mod W {}
12573 pub mod RW {}
12574 }
12575 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
12576 pub mod EDL {
12577 pub const offset: u32 = 31;
12578 pub const mask: u32 = 0x01 << offset;
12579 pub mod R {}
12580 pub mod W {}
12581 pub mod RW {}
12582 }
12583}
12584#[doc = "Message Buffer 60 ID Register"]
12585pub mod ID60 {
12586 #[doc = "Contains extended (LOW word) identifier of message buffer."]
12587 pub mod EXT {
12588 pub const offset: u32 = 0;
12589 pub const mask: u32 = 0x0003_ffff << offset;
12590 pub mod R {}
12591 pub mod W {}
12592 pub mod RW {}
12593 }
12594 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
12595 pub mod STD {
12596 pub const offset: u32 = 18;
12597 pub const mask: u32 = 0x07ff << offset;
12598 pub mod R {}
12599 pub mod W {}
12600 pub mod RW {}
12601 }
12602 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
12603 pub mod PRIO {
12604 pub const offset: u32 = 29;
12605 pub const mask: u32 = 0x07 << offset;
12606 pub mod R {}
12607 pub mod W {}
12608 pub mod RW {}
12609 }
12610}
12611#[doc = "Message Buffer 13 WORD_64B Register"]
12612pub mod MB13_64B_WORD6 {
12613 #[doc = "Data byte 0 of Rx/Tx frame."]
12614 pub mod DATA_BYTE_27 {
12615 pub const offset: u32 = 0;
12616 pub const mask: u32 = 0xff << offset;
12617 pub mod R {}
12618 pub mod W {}
12619 pub mod RW {}
12620 }
12621 #[doc = "Data byte 1 of Rx/Tx frame."]
12622 pub mod DATA_BYTE_26 {
12623 pub const offset: u32 = 8;
12624 pub const mask: u32 = 0xff << offset;
12625 pub mod R {}
12626 pub mod W {}
12627 pub mod RW {}
12628 }
12629 #[doc = "Data byte 2 of Rx/Tx frame."]
12630 pub mod DATA_BYTE_25 {
12631 pub const offset: u32 = 16;
12632 pub const mask: u32 = 0xff << offset;
12633 pub mod R {}
12634 pub mod W {}
12635 pub mod RW {}
12636 }
12637 #[doc = "Data byte 3 of Rx/Tx frame."]
12638 pub mod DATA_BYTE_24 {
12639 pub const offset: u32 = 24;
12640 pub const mask: u32 = 0xff << offset;
12641 pub mod R {}
12642 pub mod W {}
12643 pub mod RW {}
12644 }
12645}
12646#[doc = "Message Buffer 13 WORD_64B Register"]
12647pub mod MB13_64B_WORD7 {
12648 #[doc = "Data byte 0 of Rx/Tx frame."]
12649 pub mod DATA_BYTE_31 {
12650 pub const offset: u32 = 0;
12651 pub const mask: u32 = 0xff << offset;
12652 pub mod R {}
12653 pub mod W {}
12654 pub mod RW {}
12655 }
12656 #[doc = "Data byte 1 of Rx/Tx frame."]
12657 pub mod DATA_BYTE_30 {
12658 pub const offset: u32 = 8;
12659 pub const mask: u32 = 0xff << offset;
12660 pub mod R {}
12661 pub mod W {}
12662 pub mod RW {}
12663 }
12664 #[doc = "Data byte 2 of Rx/Tx frame."]
12665 pub mod DATA_BYTE_29 {
12666 pub const offset: u32 = 16;
12667 pub const mask: u32 = 0xff << offset;
12668 pub mod R {}
12669 pub mod W {}
12670 pub mod RW {}
12671 }
12672 #[doc = "Data byte 3 of Rx/Tx frame."]
12673 pub mod DATA_BYTE_28 {
12674 pub const offset: u32 = 24;
12675 pub const mask: u32 = 0xff << offset;
12676 pub mod R {}
12677 pub mod W {}
12678 pub mod RW {}
12679 }
12680}
12681#[doc = "Message Buffer 61 CS Register"]
12682pub mod CS61 {
12683 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
12684 pub mod TIME_STAMP {
12685 pub const offset: u32 = 0;
12686 pub const mask: u32 = 0xffff << offset;
12687 pub mod R {}
12688 pub mod W {}
12689 pub mod RW {}
12690 }
12691 #[doc = "Length of the data to be stored/transmitted."]
12692 pub mod DLC {
12693 pub const offset: u32 = 16;
12694 pub const mask: u32 = 0x0f << offset;
12695 pub mod R {}
12696 pub mod W {}
12697 pub mod RW {}
12698 }
12699 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
12700 pub mod RTR {
12701 pub const offset: u32 = 20;
12702 pub const mask: u32 = 0x01 << offset;
12703 pub mod R {}
12704 pub mod W {}
12705 pub mod RW {}
12706 }
12707 #[doc = "ID Extended. One/zero for extended/standard format frame."]
12708 pub mod IDE {
12709 pub const offset: u32 = 21;
12710 pub const mask: u32 = 0x01 << offset;
12711 pub mod R {}
12712 pub mod W {}
12713 pub mod RW {}
12714 }
12715 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
12716 pub mod SRR {
12717 pub const offset: u32 = 22;
12718 pub const mask: u32 = 0x01 << offset;
12719 pub mod R {}
12720 pub mod W {}
12721 pub mod RW {}
12722 }
12723 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
12724 pub mod CODE {
12725 pub const offset: u32 = 24;
12726 pub const mask: u32 = 0x0f << offset;
12727 pub mod R {}
12728 pub mod W {}
12729 pub mod RW {}
12730 }
12731 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
12732 pub mod ESI {
12733 pub const offset: u32 = 29;
12734 pub const mask: u32 = 0x01 << offset;
12735 pub mod R {}
12736 pub mod W {}
12737 pub mod RW {}
12738 }
12739 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
12740 pub mod BRS {
12741 pub const offset: u32 = 30;
12742 pub const mask: u32 = 0x01 << offset;
12743 pub mod R {}
12744 pub mod W {}
12745 pub mod RW {}
12746 }
12747 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
12748 pub mod EDL {
12749 pub const offset: u32 = 31;
12750 pub const mask: u32 = 0x01 << offset;
12751 pub mod R {}
12752 pub mod W {}
12753 pub mod RW {}
12754 }
12755}
12756#[doc = "Message Buffer 61 ID Register"]
12757pub mod ID61 {
12758 #[doc = "Contains extended (LOW word) identifier of message buffer."]
12759 pub mod EXT {
12760 pub const offset: u32 = 0;
12761 pub const mask: u32 = 0x0003_ffff << offset;
12762 pub mod R {}
12763 pub mod W {}
12764 pub mod RW {}
12765 }
12766 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
12767 pub mod STD {
12768 pub const offset: u32 = 18;
12769 pub const mask: u32 = 0x07ff << offset;
12770 pub mod R {}
12771 pub mod W {}
12772 pub mod RW {}
12773 }
12774 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
12775 pub mod PRIO {
12776 pub const offset: u32 = 29;
12777 pub const mask: u32 = 0x07 << offset;
12778 pub mod R {}
12779 pub mod W {}
12780 pub mod RW {}
12781 }
12782}
12783#[doc = "Message Buffer 13 WORD_64B Register"]
12784pub mod MB13_64B_WORD10 {
12785 #[doc = "Data byte 0 of Rx/Tx frame."]
12786 pub mod DATA_BYTE_43 {
12787 pub const offset: u32 = 0;
12788 pub const mask: u32 = 0xff << offset;
12789 pub mod R {}
12790 pub mod W {}
12791 pub mod RW {}
12792 }
12793 #[doc = "Data byte 1 of Rx/Tx frame."]
12794 pub mod DATA_BYTE_42 {
12795 pub const offset: u32 = 8;
12796 pub const mask: u32 = 0xff << offset;
12797 pub mod R {}
12798 pub mod W {}
12799 pub mod RW {}
12800 }
12801 #[doc = "Data byte 2 of Rx/Tx frame."]
12802 pub mod DATA_BYTE_41 {
12803 pub const offset: u32 = 16;
12804 pub const mask: u32 = 0xff << offset;
12805 pub mod R {}
12806 pub mod W {}
12807 pub mod RW {}
12808 }
12809 #[doc = "Data byte 3 of Rx/Tx frame."]
12810 pub mod DATA_BYTE_40 {
12811 pub const offset: u32 = 24;
12812 pub const mask: u32 = 0xff << offset;
12813 pub mod R {}
12814 pub mod W {}
12815 pub mod RW {}
12816 }
12817}
12818#[doc = "Message Buffer 13 WORD_64B Register"]
12819pub mod MB13_64B_WORD11 {
12820 #[doc = "Data byte 0 of Rx/Tx frame."]
12821 pub mod DATA_BYTE_47 {
12822 pub const offset: u32 = 0;
12823 pub const mask: u32 = 0xff << offset;
12824 pub mod R {}
12825 pub mod W {}
12826 pub mod RW {}
12827 }
12828 #[doc = "Data byte 1 of Rx/Tx frame."]
12829 pub mod DATA_BYTE_46 {
12830 pub const offset: u32 = 8;
12831 pub const mask: u32 = 0xff << offset;
12832 pub mod R {}
12833 pub mod W {}
12834 pub mod RW {}
12835 }
12836 #[doc = "Data byte 2 of Rx/Tx frame."]
12837 pub mod DATA_BYTE_45 {
12838 pub const offset: u32 = 16;
12839 pub const mask: u32 = 0xff << offset;
12840 pub mod R {}
12841 pub mod W {}
12842 pub mod RW {}
12843 }
12844 #[doc = "Data byte 3 of Rx/Tx frame."]
12845 pub mod DATA_BYTE_44 {
12846 pub const offset: u32 = 24;
12847 pub const mask: u32 = 0xff << offset;
12848 pub mod R {}
12849 pub mod W {}
12850 pub mod RW {}
12851 }
12852}
12853#[doc = "Message Buffer 62 CS Register"]
12854pub mod CS62 {
12855 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
12856 pub mod TIME_STAMP {
12857 pub const offset: u32 = 0;
12858 pub const mask: u32 = 0xffff << offset;
12859 pub mod R {}
12860 pub mod W {}
12861 pub mod RW {}
12862 }
12863 #[doc = "Length of the data to be stored/transmitted."]
12864 pub mod DLC {
12865 pub const offset: u32 = 16;
12866 pub const mask: u32 = 0x0f << offset;
12867 pub mod R {}
12868 pub mod W {}
12869 pub mod RW {}
12870 }
12871 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
12872 pub mod RTR {
12873 pub const offset: u32 = 20;
12874 pub const mask: u32 = 0x01 << offset;
12875 pub mod R {}
12876 pub mod W {}
12877 pub mod RW {}
12878 }
12879 #[doc = "ID Extended. One/zero for extended/standard format frame."]
12880 pub mod IDE {
12881 pub const offset: u32 = 21;
12882 pub const mask: u32 = 0x01 << offset;
12883 pub mod R {}
12884 pub mod W {}
12885 pub mod RW {}
12886 }
12887 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
12888 pub mod SRR {
12889 pub const offset: u32 = 22;
12890 pub const mask: u32 = 0x01 << offset;
12891 pub mod R {}
12892 pub mod W {}
12893 pub mod RW {}
12894 }
12895 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
12896 pub mod CODE {
12897 pub const offset: u32 = 24;
12898 pub const mask: u32 = 0x0f << offset;
12899 pub mod R {}
12900 pub mod W {}
12901 pub mod RW {}
12902 }
12903 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
12904 pub mod ESI {
12905 pub const offset: u32 = 29;
12906 pub const mask: u32 = 0x01 << offset;
12907 pub mod R {}
12908 pub mod W {}
12909 pub mod RW {}
12910 }
12911 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
12912 pub mod BRS {
12913 pub const offset: u32 = 30;
12914 pub const mask: u32 = 0x01 << offset;
12915 pub mod R {}
12916 pub mod W {}
12917 pub mod RW {}
12918 }
12919 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
12920 pub mod EDL {
12921 pub const offset: u32 = 31;
12922 pub const mask: u32 = 0x01 << offset;
12923 pub mod R {}
12924 pub mod W {}
12925 pub mod RW {}
12926 }
12927}
12928#[doc = "Message Buffer 62 ID Register"]
12929pub mod ID62 {
12930 #[doc = "Contains extended (LOW word) identifier of message buffer."]
12931 pub mod EXT {
12932 pub const offset: u32 = 0;
12933 pub const mask: u32 = 0x0003_ffff << offset;
12934 pub mod R {}
12935 pub mod W {}
12936 pub mod RW {}
12937 }
12938 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
12939 pub mod STD {
12940 pub const offset: u32 = 18;
12941 pub const mask: u32 = 0x07ff << offset;
12942 pub mod R {}
12943 pub mod W {}
12944 pub mod RW {}
12945 }
12946 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
12947 pub mod PRIO {
12948 pub const offset: u32 = 29;
12949 pub const mask: u32 = 0x07 << offset;
12950 pub mod R {}
12951 pub mod W {}
12952 pub mod RW {}
12953 }
12954}
12955#[doc = "Message Buffer 13 WORD_64B Register"]
12956pub mod MB13_64B_WORD14 {
12957 #[doc = "Data byte 0 of Rx/Tx frame."]
12958 pub mod DATA_BYTE_59 {
12959 pub const offset: u32 = 0;
12960 pub const mask: u32 = 0xff << offset;
12961 pub mod R {}
12962 pub mod W {}
12963 pub mod RW {}
12964 }
12965 #[doc = "Data byte 1 of Rx/Tx frame."]
12966 pub mod DATA_BYTE_58 {
12967 pub const offset: u32 = 8;
12968 pub const mask: u32 = 0xff << offset;
12969 pub mod R {}
12970 pub mod W {}
12971 pub mod RW {}
12972 }
12973 #[doc = "Data byte 2 of Rx/Tx frame."]
12974 pub mod DATA_BYTE_57 {
12975 pub const offset: u32 = 16;
12976 pub const mask: u32 = 0xff << offset;
12977 pub mod R {}
12978 pub mod W {}
12979 pub mod RW {}
12980 }
12981 #[doc = "Data byte 3 of Rx/Tx frame."]
12982 pub mod DATA_BYTE_56 {
12983 pub const offset: u32 = 24;
12984 pub const mask: u32 = 0xff << offset;
12985 pub mod R {}
12986 pub mod W {}
12987 pub mod RW {}
12988 }
12989}
12990#[doc = "Message Buffer 13 WORD_64B Register"]
12991pub mod MB13_64B_WORD15 {
12992 #[doc = "Data byte 0 of Rx/Tx frame."]
12993 pub mod DATA_BYTE_63 {
12994 pub const offset: u32 = 0;
12995 pub const mask: u32 = 0xff << offset;
12996 pub mod R {}
12997 pub mod W {}
12998 pub mod RW {}
12999 }
13000 #[doc = "Data byte 1 of Rx/Tx frame."]
13001 pub mod DATA_BYTE_62 {
13002 pub const offset: u32 = 8;
13003 pub const mask: u32 = 0xff << offset;
13004 pub mod R {}
13005 pub mod W {}
13006 pub mod RW {}
13007 }
13008 #[doc = "Data byte 2 of Rx/Tx frame."]
13009 pub mod DATA_BYTE_61 {
13010 pub const offset: u32 = 16;
13011 pub const mask: u32 = 0xff << offset;
13012 pub mod R {}
13013 pub mod W {}
13014 pub mod RW {}
13015 }
13016 #[doc = "Data byte 3 of Rx/Tx frame."]
13017 pub mod DATA_BYTE_60 {
13018 pub const offset: u32 = 24;
13019 pub const mask: u32 = 0xff << offset;
13020 pub mod R {}
13021 pub mod W {}
13022 pub mod RW {}
13023 }
13024}
13025#[doc = "Message Buffer 63 CS Register"]
13026pub mod CS63 {
13027 #[doc = "Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus."]
13028 pub mod TIME_STAMP {
13029 pub const offset: u32 = 0;
13030 pub const mask: u32 = 0xffff << offset;
13031 pub mod R {}
13032 pub mod W {}
13033 pub mod RW {}
13034 }
13035 #[doc = "Length of the data to be stored/transmitted."]
13036 pub mod DLC {
13037 pub const offset: u32 = 16;
13038 pub const mask: u32 = 0x0f << offset;
13039 pub mod R {}
13040 pub mod W {}
13041 pub mod RW {}
13042 }
13043 #[doc = "Remote Transmission Request. One/zero for remote/data frame."]
13044 pub mod RTR {
13045 pub const offset: u32 = 20;
13046 pub const mask: u32 = 0x01 << offset;
13047 pub mod R {}
13048 pub mod W {}
13049 pub mod RW {}
13050 }
13051 #[doc = "ID Extended. One/zero for extended/standard format frame."]
13052 pub mod IDE {
13053 pub const offset: u32 = 21;
13054 pub const mask: u32 = 0x01 << offset;
13055 pub mod R {}
13056 pub mod W {}
13057 pub mod RW {}
13058 }
13059 #[doc = "Substitute Remote Request. Contains a fixed recessive bit."]
13060 pub mod SRR {
13061 pub const offset: u32 = 22;
13062 pub const mask: u32 = 0x01 << offset;
13063 pub mod R {}
13064 pub mod W {}
13065 pub mod RW {}
13066 }
13067 #[doc = "Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process."]
13068 pub mod CODE {
13069 pub const offset: u32 = 24;
13070 pub const mask: u32 = 0x0f << offset;
13071 pub mod R {}
13072 pub mod W {}
13073 pub mod RW {}
13074 }
13075 #[doc = "Error State Indicator. This bit indicates if the transmitting node is error active or error passive."]
13076 pub mod ESI {
13077 pub const offset: u32 = 29;
13078 pub const mask: u32 = 0x01 << offset;
13079 pub mod R {}
13080 pub mod W {}
13081 pub mod RW {}
13082 }
13083 #[doc = "Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame."]
13084 pub mod BRS {
13085 pub const offset: u32 = 30;
13086 pub const mask: u32 = 0x01 << offset;
13087 pub mod R {}
13088 pub mod W {}
13089 pub mod RW {}
13090 }
13091 #[doc = "Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010."]
13092 pub mod EDL {
13093 pub const offset: u32 = 31;
13094 pub const mask: u32 = 0x01 << offset;
13095 pub mod R {}
13096 pub mod W {}
13097 pub mod RW {}
13098 }
13099}
13100#[doc = "Message Buffer 63 ID Register"]
13101pub mod ID63 {
13102 #[doc = "Contains extended (LOW word) identifier of message buffer."]
13103 pub mod EXT {
13104 pub const offset: u32 = 0;
13105 pub const mask: u32 = 0x0003_ffff << offset;
13106 pub mod R {}
13107 pub mod W {}
13108 pub mod RW {}
13109 }
13110 #[doc = "Contains standard/extended (HIGH word) identifier of message buffer."]
13111 pub mod STD {
13112 pub const offset: u32 = 18;
13113 pub const mask: u32 = 0x07ff << offset;
13114 pub mod R {}
13115 pub mod W {}
13116 pub mod RW {}
13117 }
13118 #[doc = "Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority."]
13119 pub mod PRIO {
13120 pub const offset: u32 = 29;
13121 pub const mask: u32 = 0x07 << offset;
13122 pub mod R {}
13123 pub mod W {}
13124 pub mod RW {}
13125 }
13126}
13127#[doc = "Message Buffer 63 WORD_8B Register"]
13128pub mod MB63_8B_WORD0 {
13129 #[doc = "Data byte 0 of Rx/Tx frame."]
13130 pub mod DATA_BYTE_3 {
13131 pub const offset: u32 = 0;
13132 pub const mask: u32 = 0xff << offset;
13133 pub mod R {}
13134 pub mod W {}
13135 pub mod RW {}
13136 }
13137 #[doc = "Data byte 1 of Rx/Tx frame."]
13138 pub mod DATA_BYTE_2 {
13139 pub const offset: u32 = 8;
13140 pub const mask: u32 = 0xff << offset;
13141 pub mod R {}
13142 pub mod W {}
13143 pub mod RW {}
13144 }
13145 #[doc = "Data byte 2 of Rx/Tx frame."]
13146 pub mod DATA_BYTE_1 {
13147 pub const offset: u32 = 16;
13148 pub const mask: u32 = 0xff << offset;
13149 pub mod R {}
13150 pub mod W {}
13151 pub mod RW {}
13152 }
13153 #[doc = "Data byte 3 of Rx/Tx frame."]
13154 pub mod DATA_BYTE_0 {
13155 pub const offset: u32 = 24;
13156 pub const mask: u32 = 0xff << offset;
13157 pub mod R {}
13158 pub mod W {}
13159 pub mod RW {}
13160 }
13161}
13162#[doc = "Message Buffer 63 WORD_8B Register"]
13163pub mod MB63_8B_WORD1 {
13164 #[doc = "Data byte 0 of Rx/Tx frame."]
13165 pub mod DATA_BYTE_7 {
13166 pub const offset: u32 = 0;
13167 pub const mask: u32 = 0xff << offset;
13168 pub mod R {}
13169 pub mod W {}
13170 pub mod RW {}
13171 }
13172 #[doc = "Data byte 1 of Rx/Tx frame."]
13173 pub mod DATA_BYTE_6 {
13174 pub const offset: u32 = 8;
13175 pub const mask: u32 = 0xff << offset;
13176 pub mod R {}
13177 pub mod W {}
13178 pub mod RW {}
13179 }
13180 #[doc = "Data byte 2 of Rx/Tx frame."]
13181 pub mod DATA_BYTE_5 {
13182 pub const offset: u32 = 16;
13183 pub const mask: u32 = 0xff << offset;
13184 pub mod R {}
13185 pub mod W {}
13186 pub mod RW {}
13187 }
13188 #[doc = "Data byte 3 of Rx/Tx frame."]
13189 pub mod DATA_BYTE_4 {
13190 pub const offset: u32 = 24;
13191 pub const mask: u32 = 0xff << offset;
13192 pub mod R {}
13193 pub mod W {}
13194 pub mod RW {}
13195 }
13196}
13197#[doc = "Rx Individual Mask Registers"]
13198pub mod RXIMR {
13199 #[doc = "Individual Mask Bits"]
13200 pub mod MI {
13201 pub const offset: u32 = 0;
13202 pub const mask: u32 = 0xffff_ffff << offset;
13203 pub mod R {}
13204 pub mod W {}
13205 pub mod RW {}
13206 }
13207}
13208#[doc = "Enhanced CAN Bit Timing Prescalers"]
13209pub mod EPRS {
13210 #[doc = "Extended Nominal Prescaler Division Factor"]
13211 pub mod ENPRESDIV {
13212 pub const offset: u32 = 0;
13213 pub const mask: u32 = 0x03ff << offset;
13214 pub mod R {}
13215 pub mod W {}
13216 pub mod RW {}
13217 }
13218 #[doc = "Extended Data Phase Prescaler Division Factor"]
13219 pub mod EDPRESDIV {
13220 pub const offset: u32 = 16;
13221 pub const mask: u32 = 0x03ff << offset;
13222 pub mod R {}
13223 pub mod W {}
13224 pub mod RW {}
13225 }
13226}
13227#[doc = "Enhanced Nominal CAN Bit Timing"]
13228pub mod ENCBT {
13229 #[doc = "Nominal Time Segment 1"]
13230 pub mod NTSEG1 {
13231 pub const offset: u32 = 0;
13232 pub const mask: u32 = 0xff << offset;
13233 pub mod R {}
13234 pub mod W {}
13235 pub mod RW {}
13236 }
13237 #[doc = "Nominal Time Segment 2"]
13238 pub mod NTSEG2 {
13239 pub const offset: u32 = 12;
13240 pub const mask: u32 = 0x7f << offset;
13241 pub mod R {}
13242 pub mod W {}
13243 pub mod RW {}
13244 }
13245 #[doc = "Nominal Resynchronization Jump Width"]
13246 pub mod NRJW {
13247 pub const offset: u32 = 22;
13248 pub const mask: u32 = 0x7f << offset;
13249 pub mod R {}
13250 pub mod W {}
13251 pub mod RW {}
13252 }
13253}
13254#[doc = "Enhanced Data Phase CAN bit Timing"]
13255pub mod EDCBT {
13256 #[doc = "Data Phase Segment 1"]
13257 pub mod DTSEG1 {
13258 pub const offset: u32 = 0;
13259 pub const mask: u32 = 0x1f << offset;
13260 pub mod R {}
13261 pub mod W {}
13262 pub mod RW {}
13263 }
13264 #[doc = "Data Phase Time Segment 2"]
13265 pub mod DTSEG2 {
13266 pub const offset: u32 = 12;
13267 pub const mask: u32 = 0x0f << offset;
13268 pub mod R {}
13269 pub mod W {}
13270 pub mod RW {}
13271 }
13272 #[doc = "Data Phase Resynchronization Jump Width"]
13273 pub mod DRJW {
13274 pub const offset: u32 = 22;
13275 pub const mask: u32 = 0x0f << offset;
13276 pub mod R {}
13277 pub mod W {}
13278 pub mod RW {}
13279 }
13280}
13281#[doc = "Enhanced Transceiver Delay Compensation"]
13282pub mod ETDC {
13283 #[doc = "Enhanced Transceiver Delay Compensation Value"]
13284 pub mod ETDCVAL {
13285 pub const offset: u32 = 0;
13286 pub const mask: u32 = 0xff << offset;
13287 pub mod R {}
13288 pub mod W {}
13289 pub mod RW {}
13290 }
13291 #[doc = "Enhanced Transceiver Delay Compensation Offset"]
13292 pub mod ETDCOFF {
13293 pub const offset: u32 = 16;
13294 pub const mask: u32 = 0x7f << offset;
13295 pub mod R {}
13296 pub mod W {}
13297 pub mod RW {}
13298 }
13299 #[doc = "Transceiver Delay Measurement Disable"]
13300 pub mod TDMDIS {
13301 pub const offset: u32 = 31;
13302 pub const mask: u32 = 0x01 << offset;
13303 pub mod R {}
13304 pub mod W {}
13305 pub mod RW {
13306 #[doc = "TDC measurement is enabled"]
13307 pub const TDMDIS_0: u32 = 0;
13308 #[doc = "TDC measurement is disabled"]
13309 pub const TDMDIS_1: u32 = 0x01;
13310 }
13311 }
13312}
13313#[doc = "CAN FD Control Register"]
13314pub mod FDCTRL {
13315 #[doc = "Transceiver Delay Compensation Value"]
13316 pub mod TDCVAL {
13317 pub const offset: u32 = 0;
13318 pub const mask: u32 = 0x3f << offset;
13319 pub mod R {}
13320 pub mod W {}
13321 pub mod RW {}
13322 }
13323 #[doc = "Transceiver Delay Compensation Offset"]
13324 pub mod TDCOFF {
13325 pub const offset: u32 = 8;
13326 pub const mask: u32 = 0x1f << offset;
13327 pub mod R {}
13328 pub mod W {}
13329 pub mod RW {}
13330 }
13331 #[doc = "Transceiver Delay Compensation Fail"]
13332 pub mod TDCFAIL {
13333 pub const offset: u32 = 14;
13334 pub const mask: u32 = 0x01 << offset;
13335 pub mod R {}
13336 pub mod W {}
13337 pub mod RW {
13338 #[doc = "Measured loop delay is in range."]
13339 pub const TDCFAIL_0: u32 = 0;
13340 #[doc = "Measured loop delay is out of range."]
13341 pub const TDCFAIL_1: u32 = 0x01;
13342 }
13343 }
13344 #[doc = "Transceiver Delay Compensation Enable"]
13345 pub mod TDCEN {
13346 pub const offset: u32 = 15;
13347 pub const mask: u32 = 0x01 << offset;
13348 pub mod R {}
13349 pub mod W {}
13350 pub mod RW {
13351 #[doc = "TDC is disabled"]
13352 pub const TDCEN_0: u32 = 0;
13353 #[doc = "TDC is enabled"]
13354 pub const TDCEN_1: u32 = 0x01;
13355 }
13356 }
13357 #[doc = "Message Buffer Data Size for Region 0"]
13358 pub mod MBDSR0 {
13359 pub const offset: u32 = 16;
13360 pub const mask: u32 = 0x03 << offset;
13361 pub mod R {}
13362 pub mod W {}
13363 pub mod RW {
13364 #[doc = "Selects 8 bytes per Message Buffer."]
13365 pub const MBDSR0_0: u32 = 0;
13366 #[doc = "Selects 16 bytes per Message Buffer."]
13367 pub const MBDSR0_1: u32 = 0x01;
13368 #[doc = "Selects 32 bytes per Message Buffer."]
13369 pub const MBDSR0_2: u32 = 0x02;
13370 #[doc = "Selects 64 bytes per Message Buffer."]
13371 pub const MBDSR0_3: u32 = 0x03;
13372 }
13373 }
13374 #[doc = "Message Buffer Data Size for Region 1"]
13375 pub mod MBDSR1 {
13376 pub const offset: u32 = 19;
13377 pub const mask: u32 = 0x03 << offset;
13378 pub mod R {}
13379 pub mod W {}
13380 pub mod RW {
13381 #[doc = "Selects 8 bytes per Message Buffer."]
13382 pub const MBDSR1_0: u32 = 0;
13383 #[doc = "Selects 16 bytes per Message Buffer."]
13384 pub const MBDSR1_1: u32 = 0x01;
13385 #[doc = "Selects 32 bytes per Message Buffer."]
13386 pub const MBDSR1_2: u32 = 0x02;
13387 #[doc = "Selects 64 bytes per Message Buffer."]
13388 pub const MBDSR1_3: u32 = 0x03;
13389 }
13390 }
13391 #[doc = "Bit Rate Switch Enable"]
13392 pub mod FDRATE {
13393 pub const offset: u32 = 31;
13394 pub const mask: u32 = 0x01 << offset;
13395 pub mod R {}
13396 pub mod W {}
13397 pub mod RW {
13398 #[doc = "Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect."]
13399 pub const FDRATE_0: u32 = 0;
13400 #[doc = "Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive."]
13401 pub const FDRATE_1: u32 = 0x01;
13402 }
13403 }
13404}
13405#[doc = "CAN FD Bit Timing Register"]
13406pub mod FDCBT {
13407 #[doc = "Fast Phase Segment 2"]
13408 pub mod FPSEG2 {
13409 pub const offset: u32 = 0;
13410 pub const mask: u32 = 0x07 << offset;
13411 pub mod R {}
13412 pub mod W {}
13413 pub mod RW {}
13414 }
13415 #[doc = "Fast Phase Segment 1"]
13416 pub mod FPSEG1 {
13417 pub const offset: u32 = 5;
13418 pub const mask: u32 = 0x07 << offset;
13419 pub mod R {}
13420 pub mod W {}
13421 pub mod RW {}
13422 }
13423 #[doc = "Fast Propagation Segment"]
13424 pub mod FPROPSEG {
13425 pub const offset: u32 = 10;
13426 pub const mask: u32 = 0x1f << offset;
13427 pub mod R {}
13428 pub mod W {}
13429 pub mod RW {}
13430 }
13431 #[doc = "Fast Resync Jump Width"]
13432 pub mod FRJW {
13433 pub const offset: u32 = 16;
13434 pub const mask: u32 = 0x07 << offset;
13435 pub mod R {}
13436 pub mod W {}
13437 pub mod RW {}
13438 }
13439 #[doc = "Fast Prescaler Division Factor"]
13440 pub mod FPRESDIV {
13441 pub const offset: u32 = 20;
13442 pub const mask: u32 = 0x03ff << offset;
13443 pub mod R {}
13444 pub mod W {}
13445 pub mod RW {}
13446 }
13447}
13448#[doc = "CAN FD CRC Register"]
13449pub mod FDCRC {
13450 #[doc = "Extended Transmitted CRC value"]
13451 pub mod FD_TXCRC {
13452 pub const offset: u32 = 0;
13453 pub const mask: u32 = 0x001f_ffff << offset;
13454 pub mod R {}
13455 pub mod W {}
13456 pub mod RW {}
13457 }
13458 #[doc = "CRC Mailbox Number for FD_TXCRC"]
13459 pub mod FD_MBCRC {
13460 pub const offset: u32 = 24;
13461 pub const mask: u32 = 0x7f << offset;
13462 pub mod R {}
13463 pub mod W {}
13464 pub mod RW {}
13465 }
13466}
13467#[doc = "Enhanced Rx FIFO Control Register"]
13468pub mod ERFCR {
13469 #[doc = "Enhanced Rx FIFO Watermark"]
13470 pub mod ERFWM {
13471 pub const offset: u32 = 0;
13472 pub const mask: u32 = 0x1f << offset;
13473 pub mod R {}
13474 pub mod W {}
13475 pub mod RW {}
13476 }
13477 #[doc = "Number of Enhanced Rx FIFO Filter Elements"]
13478 pub mod NFE {
13479 pub const offset: u32 = 8;
13480 pub const mask: u32 = 0x3f << offset;
13481 pub mod R {}
13482 pub mod W {}
13483 pub mod RW {}
13484 }
13485 #[doc = "Number of Extended ID Filter Elements"]
13486 pub mod NEXIF {
13487 pub const offset: u32 = 16;
13488 pub const mask: u32 = 0x7f << offset;
13489 pub mod R {}
13490 pub mod W {}
13491 pub mod RW {}
13492 }
13493 #[doc = "DMA Last Word"]
13494 pub mod DMALW {
13495 pub const offset: u32 = 26;
13496 pub const mask: u32 = 0x1f << offset;
13497 pub mod R {}
13498 pub mod W {}
13499 pub mod RW {}
13500 }
13501 #[doc = "Enhanced Rx FIFO enable"]
13502 pub mod ERFEN {
13503 pub const offset: u32 = 31;
13504 pub const mask: u32 = 0x01 << offset;
13505 pub mod R {}
13506 pub mod W {}
13507 pub mod RW {
13508 #[doc = "Enhanced Rx FIFO is disabled"]
13509 pub const ERFEN_0: u32 = 0;
13510 #[doc = "Enhanced Rx FIFO is enabled"]
13511 pub const ERFEN_1: u32 = 0x01;
13512 }
13513 }
13514}
13515#[doc = "Enhanced Rx FIFO Interrupt Enable register"]
13516pub mod ERFIER {
13517 #[doc = "Enhanced Rx FIFO Data Available Interrupt Enable"]
13518 pub mod ERFDAIE {
13519 pub const offset: u32 = 28;
13520 pub const mask: u32 = 0x01 << offset;
13521 pub mod R {}
13522 pub mod W {}
13523 pub mod RW {
13524 #[doc = "Enhanced Rx FIFO Data Available Interrupt is disabled"]
13525 pub const ERFDAIE_0: u32 = 0;
13526 #[doc = "Enhanced Rx FIFO Data Available Interrupt is enabled"]
13527 pub const ERFDAIE_1: u32 = 0x01;
13528 }
13529 }
13530 #[doc = "Enhanced Rx FIFO Watermark Indication Interrupt Enable"]
13531 pub mod ERFWMIIE {
13532 pub const offset: u32 = 29;
13533 pub const mask: u32 = 0x01 << offset;
13534 pub mod R {}
13535 pub mod W {}
13536 pub mod RW {
13537 #[doc = "Enhanced Rx FIFO Watermark Interrupt is disabled"]
13538 pub const ERFWMIIE_0: u32 = 0;
13539 #[doc = "Enhanced Rx FIFO Watermark Interrupt is enabled"]
13540 pub const ERFWMIIE_1: u32 = 0x01;
13541 }
13542 }
13543 #[doc = "Enhanced Rx FIFO Overflow Interrupt Enable"]
13544 pub mod ERFOVFIE {
13545 pub const offset: u32 = 30;
13546 pub const mask: u32 = 0x01 << offset;
13547 pub mod R {}
13548 pub mod W {}
13549 pub mod RW {
13550 #[doc = "Enhanced Rx FIFO Overflow is disabled"]
13551 pub const ERFOVFIE_0: u32 = 0;
13552 #[doc = "Enhanced Rx FIFO Overflow is enabled"]
13553 pub const ERFOVFIE_1: u32 = 0x01;
13554 }
13555 }
13556 #[doc = "Enhanced Rx FIFO Underflow Interrupt Enable"]
13557 pub mod ERFUFWIE {
13558 pub const offset: u32 = 31;
13559 pub const mask: u32 = 0x01 << offset;
13560 pub mod R {}
13561 pub mod W {}
13562 pub mod RW {
13563 #[doc = "Enhanced Rx FIFO Underflow interrupt is disabled"]
13564 pub const ERFUFWIE_0: u32 = 0;
13565 #[doc = "Enhanced Rx FIFO Underflow interrupt is enabled"]
13566 pub const ERFUFWIE_1: u32 = 0x01;
13567 }
13568 }
13569}
13570#[doc = "Enhanced Rx FIFO Status Register"]
13571pub mod ERFSR {
13572 #[doc = "Enhanced Rx FIFO Elements"]
13573 pub mod ERFEL {
13574 pub const offset: u32 = 0;
13575 pub const mask: u32 = 0x3f << offset;
13576 pub mod R {}
13577 pub mod W {}
13578 pub mod RW {}
13579 }
13580 #[doc = "Enhanced Rx FIFO full"]
13581 pub mod ERFF {
13582 pub const offset: u32 = 16;
13583 pub const mask: u32 = 0x01 << offset;
13584 pub mod R {}
13585 pub mod W {}
13586 pub mod RW {
13587 #[doc = "Enhanced Rx FIFO is not full"]
13588 pub const ERFF_0: u32 = 0;
13589 #[doc = "Enhanced Rx FIFO is full"]
13590 pub const ERFF_1: u32 = 0x01;
13591 }
13592 }
13593 #[doc = "Enhanced Rx FIFO empty"]
13594 pub mod ERFE {
13595 pub const offset: u32 = 17;
13596 pub const mask: u32 = 0x01 << offset;
13597 pub mod R {}
13598 pub mod W {}
13599 pub mod RW {
13600 #[doc = "Enhanced Rx FIFO is not empty"]
13601 pub const ERFE_0: u32 = 0;
13602 #[doc = "Enhanced Rx FIFO is empty"]
13603 pub const ERFE_1: u32 = 0x01;
13604 }
13605 }
13606 #[doc = "Enhanced Rx FIFO Clear"]
13607 pub mod ERFCLR {
13608 pub const offset: u32 = 27;
13609 pub const mask: u32 = 0x01 << offset;
13610 pub mod R {}
13611 pub mod W {}
13612 pub mod RW {
13613 #[doc = "No effect"]
13614 pub const ERFCLR_0: u32 = 0;
13615 #[doc = "Clear Enhanced Rx FIFO content"]
13616 pub const ERFCLR_1: u32 = 0x01;
13617 }
13618 }
13619 #[doc = "Enhanced Rx FIFO Data Available"]
13620 pub mod ERFDA {
13621 pub const offset: u32 = 28;
13622 pub const mask: u32 = 0x01 << offset;
13623 pub mod R {}
13624 pub mod W {}
13625 pub mod RW {
13626 #[doc = "No such occurrence"]
13627 pub const ERFDA_0: u32 = 0;
13628 #[doc = "There is at least one message stored in Enhanced Rx FIFO"]
13629 pub const ERFDA_1: u32 = 0x01;
13630 }
13631 }
13632 #[doc = "Enhanced Rx FIFO Watermark Indication"]
13633 pub mod ERFWMI {
13634 pub const offset: u32 = 29;
13635 pub const mask: u32 = 0x01 << offset;
13636 pub mod R {}
13637 pub mod W {}
13638 pub mod RW {
13639 #[doc = "No such occurrence"]
13640 pub const ERFWMI_0: u32 = 0;
13641 #[doc = "The number of messages in FIFO is greater than the watermark"]
13642 pub const ERFWMI_1: u32 = 0x01;
13643 }
13644 }
13645 #[doc = "Enhanced Rx FIFO Overflow"]
13646 pub mod ERFOVF {
13647 pub const offset: u32 = 30;
13648 pub const mask: u32 = 0x01 << offset;
13649 pub mod R {}
13650 pub mod W {}
13651 pub mod RW {
13652 #[doc = "No such occurrence"]
13653 pub const ERFOVF_0: u32 = 0;
13654 #[doc = "Enhanced Rx FIFO overflow"]
13655 pub const ERFOVF_1: u32 = 0x01;
13656 }
13657 }
13658 #[doc = "Enhanced Rx FIFO Underflow"]
13659 pub mod ERFUFW {
13660 pub const offset: u32 = 31;
13661 pub const mask: u32 = 0x01 << offset;
13662 pub mod R {}
13663 pub mod W {}
13664 pub mod RW {
13665 #[doc = "No such occurrence"]
13666 pub const ERFUFW_0: u32 = 0;
13667 #[doc = "Enhanced Rx FIFO underflow"]
13668 pub const ERFUFW_1: u32 = 0x01;
13669 }
13670 }
13671}
13672#[doc = "High Resolution Time Stamp"]
13673pub mod HR_TIME_STAMP {
13674 #[doc = "High Resolution Time Stamp"]
13675 pub mod TS {
13676 pub const offset: u32 = 0;
13677 pub const mask: u32 = 0xffff_ffff << offset;
13678 pub mod R {}
13679 pub mod W {}
13680 pub mod RW {}
13681 }
13682}
13683#[doc = "Enhanced Rx FIFO Filter Element"]
13684pub mod ERFFEL {
13685 #[doc = "Filter Element Bits"]
13686 pub mod FEL {
13687 pub const offset: u32 = 0;
13688 pub const mask: u32 = 0xffff_ffff << offset;
13689 pub mod R {}
13690 pub mod W {}
13691 pub mod RW {}
13692 }
13693}