imxrt_ral/blocks/imxrt1061/
ccm.rs

1#[doc = "CCM"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "CCM Control Register"]
5    pub CCR: crate::RWRegister<u32>,
6    _reserved0: [u8; 0x04],
7    #[doc = "CCM Status Register"]
8    pub CSR: crate::RORegister<u32>,
9    #[doc = "CCM Clock Switcher Register"]
10    pub CCSR: crate::RWRegister<u32>,
11    #[doc = "CCM Arm Clock Root Register"]
12    pub CACRR: crate::RWRegister<u32>,
13    #[doc = "CCM Bus Clock Divider Register"]
14    pub CBCDR: crate::RWRegister<u32>,
15    #[doc = "CCM Bus Clock Multiplexer Register"]
16    pub CBCMR: crate::RWRegister<u32>,
17    #[doc = "CCM Serial Clock Multiplexer Register 1"]
18    pub CSCMR1: crate::RWRegister<u32>,
19    #[doc = "CCM Serial Clock Multiplexer Register 2"]
20    pub CSCMR2: crate::RWRegister<u32>,
21    #[doc = "CCM Serial Clock Divider Register 1"]
22    pub CSCDR1: crate::RWRegister<u32>,
23    #[doc = "CCM Clock Divider Register"]
24    pub CS1CDR: crate::RWRegister<u32>,
25    #[doc = "CCM Clock Divider Register"]
26    pub CS2CDR: crate::RWRegister<u32>,
27    #[doc = "CCM D1 Clock Divider Register"]
28    pub CDCDR: crate::RWRegister<u32>,
29    _reserved1: [u8; 0x04],
30    #[doc = "CCM Serial Clock Divider Register 2"]
31    pub CSCDR2: crate::RWRegister<u32>,
32    #[doc = "CCM Serial Clock Divider Register 3"]
33    pub CSCDR3: crate::RWRegister<u32>,
34    _reserved2: [u8; 0x08],
35    #[doc = "CCM Divider Handshake In-Process Register"]
36    pub CDHIPR: crate::RORegister<u32>,
37    _reserved3: [u8; 0x08],
38    #[doc = "CCM Low Power Control Register"]
39    pub CLPCR: crate::RWRegister<u32>,
40    #[doc = "CCM Interrupt Status Register"]
41    pub CISR: crate::RWRegister<u32>,
42    #[doc = "CCM Interrupt Mask Register"]
43    pub CIMR: crate::RWRegister<u32>,
44    #[doc = "CCM Clock Output Source Register"]
45    pub CCOSR: crate::RWRegister<u32>,
46    #[doc = "CCM General Purpose Register"]
47    pub CGPR: crate::RWRegister<u32>,
48    #[doc = "CCM Clock Gating Register 0"]
49    pub CCGR0: crate::RWRegister<u32>,
50    #[doc = "CCM Clock Gating Register 1"]
51    pub CCGR1: crate::RWRegister<u32>,
52    #[doc = "CCM Clock Gating Register 2"]
53    pub CCGR2: crate::RWRegister<u32>,
54    #[doc = "CCM Clock Gating Register 3"]
55    pub CCGR3: crate::RWRegister<u32>,
56    #[doc = "CCM Clock Gating Register 4"]
57    pub CCGR4: crate::RWRegister<u32>,
58    #[doc = "CCM Clock Gating Register 5"]
59    pub CCGR5: crate::RWRegister<u32>,
60    #[doc = "CCM Clock Gating Register 6"]
61    pub CCGR6: crate::RWRegister<u32>,
62    #[doc = "CCM Clock Gating Register 7"]
63    pub CCGR7: crate::RWRegister<u32>,
64    #[doc = "CCM Module Enable Overide Register"]
65    pub CMEOR: crate::RWRegister<u32>,
66}
67#[doc = "CCM Control Register"]
68pub mod CCR {
69    #[doc = "Oscillator ready counter value. These bits define value of 32KHz counter, that serve as counter for oscillator lock time (count to n+1 ckil's). This is used for oscillator lock time. Current estimation is ~5ms. This counter will be used in ignition sequence and in wake from stop sequence if sbyos bit was defined, to notify that on chip oscillator output is ready for the dpll_ip to use and only then the gate in dpll_ip can be opened."]
70    pub mod OSCNT {
71        pub const offset: u32 = 0;
72        pub const mask: u32 = 0xff << offset;
73        pub mod R {}
74        pub mod W {}
75        pub mod RW {}
76    }
77    #[doc = "On chip oscillator enable bit - this bit value is reflected on the output cosc_en"]
78    pub mod COSC_EN {
79        pub const offset: u32 = 12;
80        pub const mask: u32 = 0x01 << offset;
81        pub mod R {}
82        pub mod W {}
83        pub mod RW {
84            #[doc = "disable on chip oscillator"]
85            pub const COSC_EN_0: u32 = 0;
86            #[doc = "enable on chip oscillator"]
87            pub const COSC_EN_1: u32 = 0x01;
88        }
89    }
90    #[doc = "Counter for analog_reg_bypass signal assertion after standby voltage request by PMIC_STBY_REQ"]
91    pub mod REG_BYPASS_COUNT {
92        pub const offset: u32 = 21;
93        pub const mask: u32 = 0x3f << offset;
94        pub mod R {}
95        pub mod W {}
96        pub mod RW {
97            #[doc = "no delay"]
98            pub const REG_BYPASS_COUNT_0: u32 = 0;
99            #[doc = "1 CKIL clock period delay"]
100            pub const REG_BYPASS_COUNT_1: u32 = 0x01;
101            #[doc = "63 CKIL clock periods delay"]
102            pub const REG_BYPASS_COUNT_63: u32 = 0x3f;
103        }
104    }
105    #[doc = "Enable for REG_BYPASS_COUNTER"]
106    pub mod RBC_EN {
107        pub const offset: u32 = 27;
108        pub const mask: u32 = 0x01 << offset;
109        pub mod R {}
110        pub mod W {}
111        pub mod RW {
112            #[doc = "REG_BYPASS_COUNTER disabled"]
113            pub const RBC_EN_0: u32 = 0;
114            #[doc = "REG_BYPASS_COUNTER enabled."]
115            pub const RBC_EN_1: u32 = 0x01;
116        }
117    }
118}
119#[doc = "CCM Status Register"]
120pub mod CSR {
121    #[doc = "Status of the value of CCM_REF_EN_B output of ccm"]
122    pub mod REF_EN_B {
123        pub const offset: u32 = 0;
124        pub const mask: u32 = 0x01 << offset;
125        pub mod R {}
126        pub mod W {}
127        pub mod RW {
128            #[doc = "value of CCM_REF_EN_B is '0'"]
129            pub const REF_EN_B_0: u32 = 0;
130            #[doc = "value of CCM_REF_EN_B is '1'"]
131            pub const REF_EN_B_1: u32 = 0x01;
132        }
133    }
134    #[doc = "Status indication of CAMP2."]
135    pub mod CAMP2_READY {
136        pub const offset: u32 = 3;
137        pub const mask: u32 = 0x01 << offset;
138        pub mod R {}
139        pub mod W {}
140        pub mod RW {
141            #[doc = "CAMP2 is not ready."]
142            pub const CAMP2_READY_0: u32 = 0;
143            #[doc = "CAMP2 is ready."]
144            pub const CAMP2_READY_1: u32 = 0x01;
145        }
146    }
147    #[doc = "Status indication of on board oscillator"]
148    pub mod COSC_READY {
149        pub const offset: u32 = 5;
150        pub const mask: u32 = 0x01 << offset;
151        pub mod R {}
152        pub mod W {}
153        pub mod RW {
154            #[doc = "on board oscillator is not ready."]
155            pub const COSC_READY_0: u32 = 0;
156            #[doc = "on board oscillator is ready."]
157            pub const COSC_READY_1: u32 = 0x01;
158        }
159    }
160}
161#[doc = "CCM Clock Switcher Register"]
162pub mod CCSR {
163    #[doc = "Selects source to generate pll3_sw_clk. This bit should only be used for testing purposes."]
164    pub mod PLL3_SW_CLK_SEL {
165        pub const offset: u32 = 0;
166        pub const mask: u32 = 0x01 << offset;
167        pub mod R {}
168        pub mod W {}
169        pub mod RW {
170            #[doc = "pll3_main_clk"]
171            pub const PLL3_SW_CLK_SEL_0: u32 = 0;
172            #[doc = "pll3 bypass clock"]
173            pub const PLL3_SW_CLK_SEL_1: u32 = 0x01;
174        }
175    }
176}
177#[doc = "CCM Arm Clock Root Register"]
178pub mod CACRR {
179    #[doc = "Divider for ARM clock root"]
180    pub mod ARM_PODF {
181        pub const offset: u32 = 0;
182        pub const mask: u32 = 0x07 << offset;
183        pub mod R {}
184        pub mod W {}
185        pub mod RW {
186            #[doc = "divide by 1"]
187            pub const ARM_PODF_0: u32 = 0;
188            #[doc = "divide by 2"]
189            pub const ARM_PODF_1: u32 = 0x01;
190            #[doc = "divide by 3"]
191            pub const ARM_PODF_2: u32 = 0x02;
192            #[doc = "divide by 4"]
193            pub const ARM_PODF_3: u32 = 0x03;
194            #[doc = "divide by 5"]
195            pub const ARM_PODF_4: u32 = 0x04;
196            #[doc = "divide by 6"]
197            pub const ARM_PODF_5: u32 = 0x05;
198            #[doc = "divide by 7"]
199            pub const ARM_PODF_6: u32 = 0x06;
200            #[doc = "divide by 8"]
201            pub const ARM_PODF_7: u32 = 0x07;
202        }
203    }
204}
205#[doc = "CCM Bus Clock Divider Register"]
206pub mod CBCDR {
207    #[doc = "SEMC clock source select"]
208    pub mod SEMC_CLK_SEL {
209        pub const offset: u32 = 6;
210        pub const mask: u32 = 0x01 << offset;
211        pub mod R {}
212        pub mod W {}
213        pub mod RW {
214            #[doc = "Periph_clk output will be used as SEMC clock root"]
215            pub const SEMC_CLK_SEL_0: u32 = 0;
216            #[doc = "SEMC alternative clock will be used as SEMC clock root"]
217            pub const SEMC_CLK_SEL_1: u32 = 0x01;
218        }
219    }
220    #[doc = "SEMC alternative clock select"]
221    pub mod SEMC_ALT_CLK_SEL {
222        pub const offset: u32 = 7;
223        pub const mask: u32 = 0x01 << offset;
224        pub mod R {}
225        pub mod W {}
226        pub mod RW {
227            #[doc = "PLL2 PFD2 will be selected as alternative clock for SEMC root clock"]
228            pub const SEMC_ALT_CLK_SEL_0: u32 = 0;
229            #[doc = "PLL3 PFD1 will be selected as alternative clock for SEMC root clock"]
230            pub const SEMC_ALT_CLK_SEL_1: u32 = 0x01;
231        }
232    }
233    #[doc = "Divider for ipg podf."]
234    pub mod IPG_PODF {
235        pub const offset: u32 = 8;
236        pub const mask: u32 = 0x03 << offset;
237        pub mod R {}
238        pub mod W {}
239        pub mod RW {
240            #[doc = "divide by 1"]
241            pub const IPG_PODF_0: u32 = 0;
242            #[doc = "divide by 2"]
243            pub const IPG_PODF_1: u32 = 0x01;
244            #[doc = "divide by 3"]
245            pub const IPG_PODF_2: u32 = 0x02;
246            #[doc = "divide by 4"]
247            pub const IPG_PODF_3: u32 = 0x03;
248        }
249    }
250    #[doc = "Divider for AHB PODF"]
251    pub mod AHB_PODF {
252        pub const offset: u32 = 10;
253        pub const mask: u32 = 0x07 << offset;
254        pub mod R {}
255        pub mod W {}
256        pub mod RW {
257            #[doc = "divide by 1"]
258            pub const AHB_PODF_0: u32 = 0;
259            #[doc = "divide by 2"]
260            pub const AHB_PODF_1: u32 = 0x01;
261            #[doc = "divide by 3"]
262            pub const AHB_PODF_2: u32 = 0x02;
263            #[doc = "divide by 4"]
264            pub const AHB_PODF_3: u32 = 0x03;
265            #[doc = "divide by 5"]
266            pub const AHB_PODF_4: u32 = 0x04;
267            #[doc = "divide by 6"]
268            pub const AHB_PODF_5: u32 = 0x05;
269            #[doc = "divide by 7"]
270            pub const AHB_PODF_6: u32 = 0x06;
271            #[doc = "divide by 8"]
272            pub const AHB_PODF_7: u32 = 0x07;
273        }
274    }
275    #[doc = "Post divider for SEMC clock"]
276    pub mod SEMC_PODF {
277        pub const offset: u32 = 16;
278        pub const mask: u32 = 0x07 << offset;
279        pub mod R {}
280        pub mod W {}
281        pub mod RW {
282            #[doc = "divide by 1"]
283            pub const SEMC_PODF_0: u32 = 0;
284            #[doc = "divide by 2"]
285            pub const SEMC_PODF_1: u32 = 0x01;
286            #[doc = "divide by 3"]
287            pub const SEMC_PODF_2: u32 = 0x02;
288            #[doc = "divide by 4"]
289            pub const SEMC_PODF_3: u32 = 0x03;
290            #[doc = "divide by 5"]
291            pub const SEMC_PODF_4: u32 = 0x04;
292            #[doc = "divide by 6"]
293            pub const SEMC_PODF_5: u32 = 0x05;
294            #[doc = "divide by 7"]
295            pub const SEMC_PODF_6: u32 = 0x06;
296            #[doc = "divide by 8"]
297            pub const SEMC_PODF_7: u32 = 0x07;
298        }
299    }
300    #[doc = "Selector for peripheral main clock"]
301    pub mod PERIPH_CLK_SEL {
302        pub const offset: u32 = 25;
303        pub const mask: u32 = 0x01 << offset;
304        pub mod R {}
305        pub mod W {}
306        pub mod RW {
307            #[doc = "derive clock selected by CCM_CBCMR\\[CORE_CLK_PRE_SEL\\]"]
308            pub const PERIPH_CLK_SEL_0: u32 = 0;
309            #[doc = "derive clock selected by CCM_CBCMR\\[PERIPH_CLK2_SEL\\]"]
310            pub const PERIPH_CLK_SEL_1: u32 = 0x01;
311        }
312    }
313    #[doc = "Divider for periph_clk2_podf."]
314    pub mod PERIPH_CLK2_PODF {
315        pub const offset: u32 = 27;
316        pub const mask: u32 = 0x07 << offset;
317        pub mod R {}
318        pub mod W {}
319        pub mod RW {
320            #[doc = "divide by 1"]
321            pub const PERIPH_CLK2_PODF_0: u32 = 0;
322            #[doc = "divide by 2"]
323            pub const PERIPH_CLK2_PODF_1: u32 = 0x01;
324            #[doc = "divide by 3"]
325            pub const PERIPH_CLK2_PODF_2: u32 = 0x02;
326            #[doc = "divide by 4"]
327            pub const PERIPH_CLK2_PODF_3: u32 = 0x03;
328            #[doc = "divide by 5"]
329            pub const PERIPH_CLK2_PODF_4: u32 = 0x04;
330            #[doc = "divide by 6"]
331            pub const PERIPH_CLK2_PODF_5: u32 = 0x05;
332            #[doc = "divide by 7"]
333            pub const PERIPH_CLK2_PODF_6: u32 = 0x06;
334            #[doc = "divide by 8"]
335            pub const PERIPH_CLK2_PODF_7: u32 = 0x07;
336        }
337    }
338}
339#[doc = "CCM Bus Clock Multiplexer Register"]
340pub mod CBCMR {
341    #[doc = "Selector for lpspi clock multiplexer"]
342    pub mod LPSPI_CLK_SEL {
343        pub const offset: u32 = 4;
344        pub const mask: u32 = 0x03 << offset;
345        pub mod R {}
346        pub mod W {}
347        pub mod RW {
348            #[doc = "derive clock from PLL3 PFD1 clk"]
349            pub const LPSPI_CLK_SEL_0: u32 = 0;
350            #[doc = "derive clock from PLL3 PFD0"]
351            pub const LPSPI_CLK_SEL_1: u32 = 0x01;
352            #[doc = "derive clock from PLL2"]
353            pub const LPSPI_CLK_SEL_2: u32 = 0x02;
354            #[doc = "derive clock from PLL2 PFD2"]
355            pub const LPSPI_CLK_SEL_3: u32 = 0x03;
356        }
357    }
358    #[doc = "Selector for flexspi2 clock multiplexer"]
359    pub mod FLEXSPI2_CLK_SEL {
360        pub const offset: u32 = 8;
361        pub const mask: u32 = 0x03 << offset;
362        pub mod R {}
363        pub mod W {}
364        pub mod RW {
365            #[doc = "derive clock from PLL2 PFD2"]
366            pub const FLEXSPI2_CLK_SEL_0: u32 = 0;
367            #[doc = "derive clock from PLL3 PFD0"]
368            pub const FLEXSPI2_CLK_SEL_1: u32 = 0x01;
369            #[doc = "derive clock from PLL3 PFD1"]
370            pub const FLEXSPI2_CLK_SEL_2: u32 = 0x02;
371            #[doc = "derive clock from PLL2 (pll2_main_clk)"]
372            pub const FLEXSPI2_CLK_SEL_3: u32 = 0x03;
373        }
374    }
375    #[doc = "Selector for peripheral clk2 clock multiplexer"]
376    pub mod PERIPH_CLK2_SEL {
377        pub const offset: u32 = 12;
378        pub const mask: u32 = 0x03 << offset;
379        pub mod R {}
380        pub mod W {}
381        pub mod RW {
382            #[doc = "derive clock from pll3_sw_clk"]
383            pub const PERIPH_CLK2_SEL_0: u32 = 0;
384            #[doc = "derive clock from osc_clk"]
385            pub const PERIPH_CLK2_SEL_1: u32 = 0x01;
386            #[doc = "derive clock from pll2_bypass_clk"]
387            pub const PERIPH_CLK2_SEL_2: u32 = 0x02;
388        }
389    }
390    #[doc = "Selector for Trace clock multiplexer"]
391    pub mod TRACE_CLK_SEL {
392        pub const offset: u32 = 14;
393        pub const mask: u32 = 0x03 << offset;
394        pub mod R {}
395        pub mod W {}
396        pub mod RW {
397            #[doc = "derive clock from PLL2"]
398            pub const TRACE_CLK_SEL_0: u32 = 0;
399            #[doc = "derive clock from PLL2 PFD2"]
400            pub const TRACE_CLK_SEL_1: u32 = 0x01;
401            #[doc = "derive clock from PLL2 PFD0"]
402            pub const TRACE_CLK_SEL_2: u32 = 0x02;
403            #[doc = "derive clock from PLL2 PFD1"]
404            pub const TRACE_CLK_SEL_3: u32 = 0x03;
405        }
406    }
407    #[doc = "Selector for pre_periph clock multiplexer"]
408    pub mod PRE_PERIPH_CLK_SEL {
409        pub const offset: u32 = 18;
410        pub const mask: u32 = 0x03 << offset;
411        pub mod R {}
412        pub mod W {}
413        pub mod RW {
414            #[doc = "derive clock from PLL2"]
415            pub const PRE_PERIPH_CLK_SEL_0: u32 = 0;
416            #[doc = "derive clock from PLL3 PFD3"]
417            pub const PRE_PERIPH_CLK_SEL_1: u32 = 0x01;
418            #[doc = "derive clock from PLL2 PFD3"]
419            pub const PRE_PERIPH_CLK_SEL_2: u32 = 0x02;
420            #[doc = "derive clock from PLL6"]
421            pub const PRE_PERIPH_CLK_SEL_3: u32 = 0x03;
422        }
423    }
424    #[doc = "Post-divider for LCDIF clock."]
425    pub mod LCDIF_PODF {
426        pub const offset: u32 = 23;
427        pub const mask: u32 = 0x07 << offset;
428        pub mod R {}
429        pub mod W {}
430        pub mod RW {
431            #[doc = "divide by 1"]
432            pub const LCDIF_PODF_0: u32 = 0;
433            #[doc = "divide by 2"]
434            pub const LCDIF_PODF_1: u32 = 0x01;
435            #[doc = "divide by 3"]
436            pub const LCDIF_PODF_2: u32 = 0x02;
437            #[doc = "divide by 4"]
438            pub const LCDIF_PODF_3: u32 = 0x03;
439            #[doc = "divide by 5"]
440            pub const LCDIF_PODF_4: u32 = 0x04;
441            #[doc = "divide by 6"]
442            pub const LCDIF_PODF_5: u32 = 0x05;
443            #[doc = "divide by 7"]
444            pub const LCDIF_PODF_6: u32 = 0x06;
445            #[doc = "divide by 8"]
446            pub const LCDIF_PODF_7: u32 = 0x07;
447        }
448    }
449    #[doc = "Divider for LPSPI. Divider should be updated when output clock is gated."]
450    pub mod LPSPI_PODF {
451        pub const offset: u32 = 26;
452        pub const mask: u32 = 0x07 << offset;
453        pub mod R {}
454        pub mod W {}
455        pub mod RW {
456            #[doc = "divide by 1"]
457            pub const LPSPI_PODF_0: u32 = 0;
458            #[doc = "divide by 2"]
459            pub const LPSPI_PODF_1: u32 = 0x01;
460            #[doc = "divide by 3"]
461            pub const LPSPI_PODF_2: u32 = 0x02;
462            #[doc = "divide by 4"]
463            pub const LPSPI_PODF_3: u32 = 0x03;
464            #[doc = "divide by 5"]
465            pub const LPSPI_PODF_4: u32 = 0x04;
466            #[doc = "divide by 6"]
467            pub const LPSPI_PODF_5: u32 = 0x05;
468            #[doc = "divide by 7"]
469            pub const LPSPI_PODF_6: u32 = 0x06;
470            #[doc = "divide by 8"]
471            pub const LPSPI_PODF_7: u32 = 0x07;
472        }
473    }
474    #[doc = "Divider for flexspi2 clock root."]
475    pub mod FLEXSPI2_PODF {
476        pub const offset: u32 = 29;
477        pub const mask: u32 = 0x07 << offset;
478        pub mod R {}
479        pub mod W {}
480        pub mod RW {
481            #[doc = "divide by 1"]
482            pub const FLEXSPI2_PODF_0: u32 = 0;
483            #[doc = "divide by 2"]
484            pub const FLEXSPI2_PODF_1: u32 = 0x01;
485            #[doc = "divide by 3"]
486            pub const FLEXSPI2_PODF_2: u32 = 0x02;
487            #[doc = "divide by 4"]
488            pub const FLEXSPI2_PODF_3: u32 = 0x03;
489            #[doc = "divide by 5"]
490            pub const FLEXSPI2_PODF_4: u32 = 0x04;
491            #[doc = "divide by 6"]
492            pub const FLEXSPI2_PODF_5: u32 = 0x05;
493            #[doc = "divide by 7"]
494            pub const FLEXSPI2_PODF_6: u32 = 0x06;
495            #[doc = "divide by 8"]
496            pub const FLEXSPI2_PODF_7: u32 = 0x07;
497        }
498    }
499}
500#[doc = "CCM Serial Clock Multiplexer Register 1"]
501pub mod CSCMR1 {
502    #[doc = "Divider for perclk podf."]
503    pub mod PERCLK_PODF {
504        pub const offset: u32 = 0;
505        pub const mask: u32 = 0x3f << offset;
506        pub mod R {}
507        pub mod W {}
508        pub mod RW {
509            #[doc = "Divide by 1"]
510            pub const DIVIDE_1: u32 = 0;
511            #[doc = "Divide by 2"]
512            pub const DIVIDE_2: u32 = 0x01;
513            #[doc = "Divide by 3"]
514            pub const DIVIDE_3: u32 = 0x02;
515            #[doc = "Divide by 4"]
516            pub const DIVIDE_4: u32 = 0x03;
517            #[doc = "Divide by 5"]
518            pub const DIVIDE_5: u32 = 0x04;
519            #[doc = "Divide by 6"]
520            pub const DIVIDE_6: u32 = 0x05;
521            #[doc = "Divide by 7"]
522            pub const DIVIDE_7: u32 = 0x06;
523            #[doc = "Divide by 8"]
524            pub const DIVIDE_8: u32 = 0x07;
525            #[doc = "Divide by 9"]
526            pub const DIVIDE_9: u32 = 0x08;
527            #[doc = "Divide by 10"]
528            pub const DIVIDE_10: u32 = 0x09;
529            #[doc = "Divide by 11"]
530            pub const DIVIDE_11: u32 = 0x0a;
531            #[doc = "Divide by 12"]
532            pub const DIVIDE_12: u32 = 0x0b;
533            #[doc = "Divide by 13"]
534            pub const DIVIDE_13: u32 = 0x0c;
535            #[doc = "Divide by 14"]
536            pub const DIVIDE_14: u32 = 0x0d;
537            #[doc = "Divide by 15"]
538            pub const DIVIDE_15: u32 = 0x0e;
539            #[doc = "Divide by 16"]
540            pub const DIVIDE_16: u32 = 0x0f;
541            #[doc = "Divide by 17"]
542            pub const DIVIDE_17: u32 = 0x10;
543            #[doc = "Divide by 18"]
544            pub const DIVIDE_18: u32 = 0x11;
545            #[doc = "Divide by 19"]
546            pub const DIVIDE_19: u32 = 0x12;
547            #[doc = "Divide by 20"]
548            pub const DIVIDE_20: u32 = 0x13;
549            #[doc = "Divide by 21"]
550            pub const DIVIDE_21: u32 = 0x14;
551            #[doc = "Divide by 22"]
552            pub const DIVIDE_22: u32 = 0x15;
553            #[doc = "Divide by 23"]
554            pub const DIVIDE_23: u32 = 0x16;
555            #[doc = "Divide by 24"]
556            pub const DIVIDE_24: u32 = 0x17;
557            #[doc = "Divide by 25"]
558            pub const DIVIDE_25: u32 = 0x18;
559            #[doc = "Divide by 26"]
560            pub const DIVIDE_26: u32 = 0x19;
561            #[doc = "Divide by 27"]
562            pub const DIVIDE_27: u32 = 0x1a;
563            #[doc = "Divide by 28"]
564            pub const DIVIDE_28: u32 = 0x1b;
565            #[doc = "Divide by 29"]
566            pub const DIVIDE_29: u32 = 0x1c;
567            #[doc = "Divide by 30"]
568            pub const DIVIDE_30: u32 = 0x1d;
569            #[doc = "Divide by 31"]
570            pub const DIVIDE_31: u32 = 0x1e;
571            #[doc = "Divide by 32"]
572            pub const DIVIDE_32: u32 = 0x1f;
573            #[doc = "Divide by 33"]
574            pub const DIVIDE_33: u32 = 0x20;
575            #[doc = "Divide by 34"]
576            pub const DIVIDE_34: u32 = 0x21;
577            #[doc = "Divide by 35"]
578            pub const DIVIDE_35: u32 = 0x22;
579            #[doc = "Divide by 36"]
580            pub const DIVIDE_36: u32 = 0x23;
581            #[doc = "Divide by 37"]
582            pub const DIVIDE_37: u32 = 0x24;
583            #[doc = "Divide by 38"]
584            pub const DIVIDE_38: u32 = 0x25;
585            #[doc = "Divide by 39"]
586            pub const DIVIDE_39: u32 = 0x26;
587            #[doc = "Divide by 40"]
588            pub const DIVIDE_40: u32 = 0x27;
589            #[doc = "Divide by 41"]
590            pub const DIVIDE_41: u32 = 0x28;
591            #[doc = "Divide by 42"]
592            pub const DIVIDE_42: u32 = 0x29;
593            #[doc = "Divide by 43"]
594            pub const DIVIDE_43: u32 = 0x2a;
595            #[doc = "Divide by 44"]
596            pub const DIVIDE_44: u32 = 0x2b;
597            #[doc = "Divide by 45"]
598            pub const DIVIDE_45: u32 = 0x2c;
599            #[doc = "Divide by 46"]
600            pub const DIVIDE_46: u32 = 0x2d;
601            #[doc = "Divide by 47"]
602            pub const DIVIDE_47: u32 = 0x2e;
603            #[doc = "Divide by 48"]
604            pub const DIVIDE_48: u32 = 0x2f;
605            #[doc = "Divide by 49"]
606            pub const DIVIDE_49: u32 = 0x30;
607            #[doc = "Divide by 50"]
608            pub const DIVIDE_50: u32 = 0x31;
609            #[doc = "Divide by 51"]
610            pub const DIVIDE_51: u32 = 0x32;
611            #[doc = "Divide by 52"]
612            pub const DIVIDE_52: u32 = 0x33;
613            #[doc = "Divide by 53"]
614            pub const DIVIDE_53: u32 = 0x34;
615            #[doc = "Divide by 54"]
616            pub const DIVIDE_54: u32 = 0x35;
617            #[doc = "Divide by 55"]
618            pub const DIVIDE_55: u32 = 0x36;
619            #[doc = "Divide by 56"]
620            pub const DIVIDE_56: u32 = 0x37;
621            #[doc = "Divide by 57"]
622            pub const DIVIDE_57: u32 = 0x38;
623            #[doc = "Divide by 58"]
624            pub const DIVIDE_58: u32 = 0x39;
625            #[doc = "Divide by 59"]
626            pub const DIVIDE_59: u32 = 0x3a;
627            #[doc = "Divide by 60"]
628            pub const DIVIDE_60: u32 = 0x3b;
629            #[doc = "Divide by 61"]
630            pub const DIVIDE_61: u32 = 0x3c;
631            #[doc = "Divide by 62"]
632            pub const DIVIDE_62: u32 = 0x3d;
633            #[doc = "Divide by 63"]
634            pub const DIVIDE_63: u32 = 0x3e;
635            #[doc = "Divide by 64"]
636            pub const DIVIDE_64: u32 = 0x3f;
637        }
638    }
639    #[doc = "Selector for the perclk clock multiplexor"]
640    pub mod PERCLK_CLK_SEL {
641        pub const offset: u32 = 6;
642        pub const mask: u32 = 0x01 << offset;
643        pub mod R {}
644        pub mod W {}
645        pub mod RW {
646            #[doc = "derive clock from ipg clk root"]
647            pub const PERCLK_CLK_SEL_0: u32 = 0;
648            #[doc = "derive clock from osc_clk"]
649            pub const PERCLK_CLK_SEL_1: u32 = 0x01;
650        }
651    }
652    #[doc = "Selector for sai1 clock multiplexer"]
653    pub mod SAI1_CLK_SEL {
654        pub const offset: u32 = 10;
655        pub const mask: u32 = 0x03 << offset;
656        pub mod R {}
657        pub mod W {}
658        pub mod RW {
659            #[doc = "derive clock from PLL3 PFD2"]
660            pub const SAI1_CLK_SEL_0: u32 = 0;
661            #[doc = "derive from pll3_sw_clk"]
662            pub const SAI1_CLK_SEL_1: u32 = 0x01;
663            #[doc = "derive clock from PLL4"]
664            pub const SAI1_CLK_SEL_2: u32 = 0x02;
665        }
666    }
667    #[doc = "Selector for sai2 clock multiplexer"]
668    pub mod SAI2_CLK_SEL {
669        pub const offset: u32 = 12;
670        pub const mask: u32 = 0x03 << offset;
671        pub mod R {}
672        pub mod W {}
673        pub mod RW {
674            #[doc = "derive clock from PLL3 PFD2"]
675            pub const SAI2_CLK_SEL_0: u32 = 0;
676            #[doc = "derive clock from PLL5"]
677            pub const SAI2_CLK_SEL_1: u32 = 0x01;
678            #[doc = "derive clock from PLL4"]
679            pub const SAI2_CLK_SEL_2: u32 = 0x02;
680        }
681    }
682    #[doc = "Selector for sai3 clock multiplexer"]
683    pub mod SAI3_CLK_SEL {
684        pub const offset: u32 = 14;
685        pub const mask: u32 = 0x03 << offset;
686        pub mod R {}
687        pub mod W {}
688        pub mod RW {
689            #[doc = "derive clock from PLL3 PFD2"]
690            pub const SAI3_CLK_SEL_0: u32 = 0;
691            #[doc = "derive from pll3_sw_clk"]
692            pub const SAI3_CLK_SEL_1: u32 = 0x01;
693            #[doc = "derive clock from PLL4"]
694            pub const SAI3_CLK_SEL_2: u32 = 0x02;
695        }
696    }
697    #[doc = "Selector for usdhc1 clock multiplexer"]
698    pub mod USDHC1_CLK_SEL {
699        pub const offset: u32 = 16;
700        pub const mask: u32 = 0x01 << offset;
701        pub mod R {}
702        pub mod W {}
703        pub mod RW {
704            #[doc = "derive clock from PLL2 PFD2"]
705            pub const USDHC1_CLK_SEL_0: u32 = 0;
706            #[doc = "derive clock from PLL2 PFD0"]
707            pub const USDHC1_CLK_SEL_1: u32 = 0x01;
708        }
709    }
710    #[doc = "Selector for usdhc2 clock multiplexer"]
711    pub mod USDHC2_CLK_SEL {
712        pub const offset: u32 = 17;
713        pub const mask: u32 = 0x01 << offset;
714        pub mod R {}
715        pub mod W {}
716        pub mod RW {
717            #[doc = "derive clock from PLL2 PFD2"]
718            pub const USDHC2_CLK_SEL_0: u32 = 0;
719            #[doc = "derive clock from PLL2 PFD0"]
720            pub const USDHC2_CLK_SEL_1: u32 = 0x01;
721        }
722    }
723    #[doc = "Divider for flexspi clock root."]
724    pub mod FLEXSPI_PODF {
725        pub const offset: u32 = 23;
726        pub const mask: u32 = 0x07 << offset;
727        pub mod R {}
728        pub mod W {}
729        pub mod RW {
730            #[doc = "divide by 1"]
731            pub const FLEXSPI_PODF_0: u32 = 0;
732            #[doc = "divide by 2"]
733            pub const FLEXSPI_PODF_1: u32 = 0x01;
734            #[doc = "divide by 3"]
735            pub const FLEXSPI_PODF_2: u32 = 0x02;
736            #[doc = "divide by 4"]
737            pub const FLEXSPI_PODF_3: u32 = 0x03;
738            #[doc = "divide by 5"]
739            pub const FLEXSPI_PODF_4: u32 = 0x04;
740            #[doc = "divide by 6"]
741            pub const FLEXSPI_PODF_5: u32 = 0x05;
742            #[doc = "divide by 7"]
743            pub const FLEXSPI_PODF_6: u32 = 0x06;
744            #[doc = "divide by 8"]
745            pub const FLEXSPI_PODF_7: u32 = 0x07;
746        }
747    }
748    #[doc = "Selector for flexspi clock multiplexer"]
749    pub mod FLEXSPI_CLK_SEL {
750        pub const offset: u32 = 29;
751        pub const mask: u32 = 0x03 << offset;
752        pub mod R {}
753        pub mod W {}
754        pub mod RW {
755            #[doc = "derive clock from PLL2"]
756            pub const FLEXSPI_CLK_SEL_0: u32 = 0;
757            #[doc = "derive clock from pll3_sw_clk"]
758            pub const FLEXSPI_CLK_SEL_1: u32 = 0x01;
759            #[doc = "derive clock from PLL2 PFD2"]
760            pub const FLEXSPI_CLK_SEL_2: u32 = 0x02;
761            #[doc = "derive clock from PLL3 PFD0"]
762            pub const FLEXSPI_CLK_SEL_3: u32 = 0x03;
763        }
764    }
765}
766#[doc = "CCM Serial Clock Multiplexer Register 2"]
767pub mod CSCMR2 {
768    #[doc = "Divider for CAN clock podf."]
769    pub mod CAN_CLK_PODF {
770        pub const offset: u32 = 2;
771        pub const mask: u32 = 0x3f << offset;
772        pub mod R {}
773        pub mod W {}
774        pub mod RW {
775            #[doc = "Divide by 1"]
776            pub const DIVIDE_1: u32 = 0;
777            #[doc = "Divide by 2"]
778            pub const DIVIDE_2: u32 = 0x01;
779            #[doc = "Divide by 3"]
780            pub const DIVIDE_3: u32 = 0x02;
781            #[doc = "Divide by 4"]
782            pub const DIVIDE_4: u32 = 0x03;
783            #[doc = "Divide by 5"]
784            pub const DIVIDE_5: u32 = 0x04;
785            #[doc = "Divide by 6"]
786            pub const DIVIDE_6: u32 = 0x05;
787            #[doc = "Divide by 7"]
788            pub const DIVIDE_7: u32 = 0x06;
789            #[doc = "Divide by 8"]
790            pub const DIVIDE_8: u32 = 0x07;
791            #[doc = "Divide by 9"]
792            pub const DIVIDE_9: u32 = 0x08;
793            #[doc = "Divide by 10"]
794            pub const DIVIDE_10: u32 = 0x09;
795            #[doc = "Divide by 11"]
796            pub const DIVIDE_11: u32 = 0x0a;
797            #[doc = "Divide by 12"]
798            pub const DIVIDE_12: u32 = 0x0b;
799            #[doc = "Divide by 13"]
800            pub const DIVIDE_13: u32 = 0x0c;
801            #[doc = "Divide by 14"]
802            pub const DIVIDE_14: u32 = 0x0d;
803            #[doc = "Divide by 15"]
804            pub const DIVIDE_15: u32 = 0x0e;
805            #[doc = "Divide by 16"]
806            pub const DIVIDE_16: u32 = 0x0f;
807            #[doc = "Divide by 17"]
808            pub const DIVIDE_17: u32 = 0x10;
809            #[doc = "Divide by 18"]
810            pub const DIVIDE_18: u32 = 0x11;
811            #[doc = "Divide by 19"]
812            pub const DIVIDE_19: u32 = 0x12;
813            #[doc = "Divide by 20"]
814            pub const DIVIDE_20: u32 = 0x13;
815            #[doc = "Divide by 21"]
816            pub const DIVIDE_21: u32 = 0x14;
817            #[doc = "Divide by 22"]
818            pub const DIVIDE_22: u32 = 0x15;
819            #[doc = "Divide by 23"]
820            pub const DIVIDE_23: u32 = 0x16;
821            #[doc = "Divide by 24"]
822            pub const DIVIDE_24: u32 = 0x17;
823            #[doc = "Divide by 25"]
824            pub const DIVIDE_25: u32 = 0x18;
825            #[doc = "Divide by 26"]
826            pub const DIVIDE_26: u32 = 0x19;
827            #[doc = "Divide by 27"]
828            pub const DIVIDE_27: u32 = 0x1a;
829            #[doc = "Divide by 28"]
830            pub const DIVIDE_28: u32 = 0x1b;
831            #[doc = "Divide by 29"]
832            pub const DIVIDE_29: u32 = 0x1c;
833            #[doc = "Divide by 30"]
834            pub const DIVIDE_30: u32 = 0x1d;
835            #[doc = "Divide by 31"]
836            pub const DIVIDE_31: u32 = 0x1e;
837            #[doc = "Divide by 32"]
838            pub const DIVIDE_32: u32 = 0x1f;
839            #[doc = "Divide by 33"]
840            pub const DIVIDE_33: u32 = 0x20;
841            #[doc = "Divide by 34"]
842            pub const DIVIDE_34: u32 = 0x21;
843            #[doc = "Divide by 35"]
844            pub const DIVIDE_35: u32 = 0x22;
845            #[doc = "Divide by 36"]
846            pub const DIVIDE_36: u32 = 0x23;
847            #[doc = "Divide by 37"]
848            pub const DIVIDE_37: u32 = 0x24;
849            #[doc = "Divide by 38"]
850            pub const DIVIDE_38: u32 = 0x25;
851            #[doc = "Divide by 39"]
852            pub const DIVIDE_39: u32 = 0x26;
853            #[doc = "Divide by 40"]
854            pub const DIVIDE_40: u32 = 0x27;
855            #[doc = "Divide by 41"]
856            pub const DIVIDE_41: u32 = 0x28;
857            #[doc = "Divide by 42"]
858            pub const DIVIDE_42: u32 = 0x29;
859            #[doc = "Divide by 43"]
860            pub const DIVIDE_43: u32 = 0x2a;
861            #[doc = "Divide by 44"]
862            pub const DIVIDE_44: u32 = 0x2b;
863            #[doc = "Divide by 45"]
864            pub const DIVIDE_45: u32 = 0x2c;
865            #[doc = "Divide by 46"]
866            pub const DIVIDE_46: u32 = 0x2d;
867            #[doc = "Divide by 47"]
868            pub const DIVIDE_47: u32 = 0x2e;
869            #[doc = "Divide by 48"]
870            pub const DIVIDE_48: u32 = 0x2f;
871            #[doc = "Divide by 49"]
872            pub const DIVIDE_49: u32 = 0x30;
873            #[doc = "Divide by 50"]
874            pub const DIVIDE_50: u32 = 0x31;
875            #[doc = "Divide by 51"]
876            pub const DIVIDE_51: u32 = 0x32;
877            #[doc = "Divide by 52"]
878            pub const DIVIDE_52: u32 = 0x33;
879            #[doc = "Divide by 53"]
880            pub const DIVIDE_53: u32 = 0x34;
881            #[doc = "Divide by 54"]
882            pub const DIVIDE_54: u32 = 0x35;
883            #[doc = "Divide by 55"]
884            pub const DIVIDE_55: u32 = 0x36;
885            #[doc = "Divide by 56"]
886            pub const DIVIDE_56: u32 = 0x37;
887            #[doc = "Divide by 57"]
888            pub const DIVIDE_57: u32 = 0x38;
889            #[doc = "Divide by 58"]
890            pub const DIVIDE_58: u32 = 0x39;
891            #[doc = "Divide by 59"]
892            pub const DIVIDE_59: u32 = 0x3a;
893            #[doc = "Divide by 60"]
894            pub const DIVIDE_60: u32 = 0x3b;
895            #[doc = "Divide by 61"]
896            pub const DIVIDE_61: u32 = 0x3c;
897            #[doc = "Divide by 62"]
898            pub const DIVIDE_62: u32 = 0x3d;
899            #[doc = "Divide by 63"]
900            pub const DIVIDE_63: u32 = 0x3e;
901            #[doc = "Divide by 64"]
902            pub const DIVIDE_64: u32 = 0x3f;
903        }
904    }
905    #[doc = "Selector for CAN clock multiplexer"]
906    pub mod CAN_CLK_SEL {
907        pub const offset: u32 = 8;
908        pub const mask: u32 = 0x03 << offset;
909        pub mod R {}
910        pub mod W {}
911        pub mod RW {
912            #[doc = "derive clock from pll3_sw_clk divided clock (60M)"]
913            pub const CAN_CLK_SEL_0: u32 = 0;
914            #[doc = "derive clock from osc_clk (24M)"]
915            pub const CAN_CLK_SEL_1: u32 = 0x01;
916            #[doc = "derive clock from pll3_sw_clk divided clock (80M)"]
917            pub const CAN_CLK_SEL_2: u32 = 0x02;
918            #[doc = "Disable FlexCAN clock"]
919            pub const CAN_CLK_SEL_3: u32 = 0x03;
920        }
921    }
922    #[doc = "Selector for flexio2 clock multiplexer"]
923    pub mod FLEXIO2_CLK_SEL {
924        pub const offset: u32 = 19;
925        pub const mask: u32 = 0x03 << offset;
926        pub mod R {}
927        pub mod W {}
928        pub mod RW {
929            #[doc = "derive clock from PLL4 divided clock"]
930            pub const FLEXIO2_CLK_SEL_0: u32 = 0;
931            #[doc = "derive clock from PLL3 PFD2 clock"]
932            pub const FLEXIO2_CLK_SEL_1: u32 = 0x01;
933            #[doc = "derive clock from PLL5 clock"]
934            pub const FLEXIO2_CLK_SEL_2: u32 = 0x02;
935            #[doc = "derive clock from pll3_sw_clk"]
936            pub const FLEXIO2_CLK_SEL_3: u32 = 0x03;
937        }
938    }
939}
940#[doc = "CCM Serial Clock Divider Register 1"]
941pub mod CSCDR1 {
942    #[doc = "Divider for uart clock podf."]
943    pub mod UART_CLK_PODF {
944        pub const offset: u32 = 0;
945        pub const mask: u32 = 0x3f << offset;
946        pub mod R {}
947        pub mod W {}
948        pub mod RW {
949            #[doc = "Divide by 1"]
950            pub const DIVIDE_1: u32 = 0;
951            #[doc = "Divide by 2"]
952            pub const DIVIDE_2: u32 = 0x01;
953            #[doc = "Divide by 3"]
954            pub const DIVIDE_3: u32 = 0x02;
955            #[doc = "Divide by 4"]
956            pub const DIVIDE_4: u32 = 0x03;
957            #[doc = "Divide by 5"]
958            pub const DIVIDE_5: u32 = 0x04;
959            #[doc = "Divide by 6"]
960            pub const DIVIDE_6: u32 = 0x05;
961            #[doc = "Divide by 7"]
962            pub const DIVIDE_7: u32 = 0x06;
963            #[doc = "Divide by 8"]
964            pub const DIVIDE_8: u32 = 0x07;
965            #[doc = "Divide by 9"]
966            pub const DIVIDE_9: u32 = 0x08;
967            #[doc = "Divide by 10"]
968            pub const DIVIDE_10: u32 = 0x09;
969            #[doc = "Divide by 11"]
970            pub const DIVIDE_11: u32 = 0x0a;
971            #[doc = "Divide by 12"]
972            pub const DIVIDE_12: u32 = 0x0b;
973            #[doc = "Divide by 13"]
974            pub const DIVIDE_13: u32 = 0x0c;
975            #[doc = "Divide by 14"]
976            pub const DIVIDE_14: u32 = 0x0d;
977            #[doc = "Divide by 15"]
978            pub const DIVIDE_15: u32 = 0x0e;
979            #[doc = "Divide by 16"]
980            pub const DIVIDE_16: u32 = 0x0f;
981            #[doc = "Divide by 17"]
982            pub const DIVIDE_17: u32 = 0x10;
983            #[doc = "Divide by 18"]
984            pub const DIVIDE_18: u32 = 0x11;
985            #[doc = "Divide by 19"]
986            pub const DIVIDE_19: u32 = 0x12;
987            #[doc = "Divide by 20"]
988            pub const DIVIDE_20: u32 = 0x13;
989            #[doc = "Divide by 21"]
990            pub const DIVIDE_21: u32 = 0x14;
991            #[doc = "Divide by 22"]
992            pub const DIVIDE_22: u32 = 0x15;
993            #[doc = "Divide by 23"]
994            pub const DIVIDE_23: u32 = 0x16;
995            #[doc = "Divide by 24"]
996            pub const DIVIDE_24: u32 = 0x17;
997            #[doc = "Divide by 25"]
998            pub const DIVIDE_25: u32 = 0x18;
999            #[doc = "Divide by 26"]
1000            pub const DIVIDE_26: u32 = 0x19;
1001            #[doc = "Divide by 27"]
1002            pub const DIVIDE_27: u32 = 0x1a;
1003            #[doc = "Divide by 28"]
1004            pub const DIVIDE_28: u32 = 0x1b;
1005            #[doc = "Divide by 29"]
1006            pub const DIVIDE_29: u32 = 0x1c;
1007            #[doc = "Divide by 30"]
1008            pub const DIVIDE_30: u32 = 0x1d;
1009            #[doc = "Divide by 31"]
1010            pub const DIVIDE_31: u32 = 0x1e;
1011            #[doc = "Divide by 32"]
1012            pub const DIVIDE_32: u32 = 0x1f;
1013            #[doc = "Divide by 33"]
1014            pub const DIVIDE_33: u32 = 0x20;
1015            #[doc = "Divide by 34"]
1016            pub const DIVIDE_34: u32 = 0x21;
1017            #[doc = "Divide by 35"]
1018            pub const DIVIDE_35: u32 = 0x22;
1019            #[doc = "Divide by 36"]
1020            pub const DIVIDE_36: u32 = 0x23;
1021            #[doc = "Divide by 37"]
1022            pub const DIVIDE_37: u32 = 0x24;
1023            #[doc = "Divide by 38"]
1024            pub const DIVIDE_38: u32 = 0x25;
1025            #[doc = "Divide by 39"]
1026            pub const DIVIDE_39: u32 = 0x26;
1027            #[doc = "Divide by 40"]
1028            pub const DIVIDE_40: u32 = 0x27;
1029            #[doc = "Divide by 41"]
1030            pub const DIVIDE_41: u32 = 0x28;
1031            #[doc = "Divide by 42"]
1032            pub const DIVIDE_42: u32 = 0x29;
1033            #[doc = "Divide by 43"]
1034            pub const DIVIDE_43: u32 = 0x2a;
1035            #[doc = "Divide by 44"]
1036            pub const DIVIDE_44: u32 = 0x2b;
1037            #[doc = "Divide by 45"]
1038            pub const DIVIDE_45: u32 = 0x2c;
1039            #[doc = "Divide by 46"]
1040            pub const DIVIDE_46: u32 = 0x2d;
1041            #[doc = "Divide by 47"]
1042            pub const DIVIDE_47: u32 = 0x2e;
1043            #[doc = "Divide by 48"]
1044            pub const DIVIDE_48: u32 = 0x2f;
1045            #[doc = "Divide by 49"]
1046            pub const DIVIDE_49: u32 = 0x30;
1047            #[doc = "Divide by 50"]
1048            pub const DIVIDE_50: u32 = 0x31;
1049            #[doc = "Divide by 51"]
1050            pub const DIVIDE_51: u32 = 0x32;
1051            #[doc = "Divide by 52"]
1052            pub const DIVIDE_52: u32 = 0x33;
1053            #[doc = "Divide by 53"]
1054            pub const DIVIDE_53: u32 = 0x34;
1055            #[doc = "Divide by 54"]
1056            pub const DIVIDE_54: u32 = 0x35;
1057            #[doc = "Divide by 55"]
1058            pub const DIVIDE_55: u32 = 0x36;
1059            #[doc = "Divide by 56"]
1060            pub const DIVIDE_56: u32 = 0x37;
1061            #[doc = "Divide by 57"]
1062            pub const DIVIDE_57: u32 = 0x38;
1063            #[doc = "Divide by 58"]
1064            pub const DIVIDE_58: u32 = 0x39;
1065            #[doc = "Divide by 59"]
1066            pub const DIVIDE_59: u32 = 0x3a;
1067            #[doc = "Divide by 60"]
1068            pub const DIVIDE_60: u32 = 0x3b;
1069            #[doc = "Divide by 61"]
1070            pub const DIVIDE_61: u32 = 0x3c;
1071            #[doc = "Divide by 62"]
1072            pub const DIVIDE_62: u32 = 0x3d;
1073            #[doc = "Divide by 63"]
1074            pub const DIVIDE_63: u32 = 0x3e;
1075            #[doc = "Divide by 64"]
1076            pub const DIVIDE_64: u32 = 0x3f;
1077        }
1078    }
1079    #[doc = "Selector for the UART clock multiplexor"]
1080    pub mod UART_CLK_SEL {
1081        pub const offset: u32 = 6;
1082        pub const mask: u32 = 0x01 << offset;
1083        pub mod R {}
1084        pub mod W {}
1085        pub mod RW {
1086            #[doc = "derive clock from pll3_80m"]
1087            pub const UART_CLK_SEL_0: u32 = 0;
1088            #[doc = "derive clock from osc_clk"]
1089            pub const UART_CLK_SEL_1: u32 = 0x01;
1090        }
1091    }
1092    #[doc = "Divider for usdhc1 clock podf. Divider should be updated when output clock is gated."]
1093    pub mod USDHC1_PODF {
1094        pub const offset: u32 = 11;
1095        pub const mask: u32 = 0x07 << offset;
1096        pub mod R {}
1097        pub mod W {}
1098        pub mod RW {
1099            #[doc = "divide by 1"]
1100            pub const USDHC1_PODF_0: u32 = 0;
1101            #[doc = "divide by 2"]
1102            pub const USDHC1_PODF_1: u32 = 0x01;
1103            #[doc = "divide by 3"]
1104            pub const USDHC1_PODF_2: u32 = 0x02;
1105            #[doc = "divide by 4"]
1106            pub const USDHC1_PODF_3: u32 = 0x03;
1107            #[doc = "divide by 5"]
1108            pub const USDHC1_PODF_4: u32 = 0x04;
1109            #[doc = "divide by 6"]
1110            pub const USDHC1_PODF_5: u32 = 0x05;
1111            #[doc = "divide by 7"]
1112            pub const USDHC1_PODF_6: u32 = 0x06;
1113            #[doc = "divide by 8"]
1114            pub const USDHC1_PODF_7: u32 = 0x07;
1115        }
1116    }
1117    #[doc = "Divider for usdhc2 clock. Divider should be updated when output clock is gated."]
1118    pub mod USDHC2_PODF {
1119        pub const offset: u32 = 16;
1120        pub const mask: u32 = 0x07 << offset;
1121        pub mod R {}
1122        pub mod W {}
1123        pub mod RW {
1124            #[doc = "divide by 1"]
1125            pub const USDHC2_PODF_0: u32 = 0;
1126            #[doc = "divide by 2"]
1127            pub const USDHC2_PODF_1: u32 = 0x01;
1128            #[doc = "divide by 3"]
1129            pub const USDHC2_PODF_2: u32 = 0x02;
1130            #[doc = "divide by 4"]
1131            pub const USDHC2_PODF_3: u32 = 0x03;
1132            #[doc = "divide by 5"]
1133            pub const USDHC2_PODF_4: u32 = 0x04;
1134            #[doc = "divide by 6"]
1135            pub const USDHC2_PODF_5: u32 = 0x05;
1136            #[doc = "divide by 7"]
1137            pub const USDHC2_PODF_6: u32 = 0x06;
1138            #[doc = "divide by 8"]
1139            pub const USDHC2_PODF_7: u32 = 0x07;
1140        }
1141    }
1142    #[doc = "Divider for trace clock. Divider should be updated when output clock is gated."]
1143    pub mod TRACE_PODF {
1144        pub const offset: u32 = 25;
1145        pub const mask: u32 = 0x03 << offset;
1146        pub mod R {}
1147        pub mod W {}
1148        pub mod RW {
1149            #[doc = "divide by 1"]
1150            pub const TRACE_PODF_0: u32 = 0;
1151            #[doc = "divide by 2"]
1152            pub const TRACE_PODF_1: u32 = 0x01;
1153            #[doc = "divide by 3"]
1154            pub const TRACE_PODF_2: u32 = 0x02;
1155            #[doc = "divide by 4"]
1156            pub const TRACE_PODF_3: u32 = 0x03;
1157        }
1158    }
1159}
1160#[doc = "CCM Clock Divider Register"]
1161pub mod CS1CDR {
1162    #[doc = "Divider for sai1 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this."]
1163    pub mod SAI1_CLK_PODF {
1164        pub const offset: u32 = 0;
1165        pub const mask: u32 = 0x3f << offset;
1166        pub mod R {}
1167        pub mod W {}
1168        pub mod RW {
1169            #[doc = "Divide by 1"]
1170            pub const DIVIDE_1: u32 = 0;
1171            #[doc = "Divide by 2"]
1172            pub const DIVIDE_2: u32 = 0x01;
1173            #[doc = "Divide by 3"]
1174            pub const DIVIDE_3: u32 = 0x02;
1175            #[doc = "Divide by 4"]
1176            pub const DIVIDE_4: u32 = 0x03;
1177            #[doc = "Divide by 5"]
1178            pub const DIVIDE_5: u32 = 0x04;
1179            #[doc = "Divide by 6"]
1180            pub const DIVIDE_6: u32 = 0x05;
1181            #[doc = "Divide by 7"]
1182            pub const DIVIDE_7: u32 = 0x06;
1183            #[doc = "Divide by 8"]
1184            pub const DIVIDE_8: u32 = 0x07;
1185            #[doc = "Divide by 9"]
1186            pub const DIVIDE_9: u32 = 0x08;
1187            #[doc = "Divide by 10"]
1188            pub const DIVIDE_10: u32 = 0x09;
1189            #[doc = "Divide by 11"]
1190            pub const DIVIDE_11: u32 = 0x0a;
1191            #[doc = "Divide by 12"]
1192            pub const DIVIDE_12: u32 = 0x0b;
1193            #[doc = "Divide by 13"]
1194            pub const DIVIDE_13: u32 = 0x0c;
1195            #[doc = "Divide by 14"]
1196            pub const DIVIDE_14: u32 = 0x0d;
1197            #[doc = "Divide by 15"]
1198            pub const DIVIDE_15: u32 = 0x0e;
1199            #[doc = "Divide by 16"]
1200            pub const DIVIDE_16: u32 = 0x0f;
1201            #[doc = "Divide by 17"]
1202            pub const DIVIDE_17: u32 = 0x10;
1203            #[doc = "Divide by 18"]
1204            pub const DIVIDE_18: u32 = 0x11;
1205            #[doc = "Divide by 19"]
1206            pub const DIVIDE_19: u32 = 0x12;
1207            #[doc = "Divide by 20"]
1208            pub const DIVIDE_20: u32 = 0x13;
1209            #[doc = "Divide by 21"]
1210            pub const DIVIDE_21: u32 = 0x14;
1211            #[doc = "Divide by 22"]
1212            pub const DIVIDE_22: u32 = 0x15;
1213            #[doc = "Divide by 23"]
1214            pub const DIVIDE_23: u32 = 0x16;
1215            #[doc = "Divide by 24"]
1216            pub const DIVIDE_24: u32 = 0x17;
1217            #[doc = "Divide by 25"]
1218            pub const DIVIDE_25: u32 = 0x18;
1219            #[doc = "Divide by 26"]
1220            pub const DIVIDE_26: u32 = 0x19;
1221            #[doc = "Divide by 27"]
1222            pub const DIVIDE_27: u32 = 0x1a;
1223            #[doc = "Divide by 28"]
1224            pub const DIVIDE_28: u32 = 0x1b;
1225            #[doc = "Divide by 29"]
1226            pub const DIVIDE_29: u32 = 0x1c;
1227            #[doc = "Divide by 30"]
1228            pub const DIVIDE_30: u32 = 0x1d;
1229            #[doc = "Divide by 31"]
1230            pub const DIVIDE_31: u32 = 0x1e;
1231            #[doc = "Divide by 32"]
1232            pub const DIVIDE_32: u32 = 0x1f;
1233            #[doc = "Divide by 33"]
1234            pub const DIVIDE_33: u32 = 0x20;
1235            #[doc = "Divide by 34"]
1236            pub const DIVIDE_34: u32 = 0x21;
1237            #[doc = "Divide by 35"]
1238            pub const DIVIDE_35: u32 = 0x22;
1239            #[doc = "Divide by 36"]
1240            pub const DIVIDE_36: u32 = 0x23;
1241            #[doc = "Divide by 37"]
1242            pub const DIVIDE_37: u32 = 0x24;
1243            #[doc = "Divide by 38"]
1244            pub const DIVIDE_38: u32 = 0x25;
1245            #[doc = "Divide by 39"]
1246            pub const DIVIDE_39: u32 = 0x26;
1247            #[doc = "Divide by 40"]
1248            pub const DIVIDE_40: u32 = 0x27;
1249            #[doc = "Divide by 41"]
1250            pub const DIVIDE_41: u32 = 0x28;
1251            #[doc = "Divide by 42"]
1252            pub const DIVIDE_42: u32 = 0x29;
1253            #[doc = "Divide by 43"]
1254            pub const DIVIDE_43: u32 = 0x2a;
1255            #[doc = "Divide by 44"]
1256            pub const DIVIDE_44: u32 = 0x2b;
1257            #[doc = "Divide by 45"]
1258            pub const DIVIDE_45: u32 = 0x2c;
1259            #[doc = "Divide by 46"]
1260            pub const DIVIDE_46: u32 = 0x2d;
1261            #[doc = "Divide by 47"]
1262            pub const DIVIDE_47: u32 = 0x2e;
1263            #[doc = "Divide by 48"]
1264            pub const DIVIDE_48: u32 = 0x2f;
1265            #[doc = "Divide by 49"]
1266            pub const DIVIDE_49: u32 = 0x30;
1267            #[doc = "Divide by 50"]
1268            pub const DIVIDE_50: u32 = 0x31;
1269            #[doc = "Divide by 51"]
1270            pub const DIVIDE_51: u32 = 0x32;
1271            #[doc = "Divide by 52"]
1272            pub const DIVIDE_52: u32 = 0x33;
1273            #[doc = "Divide by 53"]
1274            pub const DIVIDE_53: u32 = 0x34;
1275            #[doc = "Divide by 54"]
1276            pub const DIVIDE_54: u32 = 0x35;
1277            #[doc = "Divide by 55"]
1278            pub const DIVIDE_55: u32 = 0x36;
1279            #[doc = "Divide by 56"]
1280            pub const DIVIDE_56: u32 = 0x37;
1281            #[doc = "Divide by 57"]
1282            pub const DIVIDE_57: u32 = 0x38;
1283            #[doc = "Divide by 58"]
1284            pub const DIVIDE_58: u32 = 0x39;
1285            #[doc = "Divide by 59"]
1286            pub const DIVIDE_59: u32 = 0x3a;
1287            #[doc = "Divide by 60"]
1288            pub const DIVIDE_60: u32 = 0x3b;
1289            #[doc = "Divide by 61"]
1290            pub const DIVIDE_61: u32 = 0x3c;
1291            #[doc = "Divide by 62"]
1292            pub const DIVIDE_62: u32 = 0x3d;
1293            #[doc = "Divide by 63"]
1294            pub const DIVIDE_63: u32 = 0x3e;
1295            #[doc = "Divide by 64"]
1296            pub const DIVIDE_64: u32 = 0x3f;
1297        }
1298    }
1299    #[doc = "Divider for sai1 clock pred."]
1300    pub mod SAI1_CLK_PRED {
1301        pub const offset: u32 = 6;
1302        pub const mask: u32 = 0x07 << offset;
1303        pub mod R {}
1304        pub mod W {}
1305        pub mod RW {
1306            #[doc = "divide by 1"]
1307            pub const SAI1_CLK_PRED_0: u32 = 0;
1308            #[doc = "divide by 2"]
1309            pub const SAI1_CLK_PRED_1: u32 = 0x01;
1310            #[doc = "divide by 3"]
1311            pub const SAI1_CLK_PRED_2: u32 = 0x02;
1312            #[doc = "divide by 4"]
1313            pub const SAI1_CLK_PRED_3: u32 = 0x03;
1314            #[doc = "divide by 5"]
1315            pub const SAI1_CLK_PRED_4: u32 = 0x04;
1316            #[doc = "divide by 6"]
1317            pub const SAI1_CLK_PRED_5: u32 = 0x05;
1318            #[doc = "divide by 7"]
1319            pub const SAI1_CLK_PRED_6: u32 = 0x06;
1320            #[doc = "divide by 8"]
1321            pub const SAI1_CLK_PRED_7: u32 = 0x07;
1322        }
1323    }
1324    #[doc = "Divider for flexio2 clock."]
1325    pub mod FLEXIO2_CLK_PRED {
1326        pub const offset: u32 = 9;
1327        pub const mask: u32 = 0x07 << offset;
1328        pub mod R {}
1329        pub mod W {}
1330        pub mod RW {
1331            #[doc = "divide by 1"]
1332            pub const FLEXIO2_CLK_PRED_0: u32 = 0;
1333            #[doc = "divide by 2"]
1334            pub const FLEXIO2_CLK_PRED_1: u32 = 0x01;
1335            #[doc = "divide by 3"]
1336            pub const FLEXIO2_CLK_PRED_2: u32 = 0x02;
1337            #[doc = "divide by 4"]
1338            pub const FLEXIO2_CLK_PRED_3: u32 = 0x03;
1339            #[doc = "divide by 5"]
1340            pub const FLEXIO2_CLK_PRED_4: u32 = 0x04;
1341            #[doc = "divide by 6"]
1342            pub const FLEXIO2_CLK_PRED_5: u32 = 0x05;
1343            #[doc = "divide by 7"]
1344            pub const FLEXIO2_CLK_PRED_6: u32 = 0x06;
1345            #[doc = "divide by 8"]
1346            pub const FLEXIO2_CLK_PRED_7: u32 = 0x07;
1347        }
1348    }
1349    #[doc = "Divider for sai3 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this."]
1350    pub mod SAI3_CLK_PODF {
1351        pub const offset: u32 = 16;
1352        pub const mask: u32 = 0x3f << offset;
1353        pub mod R {}
1354        pub mod W {}
1355        pub mod RW {
1356            #[doc = "Divide by 1"]
1357            pub const DIVIDE_1: u32 = 0;
1358            #[doc = "Divide by 2"]
1359            pub const DIVIDE_2: u32 = 0x01;
1360            #[doc = "Divide by 3"]
1361            pub const DIVIDE_3: u32 = 0x02;
1362            #[doc = "Divide by 4"]
1363            pub const DIVIDE_4: u32 = 0x03;
1364            #[doc = "Divide by 5"]
1365            pub const DIVIDE_5: u32 = 0x04;
1366            #[doc = "Divide by 6"]
1367            pub const DIVIDE_6: u32 = 0x05;
1368            #[doc = "Divide by 7"]
1369            pub const DIVIDE_7: u32 = 0x06;
1370            #[doc = "Divide by 8"]
1371            pub const DIVIDE_8: u32 = 0x07;
1372            #[doc = "Divide by 9"]
1373            pub const DIVIDE_9: u32 = 0x08;
1374            #[doc = "Divide by 10"]
1375            pub const DIVIDE_10: u32 = 0x09;
1376            #[doc = "Divide by 11"]
1377            pub const DIVIDE_11: u32 = 0x0a;
1378            #[doc = "Divide by 12"]
1379            pub const DIVIDE_12: u32 = 0x0b;
1380            #[doc = "Divide by 13"]
1381            pub const DIVIDE_13: u32 = 0x0c;
1382            #[doc = "Divide by 14"]
1383            pub const DIVIDE_14: u32 = 0x0d;
1384            #[doc = "Divide by 15"]
1385            pub const DIVIDE_15: u32 = 0x0e;
1386            #[doc = "Divide by 16"]
1387            pub const DIVIDE_16: u32 = 0x0f;
1388            #[doc = "Divide by 17"]
1389            pub const DIVIDE_17: u32 = 0x10;
1390            #[doc = "Divide by 18"]
1391            pub const DIVIDE_18: u32 = 0x11;
1392            #[doc = "Divide by 19"]
1393            pub const DIVIDE_19: u32 = 0x12;
1394            #[doc = "Divide by 20"]
1395            pub const DIVIDE_20: u32 = 0x13;
1396            #[doc = "Divide by 21"]
1397            pub const DIVIDE_21: u32 = 0x14;
1398            #[doc = "Divide by 22"]
1399            pub const DIVIDE_22: u32 = 0x15;
1400            #[doc = "Divide by 23"]
1401            pub const DIVIDE_23: u32 = 0x16;
1402            #[doc = "Divide by 24"]
1403            pub const DIVIDE_24: u32 = 0x17;
1404            #[doc = "Divide by 25"]
1405            pub const DIVIDE_25: u32 = 0x18;
1406            #[doc = "Divide by 26"]
1407            pub const DIVIDE_26: u32 = 0x19;
1408            #[doc = "Divide by 27"]
1409            pub const DIVIDE_27: u32 = 0x1a;
1410            #[doc = "Divide by 28"]
1411            pub const DIVIDE_28: u32 = 0x1b;
1412            #[doc = "Divide by 29"]
1413            pub const DIVIDE_29: u32 = 0x1c;
1414            #[doc = "Divide by 30"]
1415            pub const DIVIDE_30: u32 = 0x1d;
1416            #[doc = "Divide by 31"]
1417            pub const DIVIDE_31: u32 = 0x1e;
1418            #[doc = "Divide by 32"]
1419            pub const DIVIDE_32: u32 = 0x1f;
1420            #[doc = "Divide by 33"]
1421            pub const DIVIDE_33: u32 = 0x20;
1422            #[doc = "Divide by 34"]
1423            pub const DIVIDE_34: u32 = 0x21;
1424            #[doc = "Divide by 35"]
1425            pub const DIVIDE_35: u32 = 0x22;
1426            #[doc = "Divide by 36"]
1427            pub const DIVIDE_36: u32 = 0x23;
1428            #[doc = "Divide by 37"]
1429            pub const DIVIDE_37: u32 = 0x24;
1430            #[doc = "Divide by 38"]
1431            pub const DIVIDE_38: u32 = 0x25;
1432            #[doc = "Divide by 39"]
1433            pub const DIVIDE_39: u32 = 0x26;
1434            #[doc = "Divide by 40"]
1435            pub const DIVIDE_40: u32 = 0x27;
1436            #[doc = "Divide by 41"]
1437            pub const DIVIDE_41: u32 = 0x28;
1438            #[doc = "Divide by 42"]
1439            pub const DIVIDE_42: u32 = 0x29;
1440            #[doc = "Divide by 43"]
1441            pub const DIVIDE_43: u32 = 0x2a;
1442            #[doc = "Divide by 44"]
1443            pub const DIVIDE_44: u32 = 0x2b;
1444            #[doc = "Divide by 45"]
1445            pub const DIVIDE_45: u32 = 0x2c;
1446            #[doc = "Divide by 46"]
1447            pub const DIVIDE_46: u32 = 0x2d;
1448            #[doc = "Divide by 47"]
1449            pub const DIVIDE_47: u32 = 0x2e;
1450            #[doc = "Divide by 48"]
1451            pub const DIVIDE_48: u32 = 0x2f;
1452            #[doc = "Divide by 49"]
1453            pub const DIVIDE_49: u32 = 0x30;
1454            #[doc = "Divide by 50"]
1455            pub const DIVIDE_50: u32 = 0x31;
1456            #[doc = "Divide by 51"]
1457            pub const DIVIDE_51: u32 = 0x32;
1458            #[doc = "Divide by 52"]
1459            pub const DIVIDE_52: u32 = 0x33;
1460            #[doc = "Divide by 53"]
1461            pub const DIVIDE_53: u32 = 0x34;
1462            #[doc = "Divide by 54"]
1463            pub const DIVIDE_54: u32 = 0x35;
1464            #[doc = "Divide by 55"]
1465            pub const DIVIDE_55: u32 = 0x36;
1466            #[doc = "Divide by 56"]
1467            pub const DIVIDE_56: u32 = 0x37;
1468            #[doc = "Divide by 57"]
1469            pub const DIVIDE_57: u32 = 0x38;
1470            #[doc = "Divide by 58"]
1471            pub const DIVIDE_58: u32 = 0x39;
1472            #[doc = "Divide by 59"]
1473            pub const DIVIDE_59: u32 = 0x3a;
1474            #[doc = "Divide by 60"]
1475            pub const DIVIDE_60: u32 = 0x3b;
1476            #[doc = "Divide by 61"]
1477            pub const DIVIDE_61: u32 = 0x3c;
1478            #[doc = "Divide by 62"]
1479            pub const DIVIDE_62: u32 = 0x3d;
1480            #[doc = "Divide by 63"]
1481            pub const DIVIDE_63: u32 = 0x3e;
1482            #[doc = "Divide by 64"]
1483            pub const DIVIDE_64: u32 = 0x3f;
1484        }
1485    }
1486    #[doc = "Divider for sai3 clock pred."]
1487    pub mod SAI3_CLK_PRED {
1488        pub const offset: u32 = 22;
1489        pub const mask: u32 = 0x07 << offset;
1490        pub mod R {}
1491        pub mod W {}
1492        pub mod RW {
1493            #[doc = "divide by 1"]
1494            pub const SAI3_CLK_PRED_0: u32 = 0;
1495            #[doc = "divide by 2"]
1496            pub const SAI3_CLK_PRED_1: u32 = 0x01;
1497            #[doc = "divide by 3"]
1498            pub const SAI3_CLK_PRED_2: u32 = 0x02;
1499            #[doc = "divide by 4"]
1500            pub const SAI3_CLK_PRED_3: u32 = 0x03;
1501            #[doc = "divide by 5"]
1502            pub const SAI3_CLK_PRED_4: u32 = 0x04;
1503            #[doc = "divide by 6"]
1504            pub const SAI3_CLK_PRED_5: u32 = 0x05;
1505            #[doc = "divide by 7"]
1506            pub const SAI3_CLK_PRED_6: u32 = 0x06;
1507            #[doc = "divide by 8"]
1508            pub const SAI3_CLK_PRED_7: u32 = 0x07;
1509        }
1510    }
1511    #[doc = "Divider for flexio2 clock. Divider should be updated when output clock is gated."]
1512    pub mod FLEXIO2_CLK_PODF {
1513        pub const offset: u32 = 25;
1514        pub const mask: u32 = 0x07 << offset;
1515        pub mod R {}
1516        pub mod W {}
1517        pub mod RW {
1518            #[doc = "Divide by 1"]
1519            pub const DIVIDE_1: u32 = 0;
1520            #[doc = "Divide by 2"]
1521            pub const DIVIDE_2: u32 = 0x01;
1522            #[doc = "Divide by 3"]
1523            pub const DIVIDE_3: u32 = 0x02;
1524            #[doc = "Divide by 4"]
1525            pub const DIVIDE_4: u32 = 0x03;
1526            #[doc = "Divide by 5"]
1527            pub const DIVIDE_5: u32 = 0x04;
1528            #[doc = "Divide by 6"]
1529            pub const DIVIDE_6: u32 = 0x05;
1530            #[doc = "Divide by 7"]
1531            pub const DIVIDE_7: u32 = 0x06;
1532            #[doc = "Divide by 8"]
1533            pub const DIVIDE_8: u32 = 0x07;
1534        }
1535    }
1536}
1537#[doc = "CCM Clock Divider Register"]
1538pub mod CS2CDR {
1539    #[doc = "Divider for sai2 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this."]
1540    pub mod SAI2_CLK_PODF {
1541        pub const offset: u32 = 0;
1542        pub const mask: u32 = 0x3f << offset;
1543        pub mod R {}
1544        pub mod W {}
1545        pub mod RW {
1546            #[doc = "Divide by 1"]
1547            pub const DIVIDE_1: u32 = 0;
1548            #[doc = "Divide by 2"]
1549            pub const DIVIDE_2: u32 = 0x01;
1550            #[doc = "Divide by 3"]
1551            pub const DIVIDE_3: u32 = 0x02;
1552            #[doc = "Divide by 4"]
1553            pub const DIVIDE_4: u32 = 0x03;
1554            #[doc = "Divide by 5"]
1555            pub const DIVIDE_5: u32 = 0x04;
1556            #[doc = "Divide by 6"]
1557            pub const DIVIDE_6: u32 = 0x05;
1558            #[doc = "Divide by 7"]
1559            pub const DIVIDE_7: u32 = 0x06;
1560            #[doc = "Divide by 8"]
1561            pub const DIVIDE_8: u32 = 0x07;
1562            #[doc = "Divide by 9"]
1563            pub const DIVIDE_9: u32 = 0x08;
1564            #[doc = "Divide by 10"]
1565            pub const DIVIDE_10: u32 = 0x09;
1566            #[doc = "Divide by 11"]
1567            pub const DIVIDE_11: u32 = 0x0a;
1568            #[doc = "Divide by 12"]
1569            pub const DIVIDE_12: u32 = 0x0b;
1570            #[doc = "Divide by 13"]
1571            pub const DIVIDE_13: u32 = 0x0c;
1572            #[doc = "Divide by 14"]
1573            pub const DIVIDE_14: u32 = 0x0d;
1574            #[doc = "Divide by 15"]
1575            pub const DIVIDE_15: u32 = 0x0e;
1576            #[doc = "Divide by 16"]
1577            pub const DIVIDE_16: u32 = 0x0f;
1578            #[doc = "Divide by 17"]
1579            pub const DIVIDE_17: u32 = 0x10;
1580            #[doc = "Divide by 18"]
1581            pub const DIVIDE_18: u32 = 0x11;
1582            #[doc = "Divide by 19"]
1583            pub const DIVIDE_19: u32 = 0x12;
1584            #[doc = "Divide by 20"]
1585            pub const DIVIDE_20: u32 = 0x13;
1586            #[doc = "Divide by 21"]
1587            pub const DIVIDE_21: u32 = 0x14;
1588            #[doc = "Divide by 22"]
1589            pub const DIVIDE_22: u32 = 0x15;
1590            #[doc = "Divide by 23"]
1591            pub const DIVIDE_23: u32 = 0x16;
1592            #[doc = "Divide by 24"]
1593            pub const DIVIDE_24: u32 = 0x17;
1594            #[doc = "Divide by 25"]
1595            pub const DIVIDE_25: u32 = 0x18;
1596            #[doc = "Divide by 26"]
1597            pub const DIVIDE_26: u32 = 0x19;
1598            #[doc = "Divide by 27"]
1599            pub const DIVIDE_27: u32 = 0x1a;
1600            #[doc = "Divide by 28"]
1601            pub const DIVIDE_28: u32 = 0x1b;
1602            #[doc = "Divide by 29"]
1603            pub const DIVIDE_29: u32 = 0x1c;
1604            #[doc = "Divide by 30"]
1605            pub const DIVIDE_30: u32 = 0x1d;
1606            #[doc = "Divide by 31"]
1607            pub const DIVIDE_31: u32 = 0x1e;
1608            #[doc = "Divide by 32"]
1609            pub const DIVIDE_32: u32 = 0x1f;
1610            #[doc = "Divide by 33"]
1611            pub const DIVIDE_33: u32 = 0x20;
1612            #[doc = "Divide by 34"]
1613            pub const DIVIDE_34: u32 = 0x21;
1614            #[doc = "Divide by 35"]
1615            pub const DIVIDE_35: u32 = 0x22;
1616            #[doc = "Divide by 36"]
1617            pub const DIVIDE_36: u32 = 0x23;
1618            #[doc = "Divide by 37"]
1619            pub const DIVIDE_37: u32 = 0x24;
1620            #[doc = "Divide by 38"]
1621            pub const DIVIDE_38: u32 = 0x25;
1622            #[doc = "Divide by 39"]
1623            pub const DIVIDE_39: u32 = 0x26;
1624            #[doc = "Divide by 40"]
1625            pub const DIVIDE_40: u32 = 0x27;
1626            #[doc = "Divide by 41"]
1627            pub const DIVIDE_41: u32 = 0x28;
1628            #[doc = "Divide by 42"]
1629            pub const DIVIDE_42: u32 = 0x29;
1630            #[doc = "Divide by 43"]
1631            pub const DIVIDE_43: u32 = 0x2a;
1632            #[doc = "Divide by 44"]
1633            pub const DIVIDE_44: u32 = 0x2b;
1634            #[doc = "Divide by 45"]
1635            pub const DIVIDE_45: u32 = 0x2c;
1636            #[doc = "Divide by 46"]
1637            pub const DIVIDE_46: u32 = 0x2d;
1638            #[doc = "Divide by 47"]
1639            pub const DIVIDE_47: u32 = 0x2e;
1640            #[doc = "Divide by 48"]
1641            pub const DIVIDE_48: u32 = 0x2f;
1642            #[doc = "Divide by 49"]
1643            pub const DIVIDE_49: u32 = 0x30;
1644            #[doc = "Divide by 50"]
1645            pub const DIVIDE_50: u32 = 0x31;
1646            #[doc = "Divide by 51"]
1647            pub const DIVIDE_51: u32 = 0x32;
1648            #[doc = "Divide by 52"]
1649            pub const DIVIDE_52: u32 = 0x33;
1650            #[doc = "Divide by 53"]
1651            pub const DIVIDE_53: u32 = 0x34;
1652            #[doc = "Divide by 54"]
1653            pub const DIVIDE_54: u32 = 0x35;
1654            #[doc = "Divide by 55"]
1655            pub const DIVIDE_55: u32 = 0x36;
1656            #[doc = "Divide by 56"]
1657            pub const DIVIDE_56: u32 = 0x37;
1658            #[doc = "Divide by 57"]
1659            pub const DIVIDE_57: u32 = 0x38;
1660            #[doc = "Divide by 58"]
1661            pub const DIVIDE_58: u32 = 0x39;
1662            #[doc = "Divide by 59"]
1663            pub const DIVIDE_59: u32 = 0x3a;
1664            #[doc = "Divide by 60"]
1665            pub const DIVIDE_60: u32 = 0x3b;
1666            #[doc = "Divide by 61"]
1667            pub const DIVIDE_61: u32 = 0x3c;
1668            #[doc = "Divide by 62"]
1669            pub const DIVIDE_62: u32 = 0x3d;
1670            #[doc = "Divide by 63"]
1671            pub const DIVIDE_63: u32 = 0x3e;
1672            #[doc = "Divide by 64"]
1673            pub const DIVIDE_64: u32 = 0x3f;
1674        }
1675    }
1676    #[doc = "Divider for sai2 clock pred.Divider should be updated when output clock is gated."]
1677    pub mod SAI2_CLK_PRED {
1678        pub const offset: u32 = 6;
1679        pub const mask: u32 = 0x07 << offset;
1680        pub mod R {}
1681        pub mod W {}
1682        pub mod RW {
1683            #[doc = "divide by 1"]
1684            pub const SAI2_CLK_PRED_0: u32 = 0;
1685            #[doc = "divide by 2"]
1686            pub const SAI2_CLK_PRED_1: u32 = 0x01;
1687            #[doc = "divide by 3"]
1688            pub const SAI2_CLK_PRED_2: u32 = 0x02;
1689            #[doc = "divide by 4"]
1690            pub const SAI2_CLK_PRED_3: u32 = 0x03;
1691            #[doc = "divide by 5"]
1692            pub const SAI2_CLK_PRED_4: u32 = 0x04;
1693            #[doc = "divide by 6"]
1694            pub const SAI2_CLK_PRED_5: u32 = 0x05;
1695            #[doc = "divide by 7"]
1696            pub const SAI2_CLK_PRED_6: u32 = 0x06;
1697            #[doc = "divide by 8"]
1698            pub const SAI2_CLK_PRED_7: u32 = 0x07;
1699        }
1700    }
1701}
1702#[doc = "CCM D1 Clock Divider Register"]
1703pub mod CDCDR {
1704    #[doc = "Selector for flexio1 clock multiplexer"]
1705    pub mod FLEXIO1_CLK_SEL {
1706        pub const offset: u32 = 7;
1707        pub const mask: u32 = 0x03 << offset;
1708        pub mod R {}
1709        pub mod W {}
1710        pub mod RW {
1711            #[doc = "derive clock from PLL4 divided clock"]
1712            pub const FLEXIO1_CLK_SEL_0: u32 = 0;
1713            #[doc = "derive clock from PLL3 PFD2 clock"]
1714            pub const FLEXIO1_CLK_SEL_1: u32 = 0x01;
1715            #[doc = "derive from PLL2"]
1716            pub const FLEXIO1_CLK_SEL_2: u32 = 0x02;
1717            #[doc = "derive clock from pll3_sw_clk"]
1718            pub const FLEXIO1_CLK_SEL_3: u32 = 0x03;
1719        }
1720    }
1721    #[doc = "Divider for flexio1 clock podf. Divider should be updated when output clock is gated."]
1722    pub mod FLEXIO1_CLK_PODF {
1723        pub const offset: u32 = 9;
1724        pub const mask: u32 = 0x07 << offset;
1725        pub mod R {}
1726        pub mod W {}
1727        pub mod RW {
1728            #[doc = "Divide by 1"]
1729            pub const DIVIDE_1: u32 = 0;
1730            #[doc = "Divide by 2"]
1731            pub const DIVIDE_2: u32 = 0x01;
1732            #[doc = "Divide by 3"]
1733            pub const DIVIDE_3: u32 = 0x02;
1734            #[doc = "Divide by 4"]
1735            pub const DIVIDE_4: u32 = 0x03;
1736            #[doc = "Divide by 5"]
1737            pub const DIVIDE_5: u32 = 0x04;
1738            #[doc = "Divide by 6"]
1739            pub const DIVIDE_6: u32 = 0x05;
1740            #[doc = "Divide by 7"]
1741            pub const DIVIDE_7: u32 = 0x06;
1742            #[doc = "Divide by 8"]
1743            pub const DIVIDE_8: u32 = 0x07;
1744        }
1745    }
1746    #[doc = "Divider for flexio1 clock pred. Divider should be updated when output clock is gated."]
1747    pub mod FLEXIO1_CLK_PRED {
1748        pub const offset: u32 = 12;
1749        pub const mask: u32 = 0x07 << offset;
1750        pub mod R {}
1751        pub mod W {}
1752        pub mod RW {
1753            #[doc = "divide by 1"]
1754            pub const FLEXIO1_CLK_PRED_0: u32 = 0;
1755            #[doc = "divide by 2"]
1756            pub const FLEXIO1_CLK_PRED_1: u32 = 0x01;
1757            #[doc = "divide by 3"]
1758            pub const FLEXIO1_CLK_PRED_2: u32 = 0x02;
1759            #[doc = "divide by 4"]
1760            pub const FLEXIO1_CLK_PRED_3: u32 = 0x03;
1761            #[doc = "divide by 5"]
1762            pub const FLEXIO1_CLK_PRED_4: u32 = 0x04;
1763            #[doc = "divide by 6"]
1764            pub const FLEXIO1_CLK_PRED_5: u32 = 0x05;
1765            #[doc = "divide by 7"]
1766            pub const FLEXIO1_CLK_PRED_6: u32 = 0x06;
1767            #[doc = "divide by 8"]
1768            pub const FLEXIO1_CLK_PRED_7: u32 = 0x07;
1769        }
1770    }
1771    #[doc = "Selector for spdif0 clock multiplexer"]
1772    pub mod SPDIF0_CLK_SEL {
1773        pub const offset: u32 = 20;
1774        pub const mask: u32 = 0x03 << offset;
1775        pub mod R {}
1776        pub mod W {}
1777        pub mod RW {
1778            #[doc = "derive clock from PLL4"]
1779            pub const SPDIF0_CLK_SEL_0: u32 = 0;
1780            #[doc = "derive clock from PLL3 PFD2"]
1781            pub const SPDIF0_CLK_SEL_1: u32 = 0x01;
1782            #[doc = "derive clock from PLL5"]
1783            pub const SPDIF0_CLK_SEL_2: u32 = 0x02;
1784            #[doc = "derive clock from pll3_sw_clk"]
1785            pub const SPDIF0_CLK_SEL_3: u32 = 0x03;
1786        }
1787    }
1788    #[doc = "Divider for spdif0 clock podf. Divider should be updated when output clock is gated."]
1789    pub mod SPDIF0_CLK_PODF {
1790        pub const offset: u32 = 22;
1791        pub const mask: u32 = 0x07 << offset;
1792        pub mod R {}
1793        pub mod W {}
1794        pub mod RW {
1795            #[doc = "Divide by 1"]
1796            pub const DIVIDE_1: u32 = 0;
1797            #[doc = "Divide by 2"]
1798            pub const DIVIDE_2: u32 = 0x01;
1799            #[doc = "Divide by 3"]
1800            pub const DIVIDE_3: u32 = 0x02;
1801            #[doc = "Divide by 4"]
1802            pub const DIVIDE_4: u32 = 0x03;
1803            #[doc = "Divide by 5"]
1804            pub const DIVIDE_5: u32 = 0x04;
1805            #[doc = "Divide by 6"]
1806            pub const DIVIDE_6: u32 = 0x05;
1807            #[doc = "Divide by 7"]
1808            pub const DIVIDE_7: u32 = 0x06;
1809            #[doc = "Divide by 8"]
1810            pub const DIVIDE_8: u32 = 0x07;
1811        }
1812    }
1813    #[doc = "Divider for spdif0 clock pred. Divider should be updated when output clock is gated."]
1814    pub mod SPDIF0_CLK_PRED {
1815        pub const offset: u32 = 25;
1816        pub const mask: u32 = 0x07 << offset;
1817        pub mod R {}
1818        pub mod W {}
1819        pub mod RW {
1820            #[doc = "Divide by 1"]
1821            pub const DIVIDE_1: u32 = 0;
1822            #[doc = "Divide by 2"]
1823            pub const DIVIDE_2: u32 = 0x01;
1824            #[doc = "Divide by 3"]
1825            pub const DIVIDE_3: u32 = 0x02;
1826            #[doc = "Divide by 4"]
1827            pub const DIVIDE_4: u32 = 0x03;
1828            #[doc = "Divide by 5"]
1829            pub const DIVIDE_5: u32 = 0x04;
1830            #[doc = "Divide by 6"]
1831            pub const DIVIDE_6: u32 = 0x05;
1832            #[doc = "Divide by 7"]
1833            pub const DIVIDE_7: u32 = 0x06;
1834            #[doc = "Divide by 8"]
1835            pub const DIVIDE_8: u32 = 0x07;
1836        }
1837    }
1838}
1839#[doc = "CCM Serial Clock Divider Register 2"]
1840pub mod CSCDR2 {
1841    #[doc = "Pre-divider for lcdif clock. Divider should be updated when output clock is gated."]
1842    pub mod LCDIF_PRED {
1843        pub const offset: u32 = 12;
1844        pub const mask: u32 = 0x07 << offset;
1845        pub mod R {}
1846        pub mod W {}
1847        pub mod RW {
1848            #[doc = "divide by 1"]
1849            pub const LCDIF_PRED_0: u32 = 0;
1850            #[doc = "divide by 2"]
1851            pub const LCDIF_PRED_1: u32 = 0x01;
1852            #[doc = "divide by 3"]
1853            pub const LCDIF_PRED_2: u32 = 0x02;
1854            #[doc = "divide by 4"]
1855            pub const LCDIF_PRED_3: u32 = 0x03;
1856            #[doc = "divide by 5"]
1857            pub const LCDIF_PRED_4: u32 = 0x04;
1858            #[doc = "divide by 6"]
1859            pub const LCDIF_PRED_5: u32 = 0x05;
1860            #[doc = "divide by 7"]
1861            pub const LCDIF_PRED_6: u32 = 0x06;
1862            #[doc = "divide by 8"]
1863            pub const LCDIF_PRED_7: u32 = 0x07;
1864        }
1865    }
1866    #[doc = "Selector for lcdif root clock pre-multiplexer"]
1867    pub mod LCDIF_PRE_CLK_SEL {
1868        pub const offset: u32 = 15;
1869        pub const mask: u32 = 0x07 << offset;
1870        pub mod R {}
1871        pub mod W {}
1872        pub mod RW {
1873            #[doc = "derive clock from PLL2"]
1874            pub const LCDIF_PRE_CLK_SEL_0: u32 = 0;
1875            #[doc = "derive clock from PLL3 PFD3"]
1876            pub const LCDIF_PRE_CLK_SEL_1: u32 = 0x01;
1877            #[doc = "derive clock from PLL5"]
1878            pub const LCDIF_PRE_CLK_SEL_2: u32 = 0x02;
1879            #[doc = "derive clock from PLL2 PFD0"]
1880            pub const LCDIF_PRE_CLK_SEL_3: u32 = 0x03;
1881            #[doc = "derive clock from PLL2 PFD1"]
1882            pub const LCDIF_PRE_CLK_SEL_4: u32 = 0x04;
1883            #[doc = "derive clock from PLL3 PFD1"]
1884            pub const LCDIF_PRE_CLK_SEL_5: u32 = 0x05;
1885        }
1886    }
1887    #[doc = "Selector for the LPI2C clock multiplexor"]
1888    pub mod LPI2C_CLK_SEL {
1889        pub const offset: u32 = 18;
1890        pub const mask: u32 = 0x01 << offset;
1891        pub mod R {}
1892        pub mod W {}
1893        pub mod RW {
1894            #[doc = "derive clock from pll3_60m"]
1895            pub const LPI2C_CLK_SEL_0: u32 = 0;
1896            #[doc = "derive clock from osc_clk"]
1897            pub const LPI2C_CLK_SEL_1: u32 = 0x01;
1898        }
1899    }
1900    #[doc = "Divider for lpi2c clock podf. Divider should be updated when output clock is gated. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this."]
1901    pub mod LPI2C_CLK_PODF {
1902        pub const offset: u32 = 19;
1903        pub const mask: u32 = 0x3f << offset;
1904        pub mod R {}
1905        pub mod W {}
1906        pub mod RW {
1907            #[doc = "Divide by 1"]
1908            pub const DIVIDE_1: u32 = 0;
1909            #[doc = "Divide by 2"]
1910            pub const DIVIDE_2: u32 = 0x01;
1911            #[doc = "Divide by 3"]
1912            pub const DIVIDE_3: u32 = 0x02;
1913            #[doc = "Divide by 4"]
1914            pub const DIVIDE_4: u32 = 0x03;
1915            #[doc = "Divide by 5"]
1916            pub const DIVIDE_5: u32 = 0x04;
1917            #[doc = "Divide by 6"]
1918            pub const DIVIDE_6: u32 = 0x05;
1919            #[doc = "Divide by 7"]
1920            pub const DIVIDE_7: u32 = 0x06;
1921            #[doc = "Divide by 8"]
1922            pub const DIVIDE_8: u32 = 0x07;
1923            #[doc = "Divide by 9"]
1924            pub const DIVIDE_9: u32 = 0x08;
1925            #[doc = "Divide by 10"]
1926            pub const DIVIDE_10: u32 = 0x09;
1927            #[doc = "Divide by 11"]
1928            pub const DIVIDE_11: u32 = 0x0a;
1929            #[doc = "Divide by 12"]
1930            pub const DIVIDE_12: u32 = 0x0b;
1931            #[doc = "Divide by 13"]
1932            pub const DIVIDE_13: u32 = 0x0c;
1933            #[doc = "Divide by 14"]
1934            pub const DIVIDE_14: u32 = 0x0d;
1935            #[doc = "Divide by 15"]
1936            pub const DIVIDE_15: u32 = 0x0e;
1937            #[doc = "Divide by 16"]
1938            pub const DIVIDE_16: u32 = 0x0f;
1939            #[doc = "Divide by 17"]
1940            pub const DIVIDE_17: u32 = 0x10;
1941            #[doc = "Divide by 18"]
1942            pub const DIVIDE_18: u32 = 0x11;
1943            #[doc = "Divide by 19"]
1944            pub const DIVIDE_19: u32 = 0x12;
1945            #[doc = "Divide by 20"]
1946            pub const DIVIDE_20: u32 = 0x13;
1947            #[doc = "Divide by 21"]
1948            pub const DIVIDE_21: u32 = 0x14;
1949            #[doc = "Divide by 22"]
1950            pub const DIVIDE_22: u32 = 0x15;
1951            #[doc = "Divide by 23"]
1952            pub const DIVIDE_23: u32 = 0x16;
1953            #[doc = "Divide by 24"]
1954            pub const DIVIDE_24: u32 = 0x17;
1955            #[doc = "Divide by 25"]
1956            pub const DIVIDE_25: u32 = 0x18;
1957            #[doc = "Divide by 26"]
1958            pub const DIVIDE_26: u32 = 0x19;
1959            #[doc = "Divide by 27"]
1960            pub const DIVIDE_27: u32 = 0x1a;
1961            #[doc = "Divide by 28"]
1962            pub const DIVIDE_28: u32 = 0x1b;
1963            #[doc = "Divide by 29"]
1964            pub const DIVIDE_29: u32 = 0x1c;
1965            #[doc = "Divide by 30"]
1966            pub const DIVIDE_30: u32 = 0x1d;
1967            #[doc = "Divide by 31"]
1968            pub const DIVIDE_31: u32 = 0x1e;
1969            #[doc = "Divide by 32"]
1970            pub const DIVIDE_32: u32 = 0x1f;
1971            #[doc = "Divide by 33"]
1972            pub const DIVIDE_33: u32 = 0x20;
1973            #[doc = "Divide by 34"]
1974            pub const DIVIDE_34: u32 = 0x21;
1975            #[doc = "Divide by 35"]
1976            pub const DIVIDE_35: u32 = 0x22;
1977            #[doc = "Divide by 36"]
1978            pub const DIVIDE_36: u32 = 0x23;
1979            #[doc = "Divide by 37"]
1980            pub const DIVIDE_37: u32 = 0x24;
1981            #[doc = "Divide by 38"]
1982            pub const DIVIDE_38: u32 = 0x25;
1983            #[doc = "Divide by 39"]
1984            pub const DIVIDE_39: u32 = 0x26;
1985            #[doc = "Divide by 40"]
1986            pub const DIVIDE_40: u32 = 0x27;
1987            #[doc = "Divide by 41"]
1988            pub const DIVIDE_41: u32 = 0x28;
1989            #[doc = "Divide by 42"]
1990            pub const DIVIDE_42: u32 = 0x29;
1991            #[doc = "Divide by 43"]
1992            pub const DIVIDE_43: u32 = 0x2a;
1993            #[doc = "Divide by 44"]
1994            pub const DIVIDE_44: u32 = 0x2b;
1995            #[doc = "Divide by 45"]
1996            pub const DIVIDE_45: u32 = 0x2c;
1997            #[doc = "Divide by 46"]
1998            pub const DIVIDE_46: u32 = 0x2d;
1999            #[doc = "Divide by 47"]
2000            pub const DIVIDE_47: u32 = 0x2e;
2001            #[doc = "Divide by 48"]
2002            pub const DIVIDE_48: u32 = 0x2f;
2003            #[doc = "Divide by 49"]
2004            pub const DIVIDE_49: u32 = 0x30;
2005            #[doc = "Divide by 50"]
2006            pub const DIVIDE_50: u32 = 0x31;
2007            #[doc = "Divide by 51"]
2008            pub const DIVIDE_51: u32 = 0x32;
2009            #[doc = "Divide by 52"]
2010            pub const DIVIDE_52: u32 = 0x33;
2011            #[doc = "Divide by 53"]
2012            pub const DIVIDE_53: u32 = 0x34;
2013            #[doc = "Divide by 54"]
2014            pub const DIVIDE_54: u32 = 0x35;
2015            #[doc = "Divide by 55"]
2016            pub const DIVIDE_55: u32 = 0x36;
2017            #[doc = "Divide by 56"]
2018            pub const DIVIDE_56: u32 = 0x37;
2019            #[doc = "Divide by 57"]
2020            pub const DIVIDE_57: u32 = 0x38;
2021            #[doc = "Divide by 58"]
2022            pub const DIVIDE_58: u32 = 0x39;
2023            #[doc = "Divide by 59"]
2024            pub const DIVIDE_59: u32 = 0x3a;
2025            #[doc = "Divide by 60"]
2026            pub const DIVIDE_60: u32 = 0x3b;
2027            #[doc = "Divide by 61"]
2028            pub const DIVIDE_61: u32 = 0x3c;
2029            #[doc = "Divide by 62"]
2030            pub const DIVIDE_62: u32 = 0x3d;
2031            #[doc = "Divide by 63"]
2032            pub const DIVIDE_63: u32 = 0x3e;
2033            #[doc = "Divide by 64"]
2034            pub const DIVIDE_64: u32 = 0x3f;
2035        }
2036    }
2037}
2038#[doc = "CCM Serial Clock Divider Register 3"]
2039pub mod CSCDR3 {
2040    #[doc = "Selector for csi_mclk multiplexer"]
2041    pub mod CSI_CLK_SEL {
2042        pub const offset: u32 = 9;
2043        pub const mask: u32 = 0x03 << offset;
2044        pub mod R {}
2045        pub mod W {}
2046        pub mod RW {
2047            #[doc = "derive clock from osc_clk (24M)"]
2048            pub const CSI_CLK_SEL_0: u32 = 0;
2049            #[doc = "derive clock from PLL2 PFD2"]
2050            pub const CSI_CLK_SEL_1: u32 = 0x01;
2051            #[doc = "derive clock from pll3_120M"]
2052            pub const CSI_CLK_SEL_2: u32 = 0x02;
2053            #[doc = "derive clock from PLL3 PFD1"]
2054            pub const CSI_CLK_SEL_3: u32 = 0x03;
2055        }
2056    }
2057    #[doc = "Post divider for csi_mclk. Divider should be updated when output clock is gated."]
2058    pub mod CSI_PODF {
2059        pub const offset: u32 = 11;
2060        pub const mask: u32 = 0x07 << offset;
2061        pub mod R {}
2062        pub mod W {}
2063        pub mod RW {
2064            #[doc = "divide by 1"]
2065            pub const CSI_PODF_0: u32 = 0;
2066            #[doc = "divide by 2"]
2067            pub const CSI_PODF_1: u32 = 0x01;
2068            #[doc = "divide by 3"]
2069            pub const CSI_PODF_2: u32 = 0x02;
2070            #[doc = "divide by 4"]
2071            pub const CSI_PODF_3: u32 = 0x03;
2072            #[doc = "divide by 5"]
2073            pub const CSI_PODF_4: u32 = 0x04;
2074            #[doc = "divide by 6"]
2075            pub const CSI_PODF_5: u32 = 0x05;
2076            #[doc = "divide by 7"]
2077            pub const CSI_PODF_6: u32 = 0x06;
2078            #[doc = "divide by 8"]
2079            pub const CSI_PODF_7: u32 = 0x07;
2080        }
2081    }
2082}
2083#[doc = "CCM Divider Handshake In-Process Register"]
2084pub mod CDHIPR {
2085    #[doc = "Busy indicator for semc_podf."]
2086    pub mod SEMC_PODF_BUSY {
2087        pub const offset: u32 = 0;
2088        pub const mask: u32 = 0x01 << offset;
2089        pub mod R {}
2090        pub mod W {}
2091        pub mod RW {
2092            #[doc = "divider is not busy and its value represents the actual division."]
2093            pub const SEMC_PODF_BUSY_0: u32 = 0;
2094            #[doc = "divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the semc_podf will be applied."]
2095            pub const SEMC_PODF_BUSY_1: u32 = 0x01;
2096        }
2097    }
2098    #[doc = "Busy indicator for ahb_podf."]
2099    pub mod AHB_PODF_BUSY {
2100        pub const offset: u32 = 1;
2101        pub const mask: u32 = 0x01 << offset;
2102        pub mod R {}
2103        pub mod W {}
2104        pub mod RW {
2105            #[doc = "divider is not busy and its value represents the actual division."]
2106            pub const AHB_PODF_BUSY_0: u32 = 0;
2107            #[doc = "divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the ahb_podf will be applied."]
2108            pub const AHB_PODF_BUSY_1: u32 = 0x01;
2109        }
2110    }
2111    #[doc = "Busy indicator for periph2_clk_sel mux control."]
2112    pub mod PERIPH2_CLK_SEL_BUSY {
2113        pub const offset: u32 = 3;
2114        pub const mask: u32 = 0x01 << offset;
2115        pub mod R {}
2116        pub mod W {}
2117        pub mod RW {
2118            #[doc = "mux is not busy and its value represents the actual division."]
2119            pub const PERIPH2_CLK_SEL_BUSY_0: u32 = 0;
2120            #[doc = "mux is busy with handshake process with module. The value read in the periph2_clk_sel represents the previous value of select, and after the handshake periph2_clk_sel value will be applied."]
2121            pub const PERIPH2_CLK_SEL_BUSY_1: u32 = 0x01;
2122        }
2123    }
2124    #[doc = "Busy indicator for periph_clk_sel mux control."]
2125    pub mod PERIPH_CLK_SEL_BUSY {
2126        pub const offset: u32 = 5;
2127        pub const mask: u32 = 0x01 << offset;
2128        pub mod R {}
2129        pub mod W {}
2130        pub mod RW {
2131            #[doc = "mux is not busy and its value represents the actual division."]
2132            pub const PERIPH_CLK_SEL_BUSY_0: u32 = 0;
2133            #[doc = "mux is busy with handshake process with module. The value read in the periph_clk_sel represents the previous value of select, and after the handshake periph_clk_sel value will be applied."]
2134            pub const PERIPH_CLK_SEL_BUSY_1: u32 = 0x01;
2135        }
2136    }
2137    #[doc = "Busy indicator for arm_podf."]
2138    pub mod ARM_PODF_BUSY {
2139        pub const offset: u32 = 16;
2140        pub const mask: u32 = 0x01 << offset;
2141        pub mod R {}
2142        pub mod W {}
2143        pub mod RW {
2144            #[doc = "divider is not busy and its value represents the actual division."]
2145            pub const ARM_PODF_BUSY_0: u32 = 0;
2146            #[doc = "divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the arm_podf will be applied."]
2147            pub const ARM_PODF_BUSY_1: u32 = 0x01;
2148        }
2149    }
2150}
2151#[doc = "CCM Low Power Control Register"]
2152pub mod CLPCR {
2153    #[doc = "Setting the low power mode that system will enter on next assertion of dsm_request signal."]
2154    pub mod LPM {
2155        pub const offset: u32 = 0;
2156        pub const mask: u32 = 0x03 << offset;
2157        pub mod R {}
2158        pub mod W {}
2159        pub mod RW {
2160            #[doc = "Remain in run mode"]
2161            pub const LPM_0: u32 = 0;
2162            #[doc = "Transfer to wait mode"]
2163            pub const LPM_1: u32 = 0x01;
2164            #[doc = "Transfer to stop mode"]
2165            pub const LPM_2: u32 = 0x02;
2166        }
2167    }
2168    #[doc = "Define if ARM clocks (arm_clk, soc_mxclk, soc_pclk, soc_dbg_pclk, vl_wrck) will be disabled on wait mode"]
2169    pub mod ARM_CLK_DIS_ON_LPM {
2170        pub const offset: u32 = 5;
2171        pub const mask: u32 = 0x01 << offset;
2172        pub mod R {}
2173        pub mod W {}
2174        pub mod RW {
2175            #[doc = "ARM clock enabled on wait mode."]
2176            pub const ARM_CLK_DIS_ON_LPM_0: u32 = 0;
2177            #[doc = "ARM clock disabled on wait mode. ."]
2178            pub const ARM_CLK_DIS_ON_LPM_1: u32 = 0x01;
2179        }
2180    }
2181    #[doc = "Standby clock oscillator bit"]
2182    pub mod SBYOS {
2183        pub const offset: u32 = 6;
2184        pub const mask: u32 = 0x01 << offset;
2185        pub mod R {}
2186        pub mod W {}
2187        pub mod RW {
2188            #[doc = "On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain asserted - '0' and cosc_pwrdown will remain de asserted - '0')"]
2189            pub const SBYOS_0: u32 = 0;
2190            #[doc = "On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will continue with the exit from the STOP mode process."]
2191            pub const SBYOS_1: u32 = 0x01;
2192        }
2193    }
2194    #[doc = "dis_ref_osc - in run mode, software can manually control closing of external reference oscillator clock, i"]
2195    pub mod DIS_REF_OSC {
2196        pub const offset: u32 = 7;
2197        pub const mask: u32 = 0x01 << offset;
2198        pub mod R {}
2199        pub mod W {}
2200        pub mod RW {
2201            #[doc = "external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'."]
2202            pub const DIS_REF_OSC_0: u32 = 0;
2203            #[doc = "external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1'"]
2204            pub const DIS_REF_OSC_1: u32 = 0x01;
2205        }
2206    }
2207    #[doc = "Voltage standby request bit"]
2208    pub mod VSTBY {
2209        pub const offset: u32 = 8;
2210        pub const mask: u32 = 0x01 << offset;
2211        pub mod R {}
2212        pub mod W {}
2213        pub mod RW {
2214            #[doc = "Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0')"]
2215            pub const VSTBY_0: u32 = 0;
2216            #[doc = "Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1')."]
2217            pub const VSTBY_1: u32 = 0x01;
2218        }
2219    }
2220    #[doc = "Standby counter definition"]
2221    pub mod STBY_COUNT {
2222        pub const offset: u32 = 9;
2223        pub const mask: u32 = 0x03 << offset;
2224        pub mod R {}
2225        pub mod W {}
2226        pub mod RW {
2227            #[doc = "CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles"]
2228            pub const STBY_COUNT_0: u32 = 0;
2229            #[doc = "CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles"]
2230            pub const STBY_COUNT_1: u32 = 0x01;
2231            #[doc = "CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles"]
2232            pub const STBY_COUNT_2: u32 = 0x02;
2233            #[doc = "CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles"]
2234            pub const STBY_COUNT_3: u32 = 0x03;
2235        }
2236    }
2237    #[doc = "In run mode, software can manually control powering down of on chip oscillator, i"]
2238    pub mod COSC_PWRDOWN {
2239        pub const offset: u32 = 11;
2240        pub const mask: u32 = 0x01 << offset;
2241        pub mod R {}
2242        pub mod W {}
2243        pub mod RW {
2244            #[doc = "On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'."]
2245            pub const COSC_PWRDOWN_0: u32 = 0;
2246            #[doc = "On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'."]
2247            pub const COSC_PWRDOWN_1: u32 = 0x01;
2248        }
2249    }
2250    #[doc = "Bypass low power mode handshake. This bit should always be set to 1'b1 by software."]
2251    pub mod BYPASS_LPM_HS1 {
2252        pub const offset: u32 = 19;
2253        pub const mask: u32 = 0x01 << offset;
2254        pub mod R {}
2255        pub mod W {}
2256        pub mod RW {}
2257    }
2258    #[doc = "Bypass low power mode handshake. This bit should always be set to 1'b1 by software."]
2259    pub mod BYPASS_LPM_HS0 {
2260        pub const offset: u32 = 21;
2261        pub const mask: u32 = 0x01 << offset;
2262        pub mod R {}
2263        pub mod W {}
2264        pub mod RW {}
2265    }
2266    #[doc = "Mask WFI of core0 for entering low power mode Assertion of all bits\\[27:22\\] will generate low power mode request"]
2267    pub mod MASK_CORE0_WFI {
2268        pub const offset: u32 = 22;
2269        pub const mask: u32 = 0x01 << offset;
2270        pub mod R {}
2271        pub mod W {}
2272        pub mod RW {
2273            #[doc = "WFI of core0 is not masked"]
2274            pub const MASK_CORE0_WFI_0: u32 = 0;
2275            #[doc = "WFI of core0 is masked"]
2276            pub const MASK_CORE0_WFI_1: u32 = 0x01;
2277        }
2278    }
2279    #[doc = "Mask SCU IDLE for entering low power mode Assertion of all bits\\[27:22\\] will generate low power mode request"]
2280    pub mod MASK_SCU_IDLE {
2281        pub const offset: u32 = 26;
2282        pub const mask: u32 = 0x01 << offset;
2283        pub mod R {}
2284        pub mod W {}
2285        pub mod RW {
2286            #[doc = "SCU IDLE is not masked"]
2287            pub const MASK_SCU_IDLE_0: u32 = 0;
2288            #[doc = "SCU IDLE is masked"]
2289            pub const MASK_SCU_IDLE_1: u32 = 0x01;
2290        }
2291    }
2292    #[doc = "Mask L2CC IDLE for entering low power mode"]
2293    pub mod MASK_L2CC_IDLE {
2294        pub const offset: u32 = 27;
2295        pub const mask: u32 = 0x01 << offset;
2296        pub mod R {}
2297        pub mod W {}
2298        pub mod RW {
2299            #[doc = "L2CC IDLE is not masked"]
2300            pub const MASK_L2CC_IDLE_0: u32 = 0;
2301            #[doc = "L2CC IDLE is masked"]
2302            pub const MASK_L2CC_IDLE_1: u32 = 0x01;
2303        }
2304    }
2305}
2306#[doc = "CCM Interrupt Status Register"]
2307pub mod CISR {
2308    #[doc = "CCM interrupt request 2 generated due to lock of all enabled and not bypaseed PLLs"]
2309    pub mod LRF_PLL {
2310        pub const offset: u32 = 0;
2311        pub const mask: u32 = 0x01 << offset;
2312        pub mod R {}
2313        pub mod W {}
2314        pub mod RW {
2315            #[doc = "interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs"]
2316            pub const LRF_PLL_0: u32 = 0;
2317            #[doc = "interrupt generated due to lock ready of all enabled and not bypaseed PLLs"]
2318            pub const LRF_PLL_1: u32 = 0x01;
2319        }
2320    }
2321    #[doc = "CCM interrupt request 2 generated due to on board oscillator ready, i"]
2322    pub mod COSC_READY {
2323        pub const offset: u32 = 6;
2324        pub const mask: u32 = 0x01 << offset;
2325        pub mod R {}
2326        pub mod W {}
2327        pub mod RW {
2328            #[doc = "interrupt is not generated due to on board oscillator ready"]
2329            pub const COSC_READY_0: u32 = 0;
2330            #[doc = "interrupt generated due to on board oscillator ready"]
2331            pub const COSC_READY_1: u32 = 0x01;
2332        }
2333    }
2334    #[doc = "CCM interrupt request 1 generated due to frequency change of semc_podf"]
2335    pub mod SEMC_PODF_LOADED {
2336        pub const offset: u32 = 17;
2337        pub const mask: u32 = 0x01 << offset;
2338        pub mod R {}
2339        pub mod W {}
2340        pub mod RW {
2341            #[doc = "interrupt is not generated due to frequency change of semc_podf"]
2342            pub const SEMC_PODF_LOADED_0: u32 = 0;
2343            #[doc = "interrupt generated due to frequency change of semc_podf"]
2344            pub const SEMC_PODF_LOADED_1: u32 = 0x01;
2345        }
2346    }
2347    #[doc = "CCM interrupt request 1 generated due to frequency change of periph2_clk_sel"]
2348    pub mod PERIPH2_CLK_SEL_LOADED {
2349        pub const offset: u32 = 19;
2350        pub const mask: u32 = 0x01 << offset;
2351        pub mod R {}
2352        pub mod W {}
2353        pub mod RW {
2354            #[doc = "interrupt is not generated due to frequency change of periph2_clk_sel"]
2355            pub const PERIPH2_CLK_SEL_LOADED_0: u32 = 0;
2356            #[doc = "interrupt generated due to frequency change of periph2_clk_sel"]
2357            pub const PERIPH2_CLK_SEL_LOADED_1: u32 = 0x01;
2358        }
2359    }
2360    #[doc = "CCM interrupt request 1 generated due to frequency change of ahb_podf"]
2361    pub mod AHB_PODF_LOADED {
2362        pub const offset: u32 = 20;
2363        pub const mask: u32 = 0x01 << offset;
2364        pub mod R {}
2365        pub mod W {}
2366        pub mod RW {
2367            #[doc = "interrupt is not generated due to frequency change of ahb_podf"]
2368            pub const AHB_PODF_LOADED_0: u32 = 0;
2369            #[doc = "interrupt generated due to frequency change of ahb_podf"]
2370            pub const AHB_PODF_LOADED_1: u32 = 0x01;
2371        }
2372    }
2373    #[doc = "CCM interrupt request 1 generated due to update of periph_clk_sel."]
2374    pub mod PERIPH_CLK_SEL_LOADED {
2375        pub const offset: u32 = 22;
2376        pub const mask: u32 = 0x01 << offset;
2377        pub mod R {}
2378        pub mod W {}
2379        pub mod RW {
2380            #[doc = "interrupt is not generated due to update of periph_clk_sel."]
2381            pub const PERIPH_CLK_SEL_LOADED_0: u32 = 0;
2382            #[doc = "interrupt generated due to update of periph_clk_sel."]
2383            pub const PERIPH_CLK_SEL_LOADED_1: u32 = 0x01;
2384        }
2385    }
2386    #[doc = "CCM interrupt request 1 generated due to frequency change of arm_podf"]
2387    pub mod ARM_PODF_LOADED {
2388        pub const offset: u32 = 26;
2389        pub const mask: u32 = 0x01 << offset;
2390        pub mod R {}
2391        pub mod W {}
2392        pub mod RW {
2393            #[doc = "interrupt is not generated due to frequency change of arm_podf"]
2394            pub const ARM_PODF_LOADED_0: u32 = 0;
2395            #[doc = "interrupt generated due to frequency change of arm_podf"]
2396            pub const ARM_PODF_LOADED_1: u32 = 0x01;
2397        }
2398    }
2399}
2400#[doc = "CCM Interrupt Mask Register"]
2401pub mod CIMR {
2402    #[doc = "mask interrupt generation due to lrf of PLLs"]
2403    pub mod MASK_LRF_PLL {
2404        pub const offset: u32 = 0;
2405        pub const mask: u32 = 0x01 << offset;
2406        pub mod R {}
2407        pub mod W {}
2408        pub mod RW {
2409            #[doc = "don't mask interrupt due to lrf of PLLs - interrupt will be created"]
2410            pub const MASK_LRF_PLL_0: u32 = 0;
2411            #[doc = "mask interrupt due to lrf of PLLs"]
2412            pub const MASK_LRF_PLL_1: u32 = 0x01;
2413        }
2414    }
2415    #[doc = "mask interrupt generation due to on board oscillator ready"]
2416    pub mod MASK_COSC_READY {
2417        pub const offset: u32 = 6;
2418        pub const mask: u32 = 0x01 << offset;
2419        pub mod R {}
2420        pub mod W {}
2421        pub mod RW {
2422            #[doc = "don't mask interrupt due to on board oscillator ready - interrupt will be created"]
2423            pub const MASK_COSC_READY_0: u32 = 0;
2424            #[doc = "mask interrupt due to on board oscillator ready"]
2425            pub const MASK_COSC_READY_1: u32 = 0x01;
2426        }
2427    }
2428    #[doc = "mask interrupt generation due to frequency change of semc_podf"]
2429    pub mod MASK_SEMC_PODF_LOADED {
2430        pub const offset: u32 = 17;
2431        pub const mask: u32 = 0x01 << offset;
2432        pub mod R {}
2433        pub mod W {}
2434        pub mod RW {
2435            #[doc = "don't mask interrupt due to frequency change of semc_podf - interrupt will be created"]
2436            pub const MASK_SEMC_PODF_LOADED_0: u32 = 0;
2437            #[doc = "mask interrupt due to frequency change of semc_podf"]
2438            pub const MASK_SEMC_PODF_LOADED_1: u32 = 0x01;
2439        }
2440    }
2441    #[doc = "mask interrupt generation due to update of periph2_clk_sel."]
2442    pub mod MASK_PERIPH2_CLK_SEL_LOADED {
2443        pub const offset: u32 = 19;
2444        pub const mask: u32 = 0x01 << offset;
2445        pub mod R {}
2446        pub mod W {}
2447        pub mod RW {
2448            #[doc = "don't mask interrupt due to update of periph2_clk_sel - interrupt will be created"]
2449            pub const MASK_PERIPH2_CLK_SEL_LOADED_0: u32 = 0;
2450            #[doc = "mask interrupt due to update of periph2_clk_sel"]
2451            pub const MASK_PERIPH2_CLK_SEL_LOADED_1: u32 = 0x01;
2452        }
2453    }
2454    #[doc = "mask interrupt generation due to frequency change of ahb_podf"]
2455    pub mod MASK_AHB_PODF_LOADED {
2456        pub const offset: u32 = 20;
2457        pub const mask: u32 = 0x01 << offset;
2458        pub mod R {}
2459        pub mod W {}
2460        pub mod RW {
2461            #[doc = "don't mask interrupt due to frequency change of ahb_podf - interrupt will be created"]
2462            pub const MASK_AHB_PODF_LOADED_0: u32 = 0;
2463            #[doc = "mask interrupt due to frequency change of ahb_podf"]
2464            pub const MASK_AHB_PODF_LOADED_1: u32 = 0x01;
2465        }
2466    }
2467    #[doc = "mask interrupt generation due to update of periph_clk_sel."]
2468    pub mod MASK_PERIPH_CLK_SEL_LOADED {
2469        pub const offset: u32 = 22;
2470        pub const mask: u32 = 0x01 << offset;
2471        pub mod R {}
2472        pub mod W {}
2473        pub mod RW {
2474            #[doc = "don't mask interrupt due to update of periph_clk_sel - interrupt will be created"]
2475            pub const MASK_PERIPH_CLK_SEL_LOADED_0: u32 = 0;
2476            #[doc = "mask interrupt due to update of periph_clk_sel"]
2477            pub const MASK_PERIPH_CLK_SEL_LOADED_1: u32 = 0x01;
2478        }
2479    }
2480    #[doc = "mask interrupt generation due to frequency change of arm_podf"]
2481    pub mod ARM_PODF_LOADED {
2482        pub const offset: u32 = 26;
2483        pub const mask: u32 = 0x01 << offset;
2484        pub mod R {}
2485        pub mod W {}
2486        pub mod RW {
2487            #[doc = "don't mask interrupt due to frequency change of arm_podf - interrupt will be created"]
2488            pub const ARM_PODF_LOADED_0: u32 = 0;
2489            #[doc = "mask interrupt due to frequency change of arm_podf"]
2490            pub const ARM_PODF_LOADED_1: u32 = 0x01;
2491        }
2492    }
2493}
2494#[doc = "CCM Clock Output Source Register"]
2495pub mod CCOSR {
2496    #[doc = "Selection of the clock to be generated on CCM_CLKO1"]
2497    pub mod CLKO1_SEL {
2498        pub const offset: u32 = 0;
2499        pub const mask: u32 = 0x0f << offset;
2500        pub mod R {}
2501        pub mod W {}
2502        pub mod RW {
2503            #[doc = "USB1 PLL clock (divided by 2)"]
2504            pub const CLKO1_SEL_0: u32 = 0;
2505            #[doc = "SYS PLL clock (divided by 2)"]
2506            pub const CLKO1_SEL_1: u32 = 0x01;
2507            #[doc = "VIDEO PLL clock (divided by 2)"]
2508            pub const CLKO1_SEL_3: u32 = 0x03;
2509            #[doc = "semc_clk_root"]
2510            pub const CLKO1_SEL_5: u32 = 0x05;
2511            #[doc = "lcdif_pix_clk_root"]
2512            pub const CLKO1_SEL_10: u32 = 0x0a;
2513            #[doc = "ahb_clk_root"]
2514            pub const CLKO1_SEL_11: u32 = 0x0b;
2515            #[doc = "ipg_clk_root"]
2516            pub const CLKO1_SEL_12: u32 = 0x0c;
2517            #[doc = "perclk_root"]
2518            pub const CLKO1_SEL_13: u32 = 0x0d;
2519            #[doc = "ckil_sync_clk_root"]
2520            pub const CLKO1_SEL_14: u32 = 0x0e;
2521            #[doc = "pll4_main_clk"]
2522            pub const CLKO1_SEL_15: u32 = 0x0f;
2523        }
2524    }
2525    #[doc = "Setting the divider of CCM_CLKO1"]
2526    pub mod CLKO1_DIV {
2527        pub const offset: u32 = 4;
2528        pub const mask: u32 = 0x07 << offset;
2529        pub mod R {}
2530        pub mod W {}
2531        pub mod RW {
2532            #[doc = "divide by 1"]
2533            pub const CLKO1_DIV_0: u32 = 0;
2534            #[doc = "divide by 2"]
2535            pub const CLKO1_DIV_1: u32 = 0x01;
2536            #[doc = "divide by 3"]
2537            pub const CLKO1_DIV_2: u32 = 0x02;
2538            #[doc = "divide by 4"]
2539            pub const CLKO1_DIV_3: u32 = 0x03;
2540            #[doc = "divide by 5"]
2541            pub const CLKO1_DIV_4: u32 = 0x04;
2542            #[doc = "divide by 6"]
2543            pub const CLKO1_DIV_5: u32 = 0x05;
2544            #[doc = "divide by 7"]
2545            pub const CLKO1_DIV_6: u32 = 0x06;
2546            #[doc = "divide by 8"]
2547            pub const CLKO1_DIV_7: u32 = 0x07;
2548        }
2549    }
2550    #[doc = "Enable of CCM_CLKO1 clock"]
2551    pub mod CLKO1_EN {
2552        pub const offset: u32 = 7;
2553        pub const mask: u32 = 0x01 << offset;
2554        pub mod R {}
2555        pub mod W {}
2556        pub mod RW {
2557            #[doc = "CCM_CLKO1 disabled."]
2558            pub const CLKO1_EN_0: u32 = 0;
2559            #[doc = "CCM_CLKO1 enabled."]
2560            pub const CLKO1_EN_1: u32 = 0x01;
2561        }
2562    }
2563    #[doc = "CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks"]
2564    pub mod CLK_OUT_SEL {
2565        pub const offset: u32 = 8;
2566        pub const mask: u32 = 0x01 << offset;
2567        pub mod R {}
2568        pub mod W {}
2569        pub mod RW {
2570            #[doc = "CCM_CLKO1 output drives CCM_CLKO1 clock"]
2571            pub const CLK_OUT_SEL_0: u32 = 0;
2572            #[doc = "CCM_CLKO1 output drives CCM_CLKO2 clock"]
2573            pub const CLK_OUT_SEL_1: u32 = 0x01;
2574        }
2575    }
2576    #[doc = "Selection of the clock to be generated on CCM_CLKO2"]
2577    pub mod CLKO2_SEL {
2578        pub const offset: u32 = 16;
2579        pub const mask: u32 = 0x1f << offset;
2580        pub mod R {}
2581        pub mod W {}
2582        pub mod RW {
2583            #[doc = "usdhc1_clk_root"]
2584            pub const CLKO2_SEL_3: u32 = 0x03;
2585            #[doc = "lpi2c_clk_root"]
2586            pub const CLKO2_SEL_6: u32 = 0x06;
2587            #[doc = "csi_clk_root"]
2588            pub const CLKO2_SEL_11: u32 = 0x0b;
2589            #[doc = "osc_clk"]
2590            pub const CLKO2_SEL_14: u32 = 0x0e;
2591            #[doc = "usdhc2_clk_root"]
2592            pub const CLKO2_SEL_17: u32 = 0x11;
2593            #[doc = "sai1_clk_root"]
2594            pub const CLKO2_SEL_18: u32 = 0x12;
2595            #[doc = "sai2_clk_root"]
2596            pub const CLKO2_SEL_19: u32 = 0x13;
2597            #[doc = "sai3_clk_root (shared with ADC1 and ADC2 alt_clk root)"]
2598            pub const CLKO2_SEL_20: u32 = 0x14;
2599            #[doc = "can_clk_root (FlexCAN, shared with CANFD)"]
2600            pub const CLKO2_SEL_23: u32 = 0x17;
2601            #[doc = "flexspi_clk_root"]
2602            pub const CLKO2_SEL_27: u32 = 0x1b;
2603            #[doc = "uart_clk_root"]
2604            pub const CLKO2_SEL_28: u32 = 0x1c;
2605            #[doc = "spdif0_clk_root"]
2606            pub const CLKO2_SEL_29: u32 = 0x1d;
2607        }
2608    }
2609    #[doc = "Setting the divider of CCM_CLKO2"]
2610    pub mod CLKO2_DIV {
2611        pub const offset: u32 = 21;
2612        pub const mask: u32 = 0x07 << offset;
2613        pub mod R {}
2614        pub mod W {}
2615        pub mod RW {
2616            #[doc = "divide by 1"]
2617            pub const CLKO2_DIV_0: u32 = 0;
2618            #[doc = "divide by 2"]
2619            pub const CLKO2_DIV_1: u32 = 0x01;
2620            #[doc = "divide by 3"]
2621            pub const CLKO2_DIV_2: u32 = 0x02;
2622            #[doc = "divide by 4"]
2623            pub const CLKO2_DIV_3: u32 = 0x03;
2624            #[doc = "divide by 5"]
2625            pub const CLKO2_DIV_4: u32 = 0x04;
2626            #[doc = "divide by 6"]
2627            pub const CLKO2_DIV_5: u32 = 0x05;
2628            #[doc = "divide by 7"]
2629            pub const CLKO2_DIV_6: u32 = 0x06;
2630            #[doc = "divide by 8"]
2631            pub const CLKO2_DIV_7: u32 = 0x07;
2632        }
2633    }
2634    #[doc = "Enable of CCM_CLKO2 clock"]
2635    pub mod CLKO2_EN {
2636        pub const offset: u32 = 24;
2637        pub const mask: u32 = 0x01 << offset;
2638        pub mod R {}
2639        pub mod W {}
2640        pub mod RW {
2641            #[doc = "CCM_CLKO2 disabled."]
2642            pub const CLKO2_EN_0: u32 = 0;
2643            #[doc = "CCM_CLKO2 enabled."]
2644            pub const CLKO2_EN_1: u32 = 0x01;
2645        }
2646    }
2647}
2648#[doc = "CCM General Purpose Register"]
2649pub mod CGPR {
2650    #[doc = "Defines clock dividion of clock for stby_count (pmic delay counter)"]
2651    pub mod PMIC_DELAY_SCALER {
2652        pub const offset: u32 = 0;
2653        pub const mask: u32 = 0x01 << offset;
2654        pub mod R {}
2655        pub mod W {}
2656        pub mod RW {
2657            #[doc = "clock is not divided"]
2658            pub const PMIC_DELAY_SCALER_0: u32 = 0;
2659            #[doc = "clock is divided /8"]
2660            pub const PMIC_DELAY_SCALER_1: u32 = 0x01;
2661        }
2662    }
2663    #[doc = "Defines the value of the output signal cgpr_dout\\[4\\]. Gate of program supply for efuse programing"]
2664    pub mod EFUSE_PROG_SUPPLY_GATE {
2665        pub const offset: u32 = 4;
2666        pub const mask: u32 = 0x01 << offset;
2667        pub mod R {}
2668        pub mod W {}
2669        pub mod RW {
2670            #[doc = "fuse programing supply voltage is gated off to the efuse module"]
2671            pub const EFUSE_PROG_SUPPLY_GATE_0: u32 = 0;
2672            #[doc = "allow fuse programing."]
2673            pub const EFUSE_PROG_SUPPLY_GATE_1: u32 = 0x01;
2674        }
2675    }
2676    #[doc = "System memory DS control"]
2677    pub mod SYS_MEM_DS_CTRL {
2678        pub const offset: u32 = 14;
2679        pub const mask: u32 = 0x03 << offset;
2680        pub mod R {}
2681        pub mod W {}
2682        pub mod RW {
2683            #[doc = "Disable memory DS mode always"]
2684            pub const SYS_MEM_DS_CTRL_0: u32 = 0;
2685            #[doc = "Enable memory (outside ARM platform) DS mode when system STOP and PLL are disabled"]
2686            pub const SYS_MEM_DS_CTRL_1: u32 = 0x01;
2687            #[doc = "enable memory (outside ARM platform) DS mode when system is in STOP mode"]
2688            pub const SYS_MEM_DS_CTRL_2: u32 = 0x02;
2689        }
2690    }
2691    #[doc = "Fast PLL enable."]
2692    pub mod FPL {
2693        pub const offset: u32 = 16;
2694        pub const mask: u32 = 0x01 << offset;
2695        pub mod R {}
2696        pub mod W {}
2697        pub mod RW {
2698            #[doc = "Engage PLL enable default way."]
2699            pub const FPL_0: u32 = 0;
2700            #[doc = "Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode."]
2701            pub const FPL_1: u32 = 0x01;
2702        }
2703    }
2704    #[doc = "Control for the Deep Sleep signal to the ARM Platform memories with additional control logic based on the ARM WFI signal"]
2705    pub mod INT_MEM_CLK_LPM {
2706        pub const offset: u32 = 17;
2707        pub const mask: u32 = 0x01 << offset;
2708        pub mod R {}
2709        pub mod W {}
2710        pub mod RW {
2711            #[doc = "Disable the clock to the ARM platform memories when entering Low Power Mode"]
2712            pub const INT_MEM_CLK_LPM_0: u32 = 0;
2713            #[doc = "Keep the clocks to the ARM platform memories enabled only if an interrupt is pending when entering Low Power Modes (WAIT and STOP without power gating)"]
2714            pub const INT_MEM_CLK_LPM_1: u32 = 0x01;
2715        }
2716    }
2717}
2718#[doc = "CCM Clock Gating Register 0"]
2719pub mod CCGR0 {
2720    #[doc = "aips_tz1 clocks (aips_tz1_clk_enable)"]
2721    pub mod CG0 {
2722        pub const offset: u32 = 0;
2723        pub const mask: u32 = 0x03 << offset;
2724        pub mod R {}
2725        pub mod W {}
2726        pub mod RW {}
2727    }
2728    #[doc = "aips_tz2 clocks (aips_tz2_clk_enable)"]
2729    pub mod CG1 {
2730        pub const offset: u32 = 2;
2731        pub const mask: u32 = 0x03 << offset;
2732        pub mod R {}
2733        pub mod W {}
2734        pub mod RW {}
2735    }
2736    #[doc = "mqs clock ( mqs_hmclk_clock_enable)"]
2737    pub mod CG2 {
2738        pub const offset: u32 = 4;
2739        pub const mask: u32 = 0x03 << offset;
2740        pub mod R {}
2741        pub mod W {}
2742        pub mod RW {}
2743    }
2744    #[doc = "flexspi_exsc clock (flexspi_exsc_clk_enable)"]
2745    pub mod CG3 {
2746        pub const offset: u32 = 6;
2747        pub const mask: u32 = 0x03 << offset;
2748        pub mod R {}
2749        pub mod W {}
2750        pub mod RW {}
2751    }
2752    #[doc = "sim_m or sim_main register access clock (sim_m_mainclk_r_enable)"]
2753    pub mod CG4 {
2754        pub const offset: u32 = 8;
2755        pub const mask: u32 = 0x03 << offset;
2756        pub mod R {}
2757        pub mod W {}
2758        pub mod RW {}
2759    }
2760    #[doc = "dcp clock (dcp_clk_enable)"]
2761    pub mod CG5 {
2762        pub const offset: u32 = 10;
2763        pub const mask: u32 = 0x03 << offset;
2764        pub mod R {}
2765        pub mod W {}
2766        pub mod RW {}
2767    }
2768    #[doc = "lpuart3 clock (lpuart3_clk_enable)"]
2769    pub mod CG6 {
2770        pub const offset: u32 = 12;
2771        pub const mask: u32 = 0x03 << offset;
2772        pub mod R {}
2773        pub mod W {}
2774        pub mod RW {}
2775    }
2776    #[doc = "can1 clock (can1_clk_enable)"]
2777    pub mod CG7 {
2778        pub const offset: u32 = 14;
2779        pub const mask: u32 = 0x03 << offset;
2780        pub mod R {}
2781        pub mod W {}
2782        pub mod RW {}
2783    }
2784    #[doc = "can1_serial clock (can1_serial_clk_enable)"]
2785    pub mod CG8 {
2786        pub const offset: u32 = 16;
2787        pub const mask: u32 = 0x03 << offset;
2788        pub mod R {}
2789        pub mod W {}
2790        pub mod RW {}
2791    }
2792    #[doc = "can2 clock (can2_clk_enable)"]
2793    pub mod CG9 {
2794        pub const offset: u32 = 18;
2795        pub const mask: u32 = 0x03 << offset;
2796        pub mod R {}
2797        pub mod W {}
2798        pub mod RW {}
2799    }
2800    #[doc = "can2_serial clock (can2_serial_clk_enable)"]
2801    pub mod CG10 {
2802        pub const offset: u32 = 20;
2803        pub const mask: u32 = 0x03 << offset;
2804        pub mod R {}
2805        pub mod W {}
2806        pub mod RW {}
2807    }
2808    #[doc = "trace clock (trace_clk_enable)"]
2809    pub mod CG11 {
2810        pub const offset: u32 = 22;
2811        pub const mask: u32 = 0x03 << offset;
2812        pub mod R {}
2813        pub mod W {}
2814        pub mod RW {}
2815    }
2816    #[doc = "gpt2 bus clocks (gpt2_bus_clk_enable)"]
2817    pub mod CG12 {
2818        pub const offset: u32 = 24;
2819        pub const mask: u32 = 0x03 << offset;
2820        pub mod R {}
2821        pub mod W {}
2822        pub mod RW {}
2823    }
2824    #[doc = "gpt2 serial clocks (gpt2_serial_clk_enable)"]
2825    pub mod CG13 {
2826        pub const offset: u32 = 26;
2827        pub const mask: u32 = 0x03 << offset;
2828        pub mod R {}
2829        pub mod W {}
2830        pub mod RW {}
2831    }
2832    #[doc = "lpuart2 clock (lpuart2_clk_enable)"]
2833    pub mod CG14 {
2834        pub const offset: u32 = 28;
2835        pub const mask: u32 = 0x03 << offset;
2836        pub mod R {}
2837        pub mod W {}
2838        pub mod RW {}
2839    }
2840    #[doc = "gpio2_clocks (gpio2_clk_enable)"]
2841    pub mod CG15 {
2842        pub const offset: u32 = 30;
2843        pub const mask: u32 = 0x03 << offset;
2844        pub mod R {}
2845        pub mod W {}
2846        pub mod RW {}
2847    }
2848}
2849#[doc = "CCM Clock Gating Register 1"]
2850pub mod CCGR1 {
2851    #[doc = "lpspi1 clocks (lpspi1_clk_enable)"]
2852    pub mod CG0 {
2853        pub const offset: u32 = 0;
2854        pub const mask: u32 = 0x03 << offset;
2855        pub mod R {}
2856        pub mod W {}
2857        pub mod RW {}
2858    }
2859    #[doc = "lpspi2 clocks (lpspi2_clk_enable)"]
2860    pub mod CG1 {
2861        pub const offset: u32 = 2;
2862        pub const mask: u32 = 0x03 << offset;
2863        pub mod R {}
2864        pub mod W {}
2865        pub mod RW {}
2866    }
2867    #[doc = "lpspi3 clocks (lpspi3_clk_enable)"]
2868    pub mod CG2 {
2869        pub const offset: u32 = 4;
2870        pub const mask: u32 = 0x03 << offset;
2871        pub mod R {}
2872        pub mod W {}
2873        pub mod RW {}
2874    }
2875    #[doc = "lpspi4 clocks (lpspi4_clk_enable)"]
2876    pub mod CG3 {
2877        pub const offset: u32 = 6;
2878        pub const mask: u32 = 0x03 << offset;
2879        pub mod R {}
2880        pub mod W {}
2881        pub mod RW {}
2882    }
2883    #[doc = "adc2 clock (adc2_clk_enable)"]
2884    pub mod CG4 {
2885        pub const offset: u32 = 8;
2886        pub const mask: u32 = 0x03 << offset;
2887        pub mod R {}
2888        pub mod W {}
2889        pub mod RW {}
2890    }
2891    #[doc = "enet clock (enet_clk_enable)"]
2892    pub mod CG5 {
2893        pub const offset: u32 = 10;
2894        pub const mask: u32 = 0x03 << offset;
2895        pub mod R {}
2896        pub mod W {}
2897        pub mod RW {}
2898    }
2899    #[doc = "pit clocks (pit_clk_enable)"]
2900    pub mod CG6 {
2901        pub const offset: u32 = 12;
2902        pub const mask: u32 = 0x03 << offset;
2903        pub mod R {}
2904        pub mod W {}
2905        pub mod RW {}
2906    }
2907    #[doc = "aoi2 clocks (aoi2_clk_enable)"]
2908    pub mod CG7 {
2909        pub const offset: u32 = 14;
2910        pub const mask: u32 = 0x03 << offset;
2911        pub mod R {}
2912        pub mod W {}
2913        pub mod RW {}
2914    }
2915    #[doc = "adc1 clock (adc1_clk_enable)"]
2916    pub mod CG8 {
2917        pub const offset: u32 = 16;
2918        pub const mask: u32 = 0x03 << offset;
2919        pub mod R {}
2920        pub mod W {}
2921        pub mod RW {}
2922    }
2923    #[doc = "semc_exsc clock (semc_exsc_clk_enable)"]
2924    pub mod CG9 {
2925        pub const offset: u32 = 18;
2926        pub const mask: u32 = 0x03 << offset;
2927        pub mod R {}
2928        pub mod W {}
2929        pub mod RW {}
2930    }
2931    #[doc = "gpt1 bus clock (gpt_clk_enable)"]
2932    pub mod CG10 {
2933        pub const offset: u32 = 20;
2934        pub const mask: u32 = 0x03 << offset;
2935        pub mod R {}
2936        pub mod W {}
2937        pub mod RW {}
2938    }
2939    #[doc = "gpt1 serial clock (gpt_serial_clk_enable)"]
2940    pub mod CG11 {
2941        pub const offset: u32 = 22;
2942        pub const mask: u32 = 0x03 << offset;
2943        pub mod R {}
2944        pub mod W {}
2945        pub mod RW {}
2946    }
2947    #[doc = "lpuart4 clock (lpuart4_clk_enable)"]
2948    pub mod CG12 {
2949        pub const offset: u32 = 24;
2950        pub const mask: u32 = 0x03 << offset;
2951        pub mod R {}
2952        pub mod W {}
2953        pub mod RW {}
2954    }
2955    #[doc = "gpio1 clock (gpio1_clk_enable)"]
2956    pub mod CG13 {
2957        pub const offset: u32 = 26;
2958        pub const mask: u32 = 0x03 << offset;
2959        pub mod R {}
2960        pub mod W {}
2961        pub mod RW {}
2962    }
2963    #[doc = "csu clock (csu_clk_enable)"]
2964    pub mod CG14 {
2965        pub const offset: u32 = 28;
2966        pub const mask: u32 = 0x03 << offset;
2967        pub mod R {}
2968        pub mod W {}
2969        pub mod RW {}
2970    }
2971    #[doc = "gpio5 clock (gpio5_clk_enable)"]
2972    pub mod CG15 {
2973        pub const offset: u32 = 30;
2974        pub const mask: u32 = 0x03 << offset;
2975        pub mod R {}
2976        pub mod W {}
2977        pub mod RW {}
2978    }
2979}
2980#[doc = "CCM Clock Gating Register 2"]
2981pub mod CCGR2 {
2982    #[doc = "ocram_exsc clock (ocram_exsc_clk_enable)"]
2983    pub mod CG0 {
2984        pub const offset: u32 = 0;
2985        pub const mask: u32 = 0x03 << offset;
2986        pub mod R {}
2987        pub mod W {}
2988        pub mod RW {}
2989    }
2990    #[doc = "csi clock (csi_clk_enable)"]
2991    pub mod CG1 {
2992        pub const offset: u32 = 2;
2993        pub const mask: u32 = 0x03 << offset;
2994        pub mod R {}
2995        pub mod W {}
2996        pub mod RW {}
2997    }
2998    #[doc = "iomuxc_snvs clock (iomuxc_snvs_clk_enable)"]
2999    pub mod CG2 {
3000        pub const offset: u32 = 4;
3001        pub const mask: u32 = 0x03 << offset;
3002        pub mod R {}
3003        pub mod W {}
3004        pub mod RW {}
3005    }
3006    #[doc = "lpi2c1 clock (lpi2c1_clk_enable)"]
3007    pub mod CG3 {
3008        pub const offset: u32 = 6;
3009        pub const mask: u32 = 0x03 << offset;
3010        pub mod R {}
3011        pub mod W {}
3012        pub mod RW {}
3013    }
3014    #[doc = "lpi2c2 clock (lpi2c2_clk_enable)"]
3015    pub mod CG4 {
3016        pub const offset: u32 = 8;
3017        pub const mask: u32 = 0x03 << offset;
3018        pub mod R {}
3019        pub mod W {}
3020        pub mod RW {}
3021    }
3022    #[doc = "lpi2c3 clock (lpi2c3_clk_enable)"]
3023    pub mod CG5 {
3024        pub const offset: u32 = 10;
3025        pub const mask: u32 = 0x03 << offset;
3026        pub mod R {}
3027        pub mod W {}
3028        pub mod RW {}
3029    }
3030    #[doc = "OCOTP_CTRL clock (iim_clk_enable)"]
3031    pub mod CG6 {
3032        pub const offset: u32 = 12;
3033        pub const mask: u32 = 0x03 << offset;
3034        pub mod R {}
3035        pub mod W {}
3036        pub mod RW {}
3037    }
3038    #[doc = "xbar3 clock (xbar3_clk_enable)"]
3039    pub mod CG7 {
3040        pub const offset: u32 = 14;
3041        pub const mask: u32 = 0x03 << offset;
3042        pub mod R {}
3043        pub mod W {}
3044        pub mod RW {}
3045    }
3046    #[doc = "ipmux1 clock (ipmux1_clk_enable)"]
3047    pub mod CG8 {
3048        pub const offset: u32 = 16;
3049        pub const mask: u32 = 0x03 << offset;
3050        pub mod R {}
3051        pub mod W {}
3052        pub mod RW {}
3053    }
3054    #[doc = "ipmux2 clock (ipmux2_clk_enable)"]
3055    pub mod CG9 {
3056        pub const offset: u32 = 18;
3057        pub const mask: u32 = 0x03 << offset;
3058        pub mod R {}
3059        pub mod W {}
3060        pub mod RW {}
3061    }
3062    #[doc = "ipmux3 clock (ipmux3_clk_enable)"]
3063    pub mod CG10 {
3064        pub const offset: u32 = 20;
3065        pub const mask: u32 = 0x03 << offset;
3066        pub mod R {}
3067        pub mod W {}
3068        pub mod RW {}
3069    }
3070    #[doc = "xbar1 clock (xbar1_clk_enable)"]
3071    pub mod CG11 {
3072        pub const offset: u32 = 22;
3073        pub const mask: u32 = 0x03 << offset;
3074        pub mod R {}
3075        pub mod W {}
3076        pub mod RW {}
3077    }
3078    #[doc = "xbar2 clock (xbar2_clk_enable)"]
3079    pub mod CG12 {
3080        pub const offset: u32 = 24;
3081        pub const mask: u32 = 0x03 << offset;
3082        pub mod R {}
3083        pub mod W {}
3084        pub mod RW {}
3085    }
3086    #[doc = "gpio3 clock (gpio3_clk_enable)"]
3087    pub mod CG13 {
3088        pub const offset: u32 = 26;
3089        pub const mask: u32 = 0x03 << offset;
3090        pub mod R {}
3091        pub mod W {}
3092        pub mod RW {}
3093    }
3094    #[doc = "lcd clocks (lcd_clk_enable)"]
3095    pub mod CG14 {
3096        pub const offset: u32 = 28;
3097        pub const mask: u32 = 0x03 << offset;
3098        pub mod R {}
3099        pub mod W {}
3100        pub mod RW {}
3101    }
3102    #[doc = "pxp clocks (pxp_clk_enable)"]
3103    pub mod CG15 {
3104        pub const offset: u32 = 30;
3105        pub const mask: u32 = 0x03 << offset;
3106        pub mod R {}
3107        pub mod W {}
3108        pub mod RW {}
3109    }
3110}
3111#[doc = "CCM Clock Gating Register 3"]
3112pub mod CCGR3 {
3113    #[doc = "flexio2 clocks (flexio2_clk_enable)"]
3114    pub mod CG0 {
3115        pub const offset: u32 = 0;
3116        pub const mask: u32 = 0x03 << offset;
3117        pub mod R {}
3118        pub mod W {}
3119        pub mod RW {}
3120    }
3121    #[doc = "lpuart5 clock (lpuart5_clk_enable)"]
3122    pub mod CG1 {
3123        pub const offset: u32 = 2;
3124        pub const mask: u32 = 0x03 << offset;
3125        pub mod R {}
3126        pub mod W {}
3127        pub mod RW {}
3128    }
3129    #[doc = "semc clocks (semc_clk_enable)"]
3130    pub mod CG2 {
3131        pub const offset: u32 = 4;
3132        pub const mask: u32 = 0x03 << offset;
3133        pub mod R {}
3134        pub mod W {}
3135        pub mod RW {}
3136    }
3137    #[doc = "lpuart6 clock (lpuart6_clk_enable)"]
3138    pub mod CG3 {
3139        pub const offset: u32 = 6;
3140        pub const mask: u32 = 0x03 << offset;
3141        pub mod R {}
3142        pub mod W {}
3143        pub mod RW {}
3144    }
3145    #[doc = "aoi1 clock (aoi1_clk_enable)"]
3146    pub mod CG4 {
3147        pub const offset: u32 = 8;
3148        pub const mask: u32 = 0x03 << offset;
3149        pub mod R {}
3150        pub mod W {}
3151        pub mod RW {}
3152    }
3153    #[doc = "lcdif pix clock (lcdif_pix_clk_enable)"]
3154    pub mod CG5 {
3155        pub const offset: u32 = 10;
3156        pub const mask: u32 = 0x03 << offset;
3157        pub mod R {}
3158        pub mod W {}
3159        pub mod RW {}
3160    }
3161    #[doc = "gpio4 clock (gpio4_clk_enable)"]
3162    pub mod CG6 {
3163        pub const offset: u32 = 12;
3164        pub const mask: u32 = 0x03 << offset;
3165        pub mod R {}
3166        pub mod W {}
3167        pub mod RW {}
3168    }
3169    #[doc = "ewm clocks (ewm_clk_enable)"]
3170    pub mod CG7 {
3171        pub const offset: u32 = 14;
3172        pub const mask: u32 = 0x03 << offset;
3173        pub mod R {}
3174        pub mod W {}
3175        pub mod RW {}
3176    }
3177    #[doc = "wdog1 clock (wdog1_clk_enable)"]
3178    pub mod CG8 {
3179        pub const offset: u32 = 16;
3180        pub const mask: u32 = 0x03 << offset;
3181        pub mod R {}
3182        pub mod W {}
3183        pub mod RW {}
3184    }
3185    #[doc = "flexram clock (flexram_clk_enable)"]
3186    pub mod CG9 {
3187        pub const offset: u32 = 18;
3188        pub const mask: u32 = 0x03 << offset;
3189        pub mod R {}
3190        pub mod W {}
3191        pub mod RW {}
3192    }
3193    #[doc = "acmp1 clocks (acmp1_clk_enable)"]
3194    pub mod CG10 {
3195        pub const offset: u32 = 20;
3196        pub const mask: u32 = 0x03 << offset;
3197        pub mod R {}
3198        pub mod W {}
3199        pub mod RW {}
3200    }
3201    #[doc = "acmp2 clocks (acmp2_clk_enable)"]
3202    pub mod CG11 {
3203        pub const offset: u32 = 22;
3204        pub const mask: u32 = 0x03 << offset;
3205        pub mod R {}
3206        pub mod W {}
3207        pub mod RW {}
3208    }
3209    #[doc = "acmp3 clocks (acmp3_clk_enable)"]
3210    pub mod CG12 {
3211        pub const offset: u32 = 24;
3212        pub const mask: u32 = 0x03 << offset;
3213        pub mod R {}
3214        pub mod W {}
3215        pub mod RW {}
3216    }
3217    #[doc = "acmp4 clocks (acmp4_clk_enable)"]
3218    pub mod CG13 {
3219        pub const offset: u32 = 26;
3220        pub const mask: u32 = 0x03 << offset;
3221        pub mod R {}
3222        pub mod W {}
3223        pub mod RW {}
3224    }
3225    #[doc = "The OCRAM clock cannot be turned off when the CM cache is running on this device."]
3226    pub mod CG14 {
3227        pub const offset: u32 = 28;
3228        pub const mask: u32 = 0x03 << offset;
3229        pub mod R {}
3230        pub mod W {}
3231        pub mod RW {}
3232    }
3233    #[doc = "iomuxc_snvs_gpr clock (iomuxc_snvs_gpr_clk_enable)"]
3234    pub mod CG15 {
3235        pub const offset: u32 = 30;
3236        pub const mask: u32 = 0x03 << offset;
3237        pub mod R {}
3238        pub mod W {}
3239        pub mod RW {}
3240    }
3241}
3242#[doc = "CCM Clock Gating Register 4"]
3243pub mod CCGR4 {
3244    #[doc = "sim_m7 register access clock (sim_m7_mainclk_r_enable)"]
3245    pub mod CG0 {
3246        pub const offset: u32 = 0;
3247        pub const mask: u32 = 0x03 << offset;
3248        pub mod R {}
3249        pub mod W {}
3250        pub mod RW {}
3251    }
3252    #[doc = "iomuxc clock (iomuxc_clk_enable)"]
3253    pub mod CG1 {
3254        pub const offset: u32 = 2;
3255        pub const mask: u32 = 0x03 << offset;
3256        pub mod R {}
3257        pub mod W {}
3258        pub mod RW {}
3259    }
3260    #[doc = "iomuxc gpr clock (iomuxc_gpr_clk_enable)"]
3261    pub mod CG2 {
3262        pub const offset: u32 = 4;
3263        pub const mask: u32 = 0x03 << offset;
3264        pub mod R {}
3265        pub mod W {}
3266        pub mod RW {}
3267    }
3268    #[doc = "bee clock(bee_clk_enable)"]
3269    pub mod CG3 {
3270        pub const offset: u32 = 6;
3271        pub const mask: u32 = 0x03 << offset;
3272        pub mod R {}
3273        pub mod W {}
3274        pub mod RW {}
3275    }
3276    #[doc = "sim_m7 clock (sim_m7_clk_enable)"]
3277    pub mod CG4 {
3278        pub const offset: u32 = 8;
3279        pub const mask: u32 = 0x03 << offset;
3280        pub mod R {}
3281        pub mod W {}
3282        pub mod RW {}
3283    }
3284    #[doc = "tsc_dig clock (tsc_clk_enable)"]
3285    pub mod CG5 {
3286        pub const offset: u32 = 10;
3287        pub const mask: u32 = 0x03 << offset;
3288        pub mod R {}
3289        pub mod W {}
3290        pub mod RW {}
3291    }
3292    #[doc = "sim_m clocks (sim_m_clk_enable)"]
3293    pub mod CG6 {
3294        pub const offset: u32 = 12;
3295        pub const mask: u32 = 0x03 << offset;
3296        pub mod R {}
3297        pub mod W {}
3298        pub mod RW {}
3299    }
3300    #[doc = "sim_ems clocks (sim_ems_clk_enable)"]
3301    pub mod CG7 {
3302        pub const offset: u32 = 14;
3303        pub const mask: u32 = 0x03 << offset;
3304        pub mod R {}
3305        pub mod W {}
3306        pub mod RW {}
3307    }
3308    #[doc = "pwm1 clocks (pwm1_clk_enable)"]
3309    pub mod CG8 {
3310        pub const offset: u32 = 16;
3311        pub const mask: u32 = 0x03 << offset;
3312        pub mod R {}
3313        pub mod W {}
3314        pub mod RW {}
3315    }
3316    #[doc = "pwm2 clocks (pwm2_clk_enable)"]
3317    pub mod CG9 {
3318        pub const offset: u32 = 18;
3319        pub const mask: u32 = 0x03 << offset;
3320        pub mod R {}
3321        pub mod W {}
3322        pub mod RW {}
3323    }
3324    #[doc = "pwm3 clocks (pwm3_clk_enable)"]
3325    pub mod CG10 {
3326        pub const offset: u32 = 20;
3327        pub const mask: u32 = 0x03 << offset;
3328        pub mod R {}
3329        pub mod W {}
3330        pub mod RW {}
3331    }
3332    #[doc = "pwm4 clocks (pwm4_clk_enable)"]
3333    pub mod CG11 {
3334        pub const offset: u32 = 22;
3335        pub const mask: u32 = 0x03 << offset;
3336        pub mod R {}
3337        pub mod W {}
3338        pub mod RW {}
3339    }
3340    #[doc = "enc1 clocks (enc1_clk_enable)"]
3341    pub mod CG12 {
3342        pub const offset: u32 = 24;
3343        pub const mask: u32 = 0x03 << offset;
3344        pub mod R {}
3345        pub mod W {}
3346        pub mod RW {}
3347    }
3348    #[doc = "enc2 clocks (enc2_clk_enable)"]
3349    pub mod CG13 {
3350        pub const offset: u32 = 26;
3351        pub const mask: u32 = 0x03 << offset;
3352        pub mod R {}
3353        pub mod W {}
3354        pub mod RW {}
3355    }
3356    #[doc = "enc3 clocks (enc3_clk_enable)"]
3357    pub mod CG14 {
3358        pub const offset: u32 = 28;
3359        pub const mask: u32 = 0x03 << offset;
3360        pub mod R {}
3361        pub mod W {}
3362        pub mod RW {}
3363    }
3364    #[doc = "enc4 clocks (enc4_clk_enable)"]
3365    pub mod CG15 {
3366        pub const offset: u32 = 30;
3367        pub const mask: u32 = 0x03 << offset;
3368        pub mod R {}
3369        pub mod W {}
3370        pub mod RW {}
3371    }
3372}
3373#[doc = "CCM Clock Gating Register 5"]
3374pub mod CCGR5 {
3375    #[doc = "rom clock (rom_clk_enable)"]
3376    pub mod CG0 {
3377        pub const offset: u32 = 0;
3378        pub const mask: u32 = 0x03 << offset;
3379        pub mod R {}
3380        pub mod W {}
3381        pub mod RW {}
3382    }
3383    #[doc = "flexio1 clock (flexio1_clk_enable)"]
3384    pub mod CG1 {
3385        pub const offset: u32 = 2;
3386        pub const mask: u32 = 0x03 << offset;
3387        pub mod R {}
3388        pub mod W {}
3389        pub mod RW {}
3390    }
3391    #[doc = "wdog3 clock (wdog3_clk_enable)"]
3392    pub mod CG2 {
3393        pub const offset: u32 = 4;
3394        pub const mask: u32 = 0x03 << offset;
3395        pub mod R {}
3396        pub mod W {}
3397        pub mod RW {}
3398    }
3399    #[doc = "dma clock (dma_clk_enable)"]
3400    pub mod CG3 {
3401        pub const offset: u32 = 6;
3402        pub const mask: u32 = 0x03 << offset;
3403        pub mod R {}
3404        pub mod W {}
3405        pub mod RW {}
3406    }
3407    #[doc = "kpp clock (kpp_clk_enable)"]
3408    pub mod CG4 {
3409        pub const offset: u32 = 8;
3410        pub const mask: u32 = 0x03 << offset;
3411        pub mod R {}
3412        pub mod W {}
3413        pub mod RW {}
3414    }
3415    #[doc = "wdog2 clock (wdog2_clk_enable)"]
3416    pub mod CG5 {
3417        pub const offset: u32 = 10;
3418        pub const mask: u32 = 0x03 << offset;
3419        pub mod R {}
3420        pub mod W {}
3421        pub mod RW {}
3422    }
3423    #[doc = "aipstz4 clocks (aips_tz4_clk_enable)"]
3424    pub mod CG6 {
3425        pub const offset: u32 = 12;
3426        pub const mask: u32 = 0x03 << offset;
3427        pub mod R {}
3428        pub mod W {}
3429        pub mod RW {}
3430    }
3431    #[doc = "spdif clock (spdif_clk_enable)"]
3432    pub mod CG7 {
3433        pub const offset: u32 = 14;
3434        pub const mask: u32 = 0x03 << offset;
3435        pub mod R {}
3436        pub mod W {}
3437        pub mod RW {}
3438    }
3439    #[doc = "sim_main clock (sim_main_clk_enable)"]
3440    pub mod CG8 {
3441        pub const offset: u32 = 16;
3442        pub const mask: u32 = 0x03 << offset;
3443        pub mod R {}
3444        pub mod W {}
3445        pub mod RW {}
3446    }
3447    #[doc = "sai1 clock (sai1_clk_enable)"]
3448    pub mod CG9 {
3449        pub const offset: u32 = 18;
3450        pub const mask: u32 = 0x03 << offset;
3451        pub mod R {}
3452        pub mod W {}
3453        pub mod RW {}
3454    }
3455    #[doc = "sai2 clock (sai2_clk_enable)"]
3456    pub mod CG10 {
3457        pub const offset: u32 = 20;
3458        pub const mask: u32 = 0x03 << offset;
3459        pub mod R {}
3460        pub mod W {}
3461        pub mod RW {}
3462    }
3463    #[doc = "sai3 clock (sai3_clk_enable)"]
3464    pub mod CG11 {
3465        pub const offset: u32 = 22;
3466        pub const mask: u32 = 0x03 << offset;
3467        pub mod R {}
3468        pub mod W {}
3469        pub mod RW {}
3470    }
3471    #[doc = "lpuart1 clock (lpuart1_clk_enable)"]
3472    pub mod CG12 {
3473        pub const offset: u32 = 24;
3474        pub const mask: u32 = 0x03 << offset;
3475        pub mod R {}
3476        pub mod W {}
3477        pub mod RW {}
3478    }
3479    #[doc = "lpuart7 clock (lpuart7_clk_enable)"]
3480    pub mod CG13 {
3481        pub const offset: u32 = 26;
3482        pub const mask: u32 = 0x03 << offset;
3483        pub mod R {}
3484        pub mod W {}
3485        pub mod RW {}
3486    }
3487    #[doc = "snvs_hp clock (snvs_hp_clk_enable)"]
3488    pub mod CG14 {
3489        pub const offset: u32 = 28;
3490        pub const mask: u32 = 0x03 << offset;
3491        pub mod R {}
3492        pub mod W {}
3493        pub mod RW {}
3494    }
3495    #[doc = "snvs_lp clock (snvs_lp_clk_enable)"]
3496    pub mod CG15 {
3497        pub const offset: u32 = 30;
3498        pub const mask: u32 = 0x03 << offset;
3499        pub mod R {}
3500        pub mod W {}
3501        pub mod RW {}
3502    }
3503}
3504#[doc = "CCM Clock Gating Register 6"]
3505pub mod CCGR6 {
3506    #[doc = "usboh3 clock (usboh3_clk_enable)"]
3507    pub mod CG0 {
3508        pub const offset: u32 = 0;
3509        pub const mask: u32 = 0x03 << offset;
3510        pub mod R {}
3511        pub mod W {}
3512        pub mod RW {}
3513    }
3514    #[doc = "usdhc1 clocks (usdhc1_clk_enable)"]
3515    pub mod CG1 {
3516        pub const offset: u32 = 2;
3517        pub const mask: u32 = 0x03 << offset;
3518        pub mod R {}
3519        pub mod W {}
3520        pub mod RW {}
3521    }
3522    #[doc = "usdhc2 clocks (usdhc2_clk_enable)"]
3523    pub mod CG2 {
3524        pub const offset: u32 = 4;
3525        pub const mask: u32 = 0x03 << offset;
3526        pub mod R {}
3527        pub mod W {}
3528        pub mod RW {}
3529    }
3530    #[doc = "dcdc clocks (dcdc_clk_enable)"]
3531    pub mod CG3 {
3532        pub const offset: u32 = 6;
3533        pub const mask: u32 = 0x03 << offset;
3534        pub mod R {}
3535        pub mod W {}
3536        pub mod RW {}
3537    }
3538    #[doc = "ipmux4 clock (ipmux4_clk_enable)"]
3539    pub mod CG4 {
3540        pub const offset: u32 = 8;
3541        pub const mask: u32 = 0x03 << offset;
3542        pub mod R {}
3543        pub mod W {}
3544        pub mod RW {}
3545    }
3546    #[doc = "flexspi clocks (flexspi_clk_enable) sim_ems_clk_enable must also be cleared, when flexspi_clk_enable is cleared"]
3547    pub mod CG5 {
3548        pub const offset: u32 = 10;
3549        pub const mask: u32 = 0x03 << offset;
3550        pub mod R {}
3551        pub mod W {}
3552        pub mod RW {}
3553    }
3554    #[doc = "trng clock (trng_clk_enable)"]
3555    pub mod CG6 {
3556        pub const offset: u32 = 12;
3557        pub const mask: u32 = 0x03 << offset;
3558        pub mod R {}
3559        pub mod W {}
3560        pub mod RW {}
3561    }
3562    #[doc = "lpuart8 clocks (lpuart8_clk_enable)"]
3563    pub mod CG7 {
3564        pub const offset: u32 = 14;
3565        pub const mask: u32 = 0x03 << offset;
3566        pub mod R {}
3567        pub mod W {}
3568        pub mod RW {}
3569    }
3570    #[doc = "timer4 clocks (timer4_clk_enable)"]
3571    pub mod CG8 {
3572        pub const offset: u32 = 16;
3573        pub const mask: u32 = 0x03 << offset;
3574        pub mod R {}
3575        pub mod W {}
3576        pub mod RW {}
3577    }
3578    #[doc = "aips_tz3 clock (aips_tz3_clk_enable)"]
3579    pub mod CG9 {
3580        pub const offset: u32 = 18;
3581        pub const mask: u32 = 0x03 << offset;
3582        pub mod R {}
3583        pub mod W {}
3584        pub mod RW {}
3585    }
3586    #[doc = "sim_axbs_p_clk_enable"]
3587    pub mod CG10 {
3588        pub const offset: u32 = 20;
3589        pub const mask: u32 = 0x03 << offset;
3590        pub mod R {}
3591        pub mod W {}
3592        pub mod RW {}
3593    }
3594    #[doc = "anadig clocks (anadig_clk_enable)"]
3595    pub mod CG11 {
3596        pub const offset: u32 = 22;
3597        pub const mask: u32 = 0x03 << offset;
3598        pub mod R {}
3599        pub mod W {}
3600        pub mod RW {}
3601    }
3602    #[doc = "lpi2c4 serial clock (lpi2c4_serial_clk_enable)"]
3603    pub mod CG12 {
3604        pub const offset: u32 = 24;
3605        pub const mask: u32 = 0x03 << offset;
3606        pub mod R {}
3607        pub mod W {}
3608        pub mod RW {}
3609    }
3610    #[doc = "timer1 clocks (timer1_clk_enable)"]
3611    pub mod CG13 {
3612        pub const offset: u32 = 26;
3613        pub const mask: u32 = 0x03 << offset;
3614        pub mod R {}
3615        pub mod W {}
3616        pub mod RW {}
3617    }
3618    #[doc = "timer2 clocks (timer2_clk_enable)"]
3619    pub mod CG14 {
3620        pub const offset: u32 = 28;
3621        pub const mask: u32 = 0x03 << offset;
3622        pub mod R {}
3623        pub mod W {}
3624        pub mod RW {}
3625    }
3626    #[doc = "timer3 clocks (timer3_clk_enable)"]
3627    pub mod CG15 {
3628        pub const offset: u32 = 30;
3629        pub const mask: u32 = 0x03 << offset;
3630        pub mod R {}
3631        pub mod W {}
3632        pub mod RW {}
3633    }
3634}
3635#[doc = "CCM Clock Gating Register 7"]
3636pub mod CCGR7 {
3637    #[doc = "enet2_clk_enable"]
3638    pub mod CG0 {
3639        pub const offset: u32 = 0;
3640        pub const mask: u32 = 0x03 << offset;
3641        pub mod R {}
3642        pub mod W {}
3643        pub mod RW {}
3644    }
3645    #[doc = "flexspi2_clk_enable"]
3646    pub mod CG1 {
3647        pub const offset: u32 = 2;
3648        pub const mask: u32 = 0x03 << offset;
3649        pub mod R {}
3650        pub mod W {}
3651        pub mod RW {}
3652    }
3653    #[doc = "axbs_l_clk_enable"]
3654    pub mod CG2 {
3655        pub const offset: u32 = 4;
3656        pub const mask: u32 = 0x03 << offset;
3657        pub mod R {}
3658        pub mod W {}
3659        pub mod RW {}
3660    }
3661    #[doc = "can3_clk_enable"]
3662    pub mod CG3 {
3663        pub const offset: u32 = 6;
3664        pub const mask: u32 = 0x03 << offset;
3665        pub mod R {}
3666        pub mod W {}
3667        pub mod RW {}
3668    }
3669    #[doc = "can3_serial_clk_enable"]
3670    pub mod CG4 {
3671        pub const offset: u32 = 8;
3672        pub const mask: u32 = 0x03 << offset;
3673        pub mod R {}
3674        pub mod W {}
3675        pub mod RW {}
3676    }
3677    #[doc = "aips_lite_clk_enable"]
3678    pub mod CG5 {
3679        pub const offset: u32 = 10;
3680        pub const mask: u32 = 0x03 << offset;
3681        pub mod R {}
3682        pub mod W {}
3683        pub mod RW {}
3684    }
3685    #[doc = "flexio3_clk_enable"]
3686    pub mod CG6 {
3687        pub const offset: u32 = 12;
3688        pub const mask: u32 = 0x03 << offset;
3689        pub mod R {}
3690        pub mod W {}
3691        pub mod RW {}
3692    }
3693}
3694#[doc = "CCM Module Enable Overide Register"]
3695pub mod CMEOR {
3696    #[doc = "Overide clock enable signal from GPT - clock will not be gated based on GPT's signal 'ipg_enable_clk'"]
3697    pub mod MOD_EN_OV_GPT {
3698        pub const offset: u32 = 5;
3699        pub const mask: u32 = 0x01 << offset;
3700        pub mod R {}
3701        pub mod W {}
3702        pub mod RW {
3703            #[doc = "don't override module enable signal"]
3704            pub const MOD_EN_OV_GPT_0: u32 = 0;
3705            #[doc = "override module enable signal"]
3706            pub const MOD_EN_OV_GPT_1: u32 = 0x01;
3707        }
3708    }
3709    #[doc = "Overide clock enable signal from PIT - clock will not be gated based on PIT's signal 'ipg_enable_clk'"]
3710    pub mod MOD_EN_OV_PIT {
3711        pub const offset: u32 = 6;
3712        pub const mask: u32 = 0x01 << offset;
3713        pub mod R {}
3714        pub mod W {}
3715        pub mod RW {
3716            #[doc = "don't override module enable signal"]
3717            pub const MOD_EN_OV_PIT_0: u32 = 0;
3718            #[doc = "override module enable signal"]
3719            pub const MOD_EN_OV_PIT_1: u32 = 0x01;
3720        }
3721    }
3722    #[doc = "overide clock enable signal from USDHC."]
3723    pub mod MOD_EN_USDHC {
3724        pub const offset: u32 = 7;
3725        pub const mask: u32 = 0x01 << offset;
3726        pub mod R {}
3727        pub mod W {}
3728        pub mod RW {
3729            #[doc = "don't override module enable signal"]
3730            pub const MOD_EN_USDHC_0: u32 = 0;
3731            #[doc = "override module enable signal"]
3732            pub const MOD_EN_USDHC_1: u32 = 0x01;
3733        }
3734    }
3735    #[doc = "Overide clock enable signal from TRNG"]
3736    pub mod MOD_EN_OV_TRNG {
3737        pub const offset: u32 = 9;
3738        pub const mask: u32 = 0x01 << offset;
3739        pub mod R {}
3740        pub mod W {}
3741        pub mod RW {
3742            #[doc = "don't override module enable signal"]
3743            pub const MOD_EN_OV_TRNG_0: u32 = 0;
3744            #[doc = "override module enable signal"]
3745            pub const MOD_EN_OV_TRNG_1: u32 = 0x01;
3746        }
3747    }
3748    #[doc = "Overide clock enable signal from FlexCAN3(CANFD) - clock will not be gated based on CAN's signal 'enable_clk_cpi'"]
3749    pub mod MOD_EN_OV_CANFD_CPI {
3750        pub const offset: u32 = 10;
3751        pub const mask: u32 = 0x01 << offset;
3752        pub mod R {}
3753        pub mod W {}
3754        pub mod RW {
3755            #[doc = "don't override module enable signal"]
3756            pub const MOD_EN_OV_CANFD_CPI_0: u32 = 0;
3757            #[doc = "override module enable signal"]
3758            pub const MOD_EN_OV_CANFD_CPI_1: u32 = 0x01;
3759        }
3760    }
3761    #[doc = "Overide clock enable signal from CAN2 - clock will not be gated based on CAN's signal 'enable_clk_cpi'"]
3762    pub mod MOD_EN_OV_CAN2_CPI {
3763        pub const offset: u32 = 28;
3764        pub const mask: u32 = 0x01 << offset;
3765        pub mod R {}
3766        pub mod W {}
3767        pub mod RW {
3768            #[doc = "don't override module enable signal"]
3769            pub const MOD_EN_OV_CAN2_CPI_0: u32 = 0;
3770            #[doc = "override module enable signal"]
3771            pub const MOD_EN_OV_CAN2_CPI_1: u32 = 0x01;
3772        }
3773    }
3774    #[doc = "Overide clock enable signal from CAN1 - clock will not be gated based on CAN's signal 'enable_clk_cpi'"]
3775    pub mod MOD_EN_OV_CAN1_CPI {
3776        pub const offset: u32 = 30;
3777        pub const mask: u32 = 0x01 << offset;
3778        pub mod R {}
3779        pub mod W {}
3780        pub mod RW {
3781            #[doc = "don't overide module enable signal"]
3782            pub const MOD_EN_OV_CAN1_CPI_0: u32 = 0;
3783            #[doc = "overide module enable signal"]
3784            pub const MOD_EN_OV_CAN1_CPI_1: u32 = 0x01;
3785        }
3786    }
3787}