imxrt_ral/blocks/imxrt1061/
ccm_analog.rs1#[doc = "CCM_ANALOG"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "Analog ARM PLL control Register"]
5 pub PLL_ARM: crate::RWRegister<u32>,
6 #[doc = "Analog ARM PLL control Register"]
7 pub PLL_ARM_SET: crate::RWRegister<u32>,
8 #[doc = "Analog ARM PLL control Register"]
9 pub PLL_ARM_CLR: crate::RWRegister<u32>,
10 #[doc = "Analog ARM PLL control Register"]
11 pub PLL_ARM_TOG: crate::RWRegister<u32>,
12 #[doc = "Analog USB1 480MHz PLL Control Register"]
13 pub PLL_USB1: crate::RWRegister<u32>,
14 #[doc = "Analog USB1 480MHz PLL Control Register"]
15 pub PLL_USB1_SET: crate::RWRegister<u32>,
16 #[doc = "Analog USB1 480MHz PLL Control Register"]
17 pub PLL_USB1_CLR: crate::RWRegister<u32>,
18 #[doc = "Analog USB1 480MHz PLL Control Register"]
19 pub PLL_USB1_TOG: crate::RWRegister<u32>,
20 #[doc = "Analog USB2 480MHz PLL Control Register"]
21 pub PLL_USB2: crate::RWRegister<u32>,
22 #[doc = "Analog USB2 480MHz PLL Control Register"]
23 pub PLL_USB2_SET: crate::RWRegister<u32>,
24 #[doc = "Analog USB2 480MHz PLL Control Register"]
25 pub PLL_USB2_CLR: crate::RWRegister<u32>,
26 #[doc = "Analog USB2 480MHz PLL Control Register"]
27 pub PLL_USB2_TOG: crate::RWRegister<u32>,
28 #[doc = "Analog System PLL Control Register"]
29 pub PLL_SYS: crate::RWRegister<u32>,
30 #[doc = "Analog System PLL Control Register"]
31 pub PLL_SYS_SET: crate::RWRegister<u32>,
32 #[doc = "Analog System PLL Control Register"]
33 pub PLL_SYS_CLR: crate::RWRegister<u32>,
34 #[doc = "Analog System PLL Control Register"]
35 pub PLL_SYS_TOG: crate::RWRegister<u32>,
36 #[doc = "528MHz System PLL Spread Spectrum Register"]
37 pub PLL_SYS_SS: crate::RWRegister<u32>,
38 _reserved0: [u8; 0x0c],
39 #[doc = "Numerator of 528MHz System PLL Fractional Loop Divider Register"]
40 pub PLL_SYS_NUM: crate::RWRegister<u32>,
41 _reserved1: [u8; 0x0c],
42 #[doc = "Denominator of 528MHz System PLL Fractional Loop Divider Register"]
43 pub PLL_SYS_DENOM: crate::RWRegister<u32>,
44 _reserved2: [u8; 0x0c],
45 #[doc = "Analog Audio PLL control Register"]
46 pub PLL_AUDIO: crate::RWRegister<u32>,
47 #[doc = "Analog Audio PLL control Register"]
48 pub PLL_AUDIO_SET: crate::RWRegister<u32>,
49 #[doc = "Analog Audio PLL control Register"]
50 pub PLL_AUDIO_CLR: crate::RWRegister<u32>,
51 #[doc = "Analog Audio PLL control Register"]
52 pub PLL_AUDIO_TOG: crate::RWRegister<u32>,
53 #[doc = "Numerator of Audio PLL Fractional Loop Divider Register"]
54 pub PLL_AUDIO_NUM: crate::RWRegister<u32>,
55 _reserved3: [u8; 0x0c],
56 #[doc = "Denominator of Audio PLL Fractional Loop Divider Register"]
57 pub PLL_AUDIO_DENOM: crate::RWRegister<u32>,
58 _reserved4: [u8; 0x0c],
59 #[doc = "Analog Video PLL control Register"]
60 pub PLL_VIDEO: crate::RWRegister<u32>,
61 #[doc = "Analog Video PLL control Register"]
62 pub PLL_VIDEO_SET: crate::RWRegister<u32>,
63 #[doc = "Analog Video PLL control Register"]
64 pub PLL_VIDEO_CLR: crate::RWRegister<u32>,
65 #[doc = "Analog Video PLL control Register"]
66 pub PLL_VIDEO_TOG: crate::RWRegister<u32>,
67 #[doc = "Numerator of Video PLL Fractional Loop Divider Register"]
68 pub PLL_VIDEO_NUM: crate::RWRegister<u32>,
69 _reserved5: [u8; 0x0c],
70 #[doc = "Denominator of Video PLL Fractional Loop Divider Register"]
71 pub PLL_VIDEO_DENOM: crate::RWRegister<u32>,
72 _reserved6: [u8; 0x1c],
73 #[doc = "Analog ENET PLL Control Register"]
74 pub PLL_ENET: crate::RWRegister<u32>,
75 #[doc = "Analog ENET PLL Control Register"]
76 pub PLL_ENET_SET: crate::RWRegister<u32>,
77 #[doc = "Analog ENET PLL Control Register"]
78 pub PLL_ENET_CLR: crate::RWRegister<u32>,
79 #[doc = "Analog ENET PLL Control Register"]
80 pub PLL_ENET_TOG: crate::RWRegister<u32>,
81 #[doc = "480MHz Clock (PLL3) Phase Fractional Divider Control Register"]
82 pub PFD_480: crate::RWRegister<u32>,
83 #[doc = "480MHz Clock (PLL3) Phase Fractional Divider Control Register"]
84 pub PFD_480_SET: crate::RWRegister<u32>,
85 #[doc = "480MHz Clock (PLL3) Phase Fractional Divider Control Register"]
86 pub PFD_480_CLR: crate::RWRegister<u32>,
87 #[doc = "480MHz Clock (PLL3) Phase Fractional Divider Control Register"]
88 pub PFD_480_TOG: crate::RWRegister<u32>,
89 #[doc = "528MHz Clock (PLL2) Phase Fractional Divider Control Register"]
90 pub PFD_528: crate::RWRegister<u32>,
91 #[doc = "528MHz Clock (PLL2) Phase Fractional Divider Control Register"]
92 pub PFD_528_SET: crate::RWRegister<u32>,
93 #[doc = "528MHz Clock (PLL2) Phase Fractional Divider Control Register"]
94 pub PFD_528_CLR: crate::RWRegister<u32>,
95 #[doc = "528MHz Clock (PLL2) Phase Fractional Divider Control Register"]
96 pub PFD_528_TOG: crate::RWRegister<u32>,
97 _reserved7: [u8; 0x40],
98 #[doc = "Miscellaneous Register 0"]
99 pub MISC0: crate::RWRegister<u32>,
100 #[doc = "Miscellaneous Register 0"]
101 pub MISC0_SET: crate::RWRegister<u32>,
102 #[doc = "Miscellaneous Register 0"]
103 pub MISC0_CLR: crate::RWRegister<u32>,
104 #[doc = "Miscellaneous Register 0"]
105 pub MISC0_TOG: crate::RWRegister<u32>,
106 #[doc = "Miscellaneous Register 1"]
107 pub MISC1: crate::RWRegister<u32>,
108 #[doc = "Miscellaneous Register 1"]
109 pub MISC1_SET: crate::RWRegister<u32>,
110 #[doc = "Miscellaneous Register 1"]
111 pub MISC1_CLR: crate::RWRegister<u32>,
112 #[doc = "Miscellaneous Register 1"]
113 pub MISC1_TOG: crate::RWRegister<u32>,
114 #[doc = "Miscellaneous Register 2"]
115 pub MISC2: crate::RWRegister<u32>,
116 #[doc = "Miscellaneous Register 2"]
117 pub MISC2_SET: crate::RWRegister<u32>,
118 #[doc = "Miscellaneous Register 2"]
119 pub MISC2_CLR: crate::RWRegister<u32>,
120 #[doc = "Miscellaneous Register 2"]
121 pub MISC2_TOG: crate::RWRegister<u32>,
122}
123#[doc = "Analog ARM PLL control Register"]
124pub mod PLL_ARM {
125 #[doc = "This field controls the PLL loop divider"]
126 pub mod DIV_SELECT {
127 pub const offset: u32 = 0;
128 pub const mask: u32 = 0x7f << offset;
129 pub mod R {}
130 pub mod W {}
131 pub mod RW {}
132 }
133 #[doc = "Powers down the PLL."]
134 pub mod POWERDOWN {
135 pub const offset: u32 = 12;
136 pub const mask: u32 = 0x01 << offset;
137 pub mod R {}
138 pub mod W {}
139 pub mod RW {}
140 }
141 #[doc = "Enable the clock output."]
142 pub mod ENABLE {
143 pub const offset: u32 = 13;
144 pub const mask: u32 = 0x01 << offset;
145 pub mod R {}
146 pub mod W {}
147 pub mod RW {}
148 }
149 #[doc = "Determines the bypass source"]
150 pub mod BYPASS_CLK_SRC {
151 pub const offset: u32 = 14;
152 pub const mask: u32 = 0x03 << offset;
153 pub mod R {}
154 pub mod W {}
155 pub mod RW {
156 #[doc = "Select the 24MHz oscillator as source."]
157 pub const REF_CLK_24M: u32 = 0;
158 #[doc = "Select the CLK1_N / CLK1_P as source."]
159 pub const CLK1: u32 = 0x01;
160 }
161 }
162 #[doc = "Bypass the PLL."]
163 pub mod BYPASS {
164 pub const offset: u32 = 16;
165 pub const mask: u32 = 0x01 << offset;
166 pub mod R {}
167 pub mod W {}
168 pub mod RW {}
169 }
170 #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."]
171 pub mod LOCK {
172 pub const offset: u32 = 31;
173 pub const mask: u32 = 0x01 << offset;
174 pub mod R {}
175 pub mod W {}
176 pub mod RW {}
177 }
178}
179#[doc = "Analog ARM PLL control Register"]
180pub mod PLL_ARM_SET {
181 #[doc = "This field controls the PLL loop divider"]
182 pub mod DIV_SELECT {
183 pub const offset: u32 = 0;
184 pub const mask: u32 = 0x7f << offset;
185 pub mod R {}
186 pub mod W {}
187 pub mod RW {}
188 }
189 #[doc = "Powers down the PLL."]
190 pub mod POWERDOWN {
191 pub const offset: u32 = 12;
192 pub const mask: u32 = 0x01 << offset;
193 pub mod R {}
194 pub mod W {}
195 pub mod RW {}
196 }
197 #[doc = "Enable the clock output."]
198 pub mod ENABLE {
199 pub const offset: u32 = 13;
200 pub const mask: u32 = 0x01 << offset;
201 pub mod R {}
202 pub mod W {}
203 pub mod RW {}
204 }
205 #[doc = "Determines the bypass source"]
206 pub mod BYPASS_CLK_SRC {
207 pub const offset: u32 = 14;
208 pub const mask: u32 = 0x03 << offset;
209 pub mod R {}
210 pub mod W {}
211 pub mod RW {
212 #[doc = "Select the 24MHz oscillator as source."]
213 pub const REF_CLK_24M: u32 = 0;
214 #[doc = "Select the CLK1_N / CLK1_P as source."]
215 pub const CLK1: u32 = 0x01;
216 }
217 }
218 #[doc = "Bypass the PLL."]
219 pub mod BYPASS {
220 pub const offset: u32 = 16;
221 pub const mask: u32 = 0x01 << offset;
222 pub mod R {}
223 pub mod W {}
224 pub mod RW {}
225 }
226 #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."]
227 pub mod LOCK {
228 pub const offset: u32 = 31;
229 pub const mask: u32 = 0x01 << offset;
230 pub mod R {}
231 pub mod W {}
232 pub mod RW {}
233 }
234}
235#[doc = "Analog ARM PLL control Register"]
236pub mod PLL_ARM_CLR {
237 #[doc = "This field controls the PLL loop divider"]
238 pub mod DIV_SELECT {
239 pub const offset: u32 = 0;
240 pub const mask: u32 = 0x7f << offset;
241 pub mod R {}
242 pub mod W {}
243 pub mod RW {}
244 }
245 #[doc = "Powers down the PLL."]
246 pub mod POWERDOWN {
247 pub const offset: u32 = 12;
248 pub const mask: u32 = 0x01 << offset;
249 pub mod R {}
250 pub mod W {}
251 pub mod RW {}
252 }
253 #[doc = "Enable the clock output."]
254 pub mod ENABLE {
255 pub const offset: u32 = 13;
256 pub const mask: u32 = 0x01 << offset;
257 pub mod R {}
258 pub mod W {}
259 pub mod RW {}
260 }
261 #[doc = "Determines the bypass source"]
262 pub mod BYPASS_CLK_SRC {
263 pub const offset: u32 = 14;
264 pub const mask: u32 = 0x03 << offset;
265 pub mod R {}
266 pub mod W {}
267 pub mod RW {
268 #[doc = "Select the 24MHz oscillator as source."]
269 pub const REF_CLK_24M: u32 = 0;
270 #[doc = "Select the CLK1_N / CLK1_P as source."]
271 pub const CLK1: u32 = 0x01;
272 }
273 }
274 #[doc = "Bypass the PLL."]
275 pub mod BYPASS {
276 pub const offset: u32 = 16;
277 pub const mask: u32 = 0x01 << offset;
278 pub mod R {}
279 pub mod W {}
280 pub mod RW {}
281 }
282 #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."]
283 pub mod LOCK {
284 pub const offset: u32 = 31;
285 pub const mask: u32 = 0x01 << offset;
286 pub mod R {}
287 pub mod W {}
288 pub mod RW {}
289 }
290}
291#[doc = "Analog ARM PLL control Register"]
292pub mod PLL_ARM_TOG {
293 #[doc = "This field controls the PLL loop divider"]
294 pub mod DIV_SELECT {
295 pub const offset: u32 = 0;
296 pub const mask: u32 = 0x7f << offset;
297 pub mod R {}
298 pub mod W {}
299 pub mod RW {}
300 }
301 #[doc = "Powers down the PLL."]
302 pub mod POWERDOWN {
303 pub const offset: u32 = 12;
304 pub const mask: u32 = 0x01 << offset;
305 pub mod R {}
306 pub mod W {}
307 pub mod RW {}
308 }
309 #[doc = "Enable the clock output."]
310 pub mod ENABLE {
311 pub const offset: u32 = 13;
312 pub const mask: u32 = 0x01 << offset;
313 pub mod R {}
314 pub mod W {}
315 pub mod RW {}
316 }
317 #[doc = "Determines the bypass source"]
318 pub mod BYPASS_CLK_SRC {
319 pub const offset: u32 = 14;
320 pub const mask: u32 = 0x03 << offset;
321 pub mod R {}
322 pub mod W {}
323 pub mod RW {
324 #[doc = "Select the 24MHz oscillator as source."]
325 pub const REF_CLK_24M: u32 = 0;
326 #[doc = "Select the CLK1_N / CLK1_P as source."]
327 pub const CLK1: u32 = 0x01;
328 }
329 }
330 #[doc = "Bypass the PLL."]
331 pub mod BYPASS {
332 pub const offset: u32 = 16;
333 pub const mask: u32 = 0x01 << offset;
334 pub mod R {}
335 pub mod W {}
336 pub mod RW {}
337 }
338 #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."]
339 pub mod LOCK {
340 pub const offset: u32 = 31;
341 pub const mask: u32 = 0x01 << offset;
342 pub mod R {}
343 pub mod W {}
344 pub mod RW {}
345 }
346}
347#[doc = "Analog USB1 480MHz PLL Control Register"]
348pub mod PLL_USB1 {
349 #[doc = "This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22."]
350 pub mod DIV_SELECT {
351 pub const offset: u32 = 1;
352 pub const mask: u32 = 0x01 << offset;
353 pub mod R {}
354 pub mod W {}
355 pub mod RW {}
356 }
357 #[doc = "Powers the 9-phase PLL outputs for USBPHYn"]
358 pub mod EN_USB_CLKS {
359 pub const offset: u32 = 6;
360 pub const mask: u32 = 0x01 << offset;
361 pub mod R {}
362 pub mod W {}
363 pub mod RW {
364 #[doc = "PLL outputs for USBPHYn off."]
365 pub const EN_USB_CLKS_0: u32 = 0;
366 #[doc = "PLL outputs for USBPHYn on."]
367 pub const EN_USB_CLKS_1: u32 = 0x01;
368 }
369 }
370 #[doc = "Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens."]
371 pub mod POWER {
372 pub const offset: u32 = 12;
373 pub const mask: u32 = 0x01 << offset;
374 pub mod R {}
375 pub mod W {}
376 pub mod RW {}
377 }
378 #[doc = "Enable the PLL clock output."]
379 pub mod ENABLE {
380 pub const offset: u32 = 13;
381 pub const mask: u32 = 0x01 << offset;
382 pub mod R {}
383 pub mod W {}
384 pub mod RW {}
385 }
386 #[doc = "Determines the bypass source."]
387 pub mod BYPASS_CLK_SRC {
388 pub const offset: u32 = 14;
389 pub const mask: u32 = 0x03 << offset;
390 pub mod R {}
391 pub mod W {}
392 pub mod RW {
393 #[doc = "Select the 24MHz oscillator as source."]
394 pub const REF_CLK_24M: u32 = 0;
395 #[doc = "Select the CLK1_N / CLK1_P as source."]
396 pub const CLK1: u32 = 0x01;
397 }
398 }
399 #[doc = "Bypass the PLL."]
400 pub mod BYPASS {
401 pub const offset: u32 = 16;
402 pub const mask: u32 = 0x01 << offset;
403 pub mod R {}
404 pub mod W {}
405 pub mod RW {}
406 }
407 #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."]
408 pub mod LOCK {
409 pub const offset: u32 = 31;
410 pub const mask: u32 = 0x01 << offset;
411 pub mod R {}
412 pub mod W {}
413 pub mod RW {}
414 }
415}
416#[doc = "Analog USB1 480MHz PLL Control Register"]
417pub mod PLL_USB1_SET {
418 #[doc = "This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22."]
419 pub mod DIV_SELECT {
420 pub const offset: u32 = 1;
421 pub const mask: u32 = 0x01 << offset;
422 pub mod R {}
423 pub mod W {}
424 pub mod RW {}
425 }
426 #[doc = "Powers the 9-phase PLL outputs for USBPHYn"]
427 pub mod EN_USB_CLKS {
428 pub const offset: u32 = 6;
429 pub const mask: u32 = 0x01 << offset;
430 pub mod R {}
431 pub mod W {}
432 pub mod RW {
433 #[doc = "PLL outputs for USBPHYn off."]
434 pub const EN_USB_CLKS_0: u32 = 0;
435 #[doc = "PLL outputs for USBPHYn on."]
436 pub const EN_USB_CLKS_1: u32 = 0x01;
437 }
438 }
439 #[doc = "Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens."]
440 pub mod POWER {
441 pub const offset: u32 = 12;
442 pub const mask: u32 = 0x01 << offset;
443 pub mod R {}
444 pub mod W {}
445 pub mod RW {}
446 }
447 #[doc = "Enable the PLL clock output."]
448 pub mod ENABLE {
449 pub const offset: u32 = 13;
450 pub const mask: u32 = 0x01 << offset;
451 pub mod R {}
452 pub mod W {}
453 pub mod RW {}
454 }
455 #[doc = "Determines the bypass source."]
456 pub mod BYPASS_CLK_SRC {
457 pub const offset: u32 = 14;
458 pub const mask: u32 = 0x03 << offset;
459 pub mod R {}
460 pub mod W {}
461 pub mod RW {
462 #[doc = "Select the 24MHz oscillator as source."]
463 pub const REF_CLK_24M: u32 = 0;
464 #[doc = "Select the CLK1_N / CLK1_P as source."]
465 pub const CLK1: u32 = 0x01;
466 }
467 }
468 #[doc = "Bypass the PLL."]
469 pub mod BYPASS {
470 pub const offset: u32 = 16;
471 pub const mask: u32 = 0x01 << offset;
472 pub mod R {}
473 pub mod W {}
474 pub mod RW {}
475 }
476 #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."]
477 pub mod LOCK {
478 pub const offset: u32 = 31;
479 pub const mask: u32 = 0x01 << offset;
480 pub mod R {}
481 pub mod W {}
482 pub mod RW {}
483 }
484}
485#[doc = "Analog USB1 480MHz PLL Control Register"]
486pub mod PLL_USB1_CLR {
487 #[doc = "This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22."]
488 pub mod DIV_SELECT {
489 pub const offset: u32 = 1;
490 pub const mask: u32 = 0x01 << offset;
491 pub mod R {}
492 pub mod W {}
493 pub mod RW {}
494 }
495 #[doc = "Powers the 9-phase PLL outputs for USBPHYn"]
496 pub mod EN_USB_CLKS {
497 pub const offset: u32 = 6;
498 pub const mask: u32 = 0x01 << offset;
499 pub mod R {}
500 pub mod W {}
501 pub mod RW {
502 #[doc = "PLL outputs for USBPHYn off."]
503 pub const EN_USB_CLKS_0: u32 = 0;
504 #[doc = "PLL outputs for USBPHYn on."]
505 pub const EN_USB_CLKS_1: u32 = 0x01;
506 }
507 }
508 #[doc = "Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens."]
509 pub mod POWER {
510 pub const offset: u32 = 12;
511 pub const mask: u32 = 0x01 << offset;
512 pub mod R {}
513 pub mod W {}
514 pub mod RW {}
515 }
516 #[doc = "Enable the PLL clock output."]
517 pub mod ENABLE {
518 pub const offset: u32 = 13;
519 pub const mask: u32 = 0x01 << offset;
520 pub mod R {}
521 pub mod W {}
522 pub mod RW {}
523 }
524 #[doc = "Determines the bypass source."]
525 pub mod BYPASS_CLK_SRC {
526 pub const offset: u32 = 14;
527 pub const mask: u32 = 0x03 << offset;
528 pub mod R {}
529 pub mod W {}
530 pub mod RW {
531 #[doc = "Select the 24MHz oscillator as source."]
532 pub const REF_CLK_24M: u32 = 0;
533 #[doc = "Select the CLK1_N / CLK1_P as source."]
534 pub const CLK1: u32 = 0x01;
535 }
536 }
537 #[doc = "Bypass the PLL."]
538 pub mod BYPASS {
539 pub const offset: u32 = 16;
540 pub const mask: u32 = 0x01 << offset;
541 pub mod R {}
542 pub mod W {}
543 pub mod RW {}
544 }
545 #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."]
546 pub mod LOCK {
547 pub const offset: u32 = 31;
548 pub const mask: u32 = 0x01 << offset;
549 pub mod R {}
550 pub mod W {}
551 pub mod RW {}
552 }
553}
554#[doc = "Analog USB1 480MHz PLL Control Register"]
555pub mod PLL_USB1_TOG {
556 #[doc = "This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22."]
557 pub mod DIV_SELECT {
558 pub const offset: u32 = 1;
559 pub const mask: u32 = 0x01 << offset;
560 pub mod R {}
561 pub mod W {}
562 pub mod RW {}
563 }
564 #[doc = "Powers the 9-phase PLL outputs for USBPHYn"]
565 pub mod EN_USB_CLKS {
566 pub const offset: u32 = 6;
567 pub const mask: u32 = 0x01 << offset;
568 pub mod R {}
569 pub mod W {}
570 pub mod RW {
571 #[doc = "PLL outputs for USBPHYn off."]
572 pub const EN_USB_CLKS_0: u32 = 0;
573 #[doc = "PLL outputs for USBPHYn on."]
574 pub const EN_USB_CLKS_1: u32 = 0x01;
575 }
576 }
577 #[doc = "Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens."]
578 pub mod POWER {
579 pub const offset: u32 = 12;
580 pub const mask: u32 = 0x01 << offset;
581 pub mod R {}
582 pub mod W {}
583 pub mod RW {}
584 }
585 #[doc = "Enable the PLL clock output."]
586 pub mod ENABLE {
587 pub const offset: u32 = 13;
588 pub const mask: u32 = 0x01 << offset;
589 pub mod R {}
590 pub mod W {}
591 pub mod RW {}
592 }
593 #[doc = "Determines the bypass source."]
594 pub mod BYPASS_CLK_SRC {
595 pub const offset: u32 = 14;
596 pub const mask: u32 = 0x03 << offset;
597 pub mod R {}
598 pub mod W {}
599 pub mod RW {
600 #[doc = "Select the 24MHz oscillator as source."]
601 pub const REF_CLK_24M: u32 = 0;
602 #[doc = "Select the CLK1_N / CLK1_P as source."]
603 pub const CLK1: u32 = 0x01;
604 }
605 }
606 #[doc = "Bypass the PLL."]
607 pub mod BYPASS {
608 pub const offset: u32 = 16;
609 pub const mask: u32 = 0x01 << offset;
610 pub mod R {}
611 pub mod W {}
612 pub mod RW {}
613 }
614 #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."]
615 pub mod LOCK {
616 pub const offset: u32 = 31;
617 pub const mask: u32 = 0x01 << offset;
618 pub mod R {}
619 pub mod W {}
620 pub mod RW {}
621 }
622}
623#[doc = "Analog USB2 480MHz PLL Control Register"]
624pub mod PLL_USB2 {
625 #[doc = "This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22."]
626 pub mod DIV_SELECT {
627 pub const offset: u32 = 1;
628 pub const mask: u32 = 0x01 << offset;
629 pub mod R {}
630 pub mod W {}
631 pub mod RW {}
632 }
633 #[doc = "0: 8-phase PLL outputs for USBPHY1 are powered down"]
634 pub mod EN_USB_CLKS {
635 pub const offset: u32 = 6;
636 pub const mask: u32 = 0x01 << offset;
637 pub mod R {}
638 pub mod W {}
639 pub mod RW {}
640 }
641 #[doc = "Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens."]
642 pub mod POWER {
643 pub const offset: u32 = 12;
644 pub const mask: u32 = 0x01 << offset;
645 pub mod R {}
646 pub mod W {}
647 pub mod RW {}
648 }
649 #[doc = "Enable the PLL clock output."]
650 pub mod ENABLE {
651 pub const offset: u32 = 13;
652 pub const mask: u32 = 0x01 << offset;
653 pub mod R {}
654 pub mod W {}
655 pub mod RW {}
656 }
657 #[doc = "Determines the bypass source."]
658 pub mod BYPASS_CLK_SRC {
659 pub const offset: u32 = 14;
660 pub const mask: u32 = 0x03 << offset;
661 pub mod R {}
662 pub mod W {}
663 pub mod RW {
664 #[doc = "Select the 24MHz oscillator as source."]
665 pub const REF_CLK_24M: u32 = 0;
666 #[doc = "Select the CLK1_N / CLK1_P as source."]
667 pub const CLK1: u32 = 0x01;
668 }
669 }
670 #[doc = "Bypass the PLL."]
671 pub mod BYPASS {
672 pub const offset: u32 = 16;
673 pub const mask: u32 = 0x01 << offset;
674 pub mod R {}
675 pub mod W {}
676 pub mod RW {}
677 }
678 #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."]
679 pub mod LOCK {
680 pub const offset: u32 = 31;
681 pub const mask: u32 = 0x01 << offset;
682 pub mod R {}
683 pub mod W {}
684 pub mod RW {}
685 }
686}
687#[doc = "Analog USB2 480MHz PLL Control Register"]
688pub mod PLL_USB2_SET {
689 #[doc = "This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22."]
690 pub mod DIV_SELECT {
691 pub const offset: u32 = 1;
692 pub const mask: u32 = 0x01 << offset;
693 pub mod R {}
694 pub mod W {}
695 pub mod RW {}
696 }
697 #[doc = "0: 8-phase PLL outputs for USBPHY1 are powered down"]
698 pub mod EN_USB_CLKS {
699 pub const offset: u32 = 6;
700 pub const mask: u32 = 0x01 << offset;
701 pub mod R {}
702 pub mod W {}
703 pub mod RW {}
704 }
705 #[doc = "Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens."]
706 pub mod POWER {
707 pub const offset: u32 = 12;
708 pub const mask: u32 = 0x01 << offset;
709 pub mod R {}
710 pub mod W {}
711 pub mod RW {}
712 }
713 #[doc = "Enable the PLL clock output."]
714 pub mod ENABLE {
715 pub const offset: u32 = 13;
716 pub const mask: u32 = 0x01 << offset;
717 pub mod R {}
718 pub mod W {}
719 pub mod RW {}
720 }
721 #[doc = "Determines the bypass source."]
722 pub mod BYPASS_CLK_SRC {
723 pub const offset: u32 = 14;
724 pub const mask: u32 = 0x03 << offset;
725 pub mod R {}
726 pub mod W {}
727 pub mod RW {
728 #[doc = "Select the 24MHz oscillator as source."]
729 pub const REF_CLK_24M: u32 = 0;
730 #[doc = "Select the CLK1_N / CLK1_P as source."]
731 pub const CLK1: u32 = 0x01;
732 }
733 }
734 #[doc = "Bypass the PLL."]
735 pub mod BYPASS {
736 pub const offset: u32 = 16;
737 pub const mask: u32 = 0x01 << offset;
738 pub mod R {}
739 pub mod W {}
740 pub mod RW {}
741 }
742 #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."]
743 pub mod LOCK {
744 pub const offset: u32 = 31;
745 pub const mask: u32 = 0x01 << offset;
746 pub mod R {}
747 pub mod W {}
748 pub mod RW {}
749 }
750}
751#[doc = "Analog USB2 480MHz PLL Control Register"]
752pub mod PLL_USB2_CLR {
753 #[doc = "This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22."]
754 pub mod DIV_SELECT {
755 pub const offset: u32 = 1;
756 pub const mask: u32 = 0x01 << offset;
757 pub mod R {}
758 pub mod W {}
759 pub mod RW {}
760 }
761 #[doc = "0: 8-phase PLL outputs for USBPHY1 are powered down"]
762 pub mod EN_USB_CLKS {
763 pub const offset: u32 = 6;
764 pub const mask: u32 = 0x01 << offset;
765 pub mod R {}
766 pub mod W {}
767 pub mod RW {}
768 }
769 #[doc = "Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens."]
770 pub mod POWER {
771 pub const offset: u32 = 12;
772 pub const mask: u32 = 0x01 << offset;
773 pub mod R {}
774 pub mod W {}
775 pub mod RW {}
776 }
777 #[doc = "Enable the PLL clock output."]
778 pub mod ENABLE {
779 pub const offset: u32 = 13;
780 pub const mask: u32 = 0x01 << offset;
781 pub mod R {}
782 pub mod W {}
783 pub mod RW {}
784 }
785 #[doc = "Determines the bypass source."]
786 pub mod BYPASS_CLK_SRC {
787 pub const offset: u32 = 14;
788 pub const mask: u32 = 0x03 << offset;
789 pub mod R {}
790 pub mod W {}
791 pub mod RW {
792 #[doc = "Select the 24MHz oscillator as source."]
793 pub const REF_CLK_24M: u32 = 0;
794 #[doc = "Select the CLK1_N / CLK1_P as source."]
795 pub const CLK1: u32 = 0x01;
796 }
797 }
798 #[doc = "Bypass the PLL."]
799 pub mod BYPASS {
800 pub const offset: u32 = 16;
801 pub const mask: u32 = 0x01 << offset;
802 pub mod R {}
803 pub mod W {}
804 pub mod RW {}
805 }
806 #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."]
807 pub mod LOCK {
808 pub const offset: u32 = 31;
809 pub const mask: u32 = 0x01 << offset;
810 pub mod R {}
811 pub mod W {}
812 pub mod RW {}
813 }
814}
815#[doc = "Analog USB2 480MHz PLL Control Register"]
816pub mod PLL_USB2_TOG {
817 #[doc = "This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22."]
818 pub mod DIV_SELECT {
819 pub const offset: u32 = 1;
820 pub const mask: u32 = 0x01 << offset;
821 pub mod R {}
822 pub mod W {}
823 pub mod RW {}
824 }
825 #[doc = "0: 8-phase PLL outputs for USBPHY1 are powered down"]
826 pub mod EN_USB_CLKS {
827 pub const offset: u32 = 6;
828 pub const mask: u32 = 0x01 << offset;
829 pub mod R {}
830 pub mod W {}
831 pub mod RW {}
832 }
833 #[doc = "Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens."]
834 pub mod POWER {
835 pub const offset: u32 = 12;
836 pub const mask: u32 = 0x01 << offset;
837 pub mod R {}
838 pub mod W {}
839 pub mod RW {}
840 }
841 #[doc = "Enable the PLL clock output."]
842 pub mod ENABLE {
843 pub const offset: u32 = 13;
844 pub const mask: u32 = 0x01 << offset;
845 pub mod R {}
846 pub mod W {}
847 pub mod RW {}
848 }
849 #[doc = "Determines the bypass source."]
850 pub mod BYPASS_CLK_SRC {
851 pub const offset: u32 = 14;
852 pub const mask: u32 = 0x03 << offset;
853 pub mod R {}
854 pub mod W {}
855 pub mod RW {
856 #[doc = "Select the 24MHz oscillator as source."]
857 pub const REF_CLK_24M: u32 = 0;
858 #[doc = "Select the CLK1_N / CLK1_P as source."]
859 pub const CLK1: u32 = 0x01;
860 }
861 }
862 #[doc = "Bypass the PLL."]
863 pub mod BYPASS {
864 pub const offset: u32 = 16;
865 pub const mask: u32 = 0x01 << offset;
866 pub mod R {}
867 pub mod W {}
868 pub mod RW {}
869 }
870 #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."]
871 pub mod LOCK {
872 pub const offset: u32 = 31;
873 pub const mask: u32 = 0x01 << offset;
874 pub mod R {}
875 pub mod W {}
876 pub mod RW {}
877 }
878}
879#[doc = "Analog System PLL Control Register"]
880pub mod PLL_SYS {
881 #[doc = "This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22."]
882 pub mod DIV_SELECT {
883 pub const offset: u32 = 0;
884 pub const mask: u32 = 0x01 << offset;
885 pub mod R {}
886 pub mod W {}
887 pub mod RW {}
888 }
889 #[doc = "Powers down the PLL."]
890 pub mod POWERDOWN {
891 pub const offset: u32 = 12;
892 pub const mask: u32 = 0x01 << offset;
893 pub mod R {}
894 pub mod W {}
895 pub mod RW {}
896 }
897 #[doc = "Enable PLL output"]
898 pub mod ENABLE {
899 pub const offset: u32 = 13;
900 pub const mask: u32 = 0x01 << offset;
901 pub mod R {}
902 pub mod W {}
903 pub mod RW {}
904 }
905 #[doc = "Determines the bypass source."]
906 pub mod BYPASS_CLK_SRC {
907 pub const offset: u32 = 14;
908 pub const mask: u32 = 0x03 << offset;
909 pub mod R {}
910 pub mod W {}
911 pub mod RW {
912 #[doc = "Select the 24MHz oscillator as source."]
913 pub const REF_CLK_24M: u32 = 0;
914 #[doc = "Select the CLK1_N / CLK1_P as source."]
915 pub const CLK1: u32 = 0x01;
916 }
917 }
918 #[doc = "Bypass the PLL."]
919 pub mod BYPASS {
920 pub const offset: u32 = 16;
921 pub const mask: u32 = 0x01 << offset;
922 pub mod R {}
923 pub mod W {}
924 pub mod RW {}
925 }
926 #[doc = "1 - PLL is currently locked; 0 - PLL is not currently locked."]
927 pub mod LOCK {
928 pub const offset: u32 = 31;
929 pub const mask: u32 = 0x01 << offset;
930 pub mod R {}
931 pub mod W {}
932 pub mod RW {}
933 }
934}
935#[doc = "Analog System PLL Control Register"]
936pub mod PLL_SYS_SET {
937 #[doc = "This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22."]
938 pub mod DIV_SELECT {
939 pub const offset: u32 = 0;
940 pub const mask: u32 = 0x01 << offset;
941 pub mod R {}
942 pub mod W {}
943 pub mod RW {}
944 }
945 #[doc = "Powers down the PLL."]
946 pub mod POWERDOWN {
947 pub const offset: u32 = 12;
948 pub const mask: u32 = 0x01 << offset;
949 pub mod R {}
950 pub mod W {}
951 pub mod RW {}
952 }
953 #[doc = "Enable PLL output"]
954 pub mod ENABLE {
955 pub const offset: u32 = 13;
956 pub const mask: u32 = 0x01 << offset;
957 pub mod R {}
958 pub mod W {}
959 pub mod RW {}
960 }
961 #[doc = "Determines the bypass source."]
962 pub mod BYPASS_CLK_SRC {
963 pub const offset: u32 = 14;
964 pub const mask: u32 = 0x03 << offset;
965 pub mod R {}
966 pub mod W {}
967 pub mod RW {
968 #[doc = "Select the 24MHz oscillator as source."]
969 pub const REF_CLK_24M: u32 = 0;
970 #[doc = "Select the CLK1_N / CLK1_P as source."]
971 pub const CLK1: u32 = 0x01;
972 }
973 }
974 #[doc = "Bypass the PLL."]
975 pub mod BYPASS {
976 pub const offset: u32 = 16;
977 pub const mask: u32 = 0x01 << offset;
978 pub mod R {}
979 pub mod W {}
980 pub mod RW {}
981 }
982 #[doc = "1 - PLL is currently locked; 0 - PLL is not currently locked."]
983 pub mod LOCK {
984 pub const offset: u32 = 31;
985 pub const mask: u32 = 0x01 << offset;
986 pub mod R {}
987 pub mod W {}
988 pub mod RW {}
989 }
990}
991#[doc = "Analog System PLL Control Register"]
992pub mod PLL_SYS_CLR {
993 #[doc = "This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22."]
994 pub mod DIV_SELECT {
995 pub const offset: u32 = 0;
996 pub const mask: u32 = 0x01 << offset;
997 pub mod R {}
998 pub mod W {}
999 pub mod RW {}
1000 }
1001 #[doc = "Powers down the PLL."]
1002 pub mod POWERDOWN {
1003 pub const offset: u32 = 12;
1004 pub const mask: u32 = 0x01 << offset;
1005 pub mod R {}
1006 pub mod W {}
1007 pub mod RW {}
1008 }
1009 #[doc = "Enable PLL output"]
1010 pub mod ENABLE {
1011 pub const offset: u32 = 13;
1012 pub const mask: u32 = 0x01 << offset;
1013 pub mod R {}
1014 pub mod W {}
1015 pub mod RW {}
1016 }
1017 #[doc = "Determines the bypass source."]
1018 pub mod BYPASS_CLK_SRC {
1019 pub const offset: u32 = 14;
1020 pub const mask: u32 = 0x03 << offset;
1021 pub mod R {}
1022 pub mod W {}
1023 pub mod RW {
1024 #[doc = "Select the 24MHz oscillator as source."]
1025 pub const REF_CLK_24M: u32 = 0;
1026 #[doc = "Select the CLK1_N / CLK1_P as source."]
1027 pub const CLK1: u32 = 0x01;
1028 }
1029 }
1030 #[doc = "Bypass the PLL."]
1031 pub mod BYPASS {
1032 pub const offset: u32 = 16;
1033 pub const mask: u32 = 0x01 << offset;
1034 pub mod R {}
1035 pub mod W {}
1036 pub mod RW {}
1037 }
1038 #[doc = "1 - PLL is currently locked; 0 - PLL is not currently locked."]
1039 pub mod LOCK {
1040 pub const offset: u32 = 31;
1041 pub const mask: u32 = 0x01 << offset;
1042 pub mod R {}
1043 pub mod W {}
1044 pub mod RW {}
1045 }
1046}
1047#[doc = "Analog System PLL Control Register"]
1048pub mod PLL_SYS_TOG {
1049 #[doc = "This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22."]
1050 pub mod DIV_SELECT {
1051 pub const offset: u32 = 0;
1052 pub const mask: u32 = 0x01 << offset;
1053 pub mod R {}
1054 pub mod W {}
1055 pub mod RW {}
1056 }
1057 #[doc = "Powers down the PLL."]
1058 pub mod POWERDOWN {
1059 pub const offset: u32 = 12;
1060 pub const mask: u32 = 0x01 << offset;
1061 pub mod R {}
1062 pub mod W {}
1063 pub mod RW {}
1064 }
1065 #[doc = "Enable PLL output"]
1066 pub mod ENABLE {
1067 pub const offset: u32 = 13;
1068 pub const mask: u32 = 0x01 << offset;
1069 pub mod R {}
1070 pub mod W {}
1071 pub mod RW {}
1072 }
1073 #[doc = "Determines the bypass source."]
1074 pub mod BYPASS_CLK_SRC {
1075 pub const offset: u32 = 14;
1076 pub const mask: u32 = 0x03 << offset;
1077 pub mod R {}
1078 pub mod W {}
1079 pub mod RW {
1080 #[doc = "Select the 24MHz oscillator as source."]
1081 pub const REF_CLK_24M: u32 = 0;
1082 #[doc = "Select the CLK1_N / CLK1_P as source."]
1083 pub const CLK1: u32 = 0x01;
1084 }
1085 }
1086 #[doc = "Bypass the PLL."]
1087 pub mod BYPASS {
1088 pub const offset: u32 = 16;
1089 pub const mask: u32 = 0x01 << offset;
1090 pub mod R {}
1091 pub mod W {}
1092 pub mod RW {}
1093 }
1094 #[doc = "1 - PLL is currently locked; 0 - PLL is not currently locked."]
1095 pub mod LOCK {
1096 pub const offset: u32 = 31;
1097 pub const mask: u32 = 0x01 << offset;
1098 pub mod R {}
1099 pub mod W {}
1100 pub mod RW {}
1101 }
1102}
1103#[doc = "528MHz System PLL Spread Spectrum Register"]
1104pub mod PLL_SYS_SS {
1105 #[doc = "Frequency change step = step/CCM_ANALOG_PLL_SYS_DENOM\\[B\\]*24MHz."]
1106 pub mod STEP {
1107 pub const offset: u32 = 0;
1108 pub const mask: u32 = 0x7fff << offset;
1109 pub mod R {}
1110 pub mod W {}
1111 pub mod RW {}
1112 }
1113 #[doc = "Enable bit"]
1114 pub mod ENABLE {
1115 pub const offset: u32 = 15;
1116 pub const mask: u32 = 0x01 << offset;
1117 pub mod R {}
1118 pub mod W {}
1119 pub mod RW {
1120 #[doc = "Spread spectrum modulation disabled"]
1121 pub const ENABLE_0: u32 = 0;
1122 #[doc = "Soread spectrum modulation enabled"]
1123 pub const ENABLE_1: u32 = 0x01;
1124 }
1125 }
1126 #[doc = "Frequency change = stop/CCM_ANALOG_PLL_SYS_DENOM\\[B\\]*24MHz."]
1127 pub mod STOP {
1128 pub const offset: u32 = 16;
1129 pub const mask: u32 = 0xffff << offset;
1130 pub mod R {}
1131 pub mod W {}
1132 pub mod RW {}
1133 }
1134}
1135#[doc = "Numerator of 528MHz System PLL Fractional Loop Divider Register"]
1136pub mod PLL_SYS_NUM {
1137 #[doc = "30 bit numerator (A) of fractional loop divider (signed integer)."]
1138 pub mod A {
1139 pub const offset: u32 = 0;
1140 pub const mask: u32 = 0x3fff_ffff << offset;
1141 pub mod R {}
1142 pub mod W {}
1143 pub mod RW {}
1144 }
1145}
1146#[doc = "Denominator of 528MHz System PLL Fractional Loop Divider Register"]
1147pub mod PLL_SYS_DENOM {
1148 #[doc = "30 bit denominator (B) of fractional loop divider (unsigned integer)."]
1149 pub mod B {
1150 pub const offset: u32 = 0;
1151 pub const mask: u32 = 0x3fff_ffff << offset;
1152 pub mod R {}
1153 pub mod W {}
1154 pub mod RW {}
1155 }
1156}
1157#[doc = "Analog Audio PLL control Register"]
1158pub mod PLL_AUDIO {
1159 #[doc = "This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54."]
1160 pub mod DIV_SELECT {
1161 pub const offset: u32 = 0;
1162 pub const mask: u32 = 0x7f << offset;
1163 pub mod R {}
1164 pub mod W {}
1165 pub mod RW {}
1166 }
1167 #[doc = "Powers down the PLL."]
1168 pub mod POWERDOWN {
1169 pub const offset: u32 = 12;
1170 pub const mask: u32 = 0x01 << offset;
1171 pub mod R {}
1172 pub mod W {}
1173 pub mod RW {}
1174 }
1175 #[doc = "Enable PLL output"]
1176 pub mod ENABLE {
1177 pub const offset: u32 = 13;
1178 pub const mask: u32 = 0x01 << offset;
1179 pub mod R {}
1180 pub mod W {}
1181 pub mod RW {}
1182 }
1183 #[doc = "Determines the bypass source."]
1184 pub mod BYPASS_CLK_SRC {
1185 pub const offset: u32 = 14;
1186 pub const mask: u32 = 0x03 << offset;
1187 pub mod R {}
1188 pub mod W {}
1189 pub mod RW {
1190 #[doc = "Select the 24MHz oscillator as source."]
1191 pub const REF_CLK_24M: u32 = 0;
1192 #[doc = "Select the CLK1_N / CLK1_P as source."]
1193 pub const CLK1: u32 = 0x01;
1194 }
1195 }
1196 #[doc = "Bypass the PLL."]
1197 pub mod BYPASS {
1198 pub const offset: u32 = 16;
1199 pub const mask: u32 = 0x01 << offset;
1200 pub mod R {}
1201 pub mod W {}
1202 pub mod RW {}
1203 }
1204 #[doc = "These bits implement a divider after the PLL, but before the enable and bypass mux."]
1205 pub mod POST_DIV_SELECT {
1206 pub const offset: u32 = 19;
1207 pub const mask: u32 = 0x03 << offset;
1208 pub mod R {}
1209 pub mod W {}
1210 pub mod RW {
1211 #[doc = "Divide by 4."]
1212 pub const POST_DIV_SELECT_0: u32 = 0;
1213 #[doc = "Divide by 2."]
1214 pub const POST_DIV_SELECT_1: u32 = 0x01;
1215 #[doc = "Divide by 1."]
1216 pub const POST_DIV_SELECT_2: u32 = 0x02;
1217 }
1218 }
1219 #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."]
1220 pub mod LOCK {
1221 pub const offset: u32 = 31;
1222 pub const mask: u32 = 0x01 << offset;
1223 pub mod R {}
1224 pub mod W {}
1225 pub mod RW {}
1226 }
1227}
1228#[doc = "Analog Audio PLL control Register"]
1229pub mod PLL_AUDIO_SET {
1230 #[doc = "This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54."]
1231 pub mod DIV_SELECT {
1232 pub const offset: u32 = 0;
1233 pub const mask: u32 = 0x7f << offset;
1234 pub mod R {}
1235 pub mod W {}
1236 pub mod RW {}
1237 }
1238 #[doc = "Powers down the PLL."]
1239 pub mod POWERDOWN {
1240 pub const offset: u32 = 12;
1241 pub const mask: u32 = 0x01 << offset;
1242 pub mod R {}
1243 pub mod W {}
1244 pub mod RW {}
1245 }
1246 #[doc = "Enable PLL output"]
1247 pub mod ENABLE {
1248 pub const offset: u32 = 13;
1249 pub const mask: u32 = 0x01 << offset;
1250 pub mod R {}
1251 pub mod W {}
1252 pub mod RW {}
1253 }
1254 #[doc = "Determines the bypass source."]
1255 pub mod BYPASS_CLK_SRC {
1256 pub const offset: u32 = 14;
1257 pub const mask: u32 = 0x03 << offset;
1258 pub mod R {}
1259 pub mod W {}
1260 pub mod RW {
1261 #[doc = "Select the 24MHz oscillator as source."]
1262 pub const REF_CLK_24M: u32 = 0;
1263 #[doc = "Select the CLK1_N / CLK1_P as source."]
1264 pub const CLK1: u32 = 0x01;
1265 }
1266 }
1267 #[doc = "Bypass the PLL."]
1268 pub mod BYPASS {
1269 pub const offset: u32 = 16;
1270 pub const mask: u32 = 0x01 << offset;
1271 pub mod R {}
1272 pub mod W {}
1273 pub mod RW {}
1274 }
1275 #[doc = "These bits implement a divider after the PLL, but before the enable and bypass mux."]
1276 pub mod POST_DIV_SELECT {
1277 pub const offset: u32 = 19;
1278 pub const mask: u32 = 0x03 << offset;
1279 pub mod R {}
1280 pub mod W {}
1281 pub mod RW {
1282 #[doc = "Divide by 4."]
1283 pub const POST_DIV_SELECT_0: u32 = 0;
1284 #[doc = "Divide by 2."]
1285 pub const POST_DIV_SELECT_1: u32 = 0x01;
1286 #[doc = "Divide by 1."]
1287 pub const POST_DIV_SELECT_2: u32 = 0x02;
1288 }
1289 }
1290 #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."]
1291 pub mod LOCK {
1292 pub const offset: u32 = 31;
1293 pub const mask: u32 = 0x01 << offset;
1294 pub mod R {}
1295 pub mod W {}
1296 pub mod RW {}
1297 }
1298}
1299#[doc = "Analog Audio PLL control Register"]
1300pub mod PLL_AUDIO_CLR {
1301 #[doc = "This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54."]
1302 pub mod DIV_SELECT {
1303 pub const offset: u32 = 0;
1304 pub const mask: u32 = 0x7f << offset;
1305 pub mod R {}
1306 pub mod W {}
1307 pub mod RW {}
1308 }
1309 #[doc = "Powers down the PLL."]
1310 pub mod POWERDOWN {
1311 pub const offset: u32 = 12;
1312 pub const mask: u32 = 0x01 << offset;
1313 pub mod R {}
1314 pub mod W {}
1315 pub mod RW {}
1316 }
1317 #[doc = "Enable PLL output"]
1318 pub mod ENABLE {
1319 pub const offset: u32 = 13;
1320 pub const mask: u32 = 0x01 << offset;
1321 pub mod R {}
1322 pub mod W {}
1323 pub mod RW {}
1324 }
1325 #[doc = "Determines the bypass source."]
1326 pub mod BYPASS_CLK_SRC {
1327 pub const offset: u32 = 14;
1328 pub const mask: u32 = 0x03 << offset;
1329 pub mod R {}
1330 pub mod W {}
1331 pub mod RW {
1332 #[doc = "Select the 24MHz oscillator as source."]
1333 pub const REF_CLK_24M: u32 = 0;
1334 #[doc = "Select the CLK1_N / CLK1_P as source."]
1335 pub const CLK1: u32 = 0x01;
1336 }
1337 }
1338 #[doc = "Bypass the PLL."]
1339 pub mod BYPASS {
1340 pub const offset: u32 = 16;
1341 pub const mask: u32 = 0x01 << offset;
1342 pub mod R {}
1343 pub mod W {}
1344 pub mod RW {}
1345 }
1346 #[doc = "These bits implement a divider after the PLL, but before the enable and bypass mux."]
1347 pub mod POST_DIV_SELECT {
1348 pub const offset: u32 = 19;
1349 pub const mask: u32 = 0x03 << offset;
1350 pub mod R {}
1351 pub mod W {}
1352 pub mod RW {
1353 #[doc = "Divide by 4."]
1354 pub const POST_DIV_SELECT_0: u32 = 0;
1355 #[doc = "Divide by 2."]
1356 pub const POST_DIV_SELECT_1: u32 = 0x01;
1357 #[doc = "Divide by 1."]
1358 pub const POST_DIV_SELECT_2: u32 = 0x02;
1359 }
1360 }
1361 #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."]
1362 pub mod LOCK {
1363 pub const offset: u32 = 31;
1364 pub const mask: u32 = 0x01 << offset;
1365 pub mod R {}
1366 pub mod W {}
1367 pub mod RW {}
1368 }
1369}
1370#[doc = "Analog Audio PLL control Register"]
1371pub mod PLL_AUDIO_TOG {
1372 #[doc = "This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54."]
1373 pub mod DIV_SELECT {
1374 pub const offset: u32 = 0;
1375 pub const mask: u32 = 0x7f << offset;
1376 pub mod R {}
1377 pub mod W {}
1378 pub mod RW {}
1379 }
1380 #[doc = "Powers down the PLL."]
1381 pub mod POWERDOWN {
1382 pub const offset: u32 = 12;
1383 pub const mask: u32 = 0x01 << offset;
1384 pub mod R {}
1385 pub mod W {}
1386 pub mod RW {}
1387 }
1388 #[doc = "Enable PLL output"]
1389 pub mod ENABLE {
1390 pub const offset: u32 = 13;
1391 pub const mask: u32 = 0x01 << offset;
1392 pub mod R {}
1393 pub mod W {}
1394 pub mod RW {}
1395 }
1396 #[doc = "Determines the bypass source."]
1397 pub mod BYPASS_CLK_SRC {
1398 pub const offset: u32 = 14;
1399 pub const mask: u32 = 0x03 << offset;
1400 pub mod R {}
1401 pub mod W {}
1402 pub mod RW {
1403 #[doc = "Select the 24MHz oscillator as source."]
1404 pub const REF_CLK_24M: u32 = 0;
1405 #[doc = "Select the CLK1_N / CLK1_P as source."]
1406 pub const CLK1: u32 = 0x01;
1407 }
1408 }
1409 #[doc = "Bypass the PLL."]
1410 pub mod BYPASS {
1411 pub const offset: u32 = 16;
1412 pub const mask: u32 = 0x01 << offset;
1413 pub mod R {}
1414 pub mod W {}
1415 pub mod RW {}
1416 }
1417 #[doc = "These bits implement a divider after the PLL, but before the enable and bypass mux."]
1418 pub mod POST_DIV_SELECT {
1419 pub const offset: u32 = 19;
1420 pub const mask: u32 = 0x03 << offset;
1421 pub mod R {}
1422 pub mod W {}
1423 pub mod RW {
1424 #[doc = "Divide by 4."]
1425 pub const POST_DIV_SELECT_0: u32 = 0;
1426 #[doc = "Divide by 2."]
1427 pub const POST_DIV_SELECT_1: u32 = 0x01;
1428 #[doc = "Divide by 1."]
1429 pub const POST_DIV_SELECT_2: u32 = 0x02;
1430 }
1431 }
1432 #[doc = "1 - PLL is currently locked. 0 - PLL is not currently locked."]
1433 pub mod LOCK {
1434 pub const offset: u32 = 31;
1435 pub const mask: u32 = 0x01 << offset;
1436 pub mod R {}
1437 pub mod W {}
1438 pub mod RW {}
1439 }
1440}
1441#[doc = "Numerator of Audio PLL Fractional Loop Divider Register"]
1442pub mod PLL_AUDIO_NUM {
1443 #[doc = "30 bit numerator of fractional loop divider."]
1444 pub mod A {
1445 pub const offset: u32 = 0;
1446 pub const mask: u32 = 0x3fff_ffff << offset;
1447 pub mod R {}
1448 pub mod W {}
1449 pub mod RW {}
1450 }
1451}
1452#[doc = "Denominator of Audio PLL Fractional Loop Divider Register"]
1453pub mod PLL_AUDIO_DENOM {
1454 #[doc = "30 bit denominator of fractional loop divider."]
1455 pub mod B {
1456 pub const offset: u32 = 0;
1457 pub const mask: u32 = 0x3fff_ffff << offset;
1458 pub mod R {}
1459 pub mod W {}
1460 pub mod RW {}
1461 }
1462}
1463#[doc = "Analog Video PLL control Register"]
1464pub mod PLL_VIDEO {
1465 #[doc = "This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54."]
1466 pub mod DIV_SELECT {
1467 pub const offset: u32 = 0;
1468 pub const mask: u32 = 0x7f << offset;
1469 pub mod R {}
1470 pub mod W {}
1471 pub mod RW {}
1472 }
1473 #[doc = "Powers down the PLL."]
1474 pub mod POWERDOWN {
1475 pub const offset: u32 = 12;
1476 pub const mask: u32 = 0x01 << offset;
1477 pub mod R {}
1478 pub mod W {}
1479 pub mod RW {}
1480 }
1481 #[doc = "Enalbe PLL output"]
1482 pub mod ENABLE {
1483 pub const offset: u32 = 13;
1484 pub const mask: u32 = 0x01 << offset;
1485 pub mod R {}
1486 pub mod W {}
1487 pub mod RW {}
1488 }
1489 #[doc = "Determines the bypass source."]
1490 pub mod BYPASS_CLK_SRC {
1491 pub const offset: u32 = 14;
1492 pub const mask: u32 = 0x03 << offset;
1493 pub mod R {}
1494 pub mod W {}
1495 pub mod RW {
1496 #[doc = "Select the 24MHz oscillator as source."]
1497 pub const REF_CLK_24M: u32 = 0;
1498 #[doc = "Select the CLK1_N / CLK1_P as source."]
1499 pub const CLK1: u32 = 0x01;
1500 }
1501 }
1502 #[doc = "Bypass the PLL."]
1503 pub mod BYPASS {
1504 pub const offset: u32 = 16;
1505 pub const mask: u32 = 0x01 << offset;
1506 pub mod R {}
1507 pub mod W {}
1508 pub mod RW {}
1509 }
1510 #[doc = "These bits implement a divider after the PLL, but before the enable and bypass mux."]
1511 pub mod POST_DIV_SELECT {
1512 pub const offset: u32 = 19;
1513 pub const mask: u32 = 0x03 << offset;
1514 pub mod R {}
1515 pub mod W {}
1516 pub mod RW {
1517 #[doc = "Divide by 4."]
1518 pub const POST_DIV_SELECT_0: u32 = 0;
1519 #[doc = "Divide by 2."]
1520 pub const POST_DIV_SELECT_1: u32 = 0x01;
1521 #[doc = "Divide by 1."]
1522 pub const POST_DIV_SELECT_2: u32 = 0x02;
1523 }
1524 }
1525 #[doc = "1 - PLL is currently locked; 0 - PLL is not currently locked."]
1526 pub mod LOCK {
1527 pub const offset: u32 = 31;
1528 pub const mask: u32 = 0x01 << offset;
1529 pub mod R {}
1530 pub mod W {}
1531 pub mod RW {}
1532 }
1533}
1534#[doc = "Analog Video PLL control Register"]
1535pub mod PLL_VIDEO_SET {
1536 #[doc = "This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54."]
1537 pub mod DIV_SELECT {
1538 pub const offset: u32 = 0;
1539 pub const mask: u32 = 0x7f << offset;
1540 pub mod R {}
1541 pub mod W {}
1542 pub mod RW {}
1543 }
1544 #[doc = "Powers down the PLL."]
1545 pub mod POWERDOWN {
1546 pub const offset: u32 = 12;
1547 pub const mask: u32 = 0x01 << offset;
1548 pub mod R {}
1549 pub mod W {}
1550 pub mod RW {}
1551 }
1552 #[doc = "Enalbe PLL output"]
1553 pub mod ENABLE {
1554 pub const offset: u32 = 13;
1555 pub const mask: u32 = 0x01 << offset;
1556 pub mod R {}
1557 pub mod W {}
1558 pub mod RW {}
1559 }
1560 #[doc = "Determines the bypass source."]
1561 pub mod BYPASS_CLK_SRC {
1562 pub const offset: u32 = 14;
1563 pub const mask: u32 = 0x03 << offset;
1564 pub mod R {}
1565 pub mod W {}
1566 pub mod RW {
1567 #[doc = "Select the 24MHz oscillator as source."]
1568 pub const REF_CLK_24M: u32 = 0;
1569 #[doc = "Select the CLK1_N / CLK1_P as source."]
1570 pub const CLK1: u32 = 0x01;
1571 }
1572 }
1573 #[doc = "Bypass the PLL."]
1574 pub mod BYPASS {
1575 pub const offset: u32 = 16;
1576 pub const mask: u32 = 0x01 << offset;
1577 pub mod R {}
1578 pub mod W {}
1579 pub mod RW {}
1580 }
1581 #[doc = "These bits implement a divider after the PLL, but before the enable and bypass mux."]
1582 pub mod POST_DIV_SELECT {
1583 pub const offset: u32 = 19;
1584 pub const mask: u32 = 0x03 << offset;
1585 pub mod R {}
1586 pub mod W {}
1587 pub mod RW {
1588 #[doc = "Divide by 4."]
1589 pub const POST_DIV_SELECT_0: u32 = 0;
1590 #[doc = "Divide by 2."]
1591 pub const POST_DIV_SELECT_1: u32 = 0x01;
1592 #[doc = "Divide by 1."]
1593 pub const POST_DIV_SELECT_2: u32 = 0x02;
1594 }
1595 }
1596 #[doc = "1 - PLL is currently locked; 0 - PLL is not currently locked."]
1597 pub mod LOCK {
1598 pub const offset: u32 = 31;
1599 pub const mask: u32 = 0x01 << offset;
1600 pub mod R {}
1601 pub mod W {}
1602 pub mod RW {}
1603 }
1604}
1605#[doc = "Analog Video PLL control Register"]
1606pub mod PLL_VIDEO_CLR {
1607 #[doc = "This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54."]
1608 pub mod DIV_SELECT {
1609 pub const offset: u32 = 0;
1610 pub const mask: u32 = 0x7f << offset;
1611 pub mod R {}
1612 pub mod W {}
1613 pub mod RW {}
1614 }
1615 #[doc = "Powers down the PLL."]
1616 pub mod POWERDOWN {
1617 pub const offset: u32 = 12;
1618 pub const mask: u32 = 0x01 << offset;
1619 pub mod R {}
1620 pub mod W {}
1621 pub mod RW {}
1622 }
1623 #[doc = "Enalbe PLL output"]
1624 pub mod ENABLE {
1625 pub const offset: u32 = 13;
1626 pub const mask: u32 = 0x01 << offset;
1627 pub mod R {}
1628 pub mod W {}
1629 pub mod RW {}
1630 }
1631 #[doc = "Determines the bypass source."]
1632 pub mod BYPASS_CLK_SRC {
1633 pub const offset: u32 = 14;
1634 pub const mask: u32 = 0x03 << offset;
1635 pub mod R {}
1636 pub mod W {}
1637 pub mod RW {
1638 #[doc = "Select the 24MHz oscillator as source."]
1639 pub const REF_CLK_24M: u32 = 0;
1640 #[doc = "Select the CLK1_N / CLK1_P as source."]
1641 pub const CLK1: u32 = 0x01;
1642 }
1643 }
1644 #[doc = "Bypass the PLL."]
1645 pub mod BYPASS {
1646 pub const offset: u32 = 16;
1647 pub const mask: u32 = 0x01 << offset;
1648 pub mod R {}
1649 pub mod W {}
1650 pub mod RW {}
1651 }
1652 #[doc = "These bits implement a divider after the PLL, but before the enable and bypass mux."]
1653 pub mod POST_DIV_SELECT {
1654 pub const offset: u32 = 19;
1655 pub const mask: u32 = 0x03 << offset;
1656 pub mod R {}
1657 pub mod W {}
1658 pub mod RW {
1659 #[doc = "Divide by 4."]
1660 pub const POST_DIV_SELECT_0: u32 = 0;
1661 #[doc = "Divide by 2."]
1662 pub const POST_DIV_SELECT_1: u32 = 0x01;
1663 #[doc = "Divide by 1."]
1664 pub const POST_DIV_SELECT_2: u32 = 0x02;
1665 }
1666 }
1667 #[doc = "1 - PLL is currently locked; 0 - PLL is not currently locked."]
1668 pub mod LOCK {
1669 pub const offset: u32 = 31;
1670 pub const mask: u32 = 0x01 << offset;
1671 pub mod R {}
1672 pub mod W {}
1673 pub mod RW {}
1674 }
1675}
1676#[doc = "Analog Video PLL control Register"]
1677pub mod PLL_VIDEO_TOG {
1678 #[doc = "This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54."]
1679 pub mod DIV_SELECT {
1680 pub const offset: u32 = 0;
1681 pub const mask: u32 = 0x7f << offset;
1682 pub mod R {}
1683 pub mod W {}
1684 pub mod RW {}
1685 }
1686 #[doc = "Powers down the PLL."]
1687 pub mod POWERDOWN {
1688 pub const offset: u32 = 12;
1689 pub const mask: u32 = 0x01 << offset;
1690 pub mod R {}
1691 pub mod W {}
1692 pub mod RW {}
1693 }
1694 #[doc = "Enalbe PLL output"]
1695 pub mod ENABLE {
1696 pub const offset: u32 = 13;
1697 pub const mask: u32 = 0x01 << offset;
1698 pub mod R {}
1699 pub mod W {}
1700 pub mod RW {}
1701 }
1702 #[doc = "Determines the bypass source."]
1703 pub mod BYPASS_CLK_SRC {
1704 pub const offset: u32 = 14;
1705 pub const mask: u32 = 0x03 << offset;
1706 pub mod R {}
1707 pub mod W {}
1708 pub mod RW {
1709 #[doc = "Select the 24MHz oscillator as source."]
1710 pub const REF_CLK_24M: u32 = 0;
1711 #[doc = "Select the CLK1_N / CLK1_P as source."]
1712 pub const CLK1: u32 = 0x01;
1713 }
1714 }
1715 #[doc = "Bypass the PLL."]
1716 pub mod BYPASS {
1717 pub const offset: u32 = 16;
1718 pub const mask: u32 = 0x01 << offset;
1719 pub mod R {}
1720 pub mod W {}
1721 pub mod RW {}
1722 }
1723 #[doc = "These bits implement a divider after the PLL, but before the enable and bypass mux."]
1724 pub mod POST_DIV_SELECT {
1725 pub const offset: u32 = 19;
1726 pub const mask: u32 = 0x03 << offset;
1727 pub mod R {}
1728 pub mod W {}
1729 pub mod RW {
1730 #[doc = "Divide by 4."]
1731 pub const POST_DIV_SELECT_0: u32 = 0;
1732 #[doc = "Divide by 2."]
1733 pub const POST_DIV_SELECT_1: u32 = 0x01;
1734 #[doc = "Divide by 1."]
1735 pub const POST_DIV_SELECT_2: u32 = 0x02;
1736 }
1737 }
1738 #[doc = "1 - PLL is currently locked; 0 - PLL is not currently locked."]
1739 pub mod LOCK {
1740 pub const offset: u32 = 31;
1741 pub const mask: u32 = 0x01 << offset;
1742 pub mod R {}
1743 pub mod W {}
1744 pub mod RW {}
1745 }
1746}
1747#[doc = "Numerator of Video PLL Fractional Loop Divider Register"]
1748pub mod PLL_VIDEO_NUM {
1749 #[doc = "30 bit numerator of fractional loop divider(Signed number), absolute value should be less than denominator"]
1750 pub mod A {
1751 pub const offset: u32 = 0;
1752 pub const mask: u32 = 0x3fff_ffff << offset;
1753 pub mod R {}
1754 pub mod W {}
1755 pub mod RW {}
1756 }
1757}
1758#[doc = "Denominator of Video PLL Fractional Loop Divider Register"]
1759pub mod PLL_VIDEO_DENOM {
1760 #[doc = "30 bit Denominator of fractional loop divider."]
1761 pub mod B {
1762 pub const offset: u32 = 0;
1763 pub const mask: u32 = 0x3fff_ffff << offset;
1764 pub mod R {}
1765 pub mod W {}
1766 pub mod RW {}
1767 }
1768}
1769#[doc = "Analog ENET PLL Control Register"]
1770pub mod PLL_ENET {
1771 #[doc = "Controls the frequency of the ethernet reference clock"]
1772 pub mod DIV_SELECT {
1773 pub const offset: u32 = 0;
1774 pub const mask: u32 = 0x03 << offset;
1775 pub mod R {}
1776 pub mod W {}
1777 pub mod RW {}
1778 }
1779 #[doc = "Controls the frequency of the ENET2 reference clock."]
1780 pub mod ENET2_DIV_SELECT {
1781 pub const offset: u32 = 2;
1782 pub const mask: u32 = 0x03 << offset;
1783 pub mod R {}
1784 pub mod W {}
1785 pub mod RW {
1786 #[doc = "25MHz"]
1787 pub const ENET2_DIV_SELECT_0: u32 = 0;
1788 #[doc = "50MHz"]
1789 pub const ENET2_DIV_SELECT_1: u32 = 0x01;
1790 #[doc = "100MHz (not 50% duty cycle)"]
1791 pub const ENET2_DIV_SELECT_2: u32 = 0x02;
1792 #[doc = "125MHz"]
1793 pub const ENET2_DIV_SELECT_3: u32 = 0x03;
1794 }
1795 }
1796 #[doc = "Powers down the PLL."]
1797 pub mod POWERDOWN {
1798 pub const offset: u32 = 12;
1799 pub const mask: u32 = 0x01 << offset;
1800 pub mod R {}
1801 pub mod W {}
1802 pub mod RW {}
1803 }
1804 #[doc = "Enable the PLL providing the ENET reference clock."]
1805 pub mod ENABLE {
1806 pub const offset: u32 = 13;
1807 pub const mask: u32 = 0x01 << offset;
1808 pub mod R {}
1809 pub mod W {}
1810 pub mod RW {}
1811 }
1812 #[doc = "Determines the bypass source."]
1813 pub mod BYPASS_CLK_SRC {
1814 pub const offset: u32 = 14;
1815 pub const mask: u32 = 0x03 << offset;
1816 pub mod R {}
1817 pub mod W {}
1818 pub mod RW {
1819 #[doc = "Select the 24MHz oscillator as source."]
1820 pub const REF_CLK_24M: u32 = 0;
1821 #[doc = "Select the CLK1_N / CLK1_P as source."]
1822 pub const CLK1: u32 = 0x01;
1823 }
1824 }
1825 #[doc = "Bypass the PLL."]
1826 pub mod BYPASS {
1827 pub const offset: u32 = 16;
1828 pub const mask: u32 = 0x01 << offset;
1829 pub mod R {}
1830 pub mod W {}
1831 pub mod RW {}
1832 }
1833 #[doc = "Enable the PLL providing the ENET2 reference clock"]
1834 pub mod ENET2_REF_EN {
1835 pub const offset: u32 = 20;
1836 pub const mask: u32 = 0x01 << offset;
1837 pub mod R {}
1838 pub mod W {}
1839 pub mod RW {}
1840 }
1841 #[doc = "Enable the PLL providing ENET 25 MHz reference clock"]
1842 pub mod ENET_25M_REF_EN {
1843 pub const offset: u32 = 21;
1844 pub const mask: u32 = 0x01 << offset;
1845 pub mod R {}
1846 pub mod W {}
1847 pub mod RW {}
1848 }
1849 #[doc = "1 - PLL is currently locked; 0 - PLL is not currently locked."]
1850 pub mod LOCK {
1851 pub const offset: u32 = 31;
1852 pub const mask: u32 = 0x01 << offset;
1853 pub mod R {}
1854 pub mod W {}
1855 pub mod RW {}
1856 }
1857}
1858#[doc = "Analog ENET PLL Control Register"]
1859pub mod PLL_ENET_SET {
1860 #[doc = "Controls the frequency of the ethernet reference clock"]
1861 pub mod DIV_SELECT {
1862 pub const offset: u32 = 0;
1863 pub const mask: u32 = 0x03 << offset;
1864 pub mod R {}
1865 pub mod W {}
1866 pub mod RW {}
1867 }
1868 #[doc = "Controls the frequency of the ENET2 reference clock."]
1869 pub mod ENET2_DIV_SELECT {
1870 pub const offset: u32 = 2;
1871 pub const mask: u32 = 0x03 << offset;
1872 pub mod R {}
1873 pub mod W {}
1874 pub mod RW {
1875 #[doc = "25MHz"]
1876 pub const ENET2_DIV_SELECT_0: u32 = 0;
1877 #[doc = "50MHz"]
1878 pub const ENET2_DIV_SELECT_1: u32 = 0x01;
1879 #[doc = "100MHz (not 50% duty cycle)"]
1880 pub const ENET2_DIV_SELECT_2: u32 = 0x02;
1881 #[doc = "125MHz"]
1882 pub const ENET2_DIV_SELECT_3: u32 = 0x03;
1883 }
1884 }
1885 #[doc = "Powers down the PLL."]
1886 pub mod POWERDOWN {
1887 pub const offset: u32 = 12;
1888 pub const mask: u32 = 0x01 << offset;
1889 pub mod R {}
1890 pub mod W {}
1891 pub mod RW {}
1892 }
1893 #[doc = "Enable the PLL providing the ENET reference clock."]
1894 pub mod ENABLE {
1895 pub const offset: u32 = 13;
1896 pub const mask: u32 = 0x01 << offset;
1897 pub mod R {}
1898 pub mod W {}
1899 pub mod RW {}
1900 }
1901 #[doc = "Determines the bypass source."]
1902 pub mod BYPASS_CLK_SRC {
1903 pub const offset: u32 = 14;
1904 pub const mask: u32 = 0x03 << offset;
1905 pub mod R {}
1906 pub mod W {}
1907 pub mod RW {
1908 #[doc = "Select the 24MHz oscillator as source."]
1909 pub const REF_CLK_24M: u32 = 0;
1910 #[doc = "Select the CLK1_N / CLK1_P as source."]
1911 pub const CLK1: u32 = 0x01;
1912 }
1913 }
1914 #[doc = "Bypass the PLL."]
1915 pub mod BYPASS {
1916 pub const offset: u32 = 16;
1917 pub const mask: u32 = 0x01 << offset;
1918 pub mod R {}
1919 pub mod W {}
1920 pub mod RW {}
1921 }
1922 #[doc = "Enable the PLL providing the ENET2 reference clock"]
1923 pub mod ENET2_REF_EN {
1924 pub const offset: u32 = 20;
1925 pub const mask: u32 = 0x01 << offset;
1926 pub mod R {}
1927 pub mod W {}
1928 pub mod RW {}
1929 }
1930 #[doc = "Enable the PLL providing ENET 25 MHz reference clock"]
1931 pub mod ENET_25M_REF_EN {
1932 pub const offset: u32 = 21;
1933 pub const mask: u32 = 0x01 << offset;
1934 pub mod R {}
1935 pub mod W {}
1936 pub mod RW {}
1937 }
1938 #[doc = "1 - PLL is currently locked; 0 - PLL is not currently locked."]
1939 pub mod LOCK {
1940 pub const offset: u32 = 31;
1941 pub const mask: u32 = 0x01 << offset;
1942 pub mod R {}
1943 pub mod W {}
1944 pub mod RW {}
1945 }
1946}
1947#[doc = "Analog ENET PLL Control Register"]
1948pub mod PLL_ENET_CLR {
1949 #[doc = "Controls the frequency of the ethernet reference clock"]
1950 pub mod DIV_SELECT {
1951 pub const offset: u32 = 0;
1952 pub const mask: u32 = 0x03 << offset;
1953 pub mod R {}
1954 pub mod W {}
1955 pub mod RW {}
1956 }
1957 #[doc = "Controls the frequency of the ENET2 reference clock."]
1958 pub mod ENET2_DIV_SELECT {
1959 pub const offset: u32 = 2;
1960 pub const mask: u32 = 0x03 << offset;
1961 pub mod R {}
1962 pub mod W {}
1963 pub mod RW {
1964 #[doc = "25MHz"]
1965 pub const ENET2_DIV_SELECT_0: u32 = 0;
1966 #[doc = "50MHz"]
1967 pub const ENET2_DIV_SELECT_1: u32 = 0x01;
1968 #[doc = "100MHz (not 50% duty cycle)"]
1969 pub const ENET2_DIV_SELECT_2: u32 = 0x02;
1970 #[doc = "125MHz"]
1971 pub const ENET2_DIV_SELECT_3: u32 = 0x03;
1972 }
1973 }
1974 #[doc = "Powers down the PLL."]
1975 pub mod POWERDOWN {
1976 pub const offset: u32 = 12;
1977 pub const mask: u32 = 0x01 << offset;
1978 pub mod R {}
1979 pub mod W {}
1980 pub mod RW {}
1981 }
1982 #[doc = "Enable the PLL providing the ENET reference clock."]
1983 pub mod ENABLE {
1984 pub const offset: u32 = 13;
1985 pub const mask: u32 = 0x01 << offset;
1986 pub mod R {}
1987 pub mod W {}
1988 pub mod RW {}
1989 }
1990 #[doc = "Determines the bypass source."]
1991 pub mod BYPASS_CLK_SRC {
1992 pub const offset: u32 = 14;
1993 pub const mask: u32 = 0x03 << offset;
1994 pub mod R {}
1995 pub mod W {}
1996 pub mod RW {
1997 #[doc = "Select the 24MHz oscillator as source."]
1998 pub const REF_CLK_24M: u32 = 0;
1999 #[doc = "Select the CLK1_N / CLK1_P as source."]
2000 pub const CLK1: u32 = 0x01;
2001 }
2002 }
2003 #[doc = "Bypass the PLL."]
2004 pub mod BYPASS {
2005 pub const offset: u32 = 16;
2006 pub const mask: u32 = 0x01 << offset;
2007 pub mod R {}
2008 pub mod W {}
2009 pub mod RW {}
2010 }
2011 #[doc = "Enable the PLL providing the ENET2 reference clock"]
2012 pub mod ENET2_REF_EN {
2013 pub const offset: u32 = 20;
2014 pub const mask: u32 = 0x01 << offset;
2015 pub mod R {}
2016 pub mod W {}
2017 pub mod RW {}
2018 }
2019 #[doc = "Enable the PLL providing ENET 25 MHz reference clock"]
2020 pub mod ENET_25M_REF_EN {
2021 pub const offset: u32 = 21;
2022 pub const mask: u32 = 0x01 << offset;
2023 pub mod R {}
2024 pub mod W {}
2025 pub mod RW {}
2026 }
2027 #[doc = "1 - PLL is currently locked; 0 - PLL is not currently locked."]
2028 pub mod LOCK {
2029 pub const offset: u32 = 31;
2030 pub const mask: u32 = 0x01 << offset;
2031 pub mod R {}
2032 pub mod W {}
2033 pub mod RW {}
2034 }
2035}
2036#[doc = "Analog ENET PLL Control Register"]
2037pub mod PLL_ENET_TOG {
2038 #[doc = "Controls the frequency of the ethernet reference clock"]
2039 pub mod DIV_SELECT {
2040 pub const offset: u32 = 0;
2041 pub const mask: u32 = 0x03 << offset;
2042 pub mod R {}
2043 pub mod W {}
2044 pub mod RW {}
2045 }
2046 #[doc = "Controls the frequency of the ENET2 reference clock."]
2047 pub mod ENET2_DIV_SELECT {
2048 pub const offset: u32 = 2;
2049 pub const mask: u32 = 0x03 << offset;
2050 pub mod R {}
2051 pub mod W {}
2052 pub mod RW {
2053 #[doc = "25MHz"]
2054 pub const ENET2_DIV_SELECT_0: u32 = 0;
2055 #[doc = "50MHz"]
2056 pub const ENET2_DIV_SELECT_1: u32 = 0x01;
2057 #[doc = "100MHz (not 50% duty cycle)"]
2058 pub const ENET2_DIV_SELECT_2: u32 = 0x02;
2059 #[doc = "125MHz"]
2060 pub const ENET2_DIV_SELECT_3: u32 = 0x03;
2061 }
2062 }
2063 #[doc = "Powers down the PLL."]
2064 pub mod POWERDOWN {
2065 pub const offset: u32 = 12;
2066 pub const mask: u32 = 0x01 << offset;
2067 pub mod R {}
2068 pub mod W {}
2069 pub mod RW {}
2070 }
2071 #[doc = "Enable the PLL providing the ENET reference clock."]
2072 pub mod ENABLE {
2073 pub const offset: u32 = 13;
2074 pub const mask: u32 = 0x01 << offset;
2075 pub mod R {}
2076 pub mod W {}
2077 pub mod RW {}
2078 }
2079 #[doc = "Determines the bypass source."]
2080 pub mod BYPASS_CLK_SRC {
2081 pub const offset: u32 = 14;
2082 pub const mask: u32 = 0x03 << offset;
2083 pub mod R {}
2084 pub mod W {}
2085 pub mod RW {
2086 #[doc = "Select the 24MHz oscillator as source."]
2087 pub const REF_CLK_24M: u32 = 0;
2088 #[doc = "Select the CLK1_N / CLK1_P as source."]
2089 pub const CLK1: u32 = 0x01;
2090 }
2091 }
2092 #[doc = "Bypass the PLL."]
2093 pub mod BYPASS {
2094 pub const offset: u32 = 16;
2095 pub const mask: u32 = 0x01 << offset;
2096 pub mod R {}
2097 pub mod W {}
2098 pub mod RW {}
2099 }
2100 #[doc = "Enable the PLL providing the ENET2 reference clock"]
2101 pub mod ENET2_REF_EN {
2102 pub const offset: u32 = 20;
2103 pub const mask: u32 = 0x01 << offset;
2104 pub mod R {}
2105 pub mod W {}
2106 pub mod RW {}
2107 }
2108 #[doc = "Enable the PLL providing ENET 25 MHz reference clock"]
2109 pub mod ENET_25M_REF_EN {
2110 pub const offset: u32 = 21;
2111 pub const mask: u32 = 0x01 << offset;
2112 pub mod R {}
2113 pub mod W {}
2114 pub mod RW {}
2115 }
2116 #[doc = "1 - PLL is currently locked; 0 - PLL is not currently locked."]
2117 pub mod LOCK {
2118 pub const offset: u32 = 31;
2119 pub const mask: u32 = 0x01 << offset;
2120 pub mod R {}
2121 pub mod W {}
2122 pub mod RW {}
2123 }
2124}
2125#[doc = "480MHz Clock (PLL3) Phase Fractional Divider Control Register"]
2126pub mod PFD_480 {
2127 #[doc = "This field controls the fractional divide value"]
2128 pub mod PFD0_FRAC {
2129 pub const offset: u32 = 0;
2130 pub const mask: u32 = 0x3f << offset;
2131 pub mod R {}
2132 pub mod W {}
2133 pub mod RW {}
2134 }
2135 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2136 pub mod PFD0_STABLE {
2137 pub const offset: u32 = 6;
2138 pub const mask: u32 = 0x01 << offset;
2139 pub mod R {}
2140 pub mod W {}
2141 pub mod RW {}
2142 }
2143 #[doc = "If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)"]
2144 pub mod PFD0_CLKGATE {
2145 pub const offset: u32 = 7;
2146 pub const mask: u32 = 0x01 << offset;
2147 pub mod R {}
2148 pub mod W {}
2149 pub mod RW {}
2150 }
2151 #[doc = "This field controls the fractional divide value"]
2152 pub mod PFD1_FRAC {
2153 pub const offset: u32 = 8;
2154 pub const mask: u32 = 0x3f << offset;
2155 pub mod R {}
2156 pub mod W {}
2157 pub mod RW {}
2158 }
2159 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2160 pub mod PFD1_STABLE {
2161 pub const offset: u32 = 14;
2162 pub const mask: u32 = 0x01 << offset;
2163 pub mod R {}
2164 pub mod W {}
2165 pub mod RW {}
2166 }
2167 #[doc = "IO Clock Gate"]
2168 pub mod PFD1_CLKGATE {
2169 pub const offset: u32 = 15;
2170 pub const mask: u32 = 0x01 << offset;
2171 pub mod R {}
2172 pub mod W {}
2173 pub mod RW {}
2174 }
2175 #[doc = "This field controls the fractional divide value"]
2176 pub mod PFD2_FRAC {
2177 pub const offset: u32 = 16;
2178 pub const mask: u32 = 0x3f << offset;
2179 pub mod R {}
2180 pub mod W {}
2181 pub mod RW {}
2182 }
2183 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2184 pub mod PFD2_STABLE {
2185 pub const offset: u32 = 22;
2186 pub const mask: u32 = 0x01 << offset;
2187 pub mod R {}
2188 pub mod W {}
2189 pub mod RW {}
2190 }
2191 #[doc = "IO Clock Gate"]
2192 pub mod PFD2_CLKGATE {
2193 pub const offset: u32 = 23;
2194 pub const mask: u32 = 0x01 << offset;
2195 pub mod R {}
2196 pub mod W {}
2197 pub mod RW {}
2198 }
2199 #[doc = "This field controls the fractional divide value"]
2200 pub mod PFD3_FRAC {
2201 pub const offset: u32 = 24;
2202 pub const mask: u32 = 0x3f << offset;
2203 pub mod R {}
2204 pub mod W {}
2205 pub mod RW {}
2206 }
2207 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2208 pub mod PFD3_STABLE {
2209 pub const offset: u32 = 30;
2210 pub const mask: u32 = 0x01 << offset;
2211 pub mod R {}
2212 pub mod W {}
2213 pub mod RW {}
2214 }
2215 #[doc = "IO Clock Gate"]
2216 pub mod PFD3_CLKGATE {
2217 pub const offset: u32 = 31;
2218 pub const mask: u32 = 0x01 << offset;
2219 pub mod R {}
2220 pub mod W {}
2221 pub mod RW {}
2222 }
2223}
2224#[doc = "480MHz Clock (PLL3) Phase Fractional Divider Control Register"]
2225pub mod PFD_480_SET {
2226 #[doc = "This field controls the fractional divide value"]
2227 pub mod PFD0_FRAC {
2228 pub const offset: u32 = 0;
2229 pub const mask: u32 = 0x3f << offset;
2230 pub mod R {}
2231 pub mod W {}
2232 pub mod RW {}
2233 }
2234 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2235 pub mod PFD0_STABLE {
2236 pub const offset: u32 = 6;
2237 pub const mask: u32 = 0x01 << offset;
2238 pub mod R {}
2239 pub mod W {}
2240 pub mod RW {}
2241 }
2242 #[doc = "If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)"]
2243 pub mod PFD0_CLKGATE {
2244 pub const offset: u32 = 7;
2245 pub const mask: u32 = 0x01 << offset;
2246 pub mod R {}
2247 pub mod W {}
2248 pub mod RW {}
2249 }
2250 #[doc = "This field controls the fractional divide value"]
2251 pub mod PFD1_FRAC {
2252 pub const offset: u32 = 8;
2253 pub const mask: u32 = 0x3f << offset;
2254 pub mod R {}
2255 pub mod W {}
2256 pub mod RW {}
2257 }
2258 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2259 pub mod PFD1_STABLE {
2260 pub const offset: u32 = 14;
2261 pub const mask: u32 = 0x01 << offset;
2262 pub mod R {}
2263 pub mod W {}
2264 pub mod RW {}
2265 }
2266 #[doc = "IO Clock Gate"]
2267 pub mod PFD1_CLKGATE {
2268 pub const offset: u32 = 15;
2269 pub const mask: u32 = 0x01 << offset;
2270 pub mod R {}
2271 pub mod W {}
2272 pub mod RW {}
2273 }
2274 #[doc = "This field controls the fractional divide value"]
2275 pub mod PFD2_FRAC {
2276 pub const offset: u32 = 16;
2277 pub const mask: u32 = 0x3f << offset;
2278 pub mod R {}
2279 pub mod W {}
2280 pub mod RW {}
2281 }
2282 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2283 pub mod PFD2_STABLE {
2284 pub const offset: u32 = 22;
2285 pub const mask: u32 = 0x01 << offset;
2286 pub mod R {}
2287 pub mod W {}
2288 pub mod RW {}
2289 }
2290 #[doc = "IO Clock Gate"]
2291 pub mod PFD2_CLKGATE {
2292 pub const offset: u32 = 23;
2293 pub const mask: u32 = 0x01 << offset;
2294 pub mod R {}
2295 pub mod W {}
2296 pub mod RW {}
2297 }
2298 #[doc = "This field controls the fractional divide value"]
2299 pub mod PFD3_FRAC {
2300 pub const offset: u32 = 24;
2301 pub const mask: u32 = 0x3f << offset;
2302 pub mod R {}
2303 pub mod W {}
2304 pub mod RW {}
2305 }
2306 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2307 pub mod PFD3_STABLE {
2308 pub const offset: u32 = 30;
2309 pub const mask: u32 = 0x01 << offset;
2310 pub mod R {}
2311 pub mod W {}
2312 pub mod RW {}
2313 }
2314 #[doc = "IO Clock Gate"]
2315 pub mod PFD3_CLKGATE {
2316 pub const offset: u32 = 31;
2317 pub const mask: u32 = 0x01 << offset;
2318 pub mod R {}
2319 pub mod W {}
2320 pub mod RW {}
2321 }
2322}
2323#[doc = "480MHz Clock (PLL3) Phase Fractional Divider Control Register"]
2324pub mod PFD_480_CLR {
2325 #[doc = "This field controls the fractional divide value"]
2326 pub mod PFD0_FRAC {
2327 pub const offset: u32 = 0;
2328 pub const mask: u32 = 0x3f << offset;
2329 pub mod R {}
2330 pub mod W {}
2331 pub mod RW {}
2332 }
2333 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2334 pub mod PFD0_STABLE {
2335 pub const offset: u32 = 6;
2336 pub const mask: u32 = 0x01 << offset;
2337 pub mod R {}
2338 pub mod W {}
2339 pub mod RW {}
2340 }
2341 #[doc = "If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)"]
2342 pub mod PFD0_CLKGATE {
2343 pub const offset: u32 = 7;
2344 pub const mask: u32 = 0x01 << offset;
2345 pub mod R {}
2346 pub mod W {}
2347 pub mod RW {}
2348 }
2349 #[doc = "This field controls the fractional divide value"]
2350 pub mod PFD1_FRAC {
2351 pub const offset: u32 = 8;
2352 pub const mask: u32 = 0x3f << offset;
2353 pub mod R {}
2354 pub mod W {}
2355 pub mod RW {}
2356 }
2357 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2358 pub mod PFD1_STABLE {
2359 pub const offset: u32 = 14;
2360 pub const mask: u32 = 0x01 << offset;
2361 pub mod R {}
2362 pub mod W {}
2363 pub mod RW {}
2364 }
2365 #[doc = "IO Clock Gate"]
2366 pub mod PFD1_CLKGATE {
2367 pub const offset: u32 = 15;
2368 pub const mask: u32 = 0x01 << offset;
2369 pub mod R {}
2370 pub mod W {}
2371 pub mod RW {}
2372 }
2373 #[doc = "This field controls the fractional divide value"]
2374 pub mod PFD2_FRAC {
2375 pub const offset: u32 = 16;
2376 pub const mask: u32 = 0x3f << offset;
2377 pub mod R {}
2378 pub mod W {}
2379 pub mod RW {}
2380 }
2381 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2382 pub mod PFD2_STABLE {
2383 pub const offset: u32 = 22;
2384 pub const mask: u32 = 0x01 << offset;
2385 pub mod R {}
2386 pub mod W {}
2387 pub mod RW {}
2388 }
2389 #[doc = "IO Clock Gate"]
2390 pub mod PFD2_CLKGATE {
2391 pub const offset: u32 = 23;
2392 pub const mask: u32 = 0x01 << offset;
2393 pub mod R {}
2394 pub mod W {}
2395 pub mod RW {}
2396 }
2397 #[doc = "This field controls the fractional divide value"]
2398 pub mod PFD3_FRAC {
2399 pub const offset: u32 = 24;
2400 pub const mask: u32 = 0x3f << offset;
2401 pub mod R {}
2402 pub mod W {}
2403 pub mod RW {}
2404 }
2405 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2406 pub mod PFD3_STABLE {
2407 pub const offset: u32 = 30;
2408 pub const mask: u32 = 0x01 << offset;
2409 pub mod R {}
2410 pub mod W {}
2411 pub mod RW {}
2412 }
2413 #[doc = "IO Clock Gate"]
2414 pub mod PFD3_CLKGATE {
2415 pub const offset: u32 = 31;
2416 pub const mask: u32 = 0x01 << offset;
2417 pub mod R {}
2418 pub mod W {}
2419 pub mod RW {}
2420 }
2421}
2422#[doc = "480MHz Clock (PLL3) Phase Fractional Divider Control Register"]
2423pub mod PFD_480_TOG {
2424 #[doc = "This field controls the fractional divide value"]
2425 pub mod PFD0_FRAC {
2426 pub const offset: u32 = 0;
2427 pub const mask: u32 = 0x3f << offset;
2428 pub mod R {}
2429 pub mod W {}
2430 pub mod RW {}
2431 }
2432 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2433 pub mod PFD0_STABLE {
2434 pub const offset: u32 = 6;
2435 pub const mask: u32 = 0x01 << offset;
2436 pub mod R {}
2437 pub mod W {}
2438 pub mod RW {}
2439 }
2440 #[doc = "If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)"]
2441 pub mod PFD0_CLKGATE {
2442 pub const offset: u32 = 7;
2443 pub const mask: u32 = 0x01 << offset;
2444 pub mod R {}
2445 pub mod W {}
2446 pub mod RW {}
2447 }
2448 #[doc = "This field controls the fractional divide value"]
2449 pub mod PFD1_FRAC {
2450 pub const offset: u32 = 8;
2451 pub const mask: u32 = 0x3f << offset;
2452 pub mod R {}
2453 pub mod W {}
2454 pub mod RW {}
2455 }
2456 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2457 pub mod PFD1_STABLE {
2458 pub const offset: u32 = 14;
2459 pub const mask: u32 = 0x01 << offset;
2460 pub mod R {}
2461 pub mod W {}
2462 pub mod RW {}
2463 }
2464 #[doc = "IO Clock Gate"]
2465 pub mod PFD1_CLKGATE {
2466 pub const offset: u32 = 15;
2467 pub const mask: u32 = 0x01 << offset;
2468 pub mod R {}
2469 pub mod W {}
2470 pub mod RW {}
2471 }
2472 #[doc = "This field controls the fractional divide value"]
2473 pub mod PFD2_FRAC {
2474 pub const offset: u32 = 16;
2475 pub const mask: u32 = 0x3f << offset;
2476 pub mod R {}
2477 pub mod W {}
2478 pub mod RW {}
2479 }
2480 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2481 pub mod PFD2_STABLE {
2482 pub const offset: u32 = 22;
2483 pub const mask: u32 = 0x01 << offset;
2484 pub mod R {}
2485 pub mod W {}
2486 pub mod RW {}
2487 }
2488 #[doc = "IO Clock Gate"]
2489 pub mod PFD2_CLKGATE {
2490 pub const offset: u32 = 23;
2491 pub const mask: u32 = 0x01 << offset;
2492 pub mod R {}
2493 pub mod W {}
2494 pub mod RW {}
2495 }
2496 #[doc = "This field controls the fractional divide value"]
2497 pub mod PFD3_FRAC {
2498 pub const offset: u32 = 24;
2499 pub const mask: u32 = 0x3f << offset;
2500 pub mod R {}
2501 pub mod W {}
2502 pub mod RW {}
2503 }
2504 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2505 pub mod PFD3_STABLE {
2506 pub const offset: u32 = 30;
2507 pub const mask: u32 = 0x01 << offset;
2508 pub mod R {}
2509 pub mod W {}
2510 pub mod RW {}
2511 }
2512 #[doc = "IO Clock Gate"]
2513 pub mod PFD3_CLKGATE {
2514 pub const offset: u32 = 31;
2515 pub const mask: u32 = 0x01 << offset;
2516 pub mod R {}
2517 pub mod W {}
2518 pub mod RW {}
2519 }
2520}
2521#[doc = "528MHz Clock (PLL2) Phase Fractional Divider Control Register"]
2522pub mod PFD_528 {
2523 #[doc = "This field controls the fractional divide value"]
2524 pub mod PFD0_FRAC {
2525 pub const offset: u32 = 0;
2526 pub const mask: u32 = 0x3f << offset;
2527 pub mod R {}
2528 pub mod W {}
2529 pub mod RW {}
2530 }
2531 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2532 pub mod PFD0_STABLE {
2533 pub const offset: u32 = 6;
2534 pub const mask: u32 = 0x01 << offset;
2535 pub mod R {}
2536 pub mod W {}
2537 pub mod RW {}
2538 }
2539 #[doc = "If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)"]
2540 pub mod PFD0_CLKGATE {
2541 pub const offset: u32 = 7;
2542 pub const mask: u32 = 0x01 << offset;
2543 pub mod R {}
2544 pub mod W {}
2545 pub mod RW {}
2546 }
2547 #[doc = "This field controls the fractional divide value"]
2548 pub mod PFD1_FRAC {
2549 pub const offset: u32 = 8;
2550 pub const mask: u32 = 0x3f << offset;
2551 pub mod R {}
2552 pub mod W {}
2553 pub mod RW {}
2554 }
2555 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2556 pub mod PFD1_STABLE {
2557 pub const offset: u32 = 14;
2558 pub const mask: u32 = 0x01 << offset;
2559 pub mod R {}
2560 pub mod W {}
2561 pub mod RW {}
2562 }
2563 #[doc = "IO Clock Gate"]
2564 pub mod PFD1_CLKGATE {
2565 pub const offset: u32 = 15;
2566 pub const mask: u32 = 0x01 << offset;
2567 pub mod R {}
2568 pub mod W {}
2569 pub mod RW {}
2570 }
2571 #[doc = "This field controls the fractional divide value"]
2572 pub mod PFD2_FRAC {
2573 pub const offset: u32 = 16;
2574 pub const mask: u32 = 0x3f << offset;
2575 pub mod R {}
2576 pub mod W {}
2577 pub mod RW {}
2578 }
2579 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2580 pub mod PFD2_STABLE {
2581 pub const offset: u32 = 22;
2582 pub const mask: u32 = 0x01 << offset;
2583 pub mod R {}
2584 pub mod W {}
2585 pub mod RW {}
2586 }
2587 #[doc = "IO Clock Gate"]
2588 pub mod PFD2_CLKGATE {
2589 pub const offset: u32 = 23;
2590 pub const mask: u32 = 0x01 << offset;
2591 pub mod R {}
2592 pub mod W {}
2593 pub mod RW {}
2594 }
2595 #[doc = "This field controls the fractional divide value"]
2596 pub mod PFD3_FRAC {
2597 pub const offset: u32 = 24;
2598 pub const mask: u32 = 0x3f << offset;
2599 pub mod R {}
2600 pub mod W {}
2601 pub mod RW {}
2602 }
2603 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2604 pub mod PFD3_STABLE {
2605 pub const offset: u32 = 30;
2606 pub const mask: u32 = 0x01 << offset;
2607 pub mod R {}
2608 pub mod W {}
2609 pub mod RW {}
2610 }
2611 #[doc = "IO Clock Gate"]
2612 pub mod PFD3_CLKGATE {
2613 pub const offset: u32 = 31;
2614 pub const mask: u32 = 0x01 << offset;
2615 pub mod R {}
2616 pub mod W {}
2617 pub mod RW {}
2618 }
2619}
2620#[doc = "528MHz Clock (PLL2) Phase Fractional Divider Control Register"]
2621pub mod PFD_528_SET {
2622 #[doc = "This field controls the fractional divide value"]
2623 pub mod PFD0_FRAC {
2624 pub const offset: u32 = 0;
2625 pub const mask: u32 = 0x3f << offset;
2626 pub mod R {}
2627 pub mod W {}
2628 pub mod RW {}
2629 }
2630 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2631 pub mod PFD0_STABLE {
2632 pub const offset: u32 = 6;
2633 pub const mask: u32 = 0x01 << offset;
2634 pub mod R {}
2635 pub mod W {}
2636 pub mod RW {}
2637 }
2638 #[doc = "If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)"]
2639 pub mod PFD0_CLKGATE {
2640 pub const offset: u32 = 7;
2641 pub const mask: u32 = 0x01 << offset;
2642 pub mod R {}
2643 pub mod W {}
2644 pub mod RW {}
2645 }
2646 #[doc = "This field controls the fractional divide value"]
2647 pub mod PFD1_FRAC {
2648 pub const offset: u32 = 8;
2649 pub const mask: u32 = 0x3f << offset;
2650 pub mod R {}
2651 pub mod W {}
2652 pub mod RW {}
2653 }
2654 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2655 pub mod PFD1_STABLE {
2656 pub const offset: u32 = 14;
2657 pub const mask: u32 = 0x01 << offset;
2658 pub mod R {}
2659 pub mod W {}
2660 pub mod RW {}
2661 }
2662 #[doc = "IO Clock Gate"]
2663 pub mod PFD1_CLKGATE {
2664 pub const offset: u32 = 15;
2665 pub const mask: u32 = 0x01 << offset;
2666 pub mod R {}
2667 pub mod W {}
2668 pub mod RW {}
2669 }
2670 #[doc = "This field controls the fractional divide value"]
2671 pub mod PFD2_FRAC {
2672 pub const offset: u32 = 16;
2673 pub const mask: u32 = 0x3f << offset;
2674 pub mod R {}
2675 pub mod W {}
2676 pub mod RW {}
2677 }
2678 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2679 pub mod PFD2_STABLE {
2680 pub const offset: u32 = 22;
2681 pub const mask: u32 = 0x01 << offset;
2682 pub mod R {}
2683 pub mod W {}
2684 pub mod RW {}
2685 }
2686 #[doc = "IO Clock Gate"]
2687 pub mod PFD2_CLKGATE {
2688 pub const offset: u32 = 23;
2689 pub const mask: u32 = 0x01 << offset;
2690 pub mod R {}
2691 pub mod W {}
2692 pub mod RW {}
2693 }
2694 #[doc = "This field controls the fractional divide value"]
2695 pub mod PFD3_FRAC {
2696 pub const offset: u32 = 24;
2697 pub const mask: u32 = 0x3f << offset;
2698 pub mod R {}
2699 pub mod W {}
2700 pub mod RW {}
2701 }
2702 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2703 pub mod PFD3_STABLE {
2704 pub const offset: u32 = 30;
2705 pub const mask: u32 = 0x01 << offset;
2706 pub mod R {}
2707 pub mod W {}
2708 pub mod RW {}
2709 }
2710 #[doc = "IO Clock Gate"]
2711 pub mod PFD3_CLKGATE {
2712 pub const offset: u32 = 31;
2713 pub const mask: u32 = 0x01 << offset;
2714 pub mod R {}
2715 pub mod W {}
2716 pub mod RW {}
2717 }
2718}
2719#[doc = "528MHz Clock (PLL2) Phase Fractional Divider Control Register"]
2720pub mod PFD_528_CLR {
2721 #[doc = "This field controls the fractional divide value"]
2722 pub mod PFD0_FRAC {
2723 pub const offset: u32 = 0;
2724 pub const mask: u32 = 0x3f << offset;
2725 pub mod R {}
2726 pub mod W {}
2727 pub mod RW {}
2728 }
2729 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2730 pub mod PFD0_STABLE {
2731 pub const offset: u32 = 6;
2732 pub const mask: u32 = 0x01 << offset;
2733 pub mod R {}
2734 pub mod W {}
2735 pub mod RW {}
2736 }
2737 #[doc = "If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)"]
2738 pub mod PFD0_CLKGATE {
2739 pub const offset: u32 = 7;
2740 pub const mask: u32 = 0x01 << offset;
2741 pub mod R {}
2742 pub mod W {}
2743 pub mod RW {}
2744 }
2745 #[doc = "This field controls the fractional divide value"]
2746 pub mod PFD1_FRAC {
2747 pub const offset: u32 = 8;
2748 pub const mask: u32 = 0x3f << offset;
2749 pub mod R {}
2750 pub mod W {}
2751 pub mod RW {}
2752 }
2753 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2754 pub mod PFD1_STABLE {
2755 pub const offset: u32 = 14;
2756 pub const mask: u32 = 0x01 << offset;
2757 pub mod R {}
2758 pub mod W {}
2759 pub mod RW {}
2760 }
2761 #[doc = "IO Clock Gate"]
2762 pub mod PFD1_CLKGATE {
2763 pub const offset: u32 = 15;
2764 pub const mask: u32 = 0x01 << offset;
2765 pub mod R {}
2766 pub mod W {}
2767 pub mod RW {}
2768 }
2769 #[doc = "This field controls the fractional divide value"]
2770 pub mod PFD2_FRAC {
2771 pub const offset: u32 = 16;
2772 pub const mask: u32 = 0x3f << offset;
2773 pub mod R {}
2774 pub mod W {}
2775 pub mod RW {}
2776 }
2777 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2778 pub mod PFD2_STABLE {
2779 pub const offset: u32 = 22;
2780 pub const mask: u32 = 0x01 << offset;
2781 pub mod R {}
2782 pub mod W {}
2783 pub mod RW {}
2784 }
2785 #[doc = "IO Clock Gate"]
2786 pub mod PFD2_CLKGATE {
2787 pub const offset: u32 = 23;
2788 pub const mask: u32 = 0x01 << offset;
2789 pub mod R {}
2790 pub mod W {}
2791 pub mod RW {}
2792 }
2793 #[doc = "This field controls the fractional divide value"]
2794 pub mod PFD3_FRAC {
2795 pub const offset: u32 = 24;
2796 pub const mask: u32 = 0x3f << offset;
2797 pub mod R {}
2798 pub mod W {}
2799 pub mod RW {}
2800 }
2801 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2802 pub mod PFD3_STABLE {
2803 pub const offset: u32 = 30;
2804 pub const mask: u32 = 0x01 << offset;
2805 pub mod R {}
2806 pub mod W {}
2807 pub mod RW {}
2808 }
2809 #[doc = "IO Clock Gate"]
2810 pub mod PFD3_CLKGATE {
2811 pub const offset: u32 = 31;
2812 pub const mask: u32 = 0x01 << offset;
2813 pub mod R {}
2814 pub mod W {}
2815 pub mod RW {}
2816 }
2817}
2818#[doc = "528MHz Clock (PLL2) Phase Fractional Divider Control Register"]
2819pub mod PFD_528_TOG {
2820 #[doc = "This field controls the fractional divide value"]
2821 pub mod PFD0_FRAC {
2822 pub const offset: u32 = 0;
2823 pub const mask: u32 = 0x3f << offset;
2824 pub mod R {}
2825 pub mod W {}
2826 pub mod RW {}
2827 }
2828 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2829 pub mod PFD0_STABLE {
2830 pub const offset: u32 = 6;
2831 pub const mask: u32 = 0x01 << offset;
2832 pub mod R {}
2833 pub mod W {}
2834 pub mod RW {}
2835 }
2836 #[doc = "If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)"]
2837 pub mod PFD0_CLKGATE {
2838 pub const offset: u32 = 7;
2839 pub const mask: u32 = 0x01 << offset;
2840 pub mod R {}
2841 pub mod W {}
2842 pub mod RW {}
2843 }
2844 #[doc = "This field controls the fractional divide value"]
2845 pub mod PFD1_FRAC {
2846 pub const offset: u32 = 8;
2847 pub const mask: u32 = 0x3f << offset;
2848 pub mod R {}
2849 pub mod W {}
2850 pub mod RW {}
2851 }
2852 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2853 pub mod PFD1_STABLE {
2854 pub const offset: u32 = 14;
2855 pub const mask: u32 = 0x01 << offset;
2856 pub mod R {}
2857 pub mod W {}
2858 pub mod RW {}
2859 }
2860 #[doc = "IO Clock Gate"]
2861 pub mod PFD1_CLKGATE {
2862 pub const offset: u32 = 15;
2863 pub const mask: u32 = 0x01 << offset;
2864 pub mod R {}
2865 pub mod W {}
2866 pub mod RW {}
2867 }
2868 #[doc = "This field controls the fractional divide value"]
2869 pub mod PFD2_FRAC {
2870 pub const offset: u32 = 16;
2871 pub const mask: u32 = 0x3f << offset;
2872 pub mod R {}
2873 pub mod W {}
2874 pub mod RW {}
2875 }
2876 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2877 pub mod PFD2_STABLE {
2878 pub const offset: u32 = 22;
2879 pub const mask: u32 = 0x01 << offset;
2880 pub mod R {}
2881 pub mod W {}
2882 pub mod RW {}
2883 }
2884 #[doc = "IO Clock Gate"]
2885 pub mod PFD2_CLKGATE {
2886 pub const offset: u32 = 23;
2887 pub const mask: u32 = 0x01 << offset;
2888 pub mod R {}
2889 pub mod W {}
2890 pub mod RW {}
2891 }
2892 #[doc = "This field controls the fractional divide value"]
2893 pub mod PFD3_FRAC {
2894 pub const offset: u32 = 24;
2895 pub const mask: u32 = 0x3f << offset;
2896 pub mod R {}
2897 pub mod W {}
2898 pub mod RW {}
2899 }
2900 #[doc = "This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code"]
2901 pub mod PFD3_STABLE {
2902 pub const offset: u32 = 30;
2903 pub const mask: u32 = 0x01 << offset;
2904 pub mod R {}
2905 pub mod W {}
2906 pub mod RW {}
2907 }
2908 #[doc = "IO Clock Gate"]
2909 pub mod PFD3_CLKGATE {
2910 pub const offset: u32 = 31;
2911 pub const mask: u32 = 0x01 << offset;
2912 pub mod R {}
2913 pub mod W {}
2914 pub mod RW {}
2915 }
2916}
2917#[doc = "Miscellaneous Register 0"]
2918pub mod MISC0 {
2919 #[doc = "Control bit to power-down the analog bandgap reference circuitry"]
2920 pub mod REFTOP_PWD {
2921 pub const offset: u32 = 0;
2922 pub const mask: u32 = 0x01 << offset;
2923 pub mod R {}
2924 pub mod W {}
2925 pub mod RW {}
2926 }
2927 #[doc = "Control bit to disable the self-bias circuit in the analog bandgap"]
2928 pub mod REFTOP_SELFBIASOFF {
2929 pub const offset: u32 = 3;
2930 pub const mask: u32 = 0x01 << offset;
2931 pub mod R {}
2932 pub mod W {}
2933 pub mod RW {
2934 #[doc = "Uses coarse bias currents for startup"]
2935 pub const REFTOP_SELFBIASOFF_0: u32 = 0;
2936 #[doc = "Uses bandgap-based bias currents for best performance."]
2937 pub const REFTOP_SELFBIASOFF_1: u32 = 0x01;
2938 }
2939 }
2940 #[doc = "Not related to CCM. See Power Management Unit (PMU)"]
2941 pub mod REFTOP_VBGADJ {
2942 pub const offset: u32 = 4;
2943 pub const mask: u32 = 0x07 << offset;
2944 pub mod R {}
2945 pub mod W {}
2946 pub mod RW {
2947 #[doc = "Nominal VBG"]
2948 pub const REFTOP_VBGADJ_0: u32 = 0;
2949 #[doc = "VBG+0.78%"]
2950 pub const REFTOP_VBGADJ_1: u32 = 0x01;
2951 #[doc = "VBG+1.56%"]
2952 pub const REFTOP_VBGADJ_2: u32 = 0x02;
2953 #[doc = "VBG+2.34%"]
2954 pub const REFTOP_VBGADJ_3: u32 = 0x03;
2955 #[doc = "VBG-0.78%"]
2956 pub const REFTOP_VBGADJ_4: u32 = 0x04;
2957 #[doc = "VBG-1.56%"]
2958 pub const REFTOP_VBGADJ_5: u32 = 0x05;
2959 #[doc = "VBG-2.34%"]
2960 pub const REFTOP_VBGADJ_6: u32 = 0x06;
2961 #[doc = "VBG-3.12%"]
2962 pub const REFTOP_VBGADJ_7: u32 = 0x07;
2963 }
2964 }
2965 #[doc = "Status bit that signals the analog bandgap voltage is up and stable"]
2966 pub mod REFTOP_VBGUP {
2967 pub const offset: u32 = 7;
2968 pub const mask: u32 = 0x01 << offset;
2969 pub mod R {}
2970 pub mod W {}
2971 pub mod RW {}
2972 }
2973 #[doc = "Configure the analog behavior in stop mode."]
2974 pub mod STOP_MODE_CONFIG {
2975 pub const offset: u32 = 10;
2976 pub const mask: u32 = 0x03 << offset;
2977 pub mod R {}
2978 pub mod W {}
2979 pub mod RW {
2980 #[doc = "All analog except RTC powered down on stop mode assertion."]
2981 pub const STOP_MODE_CONFIG_0: u32 = 0;
2982 #[doc = "Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on."]
2983 pub const STOP_MODE_CONFIG_1: u32 = 0x01;
2984 #[doc = "Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down."]
2985 pub const STOP_MODE_CONFIG_2: u32 = 0x02;
2986 #[doc = "Beside RTC, low-power bandgap is selected and the rest analog is powered down."]
2987 pub const STOP_MODE_CONFIG_3: u32 = 0x03;
2988 }
2989 }
2990 #[doc = "This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN."]
2991 pub mod DISCON_HIGH_SNVS {
2992 pub const offset: u32 = 12;
2993 pub const mask: u32 = 0x01 << offset;
2994 pub mod R {}
2995 pub mod W {}
2996 pub mod RW {
2997 #[doc = "Turn on the switch"]
2998 pub const DISCON_HIGH_SNVS_0: u32 = 0;
2999 #[doc = "Turn off the switch"]
3000 pub const DISCON_HIGH_SNVS_1: u32 = 0x01;
3001 }
3002 }
3003 #[doc = "This field determines the bias current in the 24MHz oscillator"]
3004 pub mod OSC_I {
3005 pub const offset: u32 = 13;
3006 pub const mask: u32 = 0x03 << offset;
3007 pub mod R {}
3008 pub mod W {}
3009 pub mod RW {
3010 #[doc = "Nominal"]
3011 pub const NOMINAL: u32 = 0;
3012 #[doc = "Decrease current by 12.5%"]
3013 pub const MINUS_12_5_PERCENT: u32 = 0x01;
3014 #[doc = "Decrease current by 25.0%"]
3015 pub const MINUS_25_PERCENT: u32 = 0x02;
3016 #[doc = "Decrease current by 37.5%"]
3017 pub const MINUS_37_5_PERCENT: u32 = 0x03;
3018 }
3019 }
3020 #[doc = "Status bit that signals that the output of the 24-MHz crystal oscillator is stable"]
3021 pub mod OSC_XTALOK {
3022 pub const offset: u32 = 15;
3023 pub const mask: u32 = 0x01 << offset;
3024 pub mod R {}
3025 pub mod W {}
3026 pub mod RW {}
3027 }
3028 #[doc = "This bit enables the detector that signals when the 24MHz crystal oscillator is stable"]
3029 pub mod OSC_XTALOK_EN {
3030 pub const offset: u32 = 16;
3031 pub const mask: u32 = 0x01 << offset;
3032 pub mod R {}
3033 pub mod W {}
3034 pub mod RW {}
3035 }
3036 #[doc = "This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block"]
3037 pub mod CLKGATE_CTRL {
3038 pub const offset: u32 = 25;
3039 pub const mask: u32 = 0x01 << offset;
3040 pub mod R {}
3041 pub mod W {}
3042 pub mod RW {
3043 #[doc = "Allow the logic to automatically gate the clock when the XTAL is powered down."]
3044 pub const ALLOW_AUTO_GATE: u32 = 0;
3045 #[doc = "Prevent the logic from ever gating off the clock."]
3046 pub const NO_AUTO_GATE: u32 = 0x01;
3047 }
3048 }
3049 #[doc = "This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block"]
3050 pub mod CLKGATE_DELAY {
3051 pub const offset: u32 = 26;
3052 pub const mask: u32 = 0x07 << offset;
3053 pub mod R {}
3054 pub mod W {}
3055 pub mod RW {
3056 #[doc = "0.5ms"]
3057 pub const CLKGATE_DELAY_0: u32 = 0;
3058 #[doc = "1.0ms"]
3059 pub const CLKGATE_DELAY_1: u32 = 0x01;
3060 #[doc = "2.0ms"]
3061 pub const CLKGATE_DELAY_2: u32 = 0x02;
3062 #[doc = "3.0ms"]
3063 pub const CLKGATE_DELAY_3: u32 = 0x03;
3064 #[doc = "4.0ms"]
3065 pub const CLKGATE_DELAY_4: u32 = 0x04;
3066 #[doc = "5.0ms"]
3067 pub const CLKGATE_DELAY_5: u32 = 0x05;
3068 #[doc = "6.0ms"]
3069 pub const CLKGATE_DELAY_6: u32 = 0x06;
3070 #[doc = "7.0ms"]
3071 pub const CLKGATE_DELAY_7: u32 = 0x07;
3072 }
3073 }
3074 #[doc = "This field indicates which chip source is being used for the rtc clock"]
3075 pub mod RTC_XTAL_SOURCE {
3076 pub const offset: u32 = 29;
3077 pub const mask: u32 = 0x01 << offset;
3078 pub mod R {}
3079 pub mod W {}
3080 pub mod RW {
3081 #[doc = "Internal ring oscillator"]
3082 pub const RTC_XTAL_SOURCE_0: u32 = 0;
3083 #[doc = "RTC_XTAL"]
3084 pub const RTC_XTAL_SOURCE_1: u32 = 0x01;
3085 }
3086 }
3087 #[doc = "This field powers down the 24M crystal oscillator if set true"]
3088 pub mod XTAL_24M_PWD {
3089 pub const offset: u32 = 30;
3090 pub const mask: u32 = 0x01 << offset;
3091 pub mod R {}
3092 pub mod W {}
3093 pub mod RW {}
3094 }
3095}
3096#[doc = "Miscellaneous Register 0"]
3097pub mod MISC0_SET {
3098 #[doc = "Control bit to power-down the analog bandgap reference circuitry"]
3099 pub mod REFTOP_PWD {
3100 pub const offset: u32 = 0;
3101 pub const mask: u32 = 0x01 << offset;
3102 pub mod R {}
3103 pub mod W {}
3104 pub mod RW {}
3105 }
3106 #[doc = "Control bit to disable the self-bias circuit in the analog bandgap"]
3107 pub mod REFTOP_SELFBIASOFF {
3108 pub const offset: u32 = 3;
3109 pub const mask: u32 = 0x01 << offset;
3110 pub mod R {}
3111 pub mod W {}
3112 pub mod RW {
3113 #[doc = "Uses coarse bias currents for startup"]
3114 pub const REFTOP_SELFBIASOFF_0: u32 = 0;
3115 #[doc = "Uses bandgap-based bias currents for best performance."]
3116 pub const REFTOP_SELFBIASOFF_1: u32 = 0x01;
3117 }
3118 }
3119 #[doc = "Not related to CCM. See Power Management Unit (PMU)"]
3120 pub mod REFTOP_VBGADJ {
3121 pub const offset: u32 = 4;
3122 pub const mask: u32 = 0x07 << offset;
3123 pub mod R {}
3124 pub mod W {}
3125 pub mod RW {
3126 #[doc = "Nominal VBG"]
3127 pub const REFTOP_VBGADJ_0: u32 = 0;
3128 #[doc = "VBG+0.78%"]
3129 pub const REFTOP_VBGADJ_1: u32 = 0x01;
3130 #[doc = "VBG+1.56%"]
3131 pub const REFTOP_VBGADJ_2: u32 = 0x02;
3132 #[doc = "VBG+2.34%"]
3133 pub const REFTOP_VBGADJ_3: u32 = 0x03;
3134 #[doc = "VBG-0.78%"]
3135 pub const REFTOP_VBGADJ_4: u32 = 0x04;
3136 #[doc = "VBG-1.56%"]
3137 pub const REFTOP_VBGADJ_5: u32 = 0x05;
3138 #[doc = "VBG-2.34%"]
3139 pub const REFTOP_VBGADJ_6: u32 = 0x06;
3140 #[doc = "VBG-3.12%"]
3141 pub const REFTOP_VBGADJ_7: u32 = 0x07;
3142 }
3143 }
3144 #[doc = "Status bit that signals the analog bandgap voltage is up and stable"]
3145 pub mod REFTOP_VBGUP {
3146 pub const offset: u32 = 7;
3147 pub const mask: u32 = 0x01 << offset;
3148 pub mod R {}
3149 pub mod W {}
3150 pub mod RW {}
3151 }
3152 #[doc = "Configure the analog behavior in stop mode."]
3153 pub mod STOP_MODE_CONFIG {
3154 pub const offset: u32 = 10;
3155 pub const mask: u32 = 0x03 << offset;
3156 pub mod R {}
3157 pub mod W {}
3158 pub mod RW {
3159 #[doc = "All analog except RTC powered down on stop mode assertion."]
3160 pub const STOP_MODE_CONFIG_0: u32 = 0;
3161 #[doc = "Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on."]
3162 pub const STOP_MODE_CONFIG_1: u32 = 0x01;
3163 #[doc = "Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down."]
3164 pub const STOP_MODE_CONFIG_2: u32 = 0x02;
3165 #[doc = "Beside RTC, low-power bandgap is selected and the rest analog is powered down."]
3166 pub const STOP_MODE_CONFIG_3: u32 = 0x03;
3167 }
3168 }
3169 #[doc = "This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN."]
3170 pub mod DISCON_HIGH_SNVS {
3171 pub const offset: u32 = 12;
3172 pub const mask: u32 = 0x01 << offset;
3173 pub mod R {}
3174 pub mod W {}
3175 pub mod RW {
3176 #[doc = "Turn on the switch"]
3177 pub const DISCON_HIGH_SNVS_0: u32 = 0;
3178 #[doc = "Turn off the switch"]
3179 pub const DISCON_HIGH_SNVS_1: u32 = 0x01;
3180 }
3181 }
3182 #[doc = "This field determines the bias current in the 24MHz oscillator"]
3183 pub mod OSC_I {
3184 pub const offset: u32 = 13;
3185 pub const mask: u32 = 0x03 << offset;
3186 pub mod R {}
3187 pub mod W {}
3188 pub mod RW {
3189 #[doc = "Nominal"]
3190 pub const NOMINAL: u32 = 0;
3191 #[doc = "Decrease current by 12.5%"]
3192 pub const MINUS_12_5_PERCENT: u32 = 0x01;
3193 #[doc = "Decrease current by 25.0%"]
3194 pub const MINUS_25_PERCENT: u32 = 0x02;
3195 #[doc = "Decrease current by 37.5%"]
3196 pub const MINUS_37_5_PERCENT: u32 = 0x03;
3197 }
3198 }
3199 #[doc = "Status bit that signals that the output of the 24-MHz crystal oscillator is stable"]
3200 pub mod OSC_XTALOK {
3201 pub const offset: u32 = 15;
3202 pub const mask: u32 = 0x01 << offset;
3203 pub mod R {}
3204 pub mod W {}
3205 pub mod RW {}
3206 }
3207 #[doc = "This bit enables the detector that signals when the 24MHz crystal oscillator is stable"]
3208 pub mod OSC_XTALOK_EN {
3209 pub const offset: u32 = 16;
3210 pub const mask: u32 = 0x01 << offset;
3211 pub mod R {}
3212 pub mod W {}
3213 pub mod RW {}
3214 }
3215 #[doc = "This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block"]
3216 pub mod CLKGATE_CTRL {
3217 pub const offset: u32 = 25;
3218 pub const mask: u32 = 0x01 << offset;
3219 pub mod R {}
3220 pub mod W {}
3221 pub mod RW {
3222 #[doc = "Allow the logic to automatically gate the clock when the XTAL is powered down."]
3223 pub const ALLOW_AUTO_GATE: u32 = 0;
3224 #[doc = "Prevent the logic from ever gating off the clock."]
3225 pub const NO_AUTO_GATE: u32 = 0x01;
3226 }
3227 }
3228 #[doc = "This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block"]
3229 pub mod CLKGATE_DELAY {
3230 pub const offset: u32 = 26;
3231 pub const mask: u32 = 0x07 << offset;
3232 pub mod R {}
3233 pub mod W {}
3234 pub mod RW {
3235 #[doc = "0.5ms"]
3236 pub const CLKGATE_DELAY_0: u32 = 0;
3237 #[doc = "1.0ms"]
3238 pub const CLKGATE_DELAY_1: u32 = 0x01;
3239 #[doc = "2.0ms"]
3240 pub const CLKGATE_DELAY_2: u32 = 0x02;
3241 #[doc = "3.0ms"]
3242 pub const CLKGATE_DELAY_3: u32 = 0x03;
3243 #[doc = "4.0ms"]
3244 pub const CLKGATE_DELAY_4: u32 = 0x04;
3245 #[doc = "5.0ms"]
3246 pub const CLKGATE_DELAY_5: u32 = 0x05;
3247 #[doc = "6.0ms"]
3248 pub const CLKGATE_DELAY_6: u32 = 0x06;
3249 #[doc = "7.0ms"]
3250 pub const CLKGATE_DELAY_7: u32 = 0x07;
3251 }
3252 }
3253 #[doc = "This field indicates which chip source is being used for the rtc clock"]
3254 pub mod RTC_XTAL_SOURCE {
3255 pub const offset: u32 = 29;
3256 pub const mask: u32 = 0x01 << offset;
3257 pub mod R {}
3258 pub mod W {}
3259 pub mod RW {
3260 #[doc = "Internal ring oscillator"]
3261 pub const RTC_XTAL_SOURCE_0: u32 = 0;
3262 #[doc = "RTC_XTAL"]
3263 pub const RTC_XTAL_SOURCE_1: u32 = 0x01;
3264 }
3265 }
3266 #[doc = "This field powers down the 24M crystal oscillator if set true"]
3267 pub mod XTAL_24M_PWD {
3268 pub const offset: u32 = 30;
3269 pub const mask: u32 = 0x01 << offset;
3270 pub mod R {}
3271 pub mod W {}
3272 pub mod RW {}
3273 }
3274}
3275#[doc = "Miscellaneous Register 0"]
3276pub mod MISC0_CLR {
3277 #[doc = "Control bit to power-down the analog bandgap reference circuitry"]
3278 pub mod REFTOP_PWD {
3279 pub const offset: u32 = 0;
3280 pub const mask: u32 = 0x01 << offset;
3281 pub mod R {}
3282 pub mod W {}
3283 pub mod RW {}
3284 }
3285 #[doc = "Control bit to disable the self-bias circuit in the analog bandgap"]
3286 pub mod REFTOP_SELFBIASOFF {
3287 pub const offset: u32 = 3;
3288 pub const mask: u32 = 0x01 << offset;
3289 pub mod R {}
3290 pub mod W {}
3291 pub mod RW {
3292 #[doc = "Uses coarse bias currents for startup"]
3293 pub const REFTOP_SELFBIASOFF_0: u32 = 0;
3294 #[doc = "Uses bandgap-based bias currents for best performance."]
3295 pub const REFTOP_SELFBIASOFF_1: u32 = 0x01;
3296 }
3297 }
3298 #[doc = "Not related to CCM. See Power Management Unit (PMU)"]
3299 pub mod REFTOP_VBGADJ {
3300 pub const offset: u32 = 4;
3301 pub const mask: u32 = 0x07 << offset;
3302 pub mod R {}
3303 pub mod W {}
3304 pub mod RW {
3305 #[doc = "Nominal VBG"]
3306 pub const REFTOP_VBGADJ_0: u32 = 0;
3307 #[doc = "VBG+0.78%"]
3308 pub const REFTOP_VBGADJ_1: u32 = 0x01;
3309 #[doc = "VBG+1.56%"]
3310 pub const REFTOP_VBGADJ_2: u32 = 0x02;
3311 #[doc = "VBG+2.34%"]
3312 pub const REFTOP_VBGADJ_3: u32 = 0x03;
3313 #[doc = "VBG-0.78%"]
3314 pub const REFTOP_VBGADJ_4: u32 = 0x04;
3315 #[doc = "VBG-1.56%"]
3316 pub const REFTOP_VBGADJ_5: u32 = 0x05;
3317 #[doc = "VBG-2.34%"]
3318 pub const REFTOP_VBGADJ_6: u32 = 0x06;
3319 #[doc = "VBG-3.12%"]
3320 pub const REFTOP_VBGADJ_7: u32 = 0x07;
3321 }
3322 }
3323 #[doc = "Status bit that signals the analog bandgap voltage is up and stable"]
3324 pub mod REFTOP_VBGUP {
3325 pub const offset: u32 = 7;
3326 pub const mask: u32 = 0x01 << offset;
3327 pub mod R {}
3328 pub mod W {}
3329 pub mod RW {}
3330 }
3331 #[doc = "Configure the analog behavior in stop mode."]
3332 pub mod STOP_MODE_CONFIG {
3333 pub const offset: u32 = 10;
3334 pub const mask: u32 = 0x03 << offset;
3335 pub mod R {}
3336 pub mod W {}
3337 pub mod RW {
3338 #[doc = "All analog except RTC powered down on stop mode assertion."]
3339 pub const STOP_MODE_CONFIG_0: u32 = 0;
3340 #[doc = "Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on."]
3341 pub const STOP_MODE_CONFIG_1: u32 = 0x01;
3342 #[doc = "Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down."]
3343 pub const STOP_MODE_CONFIG_2: u32 = 0x02;
3344 #[doc = "Beside RTC, low-power bandgap is selected and the rest analog is powered down."]
3345 pub const STOP_MODE_CONFIG_3: u32 = 0x03;
3346 }
3347 }
3348 #[doc = "This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN."]
3349 pub mod DISCON_HIGH_SNVS {
3350 pub const offset: u32 = 12;
3351 pub const mask: u32 = 0x01 << offset;
3352 pub mod R {}
3353 pub mod W {}
3354 pub mod RW {
3355 #[doc = "Turn on the switch"]
3356 pub const DISCON_HIGH_SNVS_0: u32 = 0;
3357 #[doc = "Turn off the switch"]
3358 pub const DISCON_HIGH_SNVS_1: u32 = 0x01;
3359 }
3360 }
3361 #[doc = "This field determines the bias current in the 24MHz oscillator"]
3362 pub mod OSC_I {
3363 pub const offset: u32 = 13;
3364 pub const mask: u32 = 0x03 << offset;
3365 pub mod R {}
3366 pub mod W {}
3367 pub mod RW {
3368 #[doc = "Nominal"]
3369 pub const NOMINAL: u32 = 0;
3370 #[doc = "Decrease current by 12.5%"]
3371 pub const MINUS_12_5_PERCENT: u32 = 0x01;
3372 #[doc = "Decrease current by 25.0%"]
3373 pub const MINUS_25_PERCENT: u32 = 0x02;
3374 #[doc = "Decrease current by 37.5%"]
3375 pub const MINUS_37_5_PERCENT: u32 = 0x03;
3376 }
3377 }
3378 #[doc = "Status bit that signals that the output of the 24-MHz crystal oscillator is stable"]
3379 pub mod OSC_XTALOK {
3380 pub const offset: u32 = 15;
3381 pub const mask: u32 = 0x01 << offset;
3382 pub mod R {}
3383 pub mod W {}
3384 pub mod RW {}
3385 }
3386 #[doc = "This bit enables the detector that signals when the 24MHz crystal oscillator is stable"]
3387 pub mod OSC_XTALOK_EN {
3388 pub const offset: u32 = 16;
3389 pub const mask: u32 = 0x01 << offset;
3390 pub mod R {}
3391 pub mod W {}
3392 pub mod RW {}
3393 }
3394 #[doc = "This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block"]
3395 pub mod CLKGATE_CTRL {
3396 pub const offset: u32 = 25;
3397 pub const mask: u32 = 0x01 << offset;
3398 pub mod R {}
3399 pub mod W {}
3400 pub mod RW {
3401 #[doc = "Allow the logic to automatically gate the clock when the XTAL is powered down."]
3402 pub const ALLOW_AUTO_GATE: u32 = 0;
3403 #[doc = "Prevent the logic from ever gating off the clock."]
3404 pub const NO_AUTO_GATE: u32 = 0x01;
3405 }
3406 }
3407 #[doc = "This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block"]
3408 pub mod CLKGATE_DELAY {
3409 pub const offset: u32 = 26;
3410 pub const mask: u32 = 0x07 << offset;
3411 pub mod R {}
3412 pub mod W {}
3413 pub mod RW {
3414 #[doc = "0.5ms"]
3415 pub const CLKGATE_DELAY_0: u32 = 0;
3416 #[doc = "1.0ms"]
3417 pub const CLKGATE_DELAY_1: u32 = 0x01;
3418 #[doc = "2.0ms"]
3419 pub const CLKGATE_DELAY_2: u32 = 0x02;
3420 #[doc = "3.0ms"]
3421 pub const CLKGATE_DELAY_3: u32 = 0x03;
3422 #[doc = "4.0ms"]
3423 pub const CLKGATE_DELAY_4: u32 = 0x04;
3424 #[doc = "5.0ms"]
3425 pub const CLKGATE_DELAY_5: u32 = 0x05;
3426 #[doc = "6.0ms"]
3427 pub const CLKGATE_DELAY_6: u32 = 0x06;
3428 #[doc = "7.0ms"]
3429 pub const CLKGATE_DELAY_7: u32 = 0x07;
3430 }
3431 }
3432 #[doc = "This field indicates which chip source is being used for the rtc clock"]
3433 pub mod RTC_XTAL_SOURCE {
3434 pub const offset: u32 = 29;
3435 pub const mask: u32 = 0x01 << offset;
3436 pub mod R {}
3437 pub mod W {}
3438 pub mod RW {
3439 #[doc = "Internal ring oscillator"]
3440 pub const RTC_XTAL_SOURCE_0: u32 = 0;
3441 #[doc = "RTC_XTAL"]
3442 pub const RTC_XTAL_SOURCE_1: u32 = 0x01;
3443 }
3444 }
3445 #[doc = "This field powers down the 24M crystal oscillator if set true"]
3446 pub mod XTAL_24M_PWD {
3447 pub const offset: u32 = 30;
3448 pub const mask: u32 = 0x01 << offset;
3449 pub mod R {}
3450 pub mod W {}
3451 pub mod RW {}
3452 }
3453}
3454#[doc = "Miscellaneous Register 0"]
3455pub mod MISC0_TOG {
3456 #[doc = "Control bit to power-down the analog bandgap reference circuitry"]
3457 pub mod REFTOP_PWD {
3458 pub const offset: u32 = 0;
3459 pub const mask: u32 = 0x01 << offset;
3460 pub mod R {}
3461 pub mod W {}
3462 pub mod RW {}
3463 }
3464 #[doc = "Control bit to disable the self-bias circuit in the analog bandgap"]
3465 pub mod REFTOP_SELFBIASOFF {
3466 pub const offset: u32 = 3;
3467 pub const mask: u32 = 0x01 << offset;
3468 pub mod R {}
3469 pub mod W {}
3470 pub mod RW {
3471 #[doc = "Uses coarse bias currents for startup"]
3472 pub const REFTOP_SELFBIASOFF_0: u32 = 0;
3473 #[doc = "Uses bandgap-based bias currents for best performance."]
3474 pub const REFTOP_SELFBIASOFF_1: u32 = 0x01;
3475 }
3476 }
3477 #[doc = "Not related to CCM. See Power Management Unit (PMU)"]
3478 pub mod REFTOP_VBGADJ {
3479 pub const offset: u32 = 4;
3480 pub const mask: u32 = 0x07 << offset;
3481 pub mod R {}
3482 pub mod W {}
3483 pub mod RW {
3484 #[doc = "Nominal VBG"]
3485 pub const REFTOP_VBGADJ_0: u32 = 0;
3486 #[doc = "VBG+0.78%"]
3487 pub const REFTOP_VBGADJ_1: u32 = 0x01;
3488 #[doc = "VBG+1.56%"]
3489 pub const REFTOP_VBGADJ_2: u32 = 0x02;
3490 #[doc = "VBG+2.34%"]
3491 pub const REFTOP_VBGADJ_3: u32 = 0x03;
3492 #[doc = "VBG-0.78%"]
3493 pub const REFTOP_VBGADJ_4: u32 = 0x04;
3494 #[doc = "VBG-1.56%"]
3495 pub const REFTOP_VBGADJ_5: u32 = 0x05;
3496 #[doc = "VBG-2.34%"]
3497 pub const REFTOP_VBGADJ_6: u32 = 0x06;
3498 #[doc = "VBG-3.12%"]
3499 pub const REFTOP_VBGADJ_7: u32 = 0x07;
3500 }
3501 }
3502 #[doc = "Status bit that signals the analog bandgap voltage is up and stable"]
3503 pub mod REFTOP_VBGUP {
3504 pub const offset: u32 = 7;
3505 pub const mask: u32 = 0x01 << offset;
3506 pub mod R {}
3507 pub mod W {}
3508 pub mod RW {}
3509 }
3510 #[doc = "Configure the analog behavior in stop mode."]
3511 pub mod STOP_MODE_CONFIG {
3512 pub const offset: u32 = 10;
3513 pub const mask: u32 = 0x03 << offset;
3514 pub mod R {}
3515 pub mod W {}
3516 pub mod RW {
3517 #[doc = "All analog except RTC powered down on stop mode assertion."]
3518 pub const STOP_MODE_CONFIG_0: u32 = 0;
3519 #[doc = "Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on."]
3520 pub const STOP_MODE_CONFIG_1: u32 = 0x01;
3521 #[doc = "Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down."]
3522 pub const STOP_MODE_CONFIG_2: u32 = 0x02;
3523 #[doc = "Beside RTC, low-power bandgap is selected and the rest analog is powered down."]
3524 pub const STOP_MODE_CONFIG_3: u32 = 0x03;
3525 }
3526 }
3527 #[doc = "This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN."]
3528 pub mod DISCON_HIGH_SNVS {
3529 pub const offset: u32 = 12;
3530 pub const mask: u32 = 0x01 << offset;
3531 pub mod R {}
3532 pub mod W {}
3533 pub mod RW {
3534 #[doc = "Turn on the switch"]
3535 pub const DISCON_HIGH_SNVS_0: u32 = 0;
3536 #[doc = "Turn off the switch"]
3537 pub const DISCON_HIGH_SNVS_1: u32 = 0x01;
3538 }
3539 }
3540 #[doc = "This field determines the bias current in the 24MHz oscillator"]
3541 pub mod OSC_I {
3542 pub const offset: u32 = 13;
3543 pub const mask: u32 = 0x03 << offset;
3544 pub mod R {}
3545 pub mod W {}
3546 pub mod RW {
3547 #[doc = "Nominal"]
3548 pub const NOMINAL: u32 = 0;
3549 #[doc = "Decrease current by 12.5%"]
3550 pub const MINUS_12_5_PERCENT: u32 = 0x01;
3551 #[doc = "Decrease current by 25.0%"]
3552 pub const MINUS_25_PERCENT: u32 = 0x02;
3553 #[doc = "Decrease current by 37.5%"]
3554 pub const MINUS_37_5_PERCENT: u32 = 0x03;
3555 }
3556 }
3557 #[doc = "Status bit that signals that the output of the 24-MHz crystal oscillator is stable"]
3558 pub mod OSC_XTALOK {
3559 pub const offset: u32 = 15;
3560 pub const mask: u32 = 0x01 << offset;
3561 pub mod R {}
3562 pub mod W {}
3563 pub mod RW {}
3564 }
3565 #[doc = "This bit enables the detector that signals when the 24MHz crystal oscillator is stable"]
3566 pub mod OSC_XTALOK_EN {
3567 pub const offset: u32 = 16;
3568 pub const mask: u32 = 0x01 << offset;
3569 pub mod R {}
3570 pub mod W {}
3571 pub mod RW {}
3572 }
3573 #[doc = "This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block"]
3574 pub mod CLKGATE_CTRL {
3575 pub const offset: u32 = 25;
3576 pub const mask: u32 = 0x01 << offset;
3577 pub mod R {}
3578 pub mod W {}
3579 pub mod RW {
3580 #[doc = "Allow the logic to automatically gate the clock when the XTAL is powered down."]
3581 pub const ALLOW_AUTO_GATE: u32 = 0;
3582 #[doc = "Prevent the logic from ever gating off the clock."]
3583 pub const NO_AUTO_GATE: u32 = 0x01;
3584 }
3585 }
3586 #[doc = "This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block"]
3587 pub mod CLKGATE_DELAY {
3588 pub const offset: u32 = 26;
3589 pub const mask: u32 = 0x07 << offset;
3590 pub mod R {}
3591 pub mod W {}
3592 pub mod RW {
3593 #[doc = "0.5ms"]
3594 pub const CLKGATE_DELAY_0: u32 = 0;
3595 #[doc = "1.0ms"]
3596 pub const CLKGATE_DELAY_1: u32 = 0x01;
3597 #[doc = "2.0ms"]
3598 pub const CLKGATE_DELAY_2: u32 = 0x02;
3599 #[doc = "3.0ms"]
3600 pub const CLKGATE_DELAY_3: u32 = 0x03;
3601 #[doc = "4.0ms"]
3602 pub const CLKGATE_DELAY_4: u32 = 0x04;
3603 #[doc = "5.0ms"]
3604 pub const CLKGATE_DELAY_5: u32 = 0x05;
3605 #[doc = "6.0ms"]
3606 pub const CLKGATE_DELAY_6: u32 = 0x06;
3607 #[doc = "7.0ms"]
3608 pub const CLKGATE_DELAY_7: u32 = 0x07;
3609 }
3610 }
3611 #[doc = "This field indicates which chip source is being used for the rtc clock"]
3612 pub mod RTC_XTAL_SOURCE {
3613 pub const offset: u32 = 29;
3614 pub const mask: u32 = 0x01 << offset;
3615 pub mod R {}
3616 pub mod W {}
3617 pub mod RW {
3618 #[doc = "Internal ring oscillator"]
3619 pub const RTC_XTAL_SOURCE_0: u32 = 0;
3620 #[doc = "RTC_XTAL"]
3621 pub const RTC_XTAL_SOURCE_1: u32 = 0x01;
3622 }
3623 }
3624 #[doc = "This field powers down the 24M crystal oscillator if set true"]
3625 pub mod XTAL_24M_PWD {
3626 pub const offset: u32 = 30;
3627 pub const mask: u32 = 0x01 << offset;
3628 pub mod R {}
3629 pub mod W {}
3630 pub mod RW {}
3631 }
3632}
3633#[doc = "Miscellaneous Register 1"]
3634pub mod MISC1 {
3635 #[doc = "This field selects the clk to be routed to anaclk1/1b."]
3636 pub mod LVDS1_CLK_SEL {
3637 pub const offset: u32 = 0;
3638 pub const mask: u32 = 0x1f << offset;
3639 pub mod R {}
3640 pub mod W {}
3641 pub mod RW {
3642 #[doc = "Arm PLL"]
3643 pub const ARM_PLL: u32 = 0;
3644 #[doc = "System PLL"]
3645 pub const SYS_PLL: u32 = 0x01;
3646 #[doc = "ref_pfd4_clk == pll2_pfd0_clk"]
3647 pub const PFD4: u32 = 0x02;
3648 #[doc = "ref_pfd5_clk == pll2_pfd1_clk"]
3649 pub const PFD5: u32 = 0x03;
3650 #[doc = "ref_pfd6_clk == pll2_pfd2_clk"]
3651 pub const PFD6: u32 = 0x04;
3652 #[doc = "ref_pfd7_clk == pll2_pfd3_clk"]
3653 pub const PFD7: u32 = 0x05;
3654 #[doc = "Audio PLL"]
3655 pub const AUDIO_PLL: u32 = 0x06;
3656 #[doc = "Video PLL"]
3657 pub const VIDEO_PLL: u32 = 0x07;
3658 #[doc = "ethernet ref clock (ENET_PLL)"]
3659 pub const ETHERNET_REF: u32 = 0x09;
3660 #[doc = "USB1 PLL clock"]
3661 pub const USB1_PLL: u32 = 0x0c;
3662 #[doc = "USB2 PLL clock"]
3663 pub const USB2_PLL: u32 = 0x0d;
3664 #[doc = "ref_pfd0_clk == pll3_pfd0_clk"]
3665 pub const PFD0: u32 = 0x0e;
3666 #[doc = "ref_pfd1_clk == pll3_pfd1_clk"]
3667 pub const PFD1: u32 = 0x0f;
3668 #[doc = "ref_pfd2_clk == pll3_pfd2_clk"]
3669 pub const PFD2: u32 = 0x10;
3670 #[doc = "ref_pfd3_clk == pll3_pfd3_clk"]
3671 pub const PFD3: u32 = 0x11;
3672 #[doc = "xtal (24M)"]
3673 pub const XTAL: u32 = 0x12;
3674 }
3675 }
3676 #[doc = "This enables the LVDS output buffer for anaclk1/1b"]
3677 pub mod LVDSCLK1_OBEN {
3678 pub const offset: u32 = 10;
3679 pub const mask: u32 = 0x01 << offset;
3680 pub mod R {}
3681 pub mod W {}
3682 pub mod RW {}
3683 }
3684 #[doc = "This enables the LVDS input buffer for anaclk1/1b"]
3685 pub mod LVDSCLK1_IBEN {
3686 pub const offset: u32 = 12;
3687 pub const mask: u32 = 0x01 << offset;
3688 pub mod R {}
3689 pub mod W {}
3690 pub mod RW {}
3691 }
3692 #[doc = "This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off"]
3693 pub mod PFD_480_AUTOGATE_EN {
3694 pub const offset: u32 = 16;
3695 pub const mask: u32 = 0x01 << offset;
3696 pub mod R {}
3697 pub mod W {}
3698 pub mod RW {}
3699 }
3700 #[doc = "This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off"]
3701 pub mod PFD_528_AUTOGATE_EN {
3702 pub const offset: u32 = 17;
3703 pub const mask: u32 = 0x01 << offset;
3704 pub mod R {}
3705 pub mod W {}
3706 pub mod RW {}
3707 }
3708 #[doc = "This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature"]
3709 pub mod IRQ_TEMPPANIC {
3710 pub const offset: u32 = 27;
3711 pub const mask: u32 = 0x01 << offset;
3712 pub mod R {}
3713 pub mod W {}
3714 pub mod RW {}
3715 }
3716 #[doc = "This status bit is set to one when the temperature sensor low interrupt asserts for low temperature"]
3717 pub mod IRQ_TEMPLOW {
3718 pub const offset: u32 = 28;
3719 pub const mask: u32 = 0x01 << offset;
3720 pub mod R {}
3721 pub mod W {}
3722 pub mod RW {}
3723 }
3724 #[doc = "This status bit is set to one when the temperature sensor high interrupt asserts for high temperature"]
3725 pub mod IRQ_TEMPHIGH {
3726 pub const offset: u32 = 29;
3727 pub const mask: u32 = 0x01 << offset;
3728 pub mod R {}
3729 pub mod W {}
3730 pub mod RW {}
3731 }
3732 #[doc = "This status bit is set to one when when any of the analog regulator brownout interrupts assert"]
3733 pub mod IRQ_ANA_BO {
3734 pub const offset: u32 = 30;
3735 pub const mask: u32 = 0x01 << offset;
3736 pub mod R {}
3737 pub mod W {}
3738 pub mod RW {}
3739 }
3740 #[doc = "This status bit is set to one when when any of the digital regulator brownout interrupts assert"]
3741 pub mod IRQ_DIG_BO {
3742 pub const offset: u32 = 31;
3743 pub const mask: u32 = 0x01 << offset;
3744 pub mod R {}
3745 pub mod W {}
3746 pub mod RW {}
3747 }
3748}
3749#[doc = "Miscellaneous Register 1"]
3750pub mod MISC1_SET {
3751 #[doc = "This field selects the clk to be routed to anaclk1/1b."]
3752 pub mod LVDS1_CLK_SEL {
3753 pub const offset: u32 = 0;
3754 pub const mask: u32 = 0x1f << offset;
3755 pub mod R {}
3756 pub mod W {}
3757 pub mod RW {
3758 #[doc = "Arm PLL"]
3759 pub const ARM_PLL: u32 = 0;
3760 #[doc = "System PLL"]
3761 pub const SYS_PLL: u32 = 0x01;
3762 #[doc = "ref_pfd4_clk == pll2_pfd0_clk"]
3763 pub const PFD4: u32 = 0x02;
3764 #[doc = "ref_pfd5_clk == pll2_pfd1_clk"]
3765 pub const PFD5: u32 = 0x03;
3766 #[doc = "ref_pfd6_clk == pll2_pfd2_clk"]
3767 pub const PFD6: u32 = 0x04;
3768 #[doc = "ref_pfd7_clk == pll2_pfd3_clk"]
3769 pub const PFD7: u32 = 0x05;
3770 #[doc = "Audio PLL"]
3771 pub const AUDIO_PLL: u32 = 0x06;
3772 #[doc = "Video PLL"]
3773 pub const VIDEO_PLL: u32 = 0x07;
3774 #[doc = "ethernet ref clock (ENET_PLL)"]
3775 pub const ETHERNET_REF: u32 = 0x09;
3776 #[doc = "USB1 PLL clock"]
3777 pub const USB1_PLL: u32 = 0x0c;
3778 #[doc = "USB2 PLL clock"]
3779 pub const USB2_PLL: u32 = 0x0d;
3780 #[doc = "ref_pfd0_clk == pll3_pfd0_clk"]
3781 pub const PFD0: u32 = 0x0e;
3782 #[doc = "ref_pfd1_clk == pll3_pfd1_clk"]
3783 pub const PFD1: u32 = 0x0f;
3784 #[doc = "ref_pfd2_clk == pll3_pfd2_clk"]
3785 pub const PFD2: u32 = 0x10;
3786 #[doc = "ref_pfd3_clk == pll3_pfd3_clk"]
3787 pub const PFD3: u32 = 0x11;
3788 #[doc = "xtal (24M)"]
3789 pub const XTAL: u32 = 0x12;
3790 }
3791 }
3792 #[doc = "This enables the LVDS output buffer for anaclk1/1b"]
3793 pub mod LVDSCLK1_OBEN {
3794 pub const offset: u32 = 10;
3795 pub const mask: u32 = 0x01 << offset;
3796 pub mod R {}
3797 pub mod W {}
3798 pub mod RW {}
3799 }
3800 #[doc = "This enables the LVDS input buffer for anaclk1/1b"]
3801 pub mod LVDSCLK1_IBEN {
3802 pub const offset: u32 = 12;
3803 pub const mask: u32 = 0x01 << offset;
3804 pub mod R {}
3805 pub mod W {}
3806 pub mod RW {}
3807 }
3808 #[doc = "This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off"]
3809 pub mod PFD_480_AUTOGATE_EN {
3810 pub const offset: u32 = 16;
3811 pub const mask: u32 = 0x01 << offset;
3812 pub mod R {}
3813 pub mod W {}
3814 pub mod RW {}
3815 }
3816 #[doc = "This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off"]
3817 pub mod PFD_528_AUTOGATE_EN {
3818 pub const offset: u32 = 17;
3819 pub const mask: u32 = 0x01 << offset;
3820 pub mod R {}
3821 pub mod W {}
3822 pub mod RW {}
3823 }
3824 #[doc = "This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature"]
3825 pub mod IRQ_TEMPPANIC {
3826 pub const offset: u32 = 27;
3827 pub const mask: u32 = 0x01 << offset;
3828 pub mod R {}
3829 pub mod W {}
3830 pub mod RW {}
3831 }
3832 #[doc = "This status bit is set to one when the temperature sensor low interrupt asserts for low temperature"]
3833 pub mod IRQ_TEMPLOW {
3834 pub const offset: u32 = 28;
3835 pub const mask: u32 = 0x01 << offset;
3836 pub mod R {}
3837 pub mod W {}
3838 pub mod RW {}
3839 }
3840 #[doc = "This status bit is set to one when the temperature sensor high interrupt asserts for high temperature"]
3841 pub mod IRQ_TEMPHIGH {
3842 pub const offset: u32 = 29;
3843 pub const mask: u32 = 0x01 << offset;
3844 pub mod R {}
3845 pub mod W {}
3846 pub mod RW {}
3847 }
3848 #[doc = "This status bit is set to one when when any of the analog regulator brownout interrupts assert"]
3849 pub mod IRQ_ANA_BO {
3850 pub const offset: u32 = 30;
3851 pub const mask: u32 = 0x01 << offset;
3852 pub mod R {}
3853 pub mod W {}
3854 pub mod RW {}
3855 }
3856 #[doc = "This status bit is set to one when when any of the digital regulator brownout interrupts assert"]
3857 pub mod IRQ_DIG_BO {
3858 pub const offset: u32 = 31;
3859 pub const mask: u32 = 0x01 << offset;
3860 pub mod R {}
3861 pub mod W {}
3862 pub mod RW {}
3863 }
3864}
3865#[doc = "Miscellaneous Register 1"]
3866pub mod MISC1_CLR {
3867 #[doc = "This field selects the clk to be routed to anaclk1/1b."]
3868 pub mod LVDS1_CLK_SEL {
3869 pub const offset: u32 = 0;
3870 pub const mask: u32 = 0x1f << offset;
3871 pub mod R {}
3872 pub mod W {}
3873 pub mod RW {
3874 #[doc = "Arm PLL"]
3875 pub const ARM_PLL: u32 = 0;
3876 #[doc = "System PLL"]
3877 pub const SYS_PLL: u32 = 0x01;
3878 #[doc = "ref_pfd4_clk == pll2_pfd0_clk"]
3879 pub const PFD4: u32 = 0x02;
3880 #[doc = "ref_pfd5_clk == pll2_pfd1_clk"]
3881 pub const PFD5: u32 = 0x03;
3882 #[doc = "ref_pfd6_clk == pll2_pfd2_clk"]
3883 pub const PFD6: u32 = 0x04;
3884 #[doc = "ref_pfd7_clk == pll2_pfd3_clk"]
3885 pub const PFD7: u32 = 0x05;
3886 #[doc = "Audio PLL"]
3887 pub const AUDIO_PLL: u32 = 0x06;
3888 #[doc = "Video PLL"]
3889 pub const VIDEO_PLL: u32 = 0x07;
3890 #[doc = "ethernet ref clock (ENET_PLL)"]
3891 pub const ETHERNET_REF: u32 = 0x09;
3892 #[doc = "USB1 PLL clock"]
3893 pub const USB1_PLL: u32 = 0x0c;
3894 #[doc = "USB2 PLL clock"]
3895 pub const USB2_PLL: u32 = 0x0d;
3896 #[doc = "ref_pfd0_clk == pll3_pfd0_clk"]
3897 pub const PFD0: u32 = 0x0e;
3898 #[doc = "ref_pfd1_clk == pll3_pfd1_clk"]
3899 pub const PFD1: u32 = 0x0f;
3900 #[doc = "ref_pfd2_clk == pll3_pfd2_clk"]
3901 pub const PFD2: u32 = 0x10;
3902 #[doc = "ref_pfd3_clk == pll3_pfd3_clk"]
3903 pub const PFD3: u32 = 0x11;
3904 #[doc = "xtal (24M)"]
3905 pub const XTAL: u32 = 0x12;
3906 }
3907 }
3908 #[doc = "This enables the LVDS output buffer for anaclk1/1b"]
3909 pub mod LVDSCLK1_OBEN {
3910 pub const offset: u32 = 10;
3911 pub const mask: u32 = 0x01 << offset;
3912 pub mod R {}
3913 pub mod W {}
3914 pub mod RW {}
3915 }
3916 #[doc = "This enables the LVDS input buffer for anaclk1/1b"]
3917 pub mod LVDSCLK1_IBEN {
3918 pub const offset: u32 = 12;
3919 pub const mask: u32 = 0x01 << offset;
3920 pub mod R {}
3921 pub mod W {}
3922 pub mod RW {}
3923 }
3924 #[doc = "This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off"]
3925 pub mod PFD_480_AUTOGATE_EN {
3926 pub const offset: u32 = 16;
3927 pub const mask: u32 = 0x01 << offset;
3928 pub mod R {}
3929 pub mod W {}
3930 pub mod RW {}
3931 }
3932 #[doc = "This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off"]
3933 pub mod PFD_528_AUTOGATE_EN {
3934 pub const offset: u32 = 17;
3935 pub const mask: u32 = 0x01 << offset;
3936 pub mod R {}
3937 pub mod W {}
3938 pub mod RW {}
3939 }
3940 #[doc = "This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature"]
3941 pub mod IRQ_TEMPPANIC {
3942 pub const offset: u32 = 27;
3943 pub const mask: u32 = 0x01 << offset;
3944 pub mod R {}
3945 pub mod W {}
3946 pub mod RW {}
3947 }
3948 #[doc = "This status bit is set to one when the temperature sensor low interrupt asserts for low temperature"]
3949 pub mod IRQ_TEMPLOW {
3950 pub const offset: u32 = 28;
3951 pub const mask: u32 = 0x01 << offset;
3952 pub mod R {}
3953 pub mod W {}
3954 pub mod RW {}
3955 }
3956 #[doc = "This status bit is set to one when the temperature sensor high interrupt asserts for high temperature"]
3957 pub mod IRQ_TEMPHIGH {
3958 pub const offset: u32 = 29;
3959 pub const mask: u32 = 0x01 << offset;
3960 pub mod R {}
3961 pub mod W {}
3962 pub mod RW {}
3963 }
3964 #[doc = "This status bit is set to one when when any of the analog regulator brownout interrupts assert"]
3965 pub mod IRQ_ANA_BO {
3966 pub const offset: u32 = 30;
3967 pub const mask: u32 = 0x01 << offset;
3968 pub mod R {}
3969 pub mod W {}
3970 pub mod RW {}
3971 }
3972 #[doc = "This status bit is set to one when when any of the digital regulator brownout interrupts assert"]
3973 pub mod IRQ_DIG_BO {
3974 pub const offset: u32 = 31;
3975 pub const mask: u32 = 0x01 << offset;
3976 pub mod R {}
3977 pub mod W {}
3978 pub mod RW {}
3979 }
3980}
3981#[doc = "Miscellaneous Register 1"]
3982pub mod MISC1_TOG {
3983 #[doc = "This field selects the clk to be routed to anaclk1/1b."]
3984 pub mod LVDS1_CLK_SEL {
3985 pub const offset: u32 = 0;
3986 pub const mask: u32 = 0x1f << offset;
3987 pub mod R {}
3988 pub mod W {}
3989 pub mod RW {
3990 #[doc = "Arm PLL"]
3991 pub const ARM_PLL: u32 = 0;
3992 #[doc = "System PLL"]
3993 pub const SYS_PLL: u32 = 0x01;
3994 #[doc = "ref_pfd4_clk == pll2_pfd0_clk"]
3995 pub const PFD4: u32 = 0x02;
3996 #[doc = "ref_pfd5_clk == pll2_pfd1_clk"]
3997 pub const PFD5: u32 = 0x03;
3998 #[doc = "ref_pfd6_clk == pll2_pfd2_clk"]
3999 pub const PFD6: u32 = 0x04;
4000 #[doc = "ref_pfd7_clk == pll2_pfd3_clk"]
4001 pub const PFD7: u32 = 0x05;
4002 #[doc = "Audio PLL"]
4003 pub const AUDIO_PLL: u32 = 0x06;
4004 #[doc = "Video PLL"]
4005 pub const VIDEO_PLL: u32 = 0x07;
4006 #[doc = "ethernet ref clock (ENET_PLL)"]
4007 pub const ETHERNET_REF: u32 = 0x09;
4008 #[doc = "USB1 PLL clock"]
4009 pub const USB1_PLL: u32 = 0x0c;
4010 #[doc = "USB2 PLL clock"]
4011 pub const USB2_PLL: u32 = 0x0d;
4012 #[doc = "ref_pfd0_clk == pll3_pfd0_clk"]
4013 pub const PFD0: u32 = 0x0e;
4014 #[doc = "ref_pfd1_clk == pll3_pfd1_clk"]
4015 pub const PFD1: u32 = 0x0f;
4016 #[doc = "ref_pfd2_clk == pll3_pfd2_clk"]
4017 pub const PFD2: u32 = 0x10;
4018 #[doc = "ref_pfd3_clk == pll3_pfd3_clk"]
4019 pub const PFD3: u32 = 0x11;
4020 #[doc = "xtal (24M)"]
4021 pub const XTAL: u32 = 0x12;
4022 }
4023 }
4024 #[doc = "This enables the LVDS output buffer for anaclk1/1b"]
4025 pub mod LVDSCLK1_OBEN {
4026 pub const offset: u32 = 10;
4027 pub const mask: u32 = 0x01 << offset;
4028 pub mod R {}
4029 pub mod W {}
4030 pub mod RW {}
4031 }
4032 #[doc = "This enables the LVDS input buffer for anaclk1/1b"]
4033 pub mod LVDSCLK1_IBEN {
4034 pub const offset: u32 = 12;
4035 pub const mask: u32 = 0x01 << offset;
4036 pub mod R {}
4037 pub mod W {}
4038 pub mod RW {}
4039 }
4040 #[doc = "This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off"]
4041 pub mod PFD_480_AUTOGATE_EN {
4042 pub const offset: u32 = 16;
4043 pub const mask: u32 = 0x01 << offset;
4044 pub mod R {}
4045 pub mod W {}
4046 pub mod RW {}
4047 }
4048 #[doc = "This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off"]
4049 pub mod PFD_528_AUTOGATE_EN {
4050 pub const offset: u32 = 17;
4051 pub const mask: u32 = 0x01 << offset;
4052 pub mod R {}
4053 pub mod W {}
4054 pub mod RW {}
4055 }
4056 #[doc = "This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature"]
4057 pub mod IRQ_TEMPPANIC {
4058 pub const offset: u32 = 27;
4059 pub const mask: u32 = 0x01 << offset;
4060 pub mod R {}
4061 pub mod W {}
4062 pub mod RW {}
4063 }
4064 #[doc = "This status bit is set to one when the temperature sensor low interrupt asserts for low temperature"]
4065 pub mod IRQ_TEMPLOW {
4066 pub const offset: u32 = 28;
4067 pub const mask: u32 = 0x01 << offset;
4068 pub mod R {}
4069 pub mod W {}
4070 pub mod RW {}
4071 }
4072 #[doc = "This status bit is set to one when the temperature sensor high interrupt asserts for high temperature"]
4073 pub mod IRQ_TEMPHIGH {
4074 pub const offset: u32 = 29;
4075 pub const mask: u32 = 0x01 << offset;
4076 pub mod R {}
4077 pub mod W {}
4078 pub mod RW {}
4079 }
4080 #[doc = "This status bit is set to one when when any of the analog regulator brownout interrupts assert"]
4081 pub mod IRQ_ANA_BO {
4082 pub const offset: u32 = 30;
4083 pub const mask: u32 = 0x01 << offset;
4084 pub mod R {}
4085 pub mod W {}
4086 pub mod RW {}
4087 }
4088 #[doc = "This status bit is set to one when when any of the digital regulator brownout interrupts assert"]
4089 pub mod IRQ_DIG_BO {
4090 pub const offset: u32 = 31;
4091 pub const mask: u32 = 0x01 << offset;
4092 pub mod R {}
4093 pub mod W {}
4094 pub mod RW {}
4095 }
4096}
4097#[doc = "Miscellaneous Register 2"]
4098pub mod MISC2 {
4099 #[doc = "This field defines the brown out voltage offset for the CORE power domain"]
4100 pub mod REG0_BO_OFFSET {
4101 pub const offset: u32 = 0;
4102 pub const mask: u32 = 0x07 << offset;
4103 pub mod R {}
4104 pub mod W {}
4105 pub mod RW {
4106 #[doc = "Brownout offset = 0.100V"]
4107 pub const REG0_BO_OFFSET_4: u32 = 0x04;
4108 #[doc = "Brownout offset = 0.175V"]
4109 pub const REG0_BO_OFFSET_7: u32 = 0x07;
4110 }
4111 }
4112 #[doc = "Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU)"]
4113 pub mod REG0_BO_STATUS {
4114 pub const offset: u32 = 3;
4115 pub const mask: u32 = 0x01 << offset;
4116 pub mod R {}
4117 pub mod W {}
4118 pub mod RW {
4119 #[doc = "Brownout, supply is below target minus brownout offset."]
4120 pub const REG0_BO_STATUS_1: u32 = 0x01;
4121 }
4122 }
4123 #[doc = "Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)"]
4124 pub mod REG0_ENABLE_BO {
4125 pub const offset: u32 = 5;
4126 pub const mask: u32 = 0x01 << offset;
4127 pub mod R {}
4128 pub mod W {}
4129 pub mod RW {}
4130 }
4131 #[doc = "ARM supply Not related to CCM. See Power Management Unit (PMU)"]
4132 pub mod REG0_OK {
4133 pub const offset: u32 = 6;
4134 pub const mask: u32 = 0x01 << offset;
4135 pub mod R {}
4136 pub mod W {}
4137 pub mod RW {}
4138 }
4139 #[doc = "When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode"]
4140 pub mod PLL3_DISABLE {
4141 pub const offset: u32 = 7;
4142 pub const mask: u32 = 0x01 << offset;
4143 pub mod R {}
4144 pub mod W {}
4145 pub mod RW {
4146 #[doc = "PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode"]
4147 pub const PLL3_DISABLE_0: u32 = 0;
4148 #[doc = "PLL3 can be disabled when the SoC is not in any low power mode"]
4149 pub const PLL3_DISABLE_1: u32 = 0x01;
4150 }
4151 }
4152 #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
4153 pub mod REG1_BO_OFFSET {
4154 pub const offset: u32 = 8;
4155 pub const mask: u32 = 0x07 << offset;
4156 pub mod R {}
4157 pub mod W {}
4158 pub mod RW {
4159 #[doc = "Brownout offset = 0.100V"]
4160 pub const REG1_BO_OFFSET_4: u32 = 0x04;
4161 #[doc = "Brownout offset = 0.175V"]
4162 pub const REG1_BO_OFFSET_7: u32 = 0x07;
4163 }
4164 }
4165 #[doc = "Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU)"]
4166 pub mod REG1_BO_STATUS {
4167 pub const offset: u32 = 11;
4168 pub const mask: u32 = 0x01 << offset;
4169 pub mod R {}
4170 pub mod W {}
4171 pub mod RW {
4172 #[doc = "Brownout, supply is below target minus brownout offset."]
4173 pub const REG1_BO_STATUS_1: u32 = 0x01;
4174 }
4175 }
4176 #[doc = "Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)"]
4177 pub mod REG1_ENABLE_BO {
4178 pub const offset: u32 = 13;
4179 pub const mask: u32 = 0x01 << offset;
4180 pub mod R {}
4181 pub mod W {}
4182 pub mod RW {}
4183 }
4184 #[doc = "GPU/VPU supply Not related to CCM. See Power Management Unit (PMU)"]
4185 pub mod REG1_OK {
4186 pub const offset: u32 = 14;
4187 pub const mask: u32 = 0x01 << offset;
4188 pub mod R {}
4189 pub mod W {}
4190 pub mod RW {}
4191 }
4192 #[doc = "LSB of Post-divider for Audio PLL"]
4193 pub mod AUDIO_DIV_LSB {
4194 pub const offset: u32 = 15;
4195 pub const mask: u32 = 0x01 << offset;
4196 pub mod R {}
4197 pub mod W {}
4198 pub mod RW {
4199 #[doc = "divide by 1 (Default)"]
4200 pub const AUDIO_DIV_LSB_0: u32 = 0;
4201 #[doc = "divide by 2"]
4202 pub const AUDIO_DIV_LSB_1: u32 = 0x01;
4203 }
4204 }
4205 #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
4206 pub mod REG2_BO_OFFSET {
4207 pub const offset: u32 = 16;
4208 pub const mask: u32 = 0x07 << offset;
4209 pub mod R {}
4210 pub mod W {}
4211 pub mod RW {
4212 #[doc = "Brownout offset = 0.100V"]
4213 pub const REG2_BO_OFFSET_4: u32 = 0x04;
4214 #[doc = "Brownout offset = 0.175V"]
4215 pub const REG2_BO_OFFSET_7: u32 = 0x07;
4216 }
4217 }
4218 #[doc = "Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU)"]
4219 pub mod REG2_BO_STATUS {
4220 pub const offset: u32 = 19;
4221 pub const mask: u32 = 0x01 << offset;
4222 pub mod R {}
4223 pub mod W {}
4224 pub mod RW {}
4225 }
4226 #[doc = "Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)"]
4227 pub mod REG2_ENABLE_BO {
4228 pub const offset: u32 = 21;
4229 pub const mask: u32 = 0x01 << offset;
4230 pub mod R {}
4231 pub mod W {}
4232 pub mod RW {}
4233 }
4234 #[doc = "Signals that the voltage is above the brownout level for the SOC supply"]
4235 pub mod REG2_OK {
4236 pub const offset: u32 = 22;
4237 pub const mask: u32 = 0x01 << offset;
4238 pub mod R {}
4239 pub mod W {}
4240 pub mod RW {}
4241 }
4242 #[doc = "MSB of Post-divider for Audio PLL"]
4243 pub mod AUDIO_DIV_MSB {
4244 pub const offset: u32 = 23;
4245 pub const mask: u32 = 0x01 << offset;
4246 pub mod R {}
4247 pub mod W {}
4248 pub mod RW {
4249 #[doc = "divide by 1 (Default)"]
4250 pub const AUDIO_DIV_MSB_0: u32 = 0;
4251 #[doc = "divide by 2"]
4252 pub const AUDIO_DIV_MSB_1: u32 = 0x01;
4253 }
4254 }
4255 #[doc = "Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)"]
4256 pub mod REG0_STEP_TIME {
4257 pub const offset: u32 = 24;
4258 pub const mask: u32 = 0x03 << offset;
4259 pub mod R {}
4260 pub mod W {}
4261 pub mod RW {
4262 #[doc = "64"]
4263 pub const _64_CLOCKS: u32 = 0;
4264 #[doc = "128"]
4265 pub const _128_CLOCKS: u32 = 0x01;
4266 #[doc = "256"]
4267 pub const _256_CLOCKS: u32 = 0x02;
4268 #[doc = "512"]
4269 pub const _512_CLOCKS: u32 = 0x03;
4270 }
4271 }
4272 #[doc = "Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)"]
4273 pub mod REG1_STEP_TIME {
4274 pub const offset: u32 = 26;
4275 pub const mask: u32 = 0x03 << offset;
4276 pub mod R {}
4277 pub mod W {}
4278 pub mod RW {
4279 #[doc = "64"]
4280 pub const _64_CLOCKS: u32 = 0;
4281 #[doc = "128"]
4282 pub const _128_CLOCKS: u32 = 0x01;
4283 #[doc = "256"]
4284 pub const _256_CLOCKS: u32 = 0x02;
4285 #[doc = "512"]
4286 pub const _512_CLOCKS: u32 = 0x03;
4287 }
4288 }
4289 #[doc = "Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)"]
4290 pub mod REG2_STEP_TIME {
4291 pub const offset: u32 = 28;
4292 pub const mask: u32 = 0x03 << offset;
4293 pub mod R {}
4294 pub mod W {}
4295 pub mod RW {
4296 #[doc = "64"]
4297 pub const _64_CLOCKS: u32 = 0;
4298 #[doc = "128"]
4299 pub const _128_CLOCKS: u32 = 0x01;
4300 #[doc = "256"]
4301 pub const _256_CLOCKS: u32 = 0x02;
4302 #[doc = "512"]
4303 pub const _512_CLOCKS: u32 = 0x03;
4304 }
4305 }
4306 #[doc = "Post-divider for video"]
4307 pub mod VIDEO_DIV {
4308 pub const offset: u32 = 30;
4309 pub const mask: u32 = 0x03 << offset;
4310 pub mod R {}
4311 pub mod W {}
4312 pub mod RW {
4313 #[doc = "divide by 1 (Default)"]
4314 pub const VIDEO_DIV_0: u32 = 0;
4315 #[doc = "divide by 2"]
4316 pub const VIDEO_DIV_1: u32 = 0x01;
4317 #[doc = "divide by 1"]
4318 pub const VIDEO_DIV_2: u32 = 0x02;
4319 #[doc = "divide by 4"]
4320 pub const VIDEO_DIV_3: u32 = 0x03;
4321 }
4322 }
4323}
4324#[doc = "Miscellaneous Register 2"]
4325pub mod MISC2_SET {
4326 #[doc = "This field defines the brown out voltage offset for the CORE power domain"]
4327 pub mod REG0_BO_OFFSET {
4328 pub const offset: u32 = 0;
4329 pub const mask: u32 = 0x07 << offset;
4330 pub mod R {}
4331 pub mod W {}
4332 pub mod RW {
4333 #[doc = "Brownout offset = 0.100V"]
4334 pub const REG0_BO_OFFSET_4: u32 = 0x04;
4335 #[doc = "Brownout offset = 0.175V"]
4336 pub const REG0_BO_OFFSET_7: u32 = 0x07;
4337 }
4338 }
4339 #[doc = "Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU)"]
4340 pub mod REG0_BO_STATUS {
4341 pub const offset: u32 = 3;
4342 pub const mask: u32 = 0x01 << offset;
4343 pub mod R {}
4344 pub mod W {}
4345 pub mod RW {
4346 #[doc = "Brownout, supply is below target minus brownout offset."]
4347 pub const REG0_BO_STATUS_1: u32 = 0x01;
4348 }
4349 }
4350 #[doc = "Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)"]
4351 pub mod REG0_ENABLE_BO {
4352 pub const offset: u32 = 5;
4353 pub const mask: u32 = 0x01 << offset;
4354 pub mod R {}
4355 pub mod W {}
4356 pub mod RW {}
4357 }
4358 #[doc = "ARM supply Not related to CCM. See Power Management Unit (PMU)"]
4359 pub mod REG0_OK {
4360 pub const offset: u32 = 6;
4361 pub const mask: u32 = 0x01 << offset;
4362 pub mod R {}
4363 pub mod W {}
4364 pub mod RW {}
4365 }
4366 #[doc = "When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode"]
4367 pub mod PLL3_DISABLE {
4368 pub const offset: u32 = 7;
4369 pub const mask: u32 = 0x01 << offset;
4370 pub mod R {}
4371 pub mod W {}
4372 pub mod RW {
4373 #[doc = "PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode"]
4374 pub const PLL3_DISABLE_0: u32 = 0;
4375 #[doc = "PLL3 can be disabled when the SoC is not in any low power mode"]
4376 pub const PLL3_DISABLE_1: u32 = 0x01;
4377 }
4378 }
4379 #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
4380 pub mod REG1_BO_OFFSET {
4381 pub const offset: u32 = 8;
4382 pub const mask: u32 = 0x07 << offset;
4383 pub mod R {}
4384 pub mod W {}
4385 pub mod RW {
4386 #[doc = "Brownout offset = 0.100V"]
4387 pub const REG1_BO_OFFSET_4: u32 = 0x04;
4388 #[doc = "Brownout offset = 0.175V"]
4389 pub const REG1_BO_OFFSET_7: u32 = 0x07;
4390 }
4391 }
4392 #[doc = "Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU)"]
4393 pub mod REG1_BO_STATUS {
4394 pub const offset: u32 = 11;
4395 pub const mask: u32 = 0x01 << offset;
4396 pub mod R {}
4397 pub mod W {}
4398 pub mod RW {
4399 #[doc = "Brownout, supply is below target minus brownout offset."]
4400 pub const REG1_BO_STATUS_1: u32 = 0x01;
4401 }
4402 }
4403 #[doc = "Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)"]
4404 pub mod REG1_ENABLE_BO {
4405 pub const offset: u32 = 13;
4406 pub const mask: u32 = 0x01 << offset;
4407 pub mod R {}
4408 pub mod W {}
4409 pub mod RW {}
4410 }
4411 #[doc = "GPU/VPU supply Not related to CCM. See Power Management Unit (PMU)"]
4412 pub mod REG1_OK {
4413 pub const offset: u32 = 14;
4414 pub const mask: u32 = 0x01 << offset;
4415 pub mod R {}
4416 pub mod W {}
4417 pub mod RW {}
4418 }
4419 #[doc = "LSB of Post-divider for Audio PLL"]
4420 pub mod AUDIO_DIV_LSB {
4421 pub const offset: u32 = 15;
4422 pub const mask: u32 = 0x01 << offset;
4423 pub mod R {}
4424 pub mod W {}
4425 pub mod RW {
4426 #[doc = "divide by 1 (Default)"]
4427 pub const AUDIO_DIV_LSB_0: u32 = 0;
4428 #[doc = "divide by 2"]
4429 pub const AUDIO_DIV_LSB_1: u32 = 0x01;
4430 }
4431 }
4432 #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
4433 pub mod REG2_BO_OFFSET {
4434 pub const offset: u32 = 16;
4435 pub const mask: u32 = 0x07 << offset;
4436 pub mod R {}
4437 pub mod W {}
4438 pub mod RW {
4439 #[doc = "Brownout offset = 0.100V"]
4440 pub const REG2_BO_OFFSET_4: u32 = 0x04;
4441 #[doc = "Brownout offset = 0.175V"]
4442 pub const REG2_BO_OFFSET_7: u32 = 0x07;
4443 }
4444 }
4445 #[doc = "Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU)"]
4446 pub mod REG2_BO_STATUS {
4447 pub const offset: u32 = 19;
4448 pub const mask: u32 = 0x01 << offset;
4449 pub mod R {}
4450 pub mod W {}
4451 pub mod RW {}
4452 }
4453 #[doc = "Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)"]
4454 pub mod REG2_ENABLE_BO {
4455 pub const offset: u32 = 21;
4456 pub const mask: u32 = 0x01 << offset;
4457 pub mod R {}
4458 pub mod W {}
4459 pub mod RW {}
4460 }
4461 #[doc = "Signals that the voltage is above the brownout level for the SOC supply"]
4462 pub mod REG2_OK {
4463 pub const offset: u32 = 22;
4464 pub const mask: u32 = 0x01 << offset;
4465 pub mod R {}
4466 pub mod W {}
4467 pub mod RW {}
4468 }
4469 #[doc = "MSB of Post-divider for Audio PLL"]
4470 pub mod AUDIO_DIV_MSB {
4471 pub const offset: u32 = 23;
4472 pub const mask: u32 = 0x01 << offset;
4473 pub mod R {}
4474 pub mod W {}
4475 pub mod RW {
4476 #[doc = "divide by 1 (Default)"]
4477 pub const AUDIO_DIV_MSB_0: u32 = 0;
4478 #[doc = "divide by 2"]
4479 pub const AUDIO_DIV_MSB_1: u32 = 0x01;
4480 }
4481 }
4482 #[doc = "Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)"]
4483 pub mod REG0_STEP_TIME {
4484 pub const offset: u32 = 24;
4485 pub const mask: u32 = 0x03 << offset;
4486 pub mod R {}
4487 pub mod W {}
4488 pub mod RW {
4489 #[doc = "64"]
4490 pub const _64_CLOCKS: u32 = 0;
4491 #[doc = "128"]
4492 pub const _128_CLOCKS: u32 = 0x01;
4493 #[doc = "256"]
4494 pub const _256_CLOCKS: u32 = 0x02;
4495 #[doc = "512"]
4496 pub const _512_CLOCKS: u32 = 0x03;
4497 }
4498 }
4499 #[doc = "Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)"]
4500 pub mod REG1_STEP_TIME {
4501 pub const offset: u32 = 26;
4502 pub const mask: u32 = 0x03 << offset;
4503 pub mod R {}
4504 pub mod W {}
4505 pub mod RW {
4506 #[doc = "64"]
4507 pub const _64_CLOCKS: u32 = 0;
4508 #[doc = "128"]
4509 pub const _128_CLOCKS: u32 = 0x01;
4510 #[doc = "256"]
4511 pub const _256_CLOCKS: u32 = 0x02;
4512 #[doc = "512"]
4513 pub const _512_CLOCKS: u32 = 0x03;
4514 }
4515 }
4516 #[doc = "Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)"]
4517 pub mod REG2_STEP_TIME {
4518 pub const offset: u32 = 28;
4519 pub const mask: u32 = 0x03 << offset;
4520 pub mod R {}
4521 pub mod W {}
4522 pub mod RW {
4523 #[doc = "64"]
4524 pub const _64_CLOCKS: u32 = 0;
4525 #[doc = "128"]
4526 pub const _128_CLOCKS: u32 = 0x01;
4527 #[doc = "256"]
4528 pub const _256_CLOCKS: u32 = 0x02;
4529 #[doc = "512"]
4530 pub const _512_CLOCKS: u32 = 0x03;
4531 }
4532 }
4533 #[doc = "Post-divider for video"]
4534 pub mod VIDEO_DIV {
4535 pub const offset: u32 = 30;
4536 pub const mask: u32 = 0x03 << offset;
4537 pub mod R {}
4538 pub mod W {}
4539 pub mod RW {
4540 #[doc = "divide by 1 (Default)"]
4541 pub const VIDEO_DIV_0: u32 = 0;
4542 #[doc = "divide by 2"]
4543 pub const VIDEO_DIV_1: u32 = 0x01;
4544 #[doc = "divide by 1"]
4545 pub const VIDEO_DIV_2: u32 = 0x02;
4546 #[doc = "divide by 4"]
4547 pub const VIDEO_DIV_3: u32 = 0x03;
4548 }
4549 }
4550}
4551#[doc = "Miscellaneous Register 2"]
4552pub mod MISC2_CLR {
4553 #[doc = "This field defines the brown out voltage offset for the CORE power domain"]
4554 pub mod REG0_BO_OFFSET {
4555 pub const offset: u32 = 0;
4556 pub const mask: u32 = 0x07 << offset;
4557 pub mod R {}
4558 pub mod W {}
4559 pub mod RW {
4560 #[doc = "Brownout offset = 0.100V"]
4561 pub const REG0_BO_OFFSET_4: u32 = 0x04;
4562 #[doc = "Brownout offset = 0.175V"]
4563 pub const REG0_BO_OFFSET_7: u32 = 0x07;
4564 }
4565 }
4566 #[doc = "Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU)"]
4567 pub mod REG0_BO_STATUS {
4568 pub const offset: u32 = 3;
4569 pub const mask: u32 = 0x01 << offset;
4570 pub mod R {}
4571 pub mod W {}
4572 pub mod RW {
4573 #[doc = "Brownout, supply is below target minus brownout offset."]
4574 pub const REG0_BO_STATUS_1: u32 = 0x01;
4575 }
4576 }
4577 #[doc = "Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)"]
4578 pub mod REG0_ENABLE_BO {
4579 pub const offset: u32 = 5;
4580 pub const mask: u32 = 0x01 << offset;
4581 pub mod R {}
4582 pub mod W {}
4583 pub mod RW {}
4584 }
4585 #[doc = "ARM supply Not related to CCM. See Power Management Unit (PMU)"]
4586 pub mod REG0_OK {
4587 pub const offset: u32 = 6;
4588 pub const mask: u32 = 0x01 << offset;
4589 pub mod R {}
4590 pub mod W {}
4591 pub mod RW {}
4592 }
4593 #[doc = "When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode"]
4594 pub mod PLL3_DISABLE {
4595 pub const offset: u32 = 7;
4596 pub const mask: u32 = 0x01 << offset;
4597 pub mod R {}
4598 pub mod W {}
4599 pub mod RW {
4600 #[doc = "PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode"]
4601 pub const PLL3_DISABLE_0: u32 = 0;
4602 #[doc = "PLL3 can be disabled when the SoC is not in any low power mode"]
4603 pub const PLL3_DISABLE_1: u32 = 0x01;
4604 }
4605 }
4606 #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
4607 pub mod REG1_BO_OFFSET {
4608 pub const offset: u32 = 8;
4609 pub const mask: u32 = 0x07 << offset;
4610 pub mod R {}
4611 pub mod W {}
4612 pub mod RW {
4613 #[doc = "Brownout offset = 0.100V"]
4614 pub const REG1_BO_OFFSET_4: u32 = 0x04;
4615 #[doc = "Brownout offset = 0.175V"]
4616 pub const REG1_BO_OFFSET_7: u32 = 0x07;
4617 }
4618 }
4619 #[doc = "Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU)"]
4620 pub mod REG1_BO_STATUS {
4621 pub const offset: u32 = 11;
4622 pub const mask: u32 = 0x01 << offset;
4623 pub mod R {}
4624 pub mod W {}
4625 pub mod RW {
4626 #[doc = "Brownout, supply is below target minus brownout offset."]
4627 pub const REG1_BO_STATUS_1: u32 = 0x01;
4628 }
4629 }
4630 #[doc = "Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)"]
4631 pub mod REG1_ENABLE_BO {
4632 pub const offset: u32 = 13;
4633 pub const mask: u32 = 0x01 << offset;
4634 pub mod R {}
4635 pub mod W {}
4636 pub mod RW {}
4637 }
4638 #[doc = "GPU/VPU supply Not related to CCM. See Power Management Unit (PMU)"]
4639 pub mod REG1_OK {
4640 pub const offset: u32 = 14;
4641 pub const mask: u32 = 0x01 << offset;
4642 pub mod R {}
4643 pub mod W {}
4644 pub mod RW {}
4645 }
4646 #[doc = "LSB of Post-divider for Audio PLL"]
4647 pub mod AUDIO_DIV_LSB {
4648 pub const offset: u32 = 15;
4649 pub const mask: u32 = 0x01 << offset;
4650 pub mod R {}
4651 pub mod W {}
4652 pub mod RW {
4653 #[doc = "divide by 1 (Default)"]
4654 pub const AUDIO_DIV_LSB_0: u32 = 0;
4655 #[doc = "divide by 2"]
4656 pub const AUDIO_DIV_LSB_1: u32 = 0x01;
4657 }
4658 }
4659 #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
4660 pub mod REG2_BO_OFFSET {
4661 pub const offset: u32 = 16;
4662 pub const mask: u32 = 0x07 << offset;
4663 pub mod R {}
4664 pub mod W {}
4665 pub mod RW {
4666 #[doc = "Brownout offset = 0.100V"]
4667 pub const REG2_BO_OFFSET_4: u32 = 0x04;
4668 #[doc = "Brownout offset = 0.175V"]
4669 pub const REG2_BO_OFFSET_7: u32 = 0x07;
4670 }
4671 }
4672 #[doc = "Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU)"]
4673 pub mod REG2_BO_STATUS {
4674 pub const offset: u32 = 19;
4675 pub const mask: u32 = 0x01 << offset;
4676 pub mod R {}
4677 pub mod W {}
4678 pub mod RW {}
4679 }
4680 #[doc = "Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)"]
4681 pub mod REG2_ENABLE_BO {
4682 pub const offset: u32 = 21;
4683 pub const mask: u32 = 0x01 << offset;
4684 pub mod R {}
4685 pub mod W {}
4686 pub mod RW {}
4687 }
4688 #[doc = "Signals that the voltage is above the brownout level for the SOC supply"]
4689 pub mod REG2_OK {
4690 pub const offset: u32 = 22;
4691 pub const mask: u32 = 0x01 << offset;
4692 pub mod R {}
4693 pub mod W {}
4694 pub mod RW {}
4695 }
4696 #[doc = "MSB of Post-divider for Audio PLL"]
4697 pub mod AUDIO_DIV_MSB {
4698 pub const offset: u32 = 23;
4699 pub const mask: u32 = 0x01 << offset;
4700 pub mod R {}
4701 pub mod W {}
4702 pub mod RW {
4703 #[doc = "divide by 1 (Default)"]
4704 pub const AUDIO_DIV_MSB_0: u32 = 0;
4705 #[doc = "divide by 2"]
4706 pub const AUDIO_DIV_MSB_1: u32 = 0x01;
4707 }
4708 }
4709 #[doc = "Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)"]
4710 pub mod REG0_STEP_TIME {
4711 pub const offset: u32 = 24;
4712 pub const mask: u32 = 0x03 << offset;
4713 pub mod R {}
4714 pub mod W {}
4715 pub mod RW {
4716 #[doc = "64"]
4717 pub const _64_CLOCKS: u32 = 0;
4718 #[doc = "128"]
4719 pub const _128_CLOCKS: u32 = 0x01;
4720 #[doc = "256"]
4721 pub const _256_CLOCKS: u32 = 0x02;
4722 #[doc = "512"]
4723 pub const _512_CLOCKS: u32 = 0x03;
4724 }
4725 }
4726 #[doc = "Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)"]
4727 pub mod REG1_STEP_TIME {
4728 pub const offset: u32 = 26;
4729 pub const mask: u32 = 0x03 << offset;
4730 pub mod R {}
4731 pub mod W {}
4732 pub mod RW {
4733 #[doc = "64"]
4734 pub const _64_CLOCKS: u32 = 0;
4735 #[doc = "128"]
4736 pub const _128_CLOCKS: u32 = 0x01;
4737 #[doc = "256"]
4738 pub const _256_CLOCKS: u32 = 0x02;
4739 #[doc = "512"]
4740 pub const _512_CLOCKS: u32 = 0x03;
4741 }
4742 }
4743 #[doc = "Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)"]
4744 pub mod REG2_STEP_TIME {
4745 pub const offset: u32 = 28;
4746 pub const mask: u32 = 0x03 << offset;
4747 pub mod R {}
4748 pub mod W {}
4749 pub mod RW {
4750 #[doc = "64"]
4751 pub const _64_CLOCKS: u32 = 0;
4752 #[doc = "128"]
4753 pub const _128_CLOCKS: u32 = 0x01;
4754 #[doc = "256"]
4755 pub const _256_CLOCKS: u32 = 0x02;
4756 #[doc = "512"]
4757 pub const _512_CLOCKS: u32 = 0x03;
4758 }
4759 }
4760 #[doc = "Post-divider for video"]
4761 pub mod VIDEO_DIV {
4762 pub const offset: u32 = 30;
4763 pub const mask: u32 = 0x03 << offset;
4764 pub mod R {}
4765 pub mod W {}
4766 pub mod RW {
4767 #[doc = "divide by 1 (Default)"]
4768 pub const VIDEO_DIV_0: u32 = 0;
4769 #[doc = "divide by 2"]
4770 pub const VIDEO_DIV_1: u32 = 0x01;
4771 #[doc = "divide by 1"]
4772 pub const VIDEO_DIV_2: u32 = 0x02;
4773 #[doc = "divide by 4"]
4774 pub const VIDEO_DIV_3: u32 = 0x03;
4775 }
4776 }
4777}
4778#[doc = "Miscellaneous Register 2"]
4779pub mod MISC2_TOG {
4780 #[doc = "This field defines the brown out voltage offset for the CORE power domain"]
4781 pub mod REG0_BO_OFFSET {
4782 pub const offset: u32 = 0;
4783 pub const mask: u32 = 0x07 << offset;
4784 pub mod R {}
4785 pub mod W {}
4786 pub mod RW {
4787 #[doc = "Brownout offset = 0.100V"]
4788 pub const REG0_BO_OFFSET_4: u32 = 0x04;
4789 #[doc = "Brownout offset = 0.175V"]
4790 pub const REG0_BO_OFFSET_7: u32 = 0x07;
4791 }
4792 }
4793 #[doc = "Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU)"]
4794 pub mod REG0_BO_STATUS {
4795 pub const offset: u32 = 3;
4796 pub const mask: u32 = 0x01 << offset;
4797 pub mod R {}
4798 pub mod W {}
4799 pub mod RW {
4800 #[doc = "Brownout, supply is below target minus brownout offset."]
4801 pub const REG0_BO_STATUS_1: u32 = 0x01;
4802 }
4803 }
4804 #[doc = "Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)"]
4805 pub mod REG0_ENABLE_BO {
4806 pub const offset: u32 = 5;
4807 pub const mask: u32 = 0x01 << offset;
4808 pub mod R {}
4809 pub mod W {}
4810 pub mod RW {}
4811 }
4812 #[doc = "ARM supply Not related to CCM. See Power Management Unit (PMU)"]
4813 pub mod REG0_OK {
4814 pub const offset: u32 = 6;
4815 pub const mask: u32 = 0x01 << offset;
4816 pub mod R {}
4817 pub mod W {}
4818 pub mod RW {}
4819 }
4820 #[doc = "When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode"]
4821 pub mod PLL3_DISABLE {
4822 pub const offset: u32 = 7;
4823 pub const mask: u32 = 0x01 << offset;
4824 pub mod R {}
4825 pub mod W {}
4826 pub mod RW {
4827 #[doc = "PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode"]
4828 pub const PLL3_DISABLE_0: u32 = 0;
4829 #[doc = "PLL3 can be disabled when the SoC is not in any low power mode"]
4830 pub const PLL3_DISABLE_1: u32 = 0x01;
4831 }
4832 }
4833 #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
4834 pub mod REG1_BO_OFFSET {
4835 pub const offset: u32 = 8;
4836 pub const mask: u32 = 0x07 << offset;
4837 pub mod R {}
4838 pub mod W {}
4839 pub mod RW {
4840 #[doc = "Brownout offset = 0.100V"]
4841 pub const REG1_BO_OFFSET_4: u32 = 0x04;
4842 #[doc = "Brownout offset = 0.175V"]
4843 pub const REG1_BO_OFFSET_7: u32 = 0x07;
4844 }
4845 }
4846 #[doc = "Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU)"]
4847 pub mod REG1_BO_STATUS {
4848 pub const offset: u32 = 11;
4849 pub const mask: u32 = 0x01 << offset;
4850 pub mod R {}
4851 pub mod W {}
4852 pub mod RW {
4853 #[doc = "Brownout, supply is below target minus brownout offset."]
4854 pub const REG1_BO_STATUS_1: u32 = 0x01;
4855 }
4856 }
4857 #[doc = "Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)"]
4858 pub mod REG1_ENABLE_BO {
4859 pub const offset: u32 = 13;
4860 pub const mask: u32 = 0x01 << offset;
4861 pub mod R {}
4862 pub mod W {}
4863 pub mod RW {}
4864 }
4865 #[doc = "GPU/VPU supply Not related to CCM. See Power Management Unit (PMU)"]
4866 pub mod REG1_OK {
4867 pub const offset: u32 = 14;
4868 pub const mask: u32 = 0x01 << offset;
4869 pub mod R {}
4870 pub mod W {}
4871 pub mod RW {}
4872 }
4873 #[doc = "LSB of Post-divider for Audio PLL"]
4874 pub mod AUDIO_DIV_LSB {
4875 pub const offset: u32 = 15;
4876 pub const mask: u32 = 0x01 << offset;
4877 pub mod R {}
4878 pub mod W {}
4879 pub mod RW {
4880 #[doc = "divide by 1 (Default)"]
4881 pub const AUDIO_DIV_LSB_0: u32 = 0;
4882 #[doc = "divide by 2"]
4883 pub const AUDIO_DIV_LSB_1: u32 = 0x01;
4884 }
4885 }
4886 #[doc = "This field defines the brown out voltage offset for the xPU power domain"]
4887 pub mod REG2_BO_OFFSET {
4888 pub const offset: u32 = 16;
4889 pub const mask: u32 = 0x07 << offset;
4890 pub mod R {}
4891 pub mod W {}
4892 pub mod RW {
4893 #[doc = "Brownout offset = 0.100V"]
4894 pub const REG2_BO_OFFSET_4: u32 = 0x04;
4895 #[doc = "Brownout offset = 0.175V"]
4896 pub const REG2_BO_OFFSET_7: u32 = 0x07;
4897 }
4898 }
4899 #[doc = "Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU)"]
4900 pub mod REG2_BO_STATUS {
4901 pub const offset: u32 = 19;
4902 pub const mask: u32 = 0x01 << offset;
4903 pub mod R {}
4904 pub mod W {}
4905 pub mod RW {}
4906 }
4907 #[doc = "Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)"]
4908 pub mod REG2_ENABLE_BO {
4909 pub const offset: u32 = 21;
4910 pub const mask: u32 = 0x01 << offset;
4911 pub mod R {}
4912 pub mod W {}
4913 pub mod RW {}
4914 }
4915 #[doc = "Signals that the voltage is above the brownout level for the SOC supply"]
4916 pub mod REG2_OK {
4917 pub const offset: u32 = 22;
4918 pub const mask: u32 = 0x01 << offset;
4919 pub mod R {}
4920 pub mod W {}
4921 pub mod RW {}
4922 }
4923 #[doc = "MSB of Post-divider for Audio PLL"]
4924 pub mod AUDIO_DIV_MSB {
4925 pub const offset: u32 = 23;
4926 pub const mask: u32 = 0x01 << offset;
4927 pub mod R {}
4928 pub mod W {}
4929 pub mod RW {
4930 #[doc = "divide by 1 (Default)"]
4931 pub const AUDIO_DIV_MSB_0: u32 = 0;
4932 #[doc = "divide by 2"]
4933 pub const AUDIO_DIV_MSB_1: u32 = 0x01;
4934 }
4935 }
4936 #[doc = "Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)"]
4937 pub mod REG0_STEP_TIME {
4938 pub const offset: u32 = 24;
4939 pub const mask: u32 = 0x03 << offset;
4940 pub mod R {}
4941 pub mod W {}
4942 pub mod RW {
4943 #[doc = "64"]
4944 pub const _64_CLOCKS: u32 = 0;
4945 #[doc = "128"]
4946 pub const _128_CLOCKS: u32 = 0x01;
4947 #[doc = "256"]
4948 pub const _256_CLOCKS: u32 = 0x02;
4949 #[doc = "512"]
4950 pub const _512_CLOCKS: u32 = 0x03;
4951 }
4952 }
4953 #[doc = "Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)"]
4954 pub mod REG1_STEP_TIME {
4955 pub const offset: u32 = 26;
4956 pub const mask: u32 = 0x03 << offset;
4957 pub mod R {}
4958 pub mod W {}
4959 pub mod RW {
4960 #[doc = "64"]
4961 pub const _64_CLOCKS: u32 = 0;
4962 #[doc = "128"]
4963 pub const _128_CLOCKS: u32 = 0x01;
4964 #[doc = "256"]
4965 pub const _256_CLOCKS: u32 = 0x02;
4966 #[doc = "512"]
4967 pub const _512_CLOCKS: u32 = 0x03;
4968 }
4969 }
4970 #[doc = "Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)"]
4971 pub mod REG2_STEP_TIME {
4972 pub const offset: u32 = 28;
4973 pub const mask: u32 = 0x03 << offset;
4974 pub mod R {}
4975 pub mod W {}
4976 pub mod RW {
4977 #[doc = "64"]
4978 pub const _64_CLOCKS: u32 = 0;
4979 #[doc = "128"]
4980 pub const _128_CLOCKS: u32 = 0x01;
4981 #[doc = "256"]
4982 pub const _256_CLOCKS: u32 = 0x02;
4983 #[doc = "512"]
4984 pub const _512_CLOCKS: u32 = 0x03;
4985 }
4986 }
4987 #[doc = "Post-divider for video"]
4988 pub mod VIDEO_DIV {
4989 pub const offset: u32 = 30;
4990 pub const mask: u32 = 0x03 << offset;
4991 pub mod R {}
4992 pub mod W {}
4993 pub mod RW {
4994 #[doc = "divide by 1 (Default)"]
4995 pub const VIDEO_DIV_0: u32 = 0;
4996 #[doc = "divide by 2"]
4997 pub const VIDEO_DIV_1: u32 = 0x01;
4998 #[doc = "divide by 1"]
4999 pub const VIDEO_DIV_2: u32 = 0x02;
5000 #[doc = "divide by 4"]
5001 pub const VIDEO_DIV_3: u32 = 0x03;
5002 }
5003 }
5004}