imxrt_ral/blocks/imxrt1061/
enet.rs1#[doc = "Ethernet MAC-NET Core"]
2#[repr(C)]
3pub struct RegisterBlock {
4 _reserved0: [u8; 0x04],
5 #[doc = "Interrupt Event Register"]
6 pub EIR: crate::RWRegister<u32>,
7 #[doc = "Interrupt Mask Register"]
8 pub EIMR: crate::RWRegister<u32>,
9 _reserved1: [u8; 0x04],
10 #[doc = "Receive Descriptor Active Register"]
11 pub RDAR: crate::RWRegister<u32>,
12 #[doc = "Transmit Descriptor Active Register"]
13 pub TDAR: crate::RWRegister<u32>,
14 _reserved2: [u8; 0x0c],
15 #[doc = "Ethernet Control Register"]
16 pub ECR: crate::RWRegister<u32>,
17 _reserved3: [u8; 0x18],
18 #[doc = "MII Management Frame Register"]
19 pub MMFR: crate::RWRegister<u32>,
20 #[doc = "MII Speed Control Register"]
21 pub MSCR: crate::RWRegister<u32>,
22 _reserved4: [u8; 0x1c],
23 #[doc = "MIB Control Register"]
24 pub MIBC: crate::RWRegister<u32>,
25 _reserved5: [u8; 0x1c],
26 #[doc = "Receive Control Register"]
27 pub RCR: crate::RWRegister<u32>,
28 _reserved6: [u8; 0x3c],
29 #[doc = "Transmit Control Register"]
30 pub TCR: crate::RWRegister<u32>,
31 _reserved7: [u8; 0x1c],
32 #[doc = "Physical Address Lower Register"]
33 pub PALR: crate::RWRegister<u32>,
34 #[doc = "Physical Address Upper Register"]
35 pub PAUR: crate::RWRegister<u32>,
36 #[doc = "Opcode/Pause Duration Register"]
37 pub OPD: crate::RWRegister<u32>,
38 #[doc = "Transmit Interrupt Coalescing Register"]
39 pub TXIC: crate::RWRegister<u32>,
40 _reserved8: [u8; 0x0c],
41 #[doc = "Receive Interrupt Coalescing Register"]
42 pub RXIC: crate::RWRegister<u32>,
43 _reserved9: [u8; 0x14],
44 #[doc = "Descriptor Individual Upper Address Register"]
45 pub IAUR: crate::RWRegister<u32>,
46 #[doc = "Descriptor Individual Lower Address Register"]
47 pub IALR: crate::RWRegister<u32>,
48 #[doc = "Descriptor Group Upper Address Register"]
49 pub GAUR: crate::RWRegister<u32>,
50 #[doc = "Descriptor Group Lower Address Register"]
51 pub GALR: crate::RWRegister<u32>,
52 _reserved10: [u8; 0x1c],
53 #[doc = "Transmit FIFO Watermark Register"]
54 pub TFWR: crate::RWRegister<u32>,
55 _reserved11: [u8; 0x38],
56 #[doc = "Receive Descriptor Ring Start Register"]
57 pub RDSR: crate::RWRegister<u32>,
58 #[doc = "Transmit Buffer Descriptor Ring Start Register"]
59 pub TDSR: crate::RWRegister<u32>,
60 #[doc = "Maximum Receive Buffer Size Register"]
61 pub MRBR: crate::RWRegister<u32>,
62 _reserved12: [u8; 0x04],
63 #[doc = "Receive FIFO Section Full Threshold"]
64 pub RSFL: crate::RWRegister<u32>,
65 #[doc = "Receive FIFO Section Empty Threshold"]
66 pub RSEM: crate::RWRegister<u32>,
67 #[doc = "Receive FIFO Almost Empty Threshold"]
68 pub RAEM: crate::RWRegister<u32>,
69 #[doc = "Receive FIFO Almost Full Threshold"]
70 pub RAFL: crate::RWRegister<u32>,
71 #[doc = "Transmit FIFO Section Empty Threshold"]
72 pub TSEM: crate::RWRegister<u32>,
73 #[doc = "Transmit FIFO Almost Empty Threshold"]
74 pub TAEM: crate::RWRegister<u32>,
75 #[doc = "Transmit FIFO Almost Full Threshold"]
76 pub TAFL: crate::RWRegister<u32>,
77 #[doc = "Transmit Inter-Packet Gap"]
78 pub TIPG: crate::RWRegister<u32>,
79 #[doc = "Frame Truncation Length"]
80 pub FTRL: crate::RWRegister<u32>,
81 _reserved13: [u8; 0x0c],
82 #[doc = "Transmit Accelerator Function Configuration"]
83 pub TACC: crate::RWRegister<u32>,
84 #[doc = "Receive Accelerator Function Configuration"]
85 pub RACC: crate::RWRegister<u32>,
86 _reserved14: [u8; 0x38],
87 #[doc = "Reserved Statistic Register"]
88 pub RMON_T_DROP: crate::RORegister<u32>,
89 #[doc = "Tx Packet Count Statistic Register"]
90 pub RMON_T_PACKETS: crate::RORegister<u32>,
91 #[doc = "Tx Broadcast Packets Statistic Register"]
92 pub RMON_T_BC_PKT: crate::RORegister<u32>,
93 #[doc = "Tx Multicast Packets Statistic Register"]
94 pub RMON_T_MC_PKT: crate::RORegister<u32>,
95 #[doc = "Tx Packets with CRC/Align Error Statistic Register"]
96 pub RMON_T_CRC_ALIGN: crate::RORegister<u32>,
97 #[doc = "Tx Packets Less Than Bytes and Good CRC Statistic Register"]
98 pub RMON_T_UNDERSIZE: crate::RORegister<u32>,
99 #[doc = "Tx Packets GT MAX_FL bytes and Good CRC Statistic Register"]
100 pub RMON_T_OVERSIZE: crate::RORegister<u32>,
101 #[doc = "Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register"]
102 pub RMON_T_FRAG: crate::RORegister<u32>,
103 #[doc = "Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register"]
104 pub RMON_T_JAB: crate::RORegister<u32>,
105 #[doc = "Tx Collision Count Statistic Register"]
106 pub RMON_T_COL: crate::RORegister<u32>,
107 #[doc = "Tx 64-Byte Packets Statistic Register"]
108 pub RMON_T_P64: crate::RORegister<u32>,
109 #[doc = "Tx 65- to 127-byte Packets Statistic Register"]
110 pub RMON_T_P65TO127: crate::RORegister<u32>,
111 #[doc = "Tx 128- to 255-byte Packets Statistic Register"]
112 pub RMON_T_P128TO255: crate::RORegister<u32>,
113 #[doc = "Tx 256- to 511-byte Packets Statistic Register"]
114 pub RMON_T_P256TO511: crate::RORegister<u32>,
115 #[doc = "Tx 512- to 1023-byte Packets Statistic Register"]
116 pub RMON_T_P512TO1023: crate::RORegister<u32>,
117 #[doc = "Tx 1024- to 2047-byte Packets Statistic Register"]
118 pub RMON_T_P1024TO2047: crate::RORegister<u32>,
119 #[doc = "Tx Packets Greater Than 2048 Bytes Statistic Register"]
120 pub RMON_T_P_GTE2048: crate::RORegister<u32>,
121 #[doc = "Tx Octets Statistic Register"]
122 pub RMON_T_OCTETS: crate::RORegister<u32>,
123 #[doc = "Reserved Statistic Register"]
124 pub IEEE_T_DROP: crate::RORegister<u32>,
125 #[doc = "Frames Transmitted OK Statistic Register"]
126 pub IEEE_T_FRAME_OK: crate::RORegister<u32>,
127 #[doc = "Frames Transmitted with Single Collision Statistic Register"]
128 pub IEEE_T_1COL: crate::RORegister<u32>,
129 #[doc = "Frames Transmitted with Multiple Collisions Statistic Register"]
130 pub IEEE_T_MCOL: crate::RORegister<u32>,
131 #[doc = "Frames Transmitted after Deferral Delay Statistic Register"]
132 pub IEEE_T_DEF: crate::RORegister<u32>,
133 #[doc = "Frames Transmitted with Late Collision Statistic Register"]
134 pub IEEE_T_LCOL: crate::RORegister<u32>,
135 #[doc = "Frames Transmitted with Excessive Collisions Statistic Register"]
136 pub IEEE_T_EXCOL: crate::RORegister<u32>,
137 #[doc = "Frames Transmitted with Tx FIFO Underrun Statistic Register"]
138 pub IEEE_T_MACERR: crate::RORegister<u32>,
139 #[doc = "Frames Transmitted with Carrier Sense Error Statistic Register"]
140 pub IEEE_T_CSERR: crate::RORegister<u32>,
141 #[doc = "Reserved Statistic Register"]
142 pub IEEE_T_SQE: crate::RORegister<u32>,
143 #[doc = "Flow Control Pause Frames Transmitted Statistic Register"]
144 pub IEEE_T_FDXFC: crate::RORegister<u32>,
145 #[doc = "Octet Count for Frames Transmitted w/o Error Statistic Register"]
146 pub IEEE_T_OCTETS_OK: crate::RORegister<u32>,
147 _reserved15: [u8; 0x0c],
148 #[doc = "Rx Packet Count Statistic Register"]
149 pub RMON_R_PACKETS: crate::RORegister<u32>,
150 #[doc = "Rx Broadcast Packets Statistic Register"]
151 pub RMON_R_BC_PKT: crate::RORegister<u32>,
152 #[doc = "Rx Multicast Packets Statistic Register"]
153 pub RMON_R_MC_PKT: crate::RORegister<u32>,
154 #[doc = "Rx Packets with CRC/Align Error Statistic Register"]
155 pub RMON_R_CRC_ALIGN: crate::RORegister<u32>,
156 #[doc = "Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register"]
157 pub RMON_R_UNDERSIZE: crate::RORegister<u32>,
158 #[doc = "Rx Packets Greater Than MAX_FL and Good CRC Statistic Register"]
159 pub RMON_R_OVERSIZE: crate::RORegister<u32>,
160 #[doc = "Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register"]
161 pub RMON_R_FRAG: crate::RORegister<u32>,
162 #[doc = "Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register"]
163 pub RMON_R_JAB: crate::RORegister<u32>,
164 #[doc = "Reserved Statistic Register"]
165 pub RMON_R_RESVD_0: crate::RORegister<u32>,
166 #[doc = "Rx 64-Byte Packets Statistic Register"]
167 pub RMON_R_P64: crate::RORegister<u32>,
168 #[doc = "Rx 65- to 127-Byte Packets Statistic Register"]
169 pub RMON_R_P65TO127: crate::RORegister<u32>,
170 #[doc = "Rx 128- to 255-Byte Packets Statistic Register"]
171 pub RMON_R_P128TO255: crate::RORegister<u32>,
172 #[doc = "Rx 256- to 511-Byte Packets Statistic Register"]
173 pub RMON_R_P256TO511: crate::RORegister<u32>,
174 #[doc = "Rx 512- to 1023-Byte Packets Statistic Register"]
175 pub RMON_R_P512TO1023: crate::RORegister<u32>,
176 #[doc = "Rx 1024- to 2047-Byte Packets Statistic Register"]
177 pub RMON_R_P1024TO2047: crate::RORegister<u32>,
178 #[doc = "Rx Packets Greater than 2048 Bytes Statistic Register"]
179 pub RMON_R_P_GTE2048: crate::RORegister<u32>,
180 #[doc = "Rx Octets Statistic Register"]
181 pub RMON_R_OCTETS: crate::RORegister<u32>,
182 #[doc = "Frames not Counted Correctly Statistic Register"]
183 pub IEEE_R_DROP: crate::RORegister<u32>,
184 #[doc = "Frames Received OK Statistic Register"]
185 pub IEEE_R_FRAME_OK: crate::RORegister<u32>,
186 #[doc = "Frames Received with CRC Error Statistic Register"]
187 pub IEEE_R_CRC: crate::RORegister<u32>,
188 #[doc = "Frames Received with Alignment Error Statistic Register"]
189 pub IEEE_R_ALIGN: crate::RORegister<u32>,
190 #[doc = "Receive FIFO Overflow Count Statistic Register"]
191 pub IEEE_R_MACERR: crate::RORegister<u32>,
192 #[doc = "Flow Control Pause Frames Received Statistic Register"]
193 pub IEEE_R_FDXFC: crate::RORegister<u32>,
194 #[doc = "Octet Count for Frames Received without Error Statistic Register"]
195 pub IEEE_R_OCTETS_OK: crate::RORegister<u32>,
196 _reserved16: [u8; 0x011c],
197 #[doc = "Adjustable Timer Control Register"]
198 pub ATCR: crate::RWRegister<u32>,
199 #[doc = "Timer Value Register"]
200 pub ATVR: crate::RWRegister<u32>,
201 #[doc = "Timer Offset Register"]
202 pub ATOFF: crate::RWRegister<u32>,
203 #[doc = "Timer Period Register"]
204 pub ATPER: crate::RWRegister<u32>,
205 #[doc = "Timer Correction Register"]
206 pub ATCOR: crate::RWRegister<u32>,
207 #[doc = "Time-Stamping Clock Period Register"]
208 pub ATINC: crate::RWRegister<u32>,
209 #[doc = "Timestamp of Last Transmitted Frame"]
210 pub ATSTMP: crate::RORegister<u32>,
211 _reserved17: [u8; 0x01e8],
212 #[doc = "Timer Global Status Register"]
213 pub TGSR: crate::RWRegister<u32>,
214 #[doc = "Timer Control Status Register"]
215 pub TCSR0: crate::RWRegister<u32>,
216 #[doc = "Timer Compare Capture Register"]
217 pub TCCR0: crate::RWRegister<u32>,
218 #[doc = "Timer Control Status Register"]
219 pub TCSR1: crate::RWRegister<u32>,
220 #[doc = "Timer Compare Capture Register"]
221 pub TCCR1: crate::RWRegister<u32>,
222 #[doc = "Timer Control Status Register"]
223 pub TCSR2: crate::RWRegister<u32>,
224 #[doc = "Timer Compare Capture Register"]
225 pub TCCR2: crate::RWRegister<u32>,
226 #[doc = "Timer Control Status Register"]
227 pub TCSR3: crate::RWRegister<u32>,
228 #[doc = "Timer Compare Capture Register"]
229 pub TCCR3: crate::RWRegister<u32>,
230}
231#[doc = "Interrupt Event Register"]
232pub mod EIR {
233 #[doc = "Timestamp Timer"]
234 pub mod TS_TIMER {
235 pub const offset: u32 = 15;
236 pub const mask: u32 = 0x01 << offset;
237 pub mod R {}
238 pub mod W {}
239 pub mod RW {}
240 }
241 #[doc = "Transmit Timestamp Available"]
242 pub mod TS_AVAIL {
243 pub const offset: u32 = 16;
244 pub const mask: u32 = 0x01 << offset;
245 pub mod R {}
246 pub mod W {}
247 pub mod RW {}
248 }
249 #[doc = "Node Wakeup Request Indication"]
250 pub mod WAKEUP {
251 pub const offset: u32 = 17;
252 pub const mask: u32 = 0x01 << offset;
253 pub mod R {}
254 pub mod W {}
255 pub mod RW {}
256 }
257 #[doc = "Payload Receive Error"]
258 pub mod PLR {
259 pub const offset: u32 = 18;
260 pub const mask: u32 = 0x01 << offset;
261 pub mod R {}
262 pub mod W {}
263 pub mod RW {}
264 }
265 #[doc = "Transmit FIFO Underrun"]
266 pub mod UN {
267 pub const offset: u32 = 19;
268 pub const mask: u32 = 0x01 << offset;
269 pub mod R {}
270 pub mod W {}
271 pub mod RW {}
272 }
273 #[doc = "Collision Retry Limit"]
274 pub mod RL {
275 pub const offset: u32 = 20;
276 pub const mask: u32 = 0x01 << offset;
277 pub mod R {}
278 pub mod W {}
279 pub mod RW {}
280 }
281 #[doc = "Late Collision"]
282 pub mod LC {
283 pub const offset: u32 = 21;
284 pub const mask: u32 = 0x01 << offset;
285 pub mod R {}
286 pub mod W {}
287 pub mod RW {}
288 }
289 #[doc = "Ethernet Bus Error"]
290 pub mod EBERR {
291 pub const offset: u32 = 22;
292 pub const mask: u32 = 0x01 << offset;
293 pub mod R {}
294 pub mod W {}
295 pub mod RW {}
296 }
297 #[doc = "MII Interrupt."]
298 pub mod MII {
299 pub const offset: u32 = 23;
300 pub const mask: u32 = 0x01 << offset;
301 pub mod R {}
302 pub mod W {}
303 pub mod RW {}
304 }
305 #[doc = "Receive Buffer Interrupt"]
306 pub mod RXB {
307 pub const offset: u32 = 24;
308 pub const mask: u32 = 0x01 << offset;
309 pub mod R {}
310 pub mod W {}
311 pub mod RW {}
312 }
313 #[doc = "Receive Frame Interrupt"]
314 pub mod RXF {
315 pub const offset: u32 = 25;
316 pub const mask: u32 = 0x01 << offset;
317 pub mod R {}
318 pub mod W {}
319 pub mod RW {}
320 }
321 #[doc = "Transmit Buffer Interrupt"]
322 pub mod TXB {
323 pub const offset: u32 = 26;
324 pub const mask: u32 = 0x01 << offset;
325 pub mod R {}
326 pub mod W {}
327 pub mod RW {}
328 }
329 #[doc = "Transmit Frame Interrupt"]
330 pub mod TXF {
331 pub const offset: u32 = 27;
332 pub const mask: u32 = 0x01 << offset;
333 pub mod R {}
334 pub mod W {}
335 pub mod RW {}
336 }
337 #[doc = "Graceful Stop Complete"]
338 pub mod GRA {
339 pub const offset: u32 = 28;
340 pub const mask: u32 = 0x01 << offset;
341 pub mod R {}
342 pub mod W {}
343 pub mod RW {}
344 }
345 #[doc = "Babbling Transmit Error"]
346 pub mod BABT {
347 pub const offset: u32 = 29;
348 pub const mask: u32 = 0x01 << offset;
349 pub mod R {}
350 pub mod W {}
351 pub mod RW {}
352 }
353 #[doc = "Babbling Receive Error"]
354 pub mod BABR {
355 pub const offset: u32 = 30;
356 pub const mask: u32 = 0x01 << offset;
357 pub mod R {}
358 pub mod W {}
359 pub mod RW {}
360 }
361}
362#[doc = "Interrupt Mask Register"]
363pub mod EIMR {
364 #[doc = "TS_TIMER Interrupt Mask"]
365 pub mod TS_TIMER {
366 pub const offset: u32 = 15;
367 pub const mask: u32 = 0x01 << offset;
368 pub mod R {}
369 pub mod W {}
370 pub mod RW {}
371 }
372 #[doc = "TS_AVAIL Interrupt Mask"]
373 pub mod TS_AVAIL {
374 pub const offset: u32 = 16;
375 pub const mask: u32 = 0x01 << offset;
376 pub mod R {}
377 pub mod W {}
378 pub mod RW {}
379 }
380 #[doc = "WAKEUP Interrupt Mask"]
381 pub mod WAKEUP {
382 pub const offset: u32 = 17;
383 pub const mask: u32 = 0x01 << offset;
384 pub mod R {}
385 pub mod W {}
386 pub mod RW {}
387 }
388 #[doc = "PLR Interrupt Mask"]
389 pub mod PLR {
390 pub const offset: u32 = 18;
391 pub const mask: u32 = 0x01 << offset;
392 pub mod R {}
393 pub mod W {}
394 pub mod RW {}
395 }
396 #[doc = "UN Interrupt Mask"]
397 pub mod UN {
398 pub const offset: u32 = 19;
399 pub const mask: u32 = 0x01 << offset;
400 pub mod R {}
401 pub mod W {}
402 pub mod RW {}
403 }
404 #[doc = "RL Interrupt Mask"]
405 pub mod RL {
406 pub const offset: u32 = 20;
407 pub const mask: u32 = 0x01 << offset;
408 pub mod R {}
409 pub mod W {}
410 pub mod RW {}
411 }
412 #[doc = "LC Interrupt Mask"]
413 pub mod LC {
414 pub const offset: u32 = 21;
415 pub const mask: u32 = 0x01 << offset;
416 pub mod R {}
417 pub mod W {}
418 pub mod RW {}
419 }
420 #[doc = "EBERR Interrupt Mask"]
421 pub mod EBERR {
422 pub const offset: u32 = 22;
423 pub const mask: u32 = 0x01 << offset;
424 pub mod R {}
425 pub mod W {}
426 pub mod RW {}
427 }
428 #[doc = "MII Interrupt Mask"]
429 pub mod MII {
430 pub const offset: u32 = 23;
431 pub const mask: u32 = 0x01 << offset;
432 pub mod R {}
433 pub mod W {}
434 pub mod RW {}
435 }
436 #[doc = "RXB Interrupt Mask"]
437 pub mod RXB {
438 pub const offset: u32 = 24;
439 pub const mask: u32 = 0x01 << offset;
440 pub mod R {}
441 pub mod W {}
442 pub mod RW {}
443 }
444 #[doc = "RXF Interrupt Mask"]
445 pub mod RXF {
446 pub const offset: u32 = 25;
447 pub const mask: u32 = 0x01 << offset;
448 pub mod R {}
449 pub mod W {}
450 pub mod RW {}
451 }
452 #[doc = "TXB Interrupt Mask"]
453 pub mod TXB {
454 pub const offset: u32 = 26;
455 pub const mask: u32 = 0x01 << offset;
456 pub mod R {}
457 pub mod W {}
458 pub mod RW {
459 #[doc = "The corresponding interrupt source is masked."]
460 pub const TXB_0: u32 = 0;
461 #[doc = "The corresponding interrupt source is not masked."]
462 pub const TXB_1: u32 = 0x01;
463 }
464 }
465 #[doc = "TXF Interrupt Mask"]
466 pub mod TXF {
467 pub const offset: u32 = 27;
468 pub const mask: u32 = 0x01 << offset;
469 pub mod R {}
470 pub mod W {}
471 pub mod RW {
472 #[doc = "The corresponding interrupt source is masked."]
473 pub const TXF_0: u32 = 0;
474 #[doc = "The corresponding interrupt source is not masked."]
475 pub const TXF_1: u32 = 0x01;
476 }
477 }
478 #[doc = "GRA Interrupt Mask"]
479 pub mod GRA {
480 pub const offset: u32 = 28;
481 pub const mask: u32 = 0x01 << offset;
482 pub mod R {}
483 pub mod W {}
484 pub mod RW {
485 #[doc = "The corresponding interrupt source is masked."]
486 pub const GRA_0: u32 = 0;
487 #[doc = "The corresponding interrupt source is not masked."]
488 pub const GRA_1: u32 = 0x01;
489 }
490 }
491 #[doc = "BABT Interrupt Mask"]
492 pub mod BABT {
493 pub const offset: u32 = 29;
494 pub const mask: u32 = 0x01 << offset;
495 pub mod R {}
496 pub mod W {}
497 pub mod RW {
498 #[doc = "The corresponding interrupt source is masked."]
499 pub const BABT_0: u32 = 0;
500 #[doc = "The corresponding interrupt source is not masked."]
501 pub const BABT_1: u32 = 0x01;
502 }
503 }
504 #[doc = "BABR Interrupt Mask"]
505 pub mod BABR {
506 pub const offset: u32 = 30;
507 pub const mask: u32 = 0x01 << offset;
508 pub mod R {}
509 pub mod W {}
510 pub mod RW {
511 #[doc = "The corresponding interrupt source is masked."]
512 pub const BABR_0: u32 = 0;
513 #[doc = "The corresponding interrupt source is not masked."]
514 pub const BABR_1: u32 = 0x01;
515 }
516 }
517}
518#[doc = "Receive Descriptor Active Register"]
519pub mod RDAR {
520 #[doc = "Receive Descriptor Active"]
521 pub mod RDAR {
522 pub const offset: u32 = 24;
523 pub const mask: u32 = 0x01 << offset;
524 pub mod R {}
525 pub mod W {}
526 pub mod RW {}
527 }
528}
529#[doc = "Transmit Descriptor Active Register"]
530pub mod TDAR {
531 #[doc = "Transmit Descriptor Active"]
532 pub mod TDAR {
533 pub const offset: u32 = 24;
534 pub const mask: u32 = 0x01 << offset;
535 pub mod R {}
536 pub mod W {}
537 pub mod RW {}
538 }
539}
540#[doc = "Ethernet Control Register"]
541pub mod ECR {
542 #[doc = "Ethernet MAC Reset"]
543 pub mod RESET {
544 pub const offset: u32 = 0;
545 pub const mask: u32 = 0x01 << offset;
546 pub mod R {}
547 pub mod W {}
548 pub mod RW {}
549 }
550 #[doc = "Ethernet Enable"]
551 pub mod ETHEREN {
552 pub const offset: u32 = 1;
553 pub const mask: u32 = 0x01 << offset;
554 pub mod R {}
555 pub mod W {}
556 pub mod RW {
557 #[doc = "Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame."]
558 pub const ETHEREN_0: u32 = 0;
559 #[doc = "MAC is enabled, and reception and transmission are possible."]
560 pub const ETHEREN_1: u32 = 0x01;
561 }
562 }
563 #[doc = "Magic Packet Detection Enable"]
564 pub mod MAGICEN {
565 pub const offset: u32 = 2;
566 pub const mask: u32 = 0x01 << offset;
567 pub mod R {}
568 pub mod W {}
569 pub mod RW {
570 #[doc = "Magic detection logic disabled."]
571 pub const MAGICEN_0: u32 = 0;
572 #[doc = "The MAC core detects magic packets and asserts EIR\\[WAKEUP\\] when a frame is detected."]
573 pub const MAGICEN_1: u32 = 0x01;
574 }
575 }
576 #[doc = "Sleep Mode Enable"]
577 pub mod SLEEP {
578 pub const offset: u32 = 3;
579 pub const mask: u32 = 0x01 << offset;
580 pub mod R {}
581 pub mod W {}
582 pub mod RW {
583 #[doc = "Normal operating mode."]
584 pub const SLEEP_0: u32 = 0;
585 #[doc = "Sleep mode."]
586 pub const SLEEP_1: u32 = 0x01;
587 }
588 }
589 #[doc = "EN1588 Enable"]
590 pub mod EN1588 {
591 pub const offset: u32 = 4;
592 pub const mask: u32 = 0x01 << offset;
593 pub mod R {}
594 pub mod W {}
595 pub mod RW {
596 #[doc = "Legacy FEC buffer descriptors and functions enabled."]
597 pub const EN1588_0: u32 = 0;
598 #[doc = "Enhanced frame time-stamping functions enabled."]
599 pub const EN1588_1: u32 = 0x01;
600 }
601 }
602 #[doc = "Debug Enable"]
603 pub mod DBGEN {
604 pub const offset: u32 = 6;
605 pub const mask: u32 = 0x01 << offset;
606 pub mod R {}
607 pub mod W {}
608 pub mod RW {
609 #[doc = "MAC continues operation in debug mode."]
610 pub const DBGEN_0: u32 = 0;
611 #[doc = "MAC enters hardware freeze mode when the processor is in debug mode."]
612 pub const DBGEN_1: u32 = 0x01;
613 }
614 }
615 #[doc = "Descriptor Byte Swapping Enable"]
616 pub mod DBSWP {
617 pub const offset: u32 = 8;
618 pub const mask: u32 = 0x01 << offset;
619 pub mod R {}
620 pub mod W {}
621 pub mod RW {
622 #[doc = "The buffer descriptor bytes are not swapped to support big-endian devices."]
623 pub const DBSWP_0: u32 = 0;
624 #[doc = "The buffer descriptor bytes are swapped to support little-endian devices."]
625 pub const DBSWP_1: u32 = 0x01;
626 }
627 }
628}
629#[doc = "MII Management Frame Register"]
630pub mod MMFR {
631 #[doc = "Management Frame Data"]
632 pub mod DATA {
633 pub const offset: u32 = 0;
634 pub const mask: u32 = 0xffff << offset;
635 pub mod R {}
636 pub mod W {}
637 pub mod RW {}
638 }
639 #[doc = "Turn Around"]
640 pub mod TA {
641 pub const offset: u32 = 16;
642 pub const mask: u32 = 0x03 << offset;
643 pub mod R {}
644 pub mod W {}
645 pub mod RW {}
646 }
647 #[doc = "Register Address"]
648 pub mod RA {
649 pub const offset: u32 = 18;
650 pub const mask: u32 = 0x1f << offset;
651 pub mod R {}
652 pub mod W {}
653 pub mod RW {}
654 }
655 #[doc = "PHY Address"]
656 pub mod PA {
657 pub const offset: u32 = 23;
658 pub const mask: u32 = 0x1f << offset;
659 pub mod R {}
660 pub mod W {}
661 pub mod RW {}
662 }
663 #[doc = "Operation Code"]
664 pub mod OP {
665 pub const offset: u32 = 28;
666 pub const mask: u32 = 0x03 << offset;
667 pub mod R {}
668 pub mod W {}
669 pub mod RW {}
670 }
671 #[doc = "Start Of Frame Delimiter"]
672 pub mod ST {
673 pub const offset: u32 = 30;
674 pub const mask: u32 = 0x03 << offset;
675 pub mod R {}
676 pub mod W {}
677 pub mod RW {}
678 }
679}
680#[doc = "MII Speed Control Register"]
681pub mod MSCR {
682 #[doc = "MII Speed"]
683 pub mod MII_SPEED {
684 pub const offset: u32 = 1;
685 pub const mask: u32 = 0x3f << offset;
686 pub mod R {}
687 pub mod W {}
688 pub mod RW {}
689 }
690 #[doc = "Disable Preamble"]
691 pub mod DIS_PRE {
692 pub const offset: u32 = 7;
693 pub const mask: u32 = 0x01 << offset;
694 pub mod R {}
695 pub mod W {}
696 pub mod RW {
697 #[doc = "Preamble enabled."]
698 pub const DIS_PRE_0: u32 = 0;
699 #[doc = "Preamble (32 ones) is not prepended to the MII management frame."]
700 pub const DIS_PRE_1: u32 = 0x01;
701 }
702 }
703 #[doc = "Hold time On MDIO Output"]
704 pub mod HOLDTIME {
705 pub const offset: u32 = 8;
706 pub const mask: u32 = 0x07 << offset;
707 pub mod R {}
708 pub mod W {}
709 pub mod RW {
710 #[doc = "1 internal module clock cycle"]
711 pub const HOLDTIME_0: u32 = 0;
712 #[doc = "2 internal module clock cycles"]
713 pub const HOLDTIME_1: u32 = 0x01;
714 #[doc = "3 internal module clock cycles"]
715 pub const HOLDTIME_2: u32 = 0x02;
716 #[doc = "8 internal module clock cycles"]
717 pub const HOLDTIME_7: u32 = 0x07;
718 }
719 }
720}
721#[doc = "MIB Control Register"]
722pub mod MIBC {
723 #[doc = "MIB Clear"]
724 pub mod MIB_CLEAR {
725 pub const offset: u32 = 29;
726 pub const mask: u32 = 0x01 << offset;
727 pub mod R {}
728 pub mod W {}
729 pub mod RW {
730 #[doc = "See note above."]
731 pub const MIB_CLEAR_0: u32 = 0;
732 #[doc = "All statistics counters are reset to 0."]
733 pub const MIB_CLEAR_1: u32 = 0x01;
734 }
735 }
736 #[doc = "MIB Idle"]
737 pub mod MIB_IDLE {
738 pub const offset: u32 = 30;
739 pub const mask: u32 = 0x01 << offset;
740 pub mod R {}
741 pub mod W {}
742 pub mod RW {
743 #[doc = "The MIB block is updating MIB counters."]
744 pub const MIB_IDLE_0: u32 = 0;
745 #[doc = "The MIB block is not currently updating any MIB counters."]
746 pub const MIB_IDLE_1: u32 = 0x01;
747 }
748 }
749 #[doc = "Disable MIB Logic"]
750 pub mod MIB_DIS {
751 pub const offset: u32 = 31;
752 pub const mask: u32 = 0x01 << offset;
753 pub mod R {}
754 pub mod W {}
755 pub mod RW {
756 #[doc = "MIB logic is enabled."]
757 pub const MIB_DIS_0: u32 = 0;
758 #[doc = "MIB logic is disabled. The MIB logic halts and does not update any MIB counters."]
759 pub const MIB_DIS_1: u32 = 0x01;
760 }
761 }
762}
763#[doc = "Receive Control Register"]
764pub mod RCR {
765 #[doc = "Internal Loopback"]
766 pub mod LOOP {
767 pub const offset: u32 = 0;
768 pub const mask: u32 = 0x01 << offset;
769 pub mod R {}
770 pub mod W {}
771 pub mod RW {
772 #[doc = "Loopback disabled."]
773 pub const LOOP_0: u32 = 0;
774 #[doc = "Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared."]
775 pub const LOOP_1: u32 = 0x01;
776 }
777 }
778 #[doc = "Disable Receive On Transmit"]
779 pub mod DRT {
780 pub const offset: u32 = 1;
781 pub const mask: u32 = 0x01 << offset;
782 pub mod R {}
783 pub mod W {}
784 pub mod RW {
785 #[doc = "Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode."]
786 pub const DRT_0: u32 = 0;
787 #[doc = "Disable reception of frames while transmitting. (Normally used for half-duplex mode.)"]
788 pub const DRT_1: u32 = 0x01;
789 }
790 }
791 #[doc = "Media Independent Interface Mode"]
792 pub mod MII_MODE {
793 pub const offset: u32 = 2;
794 pub const mask: u32 = 0x01 << offset;
795 pub mod R {}
796 pub mod W {}
797 pub mod RW {
798 #[doc = "MII or RMII mode, as indicated by the RMII_MODE field."]
799 pub const MII_MODE_1: u32 = 0x01;
800 }
801 }
802 #[doc = "Promiscuous Mode"]
803 pub mod PROM {
804 pub const offset: u32 = 3;
805 pub const mask: u32 = 0x01 << offset;
806 pub mod R {}
807 pub mod W {}
808 pub mod RW {
809 #[doc = "Disabled."]
810 pub const PROM_0: u32 = 0;
811 #[doc = "Enabled."]
812 pub const PROM_1: u32 = 0x01;
813 }
814 }
815 #[doc = "Broadcast Frame Reject"]
816 pub mod BC_REJ {
817 pub const offset: u32 = 4;
818 pub const mask: u32 = 0x01 << offset;
819 pub mod R {}
820 pub mod W {}
821 pub mod RW {}
822 }
823 #[doc = "Flow Control Enable"]
824 pub mod FCE {
825 pub const offset: u32 = 5;
826 pub const mask: u32 = 0x01 << offset;
827 pub mod R {}
828 pub mod W {}
829 pub mod RW {}
830 }
831 #[doc = "RMII Mode Enable"]
832 pub mod RMII_MODE {
833 pub const offset: u32 = 8;
834 pub const mask: u32 = 0x01 << offset;
835 pub mod R {}
836 pub mod W {}
837 pub mod RW {
838 #[doc = "MAC configured for MII mode."]
839 pub const RMII_MODE_0: u32 = 0;
840 #[doc = "MAC configured for RMII operation."]
841 pub const RMII_MODE_1: u32 = 0x01;
842 }
843 }
844 #[doc = "Enables 10-Mbit/s mode of the RMII ."]
845 pub mod RMII_10T {
846 pub const offset: u32 = 9;
847 pub const mask: u32 = 0x01 << offset;
848 pub mod R {}
849 pub mod W {}
850 pub mod RW {
851 #[doc = "100-Mbit/s operation."]
852 pub const RMII_10T_0: u32 = 0;
853 #[doc = "10-Mbit/s operation."]
854 pub const RMII_10T_1: u32 = 0x01;
855 }
856 }
857 #[doc = "Enable Frame Padding Remove On Receive"]
858 pub mod PADEN {
859 pub const offset: u32 = 12;
860 pub const mask: u32 = 0x01 << offset;
861 pub mod R {}
862 pub mod W {}
863 pub mod RW {
864 #[doc = "No padding is removed on receive by the MAC."]
865 pub const PADEN_0: u32 = 0;
866 #[doc = "Padding is removed from received frames."]
867 pub const PADEN_1: u32 = 0x01;
868 }
869 }
870 #[doc = "Terminate/Forward Pause Frames"]
871 pub mod PAUFWD {
872 pub const offset: u32 = 13;
873 pub const mask: u32 = 0x01 << offset;
874 pub mod R {}
875 pub mod W {}
876 pub mod RW {
877 #[doc = "Pause frames are terminated and discarded in the MAC."]
878 pub const PAUFWD_0: u32 = 0;
879 #[doc = "Pause frames are forwarded to the user application."]
880 pub const PAUFWD_1: u32 = 0x01;
881 }
882 }
883 #[doc = "Terminate/Forward Received CRC"]
884 pub mod CRCFWD {
885 pub const offset: u32 = 14;
886 pub const mask: u32 = 0x01 << offset;
887 pub mod R {}
888 pub mod W {}
889 pub mod RW {
890 #[doc = "The CRC field of received frames is transmitted to the user application."]
891 pub const CRCFWD_0: u32 = 0;
892 #[doc = "The CRC field is stripped from the frame."]
893 pub const CRCFWD_1: u32 = 0x01;
894 }
895 }
896 #[doc = "MAC Control Frame Enable"]
897 pub mod CFEN {
898 pub const offset: u32 = 15;
899 pub const mask: u32 = 0x01 << offset;
900 pub mod R {}
901 pub mod W {}
902 pub mod RW {
903 #[doc = "MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface."]
904 pub const CFEN_0: u32 = 0;
905 #[doc = "MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded."]
906 pub const CFEN_1: u32 = 0x01;
907 }
908 }
909 #[doc = "Maximum Frame Length"]
910 pub mod MAX_FL {
911 pub const offset: u32 = 16;
912 pub const mask: u32 = 0x3fff << offset;
913 pub mod R {}
914 pub mod W {}
915 pub mod RW {}
916 }
917 #[doc = "Payload Length Check Disable"]
918 pub mod NLC {
919 pub const offset: u32 = 30;
920 pub const mask: u32 = 0x01 << offset;
921 pub mod R {}
922 pub mod W {}
923 pub mod RW {
924 #[doc = "The payload length check is disabled."]
925 pub const NLC_0: u32 = 0;
926 #[doc = "The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR\\[PLR\\] field."]
927 pub const NLC_1: u32 = 0x01;
928 }
929 }
930 #[doc = "Graceful Receive Stopped"]
931 pub mod GRS {
932 pub const offset: u32 = 31;
933 pub const mask: u32 = 0x01 << offset;
934 pub mod R {}
935 pub mod W {}
936 pub mod RW {}
937 }
938}
939#[doc = "Transmit Control Register"]
940pub mod TCR {
941 #[doc = "Graceful Transmit Stop"]
942 pub mod GTS {
943 pub const offset: u32 = 0;
944 pub const mask: u32 = 0x01 << offset;
945 pub mod R {}
946 pub mod W {}
947 pub mod RW {}
948 }
949 #[doc = "Full-Duplex Enable"]
950 pub mod FDEN {
951 pub const offset: u32 = 2;
952 pub const mask: u32 = 0x01 << offset;
953 pub mod R {}
954 pub mod W {}
955 pub mod RW {}
956 }
957 #[doc = "Transmit Frame Control Pause"]
958 pub mod TFC_PAUSE {
959 pub const offset: u32 = 3;
960 pub const mask: u32 = 0x01 << offset;
961 pub mod R {}
962 pub mod W {}
963 pub mod RW {
964 #[doc = "No PAUSE frame transmitted."]
965 pub const TFC_PAUSE_0: u32 = 0;
966 #[doc = "The MAC stops transmission of data frames after the current transmission is complete."]
967 pub const TFC_PAUSE_1: u32 = 0x01;
968 }
969 }
970 #[doc = "Receive Frame Control Pause"]
971 pub mod RFC_PAUSE {
972 pub const offset: u32 = 4;
973 pub const mask: u32 = 0x01 << offset;
974 pub mod R {}
975 pub mod W {}
976 pub mod RW {}
977 }
978 #[doc = "Source MAC Address Select On Transmit"]
979 pub mod ADDSEL {
980 pub const offset: u32 = 5;
981 pub const mask: u32 = 0x07 << offset;
982 pub mod R {}
983 pub mod W {}
984 pub mod RW {
985 #[doc = "Node MAC address programmed on PADDR1/2 registers."]
986 pub const ADDSEL_0: u32 = 0;
987 }
988 }
989 #[doc = "Set MAC Address On Transmit"]
990 pub mod ADDINS {
991 pub const offset: u32 = 8;
992 pub const mask: u32 = 0x01 << offset;
993 pub mod R {}
994 pub mod W {}
995 pub mod RW {
996 #[doc = "The source MAC address is not modified by the MAC."]
997 pub const ADDINS_0: u32 = 0;
998 #[doc = "The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL."]
999 pub const ADDINS_1: u32 = 0x01;
1000 }
1001 }
1002 #[doc = "Forward Frame From Application With CRC"]
1003 pub mod CRCFWD {
1004 pub const offset: u32 = 9;
1005 pub const mask: u32 = 0x01 << offset;
1006 pub mod R {}
1007 pub mod W {}
1008 pub mod RW {
1009 #[doc = "TxBD\\[TC\\] controls whether the frame has a CRC from the application."]
1010 pub const CRCFWD_0: u32 = 0;
1011 #[doc = "The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application."]
1012 pub const CRCFWD_1: u32 = 0x01;
1013 }
1014 }
1015}
1016#[doc = "Physical Address Lower Register"]
1017pub mod PALR {
1018 #[doc = "Pause Address"]
1019 pub mod PADDR1 {
1020 pub const offset: u32 = 0;
1021 pub const mask: u32 = 0xffff_ffff << offset;
1022 pub mod R {}
1023 pub mod W {}
1024 pub mod RW {}
1025 }
1026}
1027#[doc = "Physical Address Upper Register"]
1028pub mod PAUR {
1029 #[doc = "Type Field In PAUSE Frames"]
1030 pub mod TYPE {
1031 pub const offset: u32 = 0;
1032 pub const mask: u32 = 0xffff << offset;
1033 pub mod R {}
1034 pub mod W {}
1035 pub mod RW {}
1036 }
1037 #[doc = "Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match, and the source address field in PAUSE frames"]
1038 pub mod PADDR2 {
1039 pub const offset: u32 = 16;
1040 pub const mask: u32 = 0xffff << offset;
1041 pub mod R {}
1042 pub mod W {}
1043 pub mod RW {}
1044 }
1045}
1046#[doc = "Opcode/Pause Duration Register"]
1047pub mod OPD {
1048 #[doc = "Pause Duration"]
1049 pub mod PAUSE_DUR {
1050 pub const offset: u32 = 0;
1051 pub const mask: u32 = 0xffff << offset;
1052 pub mod R {}
1053 pub mod W {}
1054 pub mod RW {}
1055 }
1056 #[doc = "Opcode Field In PAUSE Frames"]
1057 pub mod OPCODE {
1058 pub const offset: u32 = 16;
1059 pub const mask: u32 = 0xffff << offset;
1060 pub mod R {}
1061 pub mod W {}
1062 pub mod RW {}
1063 }
1064}
1065#[doc = "Transmit Interrupt Coalescing Register"]
1066pub mod TXIC {
1067 #[doc = "Interrupt coalescing timer threshold"]
1068 pub mod ICTT {
1069 pub const offset: u32 = 0;
1070 pub const mask: u32 = 0xffff << offset;
1071 pub mod R {}
1072 pub mod W {}
1073 pub mod RW {}
1074 }
1075 #[doc = "Interrupt coalescing frame count threshold"]
1076 pub mod ICFT {
1077 pub const offset: u32 = 20;
1078 pub const mask: u32 = 0xff << offset;
1079 pub mod R {}
1080 pub mod W {}
1081 pub mod RW {}
1082 }
1083 #[doc = "Interrupt Coalescing Timer Clock Source Select"]
1084 pub mod ICCS {
1085 pub const offset: u32 = 30;
1086 pub const mask: u32 = 0x01 << offset;
1087 pub mod R {}
1088 pub mod W {}
1089 pub mod RW {
1090 #[doc = "Use MII/GMII TX clocks."]
1091 pub const ICCS_0: u32 = 0;
1092 #[doc = "Use ENET system clock."]
1093 pub const ICCS_1: u32 = 0x01;
1094 }
1095 }
1096 #[doc = "Interrupt Coalescing Enable"]
1097 pub mod ICEN {
1098 pub const offset: u32 = 31;
1099 pub const mask: u32 = 0x01 << offset;
1100 pub mod R {}
1101 pub mod W {}
1102 pub mod RW {
1103 #[doc = "Disable Interrupt coalescing."]
1104 pub const ICEN_0: u32 = 0;
1105 #[doc = "Enable Interrupt coalescing."]
1106 pub const ICEN_1: u32 = 0x01;
1107 }
1108 }
1109}
1110#[doc = "Receive Interrupt Coalescing Register"]
1111pub mod RXIC {
1112 #[doc = "Interrupt coalescing timer threshold"]
1113 pub mod ICTT {
1114 pub const offset: u32 = 0;
1115 pub const mask: u32 = 0xffff << offset;
1116 pub mod R {}
1117 pub mod W {}
1118 pub mod RW {}
1119 }
1120 #[doc = "Interrupt coalescing frame count threshold"]
1121 pub mod ICFT {
1122 pub const offset: u32 = 20;
1123 pub const mask: u32 = 0xff << offset;
1124 pub mod R {}
1125 pub mod W {}
1126 pub mod RW {}
1127 }
1128 #[doc = "Interrupt Coalescing Timer Clock Source Select"]
1129 pub mod ICCS {
1130 pub const offset: u32 = 30;
1131 pub const mask: u32 = 0x01 << offset;
1132 pub mod R {}
1133 pub mod W {}
1134 pub mod RW {
1135 #[doc = "Use MII/GMII TX clocks."]
1136 pub const ICCS_0: u32 = 0;
1137 #[doc = "Use ENET system clock."]
1138 pub const ICCS_1: u32 = 0x01;
1139 }
1140 }
1141 #[doc = "Interrupt Coalescing Enable"]
1142 pub mod ICEN {
1143 pub const offset: u32 = 31;
1144 pub const mask: u32 = 0x01 << offset;
1145 pub mod R {}
1146 pub mod W {}
1147 pub mod RW {
1148 #[doc = "Disable Interrupt coalescing."]
1149 pub const ICEN_0: u32 = 0;
1150 #[doc = "Enable Interrupt coalescing."]
1151 pub const ICEN_1: u32 = 0x01;
1152 }
1153 }
1154}
1155#[doc = "Descriptor Individual Upper Address Register"]
1156pub mod IAUR {
1157 #[doc = "Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address"]
1158 pub mod IADDR1 {
1159 pub const offset: u32 = 0;
1160 pub const mask: u32 = 0xffff_ffff << offset;
1161 pub mod R {}
1162 pub mod W {}
1163 pub mod RW {}
1164 }
1165}
1166#[doc = "Descriptor Individual Lower Address Register"]
1167pub mod IALR {
1168 #[doc = "Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address"]
1169 pub mod IADDR2 {
1170 pub const offset: u32 = 0;
1171 pub const mask: u32 = 0xffff_ffff << offset;
1172 pub mod R {}
1173 pub mod W {}
1174 pub mod RW {}
1175 }
1176}
1177#[doc = "Descriptor Group Upper Address Register"]
1178pub mod GAUR {
1179 #[doc = "Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address"]
1180 pub mod GADDR1 {
1181 pub const offset: u32 = 0;
1182 pub const mask: u32 = 0xffff_ffff << offset;
1183 pub mod R {}
1184 pub mod W {}
1185 pub mod RW {}
1186 }
1187}
1188#[doc = "Descriptor Group Lower Address Register"]
1189pub mod GALR {
1190 #[doc = "Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address"]
1191 pub mod GADDR2 {
1192 pub const offset: u32 = 0;
1193 pub const mask: u32 = 0xffff_ffff << offset;
1194 pub mod R {}
1195 pub mod W {}
1196 pub mod RW {}
1197 }
1198}
1199#[doc = "Transmit FIFO Watermark Register"]
1200pub mod TFWR {
1201 #[doc = "Transmit FIFO Write"]
1202 pub mod TFWR {
1203 pub const offset: u32 = 0;
1204 pub const mask: u32 = 0x3f << offset;
1205 pub mod R {}
1206 pub mod W {}
1207 pub mod RW {
1208 #[doc = "64 bytes written."]
1209 pub const TFWR_0: u32 = 0;
1210 #[doc = "64 bytes written."]
1211 pub const TFWR_1: u32 = 0x01;
1212 #[doc = "128 bytes written."]
1213 pub const TFWR_2: u32 = 0x02;
1214 #[doc = "192 bytes written."]
1215 pub const TFWR_3: u32 = 0x03;
1216 #[doc = "1984 bytes written."]
1217 pub const TFWR_31: u32 = 0x1f;
1218 }
1219 }
1220 #[doc = "Store And Forward Enable"]
1221 pub mod STRFWD {
1222 pub const offset: u32 = 8;
1223 pub const mask: u32 = 0x01 << offset;
1224 pub mod R {}
1225 pub mod W {}
1226 pub mod RW {
1227 #[doc = "Reset. The transmission start threshold is programmed in TFWR\\[TFWR\\]."]
1228 pub const STRFWD_0: u32 = 0;
1229 #[doc = "Enabled."]
1230 pub const STRFWD_1: u32 = 0x01;
1231 }
1232 }
1233}
1234#[doc = "Receive Descriptor Ring Start Register"]
1235pub mod RDSR {
1236 #[doc = "Pointer to the beginning of the receive buffer descriptor queue."]
1237 pub mod R_DES_START {
1238 pub const offset: u32 = 3;
1239 pub const mask: u32 = 0x1fff_ffff << offset;
1240 pub mod R {}
1241 pub mod W {}
1242 pub mod RW {}
1243 }
1244}
1245#[doc = "Transmit Buffer Descriptor Ring Start Register"]
1246pub mod TDSR {
1247 #[doc = "Pointer to the beginning of the transmit buffer descriptor queue."]
1248 pub mod X_DES_START {
1249 pub const offset: u32 = 3;
1250 pub const mask: u32 = 0x1fff_ffff << offset;
1251 pub mod R {}
1252 pub mod W {}
1253 pub mod RW {}
1254 }
1255}
1256#[doc = "Maximum Receive Buffer Size Register"]
1257pub mod MRBR {
1258 #[doc = "Receive buffer size in bytes"]
1259 pub mod R_BUF_SIZE {
1260 pub const offset: u32 = 4;
1261 pub const mask: u32 = 0x03ff << offset;
1262 pub mod R {}
1263 pub mod W {}
1264 pub mod RW {}
1265 }
1266}
1267#[doc = "Receive FIFO Section Full Threshold"]
1268pub mod RSFL {
1269 #[doc = "Value Of Receive FIFO Section Full Threshold"]
1270 pub mod RX_SECTION_FULL {
1271 pub const offset: u32 = 0;
1272 pub const mask: u32 = 0xff << offset;
1273 pub mod R {}
1274 pub mod W {}
1275 pub mod RW {}
1276 }
1277}
1278#[doc = "Receive FIFO Section Empty Threshold"]
1279pub mod RSEM {
1280 #[doc = "Value Of The Receive FIFO Section Empty Threshold"]
1281 pub mod RX_SECTION_EMPTY {
1282 pub const offset: u32 = 0;
1283 pub const mask: u32 = 0xff << offset;
1284 pub mod R {}
1285 pub mod W {}
1286 pub mod RW {}
1287 }
1288 #[doc = "RX Status FIFO Section Empty Threshold"]
1289 pub mod STAT_SECTION_EMPTY {
1290 pub const offset: u32 = 16;
1291 pub const mask: u32 = 0x1f << offset;
1292 pub mod R {}
1293 pub mod W {}
1294 pub mod RW {}
1295 }
1296}
1297#[doc = "Receive FIFO Almost Empty Threshold"]
1298pub mod RAEM {
1299 #[doc = "Value Of The Receive FIFO Almost Empty Threshold"]
1300 pub mod RX_ALMOST_EMPTY {
1301 pub const offset: u32 = 0;
1302 pub const mask: u32 = 0xff << offset;
1303 pub mod R {}
1304 pub mod W {}
1305 pub mod RW {}
1306 }
1307}
1308#[doc = "Receive FIFO Almost Full Threshold"]
1309pub mod RAFL {
1310 #[doc = "Value Of The Receive FIFO Almost Full Threshold"]
1311 pub mod RX_ALMOST_FULL {
1312 pub const offset: u32 = 0;
1313 pub const mask: u32 = 0xff << offset;
1314 pub mod R {}
1315 pub mod W {}
1316 pub mod RW {}
1317 }
1318}
1319#[doc = "Transmit FIFO Section Empty Threshold"]
1320pub mod TSEM {
1321 #[doc = "Value Of The Transmit FIFO Section Empty Threshold"]
1322 pub mod TX_SECTION_EMPTY {
1323 pub const offset: u32 = 0;
1324 pub const mask: u32 = 0xff << offset;
1325 pub mod R {}
1326 pub mod W {}
1327 pub mod RW {}
1328 }
1329}
1330#[doc = "Transmit FIFO Almost Empty Threshold"]
1331pub mod TAEM {
1332 #[doc = "Value of Transmit FIFO Almost Empty Threshold"]
1333 pub mod TX_ALMOST_EMPTY {
1334 pub const offset: u32 = 0;
1335 pub const mask: u32 = 0xff << offset;
1336 pub mod R {}
1337 pub mod W {}
1338 pub mod RW {}
1339 }
1340}
1341#[doc = "Transmit FIFO Almost Full Threshold"]
1342pub mod TAFL {
1343 #[doc = "Value Of The Transmit FIFO Almost Full Threshold"]
1344 pub mod TX_ALMOST_FULL {
1345 pub const offset: u32 = 0;
1346 pub const mask: u32 = 0xff << offset;
1347 pub mod R {}
1348 pub mod W {}
1349 pub mod RW {}
1350 }
1351}
1352#[doc = "Transmit Inter-Packet Gap"]
1353pub mod TIPG {
1354 #[doc = "Transmit Inter-Packet Gap"]
1355 pub mod IPG {
1356 pub const offset: u32 = 0;
1357 pub const mask: u32 = 0x1f << offset;
1358 pub mod R {}
1359 pub mod W {}
1360 pub mod RW {}
1361 }
1362}
1363#[doc = "Frame Truncation Length"]
1364pub mod FTRL {
1365 #[doc = "Frame Truncation Length"]
1366 pub mod TRUNC_FL {
1367 pub const offset: u32 = 0;
1368 pub const mask: u32 = 0x3fff << offset;
1369 pub mod R {}
1370 pub mod W {}
1371 pub mod RW {}
1372 }
1373}
1374#[doc = "Transmit Accelerator Function Configuration"]
1375pub mod TACC {
1376 #[doc = "TX FIFO Shift-16"]
1377 pub mod SHIFT16 {
1378 pub const offset: u32 = 0;
1379 pub const mask: u32 = 0x01 << offset;
1380 pub mod R {}
1381 pub mod W {}
1382 pub mod RW {
1383 #[doc = "Disabled."]
1384 pub const SHIFT16_0: u32 = 0;
1385 #[doc = "Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header."]
1386 pub const SHIFT16_1: u32 = 0x01;
1387 }
1388 }
1389 #[doc = "Enables insertion of IP header checksum."]
1390 pub mod IPCHK {
1391 pub const offset: u32 = 3;
1392 pub const mask: u32 = 0x01 << offset;
1393 pub mod R {}
1394 pub mod W {}
1395 pub mod RW {
1396 #[doc = "Checksum is not inserted."]
1397 pub const IPCHK_0: u32 = 0;
1398 #[doc = "If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified."]
1399 pub const IPCHK_1: u32 = 0x01;
1400 }
1401 }
1402 #[doc = "Enables insertion of protocol checksum."]
1403 pub mod PROCHK {
1404 pub const offset: u32 = 4;
1405 pub const mask: u32 = 0x01 << offset;
1406 pub mod R {}
1407 pub mod W {}
1408 pub mod RW {
1409 #[doc = "Checksum not inserted."]
1410 pub const PROCHK_0: u32 = 0;
1411 #[doc = "If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified."]
1412 pub const PROCHK_1: u32 = 0x01;
1413 }
1414 }
1415}
1416#[doc = "Receive Accelerator Function Configuration"]
1417pub mod RACC {
1418 #[doc = "Enable Padding Removal For Short IP Frames"]
1419 pub mod PADREM {
1420 pub const offset: u32 = 0;
1421 pub const mask: u32 = 0x01 << offset;
1422 pub mod R {}
1423 pub mod W {}
1424 pub mod RW {
1425 #[doc = "Padding not removed."]
1426 pub const PADREM_0: u32 = 0;
1427 #[doc = "Any bytes following the IP payload section of the frame are removed from the frame."]
1428 pub const PADREM_1: u32 = 0x01;
1429 }
1430 }
1431 #[doc = "Enable Discard Of Frames With Wrong IPv4 Header Checksum"]
1432 pub mod IPDIS {
1433 pub const offset: u32 = 1;
1434 pub const mask: u32 = 0x01 << offset;
1435 pub mod R {}
1436 pub mod W {}
1437 pub mod RW {
1438 #[doc = "Frames with wrong IPv4 header checksum are not discarded."]
1439 pub const IPDIS_0: u32 = 0;
1440 #[doc = "If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared)."]
1441 pub const IPDIS_1: u32 = 0x01;
1442 }
1443 }
1444 #[doc = "Enable Discard Of Frames With Wrong Protocol Checksum"]
1445 pub mod PRODIS {
1446 pub const offset: u32 = 2;
1447 pub const mask: u32 = 0x01 << offset;
1448 pub mod R {}
1449 pub mod W {}
1450 pub mod RW {
1451 #[doc = "Frames with wrong checksum are not discarded."]
1452 pub const PRODIS_0: u32 = 0;
1453 #[doc = "If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared)."]
1454 pub const PRODIS_1: u32 = 0x01;
1455 }
1456 }
1457 #[doc = "Enable Discard Of Frames With MAC Layer Errors"]
1458 pub mod LINEDIS {
1459 pub const offset: u32 = 6;
1460 pub const mask: u32 = 0x01 << offset;
1461 pub mod R {}
1462 pub mod W {}
1463 pub mod RW {
1464 #[doc = "Frames with errors are not discarded."]
1465 pub const LINEDIS_0: u32 = 0;
1466 #[doc = "Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface."]
1467 pub const LINEDIS_1: u32 = 0x01;
1468 }
1469 }
1470 #[doc = "RX FIFO Shift-16"]
1471 pub mod SHIFT16 {
1472 pub const offset: u32 = 7;
1473 pub const mask: u32 = 0x01 << offset;
1474 pub mod R {}
1475 pub mod W {}
1476 pub mod RW {
1477 #[doc = "Disabled."]
1478 pub const SHIFT16_0: u32 = 0;
1479 #[doc = "Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO."]
1480 pub const SHIFT16_1: u32 = 0x01;
1481 }
1482 }
1483}
1484#[doc = "Tx Packet Count Statistic Register"]
1485pub mod RMON_T_PACKETS {
1486 #[doc = "Packet count"]
1487 pub mod TXPKTS {
1488 pub const offset: u32 = 0;
1489 pub const mask: u32 = 0xffff << offset;
1490 pub mod R {}
1491 pub mod W {}
1492 pub mod RW {}
1493 }
1494}
1495#[doc = "Tx Broadcast Packets Statistic Register"]
1496pub mod RMON_T_BC_PKT {
1497 #[doc = "Broadcast packets"]
1498 pub mod TXPKTS {
1499 pub const offset: u32 = 0;
1500 pub const mask: u32 = 0xffff << offset;
1501 pub mod R {}
1502 pub mod W {}
1503 pub mod RW {}
1504 }
1505}
1506#[doc = "Tx Multicast Packets Statistic Register"]
1507pub mod RMON_T_MC_PKT {
1508 #[doc = "Multicast packets"]
1509 pub mod TXPKTS {
1510 pub const offset: u32 = 0;
1511 pub const mask: u32 = 0xffff << offset;
1512 pub mod R {}
1513 pub mod W {}
1514 pub mod RW {}
1515 }
1516}
1517#[doc = "Tx Packets with CRC/Align Error Statistic Register"]
1518pub mod RMON_T_CRC_ALIGN {
1519 #[doc = "Packets with CRC/align error"]
1520 pub mod TXPKTS {
1521 pub const offset: u32 = 0;
1522 pub const mask: u32 = 0xffff << offset;
1523 pub mod R {}
1524 pub mod W {}
1525 pub mod RW {}
1526 }
1527}
1528#[doc = "Tx Packets Less Than Bytes and Good CRC Statistic Register"]
1529pub mod RMON_T_UNDERSIZE {
1530 #[doc = "Number of transmit packets less than 64 bytes with good CRC"]
1531 pub mod TXPKTS {
1532 pub const offset: u32 = 0;
1533 pub const mask: u32 = 0xffff << offset;
1534 pub mod R {}
1535 pub mod W {}
1536 pub mod RW {}
1537 }
1538}
1539#[doc = "Tx Packets GT MAX_FL bytes and Good CRC Statistic Register"]
1540pub mod RMON_T_OVERSIZE {
1541 #[doc = "Number of transmit packets greater than MAX_FL bytes with good CRC"]
1542 pub mod TXPKTS {
1543 pub const offset: u32 = 0;
1544 pub const mask: u32 = 0xffff << offset;
1545 pub mod R {}
1546 pub mod W {}
1547 pub mod RW {}
1548 }
1549}
1550#[doc = "Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register"]
1551pub mod RMON_T_FRAG {
1552 #[doc = "Number of packets less than 64 bytes with bad CRC"]
1553 pub mod TXPKTS {
1554 pub const offset: u32 = 0;
1555 pub const mask: u32 = 0xffff << offset;
1556 pub mod R {}
1557 pub mod W {}
1558 pub mod RW {}
1559 }
1560}
1561#[doc = "Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register"]
1562pub mod RMON_T_JAB {
1563 #[doc = "Number of transmit packets greater than MAX_FL bytes and bad CRC"]
1564 pub mod TXPKTS {
1565 pub const offset: u32 = 0;
1566 pub const mask: u32 = 0xffff << offset;
1567 pub mod R {}
1568 pub mod W {}
1569 pub mod RW {}
1570 }
1571}
1572#[doc = "Tx Collision Count Statistic Register"]
1573pub mod RMON_T_COL {
1574 #[doc = "Number of transmit collisions"]
1575 pub mod TXPKTS {
1576 pub const offset: u32 = 0;
1577 pub const mask: u32 = 0xffff << offset;
1578 pub mod R {}
1579 pub mod W {}
1580 pub mod RW {}
1581 }
1582}
1583#[doc = "Tx 64-Byte Packets Statistic Register"]
1584pub mod RMON_T_P64 {
1585 #[doc = "Number of 64-byte transmit packets"]
1586 pub mod TXPKTS {
1587 pub const offset: u32 = 0;
1588 pub const mask: u32 = 0xffff << offset;
1589 pub mod R {}
1590 pub mod W {}
1591 pub mod RW {}
1592 }
1593}
1594#[doc = "Tx 65- to 127-byte Packets Statistic Register"]
1595pub mod RMON_T_P65TO127 {
1596 #[doc = "Number of 65- to 127-byte transmit packets"]
1597 pub mod TXPKTS {
1598 pub const offset: u32 = 0;
1599 pub const mask: u32 = 0xffff << offset;
1600 pub mod R {}
1601 pub mod W {}
1602 pub mod RW {}
1603 }
1604}
1605#[doc = "Tx 128- to 255-byte Packets Statistic Register"]
1606pub mod RMON_T_P128TO255 {
1607 #[doc = "Number of 128- to 255-byte transmit packets"]
1608 pub mod TXPKTS {
1609 pub const offset: u32 = 0;
1610 pub const mask: u32 = 0xffff << offset;
1611 pub mod R {}
1612 pub mod W {}
1613 pub mod RW {}
1614 }
1615}
1616#[doc = "Tx 256- to 511-byte Packets Statistic Register"]
1617pub mod RMON_T_P256TO511 {
1618 #[doc = "Number of 256- to 511-byte transmit packets"]
1619 pub mod TXPKTS {
1620 pub const offset: u32 = 0;
1621 pub const mask: u32 = 0xffff << offset;
1622 pub mod R {}
1623 pub mod W {}
1624 pub mod RW {}
1625 }
1626}
1627#[doc = "Tx 512- to 1023-byte Packets Statistic Register"]
1628pub mod RMON_T_P512TO1023 {
1629 #[doc = "Number of 512- to 1023-byte transmit packets"]
1630 pub mod TXPKTS {
1631 pub const offset: u32 = 0;
1632 pub const mask: u32 = 0xffff << offset;
1633 pub mod R {}
1634 pub mod W {}
1635 pub mod RW {}
1636 }
1637}
1638#[doc = "Tx 1024- to 2047-byte Packets Statistic Register"]
1639pub mod RMON_T_P1024TO2047 {
1640 #[doc = "Number of 1024- to 2047-byte transmit packets"]
1641 pub mod TXPKTS {
1642 pub const offset: u32 = 0;
1643 pub const mask: u32 = 0xffff << offset;
1644 pub mod R {}
1645 pub mod W {}
1646 pub mod RW {}
1647 }
1648}
1649#[doc = "Tx Packets Greater Than 2048 Bytes Statistic Register"]
1650pub mod RMON_T_P_GTE2048 {
1651 #[doc = "Number of transmit packets greater than 2048 bytes"]
1652 pub mod TXPKTS {
1653 pub const offset: u32 = 0;
1654 pub const mask: u32 = 0xffff << offset;
1655 pub mod R {}
1656 pub mod W {}
1657 pub mod RW {}
1658 }
1659}
1660#[doc = "Tx Octets Statistic Register"]
1661pub mod RMON_T_OCTETS {
1662 #[doc = "Number of transmit octets"]
1663 pub mod TXOCTS {
1664 pub const offset: u32 = 0;
1665 pub const mask: u32 = 0xffff_ffff << offset;
1666 pub mod R {}
1667 pub mod W {}
1668 pub mod RW {}
1669 }
1670}
1671#[doc = "Frames Transmitted OK Statistic Register"]
1672pub mod IEEE_T_FRAME_OK {
1673 #[doc = "Number of frames transmitted OK"]
1674 pub mod COUNT {
1675 pub const offset: u32 = 0;
1676 pub const mask: u32 = 0xffff << offset;
1677 pub mod R {}
1678 pub mod W {}
1679 pub mod RW {}
1680 }
1681}
1682#[doc = "Frames Transmitted with Single Collision Statistic Register"]
1683pub mod IEEE_T_1COL {
1684 #[doc = "Number of frames transmitted with one collision"]
1685 pub mod COUNT {
1686 pub const offset: u32 = 0;
1687 pub const mask: u32 = 0xffff << offset;
1688 pub mod R {}
1689 pub mod W {}
1690 pub mod RW {}
1691 }
1692}
1693#[doc = "Frames Transmitted with Multiple Collisions Statistic Register"]
1694pub mod IEEE_T_MCOL {
1695 #[doc = "Number of frames transmitted with multiple collisions"]
1696 pub mod COUNT {
1697 pub const offset: u32 = 0;
1698 pub const mask: u32 = 0xffff << offset;
1699 pub mod R {}
1700 pub mod W {}
1701 pub mod RW {}
1702 }
1703}
1704#[doc = "Frames Transmitted after Deferral Delay Statistic Register"]
1705pub mod IEEE_T_DEF {
1706 #[doc = "Number of frames transmitted with deferral delay"]
1707 pub mod COUNT {
1708 pub const offset: u32 = 0;
1709 pub const mask: u32 = 0xffff << offset;
1710 pub mod R {}
1711 pub mod W {}
1712 pub mod RW {}
1713 }
1714}
1715#[doc = "Frames Transmitted with Late Collision Statistic Register"]
1716pub mod IEEE_T_LCOL {
1717 #[doc = "Number of frames transmitted with late collision"]
1718 pub mod COUNT {
1719 pub const offset: u32 = 0;
1720 pub const mask: u32 = 0xffff << offset;
1721 pub mod R {}
1722 pub mod W {}
1723 pub mod RW {}
1724 }
1725}
1726#[doc = "Frames Transmitted with Excessive Collisions Statistic Register"]
1727pub mod IEEE_T_EXCOL {
1728 #[doc = "Number of frames transmitted with excessive collisions"]
1729 pub mod COUNT {
1730 pub const offset: u32 = 0;
1731 pub const mask: u32 = 0xffff << offset;
1732 pub mod R {}
1733 pub mod W {}
1734 pub mod RW {}
1735 }
1736}
1737#[doc = "Frames Transmitted with Tx FIFO Underrun Statistic Register"]
1738pub mod IEEE_T_MACERR {
1739 #[doc = "Number of frames transmitted with transmit FIFO underrun"]
1740 pub mod COUNT {
1741 pub const offset: u32 = 0;
1742 pub const mask: u32 = 0xffff << offset;
1743 pub mod R {}
1744 pub mod W {}
1745 pub mod RW {}
1746 }
1747}
1748#[doc = "Frames Transmitted with Carrier Sense Error Statistic Register"]
1749pub mod IEEE_T_CSERR {
1750 #[doc = "Number of frames transmitted with carrier sense error"]
1751 pub mod COUNT {
1752 pub const offset: u32 = 0;
1753 pub const mask: u32 = 0xffff << offset;
1754 pub mod R {}
1755 pub mod W {}
1756 pub mod RW {}
1757 }
1758}
1759#[doc = "Reserved Statistic Register"]
1760pub mod IEEE_T_SQE {
1761 #[doc = "This read-only field is reserved and always has the value 0"]
1762 pub mod COUNT {
1763 pub const offset: u32 = 0;
1764 pub const mask: u32 = 0xffff << offset;
1765 pub mod R {}
1766 pub mod W {}
1767 pub mod RW {}
1768 }
1769}
1770#[doc = "Flow Control Pause Frames Transmitted Statistic Register"]
1771pub mod IEEE_T_FDXFC {
1772 #[doc = "Number of flow-control pause frames transmitted"]
1773 pub mod COUNT {
1774 pub const offset: u32 = 0;
1775 pub const mask: u32 = 0xffff << offset;
1776 pub mod R {}
1777 pub mod W {}
1778 pub mod RW {}
1779 }
1780}
1781#[doc = "Octet Count for Frames Transmitted w/o Error Statistic Register"]
1782pub mod IEEE_T_OCTETS_OK {
1783 #[doc = "Octet count for frames transmitted without error Counts total octets (includes header and FCS fields)."]
1784 pub mod COUNT {
1785 pub const offset: u32 = 0;
1786 pub const mask: u32 = 0xffff_ffff << offset;
1787 pub mod R {}
1788 pub mod W {}
1789 pub mod RW {}
1790 }
1791}
1792#[doc = "Rx Packet Count Statistic Register"]
1793pub mod RMON_R_PACKETS {
1794 #[doc = "Number of packets received"]
1795 pub mod COUNT {
1796 pub const offset: u32 = 0;
1797 pub const mask: u32 = 0xffff << offset;
1798 pub mod R {}
1799 pub mod W {}
1800 pub mod RW {}
1801 }
1802}
1803#[doc = "Rx Broadcast Packets Statistic Register"]
1804pub mod RMON_R_BC_PKT {
1805 #[doc = "Number of receive broadcast packets"]
1806 pub mod COUNT {
1807 pub const offset: u32 = 0;
1808 pub const mask: u32 = 0xffff << offset;
1809 pub mod R {}
1810 pub mod W {}
1811 pub mod RW {}
1812 }
1813}
1814#[doc = "Rx Multicast Packets Statistic Register"]
1815pub mod RMON_R_MC_PKT {
1816 #[doc = "Number of receive multicast packets"]
1817 pub mod COUNT {
1818 pub const offset: u32 = 0;
1819 pub const mask: u32 = 0xffff << offset;
1820 pub mod R {}
1821 pub mod W {}
1822 pub mod RW {}
1823 }
1824}
1825#[doc = "Rx Packets with CRC/Align Error Statistic Register"]
1826pub mod RMON_R_CRC_ALIGN {
1827 #[doc = "Number of receive packets with CRC or align error"]
1828 pub mod COUNT {
1829 pub const offset: u32 = 0;
1830 pub const mask: u32 = 0xffff << offset;
1831 pub mod R {}
1832 pub mod W {}
1833 pub mod RW {}
1834 }
1835}
1836#[doc = "Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register"]
1837pub mod RMON_R_UNDERSIZE {
1838 #[doc = "Number of receive packets with less than 64 bytes and good CRC"]
1839 pub mod COUNT {
1840 pub const offset: u32 = 0;
1841 pub const mask: u32 = 0xffff << offset;
1842 pub mod R {}
1843 pub mod W {}
1844 pub mod RW {}
1845 }
1846}
1847#[doc = "Rx Packets Greater Than MAX_FL and Good CRC Statistic Register"]
1848pub mod RMON_R_OVERSIZE {
1849 #[doc = "Number of receive packets greater than MAX_FL and good CRC"]
1850 pub mod COUNT {
1851 pub const offset: u32 = 0;
1852 pub const mask: u32 = 0xffff << offset;
1853 pub mod R {}
1854 pub mod W {}
1855 pub mod RW {}
1856 }
1857}
1858#[doc = "Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register"]
1859pub mod RMON_R_FRAG {
1860 #[doc = "Number of receive packets with less than 64 bytes and bad CRC"]
1861 pub mod COUNT {
1862 pub const offset: u32 = 0;
1863 pub const mask: u32 = 0xffff << offset;
1864 pub mod R {}
1865 pub mod W {}
1866 pub mod RW {}
1867 }
1868}
1869#[doc = "Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register"]
1870pub mod RMON_R_JAB {
1871 #[doc = "Number of receive packets greater than MAX_FL and bad CRC"]
1872 pub mod COUNT {
1873 pub const offset: u32 = 0;
1874 pub const mask: u32 = 0xffff << offset;
1875 pub mod R {}
1876 pub mod W {}
1877 pub mod RW {}
1878 }
1879}
1880#[doc = "Rx 64-Byte Packets Statistic Register"]
1881pub mod RMON_R_P64 {
1882 #[doc = "Number of 64-byte receive packets"]
1883 pub mod COUNT {
1884 pub const offset: u32 = 0;
1885 pub const mask: u32 = 0xffff << offset;
1886 pub mod R {}
1887 pub mod W {}
1888 pub mod RW {}
1889 }
1890}
1891#[doc = "Rx 65- to 127-Byte Packets Statistic Register"]
1892pub mod RMON_R_P65TO127 {
1893 #[doc = "Number of 65- to 127-byte recieve packets"]
1894 pub mod COUNT {
1895 pub const offset: u32 = 0;
1896 pub const mask: u32 = 0xffff << offset;
1897 pub mod R {}
1898 pub mod W {}
1899 pub mod RW {}
1900 }
1901}
1902#[doc = "Rx 128- to 255-Byte Packets Statistic Register"]
1903pub mod RMON_R_P128TO255 {
1904 #[doc = "Number of 128- to 255-byte recieve packets"]
1905 pub mod COUNT {
1906 pub const offset: u32 = 0;
1907 pub const mask: u32 = 0xffff << offset;
1908 pub mod R {}
1909 pub mod W {}
1910 pub mod RW {}
1911 }
1912}
1913#[doc = "Rx 256- to 511-Byte Packets Statistic Register"]
1914pub mod RMON_R_P256TO511 {
1915 #[doc = "Number of 256- to 511-byte recieve packets"]
1916 pub mod COUNT {
1917 pub const offset: u32 = 0;
1918 pub const mask: u32 = 0xffff << offset;
1919 pub mod R {}
1920 pub mod W {}
1921 pub mod RW {}
1922 }
1923}
1924#[doc = "Rx 512- to 1023-Byte Packets Statistic Register"]
1925pub mod RMON_R_P512TO1023 {
1926 #[doc = "Number of 512- to 1023-byte recieve packets"]
1927 pub mod COUNT {
1928 pub const offset: u32 = 0;
1929 pub const mask: u32 = 0xffff << offset;
1930 pub mod R {}
1931 pub mod W {}
1932 pub mod RW {}
1933 }
1934}
1935#[doc = "Rx 1024- to 2047-Byte Packets Statistic Register"]
1936pub mod RMON_R_P1024TO2047 {
1937 #[doc = "Number of 1024- to 2047-byte recieve packets"]
1938 pub mod COUNT {
1939 pub const offset: u32 = 0;
1940 pub const mask: u32 = 0xffff << offset;
1941 pub mod R {}
1942 pub mod W {}
1943 pub mod RW {}
1944 }
1945}
1946#[doc = "Rx Packets Greater than 2048 Bytes Statistic Register"]
1947pub mod RMON_R_P_GTE2048 {
1948 #[doc = "Number of greater-than-2048-byte recieve packets"]
1949 pub mod COUNT {
1950 pub const offset: u32 = 0;
1951 pub const mask: u32 = 0xffff << offset;
1952 pub mod R {}
1953 pub mod W {}
1954 pub mod RW {}
1955 }
1956}
1957#[doc = "Rx Octets Statistic Register"]
1958pub mod RMON_R_OCTETS {
1959 #[doc = "Number of receive octets"]
1960 pub mod COUNT {
1961 pub const offset: u32 = 0;
1962 pub const mask: u32 = 0xffff_ffff << offset;
1963 pub mod R {}
1964 pub mod W {}
1965 pub mod RW {}
1966 }
1967}
1968#[doc = "Frames not Counted Correctly Statistic Register"]
1969pub mod IEEE_R_DROP {
1970 #[doc = "Frame count"]
1971 pub mod COUNT {
1972 pub const offset: u32 = 0;
1973 pub const mask: u32 = 0xffff << offset;
1974 pub mod R {}
1975 pub mod W {}
1976 pub mod RW {}
1977 }
1978}
1979#[doc = "Frames Received OK Statistic Register"]
1980pub mod IEEE_R_FRAME_OK {
1981 #[doc = "Number of frames received OK"]
1982 pub mod COUNT {
1983 pub const offset: u32 = 0;
1984 pub const mask: u32 = 0xffff << offset;
1985 pub mod R {}
1986 pub mod W {}
1987 pub mod RW {}
1988 }
1989}
1990#[doc = "Frames Received with CRC Error Statistic Register"]
1991pub mod IEEE_R_CRC {
1992 #[doc = "Number of frames received with CRC error"]
1993 pub mod COUNT {
1994 pub const offset: u32 = 0;
1995 pub const mask: u32 = 0xffff << offset;
1996 pub mod R {}
1997 pub mod W {}
1998 pub mod RW {}
1999 }
2000}
2001#[doc = "Frames Received with Alignment Error Statistic Register"]
2002pub mod IEEE_R_ALIGN {
2003 #[doc = "Number of frames received with alignment error"]
2004 pub mod COUNT {
2005 pub const offset: u32 = 0;
2006 pub const mask: u32 = 0xffff << offset;
2007 pub mod R {}
2008 pub mod W {}
2009 pub mod RW {}
2010 }
2011}
2012#[doc = "Receive FIFO Overflow Count Statistic Register"]
2013pub mod IEEE_R_MACERR {
2014 #[doc = "Receive FIFO overflow count"]
2015 pub mod COUNT {
2016 pub const offset: u32 = 0;
2017 pub const mask: u32 = 0xffff << offset;
2018 pub mod R {}
2019 pub mod W {}
2020 pub mod RW {}
2021 }
2022}
2023#[doc = "Flow Control Pause Frames Received Statistic Register"]
2024pub mod IEEE_R_FDXFC {
2025 #[doc = "Number of flow-control pause frames received"]
2026 pub mod COUNT {
2027 pub const offset: u32 = 0;
2028 pub const mask: u32 = 0xffff << offset;
2029 pub mod R {}
2030 pub mod W {}
2031 pub mod RW {}
2032 }
2033}
2034#[doc = "Octet Count for Frames Received without Error Statistic Register"]
2035pub mod IEEE_R_OCTETS_OK {
2036 #[doc = "Number of octets for frames received without error"]
2037 pub mod COUNT {
2038 pub const offset: u32 = 0;
2039 pub const mask: u32 = 0xffff_ffff << offset;
2040 pub mod R {}
2041 pub mod W {}
2042 pub mod RW {}
2043 }
2044}
2045#[doc = "Adjustable Timer Control Register"]
2046pub mod ATCR {
2047 #[doc = "Enable Timer"]
2048 pub mod EN {
2049 pub const offset: u32 = 0;
2050 pub const mask: u32 = 0x01 << offset;
2051 pub mod R {}
2052 pub mod W {}
2053 pub mod RW {
2054 #[doc = "The timer stops at the current value."]
2055 pub const EN_0: u32 = 0;
2056 #[doc = "The timer starts incrementing."]
2057 pub const EN_1: u32 = 0x01;
2058 }
2059 }
2060 #[doc = "Enable One-Shot Offset Event"]
2061 pub mod OFFEN {
2062 pub const offset: u32 = 2;
2063 pub const mask: u32 = 0x01 << offset;
2064 pub mod R {}
2065 pub mod W {}
2066 pub mod RW {
2067 #[doc = "Disable."]
2068 pub const OFFEN_0: u32 = 0;
2069 #[doc = "The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field."]
2070 pub const OFFEN_1: u32 = 0x01;
2071 }
2072 }
2073 #[doc = "Reset Timer On Offset Event"]
2074 pub mod OFFRST {
2075 pub const offset: u32 = 3;
2076 pub const mask: u32 = 0x01 << offset;
2077 pub mod R {}
2078 pub mod W {}
2079 pub mod RW {
2080 #[doc = "The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached."]
2081 pub const OFFRST_0: u32 = 0;
2082 #[doc = "If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt."]
2083 pub const OFFRST_1: u32 = 0x01;
2084 }
2085 }
2086 #[doc = "Enable Periodical Event"]
2087 pub mod PEREN {
2088 pub const offset: u32 = 4;
2089 pub const mask: u32 = 0x01 << offset;
2090 pub mod R {}
2091 pub mod W {}
2092 pub mod RW {
2093 #[doc = "Disable."]
2094 pub const PEREN_0: u32 = 0;
2095 #[doc = "A period event interrupt can be generated (EIR\\[TS_TIMER\\]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details."]
2096 pub const PEREN_1: u32 = 0x01;
2097 }
2098 }
2099 #[doc = "Enables event signal output assertion on period event"]
2100 pub mod PINPER {
2101 pub const offset: u32 = 7;
2102 pub const mask: u32 = 0x01 << offset;
2103 pub mod R {}
2104 pub mod W {}
2105 pub mod RW {
2106 #[doc = "Disable."]
2107 pub const PINPER_0: u32 = 0;
2108 #[doc = "Enable."]
2109 pub const PINPER_1: u32 = 0x01;
2110 }
2111 }
2112 #[doc = "Reset Timer"]
2113 pub mod RESTART {
2114 pub const offset: u32 = 9;
2115 pub const mask: u32 = 0x01 << offset;
2116 pub mod R {}
2117 pub mod W {}
2118 pub mod RW {}
2119 }
2120 #[doc = "Capture Timer Value"]
2121 pub mod CAPTURE {
2122 pub const offset: u32 = 11;
2123 pub const mask: u32 = 0x01 << offset;
2124 pub mod R {}
2125 pub mod W {}
2126 pub mod RW {
2127 #[doc = "No effect."]
2128 pub const CAPTURE_0: u32 = 0;
2129 #[doc = "The current time is captured and can be read from the ATVR register."]
2130 pub const CAPTURE_1: u32 = 0x01;
2131 }
2132 }
2133 #[doc = "Enable Timer Slave Mode"]
2134 pub mod SLAVE {
2135 pub const offset: u32 = 13;
2136 pub const mask: u32 = 0x01 << offset;
2137 pub mod R {}
2138 pub mod W {}
2139 pub mod RW {
2140 #[doc = "The timer is active and all configuration fields in this register are relevant."]
2141 pub const SLAVE_0: u32 = 0;
2142 #[doc = "The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value."]
2143 pub const SLAVE_1: u32 = 0x01;
2144 }
2145 }
2146}
2147#[doc = "Timer Value Register"]
2148pub mod ATVR {
2149 #[doc = "A write sets the timer"]
2150 pub mod ATIME {
2151 pub const offset: u32 = 0;
2152 pub const mask: u32 = 0xffff_ffff << offset;
2153 pub mod R {}
2154 pub mod W {}
2155 pub mod RW {}
2156 }
2157}
2158#[doc = "Timer Offset Register"]
2159pub mod ATOFF {
2160 #[doc = "Offset value for one-shot event generation"]
2161 pub mod OFFSET {
2162 pub const offset: u32 = 0;
2163 pub const mask: u32 = 0xffff_ffff << offset;
2164 pub mod R {}
2165 pub mod W {}
2166 pub mod RW {}
2167 }
2168}
2169#[doc = "Timer Period Register"]
2170pub mod ATPER {
2171 #[doc = "Value for generating periodic events"]
2172 pub mod PERIOD {
2173 pub const offset: u32 = 0;
2174 pub const mask: u32 = 0xffff_ffff << offset;
2175 pub mod R {}
2176 pub mod W {}
2177 pub mod RW {}
2178 }
2179}
2180#[doc = "Timer Correction Register"]
2181pub mod ATCOR {
2182 #[doc = "Correction Counter Wrap-Around Value"]
2183 pub mod COR {
2184 pub const offset: u32 = 0;
2185 pub const mask: u32 = 0x7fff_ffff << offset;
2186 pub mod R {}
2187 pub mod W {}
2188 pub mod RW {}
2189 }
2190}
2191#[doc = "Time-Stamping Clock Period Register"]
2192pub mod ATINC {
2193 #[doc = "Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds"]
2194 pub mod INC {
2195 pub const offset: u32 = 0;
2196 pub const mask: u32 = 0x7f << offset;
2197 pub mod R {}
2198 pub mod W {}
2199 pub mod RW {}
2200 }
2201 #[doc = "Correction Increment Value"]
2202 pub mod INC_CORR {
2203 pub const offset: u32 = 8;
2204 pub const mask: u32 = 0x7f << offset;
2205 pub mod R {}
2206 pub mod W {}
2207 pub mod RW {}
2208 }
2209}
2210#[doc = "Timestamp of Last Transmitted Frame"]
2211pub mod ATSTMP {
2212 #[doc = "Timestamp of the last frame transmitted by the core that had TxBD\\[TS\\] set"]
2213 pub mod TIMESTAMP {
2214 pub const offset: u32 = 0;
2215 pub const mask: u32 = 0xffff_ffff << offset;
2216 pub mod R {}
2217 pub mod W {}
2218 pub mod RW {}
2219 }
2220}
2221#[doc = "Timer Global Status Register"]
2222pub mod TGSR {
2223 #[doc = "Copy Of Timer Flag For Channel 0"]
2224 pub mod TF0 {
2225 pub const offset: u32 = 0;
2226 pub const mask: u32 = 0x01 << offset;
2227 pub mod R {}
2228 pub mod W {}
2229 pub mod RW {
2230 #[doc = "Timer Flag for Channel 0 is clear"]
2231 pub const TF0_0: u32 = 0;
2232 #[doc = "Timer Flag for Channel 0 is set"]
2233 pub const TF0_1: u32 = 0x01;
2234 }
2235 }
2236 #[doc = "Copy Of Timer Flag For Channel 1"]
2237 pub mod TF1 {
2238 pub const offset: u32 = 1;
2239 pub const mask: u32 = 0x01 << offset;
2240 pub mod R {}
2241 pub mod W {}
2242 pub mod RW {
2243 #[doc = "Timer Flag for Channel 1 is clear"]
2244 pub const TF1_0: u32 = 0;
2245 #[doc = "Timer Flag for Channel 1 is set"]
2246 pub const TF1_1: u32 = 0x01;
2247 }
2248 }
2249 #[doc = "Copy Of Timer Flag For Channel 2"]
2250 pub mod TF2 {
2251 pub const offset: u32 = 2;
2252 pub const mask: u32 = 0x01 << offset;
2253 pub mod R {}
2254 pub mod W {}
2255 pub mod RW {
2256 #[doc = "Timer Flag for Channel 2 is clear"]
2257 pub const TF2_0: u32 = 0;
2258 #[doc = "Timer Flag for Channel 2 is set"]
2259 pub const TF2_1: u32 = 0x01;
2260 }
2261 }
2262 #[doc = "Copy Of Timer Flag For Channel 3"]
2263 pub mod TF3 {
2264 pub const offset: u32 = 3;
2265 pub const mask: u32 = 0x01 << offset;
2266 pub mod R {}
2267 pub mod W {}
2268 pub mod RW {
2269 #[doc = "Timer Flag for Channel 3 is clear"]
2270 pub const TF3_0: u32 = 0;
2271 #[doc = "Timer Flag for Channel 3 is set"]
2272 pub const TF3_1: u32 = 0x01;
2273 }
2274 }
2275}
2276#[doc = "Timer Control Status Register"]
2277pub mod TCSR0 {
2278 #[doc = "Timer DMA Request Enable"]
2279 pub mod TDRE {
2280 pub const offset: u32 = 0;
2281 pub const mask: u32 = 0x01 << offset;
2282 pub mod R {}
2283 pub mod W {}
2284 pub mod RW {
2285 #[doc = "DMA request is disabled"]
2286 pub const TDRE_0: u32 = 0;
2287 #[doc = "DMA request is enabled"]
2288 pub const TDRE_1: u32 = 0x01;
2289 }
2290 }
2291 #[doc = "Timer Mode"]
2292 pub mod TMODE {
2293 pub const offset: u32 = 2;
2294 pub const mask: u32 = 0x0f << offset;
2295 pub mod R {}
2296 pub mod W {}
2297 pub mod RW {
2298 #[doc = "Timer Channel is disabled."]
2299 pub const TMODE_0: u32 = 0;
2300 #[doc = "Timer Channel is configured for Input Capture on rising edge."]
2301 pub const TMODE_1: u32 = 0x01;
2302 #[doc = "Timer Channel is configured for Input Capture on falling edge."]
2303 pub const TMODE_2: u32 = 0x02;
2304 #[doc = "Timer Channel is configured for Input Capture on both edges."]
2305 pub const TMODE_3: u32 = 0x03;
2306 #[doc = "Timer Channel is configured for Output Compare - software only."]
2307 pub const TMODE_4: u32 = 0x04;
2308 #[doc = "Timer Channel is configured for Output Compare - toggle output on compare."]
2309 pub const TMODE_5: u32 = 0x05;
2310 #[doc = "Timer Channel is configured for Output Compare - clear output on compare."]
2311 pub const TMODE_6: u32 = 0x06;
2312 #[doc = "Timer Channel is configured for Output Compare - set output on compare."]
2313 pub const TMODE_7: u32 = 0x07;
2314 #[doc = "Timer Channel is configured for Output Compare - set output on compare, clear output on overflow."]
2315 pub const TMODE_9: u32 = 0x09;
2316 #[doc = "Timer Channel is configured for Output Compare - clear output on compare, set output on overflow."]
2317 pub const TMODE_10: u32 = 0x0a;
2318 #[doc = "Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC."]
2319 pub const TMODE_14: u32 = 0x0e;
2320 #[doc = "Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC."]
2321 pub const TMODE_15: u32 = 0x0f;
2322 }
2323 }
2324 #[doc = "Timer Interrupt Enable"]
2325 pub mod TIE {
2326 pub const offset: u32 = 6;
2327 pub const mask: u32 = 0x01 << offset;
2328 pub mod R {}
2329 pub mod W {}
2330 pub mod RW {
2331 #[doc = "Interrupt is disabled"]
2332 pub const TIE_0: u32 = 0;
2333 #[doc = "Interrupt is enabled"]
2334 pub const TIE_1: u32 = 0x01;
2335 }
2336 }
2337 #[doc = "Timer Flag"]
2338 pub mod TF {
2339 pub const offset: u32 = 7;
2340 pub const mask: u32 = 0x01 << offset;
2341 pub mod R {}
2342 pub mod W {}
2343 pub mod RW {
2344 #[doc = "Input Capture or Output Compare has not occurred."]
2345 pub const TF_0: u32 = 0;
2346 #[doc = "Input Capture or Output Compare has occurred."]
2347 pub const TF_1: u32 = 0x01;
2348 }
2349 }
2350 #[doc = "Timer PulseWidth Control"]
2351 pub mod TPWC {
2352 pub const offset: u32 = 11;
2353 pub const mask: u32 = 0x1f << offset;
2354 pub mod R {}
2355 pub mod W {}
2356 pub mod RW {
2357 #[doc = "Pulse width is one 1588-clock cycle."]
2358 pub const TPWC_0: u32 = 0;
2359 #[doc = "Pulse width is two 1588-clock cycles."]
2360 pub const TPWC_1: u32 = 0x01;
2361 #[doc = "Pulse width is three 1588-clock cycles."]
2362 pub const TPWC_2: u32 = 0x02;
2363 #[doc = "Pulse width is four 1588-clock cycles."]
2364 pub const TPWC_3: u32 = 0x03;
2365 #[doc = "Pulse width is 32 1588-clock cycles."]
2366 pub const TPWC_31: u32 = 0x1f;
2367 }
2368 }
2369}
2370#[doc = "Timer Compare Capture Register"]
2371pub mod TCCR0 {
2372 #[doc = "Timer Capture Compare"]
2373 pub mod TCC {
2374 pub const offset: u32 = 0;
2375 pub const mask: u32 = 0xffff_ffff << offset;
2376 pub mod R {}
2377 pub mod W {}
2378 pub mod RW {}
2379 }
2380}
2381#[doc = "Timer Control Status Register"]
2382pub mod TCSR1 {
2383 #[doc = "Timer DMA Request Enable"]
2384 pub mod TDRE {
2385 pub const offset: u32 = 0;
2386 pub const mask: u32 = 0x01 << offset;
2387 pub mod R {}
2388 pub mod W {}
2389 pub mod RW {
2390 #[doc = "DMA request is disabled"]
2391 pub const TDRE_0: u32 = 0;
2392 #[doc = "DMA request is enabled"]
2393 pub const TDRE_1: u32 = 0x01;
2394 }
2395 }
2396 #[doc = "Timer Mode"]
2397 pub mod TMODE {
2398 pub const offset: u32 = 2;
2399 pub const mask: u32 = 0x0f << offset;
2400 pub mod R {}
2401 pub mod W {}
2402 pub mod RW {
2403 #[doc = "Timer Channel is disabled."]
2404 pub const TMODE_0: u32 = 0;
2405 #[doc = "Timer Channel is configured for Input Capture on rising edge."]
2406 pub const TMODE_1: u32 = 0x01;
2407 #[doc = "Timer Channel is configured for Input Capture on falling edge."]
2408 pub const TMODE_2: u32 = 0x02;
2409 #[doc = "Timer Channel is configured for Input Capture on both edges."]
2410 pub const TMODE_3: u32 = 0x03;
2411 #[doc = "Timer Channel is configured for Output Compare - software only."]
2412 pub const TMODE_4: u32 = 0x04;
2413 #[doc = "Timer Channel is configured for Output Compare - toggle output on compare."]
2414 pub const TMODE_5: u32 = 0x05;
2415 #[doc = "Timer Channel is configured for Output Compare - clear output on compare."]
2416 pub const TMODE_6: u32 = 0x06;
2417 #[doc = "Timer Channel is configured for Output Compare - set output on compare."]
2418 pub const TMODE_7: u32 = 0x07;
2419 #[doc = "Timer Channel is configured for Output Compare - set output on compare, clear output on overflow."]
2420 pub const TMODE_9: u32 = 0x09;
2421 #[doc = "Timer Channel is configured for Output Compare - clear output on compare, set output on overflow."]
2422 pub const TMODE_10: u32 = 0x0a;
2423 #[doc = "Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC."]
2424 pub const TMODE_14: u32 = 0x0e;
2425 #[doc = "Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC."]
2426 pub const TMODE_15: u32 = 0x0f;
2427 }
2428 }
2429 #[doc = "Timer Interrupt Enable"]
2430 pub mod TIE {
2431 pub const offset: u32 = 6;
2432 pub const mask: u32 = 0x01 << offset;
2433 pub mod R {}
2434 pub mod W {}
2435 pub mod RW {
2436 #[doc = "Interrupt is disabled"]
2437 pub const TIE_0: u32 = 0;
2438 #[doc = "Interrupt is enabled"]
2439 pub const TIE_1: u32 = 0x01;
2440 }
2441 }
2442 #[doc = "Timer Flag"]
2443 pub mod TF {
2444 pub const offset: u32 = 7;
2445 pub const mask: u32 = 0x01 << offset;
2446 pub mod R {}
2447 pub mod W {}
2448 pub mod RW {
2449 #[doc = "Input Capture or Output Compare has not occurred."]
2450 pub const TF_0: u32 = 0;
2451 #[doc = "Input Capture or Output Compare has occurred."]
2452 pub const TF_1: u32 = 0x01;
2453 }
2454 }
2455 #[doc = "Timer PulseWidth Control"]
2456 pub mod TPWC {
2457 pub const offset: u32 = 11;
2458 pub const mask: u32 = 0x1f << offset;
2459 pub mod R {}
2460 pub mod W {}
2461 pub mod RW {
2462 #[doc = "Pulse width is one 1588-clock cycle."]
2463 pub const TPWC_0: u32 = 0;
2464 #[doc = "Pulse width is two 1588-clock cycles."]
2465 pub const TPWC_1: u32 = 0x01;
2466 #[doc = "Pulse width is three 1588-clock cycles."]
2467 pub const TPWC_2: u32 = 0x02;
2468 #[doc = "Pulse width is four 1588-clock cycles."]
2469 pub const TPWC_3: u32 = 0x03;
2470 #[doc = "Pulse width is 32 1588-clock cycles."]
2471 pub const TPWC_31: u32 = 0x1f;
2472 }
2473 }
2474}
2475#[doc = "Timer Compare Capture Register"]
2476pub mod TCCR1 {
2477 #[doc = "Timer Capture Compare"]
2478 pub mod TCC {
2479 pub const offset: u32 = 0;
2480 pub const mask: u32 = 0xffff_ffff << offset;
2481 pub mod R {}
2482 pub mod W {}
2483 pub mod RW {}
2484 }
2485}
2486#[doc = "Timer Control Status Register"]
2487pub mod TCSR2 {
2488 #[doc = "Timer DMA Request Enable"]
2489 pub mod TDRE {
2490 pub const offset: u32 = 0;
2491 pub const mask: u32 = 0x01 << offset;
2492 pub mod R {}
2493 pub mod W {}
2494 pub mod RW {
2495 #[doc = "DMA request is disabled"]
2496 pub const TDRE_0: u32 = 0;
2497 #[doc = "DMA request is enabled"]
2498 pub const TDRE_1: u32 = 0x01;
2499 }
2500 }
2501 #[doc = "Timer Mode"]
2502 pub mod TMODE {
2503 pub const offset: u32 = 2;
2504 pub const mask: u32 = 0x0f << offset;
2505 pub mod R {}
2506 pub mod W {}
2507 pub mod RW {
2508 #[doc = "Timer Channel is disabled."]
2509 pub const TMODE_0: u32 = 0;
2510 #[doc = "Timer Channel is configured for Input Capture on rising edge."]
2511 pub const TMODE_1: u32 = 0x01;
2512 #[doc = "Timer Channel is configured for Input Capture on falling edge."]
2513 pub const TMODE_2: u32 = 0x02;
2514 #[doc = "Timer Channel is configured for Input Capture on both edges."]
2515 pub const TMODE_3: u32 = 0x03;
2516 #[doc = "Timer Channel is configured for Output Compare - software only."]
2517 pub const TMODE_4: u32 = 0x04;
2518 #[doc = "Timer Channel is configured for Output Compare - toggle output on compare."]
2519 pub const TMODE_5: u32 = 0x05;
2520 #[doc = "Timer Channel is configured for Output Compare - clear output on compare."]
2521 pub const TMODE_6: u32 = 0x06;
2522 #[doc = "Timer Channel is configured for Output Compare - set output on compare."]
2523 pub const TMODE_7: u32 = 0x07;
2524 #[doc = "Timer Channel is configured for Output Compare - set output on compare, clear output on overflow."]
2525 pub const TMODE_9: u32 = 0x09;
2526 #[doc = "Timer Channel is configured for Output Compare - clear output on compare, set output on overflow."]
2527 pub const TMODE_10: u32 = 0x0a;
2528 #[doc = "Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC."]
2529 pub const TMODE_14: u32 = 0x0e;
2530 #[doc = "Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC."]
2531 pub const TMODE_15: u32 = 0x0f;
2532 }
2533 }
2534 #[doc = "Timer Interrupt Enable"]
2535 pub mod TIE {
2536 pub const offset: u32 = 6;
2537 pub const mask: u32 = 0x01 << offset;
2538 pub mod R {}
2539 pub mod W {}
2540 pub mod RW {
2541 #[doc = "Interrupt is disabled"]
2542 pub const TIE_0: u32 = 0;
2543 #[doc = "Interrupt is enabled"]
2544 pub const TIE_1: u32 = 0x01;
2545 }
2546 }
2547 #[doc = "Timer Flag"]
2548 pub mod TF {
2549 pub const offset: u32 = 7;
2550 pub const mask: u32 = 0x01 << offset;
2551 pub mod R {}
2552 pub mod W {}
2553 pub mod RW {
2554 #[doc = "Input Capture or Output Compare has not occurred."]
2555 pub const TF_0: u32 = 0;
2556 #[doc = "Input Capture or Output Compare has occurred."]
2557 pub const TF_1: u32 = 0x01;
2558 }
2559 }
2560 #[doc = "Timer PulseWidth Control"]
2561 pub mod TPWC {
2562 pub const offset: u32 = 11;
2563 pub const mask: u32 = 0x1f << offset;
2564 pub mod R {}
2565 pub mod W {}
2566 pub mod RW {
2567 #[doc = "Pulse width is one 1588-clock cycle."]
2568 pub const TPWC_0: u32 = 0;
2569 #[doc = "Pulse width is two 1588-clock cycles."]
2570 pub const TPWC_1: u32 = 0x01;
2571 #[doc = "Pulse width is three 1588-clock cycles."]
2572 pub const TPWC_2: u32 = 0x02;
2573 #[doc = "Pulse width is four 1588-clock cycles."]
2574 pub const TPWC_3: u32 = 0x03;
2575 #[doc = "Pulse width is 32 1588-clock cycles."]
2576 pub const TPWC_31: u32 = 0x1f;
2577 }
2578 }
2579}
2580#[doc = "Timer Compare Capture Register"]
2581pub mod TCCR2 {
2582 #[doc = "Timer Capture Compare"]
2583 pub mod TCC {
2584 pub const offset: u32 = 0;
2585 pub const mask: u32 = 0xffff_ffff << offset;
2586 pub mod R {}
2587 pub mod W {}
2588 pub mod RW {}
2589 }
2590}
2591#[doc = "Timer Control Status Register"]
2592pub mod TCSR3 {
2593 #[doc = "Timer DMA Request Enable"]
2594 pub mod TDRE {
2595 pub const offset: u32 = 0;
2596 pub const mask: u32 = 0x01 << offset;
2597 pub mod R {}
2598 pub mod W {}
2599 pub mod RW {
2600 #[doc = "DMA request is disabled"]
2601 pub const TDRE_0: u32 = 0;
2602 #[doc = "DMA request is enabled"]
2603 pub const TDRE_1: u32 = 0x01;
2604 }
2605 }
2606 #[doc = "Timer Mode"]
2607 pub mod TMODE {
2608 pub const offset: u32 = 2;
2609 pub const mask: u32 = 0x0f << offset;
2610 pub mod R {}
2611 pub mod W {}
2612 pub mod RW {
2613 #[doc = "Timer Channel is disabled."]
2614 pub const TMODE_0: u32 = 0;
2615 #[doc = "Timer Channel is configured for Input Capture on rising edge."]
2616 pub const TMODE_1: u32 = 0x01;
2617 #[doc = "Timer Channel is configured for Input Capture on falling edge."]
2618 pub const TMODE_2: u32 = 0x02;
2619 #[doc = "Timer Channel is configured for Input Capture on both edges."]
2620 pub const TMODE_3: u32 = 0x03;
2621 #[doc = "Timer Channel is configured for Output Compare - software only."]
2622 pub const TMODE_4: u32 = 0x04;
2623 #[doc = "Timer Channel is configured for Output Compare - toggle output on compare."]
2624 pub const TMODE_5: u32 = 0x05;
2625 #[doc = "Timer Channel is configured for Output Compare - clear output on compare."]
2626 pub const TMODE_6: u32 = 0x06;
2627 #[doc = "Timer Channel is configured for Output Compare - set output on compare."]
2628 pub const TMODE_7: u32 = 0x07;
2629 #[doc = "Timer Channel is configured for Output Compare - set output on compare, clear output on overflow."]
2630 pub const TMODE_9: u32 = 0x09;
2631 #[doc = "Timer Channel is configured for Output Compare - clear output on compare, set output on overflow."]
2632 pub const TMODE_10: u32 = 0x0a;
2633 #[doc = "Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC."]
2634 pub const TMODE_14: u32 = 0x0e;
2635 #[doc = "Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC."]
2636 pub const TMODE_15: u32 = 0x0f;
2637 }
2638 }
2639 #[doc = "Timer Interrupt Enable"]
2640 pub mod TIE {
2641 pub const offset: u32 = 6;
2642 pub const mask: u32 = 0x01 << offset;
2643 pub mod R {}
2644 pub mod W {}
2645 pub mod RW {
2646 #[doc = "Interrupt is disabled"]
2647 pub const TIE_0: u32 = 0;
2648 #[doc = "Interrupt is enabled"]
2649 pub const TIE_1: u32 = 0x01;
2650 }
2651 }
2652 #[doc = "Timer Flag"]
2653 pub mod TF {
2654 pub const offset: u32 = 7;
2655 pub const mask: u32 = 0x01 << offset;
2656 pub mod R {}
2657 pub mod W {}
2658 pub mod RW {
2659 #[doc = "Input Capture or Output Compare has not occurred."]
2660 pub const TF_0: u32 = 0;
2661 #[doc = "Input Capture or Output Compare has occurred."]
2662 pub const TF_1: u32 = 0x01;
2663 }
2664 }
2665 #[doc = "Timer PulseWidth Control"]
2666 pub mod TPWC {
2667 pub const offset: u32 = 11;
2668 pub const mask: u32 = 0x1f << offset;
2669 pub mod R {}
2670 pub mod W {}
2671 pub mod RW {
2672 #[doc = "Pulse width is one 1588-clock cycle."]
2673 pub const TPWC_0: u32 = 0;
2674 #[doc = "Pulse width is two 1588-clock cycles."]
2675 pub const TPWC_1: u32 = 0x01;
2676 #[doc = "Pulse width is three 1588-clock cycles."]
2677 pub const TPWC_2: u32 = 0x02;
2678 #[doc = "Pulse width is four 1588-clock cycles."]
2679 pub const TPWC_3: u32 = 0x03;
2680 #[doc = "Pulse width is 32 1588-clock cycles."]
2681 pub const TPWC_31: u32 = 0x1f;
2682 }
2683 }
2684}
2685#[doc = "Timer Compare Capture Register"]
2686pub mod TCCR3 {
2687 #[doc = "Timer Capture Compare"]
2688 pub mod TCC {
2689 pub const offset: u32 = 0;
2690 pub const mask: u32 = 0xffff_ffff << offset;
2691 pub mod R {}
2692 pub mod W {}
2693 pub mod RW {}
2694 }
2695}