imxrt_ral/blocks/imxrt1061/
flexspi.rs1#[doc = "FlexSPI"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "Module Control Register 0"]
5 pub MCR0: crate::RWRegister<u32>,
6 #[doc = "Module Control Register 1"]
7 pub MCR1: crate::RWRegister<u32>,
8 #[doc = "Module Control Register 2"]
9 pub MCR2: crate::RWRegister<u32>,
10 #[doc = "AHB Bus Control Register"]
11 pub AHBCR: crate::RWRegister<u32>,
12 #[doc = "Interrupt Enable Register"]
13 pub INTEN: crate::RWRegister<u32>,
14 #[doc = "Interrupt Register"]
15 pub INTR: crate::RWRegister<u32>,
16 #[doc = "LUT Key Register"]
17 pub LUTKEY: crate::RWRegister<u32>,
18 #[doc = "LUT Control Register"]
19 pub LUTCR: crate::RWRegister<u32>,
20 #[doc = "AHB RX Buffer 0 Control Register 0"]
21 pub AHBRXBUF0CR0: crate::RWRegister<u32>,
22 #[doc = "AHB RX Buffer 1 Control Register 0"]
23 pub AHBRXBUF1CR0: crate::RWRegister<u32>,
24 #[doc = "AHB RX Buffer 2 Control Register 0"]
25 pub AHBRXBUF2CR0: crate::RWRegister<u32>,
26 #[doc = "AHB RX Buffer 3 Control Register 0"]
27 pub AHBRXBUF3CR0: crate::RWRegister<u32>,
28 _reserved0: [u8; 0x30],
29 #[doc = "Flash A1 Control Register 0"]
30 pub FLSHA1CR0: crate::RWRegister<u32>,
31 #[doc = "Flash A2 Control Register 0"]
32 pub FLSHA2CR0: crate::RWRegister<u32>,
33 #[doc = "Flash B1 Control Register 0"]
34 pub FLSHB1CR0: crate::RWRegister<u32>,
35 #[doc = "Flash B2 Control Register 0"]
36 pub FLSHB2CR0: crate::RWRegister<u32>,
37 #[doc = "Flash A1 Control Register 1"]
38 pub FLSHCR1: [crate::RWRegister<u32>; 4usize],
39 #[doc = "Flash A1 Control Register 2"]
40 pub FLSHCR2: [crate::RWRegister<u32>; 4usize],
41 _reserved1: [u8; 0x04],
42 #[doc = "Flash Control Register 4"]
43 pub FLSHCR4: crate::RWRegister<u32>,
44 _reserved2: [u8; 0x08],
45 #[doc = "IP Control Register 0"]
46 pub IPCR0: crate::RWRegister<u32>,
47 #[doc = "IP Control Register 1"]
48 pub IPCR1: crate::RWRegister<u32>,
49 _reserved3: [u8; 0x08],
50 #[doc = "IP Command Register"]
51 pub IPCMD: crate::RWRegister<u32>,
52 _reserved4: [u8; 0x04],
53 #[doc = "IP RX FIFO Control Register"]
54 pub IPRXFCR: crate::RWRegister<u32>,
55 #[doc = "IP TX FIFO Control Register"]
56 pub IPTXFCR: crate::RWRegister<u32>,
57 #[doc = "DLL Control Register 0"]
58 pub DLLCR: [crate::RWRegister<u32>; 2usize],
59 _reserved5: [u8; 0x18],
60 #[doc = "Status Register 0"]
61 pub STS0: crate::RORegister<u32>,
62 #[doc = "Status Register 1"]
63 pub STS1: crate::RORegister<u32>,
64 #[doc = "Status Register 2"]
65 pub STS2: crate::RORegister<u32>,
66 #[doc = "AHB Suspend Status Register"]
67 pub AHBSPNDSTS: crate::RORegister<u32>,
68 #[doc = "IP RX FIFO Status Register"]
69 pub IPRXFSTS: crate::RORegister<u32>,
70 #[doc = "IP TX FIFO Status Register"]
71 pub IPTXFSTS: crate::RORegister<u32>,
72 _reserved6: [u8; 0x08],
73 #[doc = "IP RX FIFO Data Register 0"]
74 pub RFDR: [crate::RORegister<u32>; 32usize],
75 #[doc = "IP TX FIFO Data Register 0"]
76 pub TFDR: [crate::WORegister<u32>; 32usize],
77 #[doc = "LUT 0"]
78 pub LUT: [crate::RWRegister<u32>; 64usize],
79}
80#[doc = "Module Control Register 0"]
81pub mod MCR0 {
82 #[doc = "Software Reset"]
83 pub mod SWRESET {
84 pub const offset: u32 = 0;
85 pub const mask: u32 = 0x01 << offset;
86 pub mod R {}
87 pub mod W {}
88 pub mod RW {}
89 }
90 #[doc = "Module Disable"]
91 pub mod MDIS {
92 pub const offset: u32 = 1;
93 pub const mask: u32 = 0x01 << offset;
94 pub mod R {}
95 pub mod W {}
96 pub mod RW {}
97 }
98 #[doc = "Sample Clock source selection for Flash Reading"]
99 pub mod RXCLKSRC {
100 pub const offset: u32 = 4;
101 pub const mask: u32 = 0x03 << offset;
102 pub mod R {}
103 pub mod W {}
104 pub mod RW {
105 #[doc = "Dummy Read strobe generated by FlexSPI Controller and loopback internally."]
106 pub const RXCLKSRC_0: u32 = 0;
107 #[doc = "Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad."]
108 pub const RXCLKSRC_1: u32 = 0x01;
109 #[doc = "Flash provided Read strobe and input from DQS pad"]
110 pub const RXCLKSRC_3: u32 = 0x03;
111 }
112 }
113 #[doc = "Enable AHB bus Read Access to IP RX FIFO."]
114 pub mod ARDFEN {
115 pub const offset: u32 = 6;
116 pub const mask: u32 = 0x01 << offset;
117 pub mod R {}
118 pub mod W {}
119 pub mod RW {
120 #[doc = "IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response."]
121 pub const ARDFEN_0: u32 = 0;
122 #[doc = "IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response."]
123 pub const ARDFEN_1: u32 = 0x01;
124 }
125 }
126 #[doc = "Enable AHB bus Write Access to IP TX FIFO."]
127 pub mod ATDFEN {
128 pub const offset: u32 = 7;
129 pub const mask: u32 = 0x01 << offset;
130 pub mod R {}
131 pub mod W {}
132 pub mod RW {
133 #[doc = "IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response."]
134 pub const ATDFEN_0: u32 = 0;
135 #[doc = "IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response."]
136 pub const ATDFEN_1: u32 = 0x01;
137 }
138 }
139 #[doc = "The serial root clock could be divided inside FlexSPI . Refer Clocks chapter for more details on clocking."]
140 pub mod SERCLKDIV {
141 pub const offset: u32 = 8;
142 pub const mask: u32 = 0x07 << offset;
143 pub mod R {}
144 pub mod W {}
145 pub mod RW {
146 #[doc = "Divided by 1"]
147 pub const SERCLKDIV_0: u32 = 0;
148 #[doc = "Divided by 2"]
149 pub const SERCLKDIV_1: u32 = 0x01;
150 #[doc = "Divided by 3"]
151 pub const SERCLKDIV_2: u32 = 0x02;
152 #[doc = "Divided by 4"]
153 pub const SERCLKDIV_3: u32 = 0x03;
154 #[doc = "Divided by 5"]
155 pub const SERCLKDIV_4: u32 = 0x04;
156 #[doc = "Divided by 6"]
157 pub const SERCLKDIV_5: u32 = 0x05;
158 #[doc = "Divided by 7"]
159 pub const SERCLKDIV_6: u32 = 0x06;
160 #[doc = "Divided by 8"]
161 pub const SERCLKDIV_7: u32 = 0x07;
162 }
163 }
164 #[doc = "Half Speed Serial Flash access Enable."]
165 pub mod HSEN {
166 pub const offset: u32 = 11;
167 pub const mask: u32 = 0x01 << offset;
168 pub mod R {}
169 pub mod W {}
170 pub mod RW {
171 #[doc = "Disable divide by 2 of serial flash clock for half speed commands."]
172 pub const HSEN_0: u32 = 0;
173 #[doc = "Enable divide by 2 of serial flash clock for half speed commands."]
174 pub const HSEN_1: u32 = 0x01;
175 }
176 }
177 #[doc = "Doze mode enable bit"]
178 pub mod DOZEEN {
179 pub const offset: u32 = 12;
180 pub const mask: u32 = 0x01 << offset;
181 pub mod R {}
182 pub mod W {}
183 pub mod RW {
184 #[doc = "Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system."]
185 pub const DOZEEN_0: u32 = 0;
186 #[doc = "Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system."]
187 pub const DOZEEN_1: u32 = 0x01;
188 }
189 }
190 #[doc = "This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA\\[3:0\\] and B_DATA\\[3:0\\])."]
191 pub mod COMBINATIONEN {
192 pub const offset: u32 = 13;
193 pub const mask: u32 = 0x01 << offset;
194 pub mod R {}
195 pub mod W {}
196 pub mod RW {
197 #[doc = "Disable."]
198 pub const COMBINATIONEN_0: u32 = 0;
199 #[doc = "Enable."]
200 pub const COMBINATIONEN_1: u32 = 0x01;
201 }
202 }
203 #[doc = "This bit is used to force SCLK output free-running. For FPGA applications, external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0\\[RXCLKSRC\\]=2)."]
204 pub mod SCKFREERUNEN {
205 pub const offset: u32 = 14;
206 pub const mask: u32 = 0x01 << offset;
207 pub mod R {}
208 pub mod W {}
209 pub mod RW {
210 #[doc = "Disable."]
211 pub const SCKFREERUNEN_0: u32 = 0;
212 #[doc = "Enable."]
213 pub const SCKFREERUNEN_1: u32 = 0x01;
214 }
215 }
216 #[doc = "Time out wait cycle for IP command grant."]
217 pub mod IPGRANTWAIT {
218 pub const offset: u32 = 16;
219 pub const mask: u32 = 0xff << offset;
220 pub mod R {}
221 pub mod W {}
222 pub mod RW {}
223 }
224 #[doc = "Timeout wait cycle for AHB command grant."]
225 pub mod AHBGRANTWAIT {
226 pub const offset: u32 = 24;
227 pub const mask: u32 = 0xff << offset;
228 pub mod R {}
229 pub mod W {}
230 pub mod RW {}
231 }
232}
233#[doc = "Module Control Register 1"]
234pub mod MCR1 {
235 #[doc = "AHB Read/Write access to Serial Flash Memory space will timeout if not data received from Flash or data not transmitted after AHBBUSWAIT * 1024 ahb clock cycles, AHB Bus will get an error response"]
236 pub mod AHBBUSWAIT {
237 pub const offset: u32 = 0;
238 pub const mask: u32 = 0xffff << offset;
239 pub mod R {}
240 pub mod W {}
241 pub mod RW {}
242 }
243 #[doc = "Command Sequence Execution will timeout and abort after SEQWAIT * 1024 Serial Root Clock cycles"]
244 pub mod SEQWAIT {
245 pub const offset: u32 = 16;
246 pub const mask: u32 = 0xffff << offset;
247 pub mod R {}
248 pub mod W {}
249 pub mod RW {}
250 }
251}
252#[doc = "Module Control Register 2"]
253pub mod MCR2 {
254 #[doc = "This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid."]
255 pub mod CLRAHBBUFOPT {
256 pub const offset: u32 = 11;
257 pub const mask: u32 = 0x01 << offset;
258 pub mod R {}
259 pub mod W {}
260 pub mod RW {
261 #[doc = "AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK."]
262 pub const CLRAHBBUFOPT_0: u32 = 0;
263 #[doc = "AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK."]
264 pub const CLRAHBBUFOPT_1: u32 = 0x01;
265 }
266 }
267 #[doc = "The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1. This bit will be auto-cleared immediately."]
268 pub mod CLRLEARNPHASE {
269 pub const offset: u32 = 14;
270 pub const mask: u32 = 0x01 << offset;
271 pub mod R {}
272 pub mod W {}
273 pub mod RW {}
274 }
275 #[doc = "All external devices are same devices (both in types and size) for A1/A2/B1/B2."]
276 pub mod SAMEDEVICEEN {
277 pub const offset: u32 = 15;
278 pub const mask: u32 = 0x01 << offset;
279 pub mod R {}
280 pub mod W {}
281 pub mod RW {
282 #[doc = "In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be ignored."]
283 pub const SAMEDEVICEEN_0: u32 = 0;
284 #[doc = "FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored."]
285 pub const SAMEDEVICEEN_1: u32 = 0x01;
286 }
287 }
288 #[doc = "B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to A_SCLK). In this case, port B flash access is not available. After changing the value of this field, MCR0\\[SWRESET\\] should be set."]
289 pub mod SCKBDIFFOPT {
290 pub const offset: u32 = 19;
291 pub const mask: u32 = 0x01 << offset;
292 pub mod R {}
293 pub mod W {}
294 pub mod RW {
295 #[doc = "B_SCLK pad is used as port B SCLK clock output. Port B flash access is available."]
296 pub const SCKBDIFFOPT_0: u32 = 0;
297 #[doc = "B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is not available."]
298 pub const SCKBDIFFOPT_1: u32 = 0x01;
299 }
300 }
301 #[doc = "Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed."]
302 pub mod RESUMEWAIT {
303 pub const offset: u32 = 24;
304 pub const mask: u32 = 0xff << offset;
305 pub mod R {}
306 pub mod W {}
307 pub mod RW {}
308 }
309}
310#[doc = "AHB Bus Control Register"]
311pub mod AHBCR {
312 #[doc = "Parallel mode enabled for AHB triggered Command (both read and write) ."]
313 pub mod APAREN {
314 pub const offset: u32 = 0;
315 pub const mask: u32 = 0x01 << offset;
316 pub mod R {}
317 pub mod W {}
318 pub mod RW {
319 #[doc = "Flash will be accessed in Individual mode."]
320 pub const APAREN_0: u32 = 0;
321 #[doc = "Flash will be accessed in Parallel mode."]
322 pub const APAREN_1: u32 = 0x01;
323 }
324 }
325 #[doc = "Enable AHB bus cachable read access support."]
326 pub mod CACHABLEEN {
327 pub const offset: u32 = 3;
328 pub const mask: u32 = 0x01 << offset;
329 pub mod R {}
330 pub mod W {}
331 pub mod RW {
332 #[doc = "Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer."]
333 pub const CACHABLEEN_0: u32 = 0;
334 #[doc = "Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first."]
335 pub const CACHABLEEN_1: u32 = 0x01;
336 }
337 }
338 #[doc = "Enable AHB bus bufferable write access support. This field affects the last beat of AHB write access, refer for more details about AHB bufferable write."]
339 pub mod BUFFERABLEEN {
340 pub const offset: u32 = 4;
341 pub const mask: u32 = 0x01 << offset;
342 pub mod R {}
343 pub mod W {}
344 pub mod RW {
345 #[doc = "Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus ready after all data is transmitted to External device and AHB command finished."]
346 pub const BUFFERABLEEN_0: u32 = 0;
347 #[doc = "Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is granted by arbitrator and will not wait for AHB command finished."]
348 pub const BUFFERABLEEN_1: u32 = 0x01;
349 }
350 }
351 #[doc = "AHB Read Prefetch Enable."]
352 pub mod PREFETCHEN {
353 pub const offset: u32 = 5;
354 pub const mask: u32 = 0x01 << offset;
355 pub mod R {}
356 pub mod W {}
357 pub mod RW {}
358 }
359 #[doc = "AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation."]
360 pub mod READADDROPT {
361 pub const offset: u32 = 6;
362 pub const mask: u32 = 0x01 << offset;
363 pub mod R {}
364 pub mod W {}
365 pub mod RW {
366 #[doc = "There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable."]
367 pub const READADDROPT_0: u32 = 0;
368 #[doc = "There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB burst required to meet the alignment requirement."]
369 pub const READADDROPT_1: u32 = 0x01;
370 }
371 }
372}
373#[doc = "Interrupt Enable Register"]
374pub mod INTEN {
375 #[doc = "IP triggered Command Sequences Execution finished interrupt enable."]
376 pub mod IPCMDDONEEN {
377 pub const offset: u32 = 0;
378 pub const mask: u32 = 0x01 << offset;
379 pub mod R {}
380 pub mod W {}
381 pub mod RW {}
382 }
383 #[doc = "IP triggered Command Sequences Grant Timeout interrupt enable."]
384 pub mod IPCMDGEEN {
385 pub const offset: u32 = 1;
386 pub const mask: u32 = 0x01 << offset;
387 pub mod R {}
388 pub mod W {}
389 pub mod RW {}
390 }
391 #[doc = "AHB triggered Command Sequences Grant Timeout interrupt enable."]
392 pub mod AHBCMDGEEN {
393 pub const offset: u32 = 2;
394 pub const mask: u32 = 0x01 << offset;
395 pub mod R {}
396 pub mod W {}
397 pub mod RW {}
398 }
399 #[doc = "IP triggered Command Sequences Error Detected interrupt enable."]
400 pub mod IPCMDERREN {
401 pub const offset: u32 = 3;
402 pub const mask: u32 = 0x01 << offset;
403 pub mod R {}
404 pub mod W {}
405 pub mod RW {}
406 }
407 #[doc = "AHB triggered Command Sequences Error Detected interrupt enable."]
408 pub mod AHBCMDERREN {
409 pub const offset: u32 = 4;
410 pub const mask: u32 = 0x01 << offset;
411 pub mod R {}
412 pub mod W {}
413 pub mod RW {}
414 }
415 #[doc = "IP RX FIFO WaterMark available interrupt enable."]
416 pub mod IPRXWAEN {
417 pub const offset: u32 = 5;
418 pub const mask: u32 = 0x01 << offset;
419 pub mod R {}
420 pub mod W {}
421 pub mod RW {}
422 }
423 #[doc = "IP TX FIFO WaterMark empty interrupt enable."]
424 pub mod IPTXWEEN {
425 pub const offset: u32 = 6;
426 pub const mask: u32 = 0x01 << offset;
427 pub mod R {}
428 pub mod W {}
429 pub mod RW {}
430 }
431 #[doc = "SCK is stopped during command sequence because Async RX FIFO full interrupt enable."]
432 pub mod SCKSTOPBYRDEN {
433 pub const offset: u32 = 8;
434 pub const mask: u32 = 0x01 << offset;
435 pub mod R {}
436 pub mod W {}
437 pub mod RW {}
438 }
439 #[doc = "SCK is stopped during command sequence because Async TX FIFO empty interrupt enable."]
440 pub mod SCKSTOPBYWREN {
441 pub const offset: u32 = 9;
442 pub const mask: u32 = 0x01 << offset;
443 pub mod R {}
444 pub mod W {}
445 pub mod RW {}
446 }
447 #[doc = "AHB Bus timeout interrupt.Refer Interrupts chapter for more details."]
448 pub mod AHBBUSTIMEOUTEN {
449 pub const offset: u32 = 10;
450 pub const mask: u32 = 0x01 << offset;
451 pub mod R {}
452 pub mod W {}
453 pub mod RW {}
454 }
455 #[doc = "Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details."]
456 pub mod SEQTIMEOUTEN {
457 pub const offset: u32 = 11;
458 pub const mask: u32 = 0x01 << offset;
459 pub mod R {}
460 pub mod W {}
461 pub mod RW {}
462 }
463}
464#[doc = "Interrupt Register"]
465pub mod INTR {
466 #[doc = "IP triggered Command Sequences Execution finished interrupt. This interrupt is also generated when there is IPCMDGE or IPCMDERR interrupt generated."]
467 pub mod IPCMDDONE {
468 pub const offset: u32 = 0;
469 pub const mask: u32 = 0x01 << offset;
470 pub mod R {}
471 pub mod W {}
472 pub mod RW {}
473 }
474 #[doc = "IP triggered Command Sequences Grant Timeout interrupt."]
475 pub mod IPCMDGE {
476 pub const offset: u32 = 1;
477 pub const mask: u32 = 0x01 << offset;
478 pub mod R {}
479 pub mod W {}
480 pub mod RW {}
481 }
482 #[doc = "AHB triggered Command Sequences Grant Timeout interrupt."]
483 pub mod AHBCMDGE {
484 pub const offset: u32 = 2;
485 pub const mask: u32 = 0x01 << offset;
486 pub mod R {}
487 pub mod W {}
488 pub mod RW {}
489 }
490 #[doc = "IP triggered Command Sequences Error Detected interrupt. When an error detected for IP command, this command will be ignored and not executed at all."]
491 pub mod IPCMDERR {
492 pub const offset: u32 = 3;
493 pub const mask: u32 = 0x01 << offset;
494 pub mod R {}
495 pub mod W {}
496 pub mod RW {}
497 }
498 #[doc = "AHB triggered Command Sequences Error Detected interrupt. When an error detected for AHB command, this command will be ignored and not executed at all."]
499 pub mod AHBCMDERR {
500 pub const offset: u32 = 4;
501 pub const mask: u32 = 0x01 << offset;
502 pub mod R {}
503 pub mod W {}
504 pub mod RW {}
505 }
506 #[doc = "IP RX FIFO watermark available interrupt."]
507 pub mod IPRXWA {
508 pub const offset: u32 = 5;
509 pub const mask: u32 = 0x01 << offset;
510 pub mod R {}
511 pub mod W {}
512 pub mod RW {}
513 }
514 #[doc = "IP TX FIFO watermark empty interrupt."]
515 pub mod IPTXWE {
516 pub const offset: u32 = 6;
517 pub const mask: u32 = 0x01 << offset;
518 pub mod R {}
519 pub mod W {}
520 pub mod RW {}
521 }
522 #[doc = "SCK is stopped during command sequence because Async RX FIFO full interrupt."]
523 pub mod SCKSTOPBYRD {
524 pub const offset: u32 = 8;
525 pub const mask: u32 = 0x01 << offset;
526 pub mod R {}
527 pub mod W {}
528 pub mod RW {}
529 }
530 #[doc = "SCK is stopped during command sequence because Async TX FIFO empty interrupt."]
531 pub mod SCKSTOPBYWR {
532 pub const offset: u32 = 9;
533 pub const mask: u32 = 0x01 << offset;
534 pub mod R {}
535 pub mod W {}
536 pub mod RW {}
537 }
538 #[doc = "AHB Bus timeout interrupt.Refer Interrupts chapter for more details."]
539 pub mod AHBBUSTIMEOUT {
540 pub const offset: u32 = 10;
541 pub const mask: u32 = 0x01 << offset;
542 pub mod R {}
543 pub mod W {}
544 pub mod RW {}
545 }
546 #[doc = "Sequence execution timeout interrupt."]
547 pub mod SEQTIMEOUT {
548 pub const offset: u32 = 11;
549 pub const mask: u32 = 0x01 << offset;
550 pub mod R {}
551 pub mod W {}
552 pub mod RW {}
553 }
554}
555#[doc = "LUT Key Register"]
556pub mod LUTKEY {
557 #[doc = "The Key to lock or unlock LUT."]
558 pub mod KEY {
559 pub const offset: u32 = 0;
560 pub const mask: u32 = 0xffff_ffff << offset;
561 pub mod R {}
562 pub mod W {}
563 pub mod RW {}
564 }
565}
566#[doc = "LUT Control Register"]
567pub mod LUTCR {
568 #[doc = "Lock LUT"]
569 pub mod LOCK {
570 pub const offset: u32 = 0;
571 pub const mask: u32 = 0x01 << offset;
572 pub mod R {}
573 pub mod W {}
574 pub mod RW {}
575 }
576 #[doc = "Unlock LUT"]
577 pub mod UNLOCK {
578 pub const offset: u32 = 1;
579 pub const mask: u32 = 0x01 << offset;
580 pub mod R {}
581 pub mod W {}
582 pub mod RW {}
583 }
584}
585#[doc = "AHB RX Buffer 0 Control Register 0"]
586pub mod AHBRXBUF0CR0 {
587 #[doc = "AHB RX Buffer Size in 64 bits."]
588 pub mod BUFSZ {
589 pub const offset: u32 = 0;
590 pub const mask: u32 = 0xff << offset;
591 pub mod R {}
592 pub mod W {}
593 pub mod RW {}
594 }
595 #[doc = "This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)."]
596 pub mod MSTRID {
597 pub const offset: u32 = 16;
598 pub const mask: u32 = 0x0f << offset;
599 pub mod R {}
600 pub mod W {}
601 pub mod RW {}
602 }
603 #[doc = "This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest."]
604 pub mod PRIORITY {
605 pub const offset: u32 = 24;
606 pub const mask: u32 = 0x03 << offset;
607 pub mod R {}
608 pub mod W {}
609 pub mod RW {}
610 }
611 #[doc = "AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master."]
612 pub mod PREFETCHEN {
613 pub const offset: u32 = 31;
614 pub const mask: u32 = 0x01 << offset;
615 pub mod R {}
616 pub mod W {}
617 pub mod RW {}
618 }
619}
620#[doc = "AHB RX Buffer 1 Control Register 0"]
621pub mod AHBRXBUF1CR0 {
622 #[doc = "AHB RX Buffer Size in 64 bits."]
623 pub mod BUFSZ {
624 pub const offset: u32 = 0;
625 pub const mask: u32 = 0xff << offset;
626 pub mod R {}
627 pub mod W {}
628 pub mod RW {}
629 }
630 #[doc = "This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)."]
631 pub mod MSTRID {
632 pub const offset: u32 = 16;
633 pub const mask: u32 = 0x0f << offset;
634 pub mod R {}
635 pub mod W {}
636 pub mod RW {}
637 }
638 #[doc = "This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest."]
639 pub mod PRIORITY {
640 pub const offset: u32 = 24;
641 pub const mask: u32 = 0x03 << offset;
642 pub mod R {}
643 pub mod W {}
644 pub mod RW {}
645 }
646 #[doc = "AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master."]
647 pub mod PREFETCHEN {
648 pub const offset: u32 = 31;
649 pub const mask: u32 = 0x01 << offset;
650 pub mod R {}
651 pub mod W {}
652 pub mod RW {}
653 }
654}
655#[doc = "AHB RX Buffer 2 Control Register 0"]
656pub mod AHBRXBUF2CR0 {
657 #[doc = "AHB RX Buffer Size in 64 bits."]
658 pub mod BUFSZ {
659 pub const offset: u32 = 0;
660 pub const mask: u32 = 0xff << offset;
661 pub mod R {}
662 pub mod W {}
663 pub mod RW {}
664 }
665 #[doc = "This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)."]
666 pub mod MSTRID {
667 pub const offset: u32 = 16;
668 pub const mask: u32 = 0x0f << offset;
669 pub mod R {}
670 pub mod W {}
671 pub mod RW {}
672 }
673 #[doc = "This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest."]
674 pub mod PRIORITY {
675 pub const offset: u32 = 24;
676 pub const mask: u32 = 0x03 << offset;
677 pub mod R {}
678 pub mod W {}
679 pub mod RW {}
680 }
681 #[doc = "AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master."]
682 pub mod PREFETCHEN {
683 pub const offset: u32 = 31;
684 pub const mask: u32 = 0x01 << offset;
685 pub mod R {}
686 pub mod W {}
687 pub mod RW {}
688 }
689}
690#[doc = "AHB RX Buffer 3 Control Register 0"]
691pub mod AHBRXBUF3CR0 {
692 #[doc = "AHB RX Buffer Size in 64 bits."]
693 pub mod BUFSZ {
694 pub const offset: u32 = 0;
695 pub const mask: u32 = 0xff << offset;
696 pub mod R {}
697 pub mod W {}
698 pub mod RW {}
699 }
700 #[doc = "This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)."]
701 pub mod MSTRID {
702 pub const offset: u32 = 16;
703 pub const mask: u32 = 0x0f << offset;
704 pub mod R {}
705 pub mod W {}
706 pub mod RW {}
707 }
708 #[doc = "This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest."]
709 pub mod PRIORITY {
710 pub const offset: u32 = 24;
711 pub const mask: u32 = 0x03 << offset;
712 pub mod R {}
713 pub mod W {}
714 pub mod RW {}
715 }
716 #[doc = "AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master."]
717 pub mod PREFETCHEN {
718 pub const offset: u32 = 31;
719 pub const mask: u32 = 0x01 << offset;
720 pub mod R {}
721 pub mod W {}
722 pub mod RW {}
723 }
724}
725#[doc = "Flash A1 Control Register 0"]
726pub mod FLSHA1CR0 {
727 #[doc = "Flash Size in KByte."]
728 pub mod FLSHSZ {
729 pub const offset: u32 = 0;
730 pub const mask: u32 = 0x007f_ffff << offset;
731 pub mod R {}
732 pub mod W {}
733 pub mod RW {}
734 }
735}
736#[doc = "Flash A2 Control Register 0"]
737pub mod FLSHA2CR0 {
738 #[doc = "Flash Size in KByte."]
739 pub mod FLSHSZ {
740 pub const offset: u32 = 0;
741 pub const mask: u32 = 0x007f_ffff << offset;
742 pub mod R {}
743 pub mod W {}
744 pub mod RW {}
745 }
746}
747#[doc = "Flash B1 Control Register 0"]
748pub mod FLSHB1CR0 {
749 #[doc = "Flash Size in KByte."]
750 pub mod FLSHSZ {
751 pub const offset: u32 = 0;
752 pub const mask: u32 = 0x007f_ffff << offset;
753 pub mod R {}
754 pub mod W {}
755 pub mod RW {}
756 }
757}
758#[doc = "Flash B2 Control Register 0"]
759pub mod FLSHB2CR0 {
760 #[doc = "Flash Size in KByte."]
761 pub mod FLSHSZ {
762 pub const offset: u32 = 0;
763 pub const mask: u32 = 0x007f_ffff << offset;
764 pub mod R {}
765 pub mod W {}
766 pub mod RW {}
767 }
768}
769#[doc = "Flash A1 Control Register 1"]
770pub mod FLSHCR1 {
771 #[doc = "Serial Flash CS setup time."]
772 pub mod TCSS {
773 pub const offset: u32 = 0;
774 pub const mask: u32 = 0x1f << offset;
775 pub mod R {}
776 pub mod W {}
777 pub mod RW {}
778 }
779 #[doc = "Serial Flash CS Hold time."]
780 pub mod TCSH {
781 pub const offset: u32 = 5;
782 pub const mask: u32 = 0x1f << offset;
783 pub mod R {}
784 pub mod W {}
785 pub mod RW {}
786 }
787 #[doc = "Word Addressable."]
788 pub mod WA {
789 pub const offset: u32 = 10;
790 pub const mask: u32 = 0x01 << offset;
791 pub mod R {}
792 pub mod W {}
793 pub mod RW {}
794 }
795 #[doc = "Column Address Size."]
796 pub mod CAS {
797 pub const offset: u32 = 11;
798 pub const mask: u32 = 0x0f << offset;
799 pub mod R {}
800 pub mod W {}
801 pub mod RW {}
802 }
803 #[doc = "CS interval unit"]
804 pub mod CSINTERVALUNIT {
805 pub const offset: u32 = 15;
806 pub const mask: u32 = 0x01 << offset;
807 pub mod R {}
808 pub mod W {}
809 pub mod RW {
810 #[doc = "The CS interval unit is 1 serial clock cycle"]
811 pub const CSINTERVALUNIT_0: u32 = 0;
812 #[doc = "The CS interval unit is 256 serial clock cycle"]
813 pub const CSINTERVALUNIT_1: u32 = 0x01;
814 }
815 }
816 #[doc = "This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion. If external flash has a limitation on the interval between command sequences, this field should be set accordingly. If there is no limitation, set this field with value 0x0."]
817 pub mod CSINTERVAL {
818 pub const offset: u32 = 16;
819 pub const mask: u32 = 0xffff << offset;
820 pub mod R {}
821 pub mod W {}
822 pub mod RW {}
823 }
824}
825#[doc = "Flash A1 Control Register 2"]
826pub mod FLSHCR2 {
827 #[doc = "Sequence Index for AHB Read triggered Command in LUT."]
828 pub mod ARDSEQID {
829 pub const offset: u32 = 0;
830 pub const mask: u32 = 0x0f << offset;
831 pub mod R {}
832 pub mod W {}
833 pub mod RW {}
834 }
835 #[doc = "Sequence Number for AHB Read triggered Command in LUT."]
836 pub mod ARDSEQNUM {
837 pub const offset: u32 = 5;
838 pub const mask: u32 = 0x07 << offset;
839 pub mod R {}
840 pub mod W {}
841 pub mod RW {}
842 }
843 #[doc = "Sequence Index for AHB Write triggered Command."]
844 pub mod AWRSEQID {
845 pub const offset: u32 = 8;
846 pub const mask: u32 = 0x0f << offset;
847 pub mod R {}
848 pub mod W {}
849 pub mod RW {}
850 }
851 #[doc = "Sequence Number for AHB Write triggered Command."]
852 pub mod AWRSEQNUM {
853 pub const offset: u32 = 13;
854 pub const mask: u32 = 0x07 << offset;
855 pub mod R {}
856 pub mod W {}
857 pub mod RW {}
858 }
859 #[doc = "For certain devices (such as FPGA), it need some time to write data into internal memory after the command sequences finished on FlexSPI interface"]
860 pub mod AWRWAIT {
861 pub const offset: u32 = 16;
862 pub const mask: u32 = 0x0fff << offset;
863 pub mod R {}
864 pub mod W {}
865 pub mod RW {}
866 }
867 #[doc = "AWRWAIT unit"]
868 pub mod AWRWAITUNIT {
869 pub const offset: u32 = 28;
870 pub const mask: u32 = 0x07 << offset;
871 pub mod R {}
872 pub mod W {}
873 pub mod RW {
874 #[doc = "The AWRWAIT unit is 2 ahb clock cycle"]
875 pub const AWRWAITUNIT_0: u32 = 0;
876 #[doc = "The AWRWAIT unit is 8 ahb clock cycle"]
877 pub const AWRWAITUNIT_1: u32 = 0x01;
878 #[doc = "The AWRWAIT unit is 32 ahb clock cycle"]
879 pub const AWRWAITUNIT_2: u32 = 0x02;
880 #[doc = "The AWRWAIT unit is 128 ahb clock cycle"]
881 pub const AWRWAITUNIT_3: u32 = 0x03;
882 #[doc = "The AWRWAIT unit is 512 ahb clock cycle"]
883 pub const AWRWAITUNIT_4: u32 = 0x04;
884 #[doc = "The AWRWAIT unit is 2048 ahb clock cycle"]
885 pub const AWRWAITUNIT_5: u32 = 0x05;
886 #[doc = "The AWRWAIT unit is 8192 ahb clock cycle"]
887 pub const AWRWAITUNIT_6: u32 = 0x06;
888 #[doc = "The AWRWAIT unit is 32768 ahb clock cycle"]
889 pub const AWRWAITUNIT_7: u32 = 0x07;
890 }
891 }
892 #[doc = "Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. Refer Programmable Sequence Engine for details."]
893 pub mod CLRINSTRPTR {
894 pub const offset: u32 = 31;
895 pub const mask: u32 = 0x01 << offset;
896 pub mod R {}
897 pub mod W {}
898 pub mod RW {}
899 }
900}
901#[doc = "Flash Control Register 4"]
902pub mod FLSHCR4 {
903 #[doc = "Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation."]
904 pub mod WMOPT1 {
905 pub const offset: u32 = 0;
906 pub const mask: u32 = 0x01 << offset;
907 pub mod R {}
908 pub mod W {}
909 pub mod RW {
910 #[doc = "DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write burst start address alignment when flash is accessed in individual mode."]
911 pub const WMOPT1_0: u32 = 0;
912 #[doc = "DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write burst start address alignment when flash is accessed in individual mode."]
913 pub const WMOPT1_1: u32 = 0x01;
914 }
915 }
916 #[doc = "Write mask enable bit for flash device on port A. When write mask function is needed for memory device on port A, this bit must be set."]
917 pub mod WMENA {
918 pub const offset: u32 = 2;
919 pub const mask: u32 = 0x01 << offset;
920 pub mod R {}
921 pub mod W {}
922 pub mod RW {
923 #[doc = "Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device."]
924 pub const WMENA_0: u32 = 0;
925 #[doc = "Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device."]
926 pub const WMENA_1: u32 = 0x01;
927 }
928 }
929 #[doc = "Write mask enable bit for flash device on port B. When write mask function is needed for memory device on port B, this bit must be set."]
930 pub mod WMENB {
931 pub const offset: u32 = 3;
932 pub const mask: u32 = 0x01 << offset;
933 pub mod R {}
934 pub mod W {}
935 pub mod RW {
936 #[doc = "Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device."]
937 pub const WMENB_0: u32 = 0;
938 #[doc = "Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device."]
939 pub const WMENB_1: u32 = 0x01;
940 }
941 }
942}
943#[doc = "IP Control Register 0"]
944pub mod IPCR0 {
945 #[doc = "Serial Flash Address for IP command."]
946 pub mod SFAR {
947 pub const offset: u32 = 0;
948 pub const mask: u32 = 0xffff_ffff << offset;
949 pub mod R {}
950 pub mod W {}
951 pub mod RW {}
952 }
953}
954#[doc = "IP Control Register 1"]
955pub mod IPCR1 {
956 #[doc = "Flash Read/Program Data Size (in Bytes) for IP command."]
957 pub mod IDATSZ {
958 pub const offset: u32 = 0;
959 pub const mask: u32 = 0xffff << offset;
960 pub mod R {}
961 pub mod W {}
962 pub mod RW {}
963 }
964 #[doc = "Sequence Index in LUT for IP command."]
965 pub mod ISEQID {
966 pub const offset: u32 = 16;
967 pub const mask: u32 = 0x0f << offset;
968 pub mod R {}
969 pub mod W {}
970 pub mod RW {}
971 }
972 #[doc = "Sequence Number for IP command: ISEQNUM+1."]
973 pub mod ISEQNUM {
974 pub const offset: u32 = 24;
975 pub const mask: u32 = 0x07 << offset;
976 pub mod R {}
977 pub mod W {}
978 pub mod RW {}
979 }
980 #[doc = "Parallel mode Enabled for IP command."]
981 pub mod IPAREN {
982 pub const offset: u32 = 31;
983 pub const mask: u32 = 0x01 << offset;
984 pub mod R {}
985 pub mod W {}
986 pub mod RW {
987 #[doc = "Flash will be accessed in Individual mode."]
988 pub const IPAREN_0: u32 = 0;
989 #[doc = "Flash will be accessed in Parallel mode."]
990 pub const IPAREN_1: u32 = 0x01;
991 }
992 }
993}
994#[doc = "IP Command Register"]
995pub mod IPCMD {
996 #[doc = "Setting this bit will trigger an IP Command."]
997 pub mod TRG {
998 pub const offset: u32 = 0;
999 pub const mask: u32 = 0x01 << offset;
1000 pub mod R {}
1001 pub mod W {}
1002 pub mod RW {}
1003 }
1004}
1005#[doc = "IP RX FIFO Control Register"]
1006pub mod IPRXFCR {
1007 #[doc = "Clear all valid data entries in IP RX FIFO."]
1008 pub mod CLRIPRXF {
1009 pub const offset: u32 = 0;
1010 pub const mask: u32 = 0x01 << offset;
1011 pub mod R {}
1012 pub mod W {}
1013 pub mod RW {}
1014 }
1015 #[doc = "IP RX FIFO reading by DMA enabled."]
1016 pub mod RXDMAEN {
1017 pub const offset: u32 = 1;
1018 pub const mask: u32 = 0x01 << offset;
1019 pub mod R {}
1020 pub mod W {}
1021 pub mod RW {
1022 #[doc = "IP RX FIFO would be read by processor."]
1023 pub const RXDMAEN_0: u32 = 0;
1024 #[doc = "IP RX FIFO would be read by DMA."]
1025 pub const RXDMAEN_1: u32 = 0x01;
1026 }
1027 }
1028 #[doc = "Watermark level is (RXWMRK+1)*64 Bits."]
1029 pub mod RXWMRK {
1030 pub const offset: u32 = 2;
1031 pub const mask: u32 = 0x0f << offset;
1032 pub mod R {}
1033 pub mod W {}
1034 pub mod RW {}
1035 }
1036}
1037#[doc = "IP TX FIFO Control Register"]
1038pub mod IPTXFCR {
1039 #[doc = "Clear all valid data entries in IP TX FIFO."]
1040 pub mod CLRIPTXF {
1041 pub const offset: u32 = 0;
1042 pub const mask: u32 = 0x01 << offset;
1043 pub mod R {}
1044 pub mod W {}
1045 pub mod RW {}
1046 }
1047 #[doc = "IP TX FIFO filling by DMA enabled."]
1048 pub mod TXDMAEN {
1049 pub const offset: u32 = 1;
1050 pub const mask: u32 = 0x01 << offset;
1051 pub mod R {}
1052 pub mod W {}
1053 pub mod RW {
1054 #[doc = "IP TX FIFO would be filled by processor."]
1055 pub const TXDMAEN_0: u32 = 0;
1056 #[doc = "IP TX FIFO would be filled by DMA."]
1057 pub const TXDMAEN_1: u32 = 0x01;
1058 }
1059 }
1060 #[doc = "Watermark level is (TXWMRK+1)*64 Bits."]
1061 pub mod TXWMRK {
1062 pub const offset: u32 = 2;
1063 pub const mask: u32 = 0x0f << offset;
1064 pub mod R {}
1065 pub mod W {}
1066 pub mod RW {}
1067 }
1068}
1069#[doc = "DLL Control Register 0"]
1070pub mod DLLCR {
1071 #[doc = "DLL calibration enable."]
1072 pub mod DLLEN {
1073 pub const offset: u32 = 0;
1074 pub const mask: u32 = 0x01 << offset;
1075 pub mod R {}
1076 pub mod W {}
1077 pub mod RW {}
1078 }
1079 #[doc = "Software could force a reset on DLL by setting this field to 0x1. This will cause the DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset action is edge triggered, so software need to clear this bit after set this bit (no delay limitation)."]
1080 pub mod DLLRESET {
1081 pub const offset: u32 = 1;
1082 pub const mask: u32 = 0x01 << offset;
1083 pub mod R {}
1084 pub mod W {}
1085 pub mod RW {}
1086 }
1087 #[doc = "The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock). If serial root clock is >= 100 MHz, DLLEN set to 0x1, OVRDEN set to =0x0, then SLVDLYTARGET setting of 0xF is recommended."]
1088 pub mod SLVDLYTARGET {
1089 pub const offset: u32 = 3;
1090 pub const mask: u32 = 0x0f << offset;
1091 pub mod R {}
1092 pub mod W {}
1093 pub mod RW {}
1094 }
1095 #[doc = "Slave clock delay line delay cell number selection override enable."]
1096 pub mod OVRDEN {
1097 pub const offset: u32 = 8;
1098 pub const mask: u32 = 0x01 << offset;
1099 pub mod R {}
1100 pub mod W {}
1101 pub mod RW {}
1102 }
1103 #[doc = "Slave clock delay line delay cell number selection override value."]
1104 pub mod OVRDVAL {
1105 pub const offset: u32 = 9;
1106 pub const mask: u32 = 0x3f << offset;
1107 pub mod R {}
1108 pub mod W {}
1109 pub mod RW {}
1110 }
1111}
1112#[doc = "Status Register 0"]
1113pub mod STS0 {
1114 #[doc = "This status bit indicates the state machine in SEQ_CTL is idle and there is command sequence executing on FlexSPI interface."]
1115 pub mod SEQIDLE {
1116 pub const offset: u32 = 0;
1117 pub const mask: u32 = 0x01 << offset;
1118 pub mod R {}
1119 pub mod W {}
1120 pub mod RW {}
1121 }
1122 #[doc = "This status bit indicates the state machine in ARB_CTL is busy and there is command sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE."]
1123 pub mod ARBIDLE {
1124 pub const offset: u32 = 1;
1125 pub const mask: u32 = 0x01 << offset;
1126 pub mod R {}
1127 pub mod W {}
1128 pub mod RW {}
1129 }
1130 #[doc = "This status field indicates the trigger source of current command sequence granted by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0\\[ARBIDLE\\]=0x1)."]
1131 pub mod ARBCMDSRC {
1132 pub const offset: u32 = 2;
1133 pub const mask: u32 = 0x03 << offset;
1134 pub mod R {}
1135 pub mod W {}
1136 pub mod RW {
1137 #[doc = "Triggered by AHB read command (triggered by AHB read)."]
1138 pub const ARBCMDSRC_0: u32 = 0;
1139 #[doc = "Triggered by AHB write command (triggered by AHB Write)."]
1140 pub const ARBCMDSRC_1: u32 = 0x01;
1141 #[doc = "Triggered by IP command (triggered by setting register bit IPCMD.TRG)."]
1142 pub const ARBCMDSRC_2: u32 = 0x02;
1143 #[doc = "Triggered by suspended command (resumed)."]
1144 pub const ARBCMDSRC_3: u32 = 0x03;
1145 }
1146 }
1147}
1148#[doc = "Status Register 1"]
1149pub mod STS1 {
1150 #[doc = "Indicates the sequence index when an AHB command error is detected. This field will be cleared when INTR\\[AHBCMDERR\\] is write-1-clear(w1c)."]
1151 pub mod AHBCMDERRID {
1152 pub const offset: u32 = 0;
1153 pub const mask: u32 = 0x0f << offset;
1154 pub mod R {}
1155 pub mod W {}
1156 pub mod RW {}
1157 }
1158 #[doc = "Indicates the Error Code when AHB command Error detected. This field will be cleared when INTR\\[AHBCMDERR\\] is write-1-clear(w1c)."]
1159 pub mod AHBCMDERRCODE {
1160 pub const offset: u32 = 8;
1161 pub const mask: u32 = 0x0f << offset;
1162 pub mod R {}
1163 pub mod W {}
1164 pub mod RW {
1165 #[doc = "No error."]
1166 pub const AHBCMDERRCODE_0: u32 = 0;
1167 #[doc = "AHB Write command with JMP_ON_CS instruction used in the sequence."]
1168 pub const AHBCMDERRCODE_2: u32 = 0x02;
1169 #[doc = "There is unknown instruction opcode in the sequence."]
1170 pub const AHBCMDERRCODE_3: u32 = 0x03;
1171 #[doc = "Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence."]
1172 pub const AHBCMDERRCODE_4: u32 = 0x04;
1173 #[doc = "Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence."]
1174 pub const AHBCMDERRCODE_5: u32 = 0x05;
1175 #[doc = "Sequence execution timeout."]
1176 pub const AHBCMDERRCODE_14: u32 = 0x0e;
1177 }
1178 }
1179 #[doc = "Indicates the sequence Index when IP command error detected. This field will be cleared when INTR\\[IPCMDERR\\] is write-1-clear(w1c)."]
1180 pub mod IPCMDERRID {
1181 pub const offset: u32 = 16;
1182 pub const mask: u32 = 0x0f << offset;
1183 pub mod R {}
1184 pub mod W {}
1185 pub mod RW {}
1186 }
1187 #[doc = "Indicates the Error Code when IP command Error detected. This field will be cleared when INTR\\[IPCMDERR\\] is write-1-clear(w1c)."]
1188 pub mod IPCMDERRCODE {
1189 pub const offset: u32 = 24;
1190 pub const mask: u32 = 0x0f << offset;
1191 pub mod R {}
1192 pub mod W {}
1193 pub mod RW {
1194 #[doc = "No error."]
1195 pub const IPCMDERRCODE_0: u32 = 0;
1196 #[doc = "IP command with JMP_ON_CS instruction used in the sequence."]
1197 pub const IPCMDERRCODE_2: u32 = 0x02;
1198 #[doc = "There is unknown instruction opcode in the sequence."]
1199 pub const IPCMDERRCODE_3: u32 = 0x03;
1200 #[doc = "Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence."]
1201 pub const IPCMDERRCODE_4: u32 = 0x04;
1202 #[doc = "Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence."]
1203 pub const IPCMDERRCODE_5: u32 = 0x05;
1204 #[doc = "Flash access start address exceed the whole flash address range (A1/A2/B1/B2)."]
1205 pub const IPCMDERRCODE_6: u32 = 0x06;
1206 #[doc = "Sequence execution timeout."]
1207 pub const IPCMDERRCODE_14: u32 = 0x0e;
1208 #[doc = "Flash boundary crossed."]
1209 pub const IPCMDERRCODE_15: u32 = 0x0f;
1210 }
1211 }
1212}
1213#[doc = "Status Register 2"]
1214pub mod STS2 {
1215 #[doc = "Flash A sample clock slave delay line locked."]
1216 pub mod ASLVLOCK {
1217 pub const offset: u32 = 0;
1218 pub const mask: u32 = 0x01 << offset;
1219 pub mod R {}
1220 pub mod W {}
1221 pub mod RW {}
1222 }
1223 #[doc = "Flash A sample clock reference delay line locked."]
1224 pub mod AREFLOCK {
1225 pub const offset: u32 = 1;
1226 pub const mask: u32 = 0x01 << offset;
1227 pub mod R {}
1228 pub mod W {}
1229 pub mod RW {}
1230 }
1231 #[doc = "Flash A sample clock slave delay line delay cell number selection ."]
1232 pub mod ASLVSEL {
1233 pub const offset: u32 = 2;
1234 pub const mask: u32 = 0x3f << offset;
1235 pub mod R {}
1236 pub mod W {}
1237 pub mod RW {}
1238 }
1239 #[doc = "Flash A sample clock reference delay line delay cell number selection."]
1240 pub mod AREFSEL {
1241 pub const offset: u32 = 8;
1242 pub const mask: u32 = 0x3f << offset;
1243 pub mod R {}
1244 pub mod W {}
1245 pub mod RW {}
1246 }
1247 #[doc = "Flash B sample clock slave delay line locked."]
1248 pub mod BSLVLOCK {
1249 pub const offset: u32 = 16;
1250 pub const mask: u32 = 0x01 << offset;
1251 pub mod R {}
1252 pub mod W {}
1253 pub mod RW {}
1254 }
1255 #[doc = "Flash B sample clock reference delay line locked."]
1256 pub mod BREFLOCK {
1257 pub const offset: u32 = 17;
1258 pub const mask: u32 = 0x01 << offset;
1259 pub mod R {}
1260 pub mod W {}
1261 pub mod RW {}
1262 }
1263 #[doc = "Flash B sample clock slave delay line delay cell number selection."]
1264 pub mod BSLVSEL {
1265 pub const offset: u32 = 18;
1266 pub const mask: u32 = 0x3f << offset;
1267 pub mod R {}
1268 pub mod W {}
1269 pub mod RW {}
1270 }
1271 #[doc = "Flash B sample clock reference delay line delay cell number selection."]
1272 pub mod BREFSEL {
1273 pub const offset: u32 = 24;
1274 pub const mask: u32 = 0x3f << offset;
1275 pub mod R {}
1276 pub mod W {}
1277 pub mod RW {}
1278 }
1279}
1280#[doc = "AHB Suspend Status Register"]
1281pub mod AHBSPNDSTS {
1282 #[doc = "Indicates if an AHB read prefetch command sequence has been suspended."]
1283 pub mod ACTIVE {
1284 pub const offset: u32 = 0;
1285 pub const mask: u32 = 0x01 << offset;
1286 pub mod R {}
1287 pub mod W {}
1288 pub mod RW {}
1289 }
1290 #[doc = "AHB RX BUF ID for suspended command sequence."]
1291 pub mod BUFID {
1292 pub const offset: u32 = 1;
1293 pub const mask: u32 = 0x07 << offset;
1294 pub mod R {}
1295 pub mod W {}
1296 pub mod RW {}
1297 }
1298 #[doc = "Left Data size for suspended command sequence (in byte)."]
1299 pub mod DATLFT {
1300 pub const offset: u32 = 16;
1301 pub const mask: u32 = 0xffff << offset;
1302 pub mod R {}
1303 pub mod W {}
1304 pub mod RW {}
1305 }
1306}
1307#[doc = "IP RX FIFO Status Register"]
1308pub mod IPRXFSTS {
1309 #[doc = "Fill level of IP RX FIFO."]
1310 pub mod FILL {
1311 pub const offset: u32 = 0;
1312 pub const mask: u32 = 0xff << offset;
1313 pub mod R {}
1314 pub mod W {}
1315 pub mod RW {}
1316 }
1317 #[doc = "Total Read Data Counter: RDCNTR * 64 Bits."]
1318 pub mod RDCNTR {
1319 pub const offset: u32 = 16;
1320 pub const mask: u32 = 0xffff << offset;
1321 pub mod R {}
1322 pub mod W {}
1323 pub mod RW {}
1324 }
1325}
1326#[doc = "IP TX FIFO Status Register"]
1327pub mod IPTXFSTS {
1328 #[doc = "Fill level of IP TX FIFO."]
1329 pub mod FILL {
1330 pub const offset: u32 = 0;
1331 pub const mask: u32 = 0xff << offset;
1332 pub mod R {}
1333 pub mod W {}
1334 pub mod RW {}
1335 }
1336 #[doc = "Total Write Data Counter: WRCNTR * 64 Bits."]
1337 pub mod WRCNTR {
1338 pub const offset: u32 = 16;
1339 pub const mask: u32 = 0xffff << offset;
1340 pub mod R {}
1341 pub mod W {}
1342 pub mod RW {}
1343 }
1344}
1345#[doc = "IP RX FIFO Data Register 0"]
1346pub mod RFDR {
1347 #[doc = "RX Data"]
1348 pub mod RXDATA {
1349 pub const offset: u32 = 0;
1350 pub const mask: u32 = 0xffff_ffff << offset;
1351 pub mod R {}
1352 pub mod W {}
1353 pub mod RW {}
1354 }
1355}
1356#[doc = "IP TX FIFO Data Register 0"]
1357pub mod TFDR {
1358 #[doc = "TX Data"]
1359 pub mod TXDATA {
1360 pub const offset: u32 = 0;
1361 pub const mask: u32 = 0xffff_ffff << offset;
1362 pub mod R {}
1363 pub mod W {}
1364 pub mod RW {}
1365 }
1366}
1367#[doc = "LUT 0"]
1368pub mod LUT {
1369 #[doc = "OPERAND0"]
1370 pub mod OPERAND0 {
1371 pub const offset: u32 = 0;
1372 pub const mask: u32 = 0xff << offset;
1373 pub mod R {}
1374 pub mod W {}
1375 pub mod RW {}
1376 }
1377 #[doc = "NUM_PADS0"]
1378 pub mod NUM_PADS0 {
1379 pub const offset: u32 = 8;
1380 pub const mask: u32 = 0x03 << offset;
1381 pub mod R {}
1382 pub mod W {}
1383 pub mod RW {}
1384 }
1385 #[doc = "OPCODE"]
1386 pub mod OPCODE0 {
1387 pub const offset: u32 = 10;
1388 pub const mask: u32 = 0x3f << offset;
1389 pub mod R {}
1390 pub mod W {}
1391 pub mod RW {}
1392 }
1393 #[doc = "OPERAND1"]
1394 pub mod OPERAND1 {
1395 pub const offset: u32 = 16;
1396 pub const mask: u32 = 0xff << offset;
1397 pub mod R {}
1398 pub mod W {}
1399 pub mod RW {}
1400 }
1401 #[doc = "NUM_PADS1"]
1402 pub mod NUM_PADS1 {
1403 pub const offset: u32 = 24;
1404 pub const mask: u32 = 0x03 << offset;
1405 pub mod R {}
1406 pub mod W {}
1407 pub mod RW {}
1408 }
1409 #[doc = "OPCODE1"]
1410 pub mod OPCODE1 {
1411 pub const offset: u32 = 26;
1412 pub const mask: u32 = 0x3f << offset;
1413 pub mod R {}
1414 pub mod W {}
1415 pub mod RW {}
1416 }
1417}