1#[doc = "IOMUXC"]
2#[repr(C)]
3pub struct RegisterBlock {
4 _reserved0: [u8; 0x14],
5 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register"]
6 pub SW_MUX_CTL_PAD_GPIO_EMC_00: crate::RWRegister<u32>,
7 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_01 SW MUX Control Register"]
8 pub SW_MUX_CTL_PAD_GPIO_EMC_01: crate::RWRegister<u32>,
9 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_02 SW MUX Control Register"]
10 pub SW_MUX_CTL_PAD_GPIO_EMC_02: crate::RWRegister<u32>,
11 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_03 SW MUX Control Register"]
12 pub SW_MUX_CTL_PAD_GPIO_EMC_03: crate::RWRegister<u32>,
13 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_04 SW MUX Control Register"]
14 pub SW_MUX_CTL_PAD_GPIO_EMC_04: crate::RWRegister<u32>,
15 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_05 SW MUX Control Register"]
16 pub SW_MUX_CTL_PAD_GPIO_EMC_05: crate::RWRegister<u32>,
17 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_06 SW MUX Control Register"]
18 pub SW_MUX_CTL_PAD_GPIO_EMC_06: crate::RWRegister<u32>,
19 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_07 SW MUX Control Register"]
20 pub SW_MUX_CTL_PAD_GPIO_EMC_07: crate::RWRegister<u32>,
21 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_08 SW MUX Control Register"]
22 pub SW_MUX_CTL_PAD_GPIO_EMC_08: crate::RWRegister<u32>,
23 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_09 SW MUX Control Register"]
24 pub SW_MUX_CTL_PAD_GPIO_EMC_09: crate::RWRegister<u32>,
25 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_10 SW MUX Control Register"]
26 pub SW_MUX_CTL_PAD_GPIO_EMC_10: crate::RWRegister<u32>,
27 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_11 SW MUX Control Register"]
28 pub SW_MUX_CTL_PAD_GPIO_EMC_11: crate::RWRegister<u32>,
29 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_12 SW MUX Control Register"]
30 pub SW_MUX_CTL_PAD_GPIO_EMC_12: crate::RWRegister<u32>,
31 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_13 SW MUX Control Register"]
32 pub SW_MUX_CTL_PAD_GPIO_EMC_13: crate::RWRegister<u32>,
33 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_14 SW MUX Control Register"]
34 pub SW_MUX_CTL_PAD_GPIO_EMC_14: crate::RWRegister<u32>,
35 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_15 SW MUX Control Register"]
36 pub SW_MUX_CTL_PAD_GPIO_EMC_15: crate::RWRegister<u32>,
37 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_16 SW MUX Control Register"]
38 pub SW_MUX_CTL_PAD_GPIO_EMC_16: crate::RWRegister<u32>,
39 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_17 SW MUX Control Register"]
40 pub SW_MUX_CTL_PAD_GPIO_EMC_17: crate::RWRegister<u32>,
41 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_18 SW MUX Control Register"]
42 pub SW_MUX_CTL_PAD_GPIO_EMC_18: crate::RWRegister<u32>,
43 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_19 SW MUX Control Register"]
44 pub SW_MUX_CTL_PAD_GPIO_EMC_19: crate::RWRegister<u32>,
45 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_20 SW MUX Control Register"]
46 pub SW_MUX_CTL_PAD_GPIO_EMC_20: crate::RWRegister<u32>,
47 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_21 SW MUX Control Register"]
48 pub SW_MUX_CTL_PAD_GPIO_EMC_21: crate::RWRegister<u32>,
49 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_22 SW MUX Control Register"]
50 pub SW_MUX_CTL_PAD_GPIO_EMC_22: crate::RWRegister<u32>,
51 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_23 SW MUX Control Register"]
52 pub SW_MUX_CTL_PAD_GPIO_EMC_23: crate::RWRegister<u32>,
53 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_24 SW MUX Control Register"]
54 pub SW_MUX_CTL_PAD_GPIO_EMC_24: crate::RWRegister<u32>,
55 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_25 SW MUX Control Register"]
56 pub SW_MUX_CTL_PAD_GPIO_EMC_25: crate::RWRegister<u32>,
57 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_26 SW MUX Control Register"]
58 pub SW_MUX_CTL_PAD_GPIO_EMC_26: crate::RWRegister<u32>,
59 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_27 SW MUX Control Register"]
60 pub SW_MUX_CTL_PAD_GPIO_EMC_27: crate::RWRegister<u32>,
61 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_28 SW MUX Control Register"]
62 pub SW_MUX_CTL_PAD_GPIO_EMC_28: crate::RWRegister<u32>,
63 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_29 SW MUX Control Register"]
64 pub SW_MUX_CTL_PAD_GPIO_EMC_29: crate::RWRegister<u32>,
65 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_30 SW MUX Control Register"]
66 pub SW_MUX_CTL_PAD_GPIO_EMC_30: crate::RWRegister<u32>,
67 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_31 SW MUX Control Register"]
68 pub SW_MUX_CTL_PAD_GPIO_EMC_31: crate::RWRegister<u32>,
69 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_32 SW MUX Control Register"]
70 pub SW_MUX_CTL_PAD_GPIO_EMC_32: crate::RWRegister<u32>,
71 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_33 SW MUX Control Register"]
72 pub SW_MUX_CTL_PAD_GPIO_EMC_33: crate::RWRegister<u32>,
73 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_34 SW MUX Control Register"]
74 pub SW_MUX_CTL_PAD_GPIO_EMC_34: crate::RWRegister<u32>,
75 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_35 SW MUX Control Register"]
76 pub SW_MUX_CTL_PAD_GPIO_EMC_35: crate::RWRegister<u32>,
77 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_36 SW MUX Control Register"]
78 pub SW_MUX_CTL_PAD_GPIO_EMC_36: crate::RWRegister<u32>,
79 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_37 SW MUX Control Register"]
80 pub SW_MUX_CTL_PAD_GPIO_EMC_37: crate::RWRegister<u32>,
81 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_38 SW MUX Control Register"]
82 pub SW_MUX_CTL_PAD_GPIO_EMC_38: crate::RWRegister<u32>,
83 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_39 SW MUX Control Register"]
84 pub SW_MUX_CTL_PAD_GPIO_EMC_39: crate::RWRegister<u32>,
85 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_40 SW MUX Control Register"]
86 pub SW_MUX_CTL_PAD_GPIO_EMC_40: crate::RWRegister<u32>,
87 #[doc = "SW_MUX_CTL_PAD_GPIO_EMC_41 SW MUX Control Register"]
88 pub SW_MUX_CTL_PAD_GPIO_EMC_41: crate::RWRegister<u32>,
89 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_00 SW MUX Control Register"]
90 pub SW_MUX_CTL_PAD_GPIO_AD_B0_00: crate::RWRegister<u32>,
91 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_01 SW MUX Control Register"]
92 pub SW_MUX_CTL_PAD_GPIO_AD_B0_01: crate::RWRegister<u32>,
93 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_02 SW MUX Control Register"]
94 pub SW_MUX_CTL_PAD_GPIO_AD_B0_02: crate::RWRegister<u32>,
95 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_03 SW MUX Control Register"]
96 pub SW_MUX_CTL_PAD_GPIO_AD_B0_03: crate::RWRegister<u32>,
97 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_04 SW MUX Control Register"]
98 pub SW_MUX_CTL_PAD_GPIO_AD_B0_04: crate::RWRegister<u32>,
99 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_05 SW MUX Control Register"]
100 pub SW_MUX_CTL_PAD_GPIO_AD_B0_05: crate::RWRegister<u32>,
101 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_06 SW MUX Control Register"]
102 pub SW_MUX_CTL_PAD_GPIO_AD_B0_06: crate::RWRegister<u32>,
103 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_07 SW MUX Control Register"]
104 pub SW_MUX_CTL_PAD_GPIO_AD_B0_07: crate::RWRegister<u32>,
105 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_08 SW MUX Control Register"]
106 pub SW_MUX_CTL_PAD_GPIO_AD_B0_08: crate::RWRegister<u32>,
107 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_09 SW MUX Control Register"]
108 pub SW_MUX_CTL_PAD_GPIO_AD_B0_09: crate::RWRegister<u32>,
109 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_10 SW MUX Control Register"]
110 pub SW_MUX_CTL_PAD_GPIO_AD_B0_10: crate::RWRegister<u32>,
111 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_11 SW MUX Control Register"]
112 pub SW_MUX_CTL_PAD_GPIO_AD_B0_11: crate::RWRegister<u32>,
113 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_12 SW MUX Control Register"]
114 pub SW_MUX_CTL_PAD_GPIO_AD_B0_12: crate::RWRegister<u32>,
115 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_13 SW MUX Control Register"]
116 pub SW_MUX_CTL_PAD_GPIO_AD_B0_13: crate::RWRegister<u32>,
117 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_14 SW MUX Control Register"]
118 pub SW_MUX_CTL_PAD_GPIO_AD_B0_14: crate::RWRegister<u32>,
119 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_15 SW MUX Control Register"]
120 pub SW_MUX_CTL_PAD_GPIO_AD_B0_15: crate::RWRegister<u32>,
121 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_00 SW MUX Control Register"]
122 pub SW_MUX_CTL_PAD_GPIO_AD_B1_00: crate::RWRegister<u32>,
123 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_01 SW MUX Control Register"]
124 pub SW_MUX_CTL_PAD_GPIO_AD_B1_01: crate::RWRegister<u32>,
125 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_02 SW MUX Control Register"]
126 pub SW_MUX_CTL_PAD_GPIO_AD_B1_02: crate::RWRegister<u32>,
127 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_03 SW MUX Control Register"]
128 pub SW_MUX_CTL_PAD_GPIO_AD_B1_03: crate::RWRegister<u32>,
129 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_04 SW MUX Control Register"]
130 pub SW_MUX_CTL_PAD_GPIO_AD_B1_04: crate::RWRegister<u32>,
131 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_05 SW MUX Control Register"]
132 pub SW_MUX_CTL_PAD_GPIO_AD_B1_05: crate::RWRegister<u32>,
133 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_06 SW MUX Control Register"]
134 pub SW_MUX_CTL_PAD_GPIO_AD_B1_06: crate::RWRegister<u32>,
135 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_07 SW MUX Control Register"]
136 pub SW_MUX_CTL_PAD_GPIO_AD_B1_07: crate::RWRegister<u32>,
137 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_08 SW MUX Control Register"]
138 pub SW_MUX_CTL_PAD_GPIO_AD_B1_08: crate::RWRegister<u32>,
139 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_09 SW MUX Control Register"]
140 pub SW_MUX_CTL_PAD_GPIO_AD_B1_09: crate::RWRegister<u32>,
141 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_10 SW MUX Control Register"]
142 pub SW_MUX_CTL_PAD_GPIO_AD_B1_10: crate::RWRegister<u32>,
143 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_11 SW MUX Control Register"]
144 pub SW_MUX_CTL_PAD_GPIO_AD_B1_11: crate::RWRegister<u32>,
145 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_12 SW MUX Control Register"]
146 pub SW_MUX_CTL_PAD_GPIO_AD_B1_12: crate::RWRegister<u32>,
147 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_13 SW MUX Control Register"]
148 pub SW_MUX_CTL_PAD_GPIO_AD_B1_13: crate::RWRegister<u32>,
149 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_14 SW MUX Control Register"]
150 pub SW_MUX_CTL_PAD_GPIO_AD_B1_14: crate::RWRegister<u32>,
151 #[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_15 SW MUX Control Register"]
152 pub SW_MUX_CTL_PAD_GPIO_AD_B1_15: crate::RWRegister<u32>,
153 #[doc = "SW_MUX_CTL_PAD_GPIO_B0_00 SW MUX Control Register"]
154 pub SW_MUX_CTL_PAD_GPIO_B0_00: crate::RWRegister<u32>,
155 #[doc = "SW_MUX_CTL_PAD_GPIO_B0_01 SW MUX Control Register"]
156 pub SW_MUX_CTL_PAD_GPIO_B0_01: crate::RWRegister<u32>,
157 #[doc = "SW_MUX_CTL_PAD_GPIO_B0_02 SW MUX Control Register"]
158 pub SW_MUX_CTL_PAD_GPIO_B0_02: crate::RWRegister<u32>,
159 #[doc = "SW_MUX_CTL_PAD_GPIO_B0_03 SW MUX Control Register"]
160 pub SW_MUX_CTL_PAD_GPIO_B0_03: crate::RWRegister<u32>,
161 #[doc = "SW_MUX_CTL_PAD_GPIO_B0_04 SW MUX Control Register"]
162 pub SW_MUX_CTL_PAD_GPIO_B0_04: crate::RWRegister<u32>,
163 #[doc = "SW_MUX_CTL_PAD_GPIO_B0_05 SW MUX Control Register"]
164 pub SW_MUX_CTL_PAD_GPIO_B0_05: crate::RWRegister<u32>,
165 #[doc = "SW_MUX_CTL_PAD_GPIO_B0_06 SW MUX Control Register"]
166 pub SW_MUX_CTL_PAD_GPIO_B0_06: crate::RWRegister<u32>,
167 #[doc = "SW_MUX_CTL_PAD_GPIO_B0_07 SW MUX Control Register"]
168 pub SW_MUX_CTL_PAD_GPIO_B0_07: crate::RWRegister<u32>,
169 #[doc = "SW_MUX_CTL_PAD_GPIO_B0_08 SW MUX Control Register"]
170 pub SW_MUX_CTL_PAD_GPIO_B0_08: crate::RWRegister<u32>,
171 #[doc = "SW_MUX_CTL_PAD_GPIO_B0_09 SW MUX Control Register"]
172 pub SW_MUX_CTL_PAD_GPIO_B0_09: crate::RWRegister<u32>,
173 #[doc = "SW_MUX_CTL_PAD_GPIO_B0_10 SW MUX Control Register"]
174 pub SW_MUX_CTL_PAD_GPIO_B0_10: crate::RWRegister<u32>,
175 #[doc = "SW_MUX_CTL_PAD_GPIO_B0_11 SW MUX Control Register"]
176 pub SW_MUX_CTL_PAD_GPIO_B0_11: crate::RWRegister<u32>,
177 #[doc = "SW_MUX_CTL_PAD_GPIO_B0_12 SW MUX Control Register"]
178 pub SW_MUX_CTL_PAD_GPIO_B0_12: crate::RWRegister<u32>,
179 #[doc = "SW_MUX_CTL_PAD_GPIO_B0_13 SW MUX Control Register"]
180 pub SW_MUX_CTL_PAD_GPIO_B0_13: crate::RWRegister<u32>,
181 #[doc = "SW_MUX_CTL_PAD_GPIO_B0_14 SW MUX Control Register"]
182 pub SW_MUX_CTL_PAD_GPIO_B0_14: crate::RWRegister<u32>,
183 #[doc = "SW_MUX_CTL_PAD_GPIO_B0_15 SW MUX Control Register"]
184 pub SW_MUX_CTL_PAD_GPIO_B0_15: crate::RWRegister<u32>,
185 #[doc = "SW_MUX_CTL_PAD_GPIO_B1_00 SW MUX Control Register"]
186 pub SW_MUX_CTL_PAD_GPIO_B1_00: crate::RWRegister<u32>,
187 #[doc = "SW_MUX_CTL_PAD_GPIO_B1_01 SW MUX Control Register"]
188 pub SW_MUX_CTL_PAD_GPIO_B1_01: crate::RWRegister<u32>,
189 #[doc = "SW_MUX_CTL_PAD_GPIO_B1_02 SW MUX Control Register"]
190 pub SW_MUX_CTL_PAD_GPIO_B1_02: crate::RWRegister<u32>,
191 #[doc = "SW_MUX_CTL_PAD_GPIO_B1_03 SW MUX Control Register"]
192 pub SW_MUX_CTL_PAD_GPIO_B1_03: crate::RWRegister<u32>,
193 #[doc = "SW_MUX_CTL_PAD_GPIO_B1_04 SW MUX Control Register"]
194 pub SW_MUX_CTL_PAD_GPIO_B1_04: crate::RWRegister<u32>,
195 #[doc = "SW_MUX_CTL_PAD_GPIO_B1_05 SW MUX Control Register"]
196 pub SW_MUX_CTL_PAD_GPIO_B1_05: crate::RWRegister<u32>,
197 #[doc = "SW_MUX_CTL_PAD_GPIO_B1_06 SW MUX Control Register"]
198 pub SW_MUX_CTL_PAD_GPIO_B1_06: crate::RWRegister<u32>,
199 #[doc = "SW_MUX_CTL_PAD_GPIO_B1_07 SW MUX Control Register"]
200 pub SW_MUX_CTL_PAD_GPIO_B1_07: crate::RWRegister<u32>,
201 #[doc = "SW_MUX_CTL_PAD_GPIO_B1_08 SW MUX Control Register"]
202 pub SW_MUX_CTL_PAD_GPIO_B1_08: crate::RWRegister<u32>,
203 #[doc = "SW_MUX_CTL_PAD_GPIO_B1_09 SW MUX Control Register"]
204 pub SW_MUX_CTL_PAD_GPIO_B1_09: crate::RWRegister<u32>,
205 #[doc = "SW_MUX_CTL_PAD_GPIO_B1_10 SW MUX Control Register"]
206 pub SW_MUX_CTL_PAD_GPIO_B1_10: crate::RWRegister<u32>,
207 #[doc = "SW_MUX_CTL_PAD_GPIO_B1_11 SW MUX Control Register"]
208 pub SW_MUX_CTL_PAD_GPIO_B1_11: crate::RWRegister<u32>,
209 #[doc = "SW_MUX_CTL_PAD_GPIO_B1_12 SW MUX Control Register"]
210 pub SW_MUX_CTL_PAD_GPIO_B1_12: crate::RWRegister<u32>,
211 #[doc = "SW_MUX_CTL_PAD_GPIO_B1_13 SW MUX Control Register"]
212 pub SW_MUX_CTL_PAD_GPIO_B1_13: crate::RWRegister<u32>,
213 #[doc = "SW_MUX_CTL_PAD_GPIO_B1_14 SW MUX Control Register"]
214 pub SW_MUX_CTL_PAD_GPIO_B1_14: crate::RWRegister<u32>,
215 #[doc = "SW_MUX_CTL_PAD_GPIO_B1_15 SW MUX Control Register"]
216 pub SW_MUX_CTL_PAD_GPIO_B1_15: crate::RWRegister<u32>,
217 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_B0_00 SW MUX Control Register"]
218 pub SW_MUX_CTL_PAD_GPIO_SD_B0_00: crate::RWRegister<u32>,
219 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_B0_01 SW MUX Control Register"]
220 pub SW_MUX_CTL_PAD_GPIO_SD_B0_01: crate::RWRegister<u32>,
221 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_B0_02 SW MUX Control Register"]
222 pub SW_MUX_CTL_PAD_GPIO_SD_B0_02: crate::RWRegister<u32>,
223 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_B0_03 SW MUX Control Register"]
224 pub SW_MUX_CTL_PAD_GPIO_SD_B0_03: crate::RWRegister<u32>,
225 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_B0_04 SW MUX Control Register"]
226 pub SW_MUX_CTL_PAD_GPIO_SD_B0_04: crate::RWRegister<u32>,
227 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_B0_05 SW MUX Control Register"]
228 pub SW_MUX_CTL_PAD_GPIO_SD_B0_05: crate::RWRegister<u32>,
229 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_B1_00 SW MUX Control Register"]
230 pub SW_MUX_CTL_PAD_GPIO_SD_B1_00: crate::RWRegister<u32>,
231 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_B1_01 SW MUX Control Register"]
232 pub SW_MUX_CTL_PAD_GPIO_SD_B1_01: crate::RWRegister<u32>,
233 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_B1_02 SW MUX Control Register"]
234 pub SW_MUX_CTL_PAD_GPIO_SD_B1_02: crate::RWRegister<u32>,
235 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_B1_03 SW MUX Control Register"]
236 pub SW_MUX_CTL_PAD_GPIO_SD_B1_03: crate::RWRegister<u32>,
237 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_B1_04 SW MUX Control Register"]
238 pub SW_MUX_CTL_PAD_GPIO_SD_B1_04: crate::RWRegister<u32>,
239 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_B1_05 SW MUX Control Register"]
240 pub SW_MUX_CTL_PAD_GPIO_SD_B1_05: crate::RWRegister<u32>,
241 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_B1_06 SW MUX Control Register"]
242 pub SW_MUX_CTL_PAD_GPIO_SD_B1_06: crate::RWRegister<u32>,
243 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_B1_07 SW MUX Control Register"]
244 pub SW_MUX_CTL_PAD_GPIO_SD_B1_07: crate::RWRegister<u32>,
245 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_B1_08 SW MUX Control Register"]
246 pub SW_MUX_CTL_PAD_GPIO_SD_B1_08: crate::RWRegister<u32>,
247 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_B1_09 SW MUX Control Register"]
248 pub SW_MUX_CTL_PAD_GPIO_SD_B1_09: crate::RWRegister<u32>,
249 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_B1_10 SW MUX Control Register"]
250 pub SW_MUX_CTL_PAD_GPIO_SD_B1_10: crate::RWRegister<u32>,
251 #[doc = "SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register"]
252 pub SW_MUX_CTL_PAD_GPIO_SD_B1_11: crate::RWRegister<u32>,
253 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register"]
254 pub SW_PAD_CTL_PAD_GPIO_EMC_00: crate::RWRegister<u32>,
255 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_01 SW PAD Control Register"]
256 pub SW_PAD_CTL_PAD_GPIO_EMC_01: crate::RWRegister<u32>,
257 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_02 SW PAD Control Register"]
258 pub SW_PAD_CTL_PAD_GPIO_EMC_02: crate::RWRegister<u32>,
259 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_03 SW PAD Control Register"]
260 pub SW_PAD_CTL_PAD_GPIO_EMC_03: crate::RWRegister<u32>,
261 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_04 SW PAD Control Register"]
262 pub SW_PAD_CTL_PAD_GPIO_EMC_04: crate::RWRegister<u32>,
263 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_05 SW PAD Control Register"]
264 pub SW_PAD_CTL_PAD_GPIO_EMC_05: crate::RWRegister<u32>,
265 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_06 SW PAD Control Register"]
266 pub SW_PAD_CTL_PAD_GPIO_EMC_06: crate::RWRegister<u32>,
267 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_07 SW PAD Control Register"]
268 pub SW_PAD_CTL_PAD_GPIO_EMC_07: crate::RWRegister<u32>,
269 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_08 SW PAD Control Register"]
270 pub SW_PAD_CTL_PAD_GPIO_EMC_08: crate::RWRegister<u32>,
271 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_09 SW PAD Control Register"]
272 pub SW_PAD_CTL_PAD_GPIO_EMC_09: crate::RWRegister<u32>,
273 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_10 SW PAD Control Register"]
274 pub SW_PAD_CTL_PAD_GPIO_EMC_10: crate::RWRegister<u32>,
275 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_11 SW PAD Control Register"]
276 pub SW_PAD_CTL_PAD_GPIO_EMC_11: crate::RWRegister<u32>,
277 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_12 SW PAD Control Register"]
278 pub SW_PAD_CTL_PAD_GPIO_EMC_12: crate::RWRegister<u32>,
279 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_13 SW PAD Control Register"]
280 pub SW_PAD_CTL_PAD_GPIO_EMC_13: crate::RWRegister<u32>,
281 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_14 SW PAD Control Register"]
282 pub SW_PAD_CTL_PAD_GPIO_EMC_14: crate::RWRegister<u32>,
283 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_15 SW PAD Control Register"]
284 pub SW_PAD_CTL_PAD_GPIO_EMC_15: crate::RWRegister<u32>,
285 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_16 SW PAD Control Register"]
286 pub SW_PAD_CTL_PAD_GPIO_EMC_16: crate::RWRegister<u32>,
287 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_17 SW PAD Control Register"]
288 pub SW_PAD_CTL_PAD_GPIO_EMC_17: crate::RWRegister<u32>,
289 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_18 SW PAD Control Register"]
290 pub SW_PAD_CTL_PAD_GPIO_EMC_18: crate::RWRegister<u32>,
291 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_19 SW PAD Control Register"]
292 pub SW_PAD_CTL_PAD_GPIO_EMC_19: crate::RWRegister<u32>,
293 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_20 SW PAD Control Register"]
294 pub SW_PAD_CTL_PAD_GPIO_EMC_20: crate::RWRegister<u32>,
295 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_21 SW PAD Control Register"]
296 pub SW_PAD_CTL_PAD_GPIO_EMC_21: crate::RWRegister<u32>,
297 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_22 SW PAD Control Register"]
298 pub SW_PAD_CTL_PAD_GPIO_EMC_22: crate::RWRegister<u32>,
299 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_23 SW PAD Control Register"]
300 pub SW_PAD_CTL_PAD_GPIO_EMC_23: crate::RWRegister<u32>,
301 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_24 SW PAD Control Register"]
302 pub SW_PAD_CTL_PAD_GPIO_EMC_24: crate::RWRegister<u32>,
303 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_25 SW PAD Control Register"]
304 pub SW_PAD_CTL_PAD_GPIO_EMC_25: crate::RWRegister<u32>,
305 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_26 SW PAD Control Register"]
306 pub SW_PAD_CTL_PAD_GPIO_EMC_26: crate::RWRegister<u32>,
307 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_27 SW PAD Control Register"]
308 pub SW_PAD_CTL_PAD_GPIO_EMC_27: crate::RWRegister<u32>,
309 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_28 SW PAD Control Register"]
310 pub SW_PAD_CTL_PAD_GPIO_EMC_28: crate::RWRegister<u32>,
311 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_29 SW PAD Control Register"]
312 pub SW_PAD_CTL_PAD_GPIO_EMC_29: crate::RWRegister<u32>,
313 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_30 SW PAD Control Register"]
314 pub SW_PAD_CTL_PAD_GPIO_EMC_30: crate::RWRegister<u32>,
315 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_31 SW PAD Control Register"]
316 pub SW_PAD_CTL_PAD_GPIO_EMC_31: crate::RWRegister<u32>,
317 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_32 SW PAD Control Register"]
318 pub SW_PAD_CTL_PAD_GPIO_EMC_32: crate::RWRegister<u32>,
319 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_33 SW PAD Control Register"]
320 pub SW_PAD_CTL_PAD_GPIO_EMC_33: crate::RWRegister<u32>,
321 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_34 SW PAD Control Register"]
322 pub SW_PAD_CTL_PAD_GPIO_EMC_34: crate::RWRegister<u32>,
323 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_35 SW PAD Control Register"]
324 pub SW_PAD_CTL_PAD_GPIO_EMC_35: crate::RWRegister<u32>,
325 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_36 SW PAD Control Register"]
326 pub SW_PAD_CTL_PAD_GPIO_EMC_36: crate::RWRegister<u32>,
327 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_37 SW PAD Control Register"]
328 pub SW_PAD_CTL_PAD_GPIO_EMC_37: crate::RWRegister<u32>,
329 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_38 SW PAD Control Register"]
330 pub SW_PAD_CTL_PAD_GPIO_EMC_38: crate::RWRegister<u32>,
331 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_39 SW PAD Control Register"]
332 pub SW_PAD_CTL_PAD_GPIO_EMC_39: crate::RWRegister<u32>,
333 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_40 SW PAD Control Register"]
334 pub SW_PAD_CTL_PAD_GPIO_EMC_40: crate::RWRegister<u32>,
335 #[doc = "SW_PAD_CTL_PAD_GPIO_EMC_41 SW PAD Control Register"]
336 pub SW_PAD_CTL_PAD_GPIO_EMC_41: crate::RWRegister<u32>,
337 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_00 SW PAD Control Register"]
338 pub SW_PAD_CTL_PAD_GPIO_AD_B0_00: crate::RWRegister<u32>,
339 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_01 SW PAD Control Register"]
340 pub SW_PAD_CTL_PAD_GPIO_AD_B0_01: crate::RWRegister<u32>,
341 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_02 SW PAD Control Register"]
342 pub SW_PAD_CTL_PAD_GPIO_AD_B0_02: crate::RWRegister<u32>,
343 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_03 SW PAD Control Register"]
344 pub SW_PAD_CTL_PAD_GPIO_AD_B0_03: crate::RWRegister<u32>,
345 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_04 SW PAD Control Register"]
346 pub SW_PAD_CTL_PAD_GPIO_AD_B0_04: crate::RWRegister<u32>,
347 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_05 SW PAD Control Register"]
348 pub SW_PAD_CTL_PAD_GPIO_AD_B0_05: crate::RWRegister<u32>,
349 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_06 SW PAD Control Register"]
350 pub SW_PAD_CTL_PAD_GPIO_AD_B0_06: crate::RWRegister<u32>,
351 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_07 SW PAD Control Register"]
352 pub SW_PAD_CTL_PAD_GPIO_AD_B0_07: crate::RWRegister<u32>,
353 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_08 SW PAD Control Register"]
354 pub SW_PAD_CTL_PAD_GPIO_AD_B0_08: crate::RWRegister<u32>,
355 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_09 SW PAD Control Register"]
356 pub SW_PAD_CTL_PAD_GPIO_AD_B0_09: crate::RWRegister<u32>,
357 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_10 SW PAD Control Register"]
358 pub SW_PAD_CTL_PAD_GPIO_AD_B0_10: crate::RWRegister<u32>,
359 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_11 SW PAD Control Register"]
360 pub SW_PAD_CTL_PAD_GPIO_AD_B0_11: crate::RWRegister<u32>,
361 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_12 SW PAD Control Register"]
362 pub SW_PAD_CTL_PAD_GPIO_AD_B0_12: crate::RWRegister<u32>,
363 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_13 SW PAD Control Register"]
364 pub SW_PAD_CTL_PAD_GPIO_AD_B0_13: crate::RWRegister<u32>,
365 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_14 SW PAD Control Register"]
366 pub SW_PAD_CTL_PAD_GPIO_AD_B0_14: crate::RWRegister<u32>,
367 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_15 SW PAD Control Register"]
368 pub SW_PAD_CTL_PAD_GPIO_AD_B0_15: crate::RWRegister<u32>,
369 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_00 SW PAD Control Register"]
370 pub SW_PAD_CTL_PAD_GPIO_AD_B1_00: crate::RWRegister<u32>,
371 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_01 SW PAD Control Register"]
372 pub SW_PAD_CTL_PAD_GPIO_AD_B1_01: crate::RWRegister<u32>,
373 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_02 SW PAD Control Register"]
374 pub SW_PAD_CTL_PAD_GPIO_AD_B1_02: crate::RWRegister<u32>,
375 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_03 SW PAD Control Register"]
376 pub SW_PAD_CTL_PAD_GPIO_AD_B1_03: crate::RWRegister<u32>,
377 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_04 SW PAD Control Register"]
378 pub SW_PAD_CTL_PAD_GPIO_AD_B1_04: crate::RWRegister<u32>,
379 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_05 SW PAD Control Register"]
380 pub SW_PAD_CTL_PAD_GPIO_AD_B1_05: crate::RWRegister<u32>,
381 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_06 SW PAD Control Register"]
382 pub SW_PAD_CTL_PAD_GPIO_AD_B1_06: crate::RWRegister<u32>,
383 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_07 SW PAD Control Register"]
384 pub SW_PAD_CTL_PAD_GPIO_AD_B1_07: crate::RWRegister<u32>,
385 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_08 SW PAD Control Register"]
386 pub SW_PAD_CTL_PAD_GPIO_AD_B1_08: crate::RWRegister<u32>,
387 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_09 SW PAD Control Register"]
388 pub SW_PAD_CTL_PAD_GPIO_AD_B1_09: crate::RWRegister<u32>,
389 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_10 SW PAD Control Register"]
390 pub SW_PAD_CTL_PAD_GPIO_AD_B1_10: crate::RWRegister<u32>,
391 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_11 SW PAD Control Register"]
392 pub SW_PAD_CTL_PAD_GPIO_AD_B1_11: crate::RWRegister<u32>,
393 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_12 SW PAD Control Register"]
394 pub SW_PAD_CTL_PAD_GPIO_AD_B1_12: crate::RWRegister<u32>,
395 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_13 SW PAD Control Register"]
396 pub SW_PAD_CTL_PAD_GPIO_AD_B1_13: crate::RWRegister<u32>,
397 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_14 SW PAD Control Register"]
398 pub SW_PAD_CTL_PAD_GPIO_AD_B1_14: crate::RWRegister<u32>,
399 #[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_15 SW PAD Control Register"]
400 pub SW_PAD_CTL_PAD_GPIO_AD_B1_15: crate::RWRegister<u32>,
401 #[doc = "SW_PAD_CTL_PAD_GPIO_B0_00 SW PAD Control Register"]
402 pub SW_PAD_CTL_PAD_GPIO_B0_00: crate::RWRegister<u32>,
403 #[doc = "SW_PAD_CTL_PAD_GPIO_B0_01 SW PAD Control Register"]
404 pub SW_PAD_CTL_PAD_GPIO_B0_01: crate::RWRegister<u32>,
405 #[doc = "SW_PAD_CTL_PAD_GPIO_B0_02 SW PAD Control Register"]
406 pub SW_PAD_CTL_PAD_GPIO_B0_02: crate::RWRegister<u32>,
407 #[doc = "SW_PAD_CTL_PAD_GPIO_B0_03 SW PAD Control Register"]
408 pub SW_PAD_CTL_PAD_GPIO_B0_03: crate::RWRegister<u32>,
409 #[doc = "SW_PAD_CTL_PAD_GPIO_B0_04 SW PAD Control Register"]
410 pub SW_PAD_CTL_PAD_GPIO_B0_04: crate::RWRegister<u32>,
411 #[doc = "SW_PAD_CTL_PAD_GPIO_B0_05 SW PAD Control Register"]
412 pub SW_PAD_CTL_PAD_GPIO_B0_05: crate::RWRegister<u32>,
413 #[doc = "SW_PAD_CTL_PAD_GPIO_B0_06 SW PAD Control Register"]
414 pub SW_PAD_CTL_PAD_GPIO_B0_06: crate::RWRegister<u32>,
415 #[doc = "SW_PAD_CTL_PAD_GPIO_B0_07 SW PAD Control Register"]
416 pub SW_PAD_CTL_PAD_GPIO_B0_07: crate::RWRegister<u32>,
417 #[doc = "SW_PAD_CTL_PAD_GPIO_B0_08 SW PAD Control Register"]
418 pub SW_PAD_CTL_PAD_GPIO_B0_08: crate::RWRegister<u32>,
419 #[doc = "SW_PAD_CTL_PAD_GPIO_B0_09 SW PAD Control Register"]
420 pub SW_PAD_CTL_PAD_GPIO_B0_09: crate::RWRegister<u32>,
421 #[doc = "SW_PAD_CTL_PAD_GPIO_B0_10 SW PAD Control Register"]
422 pub SW_PAD_CTL_PAD_GPIO_B0_10: crate::RWRegister<u32>,
423 #[doc = "SW_PAD_CTL_PAD_GPIO_B0_11 SW PAD Control Register"]
424 pub SW_PAD_CTL_PAD_GPIO_B0_11: crate::RWRegister<u32>,
425 #[doc = "SW_PAD_CTL_PAD_GPIO_B0_12 SW PAD Control Register"]
426 pub SW_PAD_CTL_PAD_GPIO_B0_12: crate::RWRegister<u32>,
427 #[doc = "SW_PAD_CTL_PAD_GPIO_B0_13 SW PAD Control Register"]
428 pub SW_PAD_CTL_PAD_GPIO_B0_13: crate::RWRegister<u32>,
429 #[doc = "SW_PAD_CTL_PAD_GPIO_B0_14 SW PAD Control Register"]
430 pub SW_PAD_CTL_PAD_GPIO_B0_14: crate::RWRegister<u32>,
431 #[doc = "SW_PAD_CTL_PAD_GPIO_B0_15 SW PAD Control Register"]
432 pub SW_PAD_CTL_PAD_GPIO_B0_15: crate::RWRegister<u32>,
433 #[doc = "SW_PAD_CTL_PAD_GPIO_B1_00 SW PAD Control Register"]
434 pub SW_PAD_CTL_PAD_GPIO_B1_00: crate::RWRegister<u32>,
435 #[doc = "SW_PAD_CTL_PAD_GPIO_B1_01 SW PAD Control Register"]
436 pub SW_PAD_CTL_PAD_GPIO_B1_01: crate::RWRegister<u32>,
437 #[doc = "SW_PAD_CTL_PAD_GPIO_B1_02 SW PAD Control Register"]
438 pub SW_PAD_CTL_PAD_GPIO_B1_02: crate::RWRegister<u32>,
439 #[doc = "SW_PAD_CTL_PAD_GPIO_B1_03 SW PAD Control Register"]
440 pub SW_PAD_CTL_PAD_GPIO_B1_03: crate::RWRegister<u32>,
441 #[doc = "SW_PAD_CTL_PAD_GPIO_B1_04 SW PAD Control Register"]
442 pub SW_PAD_CTL_PAD_GPIO_B1_04: crate::RWRegister<u32>,
443 #[doc = "SW_PAD_CTL_PAD_GPIO_B1_05 SW PAD Control Register"]
444 pub SW_PAD_CTL_PAD_GPIO_B1_05: crate::RWRegister<u32>,
445 #[doc = "SW_PAD_CTL_PAD_GPIO_B1_06 SW PAD Control Register"]
446 pub SW_PAD_CTL_PAD_GPIO_B1_06: crate::RWRegister<u32>,
447 #[doc = "SW_PAD_CTL_PAD_GPIO_B1_07 SW PAD Control Register"]
448 pub SW_PAD_CTL_PAD_GPIO_B1_07: crate::RWRegister<u32>,
449 #[doc = "SW_PAD_CTL_PAD_GPIO_B1_08 SW PAD Control Register"]
450 pub SW_PAD_CTL_PAD_GPIO_B1_08: crate::RWRegister<u32>,
451 #[doc = "SW_PAD_CTL_PAD_GPIO_B1_09 SW PAD Control Register"]
452 pub SW_PAD_CTL_PAD_GPIO_B1_09: crate::RWRegister<u32>,
453 #[doc = "SW_PAD_CTL_PAD_GPIO_B1_10 SW PAD Control Register"]
454 pub SW_PAD_CTL_PAD_GPIO_B1_10: crate::RWRegister<u32>,
455 #[doc = "SW_PAD_CTL_PAD_GPIO_B1_11 SW PAD Control Register"]
456 pub SW_PAD_CTL_PAD_GPIO_B1_11: crate::RWRegister<u32>,
457 #[doc = "SW_PAD_CTL_PAD_GPIO_B1_12 SW PAD Control Register"]
458 pub SW_PAD_CTL_PAD_GPIO_B1_12: crate::RWRegister<u32>,
459 #[doc = "SW_PAD_CTL_PAD_GPIO_B1_13 SW PAD Control Register"]
460 pub SW_PAD_CTL_PAD_GPIO_B1_13: crate::RWRegister<u32>,
461 #[doc = "SW_PAD_CTL_PAD_GPIO_B1_14 SW PAD Control Register"]
462 pub SW_PAD_CTL_PAD_GPIO_B1_14: crate::RWRegister<u32>,
463 #[doc = "SW_PAD_CTL_PAD_GPIO_B1_15 SW PAD Control Register"]
464 pub SW_PAD_CTL_PAD_GPIO_B1_15: crate::RWRegister<u32>,
465 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_B0_00 SW PAD Control Register"]
466 pub SW_PAD_CTL_PAD_GPIO_SD_B0_00: crate::RWRegister<u32>,
467 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_B0_01 SW PAD Control Register"]
468 pub SW_PAD_CTL_PAD_GPIO_SD_B0_01: crate::RWRegister<u32>,
469 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_B0_02 SW PAD Control Register"]
470 pub SW_PAD_CTL_PAD_GPIO_SD_B0_02: crate::RWRegister<u32>,
471 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_B0_03 SW PAD Control Register"]
472 pub SW_PAD_CTL_PAD_GPIO_SD_B0_03: crate::RWRegister<u32>,
473 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_B0_04 SW PAD Control Register"]
474 pub SW_PAD_CTL_PAD_GPIO_SD_B0_04: crate::RWRegister<u32>,
475 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_B0_05 SW PAD Control Register"]
476 pub SW_PAD_CTL_PAD_GPIO_SD_B0_05: crate::RWRegister<u32>,
477 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_B1_00 SW PAD Control Register"]
478 pub SW_PAD_CTL_PAD_GPIO_SD_B1_00: crate::RWRegister<u32>,
479 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_B1_01 SW PAD Control Register"]
480 pub SW_PAD_CTL_PAD_GPIO_SD_B1_01: crate::RWRegister<u32>,
481 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_B1_02 SW PAD Control Register"]
482 pub SW_PAD_CTL_PAD_GPIO_SD_B1_02: crate::RWRegister<u32>,
483 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_B1_03 SW PAD Control Register"]
484 pub SW_PAD_CTL_PAD_GPIO_SD_B1_03: crate::RWRegister<u32>,
485 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_B1_04 SW PAD Control Register"]
486 pub SW_PAD_CTL_PAD_GPIO_SD_B1_04: crate::RWRegister<u32>,
487 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_B1_05 SW PAD Control Register"]
488 pub SW_PAD_CTL_PAD_GPIO_SD_B1_05: crate::RWRegister<u32>,
489 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_B1_06 SW PAD Control Register"]
490 pub SW_PAD_CTL_PAD_GPIO_SD_B1_06: crate::RWRegister<u32>,
491 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_B1_07 SW PAD Control Register"]
492 pub SW_PAD_CTL_PAD_GPIO_SD_B1_07: crate::RWRegister<u32>,
493 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_B1_08 SW PAD Control Register"]
494 pub SW_PAD_CTL_PAD_GPIO_SD_B1_08: crate::RWRegister<u32>,
495 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_B1_09 SW PAD Control Register"]
496 pub SW_PAD_CTL_PAD_GPIO_SD_B1_09: crate::RWRegister<u32>,
497 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_B1_10 SW PAD Control Register"]
498 pub SW_PAD_CTL_PAD_GPIO_SD_B1_10: crate::RWRegister<u32>,
499 #[doc = "SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register"]
500 pub SW_PAD_CTL_PAD_GPIO_SD_B1_11: crate::RWRegister<u32>,
501 #[doc = "ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register"]
502 pub ANATOP_USB_OTG1_ID_SELECT_INPUT: crate::RWRegister<u32>,
503 #[doc = "ANATOP_USB_OTG2_ID_SELECT_INPUT DAISY Register"]
504 pub ANATOP_USB_OTG2_ID_SELECT_INPUT: crate::RWRegister<u32>,
505 #[doc = "CCM_PMIC_READY_SELECT_INPUT DAISY Register"]
506 pub CCM_PMIC_READY_SELECT_INPUT: crate::RWRegister<u32>,
507 #[doc = "CSI_DATA02_SELECT_INPUT DAISY Register"]
508 pub CSI_DATA02_SELECT_INPUT: crate::RWRegister<u32>,
509 #[doc = "CSI_DATA03_SELECT_INPUT DAISY Register"]
510 pub CSI_DATA03_SELECT_INPUT: crate::RWRegister<u32>,
511 #[doc = "CSI_DATA04_SELECT_INPUT DAISY Register"]
512 pub CSI_DATA04_SELECT_INPUT: crate::RWRegister<u32>,
513 #[doc = "CSI_DATA05_SELECT_INPUT DAISY Register"]
514 pub CSI_DATA05_SELECT_INPUT: crate::RWRegister<u32>,
515 #[doc = "CSI_DATA06_SELECT_INPUT DAISY Register"]
516 pub CSI_DATA06_SELECT_INPUT: crate::RWRegister<u32>,
517 #[doc = "CSI_DATA07_SELECT_INPUT DAISY Register"]
518 pub CSI_DATA07_SELECT_INPUT: crate::RWRegister<u32>,
519 #[doc = "CSI_DATA08_SELECT_INPUT DAISY Register"]
520 pub CSI_DATA08_SELECT_INPUT: crate::RWRegister<u32>,
521 #[doc = "CSI_DATA09_SELECT_INPUT DAISY Register"]
522 pub CSI_DATA09_SELECT_INPUT: crate::RWRegister<u32>,
523 #[doc = "CSI_HSYNC_SELECT_INPUT DAISY Register"]
524 pub CSI_HSYNC_SELECT_INPUT: crate::RWRegister<u32>,
525 #[doc = "CSI_PIXCLK_SELECT_INPUT DAISY Register"]
526 pub CSI_PIXCLK_SELECT_INPUT: crate::RWRegister<u32>,
527 #[doc = "CSI_VSYNC_SELECT_INPUT DAISY Register"]
528 pub CSI_VSYNC_SELECT_INPUT: crate::RWRegister<u32>,
529 #[doc = "ENET_IPG_CLK_RMII_SELECT_INPUT DAISY Register"]
530 pub ENET_IPG_CLK_RMII_SELECT_INPUT: crate::RWRegister<u32>,
531 #[doc = "ENET_MDIO_SELECT_INPUT DAISY Register"]
532 pub ENET_MDIO_SELECT_INPUT: crate::RWRegister<u32>,
533 #[doc = "ENET0_RXDATA_SELECT_INPUT DAISY Register"]
534 pub ENET0_RXDATA_SELECT_INPUT: crate::RWRegister<u32>,
535 #[doc = "ENET1_RXDATA_SELECT_INPUT DAISY Register"]
536 pub ENET1_RXDATA_SELECT_INPUT: crate::RWRegister<u32>,
537 #[doc = "ENET_RXEN_SELECT_INPUT DAISY Register"]
538 pub ENET_RXEN_SELECT_INPUT: crate::RWRegister<u32>,
539 #[doc = "ENET_RXERR_SELECT_INPUT DAISY Register"]
540 pub ENET_RXERR_SELECT_INPUT: crate::RWRegister<u32>,
541 #[doc = "ENET0_TIMER_SELECT_INPUT DAISY Register"]
542 pub ENET0_TIMER_SELECT_INPUT: crate::RWRegister<u32>,
543 #[doc = "ENET_TXCLK_SELECT_INPUT DAISY Register"]
544 pub ENET_TXCLK_SELECT_INPUT: crate::RWRegister<u32>,
545 #[doc = "FLEXCAN1_RX_SELECT_INPUT DAISY Register"]
546 pub FLEXCAN1_RX_SELECT_INPUT: crate::RWRegister<u32>,
547 #[doc = "FLEXCAN2_RX_SELECT_INPUT DAISY Register"]
548 pub FLEXCAN2_RX_SELECT_INPUT: crate::RWRegister<u32>,
549 #[doc = "FLEXPWM1_PWMA3_SELECT_INPUT DAISY Register"]
550 pub FLEXPWM1_PWMA3_SELECT_INPUT: crate::RWRegister<u32>,
551 #[doc = "FLEXPWM1_PWMA0_SELECT_INPUT DAISY Register"]
552 pub FLEXPWM1_PWMA0_SELECT_INPUT: crate::RWRegister<u32>,
553 #[doc = "FLEXPWM1_PWMA1_SELECT_INPUT DAISY Register"]
554 pub FLEXPWM1_PWMA1_SELECT_INPUT: crate::RWRegister<u32>,
555 #[doc = "FLEXPWM1_PWMA2_SELECT_INPUT DAISY Register"]
556 pub FLEXPWM1_PWMA2_SELECT_INPUT: crate::RWRegister<u32>,
557 #[doc = "FLEXPWM1_PWMB3_SELECT_INPUT DAISY Register"]
558 pub FLEXPWM1_PWMB3_SELECT_INPUT: crate::RWRegister<u32>,
559 #[doc = "FLEXPWM1_PWMB0_SELECT_INPUT DAISY Register"]
560 pub FLEXPWM1_PWMB0_SELECT_INPUT: crate::RWRegister<u32>,
561 #[doc = "FLEXPWM1_PWMB1_SELECT_INPUT DAISY Register"]
562 pub FLEXPWM1_PWMB1_SELECT_INPUT: crate::RWRegister<u32>,
563 #[doc = "FLEXPWM1_PWMB2_SELECT_INPUT DAISY Register"]
564 pub FLEXPWM1_PWMB2_SELECT_INPUT: crate::RWRegister<u32>,
565 #[doc = "FLEXPWM2_PWMA3_SELECT_INPUT DAISY Register"]
566 pub FLEXPWM2_PWMA3_SELECT_INPUT: crate::RWRegister<u32>,
567 #[doc = "FLEXPWM2_PWMA0_SELECT_INPUT DAISY Register"]
568 pub FLEXPWM2_PWMA0_SELECT_INPUT: crate::RWRegister<u32>,
569 #[doc = "FLEXPWM2_PWMA1_SELECT_INPUT DAISY Register"]
570 pub FLEXPWM2_PWMA1_SELECT_INPUT: crate::RWRegister<u32>,
571 #[doc = "FLEXPWM2_PWMA2_SELECT_INPUT DAISY Register"]
572 pub FLEXPWM2_PWMA2_SELECT_INPUT: crate::RWRegister<u32>,
573 #[doc = "FLEXPWM2_PWMB3_SELECT_INPUT DAISY Register"]
574 pub FLEXPWM2_PWMB3_SELECT_INPUT: crate::RWRegister<u32>,
575 #[doc = "FLEXPWM2_PWMB0_SELECT_INPUT DAISY Register"]
576 pub FLEXPWM2_PWMB0_SELECT_INPUT: crate::RWRegister<u32>,
577 #[doc = "FLEXPWM2_PWMB1_SELECT_INPUT DAISY Register"]
578 pub FLEXPWM2_PWMB1_SELECT_INPUT: crate::RWRegister<u32>,
579 #[doc = "FLEXPWM2_PWMB2_SELECT_INPUT DAISY Register"]
580 pub FLEXPWM2_PWMB2_SELECT_INPUT: crate::RWRegister<u32>,
581 #[doc = "FLEXPWM4_PWMA0_SELECT_INPUT DAISY Register"]
582 pub FLEXPWM4_PWMA0_SELECT_INPUT: crate::RWRegister<u32>,
583 #[doc = "FLEXPWM4_PWMA1_SELECT_INPUT DAISY Register"]
584 pub FLEXPWM4_PWMA1_SELECT_INPUT: crate::RWRegister<u32>,
585 #[doc = "FLEXPWM4_PWMA2_SELECT_INPUT DAISY Register"]
586 pub FLEXPWM4_PWMA2_SELECT_INPUT: crate::RWRegister<u32>,
587 #[doc = "FLEXPWM4_PWMA3_SELECT_INPUT DAISY Register"]
588 pub FLEXPWM4_PWMA3_SELECT_INPUT: crate::RWRegister<u32>,
589 #[doc = "FLEXSPIA_DQS_SELECT_INPUT DAISY Register"]
590 pub FLEXSPIA_DQS_SELECT_INPUT: crate::RWRegister<u32>,
591 #[doc = "FLEXSPIA_DATA0_SELECT_INPUT DAISY Register"]
592 pub FLEXSPIA_DATA0_SELECT_INPUT: crate::RWRegister<u32>,
593 #[doc = "FLEXSPIA_DATA1_SELECT_INPUT DAISY Register"]
594 pub FLEXSPIA_DATA1_SELECT_INPUT: crate::RWRegister<u32>,
595 #[doc = "FLEXSPIA_DATA2_SELECT_INPUT DAISY Register"]
596 pub FLEXSPIA_DATA2_SELECT_INPUT: crate::RWRegister<u32>,
597 #[doc = "FLEXSPIA_DATA3_SELECT_INPUT DAISY Register"]
598 pub FLEXSPIA_DATA3_SELECT_INPUT: crate::RWRegister<u32>,
599 #[doc = "FLEXSPIB_DATA0_SELECT_INPUT DAISY Register"]
600 pub FLEXSPIB_DATA0_SELECT_INPUT: crate::RWRegister<u32>,
601 #[doc = "FLEXSPIB_DATA1_SELECT_INPUT DAISY Register"]
602 pub FLEXSPIB_DATA1_SELECT_INPUT: crate::RWRegister<u32>,
603 #[doc = "FLEXSPIB_DATA2_SELECT_INPUT DAISY Register"]
604 pub FLEXSPIB_DATA2_SELECT_INPUT: crate::RWRegister<u32>,
605 #[doc = "FLEXSPIB_DATA3_SELECT_INPUT DAISY Register"]
606 pub FLEXSPIB_DATA3_SELECT_INPUT: crate::RWRegister<u32>,
607 #[doc = "FLEXSPIA_SCK_SELECT_INPUT DAISY Register"]
608 pub FLEXSPIA_SCK_SELECT_INPUT: crate::RWRegister<u32>,
609 #[doc = "LPI2C1_SCL_SELECT_INPUT DAISY Register"]
610 pub LPI2C1_SCL_SELECT_INPUT: crate::RWRegister<u32>,
611 #[doc = "LPI2C1_SDA_SELECT_INPUT DAISY Register"]
612 pub LPI2C1_SDA_SELECT_INPUT: crate::RWRegister<u32>,
613 #[doc = "LPI2C2_SCL_SELECT_INPUT DAISY Register"]
614 pub LPI2C2_SCL_SELECT_INPUT: crate::RWRegister<u32>,
615 #[doc = "LPI2C2_SDA_SELECT_INPUT DAISY Register"]
616 pub LPI2C2_SDA_SELECT_INPUT: crate::RWRegister<u32>,
617 #[doc = "LPI2C3_SCL_SELECT_INPUT DAISY Register"]
618 pub LPI2C3_SCL_SELECT_INPUT: crate::RWRegister<u32>,
619 #[doc = "LPI2C3_SDA_SELECT_INPUT DAISY Register"]
620 pub LPI2C3_SDA_SELECT_INPUT: crate::RWRegister<u32>,
621 #[doc = "LPI2C4_SCL_SELECT_INPUT DAISY Register"]
622 pub LPI2C4_SCL_SELECT_INPUT: crate::RWRegister<u32>,
623 #[doc = "LPI2C4_SDA_SELECT_INPUT DAISY Register"]
624 pub LPI2C4_SDA_SELECT_INPUT: crate::RWRegister<u32>,
625 #[doc = "LPSPI1_PCS0_SELECT_INPUT DAISY Register"]
626 pub LPSPI1_PCS0_SELECT_INPUT: crate::RWRegister<u32>,
627 #[doc = "LPSPI1_SCK_SELECT_INPUT DAISY Register"]
628 pub LPSPI1_SCK_SELECT_INPUT: crate::RWRegister<u32>,
629 #[doc = "LPSPI1_SDI_SELECT_INPUT DAISY Register"]
630 pub LPSPI1_SDI_SELECT_INPUT: crate::RWRegister<u32>,
631 #[doc = "LPSPI1_SDO_SELECT_INPUT DAISY Register"]
632 pub LPSPI1_SDO_SELECT_INPUT: crate::RWRegister<u32>,
633 #[doc = "LPSPI2_PCS0_SELECT_INPUT DAISY Register"]
634 pub LPSPI2_PCS0_SELECT_INPUT: crate::RWRegister<u32>,
635 #[doc = "LPSPI2_SCK_SELECT_INPUT DAISY Register"]
636 pub LPSPI2_SCK_SELECT_INPUT: crate::RWRegister<u32>,
637 #[doc = "LPSPI2_SDI_SELECT_INPUT DAISY Register"]
638 pub LPSPI2_SDI_SELECT_INPUT: crate::RWRegister<u32>,
639 #[doc = "LPSPI2_SDO_SELECT_INPUT DAISY Register"]
640 pub LPSPI2_SDO_SELECT_INPUT: crate::RWRegister<u32>,
641 #[doc = "LPSPI3_PCS0_SELECT_INPUT DAISY Register"]
642 pub LPSPI3_PCS0_SELECT_INPUT: crate::RWRegister<u32>,
643 #[doc = "LPSPI3_SCK_SELECT_INPUT DAISY Register"]
644 pub LPSPI3_SCK_SELECT_INPUT: crate::RWRegister<u32>,
645 #[doc = "LPSPI3_SDI_SELECT_INPUT DAISY Register"]
646 pub LPSPI3_SDI_SELECT_INPUT: crate::RWRegister<u32>,
647 #[doc = "LPSPI3_SDO_SELECT_INPUT DAISY Register"]
648 pub LPSPI3_SDO_SELECT_INPUT: crate::RWRegister<u32>,
649 #[doc = "LPSPI4_PCS0_SELECT_INPUT DAISY Register"]
650 pub LPSPI4_PCS0_SELECT_INPUT: crate::RWRegister<u32>,
651 #[doc = "LPSPI4_SCK_SELECT_INPUT DAISY Register"]
652 pub LPSPI4_SCK_SELECT_INPUT: crate::RWRegister<u32>,
653 #[doc = "LPSPI4_SDI_SELECT_INPUT DAISY Register"]
654 pub LPSPI4_SDI_SELECT_INPUT: crate::RWRegister<u32>,
655 #[doc = "LPSPI4_SDO_SELECT_INPUT DAISY Register"]
656 pub LPSPI4_SDO_SELECT_INPUT: crate::RWRegister<u32>,
657 #[doc = "LPUART2_RX_SELECT_INPUT DAISY Register"]
658 pub LPUART2_RX_SELECT_INPUT: crate::RWRegister<u32>,
659 #[doc = "LPUART2_TX_SELECT_INPUT DAISY Register"]
660 pub LPUART2_TX_SELECT_INPUT: crate::RWRegister<u32>,
661 #[doc = "LPUART3_CTS_B_SELECT_INPUT DAISY Register"]
662 pub LPUART3_CTS_B_SELECT_INPUT: crate::RWRegister<u32>,
663 #[doc = "LPUART3_RX_SELECT_INPUT DAISY Register"]
664 pub LPUART3_RX_SELECT_INPUT: crate::RWRegister<u32>,
665 #[doc = "LPUART3_TX_SELECT_INPUT DAISY Register"]
666 pub LPUART3_TX_SELECT_INPUT: crate::RWRegister<u32>,
667 #[doc = "LPUART4_RX_SELECT_INPUT DAISY Register"]
668 pub LPUART4_RX_SELECT_INPUT: crate::RWRegister<u32>,
669 #[doc = "LPUART4_TX_SELECT_INPUT DAISY Register"]
670 pub LPUART4_TX_SELECT_INPUT: crate::RWRegister<u32>,
671 #[doc = "LPUART5_RX_SELECT_INPUT DAISY Register"]
672 pub LPUART5_RX_SELECT_INPUT: crate::RWRegister<u32>,
673 #[doc = "LPUART5_TX_SELECT_INPUT DAISY Register"]
674 pub LPUART5_TX_SELECT_INPUT: crate::RWRegister<u32>,
675 #[doc = "LPUART6_RX_SELECT_INPUT DAISY Register"]
676 pub LPUART6_RX_SELECT_INPUT: crate::RWRegister<u32>,
677 #[doc = "LPUART6_TX_SELECT_INPUT DAISY Register"]
678 pub LPUART6_TX_SELECT_INPUT: crate::RWRegister<u32>,
679 #[doc = "LPUART7_RX_SELECT_INPUT DAISY Register"]
680 pub LPUART7_RX_SELECT_INPUT: crate::RWRegister<u32>,
681 #[doc = "LPUART7_TX_SELECT_INPUT DAISY Register"]
682 pub LPUART7_TX_SELECT_INPUT: crate::RWRegister<u32>,
683 #[doc = "LPUART8_RX_SELECT_INPUT DAISY Register"]
684 pub LPUART8_RX_SELECT_INPUT: crate::RWRegister<u32>,
685 #[doc = "LPUART8_TX_SELECT_INPUT DAISY Register"]
686 pub LPUART8_TX_SELECT_INPUT: crate::RWRegister<u32>,
687 #[doc = "NMI_GLUE_NMI_SELECT_INPUT DAISY Register"]
688 pub NMI_SELECT_INPUT: crate::RWRegister<u32>,
689 #[doc = "QTIMER2_TIMER0_SELECT_INPUT DAISY Register"]
690 pub QTIMER2_TIMER0_SELECT_INPUT: crate::RWRegister<u32>,
691 #[doc = "QTIMER2_TIMER1_SELECT_INPUT DAISY Register"]
692 pub QTIMER2_TIMER1_SELECT_INPUT: crate::RWRegister<u32>,
693 #[doc = "QTIMER2_TIMER2_SELECT_INPUT DAISY Register"]
694 pub QTIMER2_TIMER2_SELECT_INPUT: crate::RWRegister<u32>,
695 #[doc = "QTIMER2_TIMER3_SELECT_INPUT DAISY Register"]
696 pub QTIMER2_TIMER3_SELECT_INPUT: crate::RWRegister<u32>,
697 #[doc = "QTIMER3_TIMER0_SELECT_INPUT DAISY Register"]
698 pub QTIMER3_TIMER0_SELECT_INPUT: crate::RWRegister<u32>,
699 #[doc = "QTIMER3_TIMER1_SELECT_INPUT DAISY Register"]
700 pub QTIMER3_TIMER1_SELECT_INPUT: crate::RWRegister<u32>,
701 #[doc = "QTIMER3_TIMER2_SELECT_INPUT DAISY Register"]
702 pub QTIMER3_TIMER2_SELECT_INPUT: crate::RWRegister<u32>,
703 #[doc = "QTIMER3_TIMER3_SELECT_INPUT DAISY Register"]
704 pub QTIMER3_TIMER3_SELECT_INPUT: crate::RWRegister<u32>,
705 #[doc = "SAI1_MCLK2_SELECT_INPUT DAISY Register"]
706 pub SAI1_MCLK2_SELECT_INPUT: crate::RWRegister<u32>,
707 #[doc = "SAI1_RX_BCLK_SELECT_INPUT DAISY Register"]
708 pub SAI1_RX_BCLK_SELECT_INPUT: crate::RWRegister<u32>,
709 #[doc = "SAI1_RX_DATA0_SELECT_INPUT DAISY Register"]
710 pub SAI1_RX_DATA0_SELECT_INPUT: crate::RWRegister<u32>,
711 #[doc = "SAI1_RX_DATA1_SELECT_INPUT DAISY Register"]
712 pub SAI1_RX_DATA1_SELECT_INPUT: crate::RWRegister<u32>,
713 #[doc = "SAI1_RX_DATA2_SELECT_INPUT DAISY Register"]
714 pub SAI1_RX_DATA2_SELECT_INPUT: crate::RWRegister<u32>,
715 #[doc = "SAI1_RX_DATA3_SELECT_INPUT DAISY Register"]
716 pub SAI1_RX_DATA3_SELECT_INPUT: crate::RWRegister<u32>,
717 #[doc = "SAI1_RX_SYNC_SELECT_INPUT DAISY Register"]
718 pub SAI1_RX_SYNC_SELECT_INPUT: crate::RWRegister<u32>,
719 #[doc = "SAI1_TX_BCLK_SELECT_INPUT DAISY Register"]
720 pub SAI1_TX_BCLK_SELECT_INPUT: crate::RWRegister<u32>,
721 #[doc = "SAI1_TX_SYNC_SELECT_INPUT DAISY Register"]
722 pub SAI1_TX_SYNC_SELECT_INPUT: crate::RWRegister<u32>,
723 #[doc = "SAI2_MCLK2_SELECT_INPUT DAISY Register"]
724 pub SAI2_MCLK2_SELECT_INPUT: crate::RWRegister<u32>,
725 #[doc = "SAI2_RX_BCLK_SELECT_INPUT DAISY Register"]
726 pub SAI2_RX_BCLK_SELECT_INPUT: crate::RWRegister<u32>,
727 #[doc = "SAI2_RX_DATA0_SELECT_INPUT DAISY Register"]
728 pub SAI2_RX_DATA0_SELECT_INPUT: crate::RWRegister<u32>,
729 #[doc = "SAI2_RX_SYNC_SELECT_INPUT DAISY Register"]
730 pub SAI2_RX_SYNC_SELECT_INPUT: crate::RWRegister<u32>,
731 #[doc = "SAI2_TX_BCLK_SELECT_INPUT DAISY Register"]
732 pub SAI2_TX_BCLK_SELECT_INPUT: crate::RWRegister<u32>,
733 #[doc = "SAI2_TX_SYNC_SELECT_INPUT DAISY Register"]
734 pub SAI2_TX_SYNC_SELECT_INPUT: crate::RWRegister<u32>,
735 #[doc = "SPDIF_IN_SELECT_INPUT DAISY Register"]
736 pub SPDIF_IN_SELECT_INPUT: crate::RWRegister<u32>,
737 #[doc = "USB_OTG2_OC_SELECT_INPUT DAISY Register"]
738 pub USB_OTG2_OC_SELECT_INPUT: crate::RWRegister<u32>,
739 #[doc = "USB_OTG1_OC_SELECT_INPUT DAISY Register"]
740 pub USB_OTG1_OC_SELECT_INPUT: crate::RWRegister<u32>,
741 #[doc = "USDHC1_CD_B_SELECT_INPUT DAISY Register"]
742 pub USDHC1_CD_B_SELECT_INPUT: crate::RWRegister<u32>,
743 #[doc = "USDHC1_WP_SELECT_INPUT DAISY Register"]
744 pub USDHC1_WP_SELECT_INPUT: crate::RWRegister<u32>,
745 #[doc = "USDHC2_CLK_SELECT_INPUT DAISY Register"]
746 pub USDHC2_CLK_SELECT_INPUT: crate::RWRegister<u32>,
747 #[doc = "USDHC2_CD_B_SELECT_INPUT DAISY Register"]
748 pub USDHC2_CD_B_SELECT_INPUT: crate::RWRegister<u32>,
749 #[doc = "USDHC2_CMD_SELECT_INPUT DAISY Register"]
750 pub USDHC2_CMD_SELECT_INPUT: crate::RWRegister<u32>,
751 #[doc = "USDHC2_DATA0_SELECT_INPUT DAISY Register"]
752 pub USDHC2_DATA0_SELECT_INPUT: crate::RWRegister<u32>,
753 #[doc = "USDHC2_DATA1_SELECT_INPUT DAISY Register"]
754 pub USDHC2_DATA1_SELECT_INPUT: crate::RWRegister<u32>,
755 #[doc = "USDHC2_DATA2_SELECT_INPUT DAISY Register"]
756 pub USDHC2_DATA2_SELECT_INPUT: crate::RWRegister<u32>,
757 #[doc = "USDHC2_DATA3_SELECT_INPUT DAISY Register"]
758 pub USDHC2_DATA3_SELECT_INPUT: crate::RWRegister<u32>,
759 #[doc = "USDHC2_DATA4_SELECT_INPUT DAISY Register"]
760 pub USDHC2_DATA4_SELECT_INPUT: crate::RWRegister<u32>,
761 #[doc = "USDHC2_DATA5_SELECT_INPUT DAISY Register"]
762 pub USDHC2_DATA5_SELECT_INPUT: crate::RWRegister<u32>,
763 #[doc = "USDHC2_DATA6_SELECT_INPUT DAISY Register"]
764 pub USDHC2_DATA6_SELECT_INPUT: crate::RWRegister<u32>,
765 #[doc = "USDHC2_DATA7_SELECT_INPUT DAISY Register"]
766 pub USDHC2_DATA7_SELECT_INPUT: crate::RWRegister<u32>,
767 #[doc = "USDHC2_WP_SELECT_INPUT DAISY Register"]
768 pub USDHC2_WP_SELECT_INPUT: crate::RWRegister<u32>,
769 #[doc = "XBAR1_IN02_SELECT_INPUT DAISY Register"]
770 pub XBAR1_IN02_SELECT_INPUT: crate::RWRegister<u32>,
771 #[doc = "XBAR1_IN03_SELECT_INPUT DAISY Register"]
772 pub XBAR1_IN03_SELECT_INPUT: crate::RWRegister<u32>,
773 #[doc = "XBAR1_IN04_SELECT_INPUT DAISY Register"]
774 pub XBAR1_IN04_SELECT_INPUT: crate::RWRegister<u32>,
775 #[doc = "XBAR1_IN05_SELECT_INPUT DAISY Register"]
776 pub XBAR1_IN05_SELECT_INPUT: crate::RWRegister<u32>,
777 #[doc = "XBAR1_IN06_SELECT_INPUT DAISY Register"]
778 pub XBAR1_IN06_SELECT_INPUT: crate::RWRegister<u32>,
779 #[doc = "XBAR1_IN07_SELECT_INPUT DAISY Register"]
780 pub XBAR1_IN07_SELECT_INPUT: crate::RWRegister<u32>,
781 #[doc = "XBAR1_IN08_SELECT_INPUT DAISY Register"]
782 pub XBAR1_IN08_SELECT_INPUT: crate::RWRegister<u32>,
783 #[doc = "XBAR1_IN09_SELECT_INPUT DAISY Register"]
784 pub XBAR1_IN09_SELECT_INPUT: crate::RWRegister<u32>,
785 #[doc = "XBAR1_IN17_SELECT_INPUT DAISY Register"]
786 pub XBAR1_IN17_SELECT_INPUT: crate::RWRegister<u32>,
787 #[doc = "XBAR1_IN18_SELECT_INPUT DAISY Register"]
788 pub XBAR1_IN18_SELECT_INPUT: crate::RWRegister<u32>,
789 #[doc = "XBAR1_IN20_SELECT_INPUT DAISY Register"]
790 pub XBAR1_IN20_SELECT_INPUT: crate::RWRegister<u32>,
791 #[doc = "XBAR1_IN22_SELECT_INPUT DAISY Register"]
792 pub XBAR1_IN22_SELECT_INPUT: crate::RWRegister<u32>,
793 #[doc = "XBAR1_IN23_SELECT_INPUT DAISY Register"]
794 pub XBAR1_IN23_SELECT_INPUT: crate::RWRegister<u32>,
795 #[doc = "XBAR1_IN24_SELECT_INPUT DAISY Register"]
796 pub XBAR1_IN24_SELECT_INPUT: crate::RWRegister<u32>,
797 #[doc = "XBAR1_IN14_SELECT_INPUT DAISY Register"]
798 pub XBAR1_IN14_SELECT_INPUT: crate::RWRegister<u32>,
799 #[doc = "XBAR1_IN15_SELECT_INPUT DAISY Register"]
800 pub XBAR1_IN15_SELECT_INPUT: crate::RWRegister<u32>,
801 #[doc = "XBAR1_IN16_SELECT_INPUT DAISY Register"]
802 pub XBAR1_IN16_SELECT_INPUT: crate::RWRegister<u32>,
803 #[doc = "XBAR1_IN25_SELECT_INPUT DAISY Register"]
804 pub XBAR1_IN25_SELECT_INPUT: crate::RWRegister<u32>,
805 #[doc = "XBAR1_IN19_SELECT_INPUT DAISY Register"]
806 pub XBAR1_IN19_SELECT_INPUT: crate::RWRegister<u32>,
807 #[doc = "XBAR1_IN23_SELECT_INPUT DAISY Register"]
808 pub XBAR1_IN21_SELECT_INPUT: crate::RWRegister<u32>,
809 #[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B0_00 SW MUX Control Register"]
810 pub SW_MUX_CTL_PAD_GPIO_SPI_B0_00: crate::RWRegister<u32>,
811 #[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B0_01 SW MUX Control Register"]
812 pub SW_MUX_CTL_PAD_GPIO_SPI_B0_01: crate::RWRegister<u32>,
813 #[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B0_02 SW MUX Control Register"]
814 pub SW_MUX_CTL_PAD_GPIO_SPI_B0_02: crate::RWRegister<u32>,
815 #[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B0_03 SW MUX Control Register"]
816 pub SW_MUX_CTL_PAD_GPIO_SPI_B0_03: crate::RWRegister<u32>,
817 #[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B0_04 SW MUX Control Register"]
818 pub SW_MUX_CTL_PAD_GPIO_SPI_B0_04: crate::RWRegister<u32>,
819 #[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B0_05 SW MUX Control Register"]
820 pub SW_MUX_CTL_PAD_GPIO_SPI_B0_05: crate::RWRegister<u32>,
821 #[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B0_06 SW MUX Control Register"]
822 pub SW_MUX_CTL_PAD_GPIO_SPI_B0_06: crate::RWRegister<u32>,
823 #[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B0_07 SW MUX Control Register"]
824 pub SW_MUX_CTL_PAD_GPIO_SPI_B0_07: crate::RWRegister<u32>,
825 #[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B0_08 SW MUX Control Register"]
826 pub SW_MUX_CTL_PAD_GPIO_SPI_B0_08: crate::RWRegister<u32>,
827 #[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B0_09 SW MUX Control Register"]
828 pub SW_MUX_CTL_PAD_GPIO_SPI_B0_09: crate::RWRegister<u32>,
829 #[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B0_10 SW MUX Control Register"]
830 pub SW_MUX_CTL_PAD_GPIO_SPI_B0_10: crate::RWRegister<u32>,
831 #[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B0_11 SW MUX Control Register"]
832 pub SW_MUX_CTL_PAD_GPIO_SPI_B0_11: crate::RWRegister<u32>,
833 #[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B0_12 SW MUX Control Register"]
834 pub SW_MUX_CTL_PAD_GPIO_SPI_B0_12: crate::RWRegister<u32>,
835 #[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B0_13 SW MUX Control Register"]
836 pub SW_MUX_CTL_PAD_GPIO_SPI_B0_13: crate::RWRegister<u32>,
837 #[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B1_00 SW MUX Control Register"]
838 pub SW_MUX_CTL_PAD_GPIO_SPI_B1_00: crate::RWRegister<u32>,
839 #[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B1_01 SW MUX Control Register"]
840 pub SW_MUX_CTL_PAD_GPIO_SPI_B1_01: crate::RWRegister<u32>,
841 #[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B1_02 SW MUX Control Register"]
842 pub SW_MUX_CTL_PAD_GPIO_SPI_B1_02: crate::RWRegister<u32>,
843 #[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B1_03 SW MUX Control Register"]
844 pub SW_MUX_CTL_PAD_GPIO_SPI_B1_03: crate::RWRegister<u32>,
845 #[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B1_04 SW MUX Control Register"]
846 pub SW_MUX_CTL_PAD_GPIO_SPI_B1_04: crate::RWRegister<u32>,
847 #[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B1_05 SW MUX Control Register"]
848 pub SW_MUX_CTL_PAD_GPIO_SPI_B1_05: crate::RWRegister<u32>,
849 #[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B1_06 SW MUX Control Register"]
850 pub SW_MUX_CTL_PAD_GPIO_SPI_B1_06: crate::RWRegister<u32>,
851 #[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B1_07 SW MUX Control Register"]
852 pub SW_MUX_CTL_PAD_GPIO_SPI_B1_07: crate::RWRegister<u32>,
853 #[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B0_00 SW PAD Control Register"]
854 pub SW_PAD_CTL_PAD_GPIO_SPI_B0_00: crate::RWRegister<u32>,
855 #[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B0_01 SW PAD Control Register"]
856 pub SW_PAD_CTL_PAD_GPIO_SPI_B0_01: crate::RWRegister<u32>,
857 #[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B0_02 SW PAD Control Register"]
858 pub SW_PAD_CTL_PAD_GPIO_SPI_B0_02: crate::RWRegister<u32>,
859 #[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B0_03 SW PAD Control Register"]
860 pub SW_PAD_CTL_PAD_GPIO_SPI_B0_03: crate::RWRegister<u32>,
861 #[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B0_04 SW PAD Control Register"]
862 pub SW_PAD_CTL_PAD_GPIO_SPI_B0_04: crate::RWRegister<u32>,
863 #[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B0_05 SW PAD Control Register"]
864 pub SW_PAD_CTL_PAD_GPIO_SPI_B0_05: crate::RWRegister<u32>,
865 #[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B0_06 SW PAD Control Register"]
866 pub SW_PAD_CTL_PAD_GPIO_SPI_B0_06: crate::RWRegister<u32>,
867 #[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B0_07 SW PAD Control Register"]
868 pub SW_PAD_CTL_PAD_GPIO_SPI_B0_07: crate::RWRegister<u32>,
869 #[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B0_08 SW PAD Control Register"]
870 pub SW_PAD_CTL_PAD_GPIO_SPI_B0_08: crate::RWRegister<u32>,
871 #[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B0_09 SW PAD Control Register"]
872 pub SW_PAD_CTL_PAD_GPIO_SPI_B0_09: crate::RWRegister<u32>,
873 #[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B0_10 SW PAD Control Register"]
874 pub SW_PAD_CTL_PAD_GPIO_SPI_B0_10: crate::RWRegister<u32>,
875 #[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B0_11 SW PAD Control Register"]
876 pub SW_PAD_CTL_PAD_GPIO_SPI_B0_11: crate::RWRegister<u32>,
877 #[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B0_12 SW PAD Control Register"]
878 pub SW_PAD_CTL_PAD_GPIO_SPI_B0_12: crate::RWRegister<u32>,
879 #[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B0_13 SW PAD Control Register"]
880 pub SW_PAD_CTL_PAD_GPIO_SPI_B0_13: crate::RWRegister<u32>,
881 #[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B1_00 SW PAD Control Register"]
882 pub SW_PAD_CTL_PAD_GPIO_SPI_B1_00: crate::RWRegister<u32>,
883 #[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B1_01 SW PAD Control Register"]
884 pub SW_PAD_CTL_PAD_GPIO_SPI_B1_01: crate::RWRegister<u32>,
885 #[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B1_02 SW PAD Control Register"]
886 pub SW_PAD_CTL_PAD_GPIO_SPI_B1_02: crate::RWRegister<u32>,
887 #[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B1_03 SW PAD Control Register"]
888 pub SW_PAD_CTL_PAD_GPIO_SPI_B1_03: crate::RWRegister<u32>,
889 #[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B1_04 SW PAD Control Register"]
890 pub SW_PAD_CTL_PAD_GPIO_SPI_B1_04: crate::RWRegister<u32>,
891 #[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B1_05 SW PAD Control Register"]
892 pub SW_PAD_CTL_PAD_GPIO_SPI_B1_05: crate::RWRegister<u32>,
893 #[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B1_06 SW PAD Control Register"]
894 pub SW_PAD_CTL_PAD_GPIO_SPI_B1_06: crate::RWRegister<u32>,
895 #[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B1_07 SW PAD Control Register"]
896 pub SW_PAD_CTL_PAD_GPIO_SPI_B1_07: crate::RWRegister<u32>,
897 #[doc = "ENET2_IPG_CLK_RMII_SELECT_INPUT DAISY Register"]
898 pub ENET2_IPG_CLK_RMII_SELECT_INPUT: crate::RWRegister<u32>,
899 #[doc = "ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT DAISY Register"]
900 pub ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT: crate::RWRegister<u32>,
901 #[doc = "ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_0 DAISY Register"]
902 pub ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_0: crate::RWRegister<u32>,
903 #[doc = "ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_1 DAISY Register"]
904 pub ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_1: crate::RWRegister<u32>,
905 #[doc = "ENET2_IPP_IND_MAC0_RXEN_SELECT_INPUT DAISY Register"]
906 pub ENET2_IPP_IND_MAC0_RXEN_SELECT_INPUT: crate::RWRegister<u32>,
907 #[doc = "ENET2_IPP_IND_MAC0_RXERR_SELECT_INPUT DAISY Register"]
908 pub ENET2_IPP_IND_MAC0_RXERR_SELECT_INPUT: crate::RWRegister<u32>,
909 #[doc = "ENET2_IPP_IND_MAC0_TIMER_SELECT_INPUT_0 DAISY Register"]
910 pub ENET2_IPP_IND_MAC0_TIMER_SELECT_INPUT_0: crate::RWRegister<u32>,
911 #[doc = "ENET2_IPP_IND_MAC0_TXCLK_SELECT_INPUT DAISY Register"]
912 pub ENET2_IPP_IND_MAC0_TXCLK_SELECT_INPUT: crate::RWRegister<u32>,
913 #[doc = "FLEXSPI2_IPP_IND_DQS_FA_SELECT_INPUT DAISY Register"]
914 pub FLEXSPI2_IPP_IND_DQS_FA_SELECT_INPUT: crate::RWRegister<u32>,
915 #[doc = "FLEXSPI2_IPP_IND_IO_FA_BIT0_SELECT_INPUT DAISY Register"]
916 pub FLEXSPI2_IPP_IND_IO_FA_BIT0_SELECT_INPUT: crate::RWRegister<u32>,
917 #[doc = "FLEXSPI2_IPP_IND_IO_FA_BIT1_SELECT_INPUT DAISY Register"]
918 pub FLEXSPI2_IPP_IND_IO_FA_BIT1_SELECT_INPUT: crate::RWRegister<u32>,
919 #[doc = "FLEXSPI2_IPP_IND_IO_FA_BIT2_SELECT_INPUT DAISY Register"]
920 pub FLEXSPI2_IPP_IND_IO_FA_BIT2_SELECT_INPUT: crate::RWRegister<u32>,
921 #[doc = "FLEXSPI2_IPP_IND_IO_FA_BIT3_SELECT_INPUT DAISY Register"]
922 pub FLEXSPI2_IPP_IND_IO_FA_BIT3_SELECT_INPUT: crate::RWRegister<u32>,
923 #[doc = "FLEXSPI2_IPP_IND_IO_FB_BIT0_SELECT_INPUT DAISY Register"]
924 pub FLEXSPI2_IPP_IND_IO_FB_BIT0_SELECT_INPUT: crate::RWRegister<u32>,
925 #[doc = "FLEXSPI2_IPP_IND_IO_FB_BIT1_SELECT_INPUT DAISY Register"]
926 pub FLEXSPI2_IPP_IND_IO_FB_BIT1_SELECT_INPUT: crate::RWRegister<u32>,
927 #[doc = "FLEXSPI2_IPP_IND_IO_FB_BIT2_SELECT_INPUT DAISY Register"]
928 pub FLEXSPI2_IPP_IND_IO_FB_BIT2_SELECT_INPUT: crate::RWRegister<u32>,
929 #[doc = "FLEXSPI2_IPP_IND_IO_FB_BIT3_SELECT_INPUT DAISY Register"]
930 pub FLEXSPI2_IPP_IND_IO_FB_BIT3_SELECT_INPUT: crate::RWRegister<u32>,
931 #[doc = "FLEXSPI2_IPP_IND_SCK_FA_SELECT_INPUT DAISY Register"]
932 pub FLEXSPI2_IPP_IND_SCK_FA_SELECT_INPUT: crate::RWRegister<u32>,
933 #[doc = "FLEXSPI2_IPP_IND_SCK_FB_SELECT_INPUT DAISY Register"]
934 pub FLEXSPI2_IPP_IND_SCK_FB_SELECT_INPUT: crate::RWRegister<u32>,
935 #[doc = "GPT1_IPP_IND_CAPIN1_SELECT_INPUT DAISY Register"]
936 pub GPT1_IPP_IND_CAPIN1_SELECT_INPUT: crate::RWRegister<u32>,
937 #[doc = "GPT1_IPP_IND_CAPIN2_SELECT_INPUT DAISY Register"]
938 pub GPT1_IPP_IND_CAPIN2_SELECT_INPUT: crate::RWRegister<u32>,
939 #[doc = "GPT1_IPP_IND_CLKIN_SELECT_INPUT DAISY Register"]
940 pub GPT1_IPP_IND_CLKIN_SELECT_INPUT: crate::RWRegister<u32>,
941 #[doc = "GPT2_IPP_IND_CAPIN1_SELECT_INPUT DAISY Register"]
942 pub GPT2_IPP_IND_CAPIN1_SELECT_INPUT: crate::RWRegister<u32>,
943 #[doc = "GPT2_IPP_IND_CAPIN2_SELECT_INPUT DAISY Register"]
944 pub GPT2_IPP_IND_CAPIN2_SELECT_INPUT: crate::RWRegister<u32>,
945 #[doc = "GPT2_IPP_IND_CLKIN_SELECT_INPUT DAISY Register"]
946 pub GPT2_IPP_IND_CLKIN_SELECT_INPUT: crate::RWRegister<u32>,
947 #[doc = "SAI3_IPG_CLK_SAI_MCLK_SELECT_INPUT_2 DAISY Register"]
948 pub SAI3_IPG_CLK_SAI_MCLK_SELECT_INPUT_2: crate::RWRegister<u32>,
949 #[doc = "SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT DAISY Register"]
950 pub SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT: crate::RWRegister<u32>,
951 #[doc = "SAI3_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 DAISY Register"]
952 pub SAI3_IPP_IND_SAI_RXDATA_SELECT_INPUT_0: crate::RWRegister<u32>,
953 #[doc = "SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT DAISY Register"]
954 pub SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT: crate::RWRegister<u32>,
955 #[doc = "SAI3_IPP_IND_SAI_TXBCLK_SELECT_INPUT DAISY Register"]
956 pub SAI3_IPP_IND_SAI_TXBCLK_SELECT_INPUT: crate::RWRegister<u32>,
957 #[doc = "SAI3_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register"]
958 pub SAI3_IPP_IND_SAI_TXSYNC_SELECT_INPUT: crate::RWRegister<u32>,
959 #[doc = "SEMC_I_IPP_IND_DQS4_SELECT_INPUT DAISY Register"]
960 pub SEMC_I_IPP_IND_DQS4_SELECT_INPUT: crate::RWRegister<u32>,
961 #[doc = "CANFD_IPP_IND_CANRX_SELECT_INPUT DAISY Register"]
962 pub CANFD_IPP_IND_CANRX_SELECT_INPUT: crate::RWRegister<u32>,
963}
964#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register"]
965pub mod SW_MUX_CTL_PAD_GPIO_EMC_00 {
966 #[doc = "MUX Mode Select Field."]
967 pub mod MUX_MODE {
968 pub const offset: u32 = 0;
969 pub const mask: u32 = 0x07 << offset;
970 pub mod R {}
971 pub mod W {}
972 pub mod RW {
973 #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA00 of instance: semc"]
974 pub const ALT0: u32 = 0;
975 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM4_PWMA00 of instance: flexpwm4"]
976 pub const ALT1: u32 = 0x01;
977 #[doc = "Select mux mode: ALT2 mux port: LPSPI2_SCK of instance: lpspi2"]
978 pub const ALT2: u32 = 0x02;
979 #[doc = "Select mux mode: ALT3 mux port: XBAR1_XBAR_IN02 of instance: xbar1"]
980 pub const ALT3: u32 = 0x03;
981 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO00 of instance: flexio1"]
982 pub const ALT4: u32 = 0x04;
983 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO00 of instance: gpio4"]
984 pub const ALT5: u32 = 0x05;
985 }
986 }
987 #[doc = "Software Input On Field."]
988 pub mod SION {
989 pub const offset: u32 = 4;
990 pub const mask: u32 = 0x01 << offset;
991 pub mod R {}
992 pub mod W {}
993 pub mod RW {
994 #[doc = "Input Path is determined by functionality"]
995 pub const DISABLED: u32 = 0;
996 #[doc = "Force input path of pad GPIO_EMC_00"]
997 pub const ENABLED: u32 = 0x01;
998 }
999 }
1000}
1001#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_01 SW MUX Control Register"]
1002pub mod SW_MUX_CTL_PAD_GPIO_EMC_01 {
1003 #[doc = "MUX Mode Select Field."]
1004 pub mod MUX_MODE {
1005 pub const offset: u32 = 0;
1006 pub const mask: u32 = 0x07 << offset;
1007 pub mod R {}
1008 pub mod W {}
1009 pub mod RW {
1010 #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA01 of instance: semc"]
1011 pub const ALT0: u32 = 0;
1012 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM4_PWMB00 of instance: flexpwm4"]
1013 pub const ALT1: u32 = 0x01;
1014 #[doc = "Select mux mode: ALT2 mux port: LPSPI2_PCS0 of instance: lpspi2"]
1015 pub const ALT2: u32 = 0x02;
1016 #[doc = "Select mux mode: ALT3 mux port: XBAR1_IN03 of instance: xbar1"]
1017 pub const ALT3: u32 = 0x03;
1018 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO01 of instance: flexio1"]
1019 pub const ALT4: u32 = 0x04;
1020 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO01 of instance: gpio4"]
1021 pub const ALT5: u32 = 0x05;
1022 }
1023 }
1024 #[doc = "Software Input On Field."]
1025 pub mod SION {
1026 pub const offset: u32 = 4;
1027 pub const mask: u32 = 0x01 << offset;
1028 pub mod R {}
1029 pub mod W {}
1030 pub mod RW {
1031 #[doc = "Input Path is determined by functionality"]
1032 pub const DISABLED: u32 = 0;
1033 #[doc = "Force input path of pad GPIO_EMC_01"]
1034 pub const ENABLED: u32 = 0x01;
1035 }
1036 }
1037}
1038#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_02 SW MUX Control Register"]
1039pub mod SW_MUX_CTL_PAD_GPIO_EMC_02 {
1040 #[doc = "MUX Mode Select Field."]
1041 pub mod MUX_MODE {
1042 pub const offset: u32 = 0;
1043 pub const mask: u32 = 0x07 << offset;
1044 pub mod R {}
1045 pub mod W {}
1046 pub mod RW {
1047 #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA02 of instance: semc"]
1048 pub const ALT0: u32 = 0;
1049 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM4_PWMA01 of instance: flexpwm4"]
1050 pub const ALT1: u32 = 0x01;
1051 #[doc = "Select mux mode: ALT2 mux port: LPSPI2_SDO of instance: lpspi2"]
1052 pub const ALT2: u32 = 0x02;
1053 #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT04 of instance: xbar1"]
1054 pub const ALT3: u32 = 0x03;
1055 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO02 of instance: flexio1"]
1056 pub const ALT4: u32 = 0x04;
1057 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO02 of instance: gpio4"]
1058 pub const ALT5: u32 = 0x05;
1059 }
1060 }
1061 #[doc = "Software Input On Field."]
1062 pub mod SION {
1063 pub const offset: u32 = 4;
1064 pub const mask: u32 = 0x01 << offset;
1065 pub mod R {}
1066 pub mod W {}
1067 pub mod RW {
1068 #[doc = "Input Path is determined by functionality"]
1069 pub const DISABLED: u32 = 0;
1070 #[doc = "Force input path of pad GPIO_EMC_02"]
1071 pub const ENABLED: u32 = 0x01;
1072 }
1073 }
1074}
1075#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_03 SW MUX Control Register"]
1076pub mod SW_MUX_CTL_PAD_GPIO_EMC_03 {
1077 #[doc = "MUX Mode Select Field."]
1078 pub mod MUX_MODE {
1079 pub const offset: u32 = 0;
1080 pub const mask: u32 = 0x07 << offset;
1081 pub mod R {}
1082 pub mod W {}
1083 pub mod RW {
1084 #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA03 of instance: semc"]
1085 pub const ALT0: u32 = 0;
1086 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM4_PWMB01 of instance: flexpwm4"]
1087 pub const ALT1: u32 = 0x01;
1088 #[doc = "Select mux mode: ALT2 mux port: LPSPI2_SDI of instance: lpspi2"]
1089 pub const ALT2: u32 = 0x02;
1090 #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT05 of instance: xbar1"]
1091 pub const ALT3: u32 = 0x03;
1092 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO03 of instance: flexio1"]
1093 pub const ALT4: u32 = 0x04;
1094 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO03 of instance: gpio4"]
1095 pub const ALT5: u32 = 0x05;
1096 }
1097 }
1098 #[doc = "Software Input On Field."]
1099 pub mod SION {
1100 pub const offset: u32 = 4;
1101 pub const mask: u32 = 0x01 << offset;
1102 pub mod R {}
1103 pub mod W {}
1104 pub mod RW {
1105 #[doc = "Input Path is determined by functionality"]
1106 pub const DISABLED: u32 = 0;
1107 #[doc = "Force input path of pad GPIO_EMC_03"]
1108 pub const ENABLED: u32 = 0x01;
1109 }
1110 }
1111}
1112#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_04 SW MUX Control Register"]
1113pub mod SW_MUX_CTL_PAD_GPIO_EMC_04 {
1114 #[doc = "MUX Mode Select Field."]
1115 pub mod MUX_MODE {
1116 pub const offset: u32 = 0;
1117 pub const mask: u32 = 0x07 << offset;
1118 pub mod R {}
1119 pub mod W {}
1120 pub mod RW {
1121 #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA04 of instance: semc"]
1122 pub const ALT0: u32 = 0;
1123 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM4_PWMA02 of instance: flexpwm4"]
1124 pub const ALT1: u32 = 0x01;
1125 #[doc = "Select mux mode: ALT2 mux port: SAI2_TX_DATA of instance: sai2"]
1126 pub const ALT2: u32 = 0x02;
1127 #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT06 of instance: xbar1"]
1128 pub const ALT3: u32 = 0x03;
1129 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO04 of instance: flexio1"]
1130 pub const ALT4: u32 = 0x04;
1131 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO04 of instance: gpio4"]
1132 pub const ALT5: u32 = 0x05;
1133 }
1134 }
1135 #[doc = "Software Input On Field."]
1136 pub mod SION {
1137 pub const offset: u32 = 4;
1138 pub const mask: u32 = 0x01 << offset;
1139 pub mod R {}
1140 pub mod W {}
1141 pub mod RW {
1142 #[doc = "Input Path is determined by functionality"]
1143 pub const DISABLED: u32 = 0;
1144 #[doc = "Force input path of pad GPIO_EMC_04"]
1145 pub const ENABLED: u32 = 0x01;
1146 }
1147 }
1148}
1149#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_05 SW MUX Control Register"]
1150pub mod SW_MUX_CTL_PAD_GPIO_EMC_05 {
1151 #[doc = "MUX Mode Select Field."]
1152 pub mod MUX_MODE {
1153 pub const offset: u32 = 0;
1154 pub const mask: u32 = 0x07 << offset;
1155 pub mod R {}
1156 pub mod W {}
1157 pub mod RW {
1158 #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA05 of instance: semc"]
1159 pub const ALT0: u32 = 0;
1160 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM4_PWMB02 of instance: flexpwm4"]
1161 pub const ALT1: u32 = 0x01;
1162 #[doc = "Select mux mode: ALT2 mux port: SAI2_TX_SYNC of instance: sai2"]
1163 pub const ALT2: u32 = 0x02;
1164 #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT07 of instance: xbar1"]
1165 pub const ALT3: u32 = 0x03;
1166 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO05 of instance: flexio1"]
1167 pub const ALT4: u32 = 0x04;
1168 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO05 of instance: gpio4"]
1169 pub const ALT5: u32 = 0x05;
1170 }
1171 }
1172 #[doc = "Software Input On Field."]
1173 pub mod SION {
1174 pub const offset: u32 = 4;
1175 pub const mask: u32 = 0x01 << offset;
1176 pub mod R {}
1177 pub mod W {}
1178 pub mod RW {
1179 #[doc = "Input Path is determined by functionality"]
1180 pub const DISABLED: u32 = 0;
1181 #[doc = "Force input path of pad GPIO_EMC_05"]
1182 pub const ENABLED: u32 = 0x01;
1183 }
1184 }
1185}
1186#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_06 SW MUX Control Register"]
1187pub mod SW_MUX_CTL_PAD_GPIO_EMC_06 {
1188 #[doc = "MUX Mode Select Field."]
1189 pub mod MUX_MODE {
1190 pub const offset: u32 = 0;
1191 pub const mask: u32 = 0x07 << offset;
1192 pub mod R {}
1193 pub mod W {}
1194 pub mod RW {
1195 #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA06 of instance: semc"]
1196 pub const ALT0: u32 = 0;
1197 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM2_PWMA00 of instance: flexpwm2"]
1198 pub const ALT1: u32 = 0x01;
1199 #[doc = "Select mux mode: ALT2 mux port: SAI2_TX_BCLK of instance: sai2"]
1200 pub const ALT2: u32 = 0x02;
1201 #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT08 of instance: xbar1"]
1202 pub const ALT3: u32 = 0x03;
1203 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO06 of instance: flexio1"]
1204 pub const ALT4: u32 = 0x04;
1205 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO06 of instance: gpio4"]
1206 pub const ALT5: u32 = 0x05;
1207 }
1208 }
1209 #[doc = "Software Input On Field."]
1210 pub mod SION {
1211 pub const offset: u32 = 4;
1212 pub const mask: u32 = 0x01 << offset;
1213 pub mod R {}
1214 pub mod W {}
1215 pub mod RW {
1216 #[doc = "Input Path is determined by functionality"]
1217 pub const DISABLED: u32 = 0;
1218 #[doc = "Force input path of pad GPIO_EMC_06"]
1219 pub const ENABLED: u32 = 0x01;
1220 }
1221 }
1222}
1223#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_07 SW MUX Control Register"]
1224pub mod SW_MUX_CTL_PAD_GPIO_EMC_07 {
1225 #[doc = "MUX Mode Select Field."]
1226 pub mod MUX_MODE {
1227 pub const offset: u32 = 0;
1228 pub const mask: u32 = 0x07 << offset;
1229 pub mod R {}
1230 pub mod W {}
1231 pub mod RW {
1232 #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA07 of instance: semc"]
1233 pub const ALT0: u32 = 0;
1234 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM2_PWMB00 of instance: flexpwm2"]
1235 pub const ALT1: u32 = 0x01;
1236 #[doc = "Select mux mode: ALT2 mux port: SAI2_MCLK of instance: sai2"]
1237 pub const ALT2: u32 = 0x02;
1238 #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT09 of instance: xbar1"]
1239 pub const ALT3: u32 = 0x03;
1240 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO07 of instance: flexio1"]
1241 pub const ALT4: u32 = 0x04;
1242 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO07 of instance: gpio4"]
1243 pub const ALT5: u32 = 0x05;
1244 }
1245 }
1246 #[doc = "Software Input On Field."]
1247 pub mod SION {
1248 pub const offset: u32 = 4;
1249 pub const mask: u32 = 0x01 << offset;
1250 pub mod R {}
1251 pub mod W {}
1252 pub mod RW {
1253 #[doc = "Input Path is determined by functionality"]
1254 pub const DISABLED: u32 = 0;
1255 #[doc = "Force input path of pad GPIO_EMC_07"]
1256 pub const ENABLED: u32 = 0x01;
1257 }
1258 }
1259}
1260#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_08 SW MUX Control Register"]
1261pub mod SW_MUX_CTL_PAD_GPIO_EMC_08 {
1262 #[doc = "MUX Mode Select Field."]
1263 pub mod MUX_MODE {
1264 pub const offset: u32 = 0;
1265 pub const mask: u32 = 0x07 << offset;
1266 pub mod R {}
1267 pub mod W {}
1268 pub mod RW {
1269 #[doc = "Select mux mode: ALT0 mux port: SEMC_DM00 of instance: semc"]
1270 pub const ALT0: u32 = 0;
1271 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM2_PWMA01 of instance: flexpwm2"]
1272 pub const ALT1: u32 = 0x01;
1273 #[doc = "Select mux mode: ALT2 mux port: SAI2_RX_DATA of instance: sai2"]
1274 pub const ALT2: u32 = 0x02;
1275 #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT17 of instance: xbar1"]
1276 pub const ALT3: u32 = 0x03;
1277 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO08 of instance: flexio1"]
1278 pub const ALT4: u32 = 0x04;
1279 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO08 of instance: gpio4"]
1280 pub const ALT5: u32 = 0x05;
1281 }
1282 }
1283 #[doc = "Software Input On Field."]
1284 pub mod SION {
1285 pub const offset: u32 = 4;
1286 pub const mask: u32 = 0x01 << offset;
1287 pub mod R {}
1288 pub mod W {}
1289 pub mod RW {
1290 #[doc = "Input Path is determined by functionality"]
1291 pub const DISABLED: u32 = 0;
1292 #[doc = "Force input path of pad GPIO_EMC_08"]
1293 pub const ENABLED: u32 = 0x01;
1294 }
1295 }
1296}
1297#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_09 SW MUX Control Register"]
1298pub mod SW_MUX_CTL_PAD_GPIO_EMC_09 {
1299 #[doc = "MUX Mode Select Field."]
1300 pub mod MUX_MODE {
1301 pub const offset: u32 = 0;
1302 pub const mask: u32 = 0x0f << offset;
1303 pub mod R {}
1304 pub mod W {}
1305 pub mod RW {
1306 #[doc = "Select mux mode: ALT0 mux port: SEMC_ADDR00 of instance: semc"]
1307 pub const ALT0: u32 = 0;
1308 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM2_PWMB01 of instance: flexpwm2"]
1309 pub const ALT1: u32 = 0x01;
1310 #[doc = "Select mux mode: ALT2 mux port: SAI2_RX_SYNC of instance: sai2"]
1311 pub const ALT2: u32 = 0x02;
1312 #[doc = "Select mux mode: ALT3 mux port: FLEXCAN2_TX of instance: flexcan2"]
1313 pub const ALT3: u32 = 0x03;
1314 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO09 of instance: flexio1"]
1315 pub const ALT4: u32 = 0x04;
1316 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO09 of instance: gpio4"]
1317 pub const ALT5: u32 = 0x05;
1318 #[doc = "Select mux mode: ALT8 mux port: FLEXSPI2_B_SS1_B of instance: flexspi2"]
1319 pub const ALT8: u32 = 0x08;
1320 }
1321 }
1322 #[doc = "Software Input On Field."]
1323 pub mod SION {
1324 pub const offset: u32 = 4;
1325 pub const mask: u32 = 0x01 << offset;
1326 pub mod R {}
1327 pub mod W {}
1328 pub mod RW {
1329 #[doc = "Input Path is determined by functionality"]
1330 pub const DISABLED: u32 = 0;
1331 #[doc = "Force input path of pad GPIO_EMC_09"]
1332 pub const ENABLED: u32 = 0x01;
1333 }
1334 }
1335}
1336#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_10 SW MUX Control Register"]
1337pub mod SW_MUX_CTL_PAD_GPIO_EMC_10 {
1338 #[doc = "MUX Mode Select Field."]
1339 pub mod MUX_MODE {
1340 pub const offset: u32 = 0;
1341 pub const mask: u32 = 0x0f << offset;
1342 pub mod R {}
1343 pub mod W {}
1344 pub mod RW {
1345 #[doc = "Select mux mode: ALT0 mux port: SEMC_ADDR01 of instance: semc"]
1346 pub const ALT0: u32 = 0;
1347 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM2_PWMA02 of instance: flexpwm2"]
1348 pub const ALT1: u32 = 0x01;
1349 #[doc = "Select mux mode: ALT2 mux port: SAI2_RX_BCLK of instance: sai2"]
1350 pub const ALT2: u32 = 0x02;
1351 #[doc = "Select mux mode: ALT3 mux port: FLEXCAN2_RX of instance: flexcan2"]
1352 pub const ALT3: u32 = 0x03;
1353 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO10 of instance: flexio1"]
1354 pub const ALT4: u32 = 0x04;
1355 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO10 of instance: gpio4"]
1356 pub const ALT5: u32 = 0x05;
1357 #[doc = "Select mux mode: ALT8 mux port: FLEXSPI2_B_SS0_B of instance: flexspi2"]
1358 pub const ALT8: u32 = 0x08;
1359 }
1360 }
1361 #[doc = "Software Input On Field."]
1362 pub mod SION {
1363 pub const offset: u32 = 4;
1364 pub const mask: u32 = 0x01 << offset;
1365 pub mod R {}
1366 pub mod W {}
1367 pub mod RW {
1368 #[doc = "Input Path is determined by functionality"]
1369 pub const DISABLED: u32 = 0;
1370 #[doc = "Force input path of pad GPIO_EMC_10"]
1371 pub const ENABLED: u32 = 0x01;
1372 }
1373 }
1374}
1375#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_11 SW MUX Control Register"]
1376pub mod SW_MUX_CTL_PAD_GPIO_EMC_11 {
1377 #[doc = "MUX Mode Select Field."]
1378 pub mod MUX_MODE {
1379 pub const offset: u32 = 0;
1380 pub const mask: u32 = 0x0f << offset;
1381 pub mod R {}
1382 pub mod W {}
1383 pub mod RW {
1384 #[doc = "Select mux mode: ALT0 mux port: SEMC_ADDR02 of instance: semc"]
1385 pub const ALT0: u32 = 0;
1386 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM2_PWMB02 of instance: flexpwm2"]
1387 pub const ALT1: u32 = 0x01;
1388 #[doc = "Select mux mode: ALT2 mux port: LPI2C4_SDA of instance: lpi2c4"]
1389 pub const ALT2: u32 = 0x02;
1390 #[doc = "Select mux mode: ALT3 mux port: USDHC2_RESET_B of instance: usdhc2"]
1391 pub const ALT3: u32 = 0x03;
1392 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO11 of instance: flexio1"]
1393 pub const ALT4: u32 = 0x04;
1394 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO11 of instance: gpio4"]
1395 pub const ALT5: u32 = 0x05;
1396 #[doc = "Select mux mode: ALT8 mux port: FLEXSPI2_B_DQS of instance: flexspi2"]
1397 pub const ALT8: u32 = 0x08;
1398 }
1399 }
1400 #[doc = "Software Input On Field."]
1401 pub mod SION {
1402 pub const offset: u32 = 4;
1403 pub const mask: u32 = 0x01 << offset;
1404 pub mod R {}
1405 pub mod W {}
1406 pub mod RW {
1407 #[doc = "Input Path is determined by functionality"]
1408 pub const DISABLED: u32 = 0;
1409 #[doc = "Force input path of pad GPIO_EMC_11"]
1410 pub const ENABLED: u32 = 0x01;
1411 }
1412 }
1413}
1414#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_12 SW MUX Control Register"]
1415pub mod SW_MUX_CTL_PAD_GPIO_EMC_12 {
1416 #[doc = "MUX Mode Select Field."]
1417 pub mod MUX_MODE {
1418 pub const offset: u32 = 0;
1419 pub const mask: u32 = 0x0f << offset;
1420 pub mod R {}
1421 pub mod W {}
1422 pub mod RW {
1423 #[doc = "Select mux mode: ALT0 mux port: SEMC_ADDR03 of instance: semc"]
1424 pub const ALT0: u32 = 0;
1425 #[doc = "Select mux mode: ALT1 mux port: XBAR1_IN24 of instance: xbar1"]
1426 pub const ALT1: u32 = 0x01;
1427 #[doc = "Select mux mode: ALT2 mux port: LPI2C4_SCL of instance: lpi2c4"]
1428 pub const ALT2: u32 = 0x02;
1429 #[doc = "Select mux mode: ALT3 mux port: USDHC1_WP of instance: usdhc1"]
1430 pub const ALT3: u32 = 0x03;
1431 #[doc = "Select mux mode: ALT4 mux port: FLEXPWM1_PWMA03 of instance: flexpwm1"]
1432 pub const ALT4: u32 = 0x04;
1433 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO12 of instance: gpio4"]
1434 pub const ALT5: u32 = 0x05;
1435 #[doc = "Select mux mode: ALT8 mux port: FLEXSPI2_B_SCLK of instance: flexspi2"]
1436 pub const ALT8: u32 = 0x08;
1437 }
1438 }
1439 #[doc = "Software Input On Field."]
1440 pub mod SION {
1441 pub const offset: u32 = 4;
1442 pub const mask: u32 = 0x01 << offset;
1443 pub mod R {}
1444 pub mod W {}
1445 pub mod RW {
1446 #[doc = "Input Path is determined by functionality"]
1447 pub const DISABLED: u32 = 0;
1448 #[doc = "Force input path of pad GPIO_EMC_12"]
1449 pub const ENABLED: u32 = 0x01;
1450 }
1451 }
1452}
1453#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_13 SW MUX Control Register"]
1454pub mod SW_MUX_CTL_PAD_GPIO_EMC_13 {
1455 #[doc = "MUX Mode Select Field."]
1456 pub mod MUX_MODE {
1457 pub const offset: u32 = 0;
1458 pub const mask: u32 = 0x0f << offset;
1459 pub mod R {}
1460 pub mod W {}
1461 pub mod RW {
1462 #[doc = "Select mux mode: ALT0 mux port: SEMC_ADDR04 of instance: semc"]
1463 pub const ALT0: u32 = 0;
1464 #[doc = "Select mux mode: ALT1 mux port: XBAR1_IN25 of instance: xbar1"]
1465 pub const ALT1: u32 = 0x01;
1466 #[doc = "Select mux mode: ALT2 mux port: LPUART3_TX of instance: lpuart3"]
1467 pub const ALT2: u32 = 0x02;
1468 #[doc = "Select mux mode: ALT3 mux port: MQS_RIGHT of instance: mqs"]
1469 pub const ALT3: u32 = 0x03;
1470 #[doc = "Select mux mode: ALT4 mux port: FLEXPWM1_PWMB03 of instance: flexpwm1"]
1471 pub const ALT4: u32 = 0x04;
1472 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO13 of instance: gpio4"]
1473 pub const ALT5: u32 = 0x05;
1474 #[doc = "Select mux mode: ALT8 mux port: FLEXSPI2_B_DATA00 of instance: flexspi2"]
1475 pub const ALT8: u32 = 0x08;
1476 }
1477 }
1478 #[doc = "Software Input On Field."]
1479 pub mod SION {
1480 pub const offset: u32 = 4;
1481 pub const mask: u32 = 0x01 << offset;
1482 pub mod R {}
1483 pub mod W {}
1484 pub mod RW {
1485 #[doc = "Input Path is determined by functionality"]
1486 pub const DISABLED: u32 = 0;
1487 #[doc = "Force input path of pad GPIO_EMC_13"]
1488 pub const ENABLED: u32 = 0x01;
1489 }
1490 }
1491}
1492#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_14 SW MUX Control Register"]
1493pub mod SW_MUX_CTL_PAD_GPIO_EMC_14 {
1494 #[doc = "MUX Mode Select Field."]
1495 pub mod MUX_MODE {
1496 pub const offset: u32 = 0;
1497 pub const mask: u32 = 0x0f << offset;
1498 pub mod R {}
1499 pub mod W {}
1500 pub mod RW {
1501 #[doc = "Select mux mode: ALT0 mux port: SEMC_ADDR05 of instance: semc"]
1502 pub const ALT0: u32 = 0;
1503 #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT19 of instance: xbar1"]
1504 pub const ALT1: u32 = 0x01;
1505 #[doc = "Select mux mode: ALT2 mux port: LPUART3_RX of instance: lpuart3"]
1506 pub const ALT2: u32 = 0x02;
1507 #[doc = "Select mux mode: ALT3 mux port: MQS_LEFT of instance: mqs"]
1508 pub const ALT3: u32 = 0x03;
1509 #[doc = "Select mux mode: ALT4 mux port: LPSPI2_PCS1 of instance: lpspi2"]
1510 pub const ALT4: u32 = 0x04;
1511 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO14 of instance: gpio4"]
1512 pub const ALT5: u32 = 0x05;
1513 #[doc = "Select mux mode: ALT8 mux port: FLEXSPI2_B_DATA01 of instance: flexspi2"]
1514 pub const ALT8: u32 = 0x08;
1515 }
1516 }
1517 #[doc = "Software Input On Field."]
1518 pub mod SION {
1519 pub const offset: u32 = 4;
1520 pub const mask: u32 = 0x01 << offset;
1521 pub mod R {}
1522 pub mod W {}
1523 pub mod RW {
1524 #[doc = "Input Path is determined by functionality"]
1525 pub const DISABLED: u32 = 0;
1526 #[doc = "Force input path of pad GPIO_EMC_14"]
1527 pub const ENABLED: u32 = 0x01;
1528 }
1529 }
1530}
1531#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_15 SW MUX Control Register"]
1532pub mod SW_MUX_CTL_PAD_GPIO_EMC_15 {
1533 #[doc = "MUX Mode Select Field."]
1534 pub mod MUX_MODE {
1535 pub const offset: u32 = 0;
1536 pub const mask: u32 = 0x0f << offset;
1537 pub mod R {}
1538 pub mod W {}
1539 pub mod RW {
1540 #[doc = "Select mux mode: ALT0 mux port: SEMC_ADDR06 of instance: semc"]
1541 pub const ALT0: u32 = 0;
1542 #[doc = "Select mux mode: ALT1 mux port: XBAR1_IN20 of instance: xbar1"]
1543 pub const ALT1: u32 = 0x01;
1544 #[doc = "Select mux mode: ALT2 mux port: LPUART3_CTS_B of instance: lpuart3"]
1545 pub const ALT2: u32 = 0x02;
1546 #[doc = "Select mux mode: ALT3 mux port: SPDIF_OUT of instance: spdif"]
1547 pub const ALT3: u32 = 0x03;
1548 #[doc = "Select mux mode: ALT4 mux port: QTIMER3_TIMER0 of instance: qtimer3"]
1549 pub const ALT4: u32 = 0x04;
1550 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO15 of instance: gpio4"]
1551 pub const ALT5: u32 = 0x05;
1552 #[doc = "Select mux mode: ALT8 mux port: FLEXSPI2_B_DATA02 of instance: flexspi2"]
1553 pub const ALT8: u32 = 0x08;
1554 }
1555 }
1556 #[doc = "Software Input On Field."]
1557 pub mod SION {
1558 pub const offset: u32 = 4;
1559 pub const mask: u32 = 0x01 << offset;
1560 pub mod R {}
1561 pub mod W {}
1562 pub mod RW {
1563 #[doc = "Input Path is determined by functionality"]
1564 pub const DISABLED: u32 = 0;
1565 #[doc = "Force input path of pad GPIO_EMC_15"]
1566 pub const ENABLED: u32 = 0x01;
1567 }
1568 }
1569}
1570#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_16 SW MUX Control Register"]
1571pub mod SW_MUX_CTL_PAD_GPIO_EMC_16 {
1572 #[doc = "MUX Mode Select Field."]
1573 pub mod MUX_MODE {
1574 pub const offset: u32 = 0;
1575 pub const mask: u32 = 0x0f << offset;
1576 pub mod R {}
1577 pub mod W {}
1578 pub mod RW {
1579 #[doc = "Select mux mode: ALT0 mux port: SEMC_ADDR07 of instance: semc"]
1580 pub const ALT0: u32 = 0;
1581 #[doc = "Select mux mode: ALT1 mux port: XBAR1_IN21 of instance: xbar1"]
1582 pub const ALT1: u32 = 0x01;
1583 #[doc = "Select mux mode: ALT2 mux port: LPUART3_RTS_B of instance: lpuart3"]
1584 pub const ALT2: u32 = 0x02;
1585 #[doc = "Select mux mode: ALT3 mux port: SPDIF_IN of instance: spdif"]
1586 pub const ALT3: u32 = 0x03;
1587 #[doc = "Select mux mode: ALT4 mux port: QTIMER3_TIMER1 of instance: qtimer3"]
1588 pub const ALT4: u32 = 0x04;
1589 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO16 of instance: gpio4"]
1590 pub const ALT5: u32 = 0x05;
1591 #[doc = "Select mux mode: ALT8 mux port: FLEXSPI2_B_DATA03 of instance: flexspi2"]
1592 pub const ALT8: u32 = 0x08;
1593 }
1594 }
1595 #[doc = "Software Input On Field."]
1596 pub mod SION {
1597 pub const offset: u32 = 4;
1598 pub const mask: u32 = 0x01 << offset;
1599 pub mod R {}
1600 pub mod W {}
1601 pub mod RW {
1602 #[doc = "Input Path is determined by functionality"]
1603 pub const DISABLED: u32 = 0;
1604 #[doc = "Force input path of pad GPIO_EMC_16"]
1605 pub const ENABLED: u32 = 0x01;
1606 }
1607 }
1608}
1609#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_17 SW MUX Control Register"]
1610pub mod SW_MUX_CTL_PAD_GPIO_EMC_17 {
1611 #[doc = "MUX Mode Select Field."]
1612 pub mod MUX_MODE {
1613 pub const offset: u32 = 0;
1614 pub const mask: u32 = 0x07 << offset;
1615 pub mod R {}
1616 pub mod W {}
1617 pub mod RW {
1618 #[doc = "Select mux mode: ALT0 mux port: SEMC_ADDR08 of instance: semc"]
1619 pub const ALT0: u32 = 0;
1620 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM4_PWMA03 of instance: flexpwm4"]
1621 pub const ALT1: u32 = 0x01;
1622 #[doc = "Select mux mode: ALT2 mux port: LPUART4_CTS_B of instance: lpuart4"]
1623 pub const ALT2: u32 = 0x02;
1624 #[doc = "Select mux mode: ALT3 mux port: FLEXCAN1_TX of instance: flexcan1"]
1625 pub const ALT3: u32 = 0x03;
1626 #[doc = "Select mux mode: ALT4 mux port: QTIMER3_TIMER2 of instance: qtimer3"]
1627 pub const ALT4: u32 = 0x04;
1628 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO17 of instance: gpio4"]
1629 pub const ALT5: u32 = 0x05;
1630 }
1631 }
1632 #[doc = "Software Input On Field."]
1633 pub mod SION {
1634 pub const offset: u32 = 4;
1635 pub const mask: u32 = 0x01 << offset;
1636 pub mod R {}
1637 pub mod W {}
1638 pub mod RW {
1639 #[doc = "Input Path is determined by functionality"]
1640 pub const DISABLED: u32 = 0;
1641 #[doc = "Force input path of pad GPIO_EMC_17"]
1642 pub const ENABLED: u32 = 0x01;
1643 }
1644 }
1645}
1646#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_18 SW MUX Control Register"]
1647pub mod SW_MUX_CTL_PAD_GPIO_EMC_18 {
1648 #[doc = "MUX Mode Select Field."]
1649 pub mod MUX_MODE {
1650 pub const offset: u32 = 0;
1651 pub const mask: u32 = 0x07 << offset;
1652 pub mod R {}
1653 pub mod W {}
1654 pub mod RW {
1655 #[doc = "Select mux mode: ALT0 mux port: SEMC_ADDR09 of instance: semc"]
1656 pub const ALT0: u32 = 0;
1657 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM4_PWMB03 of instance: flexpwm4"]
1658 pub const ALT1: u32 = 0x01;
1659 #[doc = "Select mux mode: ALT2 mux port: LPUART4_RTS_B of instance: lpuart4"]
1660 pub const ALT2: u32 = 0x02;
1661 #[doc = "Select mux mode: ALT3 mux port: FLEXCAN1_RX of instance: flexcan1"]
1662 pub const ALT3: u32 = 0x03;
1663 #[doc = "Select mux mode: ALT4 mux port: QTIMER3_TIMER3 of instance: qtimer3"]
1664 pub const ALT4: u32 = 0x04;
1665 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO18 of instance: gpio4"]
1666 pub const ALT5: u32 = 0x05;
1667 #[doc = "Select mux mode: ALT6 mux port: SNVS_VIO_5_CTL of instance: snvs_hp"]
1668 pub const ALT6: u32 = 0x06;
1669 }
1670 }
1671 #[doc = "Software Input On Field."]
1672 pub mod SION {
1673 pub const offset: u32 = 4;
1674 pub const mask: u32 = 0x01 << offset;
1675 pub mod R {}
1676 pub mod W {}
1677 pub mod RW {
1678 #[doc = "Input Path is determined by functionality"]
1679 pub const DISABLED: u32 = 0;
1680 #[doc = "Force input path of pad GPIO_EMC_18"]
1681 pub const ENABLED: u32 = 0x01;
1682 }
1683 }
1684}
1685#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_19 SW MUX Control Register"]
1686pub mod SW_MUX_CTL_PAD_GPIO_EMC_19 {
1687 #[doc = "MUX Mode Select Field."]
1688 pub mod MUX_MODE {
1689 pub const offset: u32 = 0;
1690 pub const mask: u32 = 0x07 << offset;
1691 pub mod R {}
1692 pub mod W {}
1693 pub mod RW {
1694 #[doc = "Select mux mode: ALT0 mux port: SEMC_ADDR11 of instance: semc"]
1695 pub const ALT0: u32 = 0;
1696 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM2_PWMA03 of instance: flexpwm2"]
1697 pub const ALT1: u32 = 0x01;
1698 #[doc = "Select mux mode: ALT2 mux port: LPUART4_TX of instance: lpuart4"]
1699 pub const ALT2: u32 = 0x02;
1700 #[doc = "Select mux mode: ALT3 mux port: ENET_RDATA01 of instance: enet"]
1701 pub const ALT3: u32 = 0x03;
1702 #[doc = "Select mux mode: ALT4 mux port: QTIMER2_TIMER0 of instance: qtimer2"]
1703 pub const ALT4: u32 = 0x04;
1704 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO19 of instance: gpio4"]
1705 pub const ALT5: u32 = 0x05;
1706 #[doc = "Select mux mode: ALT6 mux port: SNVS_VIO_5 of instance: snvs_hp"]
1707 pub const ALT6: u32 = 0x06;
1708 }
1709 }
1710 #[doc = "Software Input On Field."]
1711 pub mod SION {
1712 pub const offset: u32 = 4;
1713 pub const mask: u32 = 0x01 << offset;
1714 pub mod R {}
1715 pub mod W {}
1716 pub mod RW {
1717 #[doc = "Input Path is determined by functionality"]
1718 pub const DISABLED: u32 = 0;
1719 #[doc = "Force input path of pad GPIO_EMC_19"]
1720 pub const ENABLED: u32 = 0x01;
1721 }
1722 }
1723}
1724#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_20 SW MUX Control Register"]
1725pub mod SW_MUX_CTL_PAD_GPIO_EMC_20 {
1726 #[doc = "MUX Mode Select Field."]
1727 pub mod MUX_MODE {
1728 pub const offset: u32 = 0;
1729 pub const mask: u32 = 0x07 << offset;
1730 pub mod R {}
1731 pub mod W {}
1732 pub mod RW {
1733 #[doc = "Select mux mode: ALT0 mux port: SEMC_ADDR12 of instance: semc"]
1734 pub const ALT0: u32 = 0;
1735 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM2_PWMB03 of instance: flexpwm2"]
1736 pub const ALT1: u32 = 0x01;
1737 #[doc = "Select mux mode: ALT2 mux port: LPUART4_RX of instance: lpuart4"]
1738 pub const ALT2: u32 = 0x02;
1739 #[doc = "Select mux mode: ALT3 mux port: ENET_RDATA00 of instance: enet"]
1740 pub const ALT3: u32 = 0x03;
1741 #[doc = "Select mux mode: ALT4 mux port: QTIMER2_TIMER1 of instance: qtimer2"]
1742 pub const ALT4: u32 = 0x04;
1743 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO20 of instance: gpio4"]
1744 pub const ALT5: u32 = 0x05;
1745 }
1746 }
1747 #[doc = "Software Input On Field."]
1748 pub mod SION {
1749 pub const offset: u32 = 4;
1750 pub const mask: u32 = 0x01 << offset;
1751 pub mod R {}
1752 pub mod W {}
1753 pub mod RW {
1754 #[doc = "Input Path is determined by functionality"]
1755 pub const DISABLED: u32 = 0;
1756 #[doc = "Force input path of pad GPIO_EMC_20"]
1757 pub const ENABLED: u32 = 0x01;
1758 }
1759 }
1760}
1761#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_21 SW MUX Control Register"]
1762pub mod SW_MUX_CTL_PAD_GPIO_EMC_21 {
1763 #[doc = "MUX Mode Select Field."]
1764 pub mod MUX_MODE {
1765 pub const offset: u32 = 0;
1766 pub const mask: u32 = 0x07 << offset;
1767 pub mod R {}
1768 pub mod W {}
1769 pub mod RW {
1770 #[doc = "Select mux mode: ALT0 mux port: SEMC_BA0 of instance: semc"]
1771 pub const ALT0: u32 = 0;
1772 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM3_PWMA03 of instance: flexpwm3"]
1773 pub const ALT1: u32 = 0x01;
1774 #[doc = "Select mux mode: ALT2 mux port: LPI2C3_SDA of instance: lpi2c3"]
1775 pub const ALT2: u32 = 0x02;
1776 #[doc = "Select mux mode: ALT3 mux port: ENET_TDATA01 of instance: enet"]
1777 pub const ALT3: u32 = 0x03;
1778 #[doc = "Select mux mode: ALT4 mux port: QTIMER2_TIMER2 of instance: qtimer2"]
1779 pub const ALT4: u32 = 0x04;
1780 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO21 of instance: gpio4"]
1781 pub const ALT5: u32 = 0x05;
1782 }
1783 }
1784 #[doc = "Software Input On Field."]
1785 pub mod SION {
1786 pub const offset: u32 = 4;
1787 pub const mask: u32 = 0x01 << offset;
1788 pub mod R {}
1789 pub mod W {}
1790 pub mod RW {
1791 #[doc = "Input Path is determined by functionality"]
1792 pub const DISABLED: u32 = 0;
1793 #[doc = "Force input path of pad GPIO_EMC_21"]
1794 pub const ENABLED: u32 = 0x01;
1795 }
1796 }
1797}
1798#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_22 SW MUX Control Register"]
1799pub mod SW_MUX_CTL_PAD_GPIO_EMC_22 {
1800 #[doc = "MUX Mode Select Field."]
1801 pub mod MUX_MODE {
1802 pub const offset: u32 = 0;
1803 pub const mask: u32 = 0x0f << offset;
1804 pub mod R {}
1805 pub mod W {}
1806 pub mod RW {
1807 #[doc = "Select mux mode: ALT0 mux port: SEMC_BA1 of instance: semc"]
1808 pub const ALT0: u32 = 0;
1809 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM3_PWMB03 of instance: flexpwm3"]
1810 pub const ALT1: u32 = 0x01;
1811 #[doc = "Select mux mode: ALT2 mux port: LPI2C3_SCL of instance: lpi2c3"]
1812 pub const ALT2: u32 = 0x02;
1813 #[doc = "Select mux mode: ALT3 mux port: ENET_TDATA00 of instance: enet"]
1814 pub const ALT3: u32 = 0x03;
1815 #[doc = "Select mux mode: ALT4 mux port: QTIMER2_TIMER3 of instance: qtimer2"]
1816 pub const ALT4: u32 = 0x04;
1817 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO22 of instance: gpio4"]
1818 pub const ALT5: u32 = 0x05;
1819 #[doc = "Select mux mode: ALT8 mux port: FLEXSPI2_A_SS1_B of instance: flexspi2"]
1820 pub const ALT8: u32 = 0x08;
1821 }
1822 }
1823 #[doc = "Software Input On Field."]
1824 pub mod SION {
1825 pub const offset: u32 = 4;
1826 pub const mask: u32 = 0x01 << offset;
1827 pub mod R {}
1828 pub mod W {}
1829 pub mod RW {
1830 #[doc = "Input Path is determined by functionality"]
1831 pub const DISABLED: u32 = 0;
1832 #[doc = "Force input path of pad GPIO_EMC_22"]
1833 pub const ENABLED: u32 = 0x01;
1834 }
1835 }
1836}
1837#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_23 SW MUX Control Register"]
1838pub mod SW_MUX_CTL_PAD_GPIO_EMC_23 {
1839 #[doc = "MUX Mode Select Field."]
1840 pub mod MUX_MODE {
1841 pub const offset: u32 = 0;
1842 pub const mask: u32 = 0x0f << offset;
1843 pub mod R {}
1844 pub mod W {}
1845 pub mod RW {
1846 #[doc = "Select mux mode: ALT0 mux port: SEMC_ADDR10 of instance: semc"]
1847 pub const ALT0: u32 = 0;
1848 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM1_PWMA00 of instance: flexpwm1"]
1849 pub const ALT1: u32 = 0x01;
1850 #[doc = "Select mux mode: ALT2 mux port: LPUART5_TX of instance: lpuart5"]
1851 pub const ALT2: u32 = 0x02;
1852 #[doc = "Select mux mode: ALT3 mux port: ENET_RX_EN of instance: enet"]
1853 pub const ALT3: u32 = 0x03;
1854 #[doc = "Select mux mode: ALT4 mux port: GPT1_CAPTURE2 of instance: gpt1"]
1855 pub const ALT4: u32 = 0x04;
1856 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO23 of instance: gpio4"]
1857 pub const ALT5: u32 = 0x05;
1858 #[doc = "Select mux mode: ALT8 mux port: FLEXSPI2_A_DQS of instance: flexspi2"]
1859 pub const ALT8: u32 = 0x08;
1860 }
1861 }
1862 #[doc = "Software Input On Field."]
1863 pub mod SION {
1864 pub const offset: u32 = 4;
1865 pub const mask: u32 = 0x01 << offset;
1866 pub mod R {}
1867 pub mod W {}
1868 pub mod RW {
1869 #[doc = "Input Path is determined by functionality"]
1870 pub const DISABLED: u32 = 0;
1871 #[doc = "Force input path of pad GPIO_EMC_23"]
1872 pub const ENABLED: u32 = 0x01;
1873 }
1874 }
1875}
1876#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_24 SW MUX Control Register"]
1877pub mod SW_MUX_CTL_PAD_GPIO_EMC_24 {
1878 #[doc = "MUX Mode Select Field."]
1879 pub mod MUX_MODE {
1880 pub const offset: u32 = 0;
1881 pub const mask: u32 = 0x0f << offset;
1882 pub mod R {}
1883 pub mod W {}
1884 pub mod RW {
1885 #[doc = "Select mux mode: ALT0 mux port: SEMC_CAS of instance: semc"]
1886 pub const ALT0: u32 = 0;
1887 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM1_PWMB00 of instance: flexpwm1"]
1888 pub const ALT1: u32 = 0x01;
1889 #[doc = "Select mux mode: ALT2 mux port: LPUART5_RX of instance: lpuart5"]
1890 pub const ALT2: u32 = 0x02;
1891 #[doc = "Select mux mode: ALT3 mux port: ENET_TX_EN of instance: enet"]
1892 pub const ALT3: u32 = 0x03;
1893 #[doc = "Select mux mode: ALT4 mux port: GPT1_CAPTURE1 of instance: gpt1"]
1894 pub const ALT4: u32 = 0x04;
1895 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO24 of instance: gpio4"]
1896 pub const ALT5: u32 = 0x05;
1897 #[doc = "Select mux mode: ALT8 mux port: FLEXSPI2_A_SS0_B of instance: flexspi2"]
1898 pub const ALT8: u32 = 0x08;
1899 }
1900 }
1901 #[doc = "Software Input On Field."]
1902 pub mod SION {
1903 pub const offset: u32 = 4;
1904 pub const mask: u32 = 0x01 << offset;
1905 pub mod R {}
1906 pub mod W {}
1907 pub mod RW {
1908 #[doc = "Input Path is determined by functionality"]
1909 pub const DISABLED: u32 = 0;
1910 #[doc = "Force input path of pad GPIO_EMC_24"]
1911 pub const ENABLED: u32 = 0x01;
1912 }
1913 }
1914}
1915#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_25 SW MUX Control Register"]
1916pub mod SW_MUX_CTL_PAD_GPIO_EMC_25 {
1917 #[doc = "MUX Mode Select Field."]
1918 pub mod MUX_MODE {
1919 pub const offset: u32 = 0;
1920 pub const mask: u32 = 0x0f << offset;
1921 pub mod R {}
1922 pub mod W {}
1923 pub mod RW {
1924 #[doc = "Select mux mode: ALT0 mux port: SEMC_RAS of instance: semc"]
1925 pub const ALT0: u32 = 0;
1926 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM1_PWMA01 of instance: flexpwm1"]
1927 pub const ALT1: u32 = 0x01;
1928 #[doc = "Select mux mode: ALT2 mux port: LPUART6_TX of instance: lpuart6"]
1929 pub const ALT2: u32 = 0x02;
1930 #[doc = "Select mux mode: ALT3 mux port: ENET_TX_CLK of instance: enet"]
1931 pub const ALT3: u32 = 0x03;
1932 #[doc = "Select mux mode: ALT4 mux port: ENET_REF_CLK of instance: enet"]
1933 pub const ALT4: u32 = 0x04;
1934 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO25 of instance: gpio4"]
1935 pub const ALT5: u32 = 0x05;
1936 #[doc = "Select mux mode: ALT8 mux port: FLEXSPI2_A_SCLK of instance: flexspi2"]
1937 pub const ALT8: u32 = 0x08;
1938 }
1939 }
1940 #[doc = "Software Input On Field."]
1941 pub mod SION {
1942 pub const offset: u32 = 4;
1943 pub const mask: u32 = 0x01 << offset;
1944 pub mod R {}
1945 pub mod W {}
1946 pub mod RW {
1947 #[doc = "Input Path is determined by functionality"]
1948 pub const DISABLED: u32 = 0;
1949 #[doc = "Force input path of pad GPIO_EMC_25"]
1950 pub const ENABLED: u32 = 0x01;
1951 }
1952 }
1953}
1954#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_26 SW MUX Control Register"]
1955pub mod SW_MUX_CTL_PAD_GPIO_EMC_26 {
1956 #[doc = "MUX Mode Select Field."]
1957 pub mod MUX_MODE {
1958 pub const offset: u32 = 0;
1959 pub const mask: u32 = 0x0f << offset;
1960 pub mod R {}
1961 pub mod W {}
1962 pub mod RW {
1963 #[doc = "Select mux mode: ALT0 mux port: SEMC_CLK of instance: semc"]
1964 pub const ALT0: u32 = 0;
1965 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM1_PWMB01 of instance: flexpwm1"]
1966 pub const ALT1: u32 = 0x01;
1967 #[doc = "Select mux mode: ALT2 mux port: LPUART6_RX of instance: lpuart6"]
1968 pub const ALT2: u32 = 0x02;
1969 #[doc = "Select mux mode: ALT3 mux port: ENET_RX_ER of instance: enet"]
1970 pub const ALT3: u32 = 0x03;
1971 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO12 of instance: flexio1"]
1972 pub const ALT4: u32 = 0x04;
1973 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO26 of instance: gpio4"]
1974 pub const ALT5: u32 = 0x05;
1975 #[doc = "Select mux mode: ALT8 mux port: FLEXSPI2_A_DATA00 of instance: flexspi2"]
1976 pub const ALT8: u32 = 0x08;
1977 }
1978 }
1979 #[doc = "Software Input On Field."]
1980 pub mod SION {
1981 pub const offset: u32 = 4;
1982 pub const mask: u32 = 0x01 << offset;
1983 pub mod R {}
1984 pub mod W {}
1985 pub mod RW {
1986 #[doc = "Input Path is determined by functionality"]
1987 pub const DISABLED: u32 = 0;
1988 #[doc = "Force input path of pad GPIO_EMC_26"]
1989 pub const ENABLED: u32 = 0x01;
1990 }
1991 }
1992}
1993#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_27 SW MUX Control Register"]
1994pub mod SW_MUX_CTL_PAD_GPIO_EMC_27 {
1995 #[doc = "MUX Mode Select Field."]
1996 pub mod MUX_MODE {
1997 pub const offset: u32 = 0;
1998 pub const mask: u32 = 0x0f << offset;
1999 pub mod R {}
2000 pub mod W {}
2001 pub mod RW {
2002 #[doc = "Select mux mode: ALT0 mux port: SEMC_CKE of instance: semc"]
2003 pub const ALT0: u32 = 0;
2004 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM1_PWMA02 of instance: flexpwm1"]
2005 pub const ALT1: u32 = 0x01;
2006 #[doc = "Select mux mode: ALT2 mux port: LPUART5_RTS_B of instance: lpuart5"]
2007 pub const ALT2: u32 = 0x02;
2008 #[doc = "Select mux mode: ALT3 mux port: LPSPI1_SCK of instance: lpspi1"]
2009 pub const ALT3: u32 = 0x03;
2010 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO13 of instance: flexio1"]
2011 pub const ALT4: u32 = 0x04;
2012 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO27 of instance: gpio4"]
2013 pub const ALT5: u32 = 0x05;
2014 #[doc = "Select mux mode: ALT8 mux port: FLEXSPI2_A_DATA01 of instance: flexspi2"]
2015 pub const ALT8: u32 = 0x08;
2016 }
2017 }
2018 #[doc = "Software Input On Field."]
2019 pub mod SION {
2020 pub const offset: u32 = 4;
2021 pub const mask: u32 = 0x01 << offset;
2022 pub mod R {}
2023 pub mod W {}
2024 pub mod RW {
2025 #[doc = "Input Path is determined by functionality"]
2026 pub const DISABLED: u32 = 0;
2027 #[doc = "Force input path of pad GPIO_EMC_27"]
2028 pub const ENABLED: u32 = 0x01;
2029 }
2030 }
2031}
2032#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_28 SW MUX Control Register"]
2033pub mod SW_MUX_CTL_PAD_GPIO_EMC_28 {
2034 #[doc = "MUX Mode Select Field."]
2035 pub mod MUX_MODE {
2036 pub const offset: u32 = 0;
2037 pub const mask: u32 = 0x0f << offset;
2038 pub mod R {}
2039 pub mod W {}
2040 pub mod RW {
2041 #[doc = "Select mux mode: ALT0 mux port: SEMC_WE of instance: semc"]
2042 pub const ALT0: u32 = 0;
2043 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM1_PWMB02 of instance: flexpwm1"]
2044 pub const ALT1: u32 = 0x01;
2045 #[doc = "Select mux mode: ALT2 mux port: LPUART5_CTS_B of instance: lpuart5"]
2046 pub const ALT2: u32 = 0x02;
2047 #[doc = "Select mux mode: ALT3 mux port: LPSPI1_SDO of instance: lpspi1"]
2048 pub const ALT3: u32 = 0x03;
2049 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO14 of instance: flexio1"]
2050 pub const ALT4: u32 = 0x04;
2051 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO28 of instance: gpio4"]
2052 pub const ALT5: u32 = 0x05;
2053 #[doc = "Select mux mode: ALT8 mux port: FLEXSPI2_A_DATA02 of instance: flexspi2"]
2054 pub const ALT8: u32 = 0x08;
2055 }
2056 }
2057 #[doc = "Software Input On Field."]
2058 pub mod SION {
2059 pub const offset: u32 = 4;
2060 pub const mask: u32 = 0x01 << offset;
2061 pub mod R {}
2062 pub mod W {}
2063 pub mod RW {
2064 #[doc = "Input Path is determined by functionality"]
2065 pub const DISABLED: u32 = 0;
2066 #[doc = "Force input path of pad GPIO_EMC_28"]
2067 pub const ENABLED: u32 = 0x01;
2068 }
2069 }
2070}
2071#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_29 SW MUX Control Register"]
2072pub mod SW_MUX_CTL_PAD_GPIO_EMC_29 {
2073 #[doc = "MUX Mode Select Field."]
2074 pub mod MUX_MODE {
2075 pub const offset: u32 = 0;
2076 pub const mask: u32 = 0x0f << offset;
2077 pub mod R {}
2078 pub mod W {}
2079 pub mod RW {
2080 #[doc = "Select mux mode: ALT0 mux port: SEMC_CS0 of instance: semc"]
2081 pub const ALT0: u32 = 0;
2082 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM3_PWMA00 of instance: flexpwm3"]
2083 pub const ALT1: u32 = 0x01;
2084 #[doc = "Select mux mode: ALT2 mux port: LPUART6_RTS_B of instance: lpuart6"]
2085 pub const ALT2: u32 = 0x02;
2086 #[doc = "Select mux mode: ALT3 mux port: LPSPI1_SDI of instance: lpspi1"]
2087 pub const ALT3: u32 = 0x03;
2088 #[doc = "Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO15 of instance: flexio1"]
2089 pub const ALT4: u32 = 0x04;
2090 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO29 of instance: gpio4"]
2091 pub const ALT5: u32 = 0x05;
2092 #[doc = "Select mux mode: ALT8 mux port: FLEXSPI2_A_DATA03 of instance: flexspi2"]
2093 pub const ALT8: u32 = 0x08;
2094 }
2095 }
2096 #[doc = "Software Input On Field."]
2097 pub mod SION {
2098 pub const offset: u32 = 4;
2099 pub const mask: u32 = 0x01 << offset;
2100 pub mod R {}
2101 pub mod W {}
2102 pub mod RW {
2103 #[doc = "Input Path is determined by functionality"]
2104 pub const DISABLED: u32 = 0;
2105 #[doc = "Force input path of pad GPIO_EMC_29"]
2106 pub const ENABLED: u32 = 0x01;
2107 }
2108 }
2109}
2110#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_30 SW MUX Control Register"]
2111pub mod SW_MUX_CTL_PAD_GPIO_EMC_30 {
2112 #[doc = "MUX Mode Select Field."]
2113 pub mod MUX_MODE {
2114 pub const offset: u32 = 0;
2115 pub const mask: u32 = 0x0f << offset;
2116 pub mod R {}
2117 pub mod W {}
2118 pub mod RW {
2119 #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA08 of instance: semc"]
2120 pub const ALT0: u32 = 0;
2121 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM3_PWMB00 of instance: flexpwm3"]
2122 pub const ALT1: u32 = 0x01;
2123 #[doc = "Select mux mode: ALT2 mux port: LPUART6_CTS_B of instance: lpuart6"]
2124 pub const ALT2: u32 = 0x02;
2125 #[doc = "Select mux mode: ALT3 mux port: LPSPI1_PCS0 of instance: lpspi1"]
2126 pub const ALT3: u32 = 0x03;
2127 #[doc = "Select mux mode: ALT4 mux port: CSI_DATA23 of instance: csi"]
2128 pub const ALT4: u32 = 0x04;
2129 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO30 of instance: gpio4"]
2130 pub const ALT5: u32 = 0x05;
2131 #[doc = "Select mux mode: ALT8 mux port: ENET2_TDATA00 of instance: enet2"]
2132 pub const ALT8: u32 = 0x08;
2133 }
2134 }
2135 #[doc = "Software Input On Field."]
2136 pub mod SION {
2137 pub const offset: u32 = 4;
2138 pub const mask: u32 = 0x01 << offset;
2139 pub mod R {}
2140 pub mod W {}
2141 pub mod RW {
2142 #[doc = "Input Path is determined by functionality"]
2143 pub const DISABLED: u32 = 0;
2144 #[doc = "Force input path of pad GPIO_EMC_30"]
2145 pub const ENABLED: u32 = 0x01;
2146 }
2147 }
2148}
2149#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_31 SW MUX Control Register"]
2150pub mod SW_MUX_CTL_PAD_GPIO_EMC_31 {
2151 #[doc = "MUX Mode Select Field."]
2152 pub mod MUX_MODE {
2153 pub const offset: u32 = 0;
2154 pub const mask: u32 = 0x0f << offset;
2155 pub mod R {}
2156 pub mod W {}
2157 pub mod RW {
2158 #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA09 of instance: semc"]
2159 pub const ALT0: u32 = 0;
2160 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM3_PWMA01 of instance: flexpwm3"]
2161 pub const ALT1: u32 = 0x01;
2162 #[doc = "Select mux mode: ALT2 mux port: LPUART7_TX of instance: lpuart7"]
2163 pub const ALT2: u32 = 0x02;
2164 #[doc = "Select mux mode: ALT3 mux port: LPSPI1_PCS1 of instance: lpspi1"]
2165 pub const ALT3: u32 = 0x03;
2166 #[doc = "Select mux mode: ALT4 mux port: CSI_DATA22 of instance: csi"]
2167 pub const ALT4: u32 = 0x04;
2168 #[doc = "Select mux mode: ALT5 mux port: GPIO4_IO31 of instance: gpio4"]
2169 pub const ALT5: u32 = 0x05;
2170 #[doc = "Select mux mode: ALT8 mux port: ENET2_TDATA01 of instance: enet2"]
2171 pub const ALT8: u32 = 0x08;
2172 }
2173 }
2174 #[doc = "Software Input On Field."]
2175 pub mod SION {
2176 pub const offset: u32 = 4;
2177 pub const mask: u32 = 0x01 << offset;
2178 pub mod R {}
2179 pub mod W {}
2180 pub mod RW {
2181 #[doc = "Input Path is determined by functionality"]
2182 pub const DISABLED: u32 = 0;
2183 #[doc = "Force input path of pad GPIO_EMC_31"]
2184 pub const ENABLED: u32 = 0x01;
2185 }
2186 }
2187}
2188#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_32 SW MUX Control Register"]
2189pub mod SW_MUX_CTL_PAD_GPIO_EMC_32 {
2190 #[doc = "MUX Mode Select Field."]
2191 pub mod MUX_MODE {
2192 pub const offset: u32 = 0;
2193 pub const mask: u32 = 0x0f << offset;
2194 pub mod R {}
2195 pub mod W {}
2196 pub mod RW {
2197 #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA10 of instance: semc"]
2198 pub const ALT0: u32 = 0;
2199 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM3_PWMB01 of instance: flexpwm3"]
2200 pub const ALT1: u32 = 0x01;
2201 #[doc = "Select mux mode: ALT2 mux port: LPUART7_RX of instance: lpuart7"]
2202 pub const ALT2: u32 = 0x02;
2203 #[doc = "Select mux mode: ALT3 mux port: CCM_PMIC_RDY of instance: ccm"]
2204 pub const ALT3: u32 = 0x03;
2205 #[doc = "Select mux mode: ALT4 mux port: CSI_DATA21 of instance: csi"]
2206 pub const ALT4: u32 = 0x04;
2207 #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO18 of instance: gpio3"]
2208 pub const ALT5: u32 = 0x05;
2209 #[doc = "Select mux mode: ALT8 mux port: ENET2_TX_EN of instance: enet2"]
2210 pub const ALT8: u32 = 0x08;
2211 }
2212 }
2213 #[doc = "Software Input On Field."]
2214 pub mod SION {
2215 pub const offset: u32 = 4;
2216 pub const mask: u32 = 0x01 << offset;
2217 pub mod R {}
2218 pub mod W {}
2219 pub mod RW {
2220 #[doc = "Input Path is determined by functionality"]
2221 pub const DISABLED: u32 = 0;
2222 #[doc = "Force input path of pad GPIO_EMC_32"]
2223 pub const ENABLED: u32 = 0x01;
2224 }
2225 }
2226}
2227#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_33 SW MUX Control Register"]
2228pub mod SW_MUX_CTL_PAD_GPIO_EMC_33 {
2229 #[doc = "MUX Mode Select Field."]
2230 pub mod MUX_MODE {
2231 pub const offset: u32 = 0;
2232 pub const mask: u32 = 0x0f << offset;
2233 pub mod R {}
2234 pub mod W {}
2235 pub mod RW {
2236 #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA11 of instance: semc"]
2237 pub const ALT0: u32 = 0;
2238 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM3_PWMA02 of instance: flexpwm3"]
2239 pub const ALT1: u32 = 0x01;
2240 #[doc = "Select mux mode: ALT2 mux port: USDHC1_RESET_B of instance: usdhc1"]
2241 pub const ALT2: u32 = 0x02;
2242 #[doc = "Select mux mode: ALT3 mux port: SAI3_RX_DATA of instance: sai3"]
2243 pub const ALT3: u32 = 0x03;
2244 #[doc = "Select mux mode: ALT4 mux port: CSI_DATA20 of instance: csi"]
2245 pub const ALT4: u32 = 0x04;
2246 #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO19 of instance: gpio3"]
2247 pub const ALT5: u32 = 0x05;
2248 #[doc = "Select mux mode: ALT8 mux port: ENET2_TX_CLK of instance: enet2"]
2249 pub const ALT8: u32 = 0x08;
2250 #[doc = "Select mux mode: ALT9 mux port: ENET2_REF_CLK2 of instance: enet2"]
2251 pub const ALT9: u32 = 0x09;
2252 }
2253 }
2254 #[doc = "Software Input On Field."]
2255 pub mod SION {
2256 pub const offset: u32 = 4;
2257 pub const mask: u32 = 0x01 << offset;
2258 pub mod R {}
2259 pub mod W {}
2260 pub mod RW {
2261 #[doc = "Input Path is determined by functionality"]
2262 pub const DISABLED: u32 = 0;
2263 #[doc = "Force input path of pad GPIO_EMC_33"]
2264 pub const ENABLED: u32 = 0x01;
2265 }
2266 }
2267}
2268#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_34 SW MUX Control Register"]
2269pub mod SW_MUX_CTL_PAD_GPIO_EMC_34 {
2270 #[doc = "MUX Mode Select Field."]
2271 pub mod MUX_MODE {
2272 pub const offset: u32 = 0;
2273 pub const mask: u32 = 0x0f << offset;
2274 pub mod R {}
2275 pub mod W {}
2276 pub mod RW {
2277 #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA12 of instance: semc"]
2278 pub const ALT0: u32 = 0;
2279 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM3_PWMB02 of instance: flexpwm3"]
2280 pub const ALT1: u32 = 0x01;
2281 #[doc = "Select mux mode: ALT2 mux port: USDHC1_VSELECT of instance: usdhc1"]
2282 pub const ALT2: u32 = 0x02;
2283 #[doc = "Select mux mode: ALT3 mux port: SAI3_RX_SYNC of instance: sai3"]
2284 pub const ALT3: u32 = 0x03;
2285 #[doc = "Select mux mode: ALT4 mux port: CSI_DATA19 of instance: csi"]
2286 pub const ALT4: u32 = 0x04;
2287 #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO20 of instance: gpio3"]
2288 pub const ALT5: u32 = 0x05;
2289 #[doc = "Select mux mode: ALT8 mux port: ENET2_RX_ER of instance: enet2"]
2290 pub const ALT8: u32 = 0x08;
2291 }
2292 }
2293 #[doc = "Software Input On Field."]
2294 pub mod SION {
2295 pub const offset: u32 = 4;
2296 pub const mask: u32 = 0x01 << offset;
2297 pub mod R {}
2298 pub mod W {}
2299 pub mod RW {
2300 #[doc = "Input Path is determined by functionality"]
2301 pub const DISABLED: u32 = 0;
2302 #[doc = "Force input path of pad GPIO_EMC_34"]
2303 pub const ENABLED: u32 = 0x01;
2304 }
2305 }
2306}
2307#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_35 SW MUX Control Register"]
2308pub mod SW_MUX_CTL_PAD_GPIO_EMC_35 {
2309 #[doc = "MUX Mode Select Field."]
2310 pub mod MUX_MODE {
2311 pub const offset: u32 = 0;
2312 pub const mask: u32 = 0x0f << offset;
2313 pub mod R {}
2314 pub mod W {}
2315 pub mod RW {
2316 #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA13 of instance: semc"]
2317 pub const ALT0: u32 = 0;
2318 #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT18 of instance: xbar1"]
2319 pub const ALT1: u32 = 0x01;
2320 #[doc = "Select mux mode: ALT2 mux port: GPT1_COMPARE1 of instance: gpt1"]
2321 pub const ALT2: u32 = 0x02;
2322 #[doc = "Select mux mode: ALT3 mux port: SAI3_RX_BCLK of instance: sai3"]
2323 pub const ALT3: u32 = 0x03;
2324 #[doc = "Select mux mode: ALT4 mux port: CSI_DATA18 of instance: csi"]
2325 pub const ALT4: u32 = 0x04;
2326 #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO21 of instance: gpio3"]
2327 pub const ALT5: u32 = 0x05;
2328 #[doc = "Select mux mode: ALT6 mux port: USDHC1_CD_B of instance: usdhc1"]
2329 pub const ALT6: u32 = 0x06;
2330 #[doc = "Select mux mode: ALT8 mux port: ENET2_RDATA00 of instance: enet2"]
2331 pub const ALT8: u32 = 0x08;
2332 }
2333 }
2334 #[doc = "Software Input On Field."]
2335 pub mod SION {
2336 pub const offset: u32 = 4;
2337 pub const mask: u32 = 0x01 << offset;
2338 pub mod R {}
2339 pub mod W {}
2340 pub mod RW {
2341 #[doc = "Input Path is determined by functionality"]
2342 pub const DISABLED: u32 = 0;
2343 #[doc = "Force input path of pad GPIO_EMC_35"]
2344 pub const ENABLED: u32 = 0x01;
2345 }
2346 }
2347}
2348#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_36 SW MUX Control Register"]
2349pub mod SW_MUX_CTL_PAD_GPIO_EMC_36 {
2350 #[doc = "MUX Mode Select Field."]
2351 pub mod MUX_MODE {
2352 pub const offset: u32 = 0;
2353 pub const mask: u32 = 0x0f << offset;
2354 pub mod R {}
2355 pub mod W {}
2356 pub mod RW {
2357 #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA14 of instance: semc"]
2358 pub const ALT0: u32 = 0;
2359 #[doc = "Select mux mode: ALT1 mux port: XBAR1_IN22 of instance: xbar1"]
2360 pub const ALT1: u32 = 0x01;
2361 #[doc = "Select mux mode: ALT2 mux port: GPT1_COMPARE2 of instance: gpt1"]
2362 pub const ALT2: u32 = 0x02;
2363 #[doc = "Select mux mode: ALT3 mux port: SAI3_TX_DATA of instance: sai3"]
2364 pub const ALT3: u32 = 0x03;
2365 #[doc = "Select mux mode: ALT4 mux port: CSI_DATA17 of instance: csi"]
2366 pub const ALT4: u32 = 0x04;
2367 #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO22 of instance: gpio3"]
2368 pub const ALT5: u32 = 0x05;
2369 #[doc = "Select mux mode: ALT6 mux port: USDHC1_WP of instance: usdhc1"]
2370 pub const ALT6: u32 = 0x06;
2371 #[doc = "Select mux mode: ALT8 mux port: ENET2_RDATA01 of instance: enet2"]
2372 pub const ALT8: u32 = 0x08;
2373 #[doc = "Select mux mode: ALT9 mux port: FLEXCAN3_TX of instance: flexcan3/canfd"]
2374 pub const ALT9: u32 = 0x09;
2375 }
2376 }
2377 #[doc = "Software Input On Field."]
2378 pub mod SION {
2379 pub const offset: u32 = 4;
2380 pub const mask: u32 = 0x01 << offset;
2381 pub mod R {}
2382 pub mod W {}
2383 pub mod RW {
2384 #[doc = "Input Path is determined by functionality"]
2385 pub const DISABLED: u32 = 0;
2386 #[doc = "Force input path of pad GPIO_EMC_36"]
2387 pub const ENABLED: u32 = 0x01;
2388 }
2389 }
2390}
2391#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_37 SW MUX Control Register"]
2392pub mod SW_MUX_CTL_PAD_GPIO_EMC_37 {
2393 #[doc = "MUX Mode Select Field."]
2394 pub mod MUX_MODE {
2395 pub const offset: u32 = 0;
2396 pub const mask: u32 = 0x0f << offset;
2397 pub mod R {}
2398 pub mod W {}
2399 pub mod RW {
2400 #[doc = "Select mux mode: ALT0 mux port: SEMC_DATA15 of instance: semc"]
2401 pub const ALT0: u32 = 0;
2402 #[doc = "Select mux mode: ALT1 mux port: XBAR1_IN23 of instance: xbar1"]
2403 pub const ALT1: u32 = 0x01;
2404 #[doc = "Select mux mode: ALT2 mux port: GPT1_COMPARE3 of instance: gpt1"]
2405 pub const ALT2: u32 = 0x02;
2406 #[doc = "Select mux mode: ALT3 mux port: SAI3_MCLK of instance: sai3"]
2407 pub const ALT3: u32 = 0x03;
2408 #[doc = "Select mux mode: ALT4 mux port: CSI_DATA16 of instance: csi"]
2409 pub const ALT4: u32 = 0x04;
2410 #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO23 of instance: gpio3"]
2411 pub const ALT5: u32 = 0x05;
2412 #[doc = "Select mux mode: ALT6 mux port: USDHC2_WP of instance: usdhc2"]
2413 pub const ALT6: u32 = 0x06;
2414 #[doc = "Select mux mode: ALT8 mux port: ENET2_RX_EN of instance: enet2"]
2415 pub const ALT8: u32 = 0x08;
2416 #[doc = "Select mux mode: ALT9 mux port: FLEXCAN3_RX of instance: flexcan3/canfd"]
2417 pub const ALT9: u32 = 0x09;
2418 }
2419 }
2420 #[doc = "Software Input On Field."]
2421 pub mod SION {
2422 pub const offset: u32 = 4;
2423 pub const mask: u32 = 0x01 << offset;
2424 pub mod R {}
2425 pub mod W {}
2426 pub mod RW {
2427 #[doc = "Input Path is determined by functionality"]
2428 pub const DISABLED: u32 = 0;
2429 #[doc = "Force input path of pad GPIO_EMC_37"]
2430 pub const ENABLED: u32 = 0x01;
2431 }
2432 }
2433}
2434#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_38 SW MUX Control Register"]
2435pub mod SW_MUX_CTL_PAD_GPIO_EMC_38 {
2436 #[doc = "MUX Mode Select Field."]
2437 pub mod MUX_MODE {
2438 pub const offset: u32 = 0;
2439 pub const mask: u32 = 0x0f << offset;
2440 pub mod R {}
2441 pub mod W {}
2442 pub mod RW {
2443 #[doc = "Select mux mode: ALT0 mux port: SEMC_DM01 of instance: semc"]
2444 pub const ALT0: u32 = 0;
2445 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM1_PWMA03 of instance: flexpwm1"]
2446 pub const ALT1: u32 = 0x01;
2447 #[doc = "Select mux mode: ALT2 mux port: LPUART8_TX of instance: lpuart8"]
2448 pub const ALT2: u32 = 0x02;
2449 #[doc = "Select mux mode: ALT3 mux port: SAI3_TX_BCLK of instance: sai3"]
2450 pub const ALT3: u32 = 0x03;
2451 #[doc = "Select mux mode: ALT4 mux port: CSI_FIELD of instance: csi"]
2452 pub const ALT4: u32 = 0x04;
2453 #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO24 of instance: gpio3"]
2454 pub const ALT5: u32 = 0x05;
2455 #[doc = "Select mux mode: ALT6 mux port: USDHC2_VSELECT of instance: usdhc2"]
2456 pub const ALT6: u32 = 0x06;
2457 #[doc = "Select mux mode: ALT8 mux port: ENET2_MDC of instance: enet2"]
2458 pub const ALT8: u32 = 0x08;
2459 }
2460 }
2461 #[doc = "Software Input On Field."]
2462 pub mod SION {
2463 pub const offset: u32 = 4;
2464 pub const mask: u32 = 0x01 << offset;
2465 pub mod R {}
2466 pub mod W {}
2467 pub mod RW {
2468 #[doc = "Input Path is determined by functionality"]
2469 pub const DISABLED: u32 = 0;
2470 #[doc = "Force input path of pad GPIO_EMC_38"]
2471 pub const ENABLED: u32 = 0x01;
2472 }
2473 }
2474}
2475#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_39 SW MUX Control Register"]
2476pub mod SW_MUX_CTL_PAD_GPIO_EMC_39 {
2477 #[doc = "MUX Mode Select Field."]
2478 pub mod MUX_MODE {
2479 pub const offset: u32 = 0;
2480 pub const mask: u32 = 0x0f << offset;
2481 pub mod R {}
2482 pub mod W {}
2483 pub mod RW {
2484 #[doc = "Select mux mode: ALT0 mux port: SEMC_DQS of instance: semc"]
2485 pub const ALT0: u32 = 0;
2486 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM1_PWMB03 of instance: flexpwm1"]
2487 pub const ALT1: u32 = 0x01;
2488 #[doc = "Select mux mode: ALT2 mux port: LPUART8_RX of instance: lpuart8"]
2489 pub const ALT2: u32 = 0x02;
2490 #[doc = "Select mux mode: ALT3 mux port: SAI3_TX_SYNC of instance: sai3"]
2491 pub const ALT3: u32 = 0x03;
2492 #[doc = "Select mux mode: ALT4 mux port: WDOG1_WDOG_B of instance: wdog1"]
2493 pub const ALT4: u32 = 0x04;
2494 #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO25 of instance: gpio3"]
2495 pub const ALT5: u32 = 0x05;
2496 #[doc = "Select mux mode: ALT6 mux port: USDHC2_CD_B of instance: usdhc2"]
2497 pub const ALT6: u32 = 0x06;
2498 #[doc = "Select mux mode: ALT8 mux port: ENET2_MDIO of instance: enet2"]
2499 pub const ALT8: u32 = 0x08;
2500 #[doc = "Select mux mode: ALT9 mux port: SEMC_DQS4 of instance: semc"]
2501 pub const ALT9: u32 = 0x09;
2502 }
2503 }
2504 #[doc = "Software Input On Field."]
2505 pub mod SION {
2506 pub const offset: u32 = 4;
2507 pub const mask: u32 = 0x01 << offset;
2508 pub mod R {}
2509 pub mod W {}
2510 pub mod RW {
2511 #[doc = "Input Path is determined by functionality"]
2512 pub const DISABLED: u32 = 0;
2513 #[doc = "Force input path of pad GPIO_EMC_39"]
2514 pub const ENABLED: u32 = 0x01;
2515 }
2516 }
2517}
2518#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_40 SW MUX Control Register"]
2519pub mod SW_MUX_CTL_PAD_GPIO_EMC_40 {
2520 #[doc = "MUX Mode Select Field."]
2521 pub mod MUX_MODE {
2522 pub const offset: u32 = 0;
2523 pub const mask: u32 = 0x0f << offset;
2524 pub mod R {}
2525 pub mod W {}
2526 pub mod RW {
2527 #[doc = "Select mux mode: ALT0 mux port: SEMC_RDY of instance: semc"]
2528 pub const ALT0: u32 = 0;
2529 #[doc = "Select mux mode: ALT1 mux port: GPT2_CAPTURE2 of instance: gpt2"]
2530 pub const ALT1: u32 = 0x01;
2531 #[doc = "Select mux mode: ALT2 mux port: LPSPI1_PCS2 of instance: lpspi1"]
2532 pub const ALT2: u32 = 0x02;
2533 #[doc = "Select mux mode: ALT3 mux port: USB_OTG2_OC of instance: usb"]
2534 pub const ALT3: u32 = 0x03;
2535 #[doc = "Select mux mode: ALT4 mux port: ENET_MDC of instance: enet"]
2536 pub const ALT4: u32 = 0x04;
2537 #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO26 of instance: gpio3"]
2538 pub const ALT5: u32 = 0x05;
2539 #[doc = "Select mux mode: ALT6 mux port: USDHC2_RESET_B of instance: usdhc2"]
2540 pub const ALT6: u32 = 0x06;
2541 #[doc = "Select mux mode: ALT9 mux port: SEMC_CLK5 of instance: semc"]
2542 pub const ALT9: u32 = 0x09;
2543 }
2544 }
2545 #[doc = "Software Input On Field."]
2546 pub mod SION {
2547 pub const offset: u32 = 4;
2548 pub const mask: u32 = 0x01 << offset;
2549 pub mod R {}
2550 pub mod W {}
2551 pub mod RW {
2552 #[doc = "Input Path is determined by functionality"]
2553 pub const DISABLED: u32 = 0;
2554 #[doc = "Force input path of pad GPIO_EMC_40"]
2555 pub const ENABLED: u32 = 0x01;
2556 }
2557 }
2558}
2559#[doc = "SW_MUX_CTL_PAD_GPIO_EMC_41 SW MUX Control Register"]
2560pub mod SW_MUX_CTL_PAD_GPIO_EMC_41 {
2561 #[doc = "MUX Mode Select Field."]
2562 pub mod MUX_MODE {
2563 pub const offset: u32 = 0;
2564 pub const mask: u32 = 0x07 << offset;
2565 pub mod R {}
2566 pub mod W {}
2567 pub mod RW {
2568 #[doc = "Select mux mode: ALT0 mux port: SEMC_CSX00 of instance: semc"]
2569 pub const ALT0: u32 = 0;
2570 #[doc = "Select mux mode: ALT1 mux port: GPT2_CAPTURE1 of instance: gpt2"]
2571 pub const ALT1: u32 = 0x01;
2572 #[doc = "Select mux mode: ALT2 mux port: LPSPI1_PCS3 of instance: lpspi1"]
2573 pub const ALT2: u32 = 0x02;
2574 #[doc = "Select mux mode: ALT3 mux port: USB_OTG2_PWR of instance: usb"]
2575 pub const ALT3: u32 = 0x03;
2576 #[doc = "Select mux mode: ALT4 mux port: ENET_MDIO of instance: enet"]
2577 pub const ALT4: u32 = 0x04;
2578 #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO27 of instance: gpio3"]
2579 pub const ALT5: u32 = 0x05;
2580 #[doc = "Select mux mode: ALT6 mux port: USDHC1_VSELECT of instance: usdhc1"]
2581 pub const ALT6: u32 = 0x06;
2582 }
2583 }
2584 #[doc = "Software Input On Field."]
2585 pub mod SION {
2586 pub const offset: u32 = 4;
2587 pub const mask: u32 = 0x01 << offset;
2588 pub mod R {}
2589 pub mod W {}
2590 pub mod RW {
2591 #[doc = "Input Path is determined by functionality"]
2592 pub const DISABLED: u32 = 0;
2593 #[doc = "Force input path of pad GPIO_EMC_41"]
2594 pub const ENABLED: u32 = 0x01;
2595 }
2596 }
2597}
2598#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_00 SW MUX Control Register"]
2599pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_00 {
2600 #[doc = "MUX Mode Select Field."]
2601 pub mod MUX_MODE {
2602 pub const offset: u32 = 0;
2603 pub const mask: u32 = 0x07 << offset;
2604 pub mod R {}
2605 pub mod W {}
2606 pub mod RW {
2607 #[doc = "Select mux mode: ALT0 mux port: FLEXPWM2_PWMA03 of instance: flexpwm2"]
2608 pub const ALT0: u32 = 0;
2609 #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT14 of instance: xbar1"]
2610 pub const ALT1: u32 = 0x01;
2611 #[doc = "Select mux mode: ALT2 mux port: REF_CLK_32K of instance: xtalosc"]
2612 pub const ALT2: u32 = 0x02;
2613 #[doc = "Select mux mode: ALT3 mux port: USB_OTG2_ID of instance: usb"]
2614 pub const ALT3: u32 = 0x03;
2615 #[doc = "Select mux mode: ALT4 mux port: LPI2C1_SCLS of instance: lpi2c1"]
2616 pub const ALT4: u32 = 0x04;
2617 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO00 of instance: gpio1"]
2618 pub const ALT5: u32 = 0x05;
2619 #[doc = "Select mux mode: ALT6 mux port: USDHC1_RESET_B of instance: usdhc1"]
2620 pub const ALT6: u32 = 0x06;
2621 #[doc = "Select mux mode: ALT7 mux port: LPSPI3_SCK of instance: lpspi3"]
2622 pub const ALT7: u32 = 0x07;
2623 }
2624 }
2625 #[doc = "Software Input On Field."]
2626 pub mod SION {
2627 pub const offset: u32 = 4;
2628 pub const mask: u32 = 0x01 << offset;
2629 pub mod R {}
2630 pub mod W {}
2631 pub mod RW {
2632 #[doc = "Input Path is determined by functionality"]
2633 pub const DISABLED: u32 = 0;
2634 #[doc = "Force input path of pad GPIO_AD_B0_00"]
2635 pub const ENABLED: u32 = 0x01;
2636 }
2637 }
2638}
2639#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_01 SW MUX Control Register"]
2640pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_01 {
2641 #[doc = "MUX Mode Select Field."]
2642 pub mod MUX_MODE {
2643 pub const offset: u32 = 0;
2644 pub const mask: u32 = 0x07 << offset;
2645 pub mod R {}
2646 pub mod W {}
2647 pub mod RW {
2648 #[doc = "Select mux mode: ALT0 mux port: FLEXPWM2_PWMB03 of instance: flexpwm2"]
2649 pub const ALT0: u32 = 0;
2650 #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT15 of instance: xbar1"]
2651 pub const ALT1: u32 = 0x01;
2652 #[doc = "Select mux mode: ALT2 mux port: REF_CLK_24M of instance: anatop"]
2653 pub const ALT2: u32 = 0x02;
2654 #[doc = "Select mux mode: ALT3 mux port: USB_OTG1_ID of instance: anatop"]
2655 pub const ALT3: u32 = 0x03;
2656 #[doc = "Select mux mode: ALT4 mux port: LPI2C1_SDAS of instance: lpi2c1"]
2657 pub const ALT4: u32 = 0x04;
2658 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO01 of instance: gpio1"]
2659 pub const ALT5: u32 = 0x05;
2660 #[doc = "Select mux mode: ALT6 mux port: EWM_OUT_B of instance: ewm"]
2661 pub const ALT6: u32 = 0x06;
2662 #[doc = "Select mux mode: ALT7 mux port: LPSPI3_SDO of instance: lpspi3"]
2663 pub const ALT7: u32 = 0x07;
2664 }
2665 }
2666 #[doc = "Software Input On Field."]
2667 pub mod SION {
2668 pub const offset: u32 = 4;
2669 pub const mask: u32 = 0x01 << offset;
2670 pub mod R {}
2671 pub mod W {}
2672 pub mod RW {
2673 #[doc = "Input Path is determined by functionality"]
2674 pub const DISABLED: u32 = 0;
2675 #[doc = "Force input path of pad GPIO_AD_B0_01"]
2676 pub const ENABLED: u32 = 0x01;
2677 }
2678 }
2679}
2680#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_02 SW MUX Control Register"]
2681pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_02 {
2682 #[doc = "MUX Mode Select Field."]
2683 pub mod MUX_MODE {
2684 pub const offset: u32 = 0;
2685 pub const mask: u32 = 0x07 << offset;
2686 pub mod R {}
2687 pub mod W {}
2688 pub mod RW {
2689 #[doc = "Select mux mode: ALT0 mux port: FLEXCAN2_TX of instance: flexcan2"]
2690 pub const ALT0: u32 = 0;
2691 #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT16 of instance: xbar1"]
2692 pub const ALT1: u32 = 0x01;
2693 #[doc = "Select mux mode: ALT2 mux port: LPUART6_TX of instance: lpuart6"]
2694 pub const ALT2: u32 = 0x02;
2695 #[doc = "Select mux mode: ALT3 mux port: USB_OTG1_PWR of instance: usb"]
2696 pub const ALT3: u32 = 0x03;
2697 #[doc = "Select mux mode: ALT4 mux port: FLEXPWM1_PWMX00 of instance: flexpwm1"]
2698 pub const ALT4: u32 = 0x04;
2699 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO02 of instance: gpio1"]
2700 pub const ALT5: u32 = 0x05;
2701 #[doc = "Select mux mode: ALT6 mux port: LPI2C1_HREQ of instance: lpi2c1"]
2702 pub const ALT6: u32 = 0x06;
2703 #[doc = "Select mux mode: ALT7 mux port: LPSPI3_SDI of instance: lpspi3"]
2704 pub const ALT7: u32 = 0x07;
2705 }
2706 }
2707 #[doc = "Software Input On Field."]
2708 pub mod SION {
2709 pub const offset: u32 = 4;
2710 pub const mask: u32 = 0x01 << offset;
2711 pub mod R {}
2712 pub mod W {}
2713 pub mod RW {
2714 #[doc = "Input Path is determined by functionality"]
2715 pub const DISABLED: u32 = 0;
2716 #[doc = "Force input path of pad GPIO_AD_B0_02"]
2717 pub const ENABLED: u32 = 0x01;
2718 }
2719 }
2720}
2721#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_03 SW MUX Control Register"]
2722pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_03 {
2723 #[doc = "MUX Mode Select Field."]
2724 pub mod MUX_MODE {
2725 pub const offset: u32 = 0;
2726 pub const mask: u32 = 0x07 << offset;
2727 pub mod R {}
2728 pub mod W {}
2729 pub mod RW {
2730 #[doc = "Select mux mode: ALT0 mux port: FLEXCAN2_RX of instance: flexcan2"]
2731 pub const ALT0: u32 = 0;
2732 #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT17 of instance: xbar1"]
2733 pub const ALT1: u32 = 0x01;
2734 #[doc = "Select mux mode: ALT2 mux port: LPUART6_RX of instance: lpuart6"]
2735 pub const ALT2: u32 = 0x02;
2736 #[doc = "Select mux mode: ALT3 mux port: USB_OTG1_OC of instance: usb"]
2737 pub const ALT3: u32 = 0x03;
2738 #[doc = "Select mux mode: ALT4 mux port: FLEXPWM1_PWMX01 of instance: flexpwm1"]
2739 pub const ALT4: u32 = 0x04;
2740 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO03 of instance: gpio1"]
2741 pub const ALT5: u32 = 0x05;
2742 #[doc = "Select mux mode: ALT6 mux port: REF_CLK_24M of instance: anatop"]
2743 pub const ALT6: u32 = 0x06;
2744 #[doc = "Select mux mode: ALT7 mux port: LPSPI3_PCS0 of instance: lpspi3"]
2745 pub const ALT7: u32 = 0x07;
2746 }
2747 }
2748 #[doc = "Software Input On Field."]
2749 pub mod SION {
2750 pub const offset: u32 = 4;
2751 pub const mask: u32 = 0x01 << offset;
2752 pub mod R {}
2753 pub mod W {}
2754 pub mod RW {
2755 #[doc = "Input Path is determined by functionality"]
2756 pub const DISABLED: u32 = 0;
2757 #[doc = "Force input path of pad GPIO_AD_B0_03"]
2758 pub const ENABLED: u32 = 0x01;
2759 }
2760 }
2761}
2762#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_04 SW MUX Control Register"]
2763pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_04 {
2764 #[doc = "MUX Mode Select Field."]
2765 pub mod MUX_MODE {
2766 pub const offset: u32 = 0;
2767 pub const mask: u32 = 0x07 << offset;
2768 pub mod R {}
2769 pub mod W {}
2770 pub mod RW {
2771 #[doc = "Select mux mode: ALT0 mux port: SRC_BOOT_MODE00 of instance: src"]
2772 pub const ALT0: u32 = 0;
2773 #[doc = "Select mux mode: ALT1 mux port: MQS_RIGHT of instance: mqs"]
2774 pub const ALT1: u32 = 0x01;
2775 #[doc = "Select mux mode: ALT2 mux port: ENET_TX_DATA03 of instance: enet"]
2776 pub const ALT2: u32 = 0x02;
2777 #[doc = "Select mux mode: ALT3 mux port: SAI2_TX_SYNC of instance: sai2"]
2778 pub const ALT3: u32 = 0x03;
2779 #[doc = "Select mux mode: ALT4 mux port: CSI_DATA09 of instance: csi"]
2780 pub const ALT4: u32 = 0x04;
2781 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO04 of instance: gpio1"]
2782 pub const ALT5: u32 = 0x05;
2783 #[doc = "Select mux mode: ALT6 mux port: PIT_TRIGGER00 of instance: pit"]
2784 pub const ALT6: u32 = 0x06;
2785 #[doc = "Select mux mode: ALT7 mux port: LPSPI3_PCS1 of instance: lpspi3"]
2786 pub const ALT7: u32 = 0x07;
2787 }
2788 }
2789 #[doc = "Software Input On Field."]
2790 pub mod SION {
2791 pub const offset: u32 = 4;
2792 pub const mask: u32 = 0x01 << offset;
2793 pub mod R {}
2794 pub mod W {}
2795 pub mod RW {
2796 #[doc = "Input Path is determined by functionality"]
2797 pub const DISABLED: u32 = 0;
2798 #[doc = "Force input path of pad GPIO_AD_B0_04"]
2799 pub const ENABLED: u32 = 0x01;
2800 }
2801 }
2802}
2803#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_05 SW MUX Control Register"]
2804pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_05 {
2805 #[doc = "MUX Mode Select Field."]
2806 pub mod MUX_MODE {
2807 pub const offset: u32 = 0;
2808 pub const mask: u32 = 0x07 << offset;
2809 pub mod R {}
2810 pub mod W {}
2811 pub mod RW {
2812 #[doc = "Select mux mode: ALT0 mux port: SRC_BOOT_MODE01 of instance: src"]
2813 pub const ALT0: u32 = 0;
2814 #[doc = "Select mux mode: ALT1 mux port: MQS_LEFT of instance: mqs"]
2815 pub const ALT1: u32 = 0x01;
2816 #[doc = "Select mux mode: ALT2 mux port: ENET_TX_DATA02 of instance: enet"]
2817 pub const ALT2: u32 = 0x02;
2818 #[doc = "Select mux mode: ALT3 mux port: SAI2_TX_BCLK of instance: sai2"]
2819 pub const ALT3: u32 = 0x03;
2820 #[doc = "Select mux mode: ALT4 mux port: CSI_DATA08 of instance: csi"]
2821 pub const ALT4: u32 = 0x04;
2822 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO05 of instance: gpio1"]
2823 pub const ALT5: u32 = 0x05;
2824 #[doc = "Select mux mode: ALT6 mux port: XBAR1_INOUT17 of instance: xbar1"]
2825 pub const ALT6: u32 = 0x06;
2826 #[doc = "Select mux mode: ALT7 mux port: LPSPI3_PCS2 of instance: lpspi3"]
2827 pub const ALT7: u32 = 0x07;
2828 }
2829 }
2830 #[doc = "Software Input On Field."]
2831 pub mod SION {
2832 pub const offset: u32 = 4;
2833 pub const mask: u32 = 0x01 << offset;
2834 pub mod R {}
2835 pub mod W {}
2836 pub mod RW {
2837 #[doc = "Input Path is determined by functionality"]
2838 pub const DISABLED: u32 = 0;
2839 #[doc = "Force input path of pad GPIO_AD_B0_05"]
2840 pub const ENABLED: u32 = 0x01;
2841 }
2842 }
2843}
2844#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_06 SW MUX Control Register"]
2845pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_06 {
2846 #[doc = "MUX Mode Select Field."]
2847 pub mod MUX_MODE {
2848 pub const offset: u32 = 0;
2849 pub const mask: u32 = 0x07 << offset;
2850 pub mod R {}
2851 pub mod W {}
2852 pub mod RW {
2853 #[doc = "Select mux mode: ALT0 mux port: JTAG_TMS of instance: jtag_mux"]
2854 pub const ALT0: u32 = 0;
2855 #[doc = "Select mux mode: ALT1 mux port: GPT2_COMPARE1 of instance: gpt2"]
2856 pub const ALT1: u32 = 0x01;
2857 #[doc = "Select mux mode: ALT2 mux port: ENET_RX_CLK of instance: enet"]
2858 pub const ALT2: u32 = 0x02;
2859 #[doc = "Select mux mode: ALT3 mux port: SAI2_RX_BCLK of instance: sai2"]
2860 pub const ALT3: u32 = 0x03;
2861 #[doc = "Select mux mode: ALT4 mux port: CSI_DATA07 of instance: csi"]
2862 pub const ALT4: u32 = 0x04;
2863 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO06 of instance: gpio1"]
2864 pub const ALT5: u32 = 0x05;
2865 #[doc = "Select mux mode: ALT6 mux port: XBAR1_INOUT18 of instance: xbar1"]
2866 pub const ALT6: u32 = 0x06;
2867 #[doc = "Select mux mode: ALT7 mux port: LPSPI3_PCS3 of instance: lpspi3"]
2868 pub const ALT7: u32 = 0x07;
2869 }
2870 }
2871 #[doc = "Software Input On Field."]
2872 pub mod SION {
2873 pub const offset: u32 = 4;
2874 pub const mask: u32 = 0x01 << offset;
2875 pub mod R {}
2876 pub mod W {}
2877 pub mod RW {
2878 #[doc = "Input Path is determined by functionality"]
2879 pub const DISABLED: u32 = 0;
2880 #[doc = "Force input path of pad GPIO_AD_B0_06"]
2881 pub const ENABLED: u32 = 0x01;
2882 }
2883 }
2884}
2885#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_07 SW MUX Control Register"]
2886pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_07 {
2887 #[doc = "MUX Mode Select Field."]
2888 pub mod MUX_MODE {
2889 pub const offset: u32 = 0;
2890 pub const mask: u32 = 0x07 << offset;
2891 pub mod R {}
2892 pub mod W {}
2893 pub mod RW {
2894 #[doc = "Select mux mode: ALT0 mux port: JTAG_TCK of instance: jtag_mux"]
2895 pub const ALT0: u32 = 0;
2896 #[doc = "Select mux mode: ALT1 mux port: GPT2_COMPARE2 of instance: gpt2"]
2897 pub const ALT1: u32 = 0x01;
2898 #[doc = "Select mux mode: ALT2 mux port: ENET_TX_ER of instance: enet"]
2899 pub const ALT2: u32 = 0x02;
2900 #[doc = "Select mux mode: ALT3 mux port: SAI2_RX_SYNC of instance: sai2"]
2901 pub const ALT3: u32 = 0x03;
2902 #[doc = "Select mux mode: ALT4 mux port: CSI_DATA06 of instance: csi"]
2903 pub const ALT4: u32 = 0x04;
2904 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO07 of instance: gpio1"]
2905 pub const ALT5: u32 = 0x05;
2906 #[doc = "Select mux mode: ALT6 mux port: XBAR1_INOUT19 of instance: xbar1"]
2907 pub const ALT6: u32 = 0x06;
2908 #[doc = "Select mux mode: ALT7 mux port: ENET_1588_EVENT3_OUT of instance: enet"]
2909 pub const ALT7: u32 = 0x07;
2910 }
2911 }
2912 #[doc = "Software Input On Field."]
2913 pub mod SION {
2914 pub const offset: u32 = 4;
2915 pub const mask: u32 = 0x01 << offset;
2916 pub mod R {}
2917 pub mod W {}
2918 pub mod RW {
2919 #[doc = "Input Path is determined by functionality"]
2920 pub const DISABLED: u32 = 0;
2921 #[doc = "Force input path of pad GPIO_AD_B0_07"]
2922 pub const ENABLED: u32 = 0x01;
2923 }
2924 }
2925}
2926#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_08 SW MUX Control Register"]
2927pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_08 {
2928 #[doc = "MUX Mode Select Field."]
2929 pub mod MUX_MODE {
2930 pub const offset: u32 = 0;
2931 pub const mask: u32 = 0x07 << offset;
2932 pub mod R {}
2933 pub mod W {}
2934 pub mod RW {
2935 #[doc = "Select mux mode: ALT0 mux port: JTAG_MOD of instance: jtag_mux"]
2936 pub const ALT0: u32 = 0;
2937 #[doc = "Select mux mode: ALT1 mux port: GPT2_COMPARE3 of instance: gpt2"]
2938 pub const ALT1: u32 = 0x01;
2939 #[doc = "Select mux mode: ALT2 mux port: ENET_RX_DATA03 of instance: enet"]
2940 pub const ALT2: u32 = 0x02;
2941 #[doc = "Select mux mode: ALT3 mux port: SAI2_RX_DATA of instance: sai2"]
2942 pub const ALT3: u32 = 0x03;
2943 #[doc = "Select mux mode: ALT4 mux port: CSI_DATA05 of instance: csi"]
2944 pub const ALT4: u32 = 0x04;
2945 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO08 of instance: gpio1"]
2946 pub const ALT5: u32 = 0x05;
2947 #[doc = "Select mux mode: ALT6 mux port: XBAR1_IN20 of instance: xbar1"]
2948 pub const ALT6: u32 = 0x06;
2949 #[doc = "Select mux mode: ALT7 mux port: ENET_1588_EVENT3_IN of instance: enet"]
2950 pub const ALT7: u32 = 0x07;
2951 }
2952 }
2953 #[doc = "Software Input On Field."]
2954 pub mod SION {
2955 pub const offset: u32 = 4;
2956 pub const mask: u32 = 0x01 << offset;
2957 pub mod R {}
2958 pub mod W {}
2959 pub mod RW {
2960 #[doc = "Input Path is determined by functionality"]
2961 pub const DISABLED: u32 = 0;
2962 #[doc = "Force input path of pad GPIO_AD_B0_08"]
2963 pub const ENABLED: u32 = 0x01;
2964 }
2965 }
2966}
2967#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_09 SW MUX Control Register"]
2968pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_09 {
2969 #[doc = "MUX Mode Select Field."]
2970 pub mod MUX_MODE {
2971 pub const offset: u32 = 0;
2972 pub const mask: u32 = 0x0f << offset;
2973 pub mod R {}
2974 pub mod W {}
2975 pub mod RW {
2976 #[doc = "Select mux mode: ALT0 mux port: JTAG_TDI of instance: jtag_mux"]
2977 pub const ALT0: u32 = 0;
2978 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM2_PWMA03 of instance: flexpwm2"]
2979 pub const ALT1: u32 = 0x01;
2980 #[doc = "Select mux mode: ALT2 mux port: ENET_RX_DATA02 of instance: enet"]
2981 pub const ALT2: u32 = 0x02;
2982 #[doc = "Select mux mode: ALT3 mux port: SAI2_TX_DATA of instance: sai2"]
2983 pub const ALT3: u32 = 0x03;
2984 #[doc = "Select mux mode: ALT4 mux port: CSI_DATA04 of instance: csi"]
2985 pub const ALT4: u32 = 0x04;
2986 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO09 of instance: gpio1"]
2987 pub const ALT5: u32 = 0x05;
2988 #[doc = "Select mux mode: ALT6 mux port: XBAR1_IN21 of instance: xbar1"]
2989 pub const ALT6: u32 = 0x06;
2990 #[doc = "Select mux mode: ALT7 mux port: GPT2_CLK of instance: gpt2"]
2991 pub const ALT7: u32 = 0x07;
2992 #[doc = "Select mux mode: ALT9 mux port: SEMC_DQS4 of instance: semc"]
2993 pub const ALT9: u32 = 0x09;
2994 }
2995 }
2996 #[doc = "Software Input On Field."]
2997 pub mod SION {
2998 pub const offset: u32 = 4;
2999 pub const mask: u32 = 0x01 << offset;
3000 pub mod R {}
3001 pub mod W {}
3002 pub mod RW {
3003 #[doc = "Input Path is determined by functionality"]
3004 pub const DISABLED: u32 = 0;
3005 #[doc = "Force input path of pad GPIO_AD_B0_09"]
3006 pub const ENABLED: u32 = 0x01;
3007 }
3008 }
3009}
3010#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_10 SW MUX Control Register"]
3011pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_10 {
3012 #[doc = "MUX Mode Select Field."]
3013 pub mod MUX_MODE {
3014 pub const offset: u32 = 0;
3015 pub const mask: u32 = 0x0f << offset;
3016 pub mod R {}
3017 pub mod W {}
3018 pub mod RW {
3019 #[doc = "Select mux mode: ALT0 mux port: JTAG_TDO of instance: jtag_mux"]
3020 pub const ALT0: u32 = 0;
3021 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM1_PWMA03 of instance: flexpwm1"]
3022 pub const ALT1: u32 = 0x01;
3023 #[doc = "Select mux mode: ALT2 mux port: ENET_CRS of instance: enet"]
3024 pub const ALT2: u32 = 0x02;
3025 #[doc = "Select mux mode: ALT3 mux port: SAI2_MCLK of instance: sai2"]
3026 pub const ALT3: u32 = 0x03;
3027 #[doc = "Select mux mode: ALT4 mux port: CSI_DATA03 of instance: csi"]
3028 pub const ALT4: u32 = 0x04;
3029 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO10 of instance: gpio1"]
3030 pub const ALT5: u32 = 0x05;
3031 #[doc = "Select mux mode: ALT6 mux port: XBAR1_IN22 of instance: xbar1"]
3032 pub const ALT6: u32 = 0x06;
3033 #[doc = "Select mux mode: ALT7 mux port: ENET_1588_EVENT0_OUT of instance: enet"]
3034 pub const ALT7: u32 = 0x07;
3035 #[doc = "Select mux mode: ALT8 mux port: FLEXCAN3_TX of instance: flexcan3/canfd"]
3036 pub const ALT8: u32 = 0x08;
3037 #[doc = "Select mux mode: ALT9 mux port: ARM_TRACE_SWO of instance: cm7_mx6rt"]
3038 pub const ALT9: u32 = 0x09;
3039 }
3040 }
3041 #[doc = "Software Input On Field."]
3042 pub mod SION {
3043 pub const offset: u32 = 4;
3044 pub const mask: u32 = 0x01 << offset;
3045 pub mod R {}
3046 pub mod W {}
3047 pub mod RW {
3048 #[doc = "Input Path is determined by functionality"]
3049 pub const DISABLED: u32 = 0;
3050 #[doc = "Force input path of pad GPIO_AD_B0_10"]
3051 pub const ENABLED: u32 = 0x01;
3052 }
3053 }
3054}
3055#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_11 SW MUX Control Register"]
3056pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_11 {
3057 #[doc = "MUX Mode Select Field."]
3058 pub mod MUX_MODE {
3059 pub const offset: u32 = 0;
3060 pub const mask: u32 = 0x0f << offset;
3061 pub mod R {}
3062 pub mod W {}
3063 pub mod RW {
3064 #[doc = "Select mux mode: ALT0 mux port: JTAG_TRSTB of instance: jtag_mux"]
3065 pub const ALT0: u32 = 0;
3066 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM1_PWMB03 of instance: flexpwm1"]
3067 pub const ALT1: u32 = 0x01;
3068 #[doc = "Select mux mode: ALT2 mux port: ENET_COL of instance: enet"]
3069 pub const ALT2: u32 = 0x02;
3070 #[doc = "Select mux mode: ALT3 mux port: WDOG1_WDOG_B of instance: wdog1"]
3071 pub const ALT3: u32 = 0x03;
3072 #[doc = "Select mux mode: ALT4 mux port: CSI_DATA02 of instance: csi"]
3073 pub const ALT4: u32 = 0x04;
3074 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO11 of instance: gpio1"]
3075 pub const ALT5: u32 = 0x05;
3076 #[doc = "Select mux mode: ALT6 mux port: XBAR1_IN23 of instance: xbar1"]
3077 pub const ALT6: u32 = 0x06;
3078 #[doc = "Select mux mode: ALT7 mux port: ENET_1588_EVENT0_IN of instance: enet"]
3079 pub const ALT7: u32 = 0x07;
3080 #[doc = "Select mux mode: ALT8 mux port: FLEXCAN3_RX of instance: flexcan3/canfd"]
3081 pub const ALT8: u32 = 0x08;
3082 #[doc = "Select mux mode: ALT9 mux port: SEMC_CLK6 of instance: semc"]
3083 pub const ALT9: u32 = 0x09;
3084 }
3085 }
3086 #[doc = "Software Input On Field."]
3087 pub mod SION {
3088 pub const offset: u32 = 4;
3089 pub const mask: u32 = 0x01 << offset;
3090 pub mod R {}
3091 pub mod W {}
3092 pub mod RW {
3093 #[doc = "Input Path is determined by functionality"]
3094 pub const DISABLED: u32 = 0;
3095 #[doc = "Force input path of pad GPIO_AD_B0_11"]
3096 pub const ENABLED: u32 = 0x01;
3097 }
3098 }
3099}
3100#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_12 SW MUX Control Register"]
3101pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_12 {
3102 #[doc = "MUX Mode Select Field."]
3103 pub mod MUX_MODE {
3104 pub const offset: u32 = 0;
3105 pub const mask: u32 = 0x07 << offset;
3106 pub mod R {}
3107 pub mod W {}
3108 pub mod RW {
3109 #[doc = "Select mux mode: ALT0 mux port: LPI2C4_SCL of instance: lpi2c4"]
3110 pub const ALT0: u32 = 0;
3111 #[doc = "Select mux mode: ALT1 mux port: CCM_PMIC_READY of instance: ccm"]
3112 pub const ALT1: u32 = 0x01;
3113 #[doc = "Select mux mode: ALT2 mux port: LPUART1_TX of instance: lpuart1"]
3114 pub const ALT2: u32 = 0x02;
3115 #[doc = "Select mux mode: ALT3 mux port: WDOG2_WDOG_B of instance: wdog2"]
3116 pub const ALT3: u32 = 0x03;
3117 #[doc = "Select mux mode: ALT4 mux port: FLEXPWM1_PWMX02 of instance: flexpwm1"]
3118 pub const ALT4: u32 = 0x04;
3119 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO12 of instance: gpio1"]
3120 pub const ALT5: u32 = 0x05;
3121 #[doc = "Select mux mode: ALT6 mux port: ENET_1588_EVENT1_OUT of instance: enet"]
3122 pub const ALT6: u32 = 0x06;
3123 #[doc = "Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue"]
3124 pub const ALT7: u32 = 0x07;
3125 }
3126 }
3127 #[doc = "Software Input On Field."]
3128 pub mod SION {
3129 pub const offset: u32 = 4;
3130 pub const mask: u32 = 0x01 << offset;
3131 pub mod R {}
3132 pub mod W {}
3133 pub mod RW {
3134 #[doc = "Input Path is determined by functionality"]
3135 pub const DISABLED: u32 = 0;
3136 #[doc = "Force input path of pad GPIO_AD_B0_12"]
3137 pub const ENABLED: u32 = 0x01;
3138 }
3139 }
3140}
3141#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_13 SW MUX Control Register"]
3142pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_13 {
3143 #[doc = "MUX Mode Select Field."]
3144 pub mod MUX_MODE {
3145 pub const offset: u32 = 0;
3146 pub const mask: u32 = 0x07 << offset;
3147 pub mod R {}
3148 pub mod W {}
3149 pub mod RW {
3150 #[doc = "Select mux mode: ALT0 mux port: LPI2C4_SDA of instance: lpi2c4"]
3151 pub const ALT0: u32 = 0;
3152 #[doc = "Select mux mode: ALT1 mux port: GPT1_CLK of instance: gpt1"]
3153 pub const ALT1: u32 = 0x01;
3154 #[doc = "Select mux mode: ALT2 mux port: LPUART1_RX of instance: lpuart1"]
3155 pub const ALT2: u32 = 0x02;
3156 #[doc = "Select mux mode: ALT3 mux port: EWM_OUT_B of instance: ewm"]
3157 pub const ALT3: u32 = 0x03;
3158 #[doc = "Select mux mode: ALT4 mux port: FLEXPWM1_PWMX03 of instance: flexpwm1"]
3159 pub const ALT4: u32 = 0x04;
3160 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO13 of instance: gpio1"]
3161 pub const ALT5: u32 = 0x05;
3162 #[doc = "Select mux mode: ALT6 mux port: ENET_1588_EVENT1_IN of instance: enet"]
3163 pub const ALT6: u32 = 0x06;
3164 #[doc = "Select mux mode: ALT7 mux port: REF_CLK_24M of instance: anatop"]
3165 pub const ALT7: u32 = 0x07;
3166 }
3167 }
3168 #[doc = "Software Input On Field."]
3169 pub mod SION {
3170 pub const offset: u32 = 4;
3171 pub const mask: u32 = 0x01 << offset;
3172 pub mod R {}
3173 pub mod W {}
3174 pub mod RW {
3175 #[doc = "Input Path is determined by functionality"]
3176 pub const DISABLED: u32 = 0;
3177 #[doc = "Force input path of pad GPIO_AD_B0_13"]
3178 pub const ENABLED: u32 = 0x01;
3179 }
3180 }
3181}
3182#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_14 SW MUX Control Register"]
3183pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_14 {
3184 #[doc = "MUX Mode Select Field."]
3185 pub mod MUX_MODE {
3186 pub const offset: u32 = 0;
3187 pub const mask: u32 = 0x0f << offset;
3188 pub mod R {}
3189 pub mod W {}
3190 pub mod RW {
3191 #[doc = "Select mux mode: ALT0 mux port: USB_OTG2_OC of instance: usb"]
3192 pub const ALT0: u32 = 0;
3193 #[doc = "Select mux mode: ALT1 mux port: XBAR1_IN24 of instance: xbar1"]
3194 pub const ALT1: u32 = 0x01;
3195 #[doc = "Select mux mode: ALT2 mux port: LPUART1_CTS_B of instance: lpuart1"]
3196 pub const ALT2: u32 = 0x02;
3197 #[doc = "Select mux mode: ALT3 mux port: ENET_1588_EVENT0_OUT of instance: enet"]
3198 pub const ALT3: u32 = 0x03;
3199 #[doc = "Select mux mode: ALT4 mux port: CSI_VSYNC of instance: csi"]
3200 pub const ALT4: u32 = 0x04;
3201 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO14 of instance: gpio1"]
3202 pub const ALT5: u32 = 0x05;
3203 #[doc = "Select mux mode: ALT6 mux port: FLEXCAN2_TX of instance: flexcan2"]
3204 pub const ALT6: u32 = 0x06;
3205 #[doc = "Select mux mode: ALT8 mux port: FLEXCAN3_TX of instance: flexcan3/canfd"]
3206 pub const ALT8: u32 = 0x08;
3207 }
3208 }
3209 #[doc = "Software Input On Field."]
3210 pub mod SION {
3211 pub const offset: u32 = 4;
3212 pub const mask: u32 = 0x01 << offset;
3213 pub mod R {}
3214 pub mod W {}
3215 pub mod RW {
3216 #[doc = "Input Path is determined by functionality"]
3217 pub const DISABLED: u32 = 0;
3218 #[doc = "Force input path of pad GPIO_AD_B0_14"]
3219 pub const ENABLED: u32 = 0x01;
3220 }
3221 }
3222}
3223#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B0_15 SW MUX Control Register"]
3224pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_15 {
3225 #[doc = "MUX Mode Select Field."]
3226 pub mod MUX_MODE {
3227 pub const offset: u32 = 0;
3228 pub const mask: u32 = 0x0f << offset;
3229 pub mod R {}
3230 pub mod W {}
3231 pub mod RW {
3232 #[doc = "Select mux mode: ALT0 mux port: USB_OTG2_PWR of instance: usb"]
3233 pub const ALT0: u32 = 0;
3234 #[doc = "Select mux mode: ALT1 mux port: XBAR1_IN25 of instance: xbar1"]
3235 pub const ALT1: u32 = 0x01;
3236 #[doc = "Select mux mode: ALT2 mux port: LPUART1_RTS_B of instance: lpuart1"]
3237 pub const ALT2: u32 = 0x02;
3238 #[doc = "Select mux mode: ALT3 mux port: ENET_1588_EVENT0_IN of instance: enet"]
3239 pub const ALT3: u32 = 0x03;
3240 #[doc = "Select mux mode: ALT4 mux port: CSI_HSYNC of instance: csi"]
3241 pub const ALT4: u32 = 0x04;
3242 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO15 of instance: gpio1"]
3243 pub const ALT5: u32 = 0x05;
3244 #[doc = "Select mux mode: ALT6 mux port: FLEXCAN2_RX of instance: flexcan2"]
3245 pub const ALT6: u32 = 0x06;
3246 #[doc = "Select mux mode: ALT7 mux port: WDOG1_WDOG_RST_B_DEB of instance: wdog1"]
3247 pub const ALT7: u32 = 0x07;
3248 #[doc = "Select mux mode: ALT8 mux port: FLEXCAN3_RX of instance: flexcan3/canfd"]
3249 pub const ALT8: u32 = 0x08;
3250 }
3251 }
3252 #[doc = "Software Input On Field."]
3253 pub mod SION {
3254 pub const offset: u32 = 4;
3255 pub const mask: u32 = 0x01 << offset;
3256 pub mod R {}
3257 pub mod W {}
3258 pub mod RW {
3259 #[doc = "Input Path is determined by functionality"]
3260 pub const DISABLED: u32 = 0;
3261 #[doc = "Force input path of pad GPIO_AD_B0_15"]
3262 pub const ENABLED: u32 = 0x01;
3263 }
3264 }
3265}
3266#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_00 SW MUX Control Register"]
3267pub mod SW_MUX_CTL_PAD_GPIO_AD_B1_00 {
3268 #[doc = "MUX Mode Select Field."]
3269 pub mod MUX_MODE {
3270 pub const offset: u32 = 0;
3271 pub const mask: u32 = 0x0f << offset;
3272 pub mod R {}
3273 pub mod W {}
3274 pub mod RW {
3275 #[doc = "Select mux mode: ALT0 mux port: USB_OTG2_ID of instance: anatop"]
3276 pub const ALT0: u32 = 0;
3277 #[doc = "Select mux mode: ALT1 mux port: QTIMER3_TIMER0 of instance: qtimer3"]
3278 pub const ALT1: u32 = 0x01;
3279 #[doc = "Select mux mode: ALT2 mux port: LPUART2_CTS_B of instance: lpuart2"]
3280 pub const ALT2: u32 = 0x02;
3281 #[doc = "Select mux mode: ALT3 mux port: LPI2C1_SCL of instance: lpi2c1"]
3282 pub const ALT3: u32 = 0x03;
3283 #[doc = "Select mux mode: ALT4 mux port: WDOG1_B of instance: wdog1"]
3284 pub const ALT4: u32 = 0x04;
3285 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO16 of instance: gpio1"]
3286 pub const ALT5: u32 = 0x05;
3287 #[doc = "Select mux mode: ALT6 mux port: USDHC1_WP of instance: usdhc1"]
3288 pub const ALT6: u32 = 0x06;
3289 #[doc = "Select mux mode: ALT7 mux port: KPP_ROW07 of instance: kpp"]
3290 pub const ALT7: u32 = 0x07;
3291 #[doc = "Select mux mode: ALT8 mux port: ENET2_1588_EVENT0_OUT of instance: enet2"]
3292 pub const ALT8: u32 = 0x08;
3293 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO00 of instance: flexio3"]
3294 pub const ALT9: u32 = 0x09;
3295 }
3296 }
3297 #[doc = "Software Input On Field."]
3298 pub mod SION {
3299 pub const offset: u32 = 4;
3300 pub const mask: u32 = 0x01 << offset;
3301 pub mod R {}
3302 pub mod W {}
3303 pub mod RW {
3304 #[doc = "Input Path is determined by functionality"]
3305 pub const DISABLED: u32 = 0;
3306 #[doc = "Force input path of pad GPIO_AD_B1_00"]
3307 pub const ENABLED: u32 = 0x01;
3308 }
3309 }
3310}
3311#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_01 SW MUX Control Register"]
3312pub mod SW_MUX_CTL_PAD_GPIO_AD_B1_01 {
3313 #[doc = "MUX Mode Select Field."]
3314 pub mod MUX_MODE {
3315 pub const offset: u32 = 0;
3316 pub const mask: u32 = 0x0f << offset;
3317 pub mod R {}
3318 pub mod W {}
3319 pub mod RW {
3320 #[doc = "Select mux mode: ALT0 mux port: USB_OTG1_PWR of instance: usb"]
3321 pub const ALT0: u32 = 0;
3322 #[doc = "Select mux mode: ALT1 mux port: QTIMER3_TIMER1 of instance: qtimer3"]
3323 pub const ALT1: u32 = 0x01;
3324 #[doc = "Select mux mode: ALT2 mux port: LPUART2_RTS_B of instance: lpuart2"]
3325 pub const ALT2: u32 = 0x02;
3326 #[doc = "Select mux mode: ALT3 mux port: LPI2C1_SDA of instance: lpi2c1"]
3327 pub const ALT3: u32 = 0x03;
3328 #[doc = "Select mux mode: ALT4 mux port: CCM_PMIC_READY of instance: ccm"]
3329 pub const ALT4: u32 = 0x04;
3330 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO17 of instance: gpio1"]
3331 pub const ALT5: u32 = 0x05;
3332 #[doc = "Select mux mode: ALT6 mux port: USDHC1_VSELECT of instance: usdhc1"]
3333 pub const ALT6: u32 = 0x06;
3334 #[doc = "Select mux mode: ALT7 mux port: KPP_COL07 of instance: kpp"]
3335 pub const ALT7: u32 = 0x07;
3336 #[doc = "Select mux mode: ALT8 mux port: ENET2_1588_EVENT0_IN of instance: enet2"]
3337 pub const ALT8: u32 = 0x08;
3338 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO01 of instance: flexio3"]
3339 pub const ALT9: u32 = 0x09;
3340 }
3341 }
3342 #[doc = "Software Input On Field."]
3343 pub mod SION {
3344 pub const offset: u32 = 4;
3345 pub const mask: u32 = 0x01 << offset;
3346 pub mod R {}
3347 pub mod W {}
3348 pub mod RW {
3349 #[doc = "Input Path is determined by functionality"]
3350 pub const DISABLED: u32 = 0;
3351 #[doc = "Force input path of pad GPIO_AD_B1_01"]
3352 pub const ENABLED: u32 = 0x01;
3353 }
3354 }
3355}
3356#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_02 SW MUX Control Register"]
3357pub mod SW_MUX_CTL_PAD_GPIO_AD_B1_02 {
3358 #[doc = "MUX Mode Select Field."]
3359 pub mod MUX_MODE {
3360 pub const offset: u32 = 0;
3361 pub const mask: u32 = 0x0f << offset;
3362 pub mod R {}
3363 pub mod W {}
3364 pub mod RW {
3365 #[doc = "Select mux mode: ALT0 mux port: USB_OTG1_ID of instance: anatop"]
3366 pub const ALT0: u32 = 0;
3367 #[doc = "Select mux mode: ALT1 mux port: QTIMER3_TIMER2 of instance: qtimer3"]
3368 pub const ALT1: u32 = 0x01;
3369 #[doc = "Select mux mode: ALT2 mux port: LPUART2_TX of instance: lpuart2"]
3370 pub const ALT2: u32 = 0x02;
3371 #[doc = "Select mux mode: ALT3 mux port: SPDIF_OUT of instance: spdif"]
3372 pub const ALT3: u32 = 0x03;
3373 #[doc = "Select mux mode: ALT4 mux port: ENET_1588_EVENT2_OUT of instance: enet"]
3374 pub const ALT4: u32 = 0x04;
3375 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO18 of instance: gpio1"]
3376 pub const ALT5: u32 = 0x05;
3377 #[doc = "Select mux mode: ALT6 mux port: USDHC1_CD_B of instance: usdhc1"]
3378 pub const ALT6: u32 = 0x06;
3379 #[doc = "Select mux mode: ALT7 mux port: KPP_ROW06 of instance: kpp"]
3380 pub const ALT7: u32 = 0x07;
3381 #[doc = "Select mux mode: ALT8 mux port: GPT2_CLK of instance: gpt2"]
3382 pub const ALT8: u32 = 0x08;
3383 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO02 of instance: flexio3"]
3384 pub const ALT9: u32 = 0x09;
3385 }
3386 }
3387 #[doc = "Software Input On Field."]
3388 pub mod SION {
3389 pub const offset: u32 = 4;
3390 pub const mask: u32 = 0x01 << offset;
3391 pub mod R {}
3392 pub mod W {}
3393 pub mod RW {
3394 #[doc = "Input Path is determined by functionality"]
3395 pub const DISABLED: u32 = 0;
3396 #[doc = "Force input path of pad GPIO_AD_B1_02"]
3397 pub const ENABLED: u32 = 0x01;
3398 }
3399 }
3400}
3401#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_03 SW MUX Control Register"]
3402pub mod SW_MUX_CTL_PAD_GPIO_AD_B1_03 {
3403 #[doc = "MUX Mode Select Field."]
3404 pub mod MUX_MODE {
3405 pub const offset: u32 = 0;
3406 pub const mask: u32 = 0x0f << offset;
3407 pub mod R {}
3408 pub mod W {}
3409 pub mod RW {
3410 #[doc = "Select mux mode: ALT0 mux port: USB_OTG1_OC of instance: usb"]
3411 pub const ALT0: u32 = 0;
3412 #[doc = "Select mux mode: ALT1 mux port: QTIMER3_TIMER3 of instance: qtimer3"]
3413 pub const ALT1: u32 = 0x01;
3414 #[doc = "Select mux mode: ALT2 mux port: LPUART2_RX of instance: lpuart2"]
3415 pub const ALT2: u32 = 0x02;
3416 #[doc = "Select mux mode: ALT3 mux port: SPDIF_IN of instance: spdif"]
3417 pub const ALT3: u32 = 0x03;
3418 #[doc = "Select mux mode: ALT4 mux port: ENET_1588_EVENT2_IN of instance: enet"]
3419 pub const ALT4: u32 = 0x04;
3420 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO19 of instance: gpio1"]
3421 pub const ALT5: u32 = 0x05;
3422 #[doc = "Select mux mode: ALT6 mux port: USDHC2_CD_B of instance: usdhc2"]
3423 pub const ALT6: u32 = 0x06;
3424 #[doc = "Select mux mode: ALT7 mux port: KPP_COL06 of instance: kpp"]
3425 pub const ALT7: u32 = 0x07;
3426 #[doc = "Select mux mode: ALT8 mux port: GPT2_CAPTURE1 of instance: gpt2"]
3427 pub const ALT8: u32 = 0x08;
3428 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO03 of instance: flexio3"]
3429 pub const ALT9: u32 = 0x09;
3430 }
3431 }
3432 #[doc = "Software Input On Field."]
3433 pub mod SION {
3434 pub const offset: u32 = 4;
3435 pub const mask: u32 = 0x01 << offset;
3436 pub mod R {}
3437 pub mod W {}
3438 pub mod RW {
3439 #[doc = "Input Path is determined by functionality"]
3440 pub const DISABLED: u32 = 0;
3441 #[doc = "Force input path of pad GPIO_AD_B1_03"]
3442 pub const ENABLED: u32 = 0x01;
3443 }
3444 }
3445}
3446#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_04 SW MUX Control Register"]
3447pub mod SW_MUX_CTL_PAD_GPIO_AD_B1_04 {
3448 #[doc = "MUX Mode Select Field."]
3449 pub mod MUX_MODE {
3450 pub const offset: u32 = 0;
3451 pub const mask: u32 = 0x0f << offset;
3452 pub mod R {}
3453 pub mod W {}
3454 pub mod RW {
3455 #[doc = "Select mux mode: ALT0 mux port: FLEXSPIB_DATA03 of instance: flexspi"]
3456 pub const ALT0: u32 = 0;
3457 #[doc = "Select mux mode: ALT1 mux port: ENET_MDC of instance: enet"]
3458 pub const ALT1: u32 = 0x01;
3459 #[doc = "Select mux mode: ALT2 mux port: LPUART3_CTS_B of instance: lpuart3"]
3460 pub const ALT2: u32 = 0x02;
3461 #[doc = "Select mux mode: ALT3 mux port: SPDIF_SR_CLK of instance: spdif"]
3462 pub const ALT3: u32 = 0x03;
3463 #[doc = "Select mux mode: ALT4 mux port: CSI_PIXCLK of instance: csi"]
3464 pub const ALT4: u32 = 0x04;
3465 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO20 of instance: gpio1"]
3466 pub const ALT5: u32 = 0x05;
3467 #[doc = "Select mux mode: ALT6 mux port: USDHC2_DATA0 of instance: usdhc2"]
3468 pub const ALT6: u32 = 0x06;
3469 #[doc = "Select mux mode: ALT7 mux port: KPP_ROW05 of instance: kpp"]
3470 pub const ALT7: u32 = 0x07;
3471 #[doc = "Select mux mode: ALT8 mux port: GPT2_CAPTURE2 of instance: gpt2"]
3472 pub const ALT8: u32 = 0x08;
3473 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO04 of instance: flexio3"]
3474 pub const ALT9: u32 = 0x09;
3475 }
3476 }
3477 #[doc = "Software Input On Field."]
3478 pub mod SION {
3479 pub const offset: u32 = 4;
3480 pub const mask: u32 = 0x01 << offset;
3481 pub mod R {}
3482 pub mod W {}
3483 pub mod RW {
3484 #[doc = "Input Path is determined by functionality"]
3485 pub const DISABLED: u32 = 0;
3486 #[doc = "Force input path of pad GPIO_AD_B1_04"]
3487 pub const ENABLED: u32 = 0x01;
3488 }
3489 }
3490}
3491#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_05 SW MUX Control Register"]
3492pub mod SW_MUX_CTL_PAD_GPIO_AD_B1_05 {
3493 #[doc = "MUX Mode Select Field."]
3494 pub mod MUX_MODE {
3495 pub const offset: u32 = 0;
3496 pub const mask: u32 = 0x0f << offset;
3497 pub mod R {}
3498 pub mod W {}
3499 pub mod RW {
3500 #[doc = "Select mux mode: ALT0 mux port: FLEXSPIB_DATA02 of instance: flexspi"]
3501 pub const ALT0: u32 = 0;
3502 #[doc = "Select mux mode: ALT1 mux port: ENET_MDIO of instance: enet"]
3503 pub const ALT1: u32 = 0x01;
3504 #[doc = "Select mux mode: ALT2 mux port: LPUART3_RTS_B of instance: lpuart3"]
3505 pub const ALT2: u32 = 0x02;
3506 #[doc = "Select mux mode: ALT3 mux port: SPDIF_OUT of instance: spdif"]
3507 pub const ALT3: u32 = 0x03;
3508 #[doc = "Select mux mode: ALT4 mux port: CSI_MCLK of instance: csi"]
3509 pub const ALT4: u32 = 0x04;
3510 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO21 of instance: gpio1"]
3511 pub const ALT5: u32 = 0x05;
3512 #[doc = "Select mux mode: ALT6 mux port: USDHC2_DATA1 of instance: usdhc2"]
3513 pub const ALT6: u32 = 0x06;
3514 #[doc = "Select mux mode: ALT7 mux port: KPP_COL05 of instance: kpp"]
3515 pub const ALT7: u32 = 0x07;
3516 #[doc = "Select mux mode: ALT8 mux port: GPT2_COMPARE1 of instance: gpt2"]
3517 pub const ALT8: u32 = 0x08;
3518 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO05 of instance: flexio3"]
3519 pub const ALT9: u32 = 0x09;
3520 }
3521 }
3522 #[doc = "Software Input On Field."]
3523 pub mod SION {
3524 pub const offset: u32 = 4;
3525 pub const mask: u32 = 0x01 << offset;
3526 pub mod R {}
3527 pub mod W {}
3528 pub mod RW {
3529 #[doc = "Input Path is determined by functionality"]
3530 pub const DISABLED: u32 = 0;
3531 #[doc = "Force input path of pad GPIO_AD_B1_05"]
3532 pub const ENABLED: u32 = 0x01;
3533 }
3534 }
3535}
3536#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_06 SW MUX Control Register"]
3537pub mod SW_MUX_CTL_PAD_GPIO_AD_B1_06 {
3538 #[doc = "MUX Mode Select Field."]
3539 pub mod MUX_MODE {
3540 pub const offset: u32 = 0;
3541 pub const mask: u32 = 0x0f << offset;
3542 pub mod R {}
3543 pub mod W {}
3544 pub mod RW {
3545 #[doc = "Select mux mode: ALT0 mux port: FLEXSPIB_DATA01 of instance: flexspi"]
3546 pub const ALT0: u32 = 0;
3547 #[doc = "Select mux mode: ALT1 mux port: LPI2C3_SDA of instance: lpi2c3"]
3548 pub const ALT1: u32 = 0x01;
3549 #[doc = "Select mux mode: ALT2 mux port: LPUART3_TX of instance: lpuart3"]
3550 pub const ALT2: u32 = 0x02;
3551 #[doc = "Select mux mode: ALT3 mux port: SPDIF_LOCK of instance: spdif"]
3552 pub const ALT3: u32 = 0x03;
3553 #[doc = "Select mux mode: ALT4 mux port: CSI_VSYNC of instance: csi"]
3554 pub const ALT4: u32 = 0x04;
3555 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO22 of instance: gpio1"]
3556 pub const ALT5: u32 = 0x05;
3557 #[doc = "Select mux mode: ALT6 mux port: USDHC2_DATA2 of instance: usdhc2"]
3558 pub const ALT6: u32 = 0x06;
3559 #[doc = "Select mux mode: ALT7 mux port: KPP_ROW04 of instance: kpp"]
3560 pub const ALT7: u32 = 0x07;
3561 #[doc = "Select mux mode: ALT8 mux port: GPT2_COMPARE2 of instance: gpt2"]
3562 pub const ALT8: u32 = 0x08;
3563 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO06 of instance: flexio3"]
3564 pub const ALT9: u32 = 0x09;
3565 }
3566 }
3567 #[doc = "Software Input On Field."]
3568 pub mod SION {
3569 pub const offset: u32 = 4;
3570 pub const mask: u32 = 0x01 << offset;
3571 pub mod R {}
3572 pub mod W {}
3573 pub mod RW {
3574 #[doc = "Input Path is determined by functionality"]
3575 pub const DISABLED: u32 = 0;
3576 #[doc = "Force input path of pad GPIO_AD_B1_06"]
3577 pub const ENABLED: u32 = 0x01;
3578 }
3579 }
3580}
3581#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_07 SW MUX Control Register"]
3582pub mod SW_MUX_CTL_PAD_GPIO_AD_B1_07 {
3583 #[doc = "MUX Mode Select Field."]
3584 pub mod MUX_MODE {
3585 pub const offset: u32 = 0;
3586 pub const mask: u32 = 0x0f << offset;
3587 pub mod R {}
3588 pub mod W {}
3589 pub mod RW {
3590 #[doc = "Select mux mode: ALT0 mux port: FLEXSPIB_DATA00 of instance: flexspi"]
3591 pub const ALT0: u32 = 0;
3592 #[doc = "Select mux mode: ALT1 mux port: LPI2C3_SCL of instance: lpi2c3"]
3593 pub const ALT1: u32 = 0x01;
3594 #[doc = "Select mux mode: ALT2 mux port: LPUART3_RX of instance: lpuart3"]
3595 pub const ALT2: u32 = 0x02;
3596 #[doc = "Select mux mode: ALT3 mux port: SPDIF_EXT_CLK of instance: spdif"]
3597 pub const ALT3: u32 = 0x03;
3598 #[doc = "Select mux mode: ALT4 mux port: CSI_HSYNC of instance: csi"]
3599 pub const ALT4: u32 = 0x04;
3600 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO23 of instance: gpio1"]
3601 pub const ALT5: u32 = 0x05;
3602 #[doc = "Select mux mode: ALT6 mux port: USDHC2_DATA3 of instance: usdhc2"]
3603 pub const ALT6: u32 = 0x06;
3604 #[doc = "Select mux mode: ALT7 mux port: KPP_COL04 of instance: kpp"]
3605 pub const ALT7: u32 = 0x07;
3606 #[doc = "Select mux mode: ALT8 mux port: GPT2_COMPARE3 of instance: gpt2"]
3607 pub const ALT8: u32 = 0x08;
3608 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO07 of instance: flexio3"]
3609 pub const ALT9: u32 = 0x09;
3610 }
3611 }
3612 #[doc = "Software Input On Field."]
3613 pub mod SION {
3614 pub const offset: u32 = 4;
3615 pub const mask: u32 = 0x01 << offset;
3616 pub mod R {}
3617 pub mod W {}
3618 pub mod RW {
3619 #[doc = "Input Path is determined by functionality"]
3620 pub const DISABLED: u32 = 0;
3621 #[doc = "Force input path of pad GPIO_AD_B1_07"]
3622 pub const ENABLED: u32 = 0x01;
3623 }
3624 }
3625}
3626#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_08 SW MUX Control Register"]
3627pub mod SW_MUX_CTL_PAD_GPIO_AD_B1_08 {
3628 #[doc = "MUX Mode Select Field."]
3629 pub mod MUX_MODE {
3630 pub const offset: u32 = 0;
3631 pub const mask: u32 = 0x0f << offset;
3632 pub mod R {}
3633 pub mod W {}
3634 pub mod RW {
3635 #[doc = "Select mux mode: ALT0 mux port: FLEXSPIA_SS1_B of instance: flexspi"]
3636 pub const ALT0: u32 = 0;
3637 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM4_PWMA00 of instance: flexpwm4"]
3638 pub const ALT1: u32 = 0x01;
3639 #[doc = "Select mux mode: ALT2 mux port: FLEXCAN1_TX of instance: flexcan1"]
3640 pub const ALT2: u32 = 0x02;
3641 #[doc = "Select mux mode: ALT3 mux port: CCM_PMIC_READY of instance: ccm"]
3642 pub const ALT3: u32 = 0x03;
3643 #[doc = "Select mux mode: ALT4 mux port: CSI_DATA09 of instance: csi"]
3644 pub const ALT4: u32 = 0x04;
3645 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO24 of instance: gpio1"]
3646 pub const ALT5: u32 = 0x05;
3647 #[doc = "Select mux mode: ALT6 mux port: USDHC2_CMD of instance: usdhc2"]
3648 pub const ALT6: u32 = 0x06;
3649 #[doc = "Select mux mode: ALT7 mux port: KPP_ROW03 of instance: kpp"]
3650 pub const ALT7: u32 = 0x07;
3651 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO08 of instance: flexio3"]
3652 pub const ALT9: u32 = 0x09;
3653 }
3654 }
3655 #[doc = "Software Input On Field."]
3656 pub mod SION {
3657 pub const offset: u32 = 4;
3658 pub const mask: u32 = 0x01 << offset;
3659 pub mod R {}
3660 pub mod W {}
3661 pub mod RW {
3662 #[doc = "Input Path is determined by functionality"]
3663 pub const DISABLED: u32 = 0;
3664 #[doc = "Force input path of pad GPIO_AD_B1_08"]
3665 pub const ENABLED: u32 = 0x01;
3666 }
3667 }
3668}
3669#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_09 SW MUX Control Register"]
3670pub mod SW_MUX_CTL_PAD_GPIO_AD_B1_09 {
3671 #[doc = "MUX Mode Select Field."]
3672 pub mod MUX_MODE {
3673 pub const offset: u32 = 0;
3674 pub const mask: u32 = 0x0f << offset;
3675 pub mod R {}
3676 pub mod W {}
3677 pub mod RW {
3678 #[doc = "Select mux mode: ALT0 mux port: FLEXSPIA_DQS of instance: flexspi"]
3679 pub const ALT0: u32 = 0;
3680 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM4_PWMA01 of instance: flexpwm4"]
3681 pub const ALT1: u32 = 0x01;
3682 #[doc = "Select mux mode: ALT2 mux port: FLEXCAN1_RX of instance: flexcan1"]
3683 pub const ALT2: u32 = 0x02;
3684 #[doc = "Select mux mode: ALT3 mux port: SAI1_MCLK of instance: sai1"]
3685 pub const ALT3: u32 = 0x03;
3686 #[doc = "Select mux mode: ALT4 mux port: CSI_DATA08 of instance: csi"]
3687 pub const ALT4: u32 = 0x04;
3688 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO25 of instance: gpio1"]
3689 pub const ALT5: u32 = 0x05;
3690 #[doc = "Select mux mode: ALT6 mux port: USDHC2_CLK of instance: usdhc2"]
3691 pub const ALT6: u32 = 0x06;
3692 #[doc = "Select mux mode: ALT7 mux port: KPP_COL03 of instance: kpp"]
3693 pub const ALT7: u32 = 0x07;
3694 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO09 of instance: flexio3"]
3695 pub const ALT9: u32 = 0x09;
3696 }
3697 }
3698 #[doc = "Software Input On Field."]
3699 pub mod SION {
3700 pub const offset: u32 = 4;
3701 pub const mask: u32 = 0x01 << offset;
3702 pub mod R {}
3703 pub mod W {}
3704 pub mod RW {
3705 #[doc = "Input Path is determined by functionality"]
3706 pub const DISABLED: u32 = 0;
3707 #[doc = "Force input path of pad GPIO_AD_B1_09"]
3708 pub const ENABLED: u32 = 0x01;
3709 }
3710 }
3711}
3712#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_10 SW MUX Control Register"]
3713pub mod SW_MUX_CTL_PAD_GPIO_AD_B1_10 {
3714 #[doc = "MUX Mode Select Field."]
3715 pub mod MUX_MODE {
3716 pub const offset: u32 = 0;
3717 pub const mask: u32 = 0x0f << offset;
3718 pub mod R {}
3719 pub mod W {}
3720 pub mod RW {
3721 #[doc = "Select mux mode: ALT0 mux port: FLEXSPIA_DATA03 of instance: flexspi"]
3722 pub const ALT0: u32 = 0;
3723 #[doc = "Select mux mode: ALT1 mux port: WDOG1_B of instance: wdog1"]
3724 pub const ALT1: u32 = 0x01;
3725 #[doc = "Select mux mode: ALT2 mux port: LPUART8_TX of instance: lpuart8"]
3726 pub const ALT2: u32 = 0x02;
3727 #[doc = "Select mux mode: ALT3 mux port: SAI1_RX_SYNC of instance: sai1"]
3728 pub const ALT3: u32 = 0x03;
3729 #[doc = "Select mux mode: ALT4 mux port: CSI_DATA07 of instance: csi"]
3730 pub const ALT4: u32 = 0x04;
3731 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO26 of instance: gpio1"]
3732 pub const ALT5: u32 = 0x05;
3733 #[doc = "Select mux mode: ALT6 mux port: USDHC2_WP of instance: usdhc2"]
3734 pub const ALT6: u32 = 0x06;
3735 #[doc = "Select mux mode: ALT7 mux port: KPP_ROW02 of instance: kpp"]
3736 pub const ALT7: u32 = 0x07;
3737 #[doc = "Select mux mode: ALT8 mux port: ENET2_1588_EVENT1_OUT of instance: enet2"]
3738 pub const ALT8: u32 = 0x08;
3739 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO10 of instance: flexio3"]
3740 pub const ALT9: u32 = 0x09;
3741 }
3742 }
3743 #[doc = "Software Input On Field."]
3744 pub mod SION {
3745 pub const offset: u32 = 4;
3746 pub const mask: u32 = 0x01 << offset;
3747 pub mod R {}
3748 pub mod W {}
3749 pub mod RW {
3750 #[doc = "Input Path is determined by functionality"]
3751 pub const DISABLED: u32 = 0;
3752 #[doc = "Force input path of pad GPIO_AD_B1_10"]
3753 pub const ENABLED: u32 = 0x01;
3754 }
3755 }
3756}
3757#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_11 SW MUX Control Register"]
3758pub mod SW_MUX_CTL_PAD_GPIO_AD_B1_11 {
3759 #[doc = "MUX Mode Select Field."]
3760 pub mod MUX_MODE {
3761 pub const offset: u32 = 0;
3762 pub const mask: u32 = 0x0f << offset;
3763 pub mod R {}
3764 pub mod W {}
3765 pub mod RW {
3766 #[doc = "Select mux mode: ALT0 mux port: FLEXSPIA_DATA02 of instance: flexspi"]
3767 pub const ALT0: u32 = 0;
3768 #[doc = "Select mux mode: ALT1 mux port: EWM_OUT_B of instance: ewm"]
3769 pub const ALT1: u32 = 0x01;
3770 #[doc = "Select mux mode: ALT2 mux port: LPUART8_RX of instance: lpuart8"]
3771 pub const ALT2: u32 = 0x02;
3772 #[doc = "Select mux mode: ALT3 mux port: SAI1_RX_BCLK of instance: sai1"]
3773 pub const ALT3: u32 = 0x03;
3774 #[doc = "Select mux mode: ALT4 mux port: CSI_DATA06 of instance: csi"]
3775 pub const ALT4: u32 = 0x04;
3776 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO27 of instance: gpio1"]
3777 pub const ALT5: u32 = 0x05;
3778 #[doc = "Select mux mode: ALT6 mux port: USDHC2_RESET_B of instance: usdhc2"]
3779 pub const ALT6: u32 = 0x06;
3780 #[doc = "Select mux mode: ALT7 mux port: KPP_COL02 of instance: kpp"]
3781 pub const ALT7: u32 = 0x07;
3782 #[doc = "Select mux mode: ALT8 mux port: ENET2_1588_EVENT1_IN of instance: enet2"]
3783 pub const ALT8: u32 = 0x08;
3784 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO11 of instance: flexio3"]
3785 pub const ALT9: u32 = 0x09;
3786 }
3787 }
3788 #[doc = "Software Input On Field."]
3789 pub mod SION {
3790 pub const offset: u32 = 4;
3791 pub const mask: u32 = 0x01 << offset;
3792 pub mod R {}
3793 pub mod W {}
3794 pub mod RW {
3795 #[doc = "Input Path is determined by functionality"]
3796 pub const DISABLED: u32 = 0;
3797 #[doc = "Force input path of pad GPIO_AD_B1_11"]
3798 pub const ENABLED: u32 = 0x01;
3799 }
3800 }
3801}
3802#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_12 SW MUX Control Register"]
3803pub mod SW_MUX_CTL_PAD_GPIO_AD_B1_12 {
3804 #[doc = "MUX Mode Select Field."]
3805 pub mod MUX_MODE {
3806 pub const offset: u32 = 0;
3807 pub const mask: u32 = 0x0f << offset;
3808 pub mod R {}
3809 pub mod W {}
3810 pub mod RW {
3811 #[doc = "Select mux mode: ALT0 mux port: FLEXSPIA_DATA01 of instance: flexspi"]
3812 pub const ALT0: u32 = 0;
3813 #[doc = "Select mux mode: ALT1 mux port: ACMP_OUT00 of instance: acmp"]
3814 pub const ALT1: u32 = 0x01;
3815 #[doc = "Select mux mode: ALT2 mux port: LPSPI3_PCS0 of instance: lpspi3"]
3816 pub const ALT2: u32 = 0x02;
3817 #[doc = "Select mux mode: ALT3 mux port: SAI1_RX_DATA00 of instance: sai1"]
3818 pub const ALT3: u32 = 0x03;
3819 #[doc = "Select mux mode: ALT4 mux port: CSI_DATA05 of instance: csi"]
3820 pub const ALT4: u32 = 0x04;
3821 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO28 of instance: gpio1"]
3822 pub const ALT5: u32 = 0x05;
3823 #[doc = "Select mux mode: ALT6 mux port: USDHC2_DATA4 of instance: usdhc2"]
3824 pub const ALT6: u32 = 0x06;
3825 #[doc = "Select mux mode: ALT7 mux port: KPP_ROW01 of instance: kpp"]
3826 pub const ALT7: u32 = 0x07;
3827 #[doc = "Select mux mode: ALT8 mux port: ENET2_1588_EVENT2_OUT of instance: enet2"]
3828 pub const ALT8: u32 = 0x08;
3829 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO12 of instance: flexio3"]
3830 pub const ALT9: u32 = 0x09;
3831 }
3832 }
3833 #[doc = "Software Input On Field."]
3834 pub mod SION {
3835 pub const offset: u32 = 4;
3836 pub const mask: u32 = 0x01 << offset;
3837 pub mod R {}
3838 pub mod W {}
3839 pub mod RW {
3840 #[doc = "Input Path is determined by functionality"]
3841 pub const DISABLED: u32 = 0;
3842 #[doc = "Force input path of pad GPIO_AD_B1_12"]
3843 pub const ENABLED: u32 = 0x01;
3844 }
3845 }
3846}
3847#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_13 SW MUX Control Register"]
3848pub mod SW_MUX_CTL_PAD_GPIO_AD_B1_13 {
3849 #[doc = "MUX Mode Select Field."]
3850 pub mod MUX_MODE {
3851 pub const offset: u32 = 0;
3852 pub const mask: u32 = 0x0f << offset;
3853 pub mod R {}
3854 pub mod W {}
3855 pub mod RW {
3856 #[doc = "Select mux mode: ALT0 mux port: FLEXSPIA_DATA00 of instance: flexspi"]
3857 pub const ALT0: u32 = 0;
3858 #[doc = "Select mux mode: ALT1 mux port: ACMP_OUT01 of instance: acmp"]
3859 pub const ALT1: u32 = 0x01;
3860 #[doc = "Select mux mode: ALT2 mux port: LPSPI3_SDI of instance: lpspi3"]
3861 pub const ALT2: u32 = 0x02;
3862 #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_DATA00 of instance: sai1"]
3863 pub const ALT3: u32 = 0x03;
3864 #[doc = "Select mux mode: ALT4 mux port: CSI_DATA04 of instance: csi"]
3865 pub const ALT4: u32 = 0x04;
3866 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO29 of instance: gpio1"]
3867 pub const ALT5: u32 = 0x05;
3868 #[doc = "Select mux mode: ALT6 mux port: USDHC2_DATA5 of instance: usdhc2"]
3869 pub const ALT6: u32 = 0x06;
3870 #[doc = "Select mux mode: ALT7 mux port: KPP_COL01 of instance: kpp"]
3871 pub const ALT7: u32 = 0x07;
3872 #[doc = "Select mux mode: ALT8 mux port: ENET2_1588_EVENT2_IN of instance: enet2"]
3873 pub const ALT8: u32 = 0x08;
3874 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO13 of instance: flexio3"]
3875 pub const ALT9: u32 = 0x09;
3876 }
3877 }
3878 #[doc = "Software Input On Field."]
3879 pub mod SION {
3880 pub const offset: u32 = 4;
3881 pub const mask: u32 = 0x01 << offset;
3882 pub mod R {}
3883 pub mod W {}
3884 pub mod RW {
3885 #[doc = "Input Path is determined by functionality"]
3886 pub const DISABLED: u32 = 0;
3887 #[doc = "Force input path of pad GPIO_AD_B1_13"]
3888 pub const ENABLED: u32 = 0x01;
3889 }
3890 }
3891}
3892#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_14 SW MUX Control Register"]
3893pub mod SW_MUX_CTL_PAD_GPIO_AD_B1_14 {
3894 #[doc = "MUX Mode Select Field."]
3895 pub mod MUX_MODE {
3896 pub const offset: u32 = 0;
3897 pub const mask: u32 = 0x0f << offset;
3898 pub mod R {}
3899 pub mod W {}
3900 pub mod RW {
3901 #[doc = "Select mux mode: ALT0 mux port: FLEXSPIA_SCLK of instance: flexspi"]
3902 pub const ALT0: u32 = 0;
3903 #[doc = "Select mux mode: ALT1 mux port: ACMP_OUT02 of instance: acmp"]
3904 pub const ALT1: u32 = 0x01;
3905 #[doc = "Select mux mode: ALT2 mux port: LPSPI3_SDO of instance: lpspi3"]
3906 pub const ALT2: u32 = 0x02;
3907 #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_BCLK of instance: sai1"]
3908 pub const ALT3: u32 = 0x03;
3909 #[doc = "Select mux mode: ALT4 mux port: CSI_DATA03 of instance: csi"]
3910 pub const ALT4: u32 = 0x04;
3911 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO30 of instance: gpio1"]
3912 pub const ALT5: u32 = 0x05;
3913 #[doc = "Select mux mode: ALT6 mux port: USDHC2_DATA6 of instance: usdhc2"]
3914 pub const ALT6: u32 = 0x06;
3915 #[doc = "Select mux mode: ALT7 mux port: KPP_ROW00 of instance: kpp"]
3916 pub const ALT7: u32 = 0x07;
3917 #[doc = "Select mux mode: ALT8 mux port: ENET2_1588_EVENT3_OUT of instance: enet2"]
3918 pub const ALT8: u32 = 0x08;
3919 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO14 of instance: flexio3"]
3920 pub const ALT9: u32 = 0x09;
3921 }
3922 }
3923 #[doc = "Software Input On Field."]
3924 pub mod SION {
3925 pub const offset: u32 = 4;
3926 pub const mask: u32 = 0x01 << offset;
3927 pub mod R {}
3928 pub mod W {}
3929 pub mod RW {
3930 #[doc = "Input Path is determined by functionality"]
3931 pub const DISABLED: u32 = 0;
3932 #[doc = "Force input path of pad GPIO_AD_B1_14"]
3933 pub const ENABLED: u32 = 0x01;
3934 }
3935 }
3936}
3937#[doc = "SW_MUX_CTL_PAD_GPIO_AD_B1_15 SW MUX Control Register"]
3938pub mod SW_MUX_CTL_PAD_GPIO_AD_B1_15 {
3939 #[doc = "MUX Mode Select Field."]
3940 pub mod MUX_MODE {
3941 pub const offset: u32 = 0;
3942 pub const mask: u32 = 0x0f << offset;
3943 pub mod R {}
3944 pub mod W {}
3945 pub mod RW {
3946 #[doc = "Select mux mode: ALT0 mux port: FLEXSPIA_SS0_B of instance: flexspi"]
3947 pub const ALT0: u32 = 0;
3948 #[doc = "Select mux mode: ALT1 mux port: ACMP_OUT03 of instance: acmp"]
3949 pub const ALT1: u32 = 0x01;
3950 #[doc = "Select mux mode: ALT2 mux port: LPSPI3_SCK of instance: lpspi3"]
3951 pub const ALT2: u32 = 0x02;
3952 #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_SYNC of instance: sai1"]
3953 pub const ALT3: u32 = 0x03;
3954 #[doc = "Select mux mode: ALT4 mux port: CSI_DATA02 of instance: csi"]
3955 pub const ALT4: u32 = 0x04;
3956 #[doc = "Select mux mode: ALT5 mux port: GPIO1_IO31 of instance: gpio1"]
3957 pub const ALT5: u32 = 0x05;
3958 #[doc = "Select mux mode: ALT6 mux port: USDHC2_DATA7 of instance: usdhc2"]
3959 pub const ALT6: u32 = 0x06;
3960 #[doc = "Select mux mode: ALT7 mux port: KPP_COL00 of instance: kpp"]
3961 pub const ALT7: u32 = 0x07;
3962 #[doc = "Select mux mode: ALT8 mux port: ENET2_1588_EVENT3_IN of instance: enet2"]
3963 pub const ALT8: u32 = 0x08;
3964 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO15 of instance: flexio3"]
3965 pub const ALT9: u32 = 0x09;
3966 }
3967 }
3968 #[doc = "Software Input On Field."]
3969 pub mod SION {
3970 pub const offset: u32 = 4;
3971 pub const mask: u32 = 0x01 << offset;
3972 pub mod R {}
3973 pub mod W {}
3974 pub mod RW {
3975 #[doc = "Input Path is determined by functionality"]
3976 pub const DISABLED: u32 = 0;
3977 #[doc = "Force input path of pad GPIO_AD_B1_15"]
3978 pub const ENABLED: u32 = 0x01;
3979 }
3980 }
3981}
3982#[doc = "SW_MUX_CTL_PAD_GPIO_B0_00 SW MUX Control Register"]
3983pub mod SW_MUX_CTL_PAD_GPIO_B0_00 {
3984 #[doc = "MUX Mode Select Field."]
3985 pub mod MUX_MODE {
3986 pub const offset: u32 = 0;
3987 pub const mask: u32 = 0x0f << offset;
3988 pub mod R {}
3989 pub mod W {}
3990 pub mod RW {
3991 #[doc = "Select mux mode: ALT0 mux port: LCD_CLK of instance: lcdif"]
3992 pub const ALT0: u32 = 0;
3993 #[doc = "Select mux mode: ALT1 mux port: QTIMER1_TIMER0 of instance: qtimer1"]
3994 pub const ALT1: u32 = 0x01;
3995 #[doc = "Select mux mode: ALT2 mux port: MQS_RIGHT of instance: mqs"]
3996 pub const ALT2: u32 = 0x02;
3997 #[doc = "Select mux mode: ALT3 mux port: LPSPI4_PCS0 of instance: lpspi4"]
3998 pub const ALT3: u32 = 0x03;
3999 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO00 of instance: flexio2"]
4000 pub const ALT4: u32 = 0x04;
4001 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO00 of instance: gpio2"]
4002 pub const ALT5: u32 = 0x05;
4003 #[doc = "Select mux mode: ALT6 mux port: SEMC_CSX01 of instance: semc"]
4004 pub const ALT6: u32 = 0x06;
4005 #[doc = "Select mux mode: ALT8 mux port: ENET2_MDC of instance: enet2"]
4006 pub const ALT8: u32 = 0x08;
4007 }
4008 }
4009 #[doc = "Software Input On Field."]
4010 pub mod SION {
4011 pub const offset: u32 = 4;
4012 pub const mask: u32 = 0x01 << offset;
4013 pub mod R {}
4014 pub mod W {}
4015 pub mod RW {
4016 #[doc = "Input Path is determined by functionality"]
4017 pub const DISABLED: u32 = 0;
4018 #[doc = "Force input path of pad GPIO_B0_00"]
4019 pub const ENABLED: u32 = 0x01;
4020 }
4021 }
4022}
4023#[doc = "SW_MUX_CTL_PAD_GPIO_B0_01 SW MUX Control Register"]
4024pub mod SW_MUX_CTL_PAD_GPIO_B0_01 {
4025 #[doc = "MUX Mode Select Field."]
4026 pub mod MUX_MODE {
4027 pub const offset: u32 = 0;
4028 pub const mask: u32 = 0x0f << offset;
4029 pub mod R {}
4030 pub mod W {}
4031 pub mod RW {
4032 #[doc = "Select mux mode: ALT0 mux port: LCD_ENABLE of instance: lcdif"]
4033 pub const ALT0: u32 = 0;
4034 #[doc = "Select mux mode: ALT1 mux port: QTIMER1_TIMER1 of instance: qtimer1"]
4035 pub const ALT1: u32 = 0x01;
4036 #[doc = "Select mux mode: ALT2 mux port: MQS_LEFT of instance: mqs"]
4037 pub const ALT2: u32 = 0x02;
4038 #[doc = "Select mux mode: ALT3 mux port: LPSPI4_SDI of instance: lpspi4"]
4039 pub const ALT3: u32 = 0x03;
4040 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO01 of instance: flexio2"]
4041 pub const ALT4: u32 = 0x04;
4042 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO01 of instance: gpio2"]
4043 pub const ALT5: u32 = 0x05;
4044 #[doc = "Select mux mode: ALT6 mux port: SEMC_CSX02 of instance: semc"]
4045 pub const ALT6: u32 = 0x06;
4046 #[doc = "Select mux mode: ALT8 mux port: ENET2_MDIO of instance: enet2"]
4047 pub const ALT8: u32 = 0x08;
4048 }
4049 }
4050 #[doc = "Software Input On Field."]
4051 pub mod SION {
4052 pub const offset: u32 = 4;
4053 pub const mask: u32 = 0x01 << offset;
4054 pub mod R {}
4055 pub mod W {}
4056 pub mod RW {
4057 #[doc = "Input Path is determined by functionality"]
4058 pub const DISABLED: u32 = 0;
4059 #[doc = "Force input path of pad GPIO_B0_01"]
4060 pub const ENABLED: u32 = 0x01;
4061 }
4062 }
4063}
4064#[doc = "SW_MUX_CTL_PAD_GPIO_B0_02 SW MUX Control Register"]
4065pub mod SW_MUX_CTL_PAD_GPIO_B0_02 {
4066 #[doc = "MUX Mode Select Field."]
4067 pub mod MUX_MODE {
4068 pub const offset: u32 = 0;
4069 pub const mask: u32 = 0x0f << offset;
4070 pub mod R {}
4071 pub mod W {}
4072 pub mod RW {
4073 #[doc = "Select mux mode: ALT0 mux port: LCD_HSYNC of instance: lcdif"]
4074 pub const ALT0: u32 = 0;
4075 #[doc = "Select mux mode: ALT1 mux port: QTIMER1_TIMER2 of instance: qtimer1"]
4076 pub const ALT1: u32 = 0x01;
4077 #[doc = "Select mux mode: ALT2 mux port: FLEXCAN1_TX of instance: flexcan1"]
4078 pub const ALT2: u32 = 0x02;
4079 #[doc = "Select mux mode: ALT3 mux port: LPSPI4_SDO of instance: lpspi4"]
4080 pub const ALT3: u32 = 0x03;
4081 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO02 of instance: flexio2"]
4082 pub const ALT4: u32 = 0x04;
4083 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO02 of instance: gpio2"]
4084 pub const ALT5: u32 = 0x05;
4085 #[doc = "Select mux mode: ALT6 mux port: SEMC_CSX03 of instance: semc"]
4086 pub const ALT6: u32 = 0x06;
4087 #[doc = "Select mux mode: ALT8 mux port: ENET2_1588_EVENT0_OUT of instance: enet2"]
4088 pub const ALT8: u32 = 0x08;
4089 }
4090 }
4091 #[doc = "Software Input On Field."]
4092 pub mod SION {
4093 pub const offset: u32 = 4;
4094 pub const mask: u32 = 0x01 << offset;
4095 pub mod R {}
4096 pub mod W {}
4097 pub mod RW {
4098 #[doc = "Input Path is determined by functionality"]
4099 pub const DISABLED: u32 = 0;
4100 #[doc = "Force input path of pad GPIO_B0_02"]
4101 pub const ENABLED: u32 = 0x01;
4102 }
4103 }
4104}
4105#[doc = "SW_MUX_CTL_PAD_GPIO_B0_03 SW MUX Control Register"]
4106pub mod SW_MUX_CTL_PAD_GPIO_B0_03 {
4107 #[doc = "MUX Mode Select Field."]
4108 pub mod MUX_MODE {
4109 pub const offset: u32 = 0;
4110 pub const mask: u32 = 0x0f << offset;
4111 pub mod R {}
4112 pub mod W {}
4113 pub mod RW {
4114 #[doc = "Select mux mode: ALT0 mux port: LCD_VSYNC of instance: lcdif"]
4115 pub const ALT0: u32 = 0;
4116 #[doc = "Select mux mode: ALT1 mux port: QTIMER2_TIMER0 of instance: qtimer2"]
4117 pub const ALT1: u32 = 0x01;
4118 #[doc = "Select mux mode: ALT2 mux port: FLEXCAN1_RX of instance: flexcan1"]
4119 pub const ALT2: u32 = 0x02;
4120 #[doc = "Select mux mode: ALT3 mux port: LPSPI4_SCK of instance: lpspi4"]
4121 pub const ALT3: u32 = 0x03;
4122 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO03 of instance: flexio2"]
4123 pub const ALT4: u32 = 0x04;
4124 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO03 of instance: gpio2"]
4125 pub const ALT5: u32 = 0x05;
4126 #[doc = "Select mux mode: ALT6 mux port: WDOG2_RESET_B_DEB of instance: wdog2"]
4127 pub const ALT6: u32 = 0x06;
4128 #[doc = "Select mux mode: ALT8 mux port: ENET2_1588_EVENT0_IN of instance: enet2"]
4129 pub const ALT8: u32 = 0x08;
4130 }
4131 }
4132 #[doc = "Software Input On Field."]
4133 pub mod SION {
4134 pub const offset: u32 = 4;
4135 pub const mask: u32 = 0x01 << offset;
4136 pub mod R {}
4137 pub mod W {}
4138 pub mod RW {
4139 #[doc = "Input Path is determined by functionality"]
4140 pub const DISABLED: u32 = 0;
4141 #[doc = "Force input path of pad GPIO_B0_03"]
4142 pub const ENABLED: u32 = 0x01;
4143 }
4144 }
4145}
4146#[doc = "SW_MUX_CTL_PAD_GPIO_B0_04 SW MUX Control Register"]
4147pub mod SW_MUX_CTL_PAD_GPIO_B0_04 {
4148 #[doc = "MUX Mode Select Field."]
4149 pub mod MUX_MODE {
4150 pub const offset: u32 = 0;
4151 pub const mask: u32 = 0x0f << offset;
4152 pub mod R {}
4153 pub mod W {}
4154 pub mod RW {
4155 #[doc = "Select mux mode: ALT0 mux port: LCD_DATA00 of instance: lcdif"]
4156 pub const ALT0: u32 = 0;
4157 #[doc = "Select mux mode: ALT1 mux port: QTIMER2_TIMER1 of instance: qtimer2"]
4158 pub const ALT1: u32 = 0x01;
4159 #[doc = "Select mux mode: ALT2 mux port: LPI2C2_SCL of instance: lpi2c2"]
4160 pub const ALT2: u32 = 0x02;
4161 #[doc = "Select mux mode: ALT3 mux port: ARM_TRACE0 of instance: cm7_mx6rt"]
4162 pub const ALT3: u32 = 0x03;
4163 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO04 of instance: flexio2"]
4164 pub const ALT4: u32 = 0x04;
4165 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO04 of instance: gpio2"]
4166 pub const ALT5: u32 = 0x05;
4167 #[doc = "Select mux mode: ALT6 mux port: SRC_BOOT_CFG00 of instance: src"]
4168 pub const ALT6: u32 = 0x06;
4169 #[doc = "Select mux mode: ALT8 mux port: ENET2_TDATA03 of instance: enet2"]
4170 pub const ALT8: u32 = 0x08;
4171 }
4172 }
4173 #[doc = "Software Input On Field."]
4174 pub mod SION {
4175 pub const offset: u32 = 4;
4176 pub const mask: u32 = 0x01 << offset;
4177 pub mod R {}
4178 pub mod W {}
4179 pub mod RW {
4180 #[doc = "Input Path is determined by functionality"]
4181 pub const DISABLED: u32 = 0;
4182 #[doc = "Force input path of pad GPIO_B0_04"]
4183 pub const ENABLED: u32 = 0x01;
4184 }
4185 }
4186}
4187#[doc = "SW_MUX_CTL_PAD_GPIO_B0_05 SW MUX Control Register"]
4188pub mod SW_MUX_CTL_PAD_GPIO_B0_05 {
4189 #[doc = "MUX Mode Select Field."]
4190 pub mod MUX_MODE {
4191 pub const offset: u32 = 0;
4192 pub const mask: u32 = 0x0f << offset;
4193 pub mod R {}
4194 pub mod W {}
4195 pub mod RW {
4196 #[doc = "Select mux mode: ALT0 mux port: LCD_DATA01 of instance: lcdif"]
4197 pub const ALT0: u32 = 0;
4198 #[doc = "Select mux mode: ALT1 mux port: QTIMER2_TIMER2 of instance: qtimer2"]
4199 pub const ALT1: u32 = 0x01;
4200 #[doc = "Select mux mode: ALT2 mux port: LPI2C2_SDA of instance: lpi2c2"]
4201 pub const ALT2: u32 = 0x02;
4202 #[doc = "Select mux mode: ALT3 mux port: ARM_TRACE1 of instance: cm7_mx6rt"]
4203 pub const ALT3: u32 = 0x03;
4204 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO05 of instance: flexio2"]
4205 pub const ALT4: u32 = 0x04;
4206 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO05 of instance: gpio2"]
4207 pub const ALT5: u32 = 0x05;
4208 #[doc = "Select mux mode: ALT6 mux port: SRC_BOOT_CFG01 of instance: src"]
4209 pub const ALT6: u32 = 0x06;
4210 #[doc = "Select mux mode: ALT8 mux port: ENET2_TDATA02 of instance: enet2"]
4211 pub const ALT8: u32 = 0x08;
4212 }
4213 }
4214 #[doc = "Software Input On Field."]
4215 pub mod SION {
4216 pub const offset: u32 = 4;
4217 pub const mask: u32 = 0x01 << offset;
4218 pub mod R {}
4219 pub mod W {}
4220 pub mod RW {
4221 #[doc = "Input Path is determined by functionality"]
4222 pub const DISABLED: u32 = 0;
4223 #[doc = "Force input path of pad GPIO_B0_05"]
4224 pub const ENABLED: u32 = 0x01;
4225 }
4226 }
4227}
4228#[doc = "SW_MUX_CTL_PAD_GPIO_B0_06 SW MUX Control Register"]
4229pub mod SW_MUX_CTL_PAD_GPIO_B0_06 {
4230 #[doc = "MUX Mode Select Field."]
4231 pub mod MUX_MODE {
4232 pub const offset: u32 = 0;
4233 pub const mask: u32 = 0x0f << offset;
4234 pub mod R {}
4235 pub mod W {}
4236 pub mod RW {
4237 #[doc = "Select mux mode: ALT0 mux port: LCD_DATA02 of instance: lcdif"]
4238 pub const ALT0: u32 = 0;
4239 #[doc = "Select mux mode: ALT1 mux port: QTIMER3_TIMER0 of instance: qtimer3"]
4240 pub const ALT1: u32 = 0x01;
4241 #[doc = "Select mux mode: ALT2 mux port: FLEXPWM2_PWMA00 of instance: flexpwm2"]
4242 pub const ALT2: u32 = 0x02;
4243 #[doc = "Select mux mode: ALT3 mux port: ARM_TRACE2 of instance: cm7_mx6rt"]
4244 pub const ALT3: u32 = 0x03;
4245 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO06 of instance: flexio2"]
4246 pub const ALT4: u32 = 0x04;
4247 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO06 of instance: gpio2"]
4248 pub const ALT5: u32 = 0x05;
4249 #[doc = "Select mux mode: ALT6 mux port: SRC_BOOT_CFG02 of instance: src"]
4250 pub const ALT6: u32 = 0x06;
4251 #[doc = "Select mux mode: ALT8 mux port: ENET2_RX_CLK of instance: enet2"]
4252 pub const ALT8: u32 = 0x08;
4253 }
4254 }
4255 #[doc = "Software Input On Field."]
4256 pub mod SION {
4257 pub const offset: u32 = 4;
4258 pub const mask: u32 = 0x01 << offset;
4259 pub mod R {}
4260 pub mod W {}
4261 pub mod RW {
4262 #[doc = "Input Path is determined by functionality"]
4263 pub const DISABLED: u32 = 0;
4264 #[doc = "Force input path of pad GPIO_B0_06"]
4265 pub const ENABLED: u32 = 0x01;
4266 }
4267 }
4268}
4269#[doc = "SW_MUX_CTL_PAD_GPIO_B0_07 SW MUX Control Register"]
4270pub mod SW_MUX_CTL_PAD_GPIO_B0_07 {
4271 #[doc = "MUX Mode Select Field."]
4272 pub mod MUX_MODE {
4273 pub const offset: u32 = 0;
4274 pub const mask: u32 = 0x0f << offset;
4275 pub mod R {}
4276 pub mod W {}
4277 pub mod RW {
4278 #[doc = "Select mux mode: ALT0 mux port: LCD_DATA03 of instance: lcdif"]
4279 pub const ALT0: u32 = 0;
4280 #[doc = "Select mux mode: ALT1 mux port: QTIMER3_TIMER1 of instance: qtimer3"]
4281 pub const ALT1: u32 = 0x01;
4282 #[doc = "Select mux mode: ALT2 mux port: FLEXPWM2_PWMB00 of instance: flexpwm2"]
4283 pub const ALT2: u32 = 0x02;
4284 #[doc = "Select mux mode: ALT3 mux port: ARM_TRACE3 of instance: cm7_mx6rt"]
4285 pub const ALT3: u32 = 0x03;
4286 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO07 of instance: flexio2"]
4287 pub const ALT4: u32 = 0x04;
4288 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO07 of instance: gpio2"]
4289 pub const ALT5: u32 = 0x05;
4290 #[doc = "Select mux mode: ALT6 mux port: SRC_BOOT_CFG03 of instance: src"]
4291 pub const ALT6: u32 = 0x06;
4292 #[doc = "Select mux mode: ALT8 mux port: ENET2_TX_ER of instance: enet2"]
4293 pub const ALT8: u32 = 0x08;
4294 }
4295 }
4296 #[doc = "Software Input On Field."]
4297 pub mod SION {
4298 pub const offset: u32 = 4;
4299 pub const mask: u32 = 0x01 << offset;
4300 pub mod R {}
4301 pub mod W {}
4302 pub mod RW {
4303 #[doc = "Input Path is determined by functionality"]
4304 pub const DISABLED: u32 = 0;
4305 #[doc = "Force input path of pad GPIO_B0_07"]
4306 pub const ENABLED: u32 = 0x01;
4307 }
4308 }
4309}
4310#[doc = "SW_MUX_CTL_PAD_GPIO_B0_08 SW MUX Control Register"]
4311pub mod SW_MUX_CTL_PAD_GPIO_B0_08 {
4312 #[doc = "MUX Mode Select Field."]
4313 pub mod MUX_MODE {
4314 pub const offset: u32 = 0;
4315 pub const mask: u32 = 0x0f << offset;
4316 pub mod R {}
4317 pub mod W {}
4318 pub mod RW {
4319 #[doc = "Select mux mode: ALT0 mux port: LCD_DATA04 of instance: lcdif"]
4320 pub const ALT0: u32 = 0;
4321 #[doc = "Select mux mode: ALT1 mux port: QTIMER3_TIMER2 of instance: qtimer3"]
4322 pub const ALT1: u32 = 0x01;
4323 #[doc = "Select mux mode: ALT2 mux port: FLEXPWM2_PWMA01 of instance: flexpwm2"]
4324 pub const ALT2: u32 = 0x02;
4325 #[doc = "Select mux mode: ALT3 mux port: LPUART3_TX of instance: lpuart3"]
4326 pub const ALT3: u32 = 0x03;
4327 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO08 of instance: flexio2"]
4328 pub const ALT4: u32 = 0x04;
4329 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO08 of instance: gpio2"]
4330 pub const ALT5: u32 = 0x05;
4331 #[doc = "Select mux mode: ALT6 mux port: SRC_BOOT_CFG04 of instance: src"]
4332 pub const ALT6: u32 = 0x06;
4333 #[doc = "Select mux mode: ALT8 mux port: ENET2_RDATA03 of instance: enet2"]
4334 pub const ALT8: u32 = 0x08;
4335 }
4336 }
4337 #[doc = "Software Input On Field."]
4338 pub mod SION {
4339 pub const offset: u32 = 4;
4340 pub const mask: u32 = 0x01 << offset;
4341 pub mod R {}
4342 pub mod W {}
4343 pub mod RW {
4344 #[doc = "Input Path is determined by functionality"]
4345 pub const DISABLED: u32 = 0;
4346 #[doc = "Force input path of pad GPIO_B0_08"]
4347 pub const ENABLED: u32 = 0x01;
4348 }
4349 }
4350}
4351#[doc = "SW_MUX_CTL_PAD_GPIO_B0_09 SW MUX Control Register"]
4352pub mod SW_MUX_CTL_PAD_GPIO_B0_09 {
4353 #[doc = "MUX Mode Select Field."]
4354 pub mod MUX_MODE {
4355 pub const offset: u32 = 0;
4356 pub const mask: u32 = 0x0f << offset;
4357 pub mod R {}
4358 pub mod W {}
4359 pub mod RW {
4360 #[doc = "Select mux mode: ALT0 mux port: LCD_DATA05 of instance: lcdif"]
4361 pub const ALT0: u32 = 0;
4362 #[doc = "Select mux mode: ALT1 mux port: QTIMER4_TIMER0 of instance: qtimer4"]
4363 pub const ALT1: u32 = 0x01;
4364 #[doc = "Select mux mode: ALT2 mux port: FLEXPWM2_PWMB01 of instance: flexpwm2"]
4365 pub const ALT2: u32 = 0x02;
4366 #[doc = "Select mux mode: ALT3 mux port: LPUART3_RX of instance: lpuart3"]
4367 pub const ALT3: u32 = 0x03;
4368 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO09 of instance: flexio2"]
4369 pub const ALT4: u32 = 0x04;
4370 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO09 of instance: gpio2"]
4371 pub const ALT5: u32 = 0x05;
4372 #[doc = "Select mux mode: ALT6 mux port: SRC_BOOT_CFG05 of instance: src"]
4373 pub const ALT6: u32 = 0x06;
4374 #[doc = "Select mux mode: ALT8 mux port: ENET2_RDATA02 of instance: enet2"]
4375 pub const ALT8: u32 = 0x08;
4376 }
4377 }
4378 #[doc = "Software Input On Field."]
4379 pub mod SION {
4380 pub const offset: u32 = 4;
4381 pub const mask: u32 = 0x01 << offset;
4382 pub mod R {}
4383 pub mod W {}
4384 pub mod RW {
4385 #[doc = "Input Path is determined by functionality"]
4386 pub const DISABLED: u32 = 0;
4387 #[doc = "Force input path of pad GPIO_B0_09"]
4388 pub const ENABLED: u32 = 0x01;
4389 }
4390 }
4391}
4392#[doc = "SW_MUX_CTL_PAD_GPIO_B0_10 SW MUX Control Register"]
4393pub mod SW_MUX_CTL_PAD_GPIO_B0_10 {
4394 #[doc = "MUX Mode Select Field."]
4395 pub mod MUX_MODE {
4396 pub const offset: u32 = 0;
4397 pub const mask: u32 = 0x0f << offset;
4398 pub mod R {}
4399 pub mod W {}
4400 pub mod RW {
4401 #[doc = "Select mux mode: ALT0 mux port: LCD_DATA06 of instance: lcdif"]
4402 pub const ALT0: u32 = 0;
4403 #[doc = "Select mux mode: ALT1 mux port: QTIMER4_TIMER1 of instance: qtimer4"]
4404 pub const ALT1: u32 = 0x01;
4405 #[doc = "Select mux mode: ALT2 mux port: FLEXPWM2_PWMA02 of instance: flexpwm2"]
4406 pub const ALT2: u32 = 0x02;
4407 #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_DATA03 of instance: sai1"]
4408 pub const ALT3: u32 = 0x03;
4409 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO10 of instance: flexio2"]
4410 pub const ALT4: u32 = 0x04;
4411 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO10 of instance: gpio2"]
4412 pub const ALT5: u32 = 0x05;
4413 #[doc = "Select mux mode: ALT6 mux port: SRC_BOOT_CFG06 of instance: src"]
4414 pub const ALT6: u32 = 0x06;
4415 #[doc = "Select mux mode: ALT8 mux port: ENET2_CRS of instance: enet2"]
4416 pub const ALT8: u32 = 0x08;
4417 }
4418 }
4419 #[doc = "Software Input On Field."]
4420 pub mod SION {
4421 pub const offset: u32 = 4;
4422 pub const mask: u32 = 0x01 << offset;
4423 pub mod R {}
4424 pub mod W {}
4425 pub mod RW {
4426 #[doc = "Input Path is determined by functionality"]
4427 pub const DISABLED: u32 = 0;
4428 #[doc = "Force input path of pad GPIO_B0_10"]
4429 pub const ENABLED: u32 = 0x01;
4430 }
4431 }
4432}
4433#[doc = "SW_MUX_CTL_PAD_GPIO_B0_11 SW MUX Control Register"]
4434pub mod SW_MUX_CTL_PAD_GPIO_B0_11 {
4435 #[doc = "MUX Mode Select Field."]
4436 pub mod MUX_MODE {
4437 pub const offset: u32 = 0;
4438 pub const mask: u32 = 0x0f << offset;
4439 pub mod R {}
4440 pub mod W {}
4441 pub mod RW {
4442 #[doc = "Select mux mode: ALT0 mux port: LCD_DATA07 of instance: lcdif"]
4443 pub const ALT0: u32 = 0;
4444 #[doc = "Select mux mode: ALT1 mux port: QTIMER4_TIMER2 of instance: qtimer4"]
4445 pub const ALT1: u32 = 0x01;
4446 #[doc = "Select mux mode: ALT2 mux port: FLEXPWM2_PWMB02 of instance: flexpwm2"]
4447 pub const ALT2: u32 = 0x02;
4448 #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_DATA02 of instance: sai1"]
4449 pub const ALT3: u32 = 0x03;
4450 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO11 of instance: flexio2"]
4451 pub const ALT4: u32 = 0x04;
4452 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO11 of instance: gpio2"]
4453 pub const ALT5: u32 = 0x05;
4454 #[doc = "Select mux mode: ALT6 mux port: SRC_BOOT_CFG07 of instance: src"]
4455 pub const ALT6: u32 = 0x06;
4456 #[doc = "Select mux mode: ALT8 mux port: ENET2_COL of instance: enet2"]
4457 pub const ALT8: u32 = 0x08;
4458 }
4459 }
4460 #[doc = "Software Input On Field."]
4461 pub mod SION {
4462 pub const offset: u32 = 4;
4463 pub const mask: u32 = 0x01 << offset;
4464 pub mod R {}
4465 pub mod W {}
4466 pub mod RW {
4467 #[doc = "Input Path is determined by functionality"]
4468 pub const DISABLED: u32 = 0;
4469 #[doc = "Force input path of pad GPIO_B0_11"]
4470 pub const ENABLED: u32 = 0x01;
4471 }
4472 }
4473}
4474#[doc = "SW_MUX_CTL_PAD_GPIO_B0_12 SW MUX Control Register"]
4475pub mod SW_MUX_CTL_PAD_GPIO_B0_12 {
4476 #[doc = "MUX Mode Select Field."]
4477 pub mod MUX_MODE {
4478 pub const offset: u32 = 0;
4479 pub const mask: u32 = 0x0f << offset;
4480 pub mod R {}
4481 pub mod W {}
4482 pub mod RW {
4483 #[doc = "Select mux mode: ALT0 mux port: LCD_DATA08 of instance: lcdif"]
4484 pub const ALT0: u32 = 0;
4485 #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT10 of instance: xbar1"]
4486 pub const ALT1: u32 = 0x01;
4487 #[doc = "Select mux mode: ALT2 mux port: ARM_TRACE_CLK of instance: cm7_mx6rt"]
4488 pub const ALT2: u32 = 0x02;
4489 #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_DATA01 of instance: sai1"]
4490 pub const ALT3: u32 = 0x03;
4491 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO12 of instance: flexio2"]
4492 pub const ALT4: u32 = 0x04;
4493 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO12 of instance: gpio2"]
4494 pub const ALT5: u32 = 0x05;
4495 #[doc = "Select mux mode: ALT6 mux port: SRC_BOOT_CFG08 of instance: src"]
4496 pub const ALT6: u32 = 0x06;
4497 #[doc = "Select mux mode: ALT8 mux port: ENET2_TDATA00 of instance: enet2"]
4498 pub const ALT8: u32 = 0x08;
4499 }
4500 }
4501 #[doc = "Software Input On Field."]
4502 pub mod SION {
4503 pub const offset: u32 = 4;
4504 pub const mask: u32 = 0x01 << offset;
4505 pub mod R {}
4506 pub mod W {}
4507 pub mod RW {
4508 #[doc = "Input Path is determined by functionality"]
4509 pub const DISABLED: u32 = 0;
4510 #[doc = "Force input path of pad GPIO_B0_12"]
4511 pub const ENABLED: u32 = 0x01;
4512 }
4513 }
4514}
4515#[doc = "SW_MUX_CTL_PAD_GPIO_B0_13 SW MUX Control Register"]
4516pub mod SW_MUX_CTL_PAD_GPIO_B0_13 {
4517 #[doc = "MUX Mode Select Field."]
4518 pub mod MUX_MODE {
4519 pub const offset: u32 = 0;
4520 pub const mask: u32 = 0x0f << offset;
4521 pub mod R {}
4522 pub mod W {}
4523 pub mod RW {
4524 #[doc = "Select mux mode: ALT0 mux port: LCD_DATA09 of instance: lcdif"]
4525 pub const ALT0: u32 = 0;
4526 #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT11 of instance: xbar1"]
4527 pub const ALT1: u32 = 0x01;
4528 #[doc = "Select mux mode: ALT2 mux port: ARM_TRACE_SWO of instance: cm7_mx6rt"]
4529 pub const ALT2: u32 = 0x02;
4530 #[doc = "Select mux mode: ALT3 mux port: SAI1_MCLK of instance: sai1"]
4531 pub const ALT3: u32 = 0x03;
4532 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO13 of instance: flexio2"]
4533 pub const ALT4: u32 = 0x04;
4534 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO13 of instance: gpio2"]
4535 pub const ALT5: u32 = 0x05;
4536 #[doc = "Select mux mode: ALT6 mux port: SRC_BOOT_CFG09 of instance: src"]
4537 pub const ALT6: u32 = 0x06;
4538 #[doc = "Select mux mode: ALT8 mux port: ENET2_TDATA01 of instance: enet2"]
4539 pub const ALT8: u32 = 0x08;
4540 }
4541 }
4542 #[doc = "Software Input On Field."]
4543 pub mod SION {
4544 pub const offset: u32 = 4;
4545 pub const mask: u32 = 0x01 << offset;
4546 pub mod R {}
4547 pub mod W {}
4548 pub mod RW {
4549 #[doc = "Input Path is determined by functionality"]
4550 pub const DISABLED: u32 = 0;
4551 #[doc = "Force input path of pad GPIO_B0_13"]
4552 pub const ENABLED: u32 = 0x01;
4553 }
4554 }
4555}
4556#[doc = "SW_MUX_CTL_PAD_GPIO_B0_14 SW MUX Control Register"]
4557pub mod SW_MUX_CTL_PAD_GPIO_B0_14 {
4558 #[doc = "MUX Mode Select Field."]
4559 pub mod MUX_MODE {
4560 pub const offset: u32 = 0;
4561 pub const mask: u32 = 0x0f << offset;
4562 pub mod R {}
4563 pub mod W {}
4564 pub mod RW {
4565 #[doc = "Select mux mode: ALT0 mux port: LCD_DATA10 of instance: lcdif"]
4566 pub const ALT0: u32 = 0;
4567 #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT12 of instance: xbar1"]
4568 pub const ALT1: u32 = 0x01;
4569 #[doc = "Select mux mode: ALT2 mux port: ARM_TXEV of instance: cm7_mx6rt"]
4570 pub const ALT2: u32 = 0x02;
4571 #[doc = "Select mux mode: ALT3 mux port: SAI1_RX_SYNC of instance: sai1"]
4572 pub const ALT3: u32 = 0x03;
4573 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO14 of instance: flexio2"]
4574 pub const ALT4: u32 = 0x04;
4575 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO14 of instance: gpio2"]
4576 pub const ALT5: u32 = 0x05;
4577 #[doc = "Select mux mode: ALT6 mux port: SRC_BOOT_CFG10 of instance: src"]
4578 pub const ALT6: u32 = 0x06;
4579 #[doc = "Select mux mode: ALT8 mux port: ENET2_TX_EN of instance: enet2"]
4580 pub const ALT8: u32 = 0x08;
4581 }
4582 }
4583 #[doc = "Software Input On Field."]
4584 pub mod SION {
4585 pub const offset: u32 = 4;
4586 pub const mask: u32 = 0x01 << offset;
4587 pub mod R {}
4588 pub mod W {}
4589 pub mod RW {
4590 #[doc = "Input Path is determined by functionality"]
4591 pub const DISABLED: u32 = 0;
4592 #[doc = "Force input path of pad GPIO_B0_14"]
4593 pub const ENABLED: u32 = 0x01;
4594 }
4595 }
4596}
4597#[doc = "SW_MUX_CTL_PAD_GPIO_B0_15 SW MUX Control Register"]
4598pub mod SW_MUX_CTL_PAD_GPIO_B0_15 {
4599 #[doc = "MUX Mode Select Field."]
4600 pub mod MUX_MODE {
4601 pub const offset: u32 = 0;
4602 pub const mask: u32 = 0x0f << offset;
4603 pub mod R {}
4604 pub mod W {}
4605 pub mod RW {
4606 #[doc = "Select mux mode: ALT0 mux port: LCD_DATA11 of instance: lcdif"]
4607 pub const ALT0: u32 = 0;
4608 #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT13 of instance: xbar1"]
4609 pub const ALT1: u32 = 0x01;
4610 #[doc = "Select mux mode: ALT2 mux port: ARM_RXEV of instance: cm7_mx6rt"]
4611 pub const ALT2: u32 = 0x02;
4612 #[doc = "Select mux mode: ALT3 mux port: SAI1_RX_BCLK of instance: sai1"]
4613 pub const ALT3: u32 = 0x03;
4614 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO15 of instance: flexio2"]
4615 pub const ALT4: u32 = 0x04;
4616 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO15 of instance: gpio2"]
4617 pub const ALT5: u32 = 0x05;
4618 #[doc = "Select mux mode: ALT6 mux port: SRC_BOOT_CFG11 of instance: src"]
4619 pub const ALT6: u32 = 0x06;
4620 #[doc = "Select mux mode: ALT8 mux port: ENET2_TX_CLK of instance: enet2"]
4621 pub const ALT8: u32 = 0x08;
4622 #[doc = "Select mux mode: ALT9 mux port: ENET2_REF_CLK2 of instance: enet2"]
4623 pub const ALT9: u32 = 0x09;
4624 }
4625 }
4626 #[doc = "Software Input On Field."]
4627 pub mod SION {
4628 pub const offset: u32 = 4;
4629 pub const mask: u32 = 0x01 << offset;
4630 pub mod R {}
4631 pub mod W {}
4632 pub mod RW {
4633 #[doc = "Input Path is determined by functionality"]
4634 pub const DISABLED: u32 = 0;
4635 #[doc = "Force input path of pad GPIO_B0_15"]
4636 pub const ENABLED: u32 = 0x01;
4637 }
4638 }
4639}
4640#[doc = "SW_MUX_CTL_PAD_GPIO_B1_00 SW MUX Control Register"]
4641pub mod SW_MUX_CTL_PAD_GPIO_B1_00 {
4642 #[doc = "MUX Mode Select Field."]
4643 pub mod MUX_MODE {
4644 pub const offset: u32 = 0;
4645 pub const mask: u32 = 0x0f << offset;
4646 pub mod R {}
4647 pub mod W {}
4648 pub mod RW {
4649 #[doc = "Select mux mode: ALT0 mux port: LCD_DATA12 of instance: lcdif"]
4650 pub const ALT0: u32 = 0;
4651 #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT14 of instance: xbar1"]
4652 pub const ALT1: u32 = 0x01;
4653 #[doc = "Select mux mode: ALT2 mux port: LPUART4_TX of instance: lpuart4"]
4654 pub const ALT2: u32 = 0x02;
4655 #[doc = "Select mux mode: ALT3 mux port: SAI1_RX_DATA00 of instance: sai1"]
4656 pub const ALT3: u32 = 0x03;
4657 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO16 of instance: flexio2"]
4658 pub const ALT4: u32 = 0x04;
4659 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO16 of instance: gpio2"]
4660 pub const ALT5: u32 = 0x05;
4661 #[doc = "Select mux mode: ALT6 mux port: FLEXPWM1_PWMA03 of instance: flexpwm1"]
4662 pub const ALT6: u32 = 0x06;
4663 #[doc = "Select mux mode: ALT8 mux port: ENET2_RX_ER of instance: enet2"]
4664 pub const ALT8: u32 = 0x08;
4665 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO16 of instance: flexio3"]
4666 pub const ALT9: u32 = 0x09;
4667 }
4668 }
4669 #[doc = "Software Input On Field."]
4670 pub mod SION {
4671 pub const offset: u32 = 4;
4672 pub const mask: u32 = 0x01 << offset;
4673 pub mod R {}
4674 pub mod W {}
4675 pub mod RW {
4676 #[doc = "Input Path is determined by functionality"]
4677 pub const DISABLED: u32 = 0;
4678 #[doc = "Force input path of pad GPIO_B1_00"]
4679 pub const ENABLED: u32 = 0x01;
4680 }
4681 }
4682}
4683#[doc = "SW_MUX_CTL_PAD_GPIO_B1_01 SW MUX Control Register"]
4684pub mod SW_MUX_CTL_PAD_GPIO_B1_01 {
4685 #[doc = "MUX Mode Select Field."]
4686 pub mod MUX_MODE {
4687 pub const offset: u32 = 0;
4688 pub const mask: u32 = 0x0f << offset;
4689 pub mod R {}
4690 pub mod W {}
4691 pub mod RW {
4692 #[doc = "Select mux mode: ALT0 mux port: LCD_DATA13 of instance: lcdif"]
4693 pub const ALT0: u32 = 0;
4694 #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT15 of instance: xbar1"]
4695 pub const ALT1: u32 = 0x01;
4696 #[doc = "Select mux mode: ALT2 mux port: LPUART4_RX of instance: lpuart4"]
4697 pub const ALT2: u32 = 0x02;
4698 #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_DATA00 of instance: sai1"]
4699 pub const ALT3: u32 = 0x03;
4700 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO17 of instance: flexio2"]
4701 pub const ALT4: u32 = 0x04;
4702 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO17 of instance: gpio2"]
4703 pub const ALT5: u32 = 0x05;
4704 #[doc = "Select mux mode: ALT6 mux port: FLEXPWM1_PWMB03 of instance: flexpwm1"]
4705 pub const ALT6: u32 = 0x06;
4706 #[doc = "Select mux mode: ALT8 mux port: ENET2_RDATA00 of instance: enet2"]
4707 pub const ALT8: u32 = 0x08;
4708 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO17 of instance: flexio3"]
4709 pub const ALT9: u32 = 0x09;
4710 }
4711 }
4712 #[doc = "Software Input On Field."]
4713 pub mod SION {
4714 pub const offset: u32 = 4;
4715 pub const mask: u32 = 0x01 << offset;
4716 pub mod R {}
4717 pub mod W {}
4718 pub mod RW {
4719 #[doc = "Input Path is determined by functionality"]
4720 pub const DISABLED: u32 = 0;
4721 #[doc = "Force input path of pad GPIO_B1_01"]
4722 pub const ENABLED: u32 = 0x01;
4723 }
4724 }
4725}
4726#[doc = "SW_MUX_CTL_PAD_GPIO_B1_02 SW MUX Control Register"]
4727pub mod SW_MUX_CTL_PAD_GPIO_B1_02 {
4728 #[doc = "MUX Mode Select Field."]
4729 pub mod MUX_MODE {
4730 pub const offset: u32 = 0;
4731 pub const mask: u32 = 0x0f << offset;
4732 pub mod R {}
4733 pub mod W {}
4734 pub mod RW {
4735 #[doc = "Select mux mode: ALT0 mux port: LCD_DATA14 of instance: lcdif"]
4736 pub const ALT0: u32 = 0;
4737 #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT16 of instance: xbar1"]
4738 pub const ALT1: u32 = 0x01;
4739 #[doc = "Select mux mode: ALT2 mux port: LPSPI4_PCS2 of instance: lpspi4"]
4740 pub const ALT2: u32 = 0x02;
4741 #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_BCLK of instance: sai1"]
4742 pub const ALT3: u32 = 0x03;
4743 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO18 of instance: flexio2"]
4744 pub const ALT4: u32 = 0x04;
4745 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO18 of instance: gpio2"]
4746 pub const ALT5: u32 = 0x05;
4747 #[doc = "Select mux mode: ALT6 mux port: FLEXPWM2_PWMA03 of instance: flexpwm2"]
4748 pub const ALT6: u32 = 0x06;
4749 #[doc = "Select mux mode: ALT8 mux port: ENET2_RDATA01 of instance: enet2"]
4750 pub const ALT8: u32 = 0x08;
4751 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO18 of instance: flexio3"]
4752 pub const ALT9: u32 = 0x09;
4753 }
4754 }
4755 #[doc = "Software Input On Field."]
4756 pub mod SION {
4757 pub const offset: u32 = 4;
4758 pub const mask: u32 = 0x01 << offset;
4759 pub mod R {}
4760 pub mod W {}
4761 pub mod RW {
4762 #[doc = "Input Path is determined by functionality"]
4763 pub const DISABLED: u32 = 0;
4764 #[doc = "Force input path of pad GPIO_B1_02"]
4765 pub const ENABLED: u32 = 0x01;
4766 }
4767 }
4768}
4769#[doc = "SW_MUX_CTL_PAD_GPIO_B1_03 SW MUX Control Register"]
4770pub mod SW_MUX_CTL_PAD_GPIO_B1_03 {
4771 #[doc = "MUX Mode Select Field."]
4772 pub mod MUX_MODE {
4773 pub const offset: u32 = 0;
4774 pub const mask: u32 = 0x0f << offset;
4775 pub mod R {}
4776 pub mod W {}
4777 pub mod RW {
4778 #[doc = "Select mux mode: ALT0 mux port: LCD_DATA15 of instance: lcdif"]
4779 pub const ALT0: u32 = 0;
4780 #[doc = "Select mux mode: ALT1 mux port: XBAR1_INOUT17 of instance: xbar1"]
4781 pub const ALT1: u32 = 0x01;
4782 #[doc = "Select mux mode: ALT2 mux port: LPSPI4_PCS1 of instance: lpspi4"]
4783 pub const ALT2: u32 = 0x02;
4784 #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_SYNC of instance: sai1"]
4785 pub const ALT3: u32 = 0x03;
4786 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO19 of instance: flexio2"]
4787 pub const ALT4: u32 = 0x04;
4788 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO19 of instance: gpio2"]
4789 pub const ALT5: u32 = 0x05;
4790 #[doc = "Select mux mode: ALT6 mux port: FLEXPWM2_PWMB03 of instance: flexpwm2"]
4791 pub const ALT6: u32 = 0x06;
4792 #[doc = "Select mux mode: ALT8 mux port: ENET2_RX_EN of instance: enet2"]
4793 pub const ALT8: u32 = 0x08;
4794 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO19 of instance: flexio3"]
4795 pub const ALT9: u32 = 0x09;
4796 }
4797 }
4798 #[doc = "Software Input On Field."]
4799 pub mod SION {
4800 pub const offset: u32 = 4;
4801 pub const mask: u32 = 0x01 << offset;
4802 pub mod R {}
4803 pub mod W {}
4804 pub mod RW {
4805 #[doc = "Input Path is determined by functionality"]
4806 pub const DISABLED: u32 = 0;
4807 #[doc = "Force input path of pad GPIO_B1_03"]
4808 pub const ENABLED: u32 = 0x01;
4809 }
4810 }
4811}
4812#[doc = "SW_MUX_CTL_PAD_GPIO_B1_04 SW MUX Control Register"]
4813pub mod SW_MUX_CTL_PAD_GPIO_B1_04 {
4814 #[doc = "MUX Mode Select Field."]
4815 pub mod MUX_MODE {
4816 pub const offset: u32 = 0;
4817 pub const mask: u32 = 0x0f << offset;
4818 pub mod R {}
4819 pub mod W {}
4820 pub mod RW {
4821 #[doc = "Select mux mode: ALT0 mux port: LCD_DATA16 of instance: lcdif"]
4822 pub const ALT0: u32 = 0;
4823 #[doc = "Select mux mode: ALT1 mux port: LPSPI4_PCS0 of instance: lpspi4"]
4824 pub const ALT1: u32 = 0x01;
4825 #[doc = "Select mux mode: ALT2 mux port: CSI_DATA15 of instance: csi"]
4826 pub const ALT2: u32 = 0x02;
4827 #[doc = "Select mux mode: ALT3 mux port: ENET_RX_DATA00 of instance: enet"]
4828 pub const ALT3: u32 = 0x03;
4829 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO20 of instance: flexio2"]
4830 pub const ALT4: u32 = 0x04;
4831 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO20 of instance: gpio2"]
4832 pub const ALT5: u32 = 0x05;
4833 #[doc = "Select mux mode: ALT8 mux port: GPT1_CLK of instance: gpt1"]
4834 pub const ALT8: u32 = 0x08;
4835 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO20 of instance: flexio3"]
4836 pub const ALT9: u32 = 0x09;
4837 }
4838 }
4839 #[doc = "Software Input On Field."]
4840 pub mod SION {
4841 pub const offset: u32 = 4;
4842 pub const mask: u32 = 0x01 << offset;
4843 pub mod R {}
4844 pub mod W {}
4845 pub mod RW {
4846 #[doc = "Input Path is determined by functionality"]
4847 pub const DISABLED: u32 = 0;
4848 #[doc = "Force input path of pad GPIO_B1_04"]
4849 pub const ENABLED: u32 = 0x01;
4850 }
4851 }
4852}
4853#[doc = "SW_MUX_CTL_PAD_GPIO_B1_05 SW MUX Control Register"]
4854pub mod SW_MUX_CTL_PAD_GPIO_B1_05 {
4855 #[doc = "MUX Mode Select Field."]
4856 pub mod MUX_MODE {
4857 pub const offset: u32 = 0;
4858 pub const mask: u32 = 0x0f << offset;
4859 pub mod R {}
4860 pub mod W {}
4861 pub mod RW {
4862 #[doc = "Select mux mode: ALT0 mux port: LCD_DATA17 of instance: lcdif"]
4863 pub const ALT0: u32 = 0;
4864 #[doc = "Select mux mode: ALT1 mux port: LPSPI4_SDI of instance: lpspi4"]
4865 pub const ALT1: u32 = 0x01;
4866 #[doc = "Select mux mode: ALT2 mux port: CSI_DATA14 of instance: csi"]
4867 pub const ALT2: u32 = 0x02;
4868 #[doc = "Select mux mode: ALT3 mux port: ENET_RX_DATA01 of instance: enet"]
4869 pub const ALT3: u32 = 0x03;
4870 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO21 of instance: flexio2"]
4871 pub const ALT4: u32 = 0x04;
4872 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO21 of instance: gpio2"]
4873 pub const ALT5: u32 = 0x05;
4874 #[doc = "Select mux mode: ALT8 mux port: GPT1_CAPTURE1 of instance: gpt1"]
4875 pub const ALT8: u32 = 0x08;
4876 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO21 of instance: flexio3"]
4877 pub const ALT9: u32 = 0x09;
4878 }
4879 }
4880 #[doc = "Software Input On Field."]
4881 pub mod SION {
4882 pub const offset: u32 = 4;
4883 pub const mask: u32 = 0x01 << offset;
4884 pub mod R {}
4885 pub mod W {}
4886 pub mod RW {
4887 #[doc = "Input Path is determined by functionality"]
4888 pub const DISABLED: u32 = 0;
4889 #[doc = "Force input path of pad GPIO_B1_05"]
4890 pub const ENABLED: u32 = 0x01;
4891 }
4892 }
4893}
4894#[doc = "SW_MUX_CTL_PAD_GPIO_B1_06 SW MUX Control Register"]
4895pub mod SW_MUX_CTL_PAD_GPIO_B1_06 {
4896 #[doc = "MUX Mode Select Field."]
4897 pub mod MUX_MODE {
4898 pub const offset: u32 = 0;
4899 pub const mask: u32 = 0x0f << offset;
4900 pub mod R {}
4901 pub mod W {}
4902 pub mod RW {
4903 #[doc = "Select mux mode: ALT0 mux port: LCD_DATA18 of instance: lcdif"]
4904 pub const ALT0: u32 = 0;
4905 #[doc = "Select mux mode: ALT1 mux port: LPSPI4_SDO of instance: lpspi4"]
4906 pub const ALT1: u32 = 0x01;
4907 #[doc = "Select mux mode: ALT2 mux port: CSI_DATA13 of instance: csi"]
4908 pub const ALT2: u32 = 0x02;
4909 #[doc = "Select mux mode: ALT3 mux port: ENET_RX_EN of instance: enet"]
4910 pub const ALT3: u32 = 0x03;
4911 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO22 of instance: flexio2"]
4912 pub const ALT4: u32 = 0x04;
4913 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO22 of instance: gpio2"]
4914 pub const ALT5: u32 = 0x05;
4915 #[doc = "Select mux mode: ALT8 mux port: GPT1_CAPTURE2 of instance: gpt1"]
4916 pub const ALT8: u32 = 0x08;
4917 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO22 of instance: flexio3"]
4918 pub const ALT9: u32 = 0x09;
4919 }
4920 }
4921 #[doc = "Software Input On Field."]
4922 pub mod SION {
4923 pub const offset: u32 = 4;
4924 pub const mask: u32 = 0x01 << offset;
4925 pub mod R {}
4926 pub mod W {}
4927 pub mod RW {
4928 #[doc = "Input Path is determined by functionality"]
4929 pub const DISABLED: u32 = 0;
4930 #[doc = "Force input path of pad GPIO_B1_06"]
4931 pub const ENABLED: u32 = 0x01;
4932 }
4933 }
4934}
4935#[doc = "SW_MUX_CTL_PAD_GPIO_B1_07 SW MUX Control Register"]
4936pub mod SW_MUX_CTL_PAD_GPIO_B1_07 {
4937 #[doc = "MUX Mode Select Field."]
4938 pub mod MUX_MODE {
4939 pub const offset: u32 = 0;
4940 pub const mask: u32 = 0x0f << offset;
4941 pub mod R {}
4942 pub mod W {}
4943 pub mod RW {
4944 #[doc = "Select mux mode: ALT0 mux port: LCD_DATA19 of instance: lcdif"]
4945 pub const ALT0: u32 = 0;
4946 #[doc = "Select mux mode: ALT1 mux port: LPSPI4_SCK of instance: lpspi4"]
4947 pub const ALT1: u32 = 0x01;
4948 #[doc = "Select mux mode: ALT2 mux port: CSI_DATA12 of instance: csi"]
4949 pub const ALT2: u32 = 0x02;
4950 #[doc = "Select mux mode: ALT3 mux port: ENET_TX_DATA00 of instance: enet"]
4951 pub const ALT3: u32 = 0x03;
4952 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO23 of instance: flexio2"]
4953 pub const ALT4: u32 = 0x04;
4954 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO23 of instance: gpio2"]
4955 pub const ALT5: u32 = 0x05;
4956 #[doc = "Select mux mode: ALT8 mux port: GPT1_COMPARE1 of instance: gpt1"]
4957 pub const ALT8: u32 = 0x08;
4958 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO23 of instance: flexio3"]
4959 pub const ALT9: u32 = 0x09;
4960 }
4961 }
4962 #[doc = "Software Input On Field."]
4963 pub mod SION {
4964 pub const offset: u32 = 4;
4965 pub const mask: u32 = 0x01 << offset;
4966 pub mod R {}
4967 pub mod W {}
4968 pub mod RW {
4969 #[doc = "Input Path is determined by functionality"]
4970 pub const DISABLED: u32 = 0;
4971 #[doc = "Force input path of pad GPIO_B1_07"]
4972 pub const ENABLED: u32 = 0x01;
4973 }
4974 }
4975}
4976#[doc = "SW_MUX_CTL_PAD_GPIO_B1_08 SW MUX Control Register"]
4977pub mod SW_MUX_CTL_PAD_GPIO_B1_08 {
4978 #[doc = "MUX Mode Select Field."]
4979 pub mod MUX_MODE {
4980 pub const offset: u32 = 0;
4981 pub const mask: u32 = 0x0f << offset;
4982 pub mod R {}
4983 pub mod W {}
4984 pub mod RW {
4985 #[doc = "Select mux mode: ALT0 mux port: LCD_DATA20 of instance: lcdif"]
4986 pub const ALT0: u32 = 0;
4987 #[doc = "Select mux mode: ALT1 mux port: QTIMER1_TIMER3 of instance: qtimer1"]
4988 pub const ALT1: u32 = 0x01;
4989 #[doc = "Select mux mode: ALT2 mux port: CSI_DATA11 of instance: csi"]
4990 pub const ALT2: u32 = 0x02;
4991 #[doc = "Select mux mode: ALT3 mux port: ENET_TX_DATA01 of instance: enet"]
4992 pub const ALT3: u32 = 0x03;
4993 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO24 of instance: flexio2"]
4994 pub const ALT4: u32 = 0x04;
4995 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO24 of instance: gpio2"]
4996 pub const ALT5: u32 = 0x05;
4997 #[doc = "Select mux mode: ALT6 mux port: FLEXCAN2_TX of instance: flexcan2"]
4998 pub const ALT6: u32 = 0x06;
4999 #[doc = "Select mux mode: ALT8 mux port: GPT1_COMPARE2 of instance: gpt1"]
5000 pub const ALT8: u32 = 0x08;
5001 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO24 of instance: flexio3"]
5002 pub const ALT9: u32 = 0x09;
5003 }
5004 }
5005 #[doc = "Software Input On Field."]
5006 pub mod SION {
5007 pub const offset: u32 = 4;
5008 pub const mask: u32 = 0x01 << offset;
5009 pub mod R {}
5010 pub mod W {}
5011 pub mod RW {
5012 #[doc = "Input Path is determined by functionality"]
5013 pub const DISABLED: u32 = 0;
5014 #[doc = "Force input path of pad GPIO_B1_08"]
5015 pub const ENABLED: u32 = 0x01;
5016 }
5017 }
5018}
5019#[doc = "SW_MUX_CTL_PAD_GPIO_B1_09 SW MUX Control Register"]
5020pub mod SW_MUX_CTL_PAD_GPIO_B1_09 {
5021 #[doc = "MUX Mode Select Field."]
5022 pub mod MUX_MODE {
5023 pub const offset: u32 = 0;
5024 pub const mask: u32 = 0x0f << offset;
5025 pub mod R {}
5026 pub mod W {}
5027 pub mod RW {
5028 #[doc = "Select mux mode: ALT0 mux port: LCD_DATA21 of instance: lcdif"]
5029 pub const ALT0: u32 = 0;
5030 #[doc = "Select mux mode: ALT1 mux port: QTIMER2_TIMER3 of instance: qtimer2"]
5031 pub const ALT1: u32 = 0x01;
5032 #[doc = "Select mux mode: ALT2 mux port: CSI_DATA10 of instance: csi"]
5033 pub const ALT2: u32 = 0x02;
5034 #[doc = "Select mux mode: ALT3 mux port: ENET_TX_EN of instance: enet"]
5035 pub const ALT3: u32 = 0x03;
5036 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO25 of instance: flexio2"]
5037 pub const ALT4: u32 = 0x04;
5038 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO25 of instance: gpio2"]
5039 pub const ALT5: u32 = 0x05;
5040 #[doc = "Select mux mode: ALT6 mux port: FLEXCAN2_RX of instance: flexcan2"]
5041 pub const ALT6: u32 = 0x06;
5042 #[doc = "Select mux mode: ALT8 mux port: GPT1_COMPARE3 of instance: gpt1"]
5043 pub const ALT8: u32 = 0x08;
5044 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO25 of instance: flexio3"]
5045 pub const ALT9: u32 = 0x09;
5046 }
5047 }
5048 #[doc = "Software Input On Field."]
5049 pub mod SION {
5050 pub const offset: u32 = 4;
5051 pub const mask: u32 = 0x01 << offset;
5052 pub mod R {}
5053 pub mod W {}
5054 pub mod RW {
5055 #[doc = "Input Path is determined by functionality"]
5056 pub const DISABLED: u32 = 0;
5057 #[doc = "Force input path of pad GPIO_B1_09"]
5058 pub const ENABLED: u32 = 0x01;
5059 }
5060 }
5061}
5062#[doc = "SW_MUX_CTL_PAD_GPIO_B1_10 SW MUX Control Register"]
5063pub mod SW_MUX_CTL_PAD_GPIO_B1_10 {
5064 #[doc = "MUX Mode Select Field."]
5065 pub mod MUX_MODE {
5066 pub const offset: u32 = 0;
5067 pub const mask: u32 = 0x0f << offset;
5068 pub mod R {}
5069 pub mod W {}
5070 pub mod RW {
5071 #[doc = "Select mux mode: ALT0 mux port: LCD_DATA22 of instance: lcdif"]
5072 pub const ALT0: u32 = 0;
5073 #[doc = "Select mux mode: ALT1 mux port: QTIMER3_TIMER3 of instance: qtimer3"]
5074 pub const ALT1: u32 = 0x01;
5075 #[doc = "Select mux mode: ALT2 mux port: CSI_DATA00 of instance: csi"]
5076 pub const ALT2: u32 = 0x02;
5077 #[doc = "Select mux mode: ALT3 mux port: ENET_TX_CLK of instance: enet"]
5078 pub const ALT3: u32 = 0x03;
5079 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO26 of instance: flexio2"]
5080 pub const ALT4: u32 = 0x04;
5081 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO26 of instance: gpio2"]
5082 pub const ALT5: u32 = 0x05;
5083 #[doc = "Select mux mode: ALT6 mux port: ENET_REF_CLK of instance: enet"]
5084 pub const ALT6: u32 = 0x06;
5085 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO26 of instance: flexio3"]
5086 pub const ALT9: u32 = 0x09;
5087 }
5088 }
5089 #[doc = "Software Input On Field."]
5090 pub mod SION {
5091 pub const offset: u32 = 4;
5092 pub const mask: u32 = 0x01 << offset;
5093 pub mod R {}
5094 pub mod W {}
5095 pub mod RW {
5096 #[doc = "Input Path is determined by functionality"]
5097 pub const DISABLED: u32 = 0;
5098 #[doc = "Force input path of pad GPIO_B1_10"]
5099 pub const ENABLED: u32 = 0x01;
5100 }
5101 }
5102}
5103#[doc = "SW_MUX_CTL_PAD_GPIO_B1_11 SW MUX Control Register"]
5104pub mod SW_MUX_CTL_PAD_GPIO_B1_11 {
5105 #[doc = "MUX Mode Select Field."]
5106 pub mod MUX_MODE {
5107 pub const offset: u32 = 0;
5108 pub const mask: u32 = 0x0f << offset;
5109 pub mod R {}
5110 pub mod W {}
5111 pub mod RW {
5112 #[doc = "Select mux mode: ALT0 mux port: LCD_DATA23 of instance: lcdif"]
5113 pub const ALT0: u32 = 0;
5114 #[doc = "Select mux mode: ALT1 mux port: QTIMER4_TIMER3 of instance: qtimer4"]
5115 pub const ALT1: u32 = 0x01;
5116 #[doc = "Select mux mode: ALT2 mux port: CSI_DATA01 of instance: csi"]
5117 pub const ALT2: u32 = 0x02;
5118 #[doc = "Select mux mode: ALT3 mux port: ENET_RX_ER of instance: enet"]
5119 pub const ALT3: u32 = 0x03;
5120 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO27 of instance: flexio2"]
5121 pub const ALT4: u32 = 0x04;
5122 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO27 of instance: gpio2"]
5123 pub const ALT5: u32 = 0x05;
5124 #[doc = "Select mux mode: ALT6 mux port: LPSPI4_PCS3 of instance: lpspi4"]
5125 pub const ALT6: u32 = 0x06;
5126 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO27 of instance: flexio3"]
5127 pub const ALT9: u32 = 0x09;
5128 }
5129 }
5130 #[doc = "Software Input On Field."]
5131 pub mod SION {
5132 pub const offset: u32 = 4;
5133 pub const mask: u32 = 0x01 << offset;
5134 pub mod R {}
5135 pub mod W {}
5136 pub mod RW {
5137 #[doc = "Input Path is determined by functionality"]
5138 pub const DISABLED: u32 = 0;
5139 #[doc = "Force input path of pad GPIO_B1_11"]
5140 pub const ENABLED: u32 = 0x01;
5141 }
5142 }
5143}
5144#[doc = "SW_MUX_CTL_PAD_GPIO_B1_12 SW MUX Control Register"]
5145pub mod SW_MUX_CTL_PAD_GPIO_B1_12 {
5146 #[doc = "MUX Mode Select Field."]
5147 pub mod MUX_MODE {
5148 pub const offset: u32 = 0;
5149 pub const mask: u32 = 0x0f << offset;
5150 pub mod R {}
5151 pub mod W {}
5152 pub mod RW {
5153 #[doc = "Select mux mode: ALT1 mux port: LPUART5_TX of instance: lpuart5"]
5154 pub const ALT1: u32 = 0x01;
5155 #[doc = "Select mux mode: ALT2 mux port: CSI_PIXCLK of instance: csi"]
5156 pub const ALT2: u32 = 0x02;
5157 #[doc = "Select mux mode: ALT3 mux port: ENET_1588_EVENT0_IN of instance: enet"]
5158 pub const ALT3: u32 = 0x03;
5159 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO28 of instance: flexio2"]
5160 pub const ALT4: u32 = 0x04;
5161 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO28 of instance: gpio2"]
5162 pub const ALT5: u32 = 0x05;
5163 #[doc = "Select mux mode: ALT6 mux port: USDHC1_CD_B of instance: usdhc1"]
5164 pub const ALT6: u32 = 0x06;
5165 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO28 of instance: flexio3"]
5166 pub const ALT9: u32 = 0x09;
5167 }
5168 }
5169 #[doc = "Software Input On Field."]
5170 pub mod SION {
5171 pub const offset: u32 = 4;
5172 pub const mask: u32 = 0x01 << offset;
5173 pub mod R {}
5174 pub mod W {}
5175 pub mod RW {
5176 #[doc = "Input Path is determined by functionality"]
5177 pub const DISABLED: u32 = 0;
5178 #[doc = "Force input path of pad GPIO_B1_12"]
5179 pub const ENABLED: u32 = 0x01;
5180 }
5181 }
5182}
5183#[doc = "SW_MUX_CTL_PAD_GPIO_B1_13 SW MUX Control Register"]
5184pub mod SW_MUX_CTL_PAD_GPIO_B1_13 {
5185 #[doc = "MUX Mode Select Field."]
5186 pub mod MUX_MODE {
5187 pub const offset: u32 = 0;
5188 pub const mask: u32 = 0x0f << offset;
5189 pub mod R {}
5190 pub mod W {}
5191 pub mod RW {
5192 #[doc = "Select mux mode: ALT0 mux port: WDOG1_B of instance: wdog1"]
5193 pub const ALT0: u32 = 0;
5194 #[doc = "Select mux mode: ALT1 mux port: LPUART5_RX of instance: lpuart5"]
5195 pub const ALT1: u32 = 0x01;
5196 #[doc = "Select mux mode: ALT2 mux port: CSI_VSYNC of instance: csi"]
5197 pub const ALT2: u32 = 0x02;
5198 #[doc = "Select mux mode: ALT3 mux port: ENET_1588_EVENT0_OUT of instance: enet"]
5199 pub const ALT3: u32 = 0x03;
5200 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO29 of instance: flexio2"]
5201 pub const ALT4: u32 = 0x04;
5202 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO29 of instance: gpio2"]
5203 pub const ALT5: u32 = 0x05;
5204 #[doc = "Select mux mode: ALT6 mux port: USDHC1_WP of instance: usdhc1"]
5205 pub const ALT6: u32 = 0x06;
5206 #[doc = "Select mux mode: ALT8 mux port: SEMC_DQS4 of instance: semc"]
5207 pub const ALT8: u32 = 0x08;
5208 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO29 of instance: flexio3"]
5209 pub const ALT9: u32 = 0x09;
5210 }
5211 }
5212 #[doc = "Software Input On Field."]
5213 pub mod SION {
5214 pub const offset: u32 = 4;
5215 pub const mask: u32 = 0x01 << offset;
5216 pub mod R {}
5217 pub mod W {}
5218 pub mod RW {
5219 #[doc = "Input Path is determined by functionality"]
5220 pub const DISABLED: u32 = 0;
5221 #[doc = "Force input path of pad GPIO_B1_13"]
5222 pub const ENABLED: u32 = 0x01;
5223 }
5224 }
5225}
5226#[doc = "SW_MUX_CTL_PAD_GPIO_B1_14 SW MUX Control Register"]
5227pub mod SW_MUX_CTL_PAD_GPIO_B1_14 {
5228 #[doc = "MUX Mode Select Field."]
5229 pub mod MUX_MODE {
5230 pub const offset: u32 = 0;
5231 pub const mask: u32 = 0x0f << offset;
5232 pub mod R {}
5233 pub mod W {}
5234 pub mod RW {
5235 #[doc = "Select mux mode: ALT0 mux port: ENET_MDC of instance: enet"]
5236 pub const ALT0: u32 = 0;
5237 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM4_PWMA02 of instance: flexpwm4"]
5238 pub const ALT1: u32 = 0x01;
5239 #[doc = "Select mux mode: ALT2 mux port: CSI_HSYNC of instance: csi"]
5240 pub const ALT2: u32 = 0x02;
5241 #[doc = "Select mux mode: ALT3 mux port: XBAR1_IN02 of instance: xbar1"]
5242 pub const ALT3: u32 = 0x03;
5243 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO30 of instance: flexio2"]
5244 pub const ALT4: u32 = 0x04;
5245 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO30 of instance: gpio2"]
5246 pub const ALT5: u32 = 0x05;
5247 #[doc = "Select mux mode: ALT6 mux port: USDHC1_VSELECT of instance: usdhc1"]
5248 pub const ALT6: u32 = 0x06;
5249 #[doc = "Select mux mode: ALT8 mux port: ENET2_TDATA00 of instance: enet2"]
5250 pub const ALT8: u32 = 0x08;
5251 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO30 of instance: flexio3"]
5252 pub const ALT9: u32 = 0x09;
5253 }
5254 }
5255 #[doc = "Software Input On Field."]
5256 pub mod SION {
5257 pub const offset: u32 = 4;
5258 pub const mask: u32 = 0x01 << offset;
5259 pub mod R {}
5260 pub mod W {}
5261 pub mod RW {
5262 #[doc = "Input Path is determined by functionality"]
5263 pub const DISABLED: u32 = 0;
5264 #[doc = "Force input path of pad GPIO_B1_14"]
5265 pub const ENABLED: u32 = 0x01;
5266 }
5267 }
5268}
5269#[doc = "SW_MUX_CTL_PAD_GPIO_B1_15 SW MUX Control Register"]
5270pub mod SW_MUX_CTL_PAD_GPIO_B1_15 {
5271 #[doc = "MUX Mode Select Field."]
5272 pub mod MUX_MODE {
5273 pub const offset: u32 = 0;
5274 pub const mask: u32 = 0x0f << offset;
5275 pub mod R {}
5276 pub mod W {}
5277 pub mod RW {
5278 #[doc = "Select mux mode: ALT0 mux port: ENET_MDIO of instance: enet"]
5279 pub const ALT0: u32 = 0;
5280 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM4_PWMA03 of instance: flexpwm4"]
5281 pub const ALT1: u32 = 0x01;
5282 #[doc = "Select mux mode: ALT2 mux port: CSI_MCLK of instance: csi"]
5283 pub const ALT2: u32 = 0x02;
5284 #[doc = "Select mux mode: ALT3 mux port: XBAR1_IN03 of instance: xbar1"]
5285 pub const ALT3: u32 = 0x03;
5286 #[doc = "Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO31 of instance: flexio2"]
5287 pub const ALT4: u32 = 0x04;
5288 #[doc = "Select mux mode: ALT5 mux port: GPIO2_IO31 of instance: gpio2"]
5289 pub const ALT5: u32 = 0x05;
5290 #[doc = "Select mux mode: ALT6 mux port: USDHC1_RESET_B of instance: usdhc1"]
5291 pub const ALT6: u32 = 0x06;
5292 #[doc = "Select mux mode: ALT8 mux port: ENET2_TDATA01 of instance: enet2"]
5293 pub const ALT8: u32 = 0x08;
5294 #[doc = "Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO31 of instance: flexio3"]
5295 pub const ALT9: u32 = 0x09;
5296 }
5297 }
5298 #[doc = "Software Input On Field."]
5299 pub mod SION {
5300 pub const offset: u32 = 4;
5301 pub const mask: u32 = 0x01 << offset;
5302 pub mod R {}
5303 pub mod W {}
5304 pub mod RW {
5305 #[doc = "Input Path is determined by functionality"]
5306 pub const DISABLED: u32 = 0;
5307 #[doc = "Force input path of pad GPIO_B1_15"]
5308 pub const ENABLED: u32 = 0x01;
5309 }
5310 }
5311}
5312#[doc = "SW_MUX_CTL_PAD_GPIO_SD_B0_00 SW MUX Control Register"]
5313pub mod SW_MUX_CTL_PAD_GPIO_SD_B0_00 {
5314 #[doc = "MUX Mode Select Field."]
5315 pub mod MUX_MODE {
5316 pub const offset: u32 = 0;
5317 pub const mask: u32 = 0x0f << offset;
5318 pub mod R {}
5319 pub mod W {}
5320 pub mod RW {
5321 #[doc = "Select mux mode: ALT0 mux port: USDHC1_CMD of instance: usdhc1"]
5322 pub const ALT0: u32 = 0;
5323 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM1_PWMA00 of instance: flexpwm1"]
5324 pub const ALT1: u32 = 0x01;
5325 #[doc = "Select mux mode: ALT2 mux port: LPI2C3_SCL of instance: lpi2c3"]
5326 pub const ALT2: u32 = 0x02;
5327 #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT04 of instance: xbar1"]
5328 pub const ALT3: u32 = 0x03;
5329 #[doc = "Select mux mode: ALT4 mux port: LPSPI1_SCK of instance: lpspi1"]
5330 pub const ALT4: u32 = 0x04;
5331 #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO12 of instance: gpio3"]
5332 pub const ALT5: u32 = 0x05;
5333 #[doc = "Select mux mode: ALT6 mux port: FLEXSPIA_SS1_B of instance: flexspi"]
5334 pub const ALT6: u32 = 0x06;
5335 #[doc = "Select mux mode: ALT8 mux port: ENET2_TX_EN of instance: enet2"]
5336 pub const ALT8: u32 = 0x08;
5337 #[doc = "Select mux mode: ALT9 mux port: SEMC_DQS4 of instance: semc"]
5338 pub const ALT9: u32 = 0x09;
5339 }
5340 }
5341 #[doc = "Software Input On Field."]
5342 pub mod SION {
5343 pub const offset: u32 = 4;
5344 pub const mask: u32 = 0x01 << offset;
5345 pub mod R {}
5346 pub mod W {}
5347 pub mod RW {
5348 #[doc = "Input Path is determined by functionality"]
5349 pub const DISABLED: u32 = 0;
5350 #[doc = "Force input path of pad GPIO_SD_B0_00"]
5351 pub const ENABLED: u32 = 0x01;
5352 }
5353 }
5354}
5355#[doc = "SW_MUX_CTL_PAD_GPIO_SD_B0_01 SW MUX Control Register"]
5356pub mod SW_MUX_CTL_PAD_GPIO_SD_B0_01 {
5357 #[doc = "MUX Mode Select Field."]
5358 pub mod MUX_MODE {
5359 pub const offset: u32 = 0;
5360 pub const mask: u32 = 0x0f << offset;
5361 pub mod R {}
5362 pub mod W {}
5363 pub mod RW {
5364 #[doc = "Select mux mode: ALT0 mux port: USDHC1_CLK of instance: usdhc1"]
5365 pub const ALT0: u32 = 0;
5366 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM1_PWMB00 of instance: flexpwm1"]
5367 pub const ALT1: u32 = 0x01;
5368 #[doc = "Select mux mode: ALT2 mux port: LPI2C3_SDA of instance: lpi2c3"]
5369 pub const ALT2: u32 = 0x02;
5370 #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT05 of instance: xbar1"]
5371 pub const ALT3: u32 = 0x03;
5372 #[doc = "Select mux mode: ALT4 mux port: LPSPI1_PCS0 of instance: lpspi1"]
5373 pub const ALT4: u32 = 0x04;
5374 #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO13 of instance: gpio3"]
5375 pub const ALT5: u32 = 0x05;
5376 #[doc = "Select mux mode: ALT6 mux port: FLEXSPIB_SS1_B of instance: flexspi"]
5377 pub const ALT6: u32 = 0x06;
5378 #[doc = "Select mux mode: ALT8 mux port: ENET2_TX_CLK of instance: enet2"]
5379 pub const ALT8: u32 = 0x08;
5380 #[doc = "Select mux mode: ALT9 mux port: ENET2_REF_CLK2 of instance: enet2"]
5381 pub const ALT9: u32 = 0x09;
5382 }
5383 }
5384 #[doc = "Software Input On Field."]
5385 pub mod SION {
5386 pub const offset: u32 = 4;
5387 pub const mask: u32 = 0x01 << offset;
5388 pub mod R {}
5389 pub mod W {}
5390 pub mod RW {
5391 #[doc = "Input Path is determined by functionality"]
5392 pub const DISABLED: u32 = 0;
5393 #[doc = "Force input path of pad GPIO_SD_B0_01"]
5394 pub const ENABLED: u32 = 0x01;
5395 }
5396 }
5397}
5398#[doc = "SW_MUX_CTL_PAD_GPIO_SD_B0_02 SW MUX Control Register"]
5399pub mod SW_MUX_CTL_PAD_GPIO_SD_B0_02 {
5400 #[doc = "MUX Mode Select Field."]
5401 pub mod MUX_MODE {
5402 pub const offset: u32 = 0;
5403 pub const mask: u32 = 0x0f << offset;
5404 pub mod R {}
5405 pub mod W {}
5406 pub mod RW {
5407 #[doc = "Select mux mode: ALT0 mux port: USDHC1_DATA0 of instance: usdhc1"]
5408 pub const ALT0: u32 = 0;
5409 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM1_PWMA01 of instance: flexpwm1"]
5410 pub const ALT1: u32 = 0x01;
5411 #[doc = "Select mux mode: ALT2 mux port: LPUART8_CTS_B of instance: lpuart8"]
5412 pub const ALT2: u32 = 0x02;
5413 #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT06 of instance: xbar1"]
5414 pub const ALT3: u32 = 0x03;
5415 #[doc = "Select mux mode: ALT4 mux port: LPSPI1_SDO of instance: lpspi1"]
5416 pub const ALT4: u32 = 0x04;
5417 #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO14 of instance: gpio3"]
5418 pub const ALT5: u32 = 0x05;
5419 #[doc = "Select mux mode: ALT8 mux port: ENET2_RX_ER of instance: enet2"]
5420 pub const ALT8: u32 = 0x08;
5421 #[doc = "Select mux mode: ALT9 mux port: SEMC_CLK5 of instance: semc"]
5422 pub const ALT9: u32 = 0x09;
5423 }
5424 }
5425 #[doc = "Software Input On Field."]
5426 pub mod SION {
5427 pub const offset: u32 = 4;
5428 pub const mask: u32 = 0x01 << offset;
5429 pub mod R {}
5430 pub mod W {}
5431 pub mod RW {
5432 #[doc = "Input Path is determined by functionality"]
5433 pub const DISABLED: u32 = 0;
5434 #[doc = "Force input path of pad GPIO_SD_B0_02"]
5435 pub const ENABLED: u32 = 0x01;
5436 }
5437 }
5438}
5439#[doc = "SW_MUX_CTL_PAD_GPIO_SD_B0_03 SW MUX Control Register"]
5440pub mod SW_MUX_CTL_PAD_GPIO_SD_B0_03 {
5441 #[doc = "MUX Mode Select Field."]
5442 pub mod MUX_MODE {
5443 pub const offset: u32 = 0;
5444 pub const mask: u32 = 0x0f << offset;
5445 pub mod R {}
5446 pub mod W {}
5447 pub mod RW {
5448 #[doc = "Select mux mode: ALT0 mux port: USDHC1_DATA1 of instance: usdhc1"]
5449 pub const ALT0: u32 = 0;
5450 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM1_PWMB01 of instance: flexpwm1"]
5451 pub const ALT1: u32 = 0x01;
5452 #[doc = "Select mux mode: ALT2 mux port: LPUART8_RTS_B of instance: lpuart8"]
5453 pub const ALT2: u32 = 0x02;
5454 #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT07 of instance: xbar1"]
5455 pub const ALT3: u32 = 0x03;
5456 #[doc = "Select mux mode: ALT4 mux port: LPSPI1_SDI of instance: lpspi1"]
5457 pub const ALT4: u32 = 0x04;
5458 #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO15 of instance: gpio3"]
5459 pub const ALT5: u32 = 0x05;
5460 #[doc = "Select mux mode: ALT8 mux port: ENET2_RDATA00 of instance: enet2"]
5461 pub const ALT8: u32 = 0x08;
5462 #[doc = "Select mux mode: ALT9 mux port: SEMC_CLK6 of instance: semc"]
5463 pub const ALT9: u32 = 0x09;
5464 }
5465 }
5466 #[doc = "Software Input On Field."]
5467 pub mod SION {
5468 pub const offset: u32 = 4;
5469 pub const mask: u32 = 0x01 << offset;
5470 pub mod R {}
5471 pub mod W {}
5472 pub mod RW {
5473 #[doc = "Input Path is determined by functionality"]
5474 pub const DISABLED: u32 = 0;
5475 #[doc = "Force input path of pad GPIO_SD_B0_03"]
5476 pub const ENABLED: u32 = 0x01;
5477 }
5478 }
5479}
5480#[doc = "SW_MUX_CTL_PAD_GPIO_SD_B0_04 SW MUX Control Register"]
5481pub mod SW_MUX_CTL_PAD_GPIO_SD_B0_04 {
5482 #[doc = "MUX Mode Select Field."]
5483 pub mod MUX_MODE {
5484 pub const offset: u32 = 0;
5485 pub const mask: u32 = 0x0f << offset;
5486 pub mod R {}
5487 pub mod W {}
5488 pub mod RW {
5489 #[doc = "Select mux mode: ALT0 mux port: USDHC1_DATA2 of instance: usdhc1"]
5490 pub const ALT0: u32 = 0;
5491 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM1_PWMA02 of instance: flexpwm1"]
5492 pub const ALT1: u32 = 0x01;
5493 #[doc = "Select mux mode: ALT2 mux port: LPUART8_TX of instance: lpuart8"]
5494 pub const ALT2: u32 = 0x02;
5495 #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT08 of instance: xbar1"]
5496 pub const ALT3: u32 = 0x03;
5497 #[doc = "Select mux mode: ALT4 mux port: FLEXSPIB_SS0_B of instance: flexspi"]
5498 pub const ALT4: u32 = 0x04;
5499 #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO16 of instance: gpio3"]
5500 pub const ALT5: u32 = 0x05;
5501 #[doc = "Select mux mode: ALT6 mux port: CCM_CLKO1 of instance: ccm"]
5502 pub const ALT6: u32 = 0x06;
5503 #[doc = "Select mux mode: ALT8 mux port: ENET2_RDATA01 of instance: enet2"]
5504 pub const ALT8: u32 = 0x08;
5505 }
5506 }
5507 #[doc = "Software Input On Field."]
5508 pub mod SION {
5509 pub const offset: u32 = 4;
5510 pub const mask: u32 = 0x01 << offset;
5511 pub mod R {}
5512 pub mod W {}
5513 pub mod RW {
5514 #[doc = "Input Path is determined by functionality"]
5515 pub const DISABLED: u32 = 0;
5516 #[doc = "Force input path of pad GPIO_SD_B0_04"]
5517 pub const ENABLED: u32 = 0x01;
5518 }
5519 }
5520}
5521#[doc = "SW_MUX_CTL_PAD_GPIO_SD_B0_05 SW MUX Control Register"]
5522pub mod SW_MUX_CTL_PAD_GPIO_SD_B0_05 {
5523 #[doc = "MUX Mode Select Field."]
5524 pub mod MUX_MODE {
5525 pub const offset: u32 = 0;
5526 pub const mask: u32 = 0x0f << offset;
5527 pub mod R {}
5528 pub mod W {}
5529 pub mod RW {
5530 #[doc = "Select mux mode: ALT0 mux port: USDHC1_DATA3 of instance: usdhc1"]
5531 pub const ALT0: u32 = 0;
5532 #[doc = "Select mux mode: ALT1 mux port: FLEXPWM1_PWMB02 of instance: flexpwm1"]
5533 pub const ALT1: u32 = 0x01;
5534 #[doc = "Select mux mode: ALT2 mux port: LPUART8_RX of instance: lpuart8"]
5535 pub const ALT2: u32 = 0x02;
5536 #[doc = "Select mux mode: ALT3 mux port: XBAR1_INOUT09 of instance: xbar1"]
5537 pub const ALT3: u32 = 0x03;
5538 #[doc = "Select mux mode: ALT4 mux port: FLEXSPIB_DQS of instance: flexspi"]
5539 pub const ALT4: u32 = 0x04;
5540 #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO17 of instance: gpio3"]
5541 pub const ALT5: u32 = 0x05;
5542 #[doc = "Select mux mode: ALT6 mux port: CCM_CLKO2 of instance: ccm"]
5543 pub const ALT6: u32 = 0x06;
5544 #[doc = "Select mux mode: ALT8 mux port: ENET2_RX_EN of instance: enet2"]
5545 pub const ALT8: u32 = 0x08;
5546 }
5547 }
5548 #[doc = "Software Input On Field."]
5549 pub mod SION {
5550 pub const offset: u32 = 4;
5551 pub const mask: u32 = 0x01 << offset;
5552 pub mod R {}
5553 pub mod W {}
5554 pub mod RW {
5555 #[doc = "Input Path is determined by functionality"]
5556 pub const DISABLED: u32 = 0;
5557 #[doc = "Force input path of pad GPIO_SD_B0_05"]
5558 pub const ENABLED: u32 = 0x01;
5559 }
5560 }
5561}
5562#[doc = "SW_MUX_CTL_PAD_GPIO_SD_B1_00 SW MUX Control Register"]
5563pub mod SW_MUX_CTL_PAD_GPIO_SD_B1_00 {
5564 #[doc = "MUX Mode Select Field."]
5565 pub mod MUX_MODE {
5566 pub const offset: u32 = 0;
5567 pub const mask: u32 = 0x0f << offset;
5568 pub mod R {}
5569 pub mod W {}
5570 pub mod RW {
5571 #[doc = "Select mux mode: ALT0 mux port: USDHC2_DATA3 of instance: usdhc2"]
5572 pub const ALT0: u32 = 0;
5573 #[doc = "Select mux mode: ALT1 mux port: FLEXSPIB_DATA03 of instance: flexspi"]
5574 pub const ALT1: u32 = 0x01;
5575 #[doc = "Select mux mode: ALT2 mux port: FLEXPWM1_PWMA03 of instance: flexpwm1"]
5576 pub const ALT2: u32 = 0x02;
5577 #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_DATA03 of instance: sai1"]
5578 pub const ALT3: u32 = 0x03;
5579 #[doc = "Select mux mode: ALT4 mux port: LPUART4_TX of instance: lpuart4"]
5580 pub const ALT4: u32 = 0x04;
5581 #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO00 of instance: gpio3"]
5582 pub const ALT5: u32 = 0x05;
5583 #[doc = "Select mux mode: ALT8 mux port: SAI3_RX_DATA of instance: sai3"]
5584 pub const ALT8: u32 = 0x08;
5585 }
5586 }
5587 #[doc = "Software Input On Field."]
5588 pub mod SION {
5589 pub const offset: u32 = 4;
5590 pub const mask: u32 = 0x01 << offset;
5591 pub mod R {}
5592 pub mod W {}
5593 pub mod RW {
5594 #[doc = "Input Path is determined by functionality"]
5595 pub const DISABLED: u32 = 0;
5596 #[doc = "Force input path of pad GPIO_SD_B1_00"]
5597 pub const ENABLED: u32 = 0x01;
5598 }
5599 }
5600}
5601#[doc = "SW_MUX_CTL_PAD_GPIO_SD_B1_01 SW MUX Control Register"]
5602pub mod SW_MUX_CTL_PAD_GPIO_SD_B1_01 {
5603 #[doc = "MUX Mode Select Field."]
5604 pub mod MUX_MODE {
5605 pub const offset: u32 = 0;
5606 pub const mask: u32 = 0x0f << offset;
5607 pub mod R {}
5608 pub mod W {}
5609 pub mod RW {
5610 #[doc = "Select mux mode: ALT0 mux port: USDHC2_DATA2 of instance: usdhc2"]
5611 pub const ALT0: u32 = 0;
5612 #[doc = "Select mux mode: ALT1 mux port: FLEXSPIB_DATA02 of instance: flexspi"]
5613 pub const ALT1: u32 = 0x01;
5614 #[doc = "Select mux mode: ALT2 mux port: FLEXPWM1_PWMB03 of instance: flexpwm1"]
5615 pub const ALT2: u32 = 0x02;
5616 #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_DATA02 of instance: sai1"]
5617 pub const ALT3: u32 = 0x03;
5618 #[doc = "Select mux mode: ALT4 mux port: LPUART4_RX of instance: lpuart4"]
5619 pub const ALT4: u32 = 0x04;
5620 #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO01 of instance: gpio3"]
5621 pub const ALT5: u32 = 0x05;
5622 #[doc = "Select mux mode: ALT8 mux port: SAI3_TX_DATA of instance: sai3"]
5623 pub const ALT8: u32 = 0x08;
5624 }
5625 }
5626 #[doc = "Software Input On Field."]
5627 pub mod SION {
5628 pub const offset: u32 = 4;
5629 pub const mask: u32 = 0x01 << offset;
5630 pub mod R {}
5631 pub mod W {}
5632 pub mod RW {
5633 #[doc = "Input Path is determined by functionality"]
5634 pub const DISABLED: u32 = 0;
5635 #[doc = "Force input path of pad GPIO_SD_B1_01"]
5636 pub const ENABLED: u32 = 0x01;
5637 }
5638 }
5639}
5640#[doc = "SW_MUX_CTL_PAD_GPIO_SD_B1_02 SW MUX Control Register"]
5641pub mod SW_MUX_CTL_PAD_GPIO_SD_B1_02 {
5642 #[doc = "MUX Mode Select Field."]
5643 pub mod MUX_MODE {
5644 pub const offset: u32 = 0;
5645 pub const mask: u32 = 0x0f << offset;
5646 pub mod R {}
5647 pub mod W {}
5648 pub mod RW {
5649 #[doc = "Select mux mode: ALT0 mux port: USDHC2_DATA1 of instance: usdhc2"]
5650 pub const ALT0: u32 = 0;
5651 #[doc = "Select mux mode: ALT1 mux port: FLEXSPIB_DATA01 of instance: flexspi"]
5652 pub const ALT1: u32 = 0x01;
5653 #[doc = "Select mux mode: ALT2 mux port: FLEXPWM2_PWMA03 of instance: flexpwm2"]
5654 pub const ALT2: u32 = 0x02;
5655 #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_DATA01 of instance: sai1"]
5656 pub const ALT3: u32 = 0x03;
5657 #[doc = "Select mux mode: ALT4 mux port: FLEXCAN1_TX of instance: flexcan1"]
5658 pub const ALT4: u32 = 0x04;
5659 #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO02 of instance: gpio3"]
5660 pub const ALT5: u32 = 0x05;
5661 #[doc = "Select mux mode: ALT6 mux port: CCM_WAIT of instance: ccm"]
5662 pub const ALT6: u32 = 0x06;
5663 #[doc = "Select mux mode: ALT8 mux port: SAI3_TX_SYNC of instance: sai3"]
5664 pub const ALT8: u32 = 0x08;
5665 }
5666 }
5667 #[doc = "Software Input On Field."]
5668 pub mod SION {
5669 pub const offset: u32 = 4;
5670 pub const mask: u32 = 0x01 << offset;
5671 pub mod R {}
5672 pub mod W {}
5673 pub mod RW {
5674 #[doc = "Input Path is determined by functionality"]
5675 pub const DISABLED: u32 = 0;
5676 #[doc = "Force input path of pad GPIO_SD_B1_02"]
5677 pub const ENABLED: u32 = 0x01;
5678 }
5679 }
5680}
5681#[doc = "SW_MUX_CTL_PAD_GPIO_SD_B1_03 SW MUX Control Register"]
5682pub mod SW_MUX_CTL_PAD_GPIO_SD_B1_03 {
5683 #[doc = "MUX Mode Select Field."]
5684 pub mod MUX_MODE {
5685 pub const offset: u32 = 0;
5686 pub const mask: u32 = 0x0f << offset;
5687 pub mod R {}
5688 pub mod W {}
5689 pub mod RW {
5690 #[doc = "Select mux mode: ALT0 mux port: USDHC2_DATA0 of instance: usdhc2"]
5691 pub const ALT0: u32 = 0;
5692 #[doc = "Select mux mode: ALT1 mux port: FLEXSPIB_DATA00 of instance: flexspi"]
5693 pub const ALT1: u32 = 0x01;
5694 #[doc = "Select mux mode: ALT2 mux port: FLEXPWM2_PWMB03 of instance: flexpwm2"]
5695 pub const ALT2: u32 = 0x02;
5696 #[doc = "Select mux mode: ALT3 mux port: SAI1_MCLK of instance: sai1"]
5697 pub const ALT3: u32 = 0x03;
5698 #[doc = "Select mux mode: ALT4 mux port: FLEXCAN1_RX of instance: flexcan1"]
5699 pub const ALT4: u32 = 0x04;
5700 #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO03 of instance: gpio3"]
5701 pub const ALT5: u32 = 0x05;
5702 #[doc = "Select mux mode: ALT6 mux port: CCM_PMIC_READY of instance: ccm"]
5703 pub const ALT6: u32 = 0x06;
5704 #[doc = "Select mux mode: ALT8 mux port: SAI3_TX_BCLK of instance: sai3"]
5705 pub const ALT8: u32 = 0x08;
5706 }
5707 }
5708 #[doc = "Software Input On Field."]
5709 pub mod SION {
5710 pub const offset: u32 = 4;
5711 pub const mask: u32 = 0x01 << offset;
5712 pub mod R {}
5713 pub mod W {}
5714 pub mod RW {
5715 #[doc = "Input Path is determined by functionality"]
5716 pub const DISABLED: u32 = 0;
5717 #[doc = "Force input path of pad GPIO_SD_B1_03"]
5718 pub const ENABLED: u32 = 0x01;
5719 }
5720 }
5721}
5722#[doc = "SW_MUX_CTL_PAD_GPIO_SD_B1_04 SW MUX Control Register"]
5723pub mod SW_MUX_CTL_PAD_GPIO_SD_B1_04 {
5724 #[doc = "MUX Mode Select Field."]
5725 pub mod MUX_MODE {
5726 pub const offset: u32 = 0;
5727 pub const mask: u32 = 0x0f << offset;
5728 pub mod R {}
5729 pub mod W {}
5730 pub mod RW {
5731 #[doc = "Select mux mode: ALT0 mux port: USDHC2_CLK of instance: usdhc2"]
5732 pub const ALT0: u32 = 0;
5733 #[doc = "Select mux mode: ALT1 mux port: FLEXSPIB_SCLK of instance: flexspi"]
5734 pub const ALT1: u32 = 0x01;
5735 #[doc = "Select mux mode: ALT2 mux port: LPI2C1_SCL of instance: lpi2c1"]
5736 pub const ALT2: u32 = 0x02;
5737 #[doc = "Select mux mode: ALT3 mux port: SAI1_RX_SYNC of instance: sai1"]
5738 pub const ALT3: u32 = 0x03;
5739 #[doc = "Select mux mode: ALT4 mux port: FLEXSPIA_SS1_B of instance: flexspi"]
5740 pub const ALT4: u32 = 0x04;
5741 #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO04 of instance: gpio3"]
5742 pub const ALT5: u32 = 0x05;
5743 #[doc = "Select mux mode: ALT6 mux port: CCM_STOP of instance: ccm"]
5744 pub const ALT6: u32 = 0x06;
5745 #[doc = "Select mux mode: ALT8 mux port: SAI3_MCLK of instance: sai3"]
5746 pub const ALT8: u32 = 0x08;
5747 }
5748 }
5749 #[doc = "Software Input On Field."]
5750 pub mod SION {
5751 pub const offset: u32 = 4;
5752 pub const mask: u32 = 0x01 << offset;
5753 pub mod R {}
5754 pub mod W {}
5755 pub mod RW {
5756 #[doc = "Input Path is determined by functionality"]
5757 pub const DISABLED: u32 = 0;
5758 #[doc = "Force input path of pad GPIO_SD_B1_04"]
5759 pub const ENABLED: u32 = 0x01;
5760 }
5761 }
5762}
5763#[doc = "SW_MUX_CTL_PAD_GPIO_SD_B1_05 SW MUX Control Register"]
5764pub mod SW_MUX_CTL_PAD_GPIO_SD_B1_05 {
5765 #[doc = "MUX Mode Select Field."]
5766 pub mod MUX_MODE {
5767 pub const offset: u32 = 0;
5768 pub const mask: u32 = 0x0f << offset;
5769 pub mod R {}
5770 pub mod W {}
5771 pub mod RW {
5772 #[doc = "Select mux mode: ALT0 mux port: USDHC2_CMD of instance: usdhc2"]
5773 pub const ALT0: u32 = 0;
5774 #[doc = "Select mux mode: ALT1 mux port: FLEXSPIA_DQS of instance: flexspi"]
5775 pub const ALT1: u32 = 0x01;
5776 #[doc = "Select mux mode: ALT2 mux port: LPI2C1_SDA of instance: lpi2c1"]
5777 pub const ALT2: u32 = 0x02;
5778 #[doc = "Select mux mode: ALT3 mux port: SAI1_RX_BCLK of instance: sai1"]
5779 pub const ALT3: u32 = 0x03;
5780 #[doc = "Select mux mode: ALT4 mux port: FLEXSPIB_SS0_B of instance: flexspi"]
5781 pub const ALT4: u32 = 0x04;
5782 #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO05 of instance: gpio3"]
5783 pub const ALT5: u32 = 0x05;
5784 #[doc = "Select mux mode: ALT8 mux port: SAI3_RX_SYNC of instance: sai3"]
5785 pub const ALT8: u32 = 0x08;
5786 }
5787 }
5788 #[doc = "Software Input On Field."]
5789 pub mod SION {
5790 pub const offset: u32 = 4;
5791 pub const mask: u32 = 0x01 << offset;
5792 pub mod R {}
5793 pub mod W {}
5794 pub mod RW {
5795 #[doc = "Input Path is determined by functionality"]
5796 pub const DISABLED: u32 = 0;
5797 #[doc = "Force input path of pad GPIO_SD_B1_05"]
5798 pub const ENABLED: u32 = 0x01;
5799 }
5800 }
5801}
5802#[doc = "SW_MUX_CTL_PAD_GPIO_SD_B1_06 SW MUX Control Register"]
5803pub mod SW_MUX_CTL_PAD_GPIO_SD_B1_06 {
5804 #[doc = "MUX Mode Select Field."]
5805 pub mod MUX_MODE {
5806 pub const offset: u32 = 0;
5807 pub const mask: u32 = 0x0f << offset;
5808 pub mod R {}
5809 pub mod W {}
5810 pub mod RW {
5811 #[doc = "Select mux mode: ALT0 mux port: USDHC2_RESET_B of instance: usdhc2"]
5812 pub const ALT0: u32 = 0;
5813 #[doc = "Select mux mode: ALT1 mux port: FLEXSPIA_SS0_B of instance: flexspi"]
5814 pub const ALT1: u32 = 0x01;
5815 #[doc = "Select mux mode: ALT2 mux port: LPUART7_CTS_B of instance: lpuart7"]
5816 pub const ALT2: u32 = 0x02;
5817 #[doc = "Select mux mode: ALT3 mux port: SAI1_RX_DATA00 of instance: sai1"]
5818 pub const ALT3: u32 = 0x03;
5819 #[doc = "Select mux mode: ALT4 mux port: LPSPI2_PCS0 of instance: lpspi2"]
5820 pub const ALT4: u32 = 0x04;
5821 #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO06 of instance: gpio3"]
5822 pub const ALT5: u32 = 0x05;
5823 #[doc = "Select mux mode: ALT8 mux port: SAI3_RX_BCLK of instance: sai3"]
5824 pub const ALT8: u32 = 0x08;
5825 }
5826 }
5827 #[doc = "Software Input On Field."]
5828 pub mod SION {
5829 pub const offset: u32 = 4;
5830 pub const mask: u32 = 0x01 << offset;
5831 pub mod R {}
5832 pub mod W {}
5833 pub mod RW {
5834 #[doc = "Input Path is determined by functionality"]
5835 pub const DISABLED: u32 = 0;
5836 #[doc = "Force input path of pad GPIO_SD_B1_06"]
5837 pub const ENABLED: u32 = 0x01;
5838 }
5839 }
5840}
5841#[doc = "SW_MUX_CTL_PAD_GPIO_SD_B1_07 SW MUX Control Register"]
5842pub mod SW_MUX_CTL_PAD_GPIO_SD_B1_07 {
5843 #[doc = "MUX Mode Select Field."]
5844 pub mod MUX_MODE {
5845 pub const offset: u32 = 0;
5846 pub const mask: u32 = 0x07 << offset;
5847 pub mod R {}
5848 pub mod W {}
5849 pub mod RW {
5850 #[doc = "Select mux mode: ALT0 mux port: SEMC_CSX01 of instance: semc"]
5851 pub const ALT0: u32 = 0;
5852 #[doc = "Select mux mode: ALT1 mux port: FLEXSPIA_SCLK of instance: flexspi"]
5853 pub const ALT1: u32 = 0x01;
5854 #[doc = "Select mux mode: ALT2 mux port: LPUART7_RTS_B of instance: lpuart7"]
5855 pub const ALT2: u32 = 0x02;
5856 #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_DATA00 of instance: sai1"]
5857 pub const ALT3: u32 = 0x03;
5858 #[doc = "Select mux mode: ALT4 mux port: LPSPI2_SCK of instance: lpspi2"]
5859 pub const ALT4: u32 = 0x04;
5860 #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO07 of instance: gpio3"]
5861 pub const ALT5: u32 = 0x05;
5862 }
5863 }
5864 #[doc = "Software Input On Field."]
5865 pub mod SION {
5866 pub const offset: u32 = 4;
5867 pub const mask: u32 = 0x01 << offset;
5868 pub mod R {}
5869 pub mod W {}
5870 pub mod RW {
5871 #[doc = "Input Path is determined by functionality"]
5872 pub const DISABLED: u32 = 0;
5873 #[doc = "Force input path of pad GPIO_SD_B1_07"]
5874 pub const ENABLED: u32 = 0x01;
5875 }
5876 }
5877}
5878#[doc = "SW_MUX_CTL_PAD_GPIO_SD_B1_08 SW MUX Control Register"]
5879pub mod SW_MUX_CTL_PAD_GPIO_SD_B1_08 {
5880 #[doc = "MUX Mode Select Field."]
5881 pub mod MUX_MODE {
5882 pub const offset: u32 = 0;
5883 pub const mask: u32 = 0x07 << offset;
5884 pub mod R {}
5885 pub mod W {}
5886 pub mod RW {
5887 #[doc = "Select mux mode: ALT0 mux port: USDHC2_DATA4 of instance: usdhc2"]
5888 pub const ALT0: u32 = 0;
5889 #[doc = "Select mux mode: ALT1 mux port: FLEXSPIA_DATA00 of instance: flexspi"]
5890 pub const ALT1: u32 = 0x01;
5891 #[doc = "Select mux mode: ALT2 mux port: LPUART7_TX of instance: lpuart7"]
5892 pub const ALT2: u32 = 0x02;
5893 #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_BCLK of instance: sai1"]
5894 pub const ALT3: u32 = 0x03;
5895 #[doc = "Select mux mode: ALT4 mux port: LPSPI2_SD0 of instance: lpspi2"]
5896 pub const ALT4: u32 = 0x04;
5897 #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO08 of instance: gpio3"]
5898 pub const ALT5: u32 = 0x05;
5899 #[doc = "Select mux mode: ALT6 mux port: SEMC_CSX02 of instance: semc"]
5900 pub const ALT6: u32 = 0x06;
5901 }
5902 }
5903 #[doc = "Software Input On Field."]
5904 pub mod SION {
5905 pub const offset: u32 = 4;
5906 pub const mask: u32 = 0x01 << offset;
5907 pub mod R {}
5908 pub mod W {}
5909 pub mod RW {
5910 #[doc = "Input Path is determined by functionality"]
5911 pub const DISABLED: u32 = 0;
5912 #[doc = "Force input path of pad GPIO_SD_B1_08"]
5913 pub const ENABLED: u32 = 0x01;
5914 }
5915 }
5916}
5917#[doc = "SW_MUX_CTL_PAD_GPIO_SD_B1_09 SW MUX Control Register"]
5918pub mod SW_MUX_CTL_PAD_GPIO_SD_B1_09 {
5919 #[doc = "MUX Mode Select Field."]
5920 pub mod MUX_MODE {
5921 pub const offset: u32 = 0;
5922 pub const mask: u32 = 0x07 << offset;
5923 pub mod R {}
5924 pub mod W {}
5925 pub mod RW {
5926 #[doc = "Select mux mode: ALT0 mux port: USDHC2_DATA5 of instance: usdhc2"]
5927 pub const ALT0: u32 = 0;
5928 #[doc = "Select mux mode: ALT1 mux port: FLEXSPIA_DATA01 of instance: flexspi"]
5929 pub const ALT1: u32 = 0x01;
5930 #[doc = "Select mux mode: ALT2 mux port: LPUART7_RX of instance: lpuart7"]
5931 pub const ALT2: u32 = 0x02;
5932 #[doc = "Select mux mode: ALT3 mux port: SAI1_TX_SYNC of instance: sai1"]
5933 pub const ALT3: u32 = 0x03;
5934 #[doc = "Select mux mode: ALT4 mux port: LPSPI2_SDI of instance: lpspi2"]
5935 pub const ALT4: u32 = 0x04;
5936 #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO09 of instance: gpio3"]
5937 pub const ALT5: u32 = 0x05;
5938 }
5939 }
5940 #[doc = "Software Input On Field."]
5941 pub mod SION {
5942 pub const offset: u32 = 4;
5943 pub const mask: u32 = 0x01 << offset;
5944 pub mod R {}
5945 pub mod W {}
5946 pub mod RW {
5947 #[doc = "Input Path is determined by functionality"]
5948 pub const DISABLED: u32 = 0;
5949 #[doc = "Force input path of pad GPIO_SD_B1_09"]
5950 pub const ENABLED: u32 = 0x01;
5951 }
5952 }
5953}
5954#[doc = "SW_MUX_CTL_PAD_GPIO_SD_B1_10 SW MUX Control Register"]
5955pub mod SW_MUX_CTL_PAD_GPIO_SD_B1_10 {
5956 #[doc = "MUX Mode Select Field."]
5957 pub mod MUX_MODE {
5958 pub const offset: u32 = 0;
5959 pub const mask: u32 = 0x07 << offset;
5960 pub mod R {}
5961 pub mod W {}
5962 pub mod RW {
5963 #[doc = "Select mux mode: ALT0 mux port: USDHC2_DATA6 of instance: usdhc2"]
5964 pub const ALT0: u32 = 0;
5965 #[doc = "Select mux mode: ALT1 mux port: FLEXSPIA_DATA02 of instance: flexspi"]
5966 pub const ALT1: u32 = 0x01;
5967 #[doc = "Select mux mode: ALT2 mux port: LPUART2_RX of instance: lpuart2"]
5968 pub const ALT2: u32 = 0x02;
5969 #[doc = "Select mux mode: ALT3 mux port: LPI2C2_SDA of instance: lpi2c2"]
5970 pub const ALT3: u32 = 0x03;
5971 #[doc = "Select mux mode: ALT4 mux port: LPSPI2_PCS2 of instance: lpspi2"]
5972 pub const ALT4: u32 = 0x04;
5973 #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO10 of instance: gpio3"]
5974 pub const ALT5: u32 = 0x05;
5975 }
5976 }
5977 #[doc = "Software Input On Field."]
5978 pub mod SION {
5979 pub const offset: u32 = 4;
5980 pub const mask: u32 = 0x01 << offset;
5981 pub mod R {}
5982 pub mod W {}
5983 pub mod RW {
5984 #[doc = "Input Path is determined by functionality"]
5985 pub const DISABLED: u32 = 0;
5986 #[doc = "Force input path of pad GPIO_SD_B1_10"]
5987 pub const ENABLED: u32 = 0x01;
5988 }
5989 }
5990}
5991#[doc = "SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register"]
5992pub mod SW_MUX_CTL_PAD_GPIO_SD_B1_11 {
5993 #[doc = "MUX Mode Select Field."]
5994 pub mod MUX_MODE {
5995 pub const offset: u32 = 0;
5996 pub const mask: u32 = 0x07 << offset;
5997 pub mod R {}
5998 pub mod W {}
5999 pub mod RW {
6000 #[doc = "Select mux mode: ALT0 mux port: USDHC2_DATA7 of instance: usdhc2"]
6001 pub const ALT0: u32 = 0;
6002 #[doc = "Select mux mode: ALT1 mux port: FLEXSPIA_DATA03 of instance: flexspi"]
6003 pub const ALT1: u32 = 0x01;
6004 #[doc = "Select mux mode: ALT2 mux port: LPUART2_TX of instance: lpuart2"]
6005 pub const ALT2: u32 = 0x02;
6006 #[doc = "Select mux mode: ALT3 mux port: LPI2C2_SCL of instance: lpi2c2"]
6007 pub const ALT3: u32 = 0x03;
6008 #[doc = "Select mux mode: ALT4 mux port: LPSPI2_PCS3 of instance: lpspi2"]
6009 pub const ALT4: u32 = 0x04;
6010 #[doc = "Select mux mode: ALT5 mux port: GPIO3_IO11 of instance: gpio3"]
6011 pub const ALT5: u32 = 0x05;
6012 }
6013 }
6014 #[doc = "Software Input On Field."]
6015 pub mod SION {
6016 pub const offset: u32 = 4;
6017 pub const mask: u32 = 0x01 << offset;
6018 pub mod R {}
6019 pub mod W {}
6020 pub mod RW {
6021 #[doc = "Input Path is determined by functionality"]
6022 pub const DISABLED: u32 = 0;
6023 #[doc = "Force input path of pad GPIO_SD_B1_11"]
6024 pub const ENABLED: u32 = 0x01;
6025 }
6026 }
6027}
6028#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register"]
6029pub mod SW_PAD_CTL_PAD_GPIO_EMC_00 {
6030 #[doc = "Slew Rate Field"]
6031 pub mod SRE {
6032 pub const offset: u32 = 0;
6033 pub const mask: u32 = 0x01 << offset;
6034 pub mod R {}
6035 pub mod W {}
6036 pub mod RW {
6037 #[doc = "Slow Slew Rate"]
6038 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
6039 #[doc = "Fast Slew Rate"]
6040 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
6041 }
6042 }
6043 #[doc = "Drive Strength Field"]
6044 pub mod DSE {
6045 pub const offset: u32 = 3;
6046 pub const mask: u32 = 0x07 << offset;
6047 pub mod R {}
6048 pub mod W {}
6049 pub mod RW {
6050 #[doc = "output driver disabled;"]
6051 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
6052 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
6053 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
6054 #[doc = "R0/2"]
6055 pub const DSE_2_R0_2: u32 = 0x02;
6056 #[doc = "R0/3"]
6057 pub const DSE_3_R0_3: u32 = 0x03;
6058 #[doc = "R0/4"]
6059 pub const DSE_4_R0_4: u32 = 0x04;
6060 #[doc = "R0/5"]
6061 pub const DSE_5_R0_5: u32 = 0x05;
6062 #[doc = "R0/6"]
6063 pub const DSE_6_R0_6: u32 = 0x06;
6064 #[doc = "R0/7"]
6065 pub const DSE_7_R0_7: u32 = 0x07;
6066 }
6067 }
6068 #[doc = "Speed Field"]
6069 pub mod SPEED {
6070 pub const offset: u32 = 6;
6071 pub const mask: u32 = 0x03 << offset;
6072 pub mod R {}
6073 pub mod W {}
6074 pub mod RW {
6075 #[doc = "low(50MHz)"]
6076 pub const SPEED_0_LOW_50MHZ: u32 = 0;
6077 #[doc = "medium(100MHz)"]
6078 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
6079 #[doc = "medium(100MHz)"]
6080 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
6081 #[doc = "max(200MHz)"]
6082 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
6083 }
6084 }
6085 #[doc = "Open Drain Enable Field"]
6086 pub mod ODE {
6087 pub const offset: u32 = 11;
6088 pub const mask: u32 = 0x01 << offset;
6089 pub mod R {}
6090 pub mod W {}
6091 pub mod RW {
6092 #[doc = "Open Drain Disabled"]
6093 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
6094 #[doc = "Open Drain Enabled"]
6095 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
6096 }
6097 }
6098 #[doc = "Pull / Keep Enable Field"]
6099 pub mod PKE {
6100 pub const offset: u32 = 12;
6101 pub const mask: u32 = 0x01 << offset;
6102 pub mod R {}
6103 pub mod W {}
6104 pub mod RW {
6105 #[doc = "Pull/Keeper Disabled"]
6106 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
6107 #[doc = "Pull/Keeper Enabled"]
6108 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
6109 }
6110 }
6111 #[doc = "Pull / Keep Select Field"]
6112 pub mod PUE {
6113 pub const offset: u32 = 13;
6114 pub const mask: u32 = 0x01 << offset;
6115 pub mod R {}
6116 pub mod W {}
6117 pub mod RW {
6118 #[doc = "Keeper"]
6119 pub const PUE_0_KEEPER: u32 = 0;
6120 #[doc = "Pull"]
6121 pub const PUE_1_PULL: u32 = 0x01;
6122 }
6123 }
6124 #[doc = "Pull Up / Down Config. Field"]
6125 pub mod PUS {
6126 pub const offset: u32 = 14;
6127 pub const mask: u32 = 0x03 << offset;
6128 pub mod R {}
6129 pub mod W {}
6130 pub mod RW {
6131 #[doc = "100K Ohm Pull Down"]
6132 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
6133 #[doc = "47K Ohm Pull Up"]
6134 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
6135 #[doc = "100K Ohm Pull Up"]
6136 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
6137 #[doc = "22K Ohm Pull Up"]
6138 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
6139 }
6140 }
6141 #[doc = "Hyst. Enable Field"]
6142 pub mod HYS {
6143 pub const offset: u32 = 16;
6144 pub const mask: u32 = 0x01 << offset;
6145 pub mod R {}
6146 pub mod W {}
6147 pub mod RW {
6148 #[doc = "Hysteresis Disabled"]
6149 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
6150 #[doc = "Hysteresis Enabled"]
6151 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
6152 }
6153 }
6154}
6155#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_01 SW PAD Control Register"]
6156pub mod SW_PAD_CTL_PAD_GPIO_EMC_01 {
6157 #[doc = "Slew Rate Field"]
6158 pub mod SRE {
6159 pub const offset: u32 = 0;
6160 pub const mask: u32 = 0x01 << offset;
6161 pub mod R {}
6162 pub mod W {}
6163 pub mod RW {
6164 #[doc = "Slow Slew Rate"]
6165 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
6166 #[doc = "Fast Slew Rate"]
6167 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
6168 }
6169 }
6170 #[doc = "Drive Strength Field"]
6171 pub mod DSE {
6172 pub const offset: u32 = 3;
6173 pub const mask: u32 = 0x07 << offset;
6174 pub mod R {}
6175 pub mod W {}
6176 pub mod RW {
6177 #[doc = "output driver disabled;"]
6178 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
6179 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
6180 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
6181 #[doc = "R0/2"]
6182 pub const DSE_2_R0_2: u32 = 0x02;
6183 #[doc = "R0/3"]
6184 pub const DSE_3_R0_3: u32 = 0x03;
6185 #[doc = "R0/4"]
6186 pub const DSE_4_R0_4: u32 = 0x04;
6187 #[doc = "R0/5"]
6188 pub const DSE_5_R0_5: u32 = 0x05;
6189 #[doc = "R0/6"]
6190 pub const DSE_6_R0_6: u32 = 0x06;
6191 #[doc = "R0/7"]
6192 pub const DSE_7_R0_7: u32 = 0x07;
6193 }
6194 }
6195 #[doc = "Speed Field"]
6196 pub mod SPEED {
6197 pub const offset: u32 = 6;
6198 pub const mask: u32 = 0x03 << offset;
6199 pub mod R {}
6200 pub mod W {}
6201 pub mod RW {
6202 #[doc = "low(50MHz)"]
6203 pub const SPEED_0_LOW_50MHZ: u32 = 0;
6204 #[doc = "medium(100MHz)"]
6205 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
6206 #[doc = "medium(100MHz)"]
6207 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
6208 #[doc = "max(200MHz)"]
6209 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
6210 }
6211 }
6212 #[doc = "Open Drain Enable Field"]
6213 pub mod ODE {
6214 pub const offset: u32 = 11;
6215 pub const mask: u32 = 0x01 << offset;
6216 pub mod R {}
6217 pub mod W {}
6218 pub mod RW {
6219 #[doc = "Open Drain Disabled"]
6220 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
6221 #[doc = "Open Drain Enabled"]
6222 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
6223 }
6224 }
6225 #[doc = "Pull / Keep Enable Field"]
6226 pub mod PKE {
6227 pub const offset: u32 = 12;
6228 pub const mask: u32 = 0x01 << offset;
6229 pub mod R {}
6230 pub mod W {}
6231 pub mod RW {
6232 #[doc = "Pull/Keeper Disabled"]
6233 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
6234 #[doc = "Pull/Keeper Enabled"]
6235 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
6236 }
6237 }
6238 #[doc = "Pull / Keep Select Field"]
6239 pub mod PUE {
6240 pub const offset: u32 = 13;
6241 pub const mask: u32 = 0x01 << offset;
6242 pub mod R {}
6243 pub mod W {}
6244 pub mod RW {
6245 #[doc = "Keeper"]
6246 pub const PUE_0_KEEPER: u32 = 0;
6247 #[doc = "Pull"]
6248 pub const PUE_1_PULL: u32 = 0x01;
6249 }
6250 }
6251 #[doc = "Pull Up / Down Config. Field"]
6252 pub mod PUS {
6253 pub const offset: u32 = 14;
6254 pub const mask: u32 = 0x03 << offset;
6255 pub mod R {}
6256 pub mod W {}
6257 pub mod RW {
6258 #[doc = "100K Ohm Pull Down"]
6259 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
6260 #[doc = "47K Ohm Pull Up"]
6261 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
6262 #[doc = "100K Ohm Pull Up"]
6263 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
6264 #[doc = "22K Ohm Pull Up"]
6265 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
6266 }
6267 }
6268 #[doc = "Hyst. Enable Field"]
6269 pub mod HYS {
6270 pub const offset: u32 = 16;
6271 pub const mask: u32 = 0x01 << offset;
6272 pub mod R {}
6273 pub mod W {}
6274 pub mod RW {
6275 #[doc = "Hysteresis Disabled"]
6276 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
6277 #[doc = "Hysteresis Enabled"]
6278 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
6279 }
6280 }
6281}
6282#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_02 SW PAD Control Register"]
6283pub mod SW_PAD_CTL_PAD_GPIO_EMC_02 {
6284 #[doc = "Slew Rate Field"]
6285 pub mod SRE {
6286 pub const offset: u32 = 0;
6287 pub const mask: u32 = 0x01 << offset;
6288 pub mod R {}
6289 pub mod W {}
6290 pub mod RW {
6291 #[doc = "Slow Slew Rate"]
6292 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
6293 #[doc = "Fast Slew Rate"]
6294 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
6295 }
6296 }
6297 #[doc = "Drive Strength Field"]
6298 pub mod DSE {
6299 pub const offset: u32 = 3;
6300 pub const mask: u32 = 0x07 << offset;
6301 pub mod R {}
6302 pub mod W {}
6303 pub mod RW {
6304 #[doc = "output driver disabled;"]
6305 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
6306 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
6307 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
6308 #[doc = "R0/2"]
6309 pub const DSE_2_R0_2: u32 = 0x02;
6310 #[doc = "R0/3"]
6311 pub const DSE_3_R0_3: u32 = 0x03;
6312 #[doc = "R0/4"]
6313 pub const DSE_4_R0_4: u32 = 0x04;
6314 #[doc = "R0/5"]
6315 pub const DSE_5_R0_5: u32 = 0x05;
6316 #[doc = "R0/6"]
6317 pub const DSE_6_R0_6: u32 = 0x06;
6318 #[doc = "R0/7"]
6319 pub const DSE_7_R0_7: u32 = 0x07;
6320 }
6321 }
6322 #[doc = "Speed Field"]
6323 pub mod SPEED {
6324 pub const offset: u32 = 6;
6325 pub const mask: u32 = 0x03 << offset;
6326 pub mod R {}
6327 pub mod W {}
6328 pub mod RW {
6329 #[doc = "low(50MHz)"]
6330 pub const SPEED_0_LOW_50MHZ: u32 = 0;
6331 #[doc = "medium(100MHz)"]
6332 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
6333 #[doc = "medium(100MHz)"]
6334 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
6335 #[doc = "max(200MHz)"]
6336 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
6337 }
6338 }
6339 #[doc = "Open Drain Enable Field"]
6340 pub mod ODE {
6341 pub const offset: u32 = 11;
6342 pub const mask: u32 = 0x01 << offset;
6343 pub mod R {}
6344 pub mod W {}
6345 pub mod RW {
6346 #[doc = "Open Drain Disabled"]
6347 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
6348 #[doc = "Open Drain Enabled"]
6349 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
6350 }
6351 }
6352 #[doc = "Pull / Keep Enable Field"]
6353 pub mod PKE {
6354 pub const offset: u32 = 12;
6355 pub const mask: u32 = 0x01 << offset;
6356 pub mod R {}
6357 pub mod W {}
6358 pub mod RW {
6359 #[doc = "Pull/Keeper Disabled"]
6360 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
6361 #[doc = "Pull/Keeper Enabled"]
6362 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
6363 }
6364 }
6365 #[doc = "Pull / Keep Select Field"]
6366 pub mod PUE {
6367 pub const offset: u32 = 13;
6368 pub const mask: u32 = 0x01 << offset;
6369 pub mod R {}
6370 pub mod W {}
6371 pub mod RW {
6372 #[doc = "Keeper"]
6373 pub const PUE_0_KEEPER: u32 = 0;
6374 #[doc = "Pull"]
6375 pub const PUE_1_PULL: u32 = 0x01;
6376 }
6377 }
6378 #[doc = "Pull Up / Down Config. Field"]
6379 pub mod PUS {
6380 pub const offset: u32 = 14;
6381 pub const mask: u32 = 0x03 << offset;
6382 pub mod R {}
6383 pub mod W {}
6384 pub mod RW {
6385 #[doc = "100K Ohm Pull Down"]
6386 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
6387 #[doc = "47K Ohm Pull Up"]
6388 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
6389 #[doc = "100K Ohm Pull Up"]
6390 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
6391 #[doc = "22K Ohm Pull Up"]
6392 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
6393 }
6394 }
6395 #[doc = "Hyst. Enable Field"]
6396 pub mod HYS {
6397 pub const offset: u32 = 16;
6398 pub const mask: u32 = 0x01 << offset;
6399 pub mod R {}
6400 pub mod W {}
6401 pub mod RW {
6402 #[doc = "Hysteresis Disabled"]
6403 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
6404 #[doc = "Hysteresis Enabled"]
6405 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
6406 }
6407 }
6408}
6409#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_03 SW PAD Control Register"]
6410pub mod SW_PAD_CTL_PAD_GPIO_EMC_03 {
6411 #[doc = "Slew Rate Field"]
6412 pub mod SRE {
6413 pub const offset: u32 = 0;
6414 pub const mask: u32 = 0x01 << offset;
6415 pub mod R {}
6416 pub mod W {}
6417 pub mod RW {
6418 #[doc = "Slow Slew Rate"]
6419 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
6420 #[doc = "Fast Slew Rate"]
6421 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
6422 }
6423 }
6424 #[doc = "Drive Strength Field"]
6425 pub mod DSE {
6426 pub const offset: u32 = 3;
6427 pub const mask: u32 = 0x07 << offset;
6428 pub mod R {}
6429 pub mod W {}
6430 pub mod RW {
6431 #[doc = "output driver disabled;"]
6432 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
6433 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
6434 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
6435 #[doc = "R0/2"]
6436 pub const DSE_2_R0_2: u32 = 0x02;
6437 #[doc = "R0/3"]
6438 pub const DSE_3_R0_3: u32 = 0x03;
6439 #[doc = "R0/4"]
6440 pub const DSE_4_R0_4: u32 = 0x04;
6441 #[doc = "R0/5"]
6442 pub const DSE_5_R0_5: u32 = 0x05;
6443 #[doc = "R0/6"]
6444 pub const DSE_6_R0_6: u32 = 0x06;
6445 #[doc = "R0/7"]
6446 pub const DSE_7_R0_7: u32 = 0x07;
6447 }
6448 }
6449 #[doc = "Speed Field"]
6450 pub mod SPEED {
6451 pub const offset: u32 = 6;
6452 pub const mask: u32 = 0x03 << offset;
6453 pub mod R {}
6454 pub mod W {}
6455 pub mod RW {
6456 #[doc = "low(50MHz)"]
6457 pub const SPEED_0_LOW_50MHZ: u32 = 0;
6458 #[doc = "medium(100MHz)"]
6459 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
6460 #[doc = "medium(100MHz)"]
6461 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
6462 #[doc = "max(200MHz)"]
6463 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
6464 }
6465 }
6466 #[doc = "Open Drain Enable Field"]
6467 pub mod ODE {
6468 pub const offset: u32 = 11;
6469 pub const mask: u32 = 0x01 << offset;
6470 pub mod R {}
6471 pub mod W {}
6472 pub mod RW {
6473 #[doc = "Open Drain Disabled"]
6474 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
6475 #[doc = "Open Drain Enabled"]
6476 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
6477 }
6478 }
6479 #[doc = "Pull / Keep Enable Field"]
6480 pub mod PKE {
6481 pub const offset: u32 = 12;
6482 pub const mask: u32 = 0x01 << offset;
6483 pub mod R {}
6484 pub mod W {}
6485 pub mod RW {
6486 #[doc = "Pull/Keeper Disabled"]
6487 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
6488 #[doc = "Pull/Keeper Enabled"]
6489 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
6490 }
6491 }
6492 #[doc = "Pull / Keep Select Field"]
6493 pub mod PUE {
6494 pub const offset: u32 = 13;
6495 pub const mask: u32 = 0x01 << offset;
6496 pub mod R {}
6497 pub mod W {}
6498 pub mod RW {
6499 #[doc = "Keeper"]
6500 pub const PUE_0_KEEPER: u32 = 0;
6501 #[doc = "Pull"]
6502 pub const PUE_1_PULL: u32 = 0x01;
6503 }
6504 }
6505 #[doc = "Pull Up / Down Config. Field"]
6506 pub mod PUS {
6507 pub const offset: u32 = 14;
6508 pub const mask: u32 = 0x03 << offset;
6509 pub mod R {}
6510 pub mod W {}
6511 pub mod RW {
6512 #[doc = "100K Ohm Pull Down"]
6513 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
6514 #[doc = "47K Ohm Pull Up"]
6515 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
6516 #[doc = "100K Ohm Pull Up"]
6517 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
6518 #[doc = "22K Ohm Pull Up"]
6519 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
6520 }
6521 }
6522 #[doc = "Hyst. Enable Field"]
6523 pub mod HYS {
6524 pub const offset: u32 = 16;
6525 pub const mask: u32 = 0x01 << offset;
6526 pub mod R {}
6527 pub mod W {}
6528 pub mod RW {
6529 #[doc = "Hysteresis Disabled"]
6530 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
6531 #[doc = "Hysteresis Enabled"]
6532 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
6533 }
6534 }
6535}
6536#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_04 SW PAD Control Register"]
6537pub mod SW_PAD_CTL_PAD_GPIO_EMC_04 {
6538 #[doc = "Slew Rate Field"]
6539 pub mod SRE {
6540 pub const offset: u32 = 0;
6541 pub const mask: u32 = 0x01 << offset;
6542 pub mod R {}
6543 pub mod W {}
6544 pub mod RW {
6545 #[doc = "Slow Slew Rate"]
6546 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
6547 #[doc = "Fast Slew Rate"]
6548 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
6549 }
6550 }
6551 #[doc = "Drive Strength Field"]
6552 pub mod DSE {
6553 pub const offset: u32 = 3;
6554 pub const mask: u32 = 0x07 << offset;
6555 pub mod R {}
6556 pub mod W {}
6557 pub mod RW {
6558 #[doc = "output driver disabled;"]
6559 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
6560 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
6561 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
6562 #[doc = "R0/2"]
6563 pub const DSE_2_R0_2: u32 = 0x02;
6564 #[doc = "R0/3"]
6565 pub const DSE_3_R0_3: u32 = 0x03;
6566 #[doc = "R0/4"]
6567 pub const DSE_4_R0_4: u32 = 0x04;
6568 #[doc = "R0/5"]
6569 pub const DSE_5_R0_5: u32 = 0x05;
6570 #[doc = "R0/6"]
6571 pub const DSE_6_R0_6: u32 = 0x06;
6572 #[doc = "R0/7"]
6573 pub const DSE_7_R0_7: u32 = 0x07;
6574 }
6575 }
6576 #[doc = "Speed Field"]
6577 pub mod SPEED {
6578 pub const offset: u32 = 6;
6579 pub const mask: u32 = 0x03 << offset;
6580 pub mod R {}
6581 pub mod W {}
6582 pub mod RW {
6583 #[doc = "low(50MHz)"]
6584 pub const SPEED_0_LOW_50MHZ: u32 = 0;
6585 #[doc = "medium(100MHz)"]
6586 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
6587 #[doc = "medium(100MHz)"]
6588 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
6589 #[doc = "max(200MHz)"]
6590 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
6591 }
6592 }
6593 #[doc = "Open Drain Enable Field"]
6594 pub mod ODE {
6595 pub const offset: u32 = 11;
6596 pub const mask: u32 = 0x01 << offset;
6597 pub mod R {}
6598 pub mod W {}
6599 pub mod RW {
6600 #[doc = "Open Drain Disabled"]
6601 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
6602 #[doc = "Open Drain Enabled"]
6603 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
6604 }
6605 }
6606 #[doc = "Pull / Keep Enable Field"]
6607 pub mod PKE {
6608 pub const offset: u32 = 12;
6609 pub const mask: u32 = 0x01 << offset;
6610 pub mod R {}
6611 pub mod W {}
6612 pub mod RW {
6613 #[doc = "Pull/Keeper Disabled"]
6614 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
6615 #[doc = "Pull/Keeper Enabled"]
6616 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
6617 }
6618 }
6619 #[doc = "Pull / Keep Select Field"]
6620 pub mod PUE {
6621 pub const offset: u32 = 13;
6622 pub const mask: u32 = 0x01 << offset;
6623 pub mod R {}
6624 pub mod W {}
6625 pub mod RW {
6626 #[doc = "Keeper"]
6627 pub const PUE_0_KEEPER: u32 = 0;
6628 #[doc = "Pull"]
6629 pub const PUE_1_PULL: u32 = 0x01;
6630 }
6631 }
6632 #[doc = "Pull Up / Down Config. Field"]
6633 pub mod PUS {
6634 pub const offset: u32 = 14;
6635 pub const mask: u32 = 0x03 << offset;
6636 pub mod R {}
6637 pub mod W {}
6638 pub mod RW {
6639 #[doc = "100K Ohm Pull Down"]
6640 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
6641 #[doc = "47K Ohm Pull Up"]
6642 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
6643 #[doc = "100K Ohm Pull Up"]
6644 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
6645 #[doc = "22K Ohm Pull Up"]
6646 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
6647 }
6648 }
6649 #[doc = "Hyst. Enable Field"]
6650 pub mod HYS {
6651 pub const offset: u32 = 16;
6652 pub const mask: u32 = 0x01 << offset;
6653 pub mod R {}
6654 pub mod W {}
6655 pub mod RW {
6656 #[doc = "Hysteresis Disabled"]
6657 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
6658 #[doc = "Hysteresis Enabled"]
6659 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
6660 }
6661 }
6662}
6663#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_05 SW PAD Control Register"]
6664pub mod SW_PAD_CTL_PAD_GPIO_EMC_05 {
6665 #[doc = "Slew Rate Field"]
6666 pub mod SRE {
6667 pub const offset: u32 = 0;
6668 pub const mask: u32 = 0x01 << offset;
6669 pub mod R {}
6670 pub mod W {}
6671 pub mod RW {
6672 #[doc = "Slow Slew Rate"]
6673 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
6674 #[doc = "Fast Slew Rate"]
6675 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
6676 }
6677 }
6678 #[doc = "Drive Strength Field"]
6679 pub mod DSE {
6680 pub const offset: u32 = 3;
6681 pub const mask: u32 = 0x07 << offset;
6682 pub mod R {}
6683 pub mod W {}
6684 pub mod RW {
6685 #[doc = "output driver disabled;"]
6686 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
6687 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
6688 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
6689 #[doc = "R0/2"]
6690 pub const DSE_2_R0_2: u32 = 0x02;
6691 #[doc = "R0/3"]
6692 pub const DSE_3_R0_3: u32 = 0x03;
6693 #[doc = "R0/4"]
6694 pub const DSE_4_R0_4: u32 = 0x04;
6695 #[doc = "R0/5"]
6696 pub const DSE_5_R0_5: u32 = 0x05;
6697 #[doc = "R0/6"]
6698 pub const DSE_6_R0_6: u32 = 0x06;
6699 #[doc = "R0/7"]
6700 pub const DSE_7_R0_7: u32 = 0x07;
6701 }
6702 }
6703 #[doc = "Speed Field"]
6704 pub mod SPEED {
6705 pub const offset: u32 = 6;
6706 pub const mask: u32 = 0x03 << offset;
6707 pub mod R {}
6708 pub mod W {}
6709 pub mod RW {
6710 #[doc = "low(50MHz)"]
6711 pub const SPEED_0_LOW_50MHZ: u32 = 0;
6712 #[doc = "medium(100MHz)"]
6713 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
6714 #[doc = "medium(100MHz)"]
6715 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
6716 #[doc = "max(200MHz)"]
6717 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
6718 }
6719 }
6720 #[doc = "Open Drain Enable Field"]
6721 pub mod ODE {
6722 pub const offset: u32 = 11;
6723 pub const mask: u32 = 0x01 << offset;
6724 pub mod R {}
6725 pub mod W {}
6726 pub mod RW {
6727 #[doc = "Open Drain Disabled"]
6728 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
6729 #[doc = "Open Drain Enabled"]
6730 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
6731 }
6732 }
6733 #[doc = "Pull / Keep Enable Field"]
6734 pub mod PKE {
6735 pub const offset: u32 = 12;
6736 pub const mask: u32 = 0x01 << offset;
6737 pub mod R {}
6738 pub mod W {}
6739 pub mod RW {
6740 #[doc = "Pull/Keeper Disabled"]
6741 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
6742 #[doc = "Pull/Keeper Enabled"]
6743 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
6744 }
6745 }
6746 #[doc = "Pull / Keep Select Field"]
6747 pub mod PUE {
6748 pub const offset: u32 = 13;
6749 pub const mask: u32 = 0x01 << offset;
6750 pub mod R {}
6751 pub mod W {}
6752 pub mod RW {
6753 #[doc = "Keeper"]
6754 pub const PUE_0_KEEPER: u32 = 0;
6755 #[doc = "Pull"]
6756 pub const PUE_1_PULL: u32 = 0x01;
6757 }
6758 }
6759 #[doc = "Pull Up / Down Config. Field"]
6760 pub mod PUS {
6761 pub const offset: u32 = 14;
6762 pub const mask: u32 = 0x03 << offset;
6763 pub mod R {}
6764 pub mod W {}
6765 pub mod RW {
6766 #[doc = "100K Ohm Pull Down"]
6767 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
6768 #[doc = "47K Ohm Pull Up"]
6769 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
6770 #[doc = "100K Ohm Pull Up"]
6771 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
6772 #[doc = "22K Ohm Pull Up"]
6773 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
6774 }
6775 }
6776 #[doc = "Hyst. Enable Field"]
6777 pub mod HYS {
6778 pub const offset: u32 = 16;
6779 pub const mask: u32 = 0x01 << offset;
6780 pub mod R {}
6781 pub mod W {}
6782 pub mod RW {
6783 #[doc = "Hysteresis Disabled"]
6784 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
6785 #[doc = "Hysteresis Enabled"]
6786 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
6787 }
6788 }
6789}
6790#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_06 SW PAD Control Register"]
6791pub mod SW_PAD_CTL_PAD_GPIO_EMC_06 {
6792 #[doc = "Slew Rate Field"]
6793 pub mod SRE {
6794 pub const offset: u32 = 0;
6795 pub const mask: u32 = 0x01 << offset;
6796 pub mod R {}
6797 pub mod W {}
6798 pub mod RW {
6799 #[doc = "Slow Slew Rate"]
6800 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
6801 #[doc = "Fast Slew Rate"]
6802 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
6803 }
6804 }
6805 #[doc = "Drive Strength Field"]
6806 pub mod DSE {
6807 pub const offset: u32 = 3;
6808 pub const mask: u32 = 0x07 << offset;
6809 pub mod R {}
6810 pub mod W {}
6811 pub mod RW {
6812 #[doc = "output driver disabled;"]
6813 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
6814 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
6815 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
6816 #[doc = "R0/2"]
6817 pub const DSE_2_R0_2: u32 = 0x02;
6818 #[doc = "R0/3"]
6819 pub const DSE_3_R0_3: u32 = 0x03;
6820 #[doc = "R0/4"]
6821 pub const DSE_4_R0_4: u32 = 0x04;
6822 #[doc = "R0/5"]
6823 pub const DSE_5_R0_5: u32 = 0x05;
6824 #[doc = "R0/6"]
6825 pub const DSE_6_R0_6: u32 = 0x06;
6826 #[doc = "R0/7"]
6827 pub const DSE_7_R0_7: u32 = 0x07;
6828 }
6829 }
6830 #[doc = "Speed Field"]
6831 pub mod SPEED {
6832 pub const offset: u32 = 6;
6833 pub const mask: u32 = 0x03 << offset;
6834 pub mod R {}
6835 pub mod W {}
6836 pub mod RW {
6837 #[doc = "low(50MHz)"]
6838 pub const SPEED_0_LOW_50MHZ: u32 = 0;
6839 #[doc = "medium(100MHz)"]
6840 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
6841 #[doc = "medium(100MHz)"]
6842 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
6843 #[doc = "max(200MHz)"]
6844 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
6845 }
6846 }
6847 #[doc = "Open Drain Enable Field"]
6848 pub mod ODE {
6849 pub const offset: u32 = 11;
6850 pub const mask: u32 = 0x01 << offset;
6851 pub mod R {}
6852 pub mod W {}
6853 pub mod RW {
6854 #[doc = "Open Drain Disabled"]
6855 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
6856 #[doc = "Open Drain Enabled"]
6857 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
6858 }
6859 }
6860 #[doc = "Pull / Keep Enable Field"]
6861 pub mod PKE {
6862 pub const offset: u32 = 12;
6863 pub const mask: u32 = 0x01 << offset;
6864 pub mod R {}
6865 pub mod W {}
6866 pub mod RW {
6867 #[doc = "Pull/Keeper Disabled"]
6868 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
6869 #[doc = "Pull/Keeper Enabled"]
6870 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
6871 }
6872 }
6873 #[doc = "Pull / Keep Select Field"]
6874 pub mod PUE {
6875 pub const offset: u32 = 13;
6876 pub const mask: u32 = 0x01 << offset;
6877 pub mod R {}
6878 pub mod W {}
6879 pub mod RW {
6880 #[doc = "Keeper"]
6881 pub const PUE_0_KEEPER: u32 = 0;
6882 #[doc = "Pull"]
6883 pub const PUE_1_PULL: u32 = 0x01;
6884 }
6885 }
6886 #[doc = "Pull Up / Down Config. Field"]
6887 pub mod PUS {
6888 pub const offset: u32 = 14;
6889 pub const mask: u32 = 0x03 << offset;
6890 pub mod R {}
6891 pub mod W {}
6892 pub mod RW {
6893 #[doc = "100K Ohm Pull Down"]
6894 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
6895 #[doc = "47K Ohm Pull Up"]
6896 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
6897 #[doc = "100K Ohm Pull Up"]
6898 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
6899 #[doc = "22K Ohm Pull Up"]
6900 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
6901 }
6902 }
6903 #[doc = "Hyst. Enable Field"]
6904 pub mod HYS {
6905 pub const offset: u32 = 16;
6906 pub const mask: u32 = 0x01 << offset;
6907 pub mod R {}
6908 pub mod W {}
6909 pub mod RW {
6910 #[doc = "Hysteresis Disabled"]
6911 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
6912 #[doc = "Hysteresis Enabled"]
6913 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
6914 }
6915 }
6916}
6917#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_07 SW PAD Control Register"]
6918pub mod SW_PAD_CTL_PAD_GPIO_EMC_07 {
6919 #[doc = "Slew Rate Field"]
6920 pub mod SRE {
6921 pub const offset: u32 = 0;
6922 pub const mask: u32 = 0x01 << offset;
6923 pub mod R {}
6924 pub mod W {}
6925 pub mod RW {
6926 #[doc = "Slow Slew Rate"]
6927 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
6928 #[doc = "Fast Slew Rate"]
6929 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
6930 }
6931 }
6932 #[doc = "Drive Strength Field"]
6933 pub mod DSE {
6934 pub const offset: u32 = 3;
6935 pub const mask: u32 = 0x07 << offset;
6936 pub mod R {}
6937 pub mod W {}
6938 pub mod RW {
6939 #[doc = "output driver disabled;"]
6940 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
6941 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
6942 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
6943 #[doc = "R0/2"]
6944 pub const DSE_2_R0_2: u32 = 0x02;
6945 #[doc = "R0/3"]
6946 pub const DSE_3_R0_3: u32 = 0x03;
6947 #[doc = "R0/4"]
6948 pub const DSE_4_R0_4: u32 = 0x04;
6949 #[doc = "R0/5"]
6950 pub const DSE_5_R0_5: u32 = 0x05;
6951 #[doc = "R0/6"]
6952 pub const DSE_6_R0_6: u32 = 0x06;
6953 #[doc = "R0/7"]
6954 pub const DSE_7_R0_7: u32 = 0x07;
6955 }
6956 }
6957 #[doc = "Speed Field"]
6958 pub mod SPEED {
6959 pub const offset: u32 = 6;
6960 pub const mask: u32 = 0x03 << offset;
6961 pub mod R {}
6962 pub mod W {}
6963 pub mod RW {
6964 #[doc = "low(50MHz)"]
6965 pub const SPEED_0_LOW_50MHZ: u32 = 0;
6966 #[doc = "medium(100MHz)"]
6967 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
6968 #[doc = "medium(100MHz)"]
6969 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
6970 #[doc = "max(200MHz)"]
6971 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
6972 }
6973 }
6974 #[doc = "Open Drain Enable Field"]
6975 pub mod ODE {
6976 pub const offset: u32 = 11;
6977 pub const mask: u32 = 0x01 << offset;
6978 pub mod R {}
6979 pub mod W {}
6980 pub mod RW {
6981 #[doc = "Open Drain Disabled"]
6982 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
6983 #[doc = "Open Drain Enabled"]
6984 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
6985 }
6986 }
6987 #[doc = "Pull / Keep Enable Field"]
6988 pub mod PKE {
6989 pub const offset: u32 = 12;
6990 pub const mask: u32 = 0x01 << offset;
6991 pub mod R {}
6992 pub mod W {}
6993 pub mod RW {
6994 #[doc = "Pull/Keeper Disabled"]
6995 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
6996 #[doc = "Pull/Keeper Enabled"]
6997 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
6998 }
6999 }
7000 #[doc = "Pull / Keep Select Field"]
7001 pub mod PUE {
7002 pub const offset: u32 = 13;
7003 pub const mask: u32 = 0x01 << offset;
7004 pub mod R {}
7005 pub mod W {}
7006 pub mod RW {
7007 #[doc = "Keeper"]
7008 pub const PUE_0_KEEPER: u32 = 0;
7009 #[doc = "Pull"]
7010 pub const PUE_1_PULL: u32 = 0x01;
7011 }
7012 }
7013 #[doc = "Pull Up / Down Config. Field"]
7014 pub mod PUS {
7015 pub const offset: u32 = 14;
7016 pub const mask: u32 = 0x03 << offset;
7017 pub mod R {}
7018 pub mod W {}
7019 pub mod RW {
7020 #[doc = "100K Ohm Pull Down"]
7021 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
7022 #[doc = "47K Ohm Pull Up"]
7023 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
7024 #[doc = "100K Ohm Pull Up"]
7025 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
7026 #[doc = "22K Ohm Pull Up"]
7027 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
7028 }
7029 }
7030 #[doc = "Hyst. Enable Field"]
7031 pub mod HYS {
7032 pub const offset: u32 = 16;
7033 pub const mask: u32 = 0x01 << offset;
7034 pub mod R {}
7035 pub mod W {}
7036 pub mod RW {
7037 #[doc = "Hysteresis Disabled"]
7038 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
7039 #[doc = "Hysteresis Enabled"]
7040 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
7041 }
7042 }
7043}
7044#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_08 SW PAD Control Register"]
7045pub mod SW_PAD_CTL_PAD_GPIO_EMC_08 {
7046 #[doc = "Slew Rate Field"]
7047 pub mod SRE {
7048 pub const offset: u32 = 0;
7049 pub const mask: u32 = 0x01 << offset;
7050 pub mod R {}
7051 pub mod W {}
7052 pub mod RW {
7053 #[doc = "Slow Slew Rate"]
7054 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
7055 #[doc = "Fast Slew Rate"]
7056 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
7057 }
7058 }
7059 #[doc = "Drive Strength Field"]
7060 pub mod DSE {
7061 pub const offset: u32 = 3;
7062 pub const mask: u32 = 0x07 << offset;
7063 pub mod R {}
7064 pub mod W {}
7065 pub mod RW {
7066 #[doc = "output driver disabled;"]
7067 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
7068 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
7069 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
7070 #[doc = "R0/2"]
7071 pub const DSE_2_R0_2: u32 = 0x02;
7072 #[doc = "R0/3"]
7073 pub const DSE_3_R0_3: u32 = 0x03;
7074 #[doc = "R0/4"]
7075 pub const DSE_4_R0_4: u32 = 0x04;
7076 #[doc = "R0/5"]
7077 pub const DSE_5_R0_5: u32 = 0x05;
7078 #[doc = "R0/6"]
7079 pub const DSE_6_R0_6: u32 = 0x06;
7080 #[doc = "R0/7"]
7081 pub const DSE_7_R0_7: u32 = 0x07;
7082 }
7083 }
7084 #[doc = "Speed Field"]
7085 pub mod SPEED {
7086 pub const offset: u32 = 6;
7087 pub const mask: u32 = 0x03 << offset;
7088 pub mod R {}
7089 pub mod W {}
7090 pub mod RW {
7091 #[doc = "low(50MHz)"]
7092 pub const SPEED_0_LOW_50MHZ: u32 = 0;
7093 #[doc = "medium(100MHz)"]
7094 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
7095 #[doc = "medium(100MHz)"]
7096 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
7097 #[doc = "max(200MHz)"]
7098 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
7099 }
7100 }
7101 #[doc = "Open Drain Enable Field"]
7102 pub mod ODE {
7103 pub const offset: u32 = 11;
7104 pub const mask: u32 = 0x01 << offset;
7105 pub mod R {}
7106 pub mod W {}
7107 pub mod RW {
7108 #[doc = "Open Drain Disabled"]
7109 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
7110 #[doc = "Open Drain Enabled"]
7111 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
7112 }
7113 }
7114 #[doc = "Pull / Keep Enable Field"]
7115 pub mod PKE {
7116 pub const offset: u32 = 12;
7117 pub const mask: u32 = 0x01 << offset;
7118 pub mod R {}
7119 pub mod W {}
7120 pub mod RW {
7121 #[doc = "Pull/Keeper Disabled"]
7122 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
7123 #[doc = "Pull/Keeper Enabled"]
7124 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
7125 }
7126 }
7127 #[doc = "Pull / Keep Select Field"]
7128 pub mod PUE {
7129 pub const offset: u32 = 13;
7130 pub const mask: u32 = 0x01 << offset;
7131 pub mod R {}
7132 pub mod W {}
7133 pub mod RW {
7134 #[doc = "Keeper"]
7135 pub const PUE_0_KEEPER: u32 = 0;
7136 #[doc = "Pull"]
7137 pub const PUE_1_PULL: u32 = 0x01;
7138 }
7139 }
7140 #[doc = "Pull Up / Down Config. Field"]
7141 pub mod PUS {
7142 pub const offset: u32 = 14;
7143 pub const mask: u32 = 0x03 << offset;
7144 pub mod R {}
7145 pub mod W {}
7146 pub mod RW {
7147 #[doc = "100K Ohm Pull Down"]
7148 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
7149 #[doc = "47K Ohm Pull Up"]
7150 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
7151 #[doc = "100K Ohm Pull Up"]
7152 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
7153 #[doc = "22K Ohm Pull Up"]
7154 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
7155 }
7156 }
7157 #[doc = "Hyst. Enable Field"]
7158 pub mod HYS {
7159 pub const offset: u32 = 16;
7160 pub const mask: u32 = 0x01 << offset;
7161 pub mod R {}
7162 pub mod W {}
7163 pub mod RW {
7164 #[doc = "Hysteresis Disabled"]
7165 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
7166 #[doc = "Hysteresis Enabled"]
7167 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
7168 }
7169 }
7170}
7171#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_09 SW PAD Control Register"]
7172pub mod SW_PAD_CTL_PAD_GPIO_EMC_09 {
7173 #[doc = "Slew Rate Field"]
7174 pub mod SRE {
7175 pub const offset: u32 = 0;
7176 pub const mask: u32 = 0x01 << offset;
7177 pub mod R {}
7178 pub mod W {}
7179 pub mod RW {
7180 #[doc = "Slow Slew Rate"]
7181 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
7182 #[doc = "Fast Slew Rate"]
7183 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
7184 }
7185 }
7186 #[doc = "Drive Strength Field"]
7187 pub mod DSE {
7188 pub const offset: u32 = 3;
7189 pub const mask: u32 = 0x07 << offset;
7190 pub mod R {}
7191 pub mod W {}
7192 pub mod RW {
7193 #[doc = "output driver disabled;"]
7194 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
7195 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
7196 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
7197 #[doc = "R0/2"]
7198 pub const DSE_2_R0_2: u32 = 0x02;
7199 #[doc = "R0/3"]
7200 pub const DSE_3_R0_3: u32 = 0x03;
7201 #[doc = "R0/4"]
7202 pub const DSE_4_R0_4: u32 = 0x04;
7203 #[doc = "R0/5"]
7204 pub const DSE_5_R0_5: u32 = 0x05;
7205 #[doc = "R0/6"]
7206 pub const DSE_6_R0_6: u32 = 0x06;
7207 #[doc = "R0/7"]
7208 pub const DSE_7_R0_7: u32 = 0x07;
7209 }
7210 }
7211 #[doc = "Speed Field"]
7212 pub mod SPEED {
7213 pub const offset: u32 = 6;
7214 pub const mask: u32 = 0x03 << offset;
7215 pub mod R {}
7216 pub mod W {}
7217 pub mod RW {
7218 #[doc = "low(50MHz)"]
7219 pub const SPEED_0_LOW_50MHZ: u32 = 0;
7220 #[doc = "medium(100MHz)"]
7221 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
7222 #[doc = "medium(100MHz)"]
7223 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
7224 #[doc = "max(200MHz)"]
7225 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
7226 }
7227 }
7228 #[doc = "Open Drain Enable Field"]
7229 pub mod ODE {
7230 pub const offset: u32 = 11;
7231 pub const mask: u32 = 0x01 << offset;
7232 pub mod R {}
7233 pub mod W {}
7234 pub mod RW {
7235 #[doc = "Open Drain Disabled"]
7236 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
7237 #[doc = "Open Drain Enabled"]
7238 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
7239 }
7240 }
7241 #[doc = "Pull / Keep Enable Field"]
7242 pub mod PKE {
7243 pub const offset: u32 = 12;
7244 pub const mask: u32 = 0x01 << offset;
7245 pub mod R {}
7246 pub mod W {}
7247 pub mod RW {
7248 #[doc = "Pull/Keeper Disabled"]
7249 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
7250 #[doc = "Pull/Keeper Enabled"]
7251 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
7252 }
7253 }
7254 #[doc = "Pull / Keep Select Field"]
7255 pub mod PUE {
7256 pub const offset: u32 = 13;
7257 pub const mask: u32 = 0x01 << offset;
7258 pub mod R {}
7259 pub mod W {}
7260 pub mod RW {
7261 #[doc = "Keeper"]
7262 pub const PUE_0_KEEPER: u32 = 0;
7263 #[doc = "Pull"]
7264 pub const PUE_1_PULL: u32 = 0x01;
7265 }
7266 }
7267 #[doc = "Pull Up / Down Config. Field"]
7268 pub mod PUS {
7269 pub const offset: u32 = 14;
7270 pub const mask: u32 = 0x03 << offset;
7271 pub mod R {}
7272 pub mod W {}
7273 pub mod RW {
7274 #[doc = "100K Ohm Pull Down"]
7275 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
7276 #[doc = "47K Ohm Pull Up"]
7277 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
7278 #[doc = "100K Ohm Pull Up"]
7279 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
7280 #[doc = "22K Ohm Pull Up"]
7281 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
7282 }
7283 }
7284 #[doc = "Hyst. Enable Field"]
7285 pub mod HYS {
7286 pub const offset: u32 = 16;
7287 pub const mask: u32 = 0x01 << offset;
7288 pub mod R {}
7289 pub mod W {}
7290 pub mod RW {
7291 #[doc = "Hysteresis Disabled"]
7292 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
7293 #[doc = "Hysteresis Enabled"]
7294 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
7295 }
7296 }
7297}
7298#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_10 SW PAD Control Register"]
7299pub mod SW_PAD_CTL_PAD_GPIO_EMC_10 {
7300 #[doc = "Slew Rate Field"]
7301 pub mod SRE {
7302 pub const offset: u32 = 0;
7303 pub const mask: u32 = 0x01 << offset;
7304 pub mod R {}
7305 pub mod W {}
7306 pub mod RW {
7307 #[doc = "Slow Slew Rate"]
7308 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
7309 #[doc = "Fast Slew Rate"]
7310 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
7311 }
7312 }
7313 #[doc = "Drive Strength Field"]
7314 pub mod DSE {
7315 pub const offset: u32 = 3;
7316 pub const mask: u32 = 0x07 << offset;
7317 pub mod R {}
7318 pub mod W {}
7319 pub mod RW {
7320 #[doc = "output driver disabled;"]
7321 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
7322 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
7323 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
7324 #[doc = "R0/2"]
7325 pub const DSE_2_R0_2: u32 = 0x02;
7326 #[doc = "R0/3"]
7327 pub const DSE_3_R0_3: u32 = 0x03;
7328 #[doc = "R0/4"]
7329 pub const DSE_4_R0_4: u32 = 0x04;
7330 #[doc = "R0/5"]
7331 pub const DSE_5_R0_5: u32 = 0x05;
7332 #[doc = "R0/6"]
7333 pub const DSE_6_R0_6: u32 = 0x06;
7334 #[doc = "R0/7"]
7335 pub const DSE_7_R0_7: u32 = 0x07;
7336 }
7337 }
7338 #[doc = "Speed Field"]
7339 pub mod SPEED {
7340 pub const offset: u32 = 6;
7341 pub const mask: u32 = 0x03 << offset;
7342 pub mod R {}
7343 pub mod W {}
7344 pub mod RW {
7345 #[doc = "low(50MHz)"]
7346 pub const SPEED_0_LOW_50MHZ: u32 = 0;
7347 #[doc = "medium(100MHz)"]
7348 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
7349 #[doc = "medium(100MHz)"]
7350 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
7351 #[doc = "max(200MHz)"]
7352 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
7353 }
7354 }
7355 #[doc = "Open Drain Enable Field"]
7356 pub mod ODE {
7357 pub const offset: u32 = 11;
7358 pub const mask: u32 = 0x01 << offset;
7359 pub mod R {}
7360 pub mod W {}
7361 pub mod RW {
7362 #[doc = "Open Drain Disabled"]
7363 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
7364 #[doc = "Open Drain Enabled"]
7365 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
7366 }
7367 }
7368 #[doc = "Pull / Keep Enable Field"]
7369 pub mod PKE {
7370 pub const offset: u32 = 12;
7371 pub const mask: u32 = 0x01 << offset;
7372 pub mod R {}
7373 pub mod W {}
7374 pub mod RW {
7375 #[doc = "Pull/Keeper Disabled"]
7376 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
7377 #[doc = "Pull/Keeper Enabled"]
7378 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
7379 }
7380 }
7381 #[doc = "Pull / Keep Select Field"]
7382 pub mod PUE {
7383 pub const offset: u32 = 13;
7384 pub const mask: u32 = 0x01 << offset;
7385 pub mod R {}
7386 pub mod W {}
7387 pub mod RW {
7388 #[doc = "Keeper"]
7389 pub const PUE_0_KEEPER: u32 = 0;
7390 #[doc = "Pull"]
7391 pub const PUE_1_PULL: u32 = 0x01;
7392 }
7393 }
7394 #[doc = "Pull Up / Down Config. Field"]
7395 pub mod PUS {
7396 pub const offset: u32 = 14;
7397 pub const mask: u32 = 0x03 << offset;
7398 pub mod R {}
7399 pub mod W {}
7400 pub mod RW {
7401 #[doc = "100K Ohm Pull Down"]
7402 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
7403 #[doc = "47K Ohm Pull Up"]
7404 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
7405 #[doc = "100K Ohm Pull Up"]
7406 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
7407 #[doc = "22K Ohm Pull Up"]
7408 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
7409 }
7410 }
7411 #[doc = "Hyst. Enable Field"]
7412 pub mod HYS {
7413 pub const offset: u32 = 16;
7414 pub const mask: u32 = 0x01 << offset;
7415 pub mod R {}
7416 pub mod W {}
7417 pub mod RW {
7418 #[doc = "Hysteresis Disabled"]
7419 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
7420 #[doc = "Hysteresis Enabled"]
7421 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
7422 }
7423 }
7424}
7425#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_11 SW PAD Control Register"]
7426pub mod SW_PAD_CTL_PAD_GPIO_EMC_11 {
7427 #[doc = "Slew Rate Field"]
7428 pub mod SRE {
7429 pub const offset: u32 = 0;
7430 pub const mask: u32 = 0x01 << offset;
7431 pub mod R {}
7432 pub mod W {}
7433 pub mod RW {
7434 #[doc = "Slow Slew Rate"]
7435 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
7436 #[doc = "Fast Slew Rate"]
7437 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
7438 }
7439 }
7440 #[doc = "Drive Strength Field"]
7441 pub mod DSE {
7442 pub const offset: u32 = 3;
7443 pub const mask: u32 = 0x07 << offset;
7444 pub mod R {}
7445 pub mod W {}
7446 pub mod RW {
7447 #[doc = "output driver disabled;"]
7448 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
7449 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
7450 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
7451 #[doc = "R0/2"]
7452 pub const DSE_2_R0_2: u32 = 0x02;
7453 #[doc = "R0/3"]
7454 pub const DSE_3_R0_3: u32 = 0x03;
7455 #[doc = "R0/4"]
7456 pub const DSE_4_R0_4: u32 = 0x04;
7457 #[doc = "R0/5"]
7458 pub const DSE_5_R0_5: u32 = 0x05;
7459 #[doc = "R0/6"]
7460 pub const DSE_6_R0_6: u32 = 0x06;
7461 #[doc = "R0/7"]
7462 pub const DSE_7_R0_7: u32 = 0x07;
7463 }
7464 }
7465 #[doc = "Speed Field"]
7466 pub mod SPEED {
7467 pub const offset: u32 = 6;
7468 pub const mask: u32 = 0x03 << offset;
7469 pub mod R {}
7470 pub mod W {}
7471 pub mod RW {
7472 #[doc = "low(50MHz)"]
7473 pub const SPEED_0_LOW_50MHZ: u32 = 0;
7474 #[doc = "medium(100MHz)"]
7475 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
7476 #[doc = "medium(100MHz)"]
7477 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
7478 #[doc = "max(200MHz)"]
7479 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
7480 }
7481 }
7482 #[doc = "Open Drain Enable Field"]
7483 pub mod ODE {
7484 pub const offset: u32 = 11;
7485 pub const mask: u32 = 0x01 << offset;
7486 pub mod R {}
7487 pub mod W {}
7488 pub mod RW {
7489 #[doc = "Open Drain Disabled"]
7490 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
7491 #[doc = "Open Drain Enabled"]
7492 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
7493 }
7494 }
7495 #[doc = "Pull / Keep Enable Field"]
7496 pub mod PKE {
7497 pub const offset: u32 = 12;
7498 pub const mask: u32 = 0x01 << offset;
7499 pub mod R {}
7500 pub mod W {}
7501 pub mod RW {
7502 #[doc = "Pull/Keeper Disabled"]
7503 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
7504 #[doc = "Pull/Keeper Enabled"]
7505 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
7506 }
7507 }
7508 #[doc = "Pull / Keep Select Field"]
7509 pub mod PUE {
7510 pub const offset: u32 = 13;
7511 pub const mask: u32 = 0x01 << offset;
7512 pub mod R {}
7513 pub mod W {}
7514 pub mod RW {
7515 #[doc = "Keeper"]
7516 pub const PUE_0_KEEPER: u32 = 0;
7517 #[doc = "Pull"]
7518 pub const PUE_1_PULL: u32 = 0x01;
7519 }
7520 }
7521 #[doc = "Pull Up / Down Config. Field"]
7522 pub mod PUS {
7523 pub const offset: u32 = 14;
7524 pub const mask: u32 = 0x03 << offset;
7525 pub mod R {}
7526 pub mod W {}
7527 pub mod RW {
7528 #[doc = "100K Ohm Pull Down"]
7529 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
7530 #[doc = "47K Ohm Pull Up"]
7531 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
7532 #[doc = "100K Ohm Pull Up"]
7533 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
7534 #[doc = "22K Ohm Pull Up"]
7535 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
7536 }
7537 }
7538 #[doc = "Hyst. Enable Field"]
7539 pub mod HYS {
7540 pub const offset: u32 = 16;
7541 pub const mask: u32 = 0x01 << offset;
7542 pub mod R {}
7543 pub mod W {}
7544 pub mod RW {
7545 #[doc = "Hysteresis Disabled"]
7546 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
7547 #[doc = "Hysteresis Enabled"]
7548 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
7549 }
7550 }
7551}
7552#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_12 SW PAD Control Register"]
7553pub mod SW_PAD_CTL_PAD_GPIO_EMC_12 {
7554 #[doc = "Slew Rate Field"]
7555 pub mod SRE {
7556 pub const offset: u32 = 0;
7557 pub const mask: u32 = 0x01 << offset;
7558 pub mod R {}
7559 pub mod W {}
7560 pub mod RW {
7561 #[doc = "Slow Slew Rate"]
7562 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
7563 #[doc = "Fast Slew Rate"]
7564 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
7565 }
7566 }
7567 #[doc = "Drive Strength Field"]
7568 pub mod DSE {
7569 pub const offset: u32 = 3;
7570 pub const mask: u32 = 0x07 << offset;
7571 pub mod R {}
7572 pub mod W {}
7573 pub mod RW {
7574 #[doc = "output driver disabled;"]
7575 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
7576 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
7577 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
7578 #[doc = "R0/2"]
7579 pub const DSE_2_R0_2: u32 = 0x02;
7580 #[doc = "R0/3"]
7581 pub const DSE_3_R0_3: u32 = 0x03;
7582 #[doc = "R0/4"]
7583 pub const DSE_4_R0_4: u32 = 0x04;
7584 #[doc = "R0/5"]
7585 pub const DSE_5_R0_5: u32 = 0x05;
7586 #[doc = "R0/6"]
7587 pub const DSE_6_R0_6: u32 = 0x06;
7588 #[doc = "R0/7"]
7589 pub const DSE_7_R0_7: u32 = 0x07;
7590 }
7591 }
7592 #[doc = "Speed Field"]
7593 pub mod SPEED {
7594 pub const offset: u32 = 6;
7595 pub const mask: u32 = 0x03 << offset;
7596 pub mod R {}
7597 pub mod W {}
7598 pub mod RW {
7599 #[doc = "low(50MHz)"]
7600 pub const SPEED_0_LOW_50MHZ: u32 = 0;
7601 #[doc = "medium(100MHz)"]
7602 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
7603 #[doc = "medium(100MHz)"]
7604 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
7605 #[doc = "max(200MHz)"]
7606 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
7607 }
7608 }
7609 #[doc = "Open Drain Enable Field"]
7610 pub mod ODE {
7611 pub const offset: u32 = 11;
7612 pub const mask: u32 = 0x01 << offset;
7613 pub mod R {}
7614 pub mod W {}
7615 pub mod RW {
7616 #[doc = "Open Drain Disabled"]
7617 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
7618 #[doc = "Open Drain Enabled"]
7619 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
7620 }
7621 }
7622 #[doc = "Pull / Keep Enable Field"]
7623 pub mod PKE {
7624 pub const offset: u32 = 12;
7625 pub const mask: u32 = 0x01 << offset;
7626 pub mod R {}
7627 pub mod W {}
7628 pub mod RW {
7629 #[doc = "Pull/Keeper Disabled"]
7630 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
7631 #[doc = "Pull/Keeper Enabled"]
7632 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
7633 }
7634 }
7635 #[doc = "Pull / Keep Select Field"]
7636 pub mod PUE {
7637 pub const offset: u32 = 13;
7638 pub const mask: u32 = 0x01 << offset;
7639 pub mod R {}
7640 pub mod W {}
7641 pub mod RW {
7642 #[doc = "Keeper"]
7643 pub const PUE_0_KEEPER: u32 = 0;
7644 #[doc = "Pull"]
7645 pub const PUE_1_PULL: u32 = 0x01;
7646 }
7647 }
7648 #[doc = "Pull Up / Down Config. Field"]
7649 pub mod PUS {
7650 pub const offset: u32 = 14;
7651 pub const mask: u32 = 0x03 << offset;
7652 pub mod R {}
7653 pub mod W {}
7654 pub mod RW {
7655 #[doc = "100K Ohm Pull Down"]
7656 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
7657 #[doc = "47K Ohm Pull Up"]
7658 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
7659 #[doc = "100K Ohm Pull Up"]
7660 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
7661 #[doc = "22K Ohm Pull Up"]
7662 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
7663 }
7664 }
7665 #[doc = "Hyst. Enable Field"]
7666 pub mod HYS {
7667 pub const offset: u32 = 16;
7668 pub const mask: u32 = 0x01 << offset;
7669 pub mod R {}
7670 pub mod W {}
7671 pub mod RW {
7672 #[doc = "Hysteresis Disabled"]
7673 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
7674 #[doc = "Hysteresis Enabled"]
7675 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
7676 }
7677 }
7678}
7679#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_13 SW PAD Control Register"]
7680pub mod SW_PAD_CTL_PAD_GPIO_EMC_13 {
7681 #[doc = "Slew Rate Field"]
7682 pub mod SRE {
7683 pub const offset: u32 = 0;
7684 pub const mask: u32 = 0x01 << offset;
7685 pub mod R {}
7686 pub mod W {}
7687 pub mod RW {
7688 #[doc = "Slow Slew Rate"]
7689 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
7690 #[doc = "Fast Slew Rate"]
7691 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
7692 }
7693 }
7694 #[doc = "Drive Strength Field"]
7695 pub mod DSE {
7696 pub const offset: u32 = 3;
7697 pub const mask: u32 = 0x07 << offset;
7698 pub mod R {}
7699 pub mod W {}
7700 pub mod RW {
7701 #[doc = "output driver disabled;"]
7702 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
7703 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
7704 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
7705 #[doc = "R0/2"]
7706 pub const DSE_2_R0_2: u32 = 0x02;
7707 #[doc = "R0/3"]
7708 pub const DSE_3_R0_3: u32 = 0x03;
7709 #[doc = "R0/4"]
7710 pub const DSE_4_R0_4: u32 = 0x04;
7711 #[doc = "R0/5"]
7712 pub const DSE_5_R0_5: u32 = 0x05;
7713 #[doc = "R0/6"]
7714 pub const DSE_6_R0_6: u32 = 0x06;
7715 #[doc = "R0/7"]
7716 pub const DSE_7_R0_7: u32 = 0x07;
7717 }
7718 }
7719 #[doc = "Speed Field"]
7720 pub mod SPEED {
7721 pub const offset: u32 = 6;
7722 pub const mask: u32 = 0x03 << offset;
7723 pub mod R {}
7724 pub mod W {}
7725 pub mod RW {
7726 #[doc = "low(50MHz)"]
7727 pub const SPEED_0_LOW_50MHZ: u32 = 0;
7728 #[doc = "medium(100MHz)"]
7729 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
7730 #[doc = "medium(100MHz)"]
7731 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
7732 #[doc = "max(200MHz)"]
7733 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
7734 }
7735 }
7736 #[doc = "Open Drain Enable Field"]
7737 pub mod ODE {
7738 pub const offset: u32 = 11;
7739 pub const mask: u32 = 0x01 << offset;
7740 pub mod R {}
7741 pub mod W {}
7742 pub mod RW {
7743 #[doc = "Open Drain Disabled"]
7744 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
7745 #[doc = "Open Drain Enabled"]
7746 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
7747 }
7748 }
7749 #[doc = "Pull / Keep Enable Field"]
7750 pub mod PKE {
7751 pub const offset: u32 = 12;
7752 pub const mask: u32 = 0x01 << offset;
7753 pub mod R {}
7754 pub mod W {}
7755 pub mod RW {
7756 #[doc = "Pull/Keeper Disabled"]
7757 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
7758 #[doc = "Pull/Keeper Enabled"]
7759 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
7760 }
7761 }
7762 #[doc = "Pull / Keep Select Field"]
7763 pub mod PUE {
7764 pub const offset: u32 = 13;
7765 pub const mask: u32 = 0x01 << offset;
7766 pub mod R {}
7767 pub mod W {}
7768 pub mod RW {
7769 #[doc = "Keeper"]
7770 pub const PUE_0_KEEPER: u32 = 0;
7771 #[doc = "Pull"]
7772 pub const PUE_1_PULL: u32 = 0x01;
7773 }
7774 }
7775 #[doc = "Pull Up / Down Config. Field"]
7776 pub mod PUS {
7777 pub const offset: u32 = 14;
7778 pub const mask: u32 = 0x03 << offset;
7779 pub mod R {}
7780 pub mod W {}
7781 pub mod RW {
7782 #[doc = "100K Ohm Pull Down"]
7783 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
7784 #[doc = "47K Ohm Pull Up"]
7785 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
7786 #[doc = "100K Ohm Pull Up"]
7787 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
7788 #[doc = "22K Ohm Pull Up"]
7789 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
7790 }
7791 }
7792 #[doc = "Hyst. Enable Field"]
7793 pub mod HYS {
7794 pub const offset: u32 = 16;
7795 pub const mask: u32 = 0x01 << offset;
7796 pub mod R {}
7797 pub mod W {}
7798 pub mod RW {
7799 #[doc = "Hysteresis Disabled"]
7800 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
7801 #[doc = "Hysteresis Enabled"]
7802 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
7803 }
7804 }
7805}
7806#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_14 SW PAD Control Register"]
7807pub mod SW_PAD_CTL_PAD_GPIO_EMC_14 {
7808 #[doc = "Slew Rate Field"]
7809 pub mod SRE {
7810 pub const offset: u32 = 0;
7811 pub const mask: u32 = 0x01 << offset;
7812 pub mod R {}
7813 pub mod W {}
7814 pub mod RW {
7815 #[doc = "Slow Slew Rate"]
7816 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
7817 #[doc = "Fast Slew Rate"]
7818 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
7819 }
7820 }
7821 #[doc = "Drive Strength Field"]
7822 pub mod DSE {
7823 pub const offset: u32 = 3;
7824 pub const mask: u32 = 0x07 << offset;
7825 pub mod R {}
7826 pub mod W {}
7827 pub mod RW {
7828 #[doc = "output driver disabled;"]
7829 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
7830 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
7831 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
7832 #[doc = "R0/2"]
7833 pub const DSE_2_R0_2: u32 = 0x02;
7834 #[doc = "R0/3"]
7835 pub const DSE_3_R0_3: u32 = 0x03;
7836 #[doc = "R0/4"]
7837 pub const DSE_4_R0_4: u32 = 0x04;
7838 #[doc = "R0/5"]
7839 pub const DSE_5_R0_5: u32 = 0x05;
7840 #[doc = "R0/6"]
7841 pub const DSE_6_R0_6: u32 = 0x06;
7842 #[doc = "R0/7"]
7843 pub const DSE_7_R0_7: u32 = 0x07;
7844 }
7845 }
7846 #[doc = "Speed Field"]
7847 pub mod SPEED {
7848 pub const offset: u32 = 6;
7849 pub const mask: u32 = 0x03 << offset;
7850 pub mod R {}
7851 pub mod W {}
7852 pub mod RW {
7853 #[doc = "low(50MHz)"]
7854 pub const SPEED_0_LOW_50MHZ: u32 = 0;
7855 #[doc = "medium(100MHz)"]
7856 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
7857 #[doc = "medium(100MHz)"]
7858 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
7859 #[doc = "max(200MHz)"]
7860 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
7861 }
7862 }
7863 #[doc = "Open Drain Enable Field"]
7864 pub mod ODE {
7865 pub const offset: u32 = 11;
7866 pub const mask: u32 = 0x01 << offset;
7867 pub mod R {}
7868 pub mod W {}
7869 pub mod RW {
7870 #[doc = "Open Drain Disabled"]
7871 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
7872 #[doc = "Open Drain Enabled"]
7873 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
7874 }
7875 }
7876 #[doc = "Pull / Keep Enable Field"]
7877 pub mod PKE {
7878 pub const offset: u32 = 12;
7879 pub const mask: u32 = 0x01 << offset;
7880 pub mod R {}
7881 pub mod W {}
7882 pub mod RW {
7883 #[doc = "Pull/Keeper Disabled"]
7884 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
7885 #[doc = "Pull/Keeper Enabled"]
7886 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
7887 }
7888 }
7889 #[doc = "Pull / Keep Select Field"]
7890 pub mod PUE {
7891 pub const offset: u32 = 13;
7892 pub const mask: u32 = 0x01 << offset;
7893 pub mod R {}
7894 pub mod W {}
7895 pub mod RW {
7896 #[doc = "Keeper"]
7897 pub const PUE_0_KEEPER: u32 = 0;
7898 #[doc = "Pull"]
7899 pub const PUE_1_PULL: u32 = 0x01;
7900 }
7901 }
7902 #[doc = "Pull Up / Down Config. Field"]
7903 pub mod PUS {
7904 pub const offset: u32 = 14;
7905 pub const mask: u32 = 0x03 << offset;
7906 pub mod R {}
7907 pub mod W {}
7908 pub mod RW {
7909 #[doc = "100K Ohm Pull Down"]
7910 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
7911 #[doc = "47K Ohm Pull Up"]
7912 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
7913 #[doc = "100K Ohm Pull Up"]
7914 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
7915 #[doc = "22K Ohm Pull Up"]
7916 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
7917 }
7918 }
7919 #[doc = "Hyst. Enable Field"]
7920 pub mod HYS {
7921 pub const offset: u32 = 16;
7922 pub const mask: u32 = 0x01 << offset;
7923 pub mod R {}
7924 pub mod W {}
7925 pub mod RW {
7926 #[doc = "Hysteresis Disabled"]
7927 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
7928 #[doc = "Hysteresis Enabled"]
7929 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
7930 }
7931 }
7932}
7933#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_15 SW PAD Control Register"]
7934pub mod SW_PAD_CTL_PAD_GPIO_EMC_15 {
7935 #[doc = "Slew Rate Field"]
7936 pub mod SRE {
7937 pub const offset: u32 = 0;
7938 pub const mask: u32 = 0x01 << offset;
7939 pub mod R {}
7940 pub mod W {}
7941 pub mod RW {
7942 #[doc = "Slow Slew Rate"]
7943 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
7944 #[doc = "Fast Slew Rate"]
7945 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
7946 }
7947 }
7948 #[doc = "Drive Strength Field"]
7949 pub mod DSE {
7950 pub const offset: u32 = 3;
7951 pub const mask: u32 = 0x07 << offset;
7952 pub mod R {}
7953 pub mod W {}
7954 pub mod RW {
7955 #[doc = "output driver disabled;"]
7956 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
7957 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
7958 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
7959 #[doc = "R0/2"]
7960 pub const DSE_2_R0_2: u32 = 0x02;
7961 #[doc = "R0/3"]
7962 pub const DSE_3_R0_3: u32 = 0x03;
7963 #[doc = "R0/4"]
7964 pub const DSE_4_R0_4: u32 = 0x04;
7965 #[doc = "R0/5"]
7966 pub const DSE_5_R0_5: u32 = 0x05;
7967 #[doc = "R0/6"]
7968 pub const DSE_6_R0_6: u32 = 0x06;
7969 #[doc = "R0/7"]
7970 pub const DSE_7_R0_7: u32 = 0x07;
7971 }
7972 }
7973 #[doc = "Speed Field"]
7974 pub mod SPEED {
7975 pub const offset: u32 = 6;
7976 pub const mask: u32 = 0x03 << offset;
7977 pub mod R {}
7978 pub mod W {}
7979 pub mod RW {
7980 #[doc = "low(50MHz)"]
7981 pub const SPEED_0_LOW_50MHZ: u32 = 0;
7982 #[doc = "medium(100MHz)"]
7983 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
7984 #[doc = "medium(100MHz)"]
7985 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
7986 #[doc = "max(200MHz)"]
7987 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
7988 }
7989 }
7990 #[doc = "Open Drain Enable Field"]
7991 pub mod ODE {
7992 pub const offset: u32 = 11;
7993 pub const mask: u32 = 0x01 << offset;
7994 pub mod R {}
7995 pub mod W {}
7996 pub mod RW {
7997 #[doc = "Open Drain Disabled"]
7998 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
7999 #[doc = "Open Drain Enabled"]
8000 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
8001 }
8002 }
8003 #[doc = "Pull / Keep Enable Field"]
8004 pub mod PKE {
8005 pub const offset: u32 = 12;
8006 pub const mask: u32 = 0x01 << offset;
8007 pub mod R {}
8008 pub mod W {}
8009 pub mod RW {
8010 #[doc = "Pull/Keeper Disabled"]
8011 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
8012 #[doc = "Pull/Keeper Enabled"]
8013 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
8014 }
8015 }
8016 #[doc = "Pull / Keep Select Field"]
8017 pub mod PUE {
8018 pub const offset: u32 = 13;
8019 pub const mask: u32 = 0x01 << offset;
8020 pub mod R {}
8021 pub mod W {}
8022 pub mod RW {
8023 #[doc = "Keeper"]
8024 pub const PUE_0_KEEPER: u32 = 0;
8025 #[doc = "Pull"]
8026 pub const PUE_1_PULL: u32 = 0x01;
8027 }
8028 }
8029 #[doc = "Pull Up / Down Config. Field"]
8030 pub mod PUS {
8031 pub const offset: u32 = 14;
8032 pub const mask: u32 = 0x03 << offset;
8033 pub mod R {}
8034 pub mod W {}
8035 pub mod RW {
8036 #[doc = "100K Ohm Pull Down"]
8037 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
8038 #[doc = "47K Ohm Pull Up"]
8039 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
8040 #[doc = "100K Ohm Pull Up"]
8041 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
8042 #[doc = "22K Ohm Pull Up"]
8043 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
8044 }
8045 }
8046 #[doc = "Hyst. Enable Field"]
8047 pub mod HYS {
8048 pub const offset: u32 = 16;
8049 pub const mask: u32 = 0x01 << offset;
8050 pub mod R {}
8051 pub mod W {}
8052 pub mod RW {
8053 #[doc = "Hysteresis Disabled"]
8054 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
8055 #[doc = "Hysteresis Enabled"]
8056 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
8057 }
8058 }
8059}
8060#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_16 SW PAD Control Register"]
8061pub mod SW_PAD_CTL_PAD_GPIO_EMC_16 {
8062 #[doc = "Slew Rate Field"]
8063 pub mod SRE {
8064 pub const offset: u32 = 0;
8065 pub const mask: u32 = 0x01 << offset;
8066 pub mod R {}
8067 pub mod W {}
8068 pub mod RW {
8069 #[doc = "Slow Slew Rate"]
8070 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
8071 #[doc = "Fast Slew Rate"]
8072 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
8073 }
8074 }
8075 #[doc = "Drive Strength Field"]
8076 pub mod DSE {
8077 pub const offset: u32 = 3;
8078 pub const mask: u32 = 0x07 << offset;
8079 pub mod R {}
8080 pub mod W {}
8081 pub mod RW {
8082 #[doc = "output driver disabled;"]
8083 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
8084 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
8085 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
8086 #[doc = "R0/2"]
8087 pub const DSE_2_R0_2: u32 = 0x02;
8088 #[doc = "R0/3"]
8089 pub const DSE_3_R0_3: u32 = 0x03;
8090 #[doc = "R0/4"]
8091 pub const DSE_4_R0_4: u32 = 0x04;
8092 #[doc = "R0/5"]
8093 pub const DSE_5_R0_5: u32 = 0x05;
8094 #[doc = "R0/6"]
8095 pub const DSE_6_R0_6: u32 = 0x06;
8096 #[doc = "R0/7"]
8097 pub const DSE_7_R0_7: u32 = 0x07;
8098 }
8099 }
8100 #[doc = "Speed Field"]
8101 pub mod SPEED {
8102 pub const offset: u32 = 6;
8103 pub const mask: u32 = 0x03 << offset;
8104 pub mod R {}
8105 pub mod W {}
8106 pub mod RW {
8107 #[doc = "low(50MHz)"]
8108 pub const SPEED_0_LOW_50MHZ: u32 = 0;
8109 #[doc = "medium(100MHz)"]
8110 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
8111 #[doc = "medium(100MHz)"]
8112 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
8113 #[doc = "max(200MHz)"]
8114 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
8115 }
8116 }
8117 #[doc = "Open Drain Enable Field"]
8118 pub mod ODE {
8119 pub const offset: u32 = 11;
8120 pub const mask: u32 = 0x01 << offset;
8121 pub mod R {}
8122 pub mod W {}
8123 pub mod RW {
8124 #[doc = "Open Drain Disabled"]
8125 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
8126 #[doc = "Open Drain Enabled"]
8127 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
8128 }
8129 }
8130 #[doc = "Pull / Keep Enable Field"]
8131 pub mod PKE {
8132 pub const offset: u32 = 12;
8133 pub const mask: u32 = 0x01 << offset;
8134 pub mod R {}
8135 pub mod W {}
8136 pub mod RW {
8137 #[doc = "Pull/Keeper Disabled"]
8138 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
8139 #[doc = "Pull/Keeper Enabled"]
8140 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
8141 }
8142 }
8143 #[doc = "Pull / Keep Select Field"]
8144 pub mod PUE {
8145 pub const offset: u32 = 13;
8146 pub const mask: u32 = 0x01 << offset;
8147 pub mod R {}
8148 pub mod W {}
8149 pub mod RW {
8150 #[doc = "Keeper"]
8151 pub const PUE_0_KEEPER: u32 = 0;
8152 #[doc = "Pull"]
8153 pub const PUE_1_PULL: u32 = 0x01;
8154 }
8155 }
8156 #[doc = "Pull Up / Down Config. Field"]
8157 pub mod PUS {
8158 pub const offset: u32 = 14;
8159 pub const mask: u32 = 0x03 << offset;
8160 pub mod R {}
8161 pub mod W {}
8162 pub mod RW {
8163 #[doc = "100K Ohm Pull Down"]
8164 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
8165 #[doc = "47K Ohm Pull Up"]
8166 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
8167 #[doc = "100K Ohm Pull Up"]
8168 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
8169 #[doc = "22K Ohm Pull Up"]
8170 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
8171 }
8172 }
8173 #[doc = "Hyst. Enable Field"]
8174 pub mod HYS {
8175 pub const offset: u32 = 16;
8176 pub const mask: u32 = 0x01 << offset;
8177 pub mod R {}
8178 pub mod W {}
8179 pub mod RW {
8180 #[doc = "Hysteresis Disabled"]
8181 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
8182 #[doc = "Hysteresis Enabled"]
8183 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
8184 }
8185 }
8186}
8187#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_17 SW PAD Control Register"]
8188pub mod SW_PAD_CTL_PAD_GPIO_EMC_17 {
8189 #[doc = "Slew Rate Field"]
8190 pub mod SRE {
8191 pub const offset: u32 = 0;
8192 pub const mask: u32 = 0x01 << offset;
8193 pub mod R {}
8194 pub mod W {}
8195 pub mod RW {
8196 #[doc = "Slow Slew Rate"]
8197 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
8198 #[doc = "Fast Slew Rate"]
8199 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
8200 }
8201 }
8202 #[doc = "Drive Strength Field"]
8203 pub mod DSE {
8204 pub const offset: u32 = 3;
8205 pub const mask: u32 = 0x07 << offset;
8206 pub mod R {}
8207 pub mod W {}
8208 pub mod RW {
8209 #[doc = "output driver disabled;"]
8210 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
8211 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
8212 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
8213 #[doc = "R0/2"]
8214 pub const DSE_2_R0_2: u32 = 0x02;
8215 #[doc = "R0/3"]
8216 pub const DSE_3_R0_3: u32 = 0x03;
8217 #[doc = "R0/4"]
8218 pub const DSE_4_R0_4: u32 = 0x04;
8219 #[doc = "R0/5"]
8220 pub const DSE_5_R0_5: u32 = 0x05;
8221 #[doc = "R0/6"]
8222 pub const DSE_6_R0_6: u32 = 0x06;
8223 #[doc = "R0/7"]
8224 pub const DSE_7_R0_7: u32 = 0x07;
8225 }
8226 }
8227 #[doc = "Speed Field"]
8228 pub mod SPEED {
8229 pub const offset: u32 = 6;
8230 pub const mask: u32 = 0x03 << offset;
8231 pub mod R {}
8232 pub mod W {}
8233 pub mod RW {
8234 #[doc = "low(50MHz)"]
8235 pub const SPEED_0_LOW_50MHZ: u32 = 0;
8236 #[doc = "medium(100MHz)"]
8237 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
8238 #[doc = "medium(100MHz)"]
8239 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
8240 #[doc = "max(200MHz)"]
8241 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
8242 }
8243 }
8244 #[doc = "Open Drain Enable Field"]
8245 pub mod ODE {
8246 pub const offset: u32 = 11;
8247 pub const mask: u32 = 0x01 << offset;
8248 pub mod R {}
8249 pub mod W {}
8250 pub mod RW {
8251 #[doc = "Open Drain Disabled"]
8252 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
8253 #[doc = "Open Drain Enabled"]
8254 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
8255 }
8256 }
8257 #[doc = "Pull / Keep Enable Field"]
8258 pub mod PKE {
8259 pub const offset: u32 = 12;
8260 pub const mask: u32 = 0x01 << offset;
8261 pub mod R {}
8262 pub mod W {}
8263 pub mod RW {
8264 #[doc = "Pull/Keeper Disabled"]
8265 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
8266 #[doc = "Pull/Keeper Enabled"]
8267 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
8268 }
8269 }
8270 #[doc = "Pull / Keep Select Field"]
8271 pub mod PUE {
8272 pub const offset: u32 = 13;
8273 pub const mask: u32 = 0x01 << offset;
8274 pub mod R {}
8275 pub mod W {}
8276 pub mod RW {
8277 #[doc = "Keeper"]
8278 pub const PUE_0_KEEPER: u32 = 0;
8279 #[doc = "Pull"]
8280 pub const PUE_1_PULL: u32 = 0x01;
8281 }
8282 }
8283 #[doc = "Pull Up / Down Config. Field"]
8284 pub mod PUS {
8285 pub const offset: u32 = 14;
8286 pub const mask: u32 = 0x03 << offset;
8287 pub mod R {}
8288 pub mod W {}
8289 pub mod RW {
8290 #[doc = "100K Ohm Pull Down"]
8291 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
8292 #[doc = "47K Ohm Pull Up"]
8293 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
8294 #[doc = "100K Ohm Pull Up"]
8295 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
8296 #[doc = "22K Ohm Pull Up"]
8297 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
8298 }
8299 }
8300 #[doc = "Hyst. Enable Field"]
8301 pub mod HYS {
8302 pub const offset: u32 = 16;
8303 pub const mask: u32 = 0x01 << offset;
8304 pub mod R {}
8305 pub mod W {}
8306 pub mod RW {
8307 #[doc = "Hysteresis Disabled"]
8308 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
8309 #[doc = "Hysteresis Enabled"]
8310 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
8311 }
8312 }
8313}
8314#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_18 SW PAD Control Register"]
8315pub mod SW_PAD_CTL_PAD_GPIO_EMC_18 {
8316 #[doc = "Slew Rate Field"]
8317 pub mod SRE {
8318 pub const offset: u32 = 0;
8319 pub const mask: u32 = 0x01 << offset;
8320 pub mod R {}
8321 pub mod W {}
8322 pub mod RW {
8323 #[doc = "Slow Slew Rate"]
8324 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
8325 #[doc = "Fast Slew Rate"]
8326 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
8327 }
8328 }
8329 #[doc = "Drive Strength Field"]
8330 pub mod DSE {
8331 pub const offset: u32 = 3;
8332 pub const mask: u32 = 0x07 << offset;
8333 pub mod R {}
8334 pub mod W {}
8335 pub mod RW {
8336 #[doc = "output driver disabled;"]
8337 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
8338 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
8339 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
8340 #[doc = "R0/2"]
8341 pub const DSE_2_R0_2: u32 = 0x02;
8342 #[doc = "R0/3"]
8343 pub const DSE_3_R0_3: u32 = 0x03;
8344 #[doc = "R0/4"]
8345 pub const DSE_4_R0_4: u32 = 0x04;
8346 #[doc = "R0/5"]
8347 pub const DSE_5_R0_5: u32 = 0x05;
8348 #[doc = "R0/6"]
8349 pub const DSE_6_R0_6: u32 = 0x06;
8350 #[doc = "R0/7"]
8351 pub const DSE_7_R0_7: u32 = 0x07;
8352 }
8353 }
8354 #[doc = "Speed Field"]
8355 pub mod SPEED {
8356 pub const offset: u32 = 6;
8357 pub const mask: u32 = 0x03 << offset;
8358 pub mod R {}
8359 pub mod W {}
8360 pub mod RW {
8361 #[doc = "low(50MHz)"]
8362 pub const SPEED_0_LOW_50MHZ: u32 = 0;
8363 #[doc = "medium(100MHz)"]
8364 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
8365 #[doc = "medium(100MHz)"]
8366 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
8367 #[doc = "max(200MHz)"]
8368 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
8369 }
8370 }
8371 #[doc = "Open Drain Enable Field"]
8372 pub mod ODE {
8373 pub const offset: u32 = 11;
8374 pub const mask: u32 = 0x01 << offset;
8375 pub mod R {}
8376 pub mod W {}
8377 pub mod RW {
8378 #[doc = "Open Drain Disabled"]
8379 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
8380 #[doc = "Open Drain Enabled"]
8381 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
8382 }
8383 }
8384 #[doc = "Pull / Keep Enable Field"]
8385 pub mod PKE {
8386 pub const offset: u32 = 12;
8387 pub const mask: u32 = 0x01 << offset;
8388 pub mod R {}
8389 pub mod W {}
8390 pub mod RW {
8391 #[doc = "Pull/Keeper Disabled"]
8392 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
8393 #[doc = "Pull/Keeper Enabled"]
8394 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
8395 }
8396 }
8397 #[doc = "Pull / Keep Select Field"]
8398 pub mod PUE {
8399 pub const offset: u32 = 13;
8400 pub const mask: u32 = 0x01 << offset;
8401 pub mod R {}
8402 pub mod W {}
8403 pub mod RW {
8404 #[doc = "Keeper"]
8405 pub const PUE_0_KEEPER: u32 = 0;
8406 #[doc = "Pull"]
8407 pub const PUE_1_PULL: u32 = 0x01;
8408 }
8409 }
8410 #[doc = "Pull Up / Down Config. Field"]
8411 pub mod PUS {
8412 pub const offset: u32 = 14;
8413 pub const mask: u32 = 0x03 << offset;
8414 pub mod R {}
8415 pub mod W {}
8416 pub mod RW {
8417 #[doc = "100K Ohm Pull Down"]
8418 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
8419 #[doc = "47K Ohm Pull Up"]
8420 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
8421 #[doc = "100K Ohm Pull Up"]
8422 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
8423 #[doc = "22K Ohm Pull Up"]
8424 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
8425 }
8426 }
8427 #[doc = "Hyst. Enable Field"]
8428 pub mod HYS {
8429 pub const offset: u32 = 16;
8430 pub const mask: u32 = 0x01 << offset;
8431 pub mod R {}
8432 pub mod W {}
8433 pub mod RW {
8434 #[doc = "Hysteresis Disabled"]
8435 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
8436 #[doc = "Hysteresis Enabled"]
8437 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
8438 }
8439 }
8440}
8441#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_19 SW PAD Control Register"]
8442pub mod SW_PAD_CTL_PAD_GPIO_EMC_19 {
8443 #[doc = "Slew Rate Field"]
8444 pub mod SRE {
8445 pub const offset: u32 = 0;
8446 pub const mask: u32 = 0x01 << offset;
8447 pub mod R {}
8448 pub mod W {}
8449 pub mod RW {
8450 #[doc = "Slow Slew Rate"]
8451 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
8452 #[doc = "Fast Slew Rate"]
8453 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
8454 }
8455 }
8456 #[doc = "Drive Strength Field"]
8457 pub mod DSE {
8458 pub const offset: u32 = 3;
8459 pub const mask: u32 = 0x07 << offset;
8460 pub mod R {}
8461 pub mod W {}
8462 pub mod RW {
8463 #[doc = "output driver disabled;"]
8464 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
8465 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
8466 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
8467 #[doc = "R0/2"]
8468 pub const DSE_2_R0_2: u32 = 0x02;
8469 #[doc = "R0/3"]
8470 pub const DSE_3_R0_3: u32 = 0x03;
8471 #[doc = "R0/4"]
8472 pub const DSE_4_R0_4: u32 = 0x04;
8473 #[doc = "R0/5"]
8474 pub const DSE_5_R0_5: u32 = 0x05;
8475 #[doc = "R0/6"]
8476 pub const DSE_6_R0_6: u32 = 0x06;
8477 #[doc = "R0/7"]
8478 pub const DSE_7_R0_7: u32 = 0x07;
8479 }
8480 }
8481 #[doc = "Speed Field"]
8482 pub mod SPEED {
8483 pub const offset: u32 = 6;
8484 pub const mask: u32 = 0x03 << offset;
8485 pub mod R {}
8486 pub mod W {}
8487 pub mod RW {
8488 #[doc = "low(50MHz)"]
8489 pub const SPEED_0_LOW_50MHZ: u32 = 0;
8490 #[doc = "medium(100MHz)"]
8491 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
8492 #[doc = "medium(100MHz)"]
8493 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
8494 #[doc = "max(200MHz)"]
8495 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
8496 }
8497 }
8498 #[doc = "Open Drain Enable Field"]
8499 pub mod ODE {
8500 pub const offset: u32 = 11;
8501 pub const mask: u32 = 0x01 << offset;
8502 pub mod R {}
8503 pub mod W {}
8504 pub mod RW {
8505 #[doc = "Open Drain Disabled"]
8506 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
8507 #[doc = "Open Drain Enabled"]
8508 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
8509 }
8510 }
8511 #[doc = "Pull / Keep Enable Field"]
8512 pub mod PKE {
8513 pub const offset: u32 = 12;
8514 pub const mask: u32 = 0x01 << offset;
8515 pub mod R {}
8516 pub mod W {}
8517 pub mod RW {
8518 #[doc = "Pull/Keeper Disabled"]
8519 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
8520 #[doc = "Pull/Keeper Enabled"]
8521 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
8522 }
8523 }
8524 #[doc = "Pull / Keep Select Field"]
8525 pub mod PUE {
8526 pub const offset: u32 = 13;
8527 pub const mask: u32 = 0x01 << offset;
8528 pub mod R {}
8529 pub mod W {}
8530 pub mod RW {
8531 #[doc = "Keeper"]
8532 pub const PUE_0_KEEPER: u32 = 0;
8533 #[doc = "Pull"]
8534 pub const PUE_1_PULL: u32 = 0x01;
8535 }
8536 }
8537 #[doc = "Pull Up / Down Config. Field"]
8538 pub mod PUS {
8539 pub const offset: u32 = 14;
8540 pub const mask: u32 = 0x03 << offset;
8541 pub mod R {}
8542 pub mod W {}
8543 pub mod RW {
8544 #[doc = "100K Ohm Pull Down"]
8545 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
8546 #[doc = "47K Ohm Pull Up"]
8547 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
8548 #[doc = "100K Ohm Pull Up"]
8549 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
8550 #[doc = "22K Ohm Pull Up"]
8551 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
8552 }
8553 }
8554 #[doc = "Hyst. Enable Field"]
8555 pub mod HYS {
8556 pub const offset: u32 = 16;
8557 pub const mask: u32 = 0x01 << offset;
8558 pub mod R {}
8559 pub mod W {}
8560 pub mod RW {
8561 #[doc = "Hysteresis Disabled"]
8562 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
8563 #[doc = "Hysteresis Enabled"]
8564 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
8565 }
8566 }
8567}
8568#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_20 SW PAD Control Register"]
8569pub mod SW_PAD_CTL_PAD_GPIO_EMC_20 {
8570 #[doc = "Slew Rate Field"]
8571 pub mod SRE {
8572 pub const offset: u32 = 0;
8573 pub const mask: u32 = 0x01 << offset;
8574 pub mod R {}
8575 pub mod W {}
8576 pub mod RW {
8577 #[doc = "Slow Slew Rate"]
8578 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
8579 #[doc = "Fast Slew Rate"]
8580 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
8581 }
8582 }
8583 #[doc = "Drive Strength Field"]
8584 pub mod DSE {
8585 pub const offset: u32 = 3;
8586 pub const mask: u32 = 0x07 << offset;
8587 pub mod R {}
8588 pub mod W {}
8589 pub mod RW {
8590 #[doc = "output driver disabled;"]
8591 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
8592 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
8593 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
8594 #[doc = "R0/2"]
8595 pub const DSE_2_R0_2: u32 = 0x02;
8596 #[doc = "R0/3"]
8597 pub const DSE_3_R0_3: u32 = 0x03;
8598 #[doc = "R0/4"]
8599 pub const DSE_4_R0_4: u32 = 0x04;
8600 #[doc = "R0/5"]
8601 pub const DSE_5_R0_5: u32 = 0x05;
8602 #[doc = "R0/6"]
8603 pub const DSE_6_R0_6: u32 = 0x06;
8604 #[doc = "R0/7"]
8605 pub const DSE_7_R0_7: u32 = 0x07;
8606 }
8607 }
8608 #[doc = "Speed Field"]
8609 pub mod SPEED {
8610 pub const offset: u32 = 6;
8611 pub const mask: u32 = 0x03 << offset;
8612 pub mod R {}
8613 pub mod W {}
8614 pub mod RW {
8615 #[doc = "low(50MHz)"]
8616 pub const SPEED_0_LOW_50MHZ: u32 = 0;
8617 #[doc = "medium(100MHz)"]
8618 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
8619 #[doc = "medium(100MHz)"]
8620 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
8621 #[doc = "max(200MHz)"]
8622 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
8623 }
8624 }
8625 #[doc = "Open Drain Enable Field"]
8626 pub mod ODE {
8627 pub const offset: u32 = 11;
8628 pub const mask: u32 = 0x01 << offset;
8629 pub mod R {}
8630 pub mod W {}
8631 pub mod RW {
8632 #[doc = "Open Drain Disabled"]
8633 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
8634 #[doc = "Open Drain Enabled"]
8635 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
8636 }
8637 }
8638 #[doc = "Pull / Keep Enable Field"]
8639 pub mod PKE {
8640 pub const offset: u32 = 12;
8641 pub const mask: u32 = 0x01 << offset;
8642 pub mod R {}
8643 pub mod W {}
8644 pub mod RW {
8645 #[doc = "Pull/Keeper Disabled"]
8646 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
8647 #[doc = "Pull/Keeper Enabled"]
8648 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
8649 }
8650 }
8651 #[doc = "Pull / Keep Select Field"]
8652 pub mod PUE {
8653 pub const offset: u32 = 13;
8654 pub const mask: u32 = 0x01 << offset;
8655 pub mod R {}
8656 pub mod W {}
8657 pub mod RW {
8658 #[doc = "Keeper"]
8659 pub const PUE_0_KEEPER: u32 = 0;
8660 #[doc = "Pull"]
8661 pub const PUE_1_PULL: u32 = 0x01;
8662 }
8663 }
8664 #[doc = "Pull Up / Down Config. Field"]
8665 pub mod PUS {
8666 pub const offset: u32 = 14;
8667 pub const mask: u32 = 0x03 << offset;
8668 pub mod R {}
8669 pub mod W {}
8670 pub mod RW {
8671 #[doc = "100K Ohm Pull Down"]
8672 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
8673 #[doc = "47K Ohm Pull Up"]
8674 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
8675 #[doc = "100K Ohm Pull Up"]
8676 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
8677 #[doc = "22K Ohm Pull Up"]
8678 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
8679 }
8680 }
8681 #[doc = "Hyst. Enable Field"]
8682 pub mod HYS {
8683 pub const offset: u32 = 16;
8684 pub const mask: u32 = 0x01 << offset;
8685 pub mod R {}
8686 pub mod W {}
8687 pub mod RW {
8688 #[doc = "Hysteresis Disabled"]
8689 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
8690 #[doc = "Hysteresis Enabled"]
8691 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
8692 }
8693 }
8694}
8695#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_21 SW PAD Control Register"]
8696pub mod SW_PAD_CTL_PAD_GPIO_EMC_21 {
8697 #[doc = "Slew Rate Field"]
8698 pub mod SRE {
8699 pub const offset: u32 = 0;
8700 pub const mask: u32 = 0x01 << offset;
8701 pub mod R {}
8702 pub mod W {}
8703 pub mod RW {
8704 #[doc = "Slow Slew Rate"]
8705 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
8706 #[doc = "Fast Slew Rate"]
8707 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
8708 }
8709 }
8710 #[doc = "Drive Strength Field"]
8711 pub mod DSE {
8712 pub const offset: u32 = 3;
8713 pub const mask: u32 = 0x07 << offset;
8714 pub mod R {}
8715 pub mod W {}
8716 pub mod RW {
8717 #[doc = "output driver disabled;"]
8718 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
8719 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
8720 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
8721 #[doc = "R0/2"]
8722 pub const DSE_2_R0_2: u32 = 0x02;
8723 #[doc = "R0/3"]
8724 pub const DSE_3_R0_3: u32 = 0x03;
8725 #[doc = "R0/4"]
8726 pub const DSE_4_R0_4: u32 = 0x04;
8727 #[doc = "R0/5"]
8728 pub const DSE_5_R0_5: u32 = 0x05;
8729 #[doc = "R0/6"]
8730 pub const DSE_6_R0_6: u32 = 0x06;
8731 #[doc = "R0/7"]
8732 pub const DSE_7_R0_7: u32 = 0x07;
8733 }
8734 }
8735 #[doc = "Speed Field"]
8736 pub mod SPEED {
8737 pub const offset: u32 = 6;
8738 pub const mask: u32 = 0x03 << offset;
8739 pub mod R {}
8740 pub mod W {}
8741 pub mod RW {
8742 #[doc = "low(50MHz)"]
8743 pub const SPEED_0_LOW_50MHZ: u32 = 0;
8744 #[doc = "medium(100MHz)"]
8745 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
8746 #[doc = "medium(100MHz)"]
8747 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
8748 #[doc = "max(200MHz)"]
8749 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
8750 }
8751 }
8752 #[doc = "Open Drain Enable Field"]
8753 pub mod ODE {
8754 pub const offset: u32 = 11;
8755 pub const mask: u32 = 0x01 << offset;
8756 pub mod R {}
8757 pub mod W {}
8758 pub mod RW {
8759 #[doc = "Open Drain Disabled"]
8760 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
8761 #[doc = "Open Drain Enabled"]
8762 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
8763 }
8764 }
8765 #[doc = "Pull / Keep Enable Field"]
8766 pub mod PKE {
8767 pub const offset: u32 = 12;
8768 pub const mask: u32 = 0x01 << offset;
8769 pub mod R {}
8770 pub mod W {}
8771 pub mod RW {
8772 #[doc = "Pull/Keeper Disabled"]
8773 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
8774 #[doc = "Pull/Keeper Enabled"]
8775 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
8776 }
8777 }
8778 #[doc = "Pull / Keep Select Field"]
8779 pub mod PUE {
8780 pub const offset: u32 = 13;
8781 pub const mask: u32 = 0x01 << offset;
8782 pub mod R {}
8783 pub mod W {}
8784 pub mod RW {
8785 #[doc = "Keeper"]
8786 pub const PUE_0_KEEPER: u32 = 0;
8787 #[doc = "Pull"]
8788 pub const PUE_1_PULL: u32 = 0x01;
8789 }
8790 }
8791 #[doc = "Pull Up / Down Config. Field"]
8792 pub mod PUS {
8793 pub const offset: u32 = 14;
8794 pub const mask: u32 = 0x03 << offset;
8795 pub mod R {}
8796 pub mod W {}
8797 pub mod RW {
8798 #[doc = "100K Ohm Pull Down"]
8799 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
8800 #[doc = "47K Ohm Pull Up"]
8801 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
8802 #[doc = "100K Ohm Pull Up"]
8803 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
8804 #[doc = "22K Ohm Pull Up"]
8805 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
8806 }
8807 }
8808 #[doc = "Hyst. Enable Field"]
8809 pub mod HYS {
8810 pub const offset: u32 = 16;
8811 pub const mask: u32 = 0x01 << offset;
8812 pub mod R {}
8813 pub mod W {}
8814 pub mod RW {
8815 #[doc = "Hysteresis Disabled"]
8816 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
8817 #[doc = "Hysteresis Enabled"]
8818 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
8819 }
8820 }
8821}
8822#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_22 SW PAD Control Register"]
8823pub mod SW_PAD_CTL_PAD_GPIO_EMC_22 {
8824 #[doc = "Slew Rate Field"]
8825 pub mod SRE {
8826 pub const offset: u32 = 0;
8827 pub const mask: u32 = 0x01 << offset;
8828 pub mod R {}
8829 pub mod W {}
8830 pub mod RW {
8831 #[doc = "Slow Slew Rate"]
8832 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
8833 #[doc = "Fast Slew Rate"]
8834 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
8835 }
8836 }
8837 #[doc = "Drive Strength Field"]
8838 pub mod DSE {
8839 pub const offset: u32 = 3;
8840 pub const mask: u32 = 0x07 << offset;
8841 pub mod R {}
8842 pub mod W {}
8843 pub mod RW {
8844 #[doc = "output driver disabled;"]
8845 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
8846 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
8847 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
8848 #[doc = "R0/2"]
8849 pub const DSE_2_R0_2: u32 = 0x02;
8850 #[doc = "R0/3"]
8851 pub const DSE_3_R0_3: u32 = 0x03;
8852 #[doc = "R0/4"]
8853 pub const DSE_4_R0_4: u32 = 0x04;
8854 #[doc = "R0/5"]
8855 pub const DSE_5_R0_5: u32 = 0x05;
8856 #[doc = "R0/6"]
8857 pub const DSE_6_R0_6: u32 = 0x06;
8858 #[doc = "R0/7"]
8859 pub const DSE_7_R0_7: u32 = 0x07;
8860 }
8861 }
8862 #[doc = "Speed Field"]
8863 pub mod SPEED {
8864 pub const offset: u32 = 6;
8865 pub const mask: u32 = 0x03 << offset;
8866 pub mod R {}
8867 pub mod W {}
8868 pub mod RW {
8869 #[doc = "low(50MHz)"]
8870 pub const SPEED_0_LOW_50MHZ: u32 = 0;
8871 #[doc = "medium(100MHz)"]
8872 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
8873 #[doc = "medium(100MHz)"]
8874 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
8875 #[doc = "max(200MHz)"]
8876 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
8877 }
8878 }
8879 #[doc = "Open Drain Enable Field"]
8880 pub mod ODE {
8881 pub const offset: u32 = 11;
8882 pub const mask: u32 = 0x01 << offset;
8883 pub mod R {}
8884 pub mod W {}
8885 pub mod RW {
8886 #[doc = "Open Drain Disabled"]
8887 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
8888 #[doc = "Open Drain Enabled"]
8889 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
8890 }
8891 }
8892 #[doc = "Pull / Keep Enable Field"]
8893 pub mod PKE {
8894 pub const offset: u32 = 12;
8895 pub const mask: u32 = 0x01 << offset;
8896 pub mod R {}
8897 pub mod W {}
8898 pub mod RW {
8899 #[doc = "Pull/Keeper Disabled"]
8900 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
8901 #[doc = "Pull/Keeper Enabled"]
8902 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
8903 }
8904 }
8905 #[doc = "Pull / Keep Select Field"]
8906 pub mod PUE {
8907 pub const offset: u32 = 13;
8908 pub const mask: u32 = 0x01 << offset;
8909 pub mod R {}
8910 pub mod W {}
8911 pub mod RW {
8912 #[doc = "Keeper"]
8913 pub const PUE_0_KEEPER: u32 = 0;
8914 #[doc = "Pull"]
8915 pub const PUE_1_PULL: u32 = 0x01;
8916 }
8917 }
8918 #[doc = "Pull Up / Down Config. Field"]
8919 pub mod PUS {
8920 pub const offset: u32 = 14;
8921 pub const mask: u32 = 0x03 << offset;
8922 pub mod R {}
8923 pub mod W {}
8924 pub mod RW {
8925 #[doc = "100K Ohm Pull Down"]
8926 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
8927 #[doc = "47K Ohm Pull Up"]
8928 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
8929 #[doc = "100K Ohm Pull Up"]
8930 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
8931 #[doc = "22K Ohm Pull Up"]
8932 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
8933 }
8934 }
8935 #[doc = "Hyst. Enable Field"]
8936 pub mod HYS {
8937 pub const offset: u32 = 16;
8938 pub const mask: u32 = 0x01 << offset;
8939 pub mod R {}
8940 pub mod W {}
8941 pub mod RW {
8942 #[doc = "Hysteresis Disabled"]
8943 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
8944 #[doc = "Hysteresis Enabled"]
8945 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
8946 }
8947 }
8948}
8949#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_23 SW PAD Control Register"]
8950pub mod SW_PAD_CTL_PAD_GPIO_EMC_23 {
8951 #[doc = "Slew Rate Field"]
8952 pub mod SRE {
8953 pub const offset: u32 = 0;
8954 pub const mask: u32 = 0x01 << offset;
8955 pub mod R {}
8956 pub mod W {}
8957 pub mod RW {
8958 #[doc = "Slow Slew Rate"]
8959 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
8960 #[doc = "Fast Slew Rate"]
8961 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
8962 }
8963 }
8964 #[doc = "Drive Strength Field"]
8965 pub mod DSE {
8966 pub const offset: u32 = 3;
8967 pub const mask: u32 = 0x07 << offset;
8968 pub mod R {}
8969 pub mod W {}
8970 pub mod RW {
8971 #[doc = "output driver disabled;"]
8972 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
8973 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
8974 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
8975 #[doc = "R0/2"]
8976 pub const DSE_2_R0_2: u32 = 0x02;
8977 #[doc = "R0/3"]
8978 pub const DSE_3_R0_3: u32 = 0x03;
8979 #[doc = "R0/4"]
8980 pub const DSE_4_R0_4: u32 = 0x04;
8981 #[doc = "R0/5"]
8982 pub const DSE_5_R0_5: u32 = 0x05;
8983 #[doc = "R0/6"]
8984 pub const DSE_6_R0_6: u32 = 0x06;
8985 #[doc = "R0/7"]
8986 pub const DSE_7_R0_7: u32 = 0x07;
8987 }
8988 }
8989 #[doc = "Speed Field"]
8990 pub mod SPEED {
8991 pub const offset: u32 = 6;
8992 pub const mask: u32 = 0x03 << offset;
8993 pub mod R {}
8994 pub mod W {}
8995 pub mod RW {
8996 #[doc = "low(50MHz)"]
8997 pub const SPEED_0_LOW_50MHZ: u32 = 0;
8998 #[doc = "medium(100MHz)"]
8999 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
9000 #[doc = "medium(100MHz)"]
9001 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
9002 #[doc = "max(200MHz)"]
9003 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
9004 }
9005 }
9006 #[doc = "Open Drain Enable Field"]
9007 pub mod ODE {
9008 pub const offset: u32 = 11;
9009 pub const mask: u32 = 0x01 << offset;
9010 pub mod R {}
9011 pub mod W {}
9012 pub mod RW {
9013 #[doc = "Open Drain Disabled"]
9014 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
9015 #[doc = "Open Drain Enabled"]
9016 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
9017 }
9018 }
9019 #[doc = "Pull / Keep Enable Field"]
9020 pub mod PKE {
9021 pub const offset: u32 = 12;
9022 pub const mask: u32 = 0x01 << offset;
9023 pub mod R {}
9024 pub mod W {}
9025 pub mod RW {
9026 #[doc = "Pull/Keeper Disabled"]
9027 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
9028 #[doc = "Pull/Keeper Enabled"]
9029 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
9030 }
9031 }
9032 #[doc = "Pull / Keep Select Field"]
9033 pub mod PUE {
9034 pub const offset: u32 = 13;
9035 pub const mask: u32 = 0x01 << offset;
9036 pub mod R {}
9037 pub mod W {}
9038 pub mod RW {
9039 #[doc = "Keeper"]
9040 pub const PUE_0_KEEPER: u32 = 0;
9041 #[doc = "Pull"]
9042 pub const PUE_1_PULL: u32 = 0x01;
9043 }
9044 }
9045 #[doc = "Pull Up / Down Config. Field"]
9046 pub mod PUS {
9047 pub const offset: u32 = 14;
9048 pub const mask: u32 = 0x03 << offset;
9049 pub mod R {}
9050 pub mod W {}
9051 pub mod RW {
9052 #[doc = "100K Ohm Pull Down"]
9053 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
9054 #[doc = "47K Ohm Pull Up"]
9055 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
9056 #[doc = "100K Ohm Pull Up"]
9057 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
9058 #[doc = "22K Ohm Pull Up"]
9059 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
9060 }
9061 }
9062 #[doc = "Hyst. Enable Field"]
9063 pub mod HYS {
9064 pub const offset: u32 = 16;
9065 pub const mask: u32 = 0x01 << offset;
9066 pub mod R {}
9067 pub mod W {}
9068 pub mod RW {
9069 #[doc = "Hysteresis Disabled"]
9070 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
9071 #[doc = "Hysteresis Enabled"]
9072 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
9073 }
9074 }
9075}
9076#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_24 SW PAD Control Register"]
9077pub mod SW_PAD_CTL_PAD_GPIO_EMC_24 {
9078 #[doc = "Slew Rate Field"]
9079 pub mod SRE {
9080 pub const offset: u32 = 0;
9081 pub const mask: u32 = 0x01 << offset;
9082 pub mod R {}
9083 pub mod W {}
9084 pub mod RW {
9085 #[doc = "Slow Slew Rate"]
9086 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
9087 #[doc = "Fast Slew Rate"]
9088 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
9089 }
9090 }
9091 #[doc = "Drive Strength Field"]
9092 pub mod DSE {
9093 pub const offset: u32 = 3;
9094 pub const mask: u32 = 0x07 << offset;
9095 pub mod R {}
9096 pub mod W {}
9097 pub mod RW {
9098 #[doc = "output driver disabled;"]
9099 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
9100 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
9101 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
9102 #[doc = "R0/2"]
9103 pub const DSE_2_R0_2: u32 = 0x02;
9104 #[doc = "R0/3"]
9105 pub const DSE_3_R0_3: u32 = 0x03;
9106 #[doc = "R0/4"]
9107 pub const DSE_4_R0_4: u32 = 0x04;
9108 #[doc = "R0/5"]
9109 pub const DSE_5_R0_5: u32 = 0x05;
9110 #[doc = "R0/6"]
9111 pub const DSE_6_R0_6: u32 = 0x06;
9112 #[doc = "R0/7"]
9113 pub const DSE_7_R0_7: u32 = 0x07;
9114 }
9115 }
9116 #[doc = "Speed Field"]
9117 pub mod SPEED {
9118 pub const offset: u32 = 6;
9119 pub const mask: u32 = 0x03 << offset;
9120 pub mod R {}
9121 pub mod W {}
9122 pub mod RW {
9123 #[doc = "low(50MHz)"]
9124 pub const SPEED_0_LOW_50MHZ: u32 = 0;
9125 #[doc = "medium(100MHz)"]
9126 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
9127 #[doc = "medium(100MHz)"]
9128 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
9129 #[doc = "max(200MHz)"]
9130 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
9131 }
9132 }
9133 #[doc = "Open Drain Enable Field"]
9134 pub mod ODE {
9135 pub const offset: u32 = 11;
9136 pub const mask: u32 = 0x01 << offset;
9137 pub mod R {}
9138 pub mod W {}
9139 pub mod RW {
9140 #[doc = "Open Drain Disabled"]
9141 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
9142 #[doc = "Open Drain Enabled"]
9143 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
9144 }
9145 }
9146 #[doc = "Pull / Keep Enable Field"]
9147 pub mod PKE {
9148 pub const offset: u32 = 12;
9149 pub const mask: u32 = 0x01 << offset;
9150 pub mod R {}
9151 pub mod W {}
9152 pub mod RW {
9153 #[doc = "Pull/Keeper Disabled"]
9154 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
9155 #[doc = "Pull/Keeper Enabled"]
9156 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
9157 }
9158 }
9159 #[doc = "Pull / Keep Select Field"]
9160 pub mod PUE {
9161 pub const offset: u32 = 13;
9162 pub const mask: u32 = 0x01 << offset;
9163 pub mod R {}
9164 pub mod W {}
9165 pub mod RW {
9166 #[doc = "Keeper"]
9167 pub const PUE_0_KEEPER: u32 = 0;
9168 #[doc = "Pull"]
9169 pub const PUE_1_PULL: u32 = 0x01;
9170 }
9171 }
9172 #[doc = "Pull Up / Down Config. Field"]
9173 pub mod PUS {
9174 pub const offset: u32 = 14;
9175 pub const mask: u32 = 0x03 << offset;
9176 pub mod R {}
9177 pub mod W {}
9178 pub mod RW {
9179 #[doc = "100K Ohm Pull Down"]
9180 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
9181 #[doc = "47K Ohm Pull Up"]
9182 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
9183 #[doc = "100K Ohm Pull Up"]
9184 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
9185 #[doc = "22K Ohm Pull Up"]
9186 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
9187 }
9188 }
9189 #[doc = "Hyst. Enable Field"]
9190 pub mod HYS {
9191 pub const offset: u32 = 16;
9192 pub const mask: u32 = 0x01 << offset;
9193 pub mod R {}
9194 pub mod W {}
9195 pub mod RW {
9196 #[doc = "Hysteresis Disabled"]
9197 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
9198 #[doc = "Hysteresis Enabled"]
9199 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
9200 }
9201 }
9202}
9203#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_25 SW PAD Control Register"]
9204pub mod SW_PAD_CTL_PAD_GPIO_EMC_25 {
9205 #[doc = "Slew Rate Field"]
9206 pub mod SRE {
9207 pub const offset: u32 = 0;
9208 pub const mask: u32 = 0x01 << offset;
9209 pub mod R {}
9210 pub mod W {}
9211 pub mod RW {
9212 #[doc = "Slow Slew Rate"]
9213 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
9214 #[doc = "Fast Slew Rate"]
9215 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
9216 }
9217 }
9218 #[doc = "Drive Strength Field"]
9219 pub mod DSE {
9220 pub const offset: u32 = 3;
9221 pub const mask: u32 = 0x07 << offset;
9222 pub mod R {}
9223 pub mod W {}
9224 pub mod RW {
9225 #[doc = "output driver disabled;"]
9226 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
9227 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
9228 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
9229 #[doc = "R0/2"]
9230 pub const DSE_2_R0_2: u32 = 0x02;
9231 #[doc = "R0/3"]
9232 pub const DSE_3_R0_3: u32 = 0x03;
9233 #[doc = "R0/4"]
9234 pub const DSE_4_R0_4: u32 = 0x04;
9235 #[doc = "R0/5"]
9236 pub const DSE_5_R0_5: u32 = 0x05;
9237 #[doc = "R0/6"]
9238 pub const DSE_6_R0_6: u32 = 0x06;
9239 #[doc = "R0/7"]
9240 pub const DSE_7_R0_7: u32 = 0x07;
9241 }
9242 }
9243 #[doc = "Speed Field"]
9244 pub mod SPEED {
9245 pub const offset: u32 = 6;
9246 pub const mask: u32 = 0x03 << offset;
9247 pub mod R {}
9248 pub mod W {}
9249 pub mod RW {
9250 #[doc = "low(50MHz)"]
9251 pub const SPEED_0_LOW_50MHZ: u32 = 0;
9252 #[doc = "medium(100MHz)"]
9253 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
9254 #[doc = "medium(100MHz)"]
9255 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
9256 #[doc = "max(200MHz)"]
9257 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
9258 }
9259 }
9260 #[doc = "Open Drain Enable Field"]
9261 pub mod ODE {
9262 pub const offset: u32 = 11;
9263 pub const mask: u32 = 0x01 << offset;
9264 pub mod R {}
9265 pub mod W {}
9266 pub mod RW {
9267 #[doc = "Open Drain Disabled"]
9268 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
9269 #[doc = "Open Drain Enabled"]
9270 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
9271 }
9272 }
9273 #[doc = "Pull / Keep Enable Field"]
9274 pub mod PKE {
9275 pub const offset: u32 = 12;
9276 pub const mask: u32 = 0x01 << offset;
9277 pub mod R {}
9278 pub mod W {}
9279 pub mod RW {
9280 #[doc = "Pull/Keeper Disabled"]
9281 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
9282 #[doc = "Pull/Keeper Enabled"]
9283 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
9284 }
9285 }
9286 #[doc = "Pull / Keep Select Field"]
9287 pub mod PUE {
9288 pub const offset: u32 = 13;
9289 pub const mask: u32 = 0x01 << offset;
9290 pub mod R {}
9291 pub mod W {}
9292 pub mod RW {
9293 #[doc = "Keeper"]
9294 pub const PUE_0_KEEPER: u32 = 0;
9295 #[doc = "Pull"]
9296 pub const PUE_1_PULL: u32 = 0x01;
9297 }
9298 }
9299 #[doc = "Pull Up / Down Config. Field"]
9300 pub mod PUS {
9301 pub const offset: u32 = 14;
9302 pub const mask: u32 = 0x03 << offset;
9303 pub mod R {}
9304 pub mod W {}
9305 pub mod RW {
9306 #[doc = "100K Ohm Pull Down"]
9307 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
9308 #[doc = "47K Ohm Pull Up"]
9309 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
9310 #[doc = "100K Ohm Pull Up"]
9311 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
9312 #[doc = "22K Ohm Pull Up"]
9313 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
9314 }
9315 }
9316 #[doc = "Hyst. Enable Field"]
9317 pub mod HYS {
9318 pub const offset: u32 = 16;
9319 pub const mask: u32 = 0x01 << offset;
9320 pub mod R {}
9321 pub mod W {}
9322 pub mod RW {
9323 #[doc = "Hysteresis Disabled"]
9324 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
9325 #[doc = "Hysteresis Enabled"]
9326 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
9327 }
9328 }
9329}
9330#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_26 SW PAD Control Register"]
9331pub mod SW_PAD_CTL_PAD_GPIO_EMC_26 {
9332 #[doc = "Slew Rate Field"]
9333 pub mod SRE {
9334 pub const offset: u32 = 0;
9335 pub const mask: u32 = 0x01 << offset;
9336 pub mod R {}
9337 pub mod W {}
9338 pub mod RW {
9339 #[doc = "Slow Slew Rate"]
9340 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
9341 #[doc = "Fast Slew Rate"]
9342 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
9343 }
9344 }
9345 #[doc = "Drive Strength Field"]
9346 pub mod DSE {
9347 pub const offset: u32 = 3;
9348 pub const mask: u32 = 0x07 << offset;
9349 pub mod R {}
9350 pub mod W {}
9351 pub mod RW {
9352 #[doc = "output driver disabled;"]
9353 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
9354 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
9355 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
9356 #[doc = "R0/2"]
9357 pub const DSE_2_R0_2: u32 = 0x02;
9358 #[doc = "R0/3"]
9359 pub const DSE_3_R0_3: u32 = 0x03;
9360 #[doc = "R0/4"]
9361 pub const DSE_4_R0_4: u32 = 0x04;
9362 #[doc = "R0/5"]
9363 pub const DSE_5_R0_5: u32 = 0x05;
9364 #[doc = "R0/6"]
9365 pub const DSE_6_R0_6: u32 = 0x06;
9366 #[doc = "R0/7"]
9367 pub const DSE_7_R0_7: u32 = 0x07;
9368 }
9369 }
9370 #[doc = "Speed Field"]
9371 pub mod SPEED {
9372 pub const offset: u32 = 6;
9373 pub const mask: u32 = 0x03 << offset;
9374 pub mod R {}
9375 pub mod W {}
9376 pub mod RW {
9377 #[doc = "low(50MHz)"]
9378 pub const SPEED_0_LOW_50MHZ: u32 = 0;
9379 #[doc = "medium(100MHz)"]
9380 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
9381 #[doc = "medium(100MHz)"]
9382 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
9383 #[doc = "max(200MHz)"]
9384 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
9385 }
9386 }
9387 #[doc = "Open Drain Enable Field"]
9388 pub mod ODE {
9389 pub const offset: u32 = 11;
9390 pub const mask: u32 = 0x01 << offset;
9391 pub mod R {}
9392 pub mod W {}
9393 pub mod RW {
9394 #[doc = "Open Drain Disabled"]
9395 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
9396 #[doc = "Open Drain Enabled"]
9397 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
9398 }
9399 }
9400 #[doc = "Pull / Keep Enable Field"]
9401 pub mod PKE {
9402 pub const offset: u32 = 12;
9403 pub const mask: u32 = 0x01 << offset;
9404 pub mod R {}
9405 pub mod W {}
9406 pub mod RW {
9407 #[doc = "Pull/Keeper Disabled"]
9408 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
9409 #[doc = "Pull/Keeper Enabled"]
9410 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
9411 }
9412 }
9413 #[doc = "Pull / Keep Select Field"]
9414 pub mod PUE {
9415 pub const offset: u32 = 13;
9416 pub const mask: u32 = 0x01 << offset;
9417 pub mod R {}
9418 pub mod W {}
9419 pub mod RW {
9420 #[doc = "Keeper"]
9421 pub const PUE_0_KEEPER: u32 = 0;
9422 #[doc = "Pull"]
9423 pub const PUE_1_PULL: u32 = 0x01;
9424 }
9425 }
9426 #[doc = "Pull Up / Down Config. Field"]
9427 pub mod PUS {
9428 pub const offset: u32 = 14;
9429 pub const mask: u32 = 0x03 << offset;
9430 pub mod R {}
9431 pub mod W {}
9432 pub mod RW {
9433 #[doc = "100K Ohm Pull Down"]
9434 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
9435 #[doc = "47K Ohm Pull Up"]
9436 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
9437 #[doc = "100K Ohm Pull Up"]
9438 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
9439 #[doc = "22K Ohm Pull Up"]
9440 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
9441 }
9442 }
9443 #[doc = "Hyst. Enable Field"]
9444 pub mod HYS {
9445 pub const offset: u32 = 16;
9446 pub const mask: u32 = 0x01 << offset;
9447 pub mod R {}
9448 pub mod W {}
9449 pub mod RW {
9450 #[doc = "Hysteresis Disabled"]
9451 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
9452 #[doc = "Hysteresis Enabled"]
9453 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
9454 }
9455 }
9456}
9457#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_27 SW PAD Control Register"]
9458pub mod SW_PAD_CTL_PAD_GPIO_EMC_27 {
9459 #[doc = "Slew Rate Field"]
9460 pub mod SRE {
9461 pub const offset: u32 = 0;
9462 pub const mask: u32 = 0x01 << offset;
9463 pub mod R {}
9464 pub mod W {}
9465 pub mod RW {
9466 #[doc = "Slow Slew Rate"]
9467 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
9468 #[doc = "Fast Slew Rate"]
9469 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
9470 }
9471 }
9472 #[doc = "Drive Strength Field"]
9473 pub mod DSE {
9474 pub const offset: u32 = 3;
9475 pub const mask: u32 = 0x07 << offset;
9476 pub mod R {}
9477 pub mod W {}
9478 pub mod RW {
9479 #[doc = "output driver disabled;"]
9480 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
9481 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
9482 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
9483 #[doc = "R0/2"]
9484 pub const DSE_2_R0_2: u32 = 0x02;
9485 #[doc = "R0/3"]
9486 pub const DSE_3_R0_3: u32 = 0x03;
9487 #[doc = "R0/4"]
9488 pub const DSE_4_R0_4: u32 = 0x04;
9489 #[doc = "R0/5"]
9490 pub const DSE_5_R0_5: u32 = 0x05;
9491 #[doc = "R0/6"]
9492 pub const DSE_6_R0_6: u32 = 0x06;
9493 #[doc = "R0/7"]
9494 pub const DSE_7_R0_7: u32 = 0x07;
9495 }
9496 }
9497 #[doc = "Speed Field"]
9498 pub mod SPEED {
9499 pub const offset: u32 = 6;
9500 pub const mask: u32 = 0x03 << offset;
9501 pub mod R {}
9502 pub mod W {}
9503 pub mod RW {
9504 #[doc = "low(50MHz)"]
9505 pub const SPEED_0_LOW_50MHZ: u32 = 0;
9506 #[doc = "medium(100MHz)"]
9507 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
9508 #[doc = "medium(100MHz)"]
9509 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
9510 #[doc = "max(200MHz)"]
9511 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
9512 }
9513 }
9514 #[doc = "Open Drain Enable Field"]
9515 pub mod ODE {
9516 pub const offset: u32 = 11;
9517 pub const mask: u32 = 0x01 << offset;
9518 pub mod R {}
9519 pub mod W {}
9520 pub mod RW {
9521 #[doc = "Open Drain Disabled"]
9522 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
9523 #[doc = "Open Drain Enabled"]
9524 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
9525 }
9526 }
9527 #[doc = "Pull / Keep Enable Field"]
9528 pub mod PKE {
9529 pub const offset: u32 = 12;
9530 pub const mask: u32 = 0x01 << offset;
9531 pub mod R {}
9532 pub mod W {}
9533 pub mod RW {
9534 #[doc = "Pull/Keeper Disabled"]
9535 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
9536 #[doc = "Pull/Keeper Enabled"]
9537 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
9538 }
9539 }
9540 #[doc = "Pull / Keep Select Field"]
9541 pub mod PUE {
9542 pub const offset: u32 = 13;
9543 pub const mask: u32 = 0x01 << offset;
9544 pub mod R {}
9545 pub mod W {}
9546 pub mod RW {
9547 #[doc = "Keeper"]
9548 pub const PUE_0_KEEPER: u32 = 0;
9549 #[doc = "Pull"]
9550 pub const PUE_1_PULL: u32 = 0x01;
9551 }
9552 }
9553 #[doc = "Pull Up / Down Config. Field"]
9554 pub mod PUS {
9555 pub const offset: u32 = 14;
9556 pub const mask: u32 = 0x03 << offset;
9557 pub mod R {}
9558 pub mod W {}
9559 pub mod RW {
9560 #[doc = "100K Ohm Pull Down"]
9561 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
9562 #[doc = "47K Ohm Pull Up"]
9563 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
9564 #[doc = "100K Ohm Pull Up"]
9565 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
9566 #[doc = "22K Ohm Pull Up"]
9567 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
9568 }
9569 }
9570 #[doc = "Hyst. Enable Field"]
9571 pub mod HYS {
9572 pub const offset: u32 = 16;
9573 pub const mask: u32 = 0x01 << offset;
9574 pub mod R {}
9575 pub mod W {}
9576 pub mod RW {
9577 #[doc = "Hysteresis Disabled"]
9578 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
9579 #[doc = "Hysteresis Enabled"]
9580 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
9581 }
9582 }
9583}
9584#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_28 SW PAD Control Register"]
9585pub mod SW_PAD_CTL_PAD_GPIO_EMC_28 {
9586 #[doc = "Slew Rate Field"]
9587 pub mod SRE {
9588 pub const offset: u32 = 0;
9589 pub const mask: u32 = 0x01 << offset;
9590 pub mod R {}
9591 pub mod W {}
9592 pub mod RW {
9593 #[doc = "Slow Slew Rate"]
9594 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
9595 #[doc = "Fast Slew Rate"]
9596 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
9597 }
9598 }
9599 #[doc = "Drive Strength Field"]
9600 pub mod DSE {
9601 pub const offset: u32 = 3;
9602 pub const mask: u32 = 0x07 << offset;
9603 pub mod R {}
9604 pub mod W {}
9605 pub mod RW {
9606 #[doc = "output driver disabled;"]
9607 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
9608 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
9609 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
9610 #[doc = "R0/2"]
9611 pub const DSE_2_R0_2: u32 = 0x02;
9612 #[doc = "R0/3"]
9613 pub const DSE_3_R0_3: u32 = 0x03;
9614 #[doc = "R0/4"]
9615 pub const DSE_4_R0_4: u32 = 0x04;
9616 #[doc = "R0/5"]
9617 pub const DSE_5_R0_5: u32 = 0x05;
9618 #[doc = "R0/6"]
9619 pub const DSE_6_R0_6: u32 = 0x06;
9620 #[doc = "R0/7"]
9621 pub const DSE_7_R0_7: u32 = 0x07;
9622 }
9623 }
9624 #[doc = "Speed Field"]
9625 pub mod SPEED {
9626 pub const offset: u32 = 6;
9627 pub const mask: u32 = 0x03 << offset;
9628 pub mod R {}
9629 pub mod W {}
9630 pub mod RW {
9631 #[doc = "low(50MHz)"]
9632 pub const SPEED_0_LOW_50MHZ: u32 = 0;
9633 #[doc = "medium(100MHz)"]
9634 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
9635 #[doc = "medium(100MHz)"]
9636 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
9637 #[doc = "max(200MHz)"]
9638 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
9639 }
9640 }
9641 #[doc = "Open Drain Enable Field"]
9642 pub mod ODE {
9643 pub const offset: u32 = 11;
9644 pub const mask: u32 = 0x01 << offset;
9645 pub mod R {}
9646 pub mod W {}
9647 pub mod RW {
9648 #[doc = "Open Drain Disabled"]
9649 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
9650 #[doc = "Open Drain Enabled"]
9651 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
9652 }
9653 }
9654 #[doc = "Pull / Keep Enable Field"]
9655 pub mod PKE {
9656 pub const offset: u32 = 12;
9657 pub const mask: u32 = 0x01 << offset;
9658 pub mod R {}
9659 pub mod W {}
9660 pub mod RW {
9661 #[doc = "Pull/Keeper Disabled"]
9662 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
9663 #[doc = "Pull/Keeper Enabled"]
9664 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
9665 }
9666 }
9667 #[doc = "Pull / Keep Select Field"]
9668 pub mod PUE {
9669 pub const offset: u32 = 13;
9670 pub const mask: u32 = 0x01 << offset;
9671 pub mod R {}
9672 pub mod W {}
9673 pub mod RW {
9674 #[doc = "Keeper"]
9675 pub const PUE_0_KEEPER: u32 = 0;
9676 #[doc = "Pull"]
9677 pub const PUE_1_PULL: u32 = 0x01;
9678 }
9679 }
9680 #[doc = "Pull Up / Down Config. Field"]
9681 pub mod PUS {
9682 pub const offset: u32 = 14;
9683 pub const mask: u32 = 0x03 << offset;
9684 pub mod R {}
9685 pub mod W {}
9686 pub mod RW {
9687 #[doc = "100K Ohm Pull Down"]
9688 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
9689 #[doc = "47K Ohm Pull Up"]
9690 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
9691 #[doc = "100K Ohm Pull Up"]
9692 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
9693 #[doc = "22K Ohm Pull Up"]
9694 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
9695 }
9696 }
9697 #[doc = "Hyst. Enable Field"]
9698 pub mod HYS {
9699 pub const offset: u32 = 16;
9700 pub const mask: u32 = 0x01 << offset;
9701 pub mod R {}
9702 pub mod W {}
9703 pub mod RW {
9704 #[doc = "Hysteresis Disabled"]
9705 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
9706 #[doc = "Hysteresis Enabled"]
9707 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
9708 }
9709 }
9710}
9711#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_29 SW PAD Control Register"]
9712pub mod SW_PAD_CTL_PAD_GPIO_EMC_29 {
9713 #[doc = "Slew Rate Field"]
9714 pub mod SRE {
9715 pub const offset: u32 = 0;
9716 pub const mask: u32 = 0x01 << offset;
9717 pub mod R {}
9718 pub mod W {}
9719 pub mod RW {
9720 #[doc = "Slow Slew Rate"]
9721 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
9722 #[doc = "Fast Slew Rate"]
9723 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
9724 }
9725 }
9726 #[doc = "Drive Strength Field"]
9727 pub mod DSE {
9728 pub const offset: u32 = 3;
9729 pub const mask: u32 = 0x07 << offset;
9730 pub mod R {}
9731 pub mod W {}
9732 pub mod RW {
9733 #[doc = "output driver disabled;"]
9734 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
9735 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
9736 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
9737 #[doc = "R0/2"]
9738 pub const DSE_2_R0_2: u32 = 0x02;
9739 #[doc = "R0/3"]
9740 pub const DSE_3_R0_3: u32 = 0x03;
9741 #[doc = "R0/4"]
9742 pub const DSE_4_R0_4: u32 = 0x04;
9743 #[doc = "R0/5"]
9744 pub const DSE_5_R0_5: u32 = 0x05;
9745 #[doc = "R0/6"]
9746 pub const DSE_6_R0_6: u32 = 0x06;
9747 #[doc = "R0/7"]
9748 pub const DSE_7_R0_7: u32 = 0x07;
9749 }
9750 }
9751 #[doc = "Speed Field"]
9752 pub mod SPEED {
9753 pub const offset: u32 = 6;
9754 pub const mask: u32 = 0x03 << offset;
9755 pub mod R {}
9756 pub mod W {}
9757 pub mod RW {
9758 #[doc = "low(50MHz)"]
9759 pub const SPEED_0_LOW_50MHZ: u32 = 0;
9760 #[doc = "medium(100MHz)"]
9761 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
9762 #[doc = "medium(100MHz)"]
9763 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
9764 #[doc = "max(200MHz)"]
9765 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
9766 }
9767 }
9768 #[doc = "Open Drain Enable Field"]
9769 pub mod ODE {
9770 pub const offset: u32 = 11;
9771 pub const mask: u32 = 0x01 << offset;
9772 pub mod R {}
9773 pub mod W {}
9774 pub mod RW {
9775 #[doc = "Open Drain Disabled"]
9776 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
9777 #[doc = "Open Drain Enabled"]
9778 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
9779 }
9780 }
9781 #[doc = "Pull / Keep Enable Field"]
9782 pub mod PKE {
9783 pub const offset: u32 = 12;
9784 pub const mask: u32 = 0x01 << offset;
9785 pub mod R {}
9786 pub mod W {}
9787 pub mod RW {
9788 #[doc = "Pull/Keeper Disabled"]
9789 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
9790 #[doc = "Pull/Keeper Enabled"]
9791 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
9792 }
9793 }
9794 #[doc = "Pull / Keep Select Field"]
9795 pub mod PUE {
9796 pub const offset: u32 = 13;
9797 pub const mask: u32 = 0x01 << offset;
9798 pub mod R {}
9799 pub mod W {}
9800 pub mod RW {
9801 #[doc = "Keeper"]
9802 pub const PUE_0_KEEPER: u32 = 0;
9803 #[doc = "Pull"]
9804 pub const PUE_1_PULL: u32 = 0x01;
9805 }
9806 }
9807 #[doc = "Pull Up / Down Config. Field"]
9808 pub mod PUS {
9809 pub const offset: u32 = 14;
9810 pub const mask: u32 = 0x03 << offset;
9811 pub mod R {}
9812 pub mod W {}
9813 pub mod RW {
9814 #[doc = "100K Ohm Pull Down"]
9815 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
9816 #[doc = "47K Ohm Pull Up"]
9817 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
9818 #[doc = "100K Ohm Pull Up"]
9819 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
9820 #[doc = "22K Ohm Pull Up"]
9821 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
9822 }
9823 }
9824 #[doc = "Hyst. Enable Field"]
9825 pub mod HYS {
9826 pub const offset: u32 = 16;
9827 pub const mask: u32 = 0x01 << offset;
9828 pub mod R {}
9829 pub mod W {}
9830 pub mod RW {
9831 #[doc = "Hysteresis Disabled"]
9832 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
9833 #[doc = "Hysteresis Enabled"]
9834 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
9835 }
9836 }
9837}
9838#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_30 SW PAD Control Register"]
9839pub mod SW_PAD_CTL_PAD_GPIO_EMC_30 {
9840 #[doc = "Slew Rate Field"]
9841 pub mod SRE {
9842 pub const offset: u32 = 0;
9843 pub const mask: u32 = 0x01 << offset;
9844 pub mod R {}
9845 pub mod W {}
9846 pub mod RW {
9847 #[doc = "Slow Slew Rate"]
9848 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
9849 #[doc = "Fast Slew Rate"]
9850 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
9851 }
9852 }
9853 #[doc = "Drive Strength Field"]
9854 pub mod DSE {
9855 pub const offset: u32 = 3;
9856 pub const mask: u32 = 0x07 << offset;
9857 pub mod R {}
9858 pub mod W {}
9859 pub mod RW {
9860 #[doc = "output driver disabled;"]
9861 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
9862 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
9863 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
9864 #[doc = "R0/2"]
9865 pub const DSE_2_R0_2: u32 = 0x02;
9866 #[doc = "R0/3"]
9867 pub const DSE_3_R0_3: u32 = 0x03;
9868 #[doc = "R0/4"]
9869 pub const DSE_4_R0_4: u32 = 0x04;
9870 #[doc = "R0/5"]
9871 pub const DSE_5_R0_5: u32 = 0x05;
9872 #[doc = "R0/6"]
9873 pub const DSE_6_R0_6: u32 = 0x06;
9874 #[doc = "R0/7"]
9875 pub const DSE_7_R0_7: u32 = 0x07;
9876 }
9877 }
9878 #[doc = "Speed Field"]
9879 pub mod SPEED {
9880 pub const offset: u32 = 6;
9881 pub const mask: u32 = 0x03 << offset;
9882 pub mod R {}
9883 pub mod W {}
9884 pub mod RW {
9885 #[doc = "low(50MHz)"]
9886 pub const SPEED_0_LOW_50MHZ: u32 = 0;
9887 #[doc = "medium(100MHz)"]
9888 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
9889 #[doc = "medium(100MHz)"]
9890 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
9891 #[doc = "max(200MHz)"]
9892 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
9893 }
9894 }
9895 #[doc = "Open Drain Enable Field"]
9896 pub mod ODE {
9897 pub const offset: u32 = 11;
9898 pub const mask: u32 = 0x01 << offset;
9899 pub mod R {}
9900 pub mod W {}
9901 pub mod RW {
9902 #[doc = "Open Drain Disabled"]
9903 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
9904 #[doc = "Open Drain Enabled"]
9905 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
9906 }
9907 }
9908 #[doc = "Pull / Keep Enable Field"]
9909 pub mod PKE {
9910 pub const offset: u32 = 12;
9911 pub const mask: u32 = 0x01 << offset;
9912 pub mod R {}
9913 pub mod W {}
9914 pub mod RW {
9915 #[doc = "Pull/Keeper Disabled"]
9916 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
9917 #[doc = "Pull/Keeper Enabled"]
9918 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
9919 }
9920 }
9921 #[doc = "Pull / Keep Select Field"]
9922 pub mod PUE {
9923 pub const offset: u32 = 13;
9924 pub const mask: u32 = 0x01 << offset;
9925 pub mod R {}
9926 pub mod W {}
9927 pub mod RW {
9928 #[doc = "Keeper"]
9929 pub const PUE_0_KEEPER: u32 = 0;
9930 #[doc = "Pull"]
9931 pub const PUE_1_PULL: u32 = 0x01;
9932 }
9933 }
9934 #[doc = "Pull Up / Down Config. Field"]
9935 pub mod PUS {
9936 pub const offset: u32 = 14;
9937 pub const mask: u32 = 0x03 << offset;
9938 pub mod R {}
9939 pub mod W {}
9940 pub mod RW {
9941 #[doc = "100K Ohm Pull Down"]
9942 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
9943 #[doc = "47K Ohm Pull Up"]
9944 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
9945 #[doc = "100K Ohm Pull Up"]
9946 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
9947 #[doc = "22K Ohm Pull Up"]
9948 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
9949 }
9950 }
9951 #[doc = "Hyst. Enable Field"]
9952 pub mod HYS {
9953 pub const offset: u32 = 16;
9954 pub const mask: u32 = 0x01 << offset;
9955 pub mod R {}
9956 pub mod W {}
9957 pub mod RW {
9958 #[doc = "Hysteresis Disabled"]
9959 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
9960 #[doc = "Hysteresis Enabled"]
9961 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
9962 }
9963 }
9964}
9965#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_31 SW PAD Control Register"]
9966pub mod SW_PAD_CTL_PAD_GPIO_EMC_31 {
9967 #[doc = "Slew Rate Field"]
9968 pub mod SRE {
9969 pub const offset: u32 = 0;
9970 pub const mask: u32 = 0x01 << offset;
9971 pub mod R {}
9972 pub mod W {}
9973 pub mod RW {
9974 #[doc = "Slow Slew Rate"]
9975 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
9976 #[doc = "Fast Slew Rate"]
9977 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
9978 }
9979 }
9980 #[doc = "Drive Strength Field"]
9981 pub mod DSE {
9982 pub const offset: u32 = 3;
9983 pub const mask: u32 = 0x07 << offset;
9984 pub mod R {}
9985 pub mod W {}
9986 pub mod RW {
9987 #[doc = "output driver disabled;"]
9988 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
9989 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
9990 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
9991 #[doc = "R0/2"]
9992 pub const DSE_2_R0_2: u32 = 0x02;
9993 #[doc = "R0/3"]
9994 pub const DSE_3_R0_3: u32 = 0x03;
9995 #[doc = "R0/4"]
9996 pub const DSE_4_R0_4: u32 = 0x04;
9997 #[doc = "R0/5"]
9998 pub const DSE_5_R0_5: u32 = 0x05;
9999 #[doc = "R0/6"]
10000 pub const DSE_6_R0_6: u32 = 0x06;
10001 #[doc = "R0/7"]
10002 pub const DSE_7_R0_7: u32 = 0x07;
10003 }
10004 }
10005 #[doc = "Speed Field"]
10006 pub mod SPEED {
10007 pub const offset: u32 = 6;
10008 pub const mask: u32 = 0x03 << offset;
10009 pub mod R {}
10010 pub mod W {}
10011 pub mod RW {
10012 #[doc = "low(50MHz)"]
10013 pub const SPEED_0_LOW_50MHZ: u32 = 0;
10014 #[doc = "medium(100MHz)"]
10015 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
10016 #[doc = "medium(100MHz)"]
10017 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
10018 #[doc = "max(200MHz)"]
10019 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
10020 }
10021 }
10022 #[doc = "Open Drain Enable Field"]
10023 pub mod ODE {
10024 pub const offset: u32 = 11;
10025 pub const mask: u32 = 0x01 << offset;
10026 pub mod R {}
10027 pub mod W {}
10028 pub mod RW {
10029 #[doc = "Open Drain Disabled"]
10030 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
10031 #[doc = "Open Drain Enabled"]
10032 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
10033 }
10034 }
10035 #[doc = "Pull / Keep Enable Field"]
10036 pub mod PKE {
10037 pub const offset: u32 = 12;
10038 pub const mask: u32 = 0x01 << offset;
10039 pub mod R {}
10040 pub mod W {}
10041 pub mod RW {
10042 #[doc = "Pull/Keeper Disabled"]
10043 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
10044 #[doc = "Pull/Keeper Enabled"]
10045 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
10046 }
10047 }
10048 #[doc = "Pull / Keep Select Field"]
10049 pub mod PUE {
10050 pub const offset: u32 = 13;
10051 pub const mask: u32 = 0x01 << offset;
10052 pub mod R {}
10053 pub mod W {}
10054 pub mod RW {
10055 #[doc = "Keeper"]
10056 pub const PUE_0_KEEPER: u32 = 0;
10057 #[doc = "Pull"]
10058 pub const PUE_1_PULL: u32 = 0x01;
10059 }
10060 }
10061 #[doc = "Pull Up / Down Config. Field"]
10062 pub mod PUS {
10063 pub const offset: u32 = 14;
10064 pub const mask: u32 = 0x03 << offset;
10065 pub mod R {}
10066 pub mod W {}
10067 pub mod RW {
10068 #[doc = "100K Ohm Pull Down"]
10069 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
10070 #[doc = "47K Ohm Pull Up"]
10071 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
10072 #[doc = "100K Ohm Pull Up"]
10073 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
10074 #[doc = "22K Ohm Pull Up"]
10075 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
10076 }
10077 }
10078 #[doc = "Hyst. Enable Field"]
10079 pub mod HYS {
10080 pub const offset: u32 = 16;
10081 pub const mask: u32 = 0x01 << offset;
10082 pub mod R {}
10083 pub mod W {}
10084 pub mod RW {
10085 #[doc = "Hysteresis Disabled"]
10086 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
10087 #[doc = "Hysteresis Enabled"]
10088 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
10089 }
10090 }
10091}
10092#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_32 SW PAD Control Register"]
10093pub mod SW_PAD_CTL_PAD_GPIO_EMC_32 {
10094 #[doc = "Slew Rate Field"]
10095 pub mod SRE {
10096 pub const offset: u32 = 0;
10097 pub const mask: u32 = 0x01 << offset;
10098 pub mod R {}
10099 pub mod W {}
10100 pub mod RW {
10101 #[doc = "Slow Slew Rate"]
10102 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
10103 #[doc = "Fast Slew Rate"]
10104 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
10105 }
10106 }
10107 #[doc = "Drive Strength Field"]
10108 pub mod DSE {
10109 pub const offset: u32 = 3;
10110 pub const mask: u32 = 0x07 << offset;
10111 pub mod R {}
10112 pub mod W {}
10113 pub mod RW {
10114 #[doc = "output driver disabled;"]
10115 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
10116 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
10117 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
10118 #[doc = "R0/2"]
10119 pub const DSE_2_R0_2: u32 = 0x02;
10120 #[doc = "R0/3"]
10121 pub const DSE_3_R0_3: u32 = 0x03;
10122 #[doc = "R0/4"]
10123 pub const DSE_4_R0_4: u32 = 0x04;
10124 #[doc = "R0/5"]
10125 pub const DSE_5_R0_5: u32 = 0x05;
10126 #[doc = "R0/6"]
10127 pub const DSE_6_R0_6: u32 = 0x06;
10128 #[doc = "R0/7"]
10129 pub const DSE_7_R0_7: u32 = 0x07;
10130 }
10131 }
10132 #[doc = "Speed Field"]
10133 pub mod SPEED {
10134 pub const offset: u32 = 6;
10135 pub const mask: u32 = 0x03 << offset;
10136 pub mod R {}
10137 pub mod W {}
10138 pub mod RW {
10139 #[doc = "low(50MHz)"]
10140 pub const SPEED_0_LOW_50MHZ: u32 = 0;
10141 #[doc = "medium(100MHz)"]
10142 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
10143 #[doc = "medium(100MHz)"]
10144 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
10145 #[doc = "max(200MHz)"]
10146 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
10147 }
10148 }
10149 #[doc = "Open Drain Enable Field"]
10150 pub mod ODE {
10151 pub const offset: u32 = 11;
10152 pub const mask: u32 = 0x01 << offset;
10153 pub mod R {}
10154 pub mod W {}
10155 pub mod RW {
10156 #[doc = "Open Drain Disabled"]
10157 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
10158 #[doc = "Open Drain Enabled"]
10159 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
10160 }
10161 }
10162 #[doc = "Pull / Keep Enable Field"]
10163 pub mod PKE {
10164 pub const offset: u32 = 12;
10165 pub const mask: u32 = 0x01 << offset;
10166 pub mod R {}
10167 pub mod W {}
10168 pub mod RW {
10169 #[doc = "Pull/Keeper Disabled"]
10170 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
10171 #[doc = "Pull/Keeper Enabled"]
10172 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
10173 }
10174 }
10175 #[doc = "Pull / Keep Select Field"]
10176 pub mod PUE {
10177 pub const offset: u32 = 13;
10178 pub const mask: u32 = 0x01 << offset;
10179 pub mod R {}
10180 pub mod W {}
10181 pub mod RW {
10182 #[doc = "Keeper"]
10183 pub const PUE_0_KEEPER: u32 = 0;
10184 #[doc = "Pull"]
10185 pub const PUE_1_PULL: u32 = 0x01;
10186 }
10187 }
10188 #[doc = "Pull Up / Down Config. Field"]
10189 pub mod PUS {
10190 pub const offset: u32 = 14;
10191 pub const mask: u32 = 0x03 << offset;
10192 pub mod R {}
10193 pub mod W {}
10194 pub mod RW {
10195 #[doc = "100K Ohm Pull Down"]
10196 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
10197 #[doc = "47K Ohm Pull Up"]
10198 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
10199 #[doc = "100K Ohm Pull Up"]
10200 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
10201 #[doc = "22K Ohm Pull Up"]
10202 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
10203 }
10204 }
10205 #[doc = "Hyst. Enable Field"]
10206 pub mod HYS {
10207 pub const offset: u32 = 16;
10208 pub const mask: u32 = 0x01 << offset;
10209 pub mod R {}
10210 pub mod W {}
10211 pub mod RW {
10212 #[doc = "Hysteresis Disabled"]
10213 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
10214 #[doc = "Hysteresis Enabled"]
10215 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
10216 }
10217 }
10218}
10219#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_33 SW PAD Control Register"]
10220pub mod SW_PAD_CTL_PAD_GPIO_EMC_33 {
10221 #[doc = "Slew Rate Field"]
10222 pub mod SRE {
10223 pub const offset: u32 = 0;
10224 pub const mask: u32 = 0x01 << offset;
10225 pub mod R {}
10226 pub mod W {}
10227 pub mod RW {
10228 #[doc = "Slow Slew Rate"]
10229 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
10230 #[doc = "Fast Slew Rate"]
10231 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
10232 }
10233 }
10234 #[doc = "Drive Strength Field"]
10235 pub mod DSE {
10236 pub const offset: u32 = 3;
10237 pub const mask: u32 = 0x07 << offset;
10238 pub mod R {}
10239 pub mod W {}
10240 pub mod RW {
10241 #[doc = "output driver disabled;"]
10242 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
10243 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
10244 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
10245 #[doc = "R0/2"]
10246 pub const DSE_2_R0_2: u32 = 0x02;
10247 #[doc = "R0/3"]
10248 pub const DSE_3_R0_3: u32 = 0x03;
10249 #[doc = "R0/4"]
10250 pub const DSE_4_R0_4: u32 = 0x04;
10251 #[doc = "R0/5"]
10252 pub const DSE_5_R0_5: u32 = 0x05;
10253 #[doc = "R0/6"]
10254 pub const DSE_6_R0_6: u32 = 0x06;
10255 #[doc = "R0/7"]
10256 pub const DSE_7_R0_7: u32 = 0x07;
10257 }
10258 }
10259 #[doc = "Speed Field"]
10260 pub mod SPEED {
10261 pub const offset: u32 = 6;
10262 pub const mask: u32 = 0x03 << offset;
10263 pub mod R {}
10264 pub mod W {}
10265 pub mod RW {
10266 #[doc = "low(50MHz)"]
10267 pub const SPEED_0_LOW_50MHZ: u32 = 0;
10268 #[doc = "medium(100MHz)"]
10269 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
10270 #[doc = "medium(100MHz)"]
10271 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
10272 #[doc = "max(200MHz)"]
10273 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
10274 }
10275 }
10276 #[doc = "Open Drain Enable Field"]
10277 pub mod ODE {
10278 pub const offset: u32 = 11;
10279 pub const mask: u32 = 0x01 << offset;
10280 pub mod R {}
10281 pub mod W {}
10282 pub mod RW {
10283 #[doc = "Open Drain Disabled"]
10284 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
10285 #[doc = "Open Drain Enabled"]
10286 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
10287 }
10288 }
10289 #[doc = "Pull / Keep Enable Field"]
10290 pub mod PKE {
10291 pub const offset: u32 = 12;
10292 pub const mask: u32 = 0x01 << offset;
10293 pub mod R {}
10294 pub mod W {}
10295 pub mod RW {
10296 #[doc = "Pull/Keeper Disabled"]
10297 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
10298 #[doc = "Pull/Keeper Enabled"]
10299 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
10300 }
10301 }
10302 #[doc = "Pull / Keep Select Field"]
10303 pub mod PUE {
10304 pub const offset: u32 = 13;
10305 pub const mask: u32 = 0x01 << offset;
10306 pub mod R {}
10307 pub mod W {}
10308 pub mod RW {
10309 #[doc = "Keeper"]
10310 pub const PUE_0_KEEPER: u32 = 0;
10311 #[doc = "Pull"]
10312 pub const PUE_1_PULL: u32 = 0x01;
10313 }
10314 }
10315 #[doc = "Pull Up / Down Config. Field"]
10316 pub mod PUS {
10317 pub const offset: u32 = 14;
10318 pub const mask: u32 = 0x03 << offset;
10319 pub mod R {}
10320 pub mod W {}
10321 pub mod RW {
10322 #[doc = "100K Ohm Pull Down"]
10323 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
10324 #[doc = "47K Ohm Pull Up"]
10325 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
10326 #[doc = "100K Ohm Pull Up"]
10327 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
10328 #[doc = "22K Ohm Pull Up"]
10329 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
10330 }
10331 }
10332 #[doc = "Hyst. Enable Field"]
10333 pub mod HYS {
10334 pub const offset: u32 = 16;
10335 pub const mask: u32 = 0x01 << offset;
10336 pub mod R {}
10337 pub mod W {}
10338 pub mod RW {
10339 #[doc = "Hysteresis Disabled"]
10340 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
10341 #[doc = "Hysteresis Enabled"]
10342 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
10343 }
10344 }
10345}
10346#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_34 SW PAD Control Register"]
10347pub mod SW_PAD_CTL_PAD_GPIO_EMC_34 {
10348 #[doc = "Slew Rate Field"]
10349 pub mod SRE {
10350 pub const offset: u32 = 0;
10351 pub const mask: u32 = 0x01 << offset;
10352 pub mod R {}
10353 pub mod W {}
10354 pub mod RW {
10355 #[doc = "Slow Slew Rate"]
10356 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
10357 #[doc = "Fast Slew Rate"]
10358 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
10359 }
10360 }
10361 #[doc = "Drive Strength Field"]
10362 pub mod DSE {
10363 pub const offset: u32 = 3;
10364 pub const mask: u32 = 0x07 << offset;
10365 pub mod R {}
10366 pub mod W {}
10367 pub mod RW {
10368 #[doc = "output driver disabled;"]
10369 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
10370 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
10371 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
10372 #[doc = "R0/2"]
10373 pub const DSE_2_R0_2: u32 = 0x02;
10374 #[doc = "R0/3"]
10375 pub const DSE_3_R0_3: u32 = 0x03;
10376 #[doc = "R0/4"]
10377 pub const DSE_4_R0_4: u32 = 0x04;
10378 #[doc = "R0/5"]
10379 pub const DSE_5_R0_5: u32 = 0x05;
10380 #[doc = "R0/6"]
10381 pub const DSE_6_R0_6: u32 = 0x06;
10382 #[doc = "R0/7"]
10383 pub const DSE_7_R0_7: u32 = 0x07;
10384 }
10385 }
10386 #[doc = "Speed Field"]
10387 pub mod SPEED {
10388 pub const offset: u32 = 6;
10389 pub const mask: u32 = 0x03 << offset;
10390 pub mod R {}
10391 pub mod W {}
10392 pub mod RW {
10393 #[doc = "low(50MHz)"]
10394 pub const SPEED_0_LOW_50MHZ: u32 = 0;
10395 #[doc = "medium(100MHz)"]
10396 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
10397 #[doc = "medium(100MHz)"]
10398 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
10399 #[doc = "max(200MHz)"]
10400 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
10401 }
10402 }
10403 #[doc = "Open Drain Enable Field"]
10404 pub mod ODE {
10405 pub const offset: u32 = 11;
10406 pub const mask: u32 = 0x01 << offset;
10407 pub mod R {}
10408 pub mod W {}
10409 pub mod RW {
10410 #[doc = "Open Drain Disabled"]
10411 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
10412 #[doc = "Open Drain Enabled"]
10413 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
10414 }
10415 }
10416 #[doc = "Pull / Keep Enable Field"]
10417 pub mod PKE {
10418 pub const offset: u32 = 12;
10419 pub const mask: u32 = 0x01 << offset;
10420 pub mod R {}
10421 pub mod W {}
10422 pub mod RW {
10423 #[doc = "Pull/Keeper Disabled"]
10424 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
10425 #[doc = "Pull/Keeper Enabled"]
10426 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
10427 }
10428 }
10429 #[doc = "Pull / Keep Select Field"]
10430 pub mod PUE {
10431 pub const offset: u32 = 13;
10432 pub const mask: u32 = 0x01 << offset;
10433 pub mod R {}
10434 pub mod W {}
10435 pub mod RW {
10436 #[doc = "Keeper"]
10437 pub const PUE_0_KEEPER: u32 = 0;
10438 #[doc = "Pull"]
10439 pub const PUE_1_PULL: u32 = 0x01;
10440 }
10441 }
10442 #[doc = "Pull Up / Down Config. Field"]
10443 pub mod PUS {
10444 pub const offset: u32 = 14;
10445 pub const mask: u32 = 0x03 << offset;
10446 pub mod R {}
10447 pub mod W {}
10448 pub mod RW {
10449 #[doc = "100K Ohm Pull Down"]
10450 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
10451 #[doc = "47K Ohm Pull Up"]
10452 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
10453 #[doc = "100K Ohm Pull Up"]
10454 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
10455 #[doc = "22K Ohm Pull Up"]
10456 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
10457 }
10458 }
10459 #[doc = "Hyst. Enable Field"]
10460 pub mod HYS {
10461 pub const offset: u32 = 16;
10462 pub const mask: u32 = 0x01 << offset;
10463 pub mod R {}
10464 pub mod W {}
10465 pub mod RW {
10466 #[doc = "Hysteresis Disabled"]
10467 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
10468 #[doc = "Hysteresis Enabled"]
10469 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
10470 }
10471 }
10472}
10473#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_35 SW PAD Control Register"]
10474pub mod SW_PAD_CTL_PAD_GPIO_EMC_35 {
10475 #[doc = "Slew Rate Field"]
10476 pub mod SRE {
10477 pub const offset: u32 = 0;
10478 pub const mask: u32 = 0x01 << offset;
10479 pub mod R {}
10480 pub mod W {}
10481 pub mod RW {
10482 #[doc = "Slow Slew Rate"]
10483 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
10484 #[doc = "Fast Slew Rate"]
10485 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
10486 }
10487 }
10488 #[doc = "Drive Strength Field"]
10489 pub mod DSE {
10490 pub const offset: u32 = 3;
10491 pub const mask: u32 = 0x07 << offset;
10492 pub mod R {}
10493 pub mod W {}
10494 pub mod RW {
10495 #[doc = "output driver disabled;"]
10496 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
10497 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
10498 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
10499 #[doc = "R0/2"]
10500 pub const DSE_2_R0_2: u32 = 0x02;
10501 #[doc = "R0/3"]
10502 pub const DSE_3_R0_3: u32 = 0x03;
10503 #[doc = "R0/4"]
10504 pub const DSE_4_R0_4: u32 = 0x04;
10505 #[doc = "R0/5"]
10506 pub const DSE_5_R0_5: u32 = 0x05;
10507 #[doc = "R0/6"]
10508 pub const DSE_6_R0_6: u32 = 0x06;
10509 #[doc = "R0/7"]
10510 pub const DSE_7_R0_7: u32 = 0x07;
10511 }
10512 }
10513 #[doc = "Speed Field"]
10514 pub mod SPEED {
10515 pub const offset: u32 = 6;
10516 pub const mask: u32 = 0x03 << offset;
10517 pub mod R {}
10518 pub mod W {}
10519 pub mod RW {
10520 #[doc = "low(50MHz)"]
10521 pub const SPEED_0_LOW_50MHZ: u32 = 0;
10522 #[doc = "medium(100MHz)"]
10523 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
10524 #[doc = "medium(100MHz)"]
10525 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
10526 #[doc = "max(200MHz)"]
10527 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
10528 }
10529 }
10530 #[doc = "Open Drain Enable Field"]
10531 pub mod ODE {
10532 pub const offset: u32 = 11;
10533 pub const mask: u32 = 0x01 << offset;
10534 pub mod R {}
10535 pub mod W {}
10536 pub mod RW {
10537 #[doc = "Open Drain Disabled"]
10538 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
10539 #[doc = "Open Drain Enabled"]
10540 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
10541 }
10542 }
10543 #[doc = "Pull / Keep Enable Field"]
10544 pub mod PKE {
10545 pub const offset: u32 = 12;
10546 pub const mask: u32 = 0x01 << offset;
10547 pub mod R {}
10548 pub mod W {}
10549 pub mod RW {
10550 #[doc = "Pull/Keeper Disabled"]
10551 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
10552 #[doc = "Pull/Keeper Enabled"]
10553 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
10554 }
10555 }
10556 #[doc = "Pull / Keep Select Field"]
10557 pub mod PUE {
10558 pub const offset: u32 = 13;
10559 pub const mask: u32 = 0x01 << offset;
10560 pub mod R {}
10561 pub mod W {}
10562 pub mod RW {
10563 #[doc = "Keeper"]
10564 pub const PUE_0_KEEPER: u32 = 0;
10565 #[doc = "Pull"]
10566 pub const PUE_1_PULL: u32 = 0x01;
10567 }
10568 }
10569 #[doc = "Pull Up / Down Config. Field"]
10570 pub mod PUS {
10571 pub const offset: u32 = 14;
10572 pub const mask: u32 = 0x03 << offset;
10573 pub mod R {}
10574 pub mod W {}
10575 pub mod RW {
10576 #[doc = "100K Ohm Pull Down"]
10577 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
10578 #[doc = "47K Ohm Pull Up"]
10579 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
10580 #[doc = "100K Ohm Pull Up"]
10581 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
10582 #[doc = "22K Ohm Pull Up"]
10583 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
10584 }
10585 }
10586 #[doc = "Hyst. Enable Field"]
10587 pub mod HYS {
10588 pub const offset: u32 = 16;
10589 pub const mask: u32 = 0x01 << offset;
10590 pub mod R {}
10591 pub mod W {}
10592 pub mod RW {
10593 #[doc = "Hysteresis Disabled"]
10594 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
10595 #[doc = "Hysteresis Enabled"]
10596 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
10597 }
10598 }
10599}
10600#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_36 SW PAD Control Register"]
10601pub mod SW_PAD_CTL_PAD_GPIO_EMC_36 {
10602 #[doc = "Slew Rate Field"]
10603 pub mod SRE {
10604 pub const offset: u32 = 0;
10605 pub const mask: u32 = 0x01 << offset;
10606 pub mod R {}
10607 pub mod W {}
10608 pub mod RW {
10609 #[doc = "Slow Slew Rate"]
10610 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
10611 #[doc = "Fast Slew Rate"]
10612 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
10613 }
10614 }
10615 #[doc = "Drive Strength Field"]
10616 pub mod DSE {
10617 pub const offset: u32 = 3;
10618 pub const mask: u32 = 0x07 << offset;
10619 pub mod R {}
10620 pub mod W {}
10621 pub mod RW {
10622 #[doc = "output driver disabled;"]
10623 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
10624 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
10625 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
10626 #[doc = "R0/2"]
10627 pub const DSE_2_R0_2: u32 = 0x02;
10628 #[doc = "R0/3"]
10629 pub const DSE_3_R0_3: u32 = 0x03;
10630 #[doc = "R0/4"]
10631 pub const DSE_4_R0_4: u32 = 0x04;
10632 #[doc = "R0/5"]
10633 pub const DSE_5_R0_5: u32 = 0x05;
10634 #[doc = "R0/6"]
10635 pub const DSE_6_R0_6: u32 = 0x06;
10636 #[doc = "R0/7"]
10637 pub const DSE_7_R0_7: u32 = 0x07;
10638 }
10639 }
10640 #[doc = "Speed Field"]
10641 pub mod SPEED {
10642 pub const offset: u32 = 6;
10643 pub const mask: u32 = 0x03 << offset;
10644 pub mod R {}
10645 pub mod W {}
10646 pub mod RW {
10647 #[doc = "low(50MHz)"]
10648 pub const SPEED_0_LOW_50MHZ: u32 = 0;
10649 #[doc = "medium(100MHz)"]
10650 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
10651 #[doc = "medium(100MHz)"]
10652 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
10653 #[doc = "max(200MHz)"]
10654 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
10655 }
10656 }
10657 #[doc = "Open Drain Enable Field"]
10658 pub mod ODE {
10659 pub const offset: u32 = 11;
10660 pub const mask: u32 = 0x01 << offset;
10661 pub mod R {}
10662 pub mod W {}
10663 pub mod RW {
10664 #[doc = "Open Drain Disabled"]
10665 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
10666 #[doc = "Open Drain Enabled"]
10667 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
10668 }
10669 }
10670 #[doc = "Pull / Keep Enable Field"]
10671 pub mod PKE {
10672 pub const offset: u32 = 12;
10673 pub const mask: u32 = 0x01 << offset;
10674 pub mod R {}
10675 pub mod W {}
10676 pub mod RW {
10677 #[doc = "Pull/Keeper Disabled"]
10678 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
10679 #[doc = "Pull/Keeper Enabled"]
10680 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
10681 }
10682 }
10683 #[doc = "Pull / Keep Select Field"]
10684 pub mod PUE {
10685 pub const offset: u32 = 13;
10686 pub const mask: u32 = 0x01 << offset;
10687 pub mod R {}
10688 pub mod W {}
10689 pub mod RW {
10690 #[doc = "Keeper"]
10691 pub const PUE_0_KEEPER: u32 = 0;
10692 #[doc = "Pull"]
10693 pub const PUE_1_PULL: u32 = 0x01;
10694 }
10695 }
10696 #[doc = "Pull Up / Down Config. Field"]
10697 pub mod PUS {
10698 pub const offset: u32 = 14;
10699 pub const mask: u32 = 0x03 << offset;
10700 pub mod R {}
10701 pub mod W {}
10702 pub mod RW {
10703 #[doc = "100K Ohm Pull Down"]
10704 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
10705 #[doc = "47K Ohm Pull Up"]
10706 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
10707 #[doc = "100K Ohm Pull Up"]
10708 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
10709 #[doc = "22K Ohm Pull Up"]
10710 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
10711 }
10712 }
10713 #[doc = "Hyst. Enable Field"]
10714 pub mod HYS {
10715 pub const offset: u32 = 16;
10716 pub const mask: u32 = 0x01 << offset;
10717 pub mod R {}
10718 pub mod W {}
10719 pub mod RW {
10720 #[doc = "Hysteresis Disabled"]
10721 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
10722 #[doc = "Hysteresis Enabled"]
10723 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
10724 }
10725 }
10726}
10727#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_37 SW PAD Control Register"]
10728pub mod SW_PAD_CTL_PAD_GPIO_EMC_37 {
10729 #[doc = "Slew Rate Field"]
10730 pub mod SRE {
10731 pub const offset: u32 = 0;
10732 pub const mask: u32 = 0x01 << offset;
10733 pub mod R {}
10734 pub mod W {}
10735 pub mod RW {
10736 #[doc = "Slow Slew Rate"]
10737 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
10738 #[doc = "Fast Slew Rate"]
10739 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
10740 }
10741 }
10742 #[doc = "Drive Strength Field"]
10743 pub mod DSE {
10744 pub const offset: u32 = 3;
10745 pub const mask: u32 = 0x07 << offset;
10746 pub mod R {}
10747 pub mod W {}
10748 pub mod RW {
10749 #[doc = "output driver disabled;"]
10750 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
10751 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
10752 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
10753 #[doc = "R0/2"]
10754 pub const DSE_2_R0_2: u32 = 0x02;
10755 #[doc = "R0/3"]
10756 pub const DSE_3_R0_3: u32 = 0x03;
10757 #[doc = "R0/4"]
10758 pub const DSE_4_R0_4: u32 = 0x04;
10759 #[doc = "R0/5"]
10760 pub const DSE_5_R0_5: u32 = 0x05;
10761 #[doc = "R0/6"]
10762 pub const DSE_6_R0_6: u32 = 0x06;
10763 #[doc = "R0/7"]
10764 pub const DSE_7_R0_7: u32 = 0x07;
10765 }
10766 }
10767 #[doc = "Speed Field"]
10768 pub mod SPEED {
10769 pub const offset: u32 = 6;
10770 pub const mask: u32 = 0x03 << offset;
10771 pub mod R {}
10772 pub mod W {}
10773 pub mod RW {
10774 #[doc = "low(50MHz)"]
10775 pub const SPEED_0_LOW_50MHZ: u32 = 0;
10776 #[doc = "medium(100MHz)"]
10777 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
10778 #[doc = "medium(100MHz)"]
10779 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
10780 #[doc = "max(200MHz)"]
10781 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
10782 }
10783 }
10784 #[doc = "Open Drain Enable Field"]
10785 pub mod ODE {
10786 pub const offset: u32 = 11;
10787 pub const mask: u32 = 0x01 << offset;
10788 pub mod R {}
10789 pub mod W {}
10790 pub mod RW {
10791 #[doc = "Open Drain Disabled"]
10792 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
10793 #[doc = "Open Drain Enabled"]
10794 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
10795 }
10796 }
10797 #[doc = "Pull / Keep Enable Field"]
10798 pub mod PKE {
10799 pub const offset: u32 = 12;
10800 pub const mask: u32 = 0x01 << offset;
10801 pub mod R {}
10802 pub mod W {}
10803 pub mod RW {
10804 #[doc = "Pull/Keeper Disabled"]
10805 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
10806 #[doc = "Pull/Keeper Enabled"]
10807 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
10808 }
10809 }
10810 #[doc = "Pull / Keep Select Field"]
10811 pub mod PUE {
10812 pub const offset: u32 = 13;
10813 pub const mask: u32 = 0x01 << offset;
10814 pub mod R {}
10815 pub mod W {}
10816 pub mod RW {
10817 #[doc = "Keeper"]
10818 pub const PUE_0_KEEPER: u32 = 0;
10819 #[doc = "Pull"]
10820 pub const PUE_1_PULL: u32 = 0x01;
10821 }
10822 }
10823 #[doc = "Pull Up / Down Config. Field"]
10824 pub mod PUS {
10825 pub const offset: u32 = 14;
10826 pub const mask: u32 = 0x03 << offset;
10827 pub mod R {}
10828 pub mod W {}
10829 pub mod RW {
10830 #[doc = "100K Ohm Pull Down"]
10831 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
10832 #[doc = "47K Ohm Pull Up"]
10833 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
10834 #[doc = "100K Ohm Pull Up"]
10835 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
10836 #[doc = "22K Ohm Pull Up"]
10837 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
10838 }
10839 }
10840 #[doc = "Hyst. Enable Field"]
10841 pub mod HYS {
10842 pub const offset: u32 = 16;
10843 pub const mask: u32 = 0x01 << offset;
10844 pub mod R {}
10845 pub mod W {}
10846 pub mod RW {
10847 #[doc = "Hysteresis Disabled"]
10848 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
10849 #[doc = "Hysteresis Enabled"]
10850 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
10851 }
10852 }
10853}
10854#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_38 SW PAD Control Register"]
10855pub mod SW_PAD_CTL_PAD_GPIO_EMC_38 {
10856 #[doc = "Slew Rate Field"]
10857 pub mod SRE {
10858 pub const offset: u32 = 0;
10859 pub const mask: u32 = 0x01 << offset;
10860 pub mod R {}
10861 pub mod W {}
10862 pub mod RW {
10863 #[doc = "Slow Slew Rate"]
10864 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
10865 #[doc = "Fast Slew Rate"]
10866 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
10867 }
10868 }
10869 #[doc = "Drive Strength Field"]
10870 pub mod DSE {
10871 pub const offset: u32 = 3;
10872 pub const mask: u32 = 0x07 << offset;
10873 pub mod R {}
10874 pub mod W {}
10875 pub mod RW {
10876 #[doc = "output driver disabled;"]
10877 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
10878 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
10879 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
10880 #[doc = "R0/2"]
10881 pub const DSE_2_R0_2: u32 = 0x02;
10882 #[doc = "R0/3"]
10883 pub const DSE_3_R0_3: u32 = 0x03;
10884 #[doc = "R0/4"]
10885 pub const DSE_4_R0_4: u32 = 0x04;
10886 #[doc = "R0/5"]
10887 pub const DSE_5_R0_5: u32 = 0x05;
10888 #[doc = "R0/6"]
10889 pub const DSE_6_R0_6: u32 = 0x06;
10890 #[doc = "R0/7"]
10891 pub const DSE_7_R0_7: u32 = 0x07;
10892 }
10893 }
10894 #[doc = "Speed Field"]
10895 pub mod SPEED {
10896 pub const offset: u32 = 6;
10897 pub const mask: u32 = 0x03 << offset;
10898 pub mod R {}
10899 pub mod W {}
10900 pub mod RW {
10901 #[doc = "low(50MHz)"]
10902 pub const SPEED_0_LOW_50MHZ: u32 = 0;
10903 #[doc = "medium(100MHz)"]
10904 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
10905 #[doc = "medium(100MHz)"]
10906 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
10907 #[doc = "max(200MHz)"]
10908 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
10909 }
10910 }
10911 #[doc = "Open Drain Enable Field"]
10912 pub mod ODE {
10913 pub const offset: u32 = 11;
10914 pub const mask: u32 = 0x01 << offset;
10915 pub mod R {}
10916 pub mod W {}
10917 pub mod RW {
10918 #[doc = "Open Drain Disabled"]
10919 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
10920 #[doc = "Open Drain Enabled"]
10921 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
10922 }
10923 }
10924 #[doc = "Pull / Keep Enable Field"]
10925 pub mod PKE {
10926 pub const offset: u32 = 12;
10927 pub const mask: u32 = 0x01 << offset;
10928 pub mod R {}
10929 pub mod W {}
10930 pub mod RW {
10931 #[doc = "Pull/Keeper Disabled"]
10932 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
10933 #[doc = "Pull/Keeper Enabled"]
10934 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
10935 }
10936 }
10937 #[doc = "Pull / Keep Select Field"]
10938 pub mod PUE {
10939 pub const offset: u32 = 13;
10940 pub const mask: u32 = 0x01 << offset;
10941 pub mod R {}
10942 pub mod W {}
10943 pub mod RW {
10944 #[doc = "Keeper"]
10945 pub const PUE_0_KEEPER: u32 = 0;
10946 #[doc = "Pull"]
10947 pub const PUE_1_PULL: u32 = 0x01;
10948 }
10949 }
10950 #[doc = "Pull Up / Down Config. Field"]
10951 pub mod PUS {
10952 pub const offset: u32 = 14;
10953 pub const mask: u32 = 0x03 << offset;
10954 pub mod R {}
10955 pub mod W {}
10956 pub mod RW {
10957 #[doc = "100K Ohm Pull Down"]
10958 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
10959 #[doc = "47K Ohm Pull Up"]
10960 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
10961 #[doc = "100K Ohm Pull Up"]
10962 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
10963 #[doc = "22K Ohm Pull Up"]
10964 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
10965 }
10966 }
10967 #[doc = "Hyst. Enable Field"]
10968 pub mod HYS {
10969 pub const offset: u32 = 16;
10970 pub const mask: u32 = 0x01 << offset;
10971 pub mod R {}
10972 pub mod W {}
10973 pub mod RW {
10974 #[doc = "Hysteresis Disabled"]
10975 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
10976 #[doc = "Hysteresis Enabled"]
10977 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
10978 }
10979 }
10980}
10981#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_39 SW PAD Control Register"]
10982pub mod SW_PAD_CTL_PAD_GPIO_EMC_39 {
10983 #[doc = "Slew Rate Field"]
10984 pub mod SRE {
10985 pub const offset: u32 = 0;
10986 pub const mask: u32 = 0x01 << offset;
10987 pub mod R {}
10988 pub mod W {}
10989 pub mod RW {
10990 #[doc = "Slow Slew Rate"]
10991 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
10992 #[doc = "Fast Slew Rate"]
10993 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
10994 }
10995 }
10996 #[doc = "Drive Strength Field"]
10997 pub mod DSE {
10998 pub const offset: u32 = 3;
10999 pub const mask: u32 = 0x07 << offset;
11000 pub mod R {}
11001 pub mod W {}
11002 pub mod RW {
11003 #[doc = "output driver disabled;"]
11004 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
11005 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
11006 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
11007 #[doc = "R0/2"]
11008 pub const DSE_2_R0_2: u32 = 0x02;
11009 #[doc = "R0/3"]
11010 pub const DSE_3_R0_3: u32 = 0x03;
11011 #[doc = "R0/4"]
11012 pub const DSE_4_R0_4: u32 = 0x04;
11013 #[doc = "R0/5"]
11014 pub const DSE_5_R0_5: u32 = 0x05;
11015 #[doc = "R0/6"]
11016 pub const DSE_6_R0_6: u32 = 0x06;
11017 #[doc = "R0/7"]
11018 pub const DSE_7_R0_7: u32 = 0x07;
11019 }
11020 }
11021 #[doc = "Speed Field"]
11022 pub mod SPEED {
11023 pub const offset: u32 = 6;
11024 pub const mask: u32 = 0x03 << offset;
11025 pub mod R {}
11026 pub mod W {}
11027 pub mod RW {
11028 #[doc = "low(50MHz)"]
11029 pub const SPEED_0_LOW_50MHZ: u32 = 0;
11030 #[doc = "medium(100MHz)"]
11031 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
11032 #[doc = "medium(100MHz)"]
11033 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
11034 #[doc = "max(200MHz)"]
11035 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
11036 }
11037 }
11038 #[doc = "Open Drain Enable Field"]
11039 pub mod ODE {
11040 pub const offset: u32 = 11;
11041 pub const mask: u32 = 0x01 << offset;
11042 pub mod R {}
11043 pub mod W {}
11044 pub mod RW {
11045 #[doc = "Open Drain Disabled"]
11046 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
11047 #[doc = "Open Drain Enabled"]
11048 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
11049 }
11050 }
11051 #[doc = "Pull / Keep Enable Field"]
11052 pub mod PKE {
11053 pub const offset: u32 = 12;
11054 pub const mask: u32 = 0x01 << offset;
11055 pub mod R {}
11056 pub mod W {}
11057 pub mod RW {
11058 #[doc = "Pull/Keeper Disabled"]
11059 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
11060 #[doc = "Pull/Keeper Enabled"]
11061 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
11062 }
11063 }
11064 #[doc = "Pull / Keep Select Field"]
11065 pub mod PUE {
11066 pub const offset: u32 = 13;
11067 pub const mask: u32 = 0x01 << offset;
11068 pub mod R {}
11069 pub mod W {}
11070 pub mod RW {
11071 #[doc = "Keeper"]
11072 pub const PUE_0_KEEPER: u32 = 0;
11073 #[doc = "Pull"]
11074 pub const PUE_1_PULL: u32 = 0x01;
11075 }
11076 }
11077 #[doc = "Pull Up / Down Config. Field"]
11078 pub mod PUS {
11079 pub const offset: u32 = 14;
11080 pub const mask: u32 = 0x03 << offset;
11081 pub mod R {}
11082 pub mod W {}
11083 pub mod RW {
11084 #[doc = "100K Ohm Pull Down"]
11085 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
11086 #[doc = "47K Ohm Pull Up"]
11087 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
11088 #[doc = "100K Ohm Pull Up"]
11089 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
11090 #[doc = "22K Ohm Pull Up"]
11091 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
11092 }
11093 }
11094 #[doc = "Hyst. Enable Field"]
11095 pub mod HYS {
11096 pub const offset: u32 = 16;
11097 pub const mask: u32 = 0x01 << offset;
11098 pub mod R {}
11099 pub mod W {}
11100 pub mod RW {
11101 #[doc = "Hysteresis Disabled"]
11102 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
11103 #[doc = "Hysteresis Enabled"]
11104 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
11105 }
11106 }
11107}
11108#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_40 SW PAD Control Register"]
11109pub mod SW_PAD_CTL_PAD_GPIO_EMC_40 {
11110 #[doc = "Slew Rate Field"]
11111 pub mod SRE {
11112 pub const offset: u32 = 0;
11113 pub const mask: u32 = 0x01 << offset;
11114 pub mod R {}
11115 pub mod W {}
11116 pub mod RW {
11117 #[doc = "Slow Slew Rate"]
11118 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
11119 #[doc = "Fast Slew Rate"]
11120 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
11121 }
11122 }
11123 #[doc = "Drive Strength Field"]
11124 pub mod DSE {
11125 pub const offset: u32 = 3;
11126 pub const mask: u32 = 0x07 << offset;
11127 pub mod R {}
11128 pub mod W {}
11129 pub mod RW {
11130 #[doc = "output driver disabled;"]
11131 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
11132 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
11133 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
11134 #[doc = "R0/2"]
11135 pub const DSE_2_R0_2: u32 = 0x02;
11136 #[doc = "R0/3"]
11137 pub const DSE_3_R0_3: u32 = 0x03;
11138 #[doc = "R0/4"]
11139 pub const DSE_4_R0_4: u32 = 0x04;
11140 #[doc = "R0/5"]
11141 pub const DSE_5_R0_5: u32 = 0x05;
11142 #[doc = "R0/6"]
11143 pub const DSE_6_R0_6: u32 = 0x06;
11144 #[doc = "R0/7"]
11145 pub const DSE_7_R0_7: u32 = 0x07;
11146 }
11147 }
11148 #[doc = "Speed Field"]
11149 pub mod SPEED {
11150 pub const offset: u32 = 6;
11151 pub const mask: u32 = 0x03 << offset;
11152 pub mod R {}
11153 pub mod W {}
11154 pub mod RW {
11155 #[doc = "low(50MHz)"]
11156 pub const SPEED_0_LOW_50MHZ: u32 = 0;
11157 #[doc = "medium(100MHz)"]
11158 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
11159 #[doc = "medium(100MHz)"]
11160 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
11161 #[doc = "max(200MHz)"]
11162 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
11163 }
11164 }
11165 #[doc = "Open Drain Enable Field"]
11166 pub mod ODE {
11167 pub const offset: u32 = 11;
11168 pub const mask: u32 = 0x01 << offset;
11169 pub mod R {}
11170 pub mod W {}
11171 pub mod RW {
11172 #[doc = "Open Drain Disabled"]
11173 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
11174 #[doc = "Open Drain Enabled"]
11175 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
11176 }
11177 }
11178 #[doc = "Pull / Keep Enable Field"]
11179 pub mod PKE {
11180 pub const offset: u32 = 12;
11181 pub const mask: u32 = 0x01 << offset;
11182 pub mod R {}
11183 pub mod W {}
11184 pub mod RW {
11185 #[doc = "Pull/Keeper Disabled"]
11186 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
11187 #[doc = "Pull/Keeper Enabled"]
11188 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
11189 }
11190 }
11191 #[doc = "Pull / Keep Select Field"]
11192 pub mod PUE {
11193 pub const offset: u32 = 13;
11194 pub const mask: u32 = 0x01 << offset;
11195 pub mod R {}
11196 pub mod W {}
11197 pub mod RW {
11198 #[doc = "Keeper"]
11199 pub const PUE_0_KEEPER: u32 = 0;
11200 #[doc = "Pull"]
11201 pub const PUE_1_PULL: u32 = 0x01;
11202 }
11203 }
11204 #[doc = "Pull Up / Down Config. Field"]
11205 pub mod PUS {
11206 pub const offset: u32 = 14;
11207 pub const mask: u32 = 0x03 << offset;
11208 pub mod R {}
11209 pub mod W {}
11210 pub mod RW {
11211 #[doc = "100K Ohm Pull Down"]
11212 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
11213 #[doc = "47K Ohm Pull Up"]
11214 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
11215 #[doc = "100K Ohm Pull Up"]
11216 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
11217 #[doc = "22K Ohm Pull Up"]
11218 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
11219 }
11220 }
11221 #[doc = "Hyst. Enable Field"]
11222 pub mod HYS {
11223 pub const offset: u32 = 16;
11224 pub const mask: u32 = 0x01 << offset;
11225 pub mod R {}
11226 pub mod W {}
11227 pub mod RW {
11228 #[doc = "Hysteresis Disabled"]
11229 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
11230 #[doc = "Hysteresis Enabled"]
11231 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
11232 }
11233 }
11234}
11235#[doc = "SW_PAD_CTL_PAD_GPIO_EMC_41 SW PAD Control Register"]
11236pub mod SW_PAD_CTL_PAD_GPIO_EMC_41 {
11237 #[doc = "Slew Rate Field"]
11238 pub mod SRE {
11239 pub const offset: u32 = 0;
11240 pub const mask: u32 = 0x01 << offset;
11241 pub mod R {}
11242 pub mod W {}
11243 pub mod RW {
11244 #[doc = "Slow Slew Rate"]
11245 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
11246 #[doc = "Fast Slew Rate"]
11247 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
11248 }
11249 }
11250 #[doc = "Drive Strength Field"]
11251 pub mod DSE {
11252 pub const offset: u32 = 3;
11253 pub const mask: u32 = 0x07 << offset;
11254 pub mod R {}
11255 pub mod W {}
11256 pub mod RW {
11257 #[doc = "output driver disabled;"]
11258 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
11259 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
11260 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
11261 #[doc = "R0/2"]
11262 pub const DSE_2_R0_2: u32 = 0x02;
11263 #[doc = "R0/3"]
11264 pub const DSE_3_R0_3: u32 = 0x03;
11265 #[doc = "R0/4"]
11266 pub const DSE_4_R0_4: u32 = 0x04;
11267 #[doc = "R0/5"]
11268 pub const DSE_5_R0_5: u32 = 0x05;
11269 #[doc = "R0/6"]
11270 pub const DSE_6_R0_6: u32 = 0x06;
11271 #[doc = "R0/7"]
11272 pub const DSE_7_R0_7: u32 = 0x07;
11273 }
11274 }
11275 #[doc = "Speed Field"]
11276 pub mod SPEED {
11277 pub const offset: u32 = 6;
11278 pub const mask: u32 = 0x03 << offset;
11279 pub mod R {}
11280 pub mod W {}
11281 pub mod RW {
11282 #[doc = "low(50MHz)"]
11283 pub const SPEED_0_LOW_50MHZ: u32 = 0;
11284 #[doc = "medium(100MHz)"]
11285 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
11286 #[doc = "medium(100MHz)"]
11287 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
11288 #[doc = "max(200MHz)"]
11289 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
11290 }
11291 }
11292 #[doc = "Open Drain Enable Field"]
11293 pub mod ODE {
11294 pub const offset: u32 = 11;
11295 pub const mask: u32 = 0x01 << offset;
11296 pub mod R {}
11297 pub mod W {}
11298 pub mod RW {
11299 #[doc = "Open Drain Disabled"]
11300 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
11301 #[doc = "Open Drain Enabled"]
11302 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
11303 }
11304 }
11305 #[doc = "Pull / Keep Enable Field"]
11306 pub mod PKE {
11307 pub const offset: u32 = 12;
11308 pub const mask: u32 = 0x01 << offset;
11309 pub mod R {}
11310 pub mod W {}
11311 pub mod RW {
11312 #[doc = "Pull/Keeper Disabled"]
11313 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
11314 #[doc = "Pull/Keeper Enabled"]
11315 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
11316 }
11317 }
11318 #[doc = "Pull / Keep Select Field"]
11319 pub mod PUE {
11320 pub const offset: u32 = 13;
11321 pub const mask: u32 = 0x01 << offset;
11322 pub mod R {}
11323 pub mod W {}
11324 pub mod RW {
11325 #[doc = "Keeper"]
11326 pub const PUE_0_KEEPER: u32 = 0;
11327 #[doc = "Pull"]
11328 pub const PUE_1_PULL: u32 = 0x01;
11329 }
11330 }
11331 #[doc = "Pull Up / Down Config. Field"]
11332 pub mod PUS {
11333 pub const offset: u32 = 14;
11334 pub const mask: u32 = 0x03 << offset;
11335 pub mod R {}
11336 pub mod W {}
11337 pub mod RW {
11338 #[doc = "100K Ohm Pull Down"]
11339 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
11340 #[doc = "47K Ohm Pull Up"]
11341 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
11342 #[doc = "100K Ohm Pull Up"]
11343 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
11344 #[doc = "22K Ohm Pull Up"]
11345 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
11346 }
11347 }
11348 #[doc = "Hyst. Enable Field"]
11349 pub mod HYS {
11350 pub const offset: u32 = 16;
11351 pub const mask: u32 = 0x01 << offset;
11352 pub mod R {}
11353 pub mod W {}
11354 pub mod RW {
11355 #[doc = "Hysteresis Disabled"]
11356 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
11357 #[doc = "Hysteresis Enabled"]
11358 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
11359 }
11360 }
11361}
11362#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_00 SW PAD Control Register"]
11363pub mod SW_PAD_CTL_PAD_GPIO_AD_B0_00 {
11364 #[doc = "Slew Rate Field"]
11365 pub mod SRE {
11366 pub const offset: u32 = 0;
11367 pub const mask: u32 = 0x01 << offset;
11368 pub mod R {}
11369 pub mod W {}
11370 pub mod RW {
11371 #[doc = "Slow Slew Rate"]
11372 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
11373 #[doc = "Fast Slew Rate"]
11374 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
11375 }
11376 }
11377 #[doc = "Drive Strength Field"]
11378 pub mod DSE {
11379 pub const offset: u32 = 3;
11380 pub const mask: u32 = 0x07 << offset;
11381 pub mod R {}
11382 pub mod W {}
11383 pub mod RW {
11384 #[doc = "output driver disabled;"]
11385 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
11386 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
11387 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
11388 #[doc = "R0/2"]
11389 pub const DSE_2_R0_2: u32 = 0x02;
11390 #[doc = "R0/3"]
11391 pub const DSE_3_R0_3: u32 = 0x03;
11392 #[doc = "R0/4"]
11393 pub const DSE_4_R0_4: u32 = 0x04;
11394 #[doc = "R0/5"]
11395 pub const DSE_5_R0_5: u32 = 0x05;
11396 #[doc = "R0/6"]
11397 pub const DSE_6_R0_6: u32 = 0x06;
11398 #[doc = "R0/7"]
11399 pub const DSE_7_R0_7: u32 = 0x07;
11400 }
11401 }
11402 #[doc = "Speed Field"]
11403 pub mod SPEED {
11404 pub const offset: u32 = 6;
11405 pub const mask: u32 = 0x03 << offset;
11406 pub mod R {}
11407 pub mod W {}
11408 pub mod RW {
11409 #[doc = "low(50MHz)"]
11410 pub const SPEED_0_LOW_50MHZ: u32 = 0;
11411 #[doc = "medium(100MHz)"]
11412 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
11413 #[doc = "medium(100MHz)"]
11414 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
11415 #[doc = "max(200MHz)"]
11416 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
11417 }
11418 }
11419 #[doc = "Open Drain Enable Field"]
11420 pub mod ODE {
11421 pub const offset: u32 = 11;
11422 pub const mask: u32 = 0x01 << offset;
11423 pub mod R {}
11424 pub mod W {}
11425 pub mod RW {
11426 #[doc = "Open Drain Disabled"]
11427 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
11428 #[doc = "Open Drain Enabled"]
11429 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
11430 }
11431 }
11432 #[doc = "Pull / Keep Enable Field"]
11433 pub mod PKE {
11434 pub const offset: u32 = 12;
11435 pub const mask: u32 = 0x01 << offset;
11436 pub mod R {}
11437 pub mod W {}
11438 pub mod RW {
11439 #[doc = "Pull/Keeper Disabled"]
11440 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
11441 #[doc = "Pull/Keeper Enabled"]
11442 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
11443 }
11444 }
11445 #[doc = "Pull / Keep Select Field"]
11446 pub mod PUE {
11447 pub const offset: u32 = 13;
11448 pub const mask: u32 = 0x01 << offset;
11449 pub mod R {}
11450 pub mod W {}
11451 pub mod RW {
11452 #[doc = "Keeper"]
11453 pub const PUE_0_KEEPER: u32 = 0;
11454 #[doc = "Pull"]
11455 pub const PUE_1_PULL: u32 = 0x01;
11456 }
11457 }
11458 #[doc = "Pull Up / Down Config. Field"]
11459 pub mod PUS {
11460 pub const offset: u32 = 14;
11461 pub const mask: u32 = 0x03 << offset;
11462 pub mod R {}
11463 pub mod W {}
11464 pub mod RW {
11465 #[doc = "100K Ohm Pull Down"]
11466 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
11467 #[doc = "47K Ohm Pull Up"]
11468 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
11469 #[doc = "100K Ohm Pull Up"]
11470 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
11471 #[doc = "22K Ohm Pull Up"]
11472 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
11473 }
11474 }
11475 #[doc = "Hyst. Enable Field"]
11476 pub mod HYS {
11477 pub const offset: u32 = 16;
11478 pub const mask: u32 = 0x01 << offset;
11479 pub mod R {}
11480 pub mod W {}
11481 pub mod RW {
11482 #[doc = "Hysteresis Disabled"]
11483 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
11484 #[doc = "Hysteresis Enabled"]
11485 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
11486 }
11487 }
11488}
11489#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_01 SW PAD Control Register"]
11490pub mod SW_PAD_CTL_PAD_GPIO_AD_B0_01 {
11491 #[doc = "Slew Rate Field"]
11492 pub mod SRE {
11493 pub const offset: u32 = 0;
11494 pub const mask: u32 = 0x01 << offset;
11495 pub mod R {}
11496 pub mod W {}
11497 pub mod RW {
11498 #[doc = "Slow Slew Rate"]
11499 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
11500 #[doc = "Fast Slew Rate"]
11501 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
11502 }
11503 }
11504 #[doc = "Drive Strength Field"]
11505 pub mod DSE {
11506 pub const offset: u32 = 3;
11507 pub const mask: u32 = 0x07 << offset;
11508 pub mod R {}
11509 pub mod W {}
11510 pub mod RW {
11511 #[doc = "output driver disabled;"]
11512 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
11513 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
11514 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
11515 #[doc = "R0/2"]
11516 pub const DSE_2_R0_2: u32 = 0x02;
11517 #[doc = "R0/3"]
11518 pub const DSE_3_R0_3: u32 = 0x03;
11519 #[doc = "R0/4"]
11520 pub const DSE_4_R0_4: u32 = 0x04;
11521 #[doc = "R0/5"]
11522 pub const DSE_5_R0_5: u32 = 0x05;
11523 #[doc = "R0/6"]
11524 pub const DSE_6_R0_6: u32 = 0x06;
11525 #[doc = "R0/7"]
11526 pub const DSE_7_R0_7: u32 = 0x07;
11527 }
11528 }
11529 #[doc = "Speed Field"]
11530 pub mod SPEED {
11531 pub const offset: u32 = 6;
11532 pub const mask: u32 = 0x03 << offset;
11533 pub mod R {}
11534 pub mod W {}
11535 pub mod RW {
11536 #[doc = "low(50MHz)"]
11537 pub const SPEED_0_LOW_50MHZ: u32 = 0;
11538 #[doc = "medium(100MHz)"]
11539 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
11540 #[doc = "medium(100MHz)"]
11541 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
11542 #[doc = "max(200MHz)"]
11543 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
11544 }
11545 }
11546 #[doc = "Open Drain Enable Field"]
11547 pub mod ODE {
11548 pub const offset: u32 = 11;
11549 pub const mask: u32 = 0x01 << offset;
11550 pub mod R {}
11551 pub mod W {}
11552 pub mod RW {
11553 #[doc = "Open Drain Disabled"]
11554 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
11555 #[doc = "Open Drain Enabled"]
11556 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
11557 }
11558 }
11559 #[doc = "Pull / Keep Enable Field"]
11560 pub mod PKE {
11561 pub const offset: u32 = 12;
11562 pub const mask: u32 = 0x01 << offset;
11563 pub mod R {}
11564 pub mod W {}
11565 pub mod RW {
11566 #[doc = "Pull/Keeper Disabled"]
11567 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
11568 #[doc = "Pull/Keeper Enabled"]
11569 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
11570 }
11571 }
11572 #[doc = "Pull / Keep Select Field"]
11573 pub mod PUE {
11574 pub const offset: u32 = 13;
11575 pub const mask: u32 = 0x01 << offset;
11576 pub mod R {}
11577 pub mod W {}
11578 pub mod RW {
11579 #[doc = "Keeper"]
11580 pub const PUE_0_KEEPER: u32 = 0;
11581 #[doc = "Pull"]
11582 pub const PUE_1_PULL: u32 = 0x01;
11583 }
11584 }
11585 #[doc = "Pull Up / Down Config. Field"]
11586 pub mod PUS {
11587 pub const offset: u32 = 14;
11588 pub const mask: u32 = 0x03 << offset;
11589 pub mod R {}
11590 pub mod W {}
11591 pub mod RW {
11592 #[doc = "100K Ohm Pull Down"]
11593 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
11594 #[doc = "47K Ohm Pull Up"]
11595 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
11596 #[doc = "100K Ohm Pull Up"]
11597 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
11598 #[doc = "22K Ohm Pull Up"]
11599 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
11600 }
11601 }
11602 #[doc = "Hyst. Enable Field"]
11603 pub mod HYS {
11604 pub const offset: u32 = 16;
11605 pub const mask: u32 = 0x01 << offset;
11606 pub mod R {}
11607 pub mod W {}
11608 pub mod RW {
11609 #[doc = "Hysteresis Disabled"]
11610 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
11611 #[doc = "Hysteresis Enabled"]
11612 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
11613 }
11614 }
11615}
11616#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_02 SW PAD Control Register"]
11617pub mod SW_PAD_CTL_PAD_GPIO_AD_B0_02 {
11618 #[doc = "Slew Rate Field"]
11619 pub mod SRE {
11620 pub const offset: u32 = 0;
11621 pub const mask: u32 = 0x01 << offset;
11622 pub mod R {}
11623 pub mod W {}
11624 pub mod RW {
11625 #[doc = "Slow Slew Rate"]
11626 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
11627 #[doc = "Fast Slew Rate"]
11628 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
11629 }
11630 }
11631 #[doc = "Drive Strength Field"]
11632 pub mod DSE {
11633 pub const offset: u32 = 3;
11634 pub const mask: u32 = 0x07 << offset;
11635 pub mod R {}
11636 pub mod W {}
11637 pub mod RW {
11638 #[doc = "output driver disabled;"]
11639 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
11640 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
11641 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
11642 #[doc = "R0/2"]
11643 pub const DSE_2_R0_2: u32 = 0x02;
11644 #[doc = "R0/3"]
11645 pub const DSE_3_R0_3: u32 = 0x03;
11646 #[doc = "R0/4"]
11647 pub const DSE_4_R0_4: u32 = 0x04;
11648 #[doc = "R0/5"]
11649 pub const DSE_5_R0_5: u32 = 0x05;
11650 #[doc = "R0/6"]
11651 pub const DSE_6_R0_6: u32 = 0x06;
11652 #[doc = "R0/7"]
11653 pub const DSE_7_R0_7: u32 = 0x07;
11654 }
11655 }
11656 #[doc = "Speed Field"]
11657 pub mod SPEED {
11658 pub const offset: u32 = 6;
11659 pub const mask: u32 = 0x03 << offset;
11660 pub mod R {}
11661 pub mod W {}
11662 pub mod RW {
11663 #[doc = "low(50MHz)"]
11664 pub const SPEED_0_LOW_50MHZ: u32 = 0;
11665 #[doc = "medium(100MHz)"]
11666 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
11667 #[doc = "medium(100MHz)"]
11668 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
11669 #[doc = "max(200MHz)"]
11670 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
11671 }
11672 }
11673 #[doc = "Open Drain Enable Field"]
11674 pub mod ODE {
11675 pub const offset: u32 = 11;
11676 pub const mask: u32 = 0x01 << offset;
11677 pub mod R {}
11678 pub mod W {}
11679 pub mod RW {
11680 #[doc = "Open Drain Disabled"]
11681 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
11682 #[doc = "Open Drain Enabled"]
11683 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
11684 }
11685 }
11686 #[doc = "Pull / Keep Enable Field"]
11687 pub mod PKE {
11688 pub const offset: u32 = 12;
11689 pub const mask: u32 = 0x01 << offset;
11690 pub mod R {}
11691 pub mod W {}
11692 pub mod RW {
11693 #[doc = "Pull/Keeper Disabled"]
11694 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
11695 #[doc = "Pull/Keeper Enabled"]
11696 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
11697 }
11698 }
11699 #[doc = "Pull / Keep Select Field"]
11700 pub mod PUE {
11701 pub const offset: u32 = 13;
11702 pub const mask: u32 = 0x01 << offset;
11703 pub mod R {}
11704 pub mod W {}
11705 pub mod RW {
11706 #[doc = "Keeper"]
11707 pub const PUE_0_KEEPER: u32 = 0;
11708 #[doc = "Pull"]
11709 pub const PUE_1_PULL: u32 = 0x01;
11710 }
11711 }
11712 #[doc = "Pull Up / Down Config. Field"]
11713 pub mod PUS {
11714 pub const offset: u32 = 14;
11715 pub const mask: u32 = 0x03 << offset;
11716 pub mod R {}
11717 pub mod W {}
11718 pub mod RW {
11719 #[doc = "100K Ohm Pull Down"]
11720 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
11721 #[doc = "47K Ohm Pull Up"]
11722 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
11723 #[doc = "100K Ohm Pull Up"]
11724 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
11725 #[doc = "22K Ohm Pull Up"]
11726 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
11727 }
11728 }
11729 #[doc = "Hyst. Enable Field"]
11730 pub mod HYS {
11731 pub const offset: u32 = 16;
11732 pub const mask: u32 = 0x01 << offset;
11733 pub mod R {}
11734 pub mod W {}
11735 pub mod RW {
11736 #[doc = "Hysteresis Disabled"]
11737 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
11738 #[doc = "Hysteresis Enabled"]
11739 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
11740 }
11741 }
11742}
11743#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_03 SW PAD Control Register"]
11744pub mod SW_PAD_CTL_PAD_GPIO_AD_B0_03 {
11745 #[doc = "Slew Rate Field"]
11746 pub mod SRE {
11747 pub const offset: u32 = 0;
11748 pub const mask: u32 = 0x01 << offset;
11749 pub mod R {}
11750 pub mod W {}
11751 pub mod RW {
11752 #[doc = "Slow Slew Rate"]
11753 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
11754 #[doc = "Fast Slew Rate"]
11755 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
11756 }
11757 }
11758 #[doc = "Drive Strength Field"]
11759 pub mod DSE {
11760 pub const offset: u32 = 3;
11761 pub const mask: u32 = 0x07 << offset;
11762 pub mod R {}
11763 pub mod W {}
11764 pub mod RW {
11765 #[doc = "output driver disabled;"]
11766 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
11767 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
11768 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
11769 #[doc = "R0/2"]
11770 pub const DSE_2_R0_2: u32 = 0x02;
11771 #[doc = "R0/3"]
11772 pub const DSE_3_R0_3: u32 = 0x03;
11773 #[doc = "R0/4"]
11774 pub const DSE_4_R0_4: u32 = 0x04;
11775 #[doc = "R0/5"]
11776 pub const DSE_5_R0_5: u32 = 0x05;
11777 #[doc = "R0/6"]
11778 pub const DSE_6_R0_6: u32 = 0x06;
11779 #[doc = "R0/7"]
11780 pub const DSE_7_R0_7: u32 = 0x07;
11781 }
11782 }
11783 #[doc = "Speed Field"]
11784 pub mod SPEED {
11785 pub const offset: u32 = 6;
11786 pub const mask: u32 = 0x03 << offset;
11787 pub mod R {}
11788 pub mod W {}
11789 pub mod RW {
11790 #[doc = "low(50MHz)"]
11791 pub const SPEED_0_LOW_50MHZ: u32 = 0;
11792 #[doc = "medium(100MHz)"]
11793 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
11794 #[doc = "medium(100MHz)"]
11795 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
11796 #[doc = "max(200MHz)"]
11797 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
11798 }
11799 }
11800 #[doc = "Open Drain Enable Field"]
11801 pub mod ODE {
11802 pub const offset: u32 = 11;
11803 pub const mask: u32 = 0x01 << offset;
11804 pub mod R {}
11805 pub mod W {}
11806 pub mod RW {
11807 #[doc = "Open Drain Disabled"]
11808 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
11809 #[doc = "Open Drain Enabled"]
11810 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
11811 }
11812 }
11813 #[doc = "Pull / Keep Enable Field"]
11814 pub mod PKE {
11815 pub const offset: u32 = 12;
11816 pub const mask: u32 = 0x01 << offset;
11817 pub mod R {}
11818 pub mod W {}
11819 pub mod RW {
11820 #[doc = "Pull/Keeper Disabled"]
11821 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
11822 #[doc = "Pull/Keeper Enabled"]
11823 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
11824 }
11825 }
11826 #[doc = "Pull / Keep Select Field"]
11827 pub mod PUE {
11828 pub const offset: u32 = 13;
11829 pub const mask: u32 = 0x01 << offset;
11830 pub mod R {}
11831 pub mod W {}
11832 pub mod RW {
11833 #[doc = "Keeper"]
11834 pub const PUE_0_KEEPER: u32 = 0;
11835 #[doc = "Pull"]
11836 pub const PUE_1_PULL: u32 = 0x01;
11837 }
11838 }
11839 #[doc = "Pull Up / Down Config. Field"]
11840 pub mod PUS {
11841 pub const offset: u32 = 14;
11842 pub const mask: u32 = 0x03 << offset;
11843 pub mod R {}
11844 pub mod W {}
11845 pub mod RW {
11846 #[doc = "100K Ohm Pull Down"]
11847 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
11848 #[doc = "47K Ohm Pull Up"]
11849 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
11850 #[doc = "100K Ohm Pull Up"]
11851 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
11852 #[doc = "22K Ohm Pull Up"]
11853 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
11854 }
11855 }
11856 #[doc = "Hyst. Enable Field"]
11857 pub mod HYS {
11858 pub const offset: u32 = 16;
11859 pub const mask: u32 = 0x01 << offset;
11860 pub mod R {}
11861 pub mod W {}
11862 pub mod RW {
11863 #[doc = "Hysteresis Disabled"]
11864 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
11865 #[doc = "Hysteresis Enabled"]
11866 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
11867 }
11868 }
11869}
11870#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_04 SW PAD Control Register"]
11871pub mod SW_PAD_CTL_PAD_GPIO_AD_B0_04 {
11872 #[doc = "Slew Rate Field"]
11873 pub mod SRE {
11874 pub const offset: u32 = 0;
11875 pub const mask: u32 = 0x01 << offset;
11876 pub mod R {}
11877 pub mod W {}
11878 pub mod RW {
11879 #[doc = "Slow Slew Rate"]
11880 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
11881 #[doc = "Fast Slew Rate"]
11882 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
11883 }
11884 }
11885 #[doc = "Drive Strength Field"]
11886 pub mod DSE {
11887 pub const offset: u32 = 3;
11888 pub const mask: u32 = 0x07 << offset;
11889 pub mod R {}
11890 pub mod W {}
11891 pub mod RW {
11892 #[doc = "output driver disabled;"]
11893 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
11894 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
11895 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
11896 #[doc = "R0/2"]
11897 pub const DSE_2_R0_2: u32 = 0x02;
11898 #[doc = "R0/3"]
11899 pub const DSE_3_R0_3: u32 = 0x03;
11900 #[doc = "R0/4"]
11901 pub const DSE_4_R0_4: u32 = 0x04;
11902 #[doc = "R0/5"]
11903 pub const DSE_5_R0_5: u32 = 0x05;
11904 #[doc = "R0/6"]
11905 pub const DSE_6_R0_6: u32 = 0x06;
11906 #[doc = "R0/7"]
11907 pub const DSE_7_R0_7: u32 = 0x07;
11908 }
11909 }
11910 #[doc = "Speed Field"]
11911 pub mod SPEED {
11912 pub const offset: u32 = 6;
11913 pub const mask: u32 = 0x03 << offset;
11914 pub mod R {}
11915 pub mod W {}
11916 pub mod RW {
11917 #[doc = "low(50MHz)"]
11918 pub const SPEED_0_LOW_50MHZ: u32 = 0;
11919 #[doc = "medium(100MHz)"]
11920 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
11921 #[doc = "medium(100MHz)"]
11922 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
11923 #[doc = "max(200MHz)"]
11924 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
11925 }
11926 }
11927 #[doc = "Open Drain Enable Field"]
11928 pub mod ODE {
11929 pub const offset: u32 = 11;
11930 pub const mask: u32 = 0x01 << offset;
11931 pub mod R {}
11932 pub mod W {}
11933 pub mod RW {
11934 #[doc = "Open Drain Disabled"]
11935 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
11936 #[doc = "Open Drain Enabled"]
11937 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
11938 }
11939 }
11940 #[doc = "Pull / Keep Enable Field"]
11941 pub mod PKE {
11942 pub const offset: u32 = 12;
11943 pub const mask: u32 = 0x01 << offset;
11944 pub mod R {}
11945 pub mod W {}
11946 pub mod RW {
11947 #[doc = "Pull/Keeper Disabled"]
11948 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
11949 #[doc = "Pull/Keeper Enabled"]
11950 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
11951 }
11952 }
11953 #[doc = "Pull / Keep Select Field"]
11954 pub mod PUE {
11955 pub const offset: u32 = 13;
11956 pub const mask: u32 = 0x01 << offset;
11957 pub mod R {}
11958 pub mod W {}
11959 pub mod RW {
11960 #[doc = "Keeper"]
11961 pub const PUE_0_KEEPER: u32 = 0;
11962 #[doc = "Pull"]
11963 pub const PUE_1_PULL: u32 = 0x01;
11964 }
11965 }
11966 #[doc = "Pull Up / Down Config. Field"]
11967 pub mod PUS {
11968 pub const offset: u32 = 14;
11969 pub const mask: u32 = 0x03 << offset;
11970 pub mod R {}
11971 pub mod W {}
11972 pub mod RW {
11973 #[doc = "100K Ohm Pull Down"]
11974 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
11975 #[doc = "47K Ohm Pull Up"]
11976 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
11977 #[doc = "100K Ohm Pull Up"]
11978 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
11979 #[doc = "22K Ohm Pull Up"]
11980 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
11981 }
11982 }
11983 #[doc = "Hyst. Enable Field"]
11984 pub mod HYS {
11985 pub const offset: u32 = 16;
11986 pub const mask: u32 = 0x01 << offset;
11987 pub mod R {}
11988 pub mod W {}
11989 pub mod RW {
11990 #[doc = "Hysteresis Disabled"]
11991 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
11992 #[doc = "Hysteresis Enabled"]
11993 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
11994 }
11995 }
11996}
11997#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_05 SW PAD Control Register"]
11998pub mod SW_PAD_CTL_PAD_GPIO_AD_B0_05 {
11999 #[doc = "Slew Rate Field"]
12000 pub mod SRE {
12001 pub const offset: u32 = 0;
12002 pub const mask: u32 = 0x01 << offset;
12003 pub mod R {}
12004 pub mod W {}
12005 pub mod RW {
12006 #[doc = "Slow Slew Rate"]
12007 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
12008 #[doc = "Fast Slew Rate"]
12009 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
12010 }
12011 }
12012 #[doc = "Drive Strength Field"]
12013 pub mod DSE {
12014 pub const offset: u32 = 3;
12015 pub const mask: u32 = 0x07 << offset;
12016 pub mod R {}
12017 pub mod W {}
12018 pub mod RW {
12019 #[doc = "output driver disabled;"]
12020 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
12021 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
12022 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
12023 #[doc = "R0/2"]
12024 pub const DSE_2_R0_2: u32 = 0x02;
12025 #[doc = "R0/3"]
12026 pub const DSE_3_R0_3: u32 = 0x03;
12027 #[doc = "R0/4"]
12028 pub const DSE_4_R0_4: u32 = 0x04;
12029 #[doc = "R0/5"]
12030 pub const DSE_5_R0_5: u32 = 0x05;
12031 #[doc = "R0/6"]
12032 pub const DSE_6_R0_6: u32 = 0x06;
12033 #[doc = "R0/7"]
12034 pub const DSE_7_R0_7: u32 = 0x07;
12035 }
12036 }
12037 #[doc = "Speed Field"]
12038 pub mod SPEED {
12039 pub const offset: u32 = 6;
12040 pub const mask: u32 = 0x03 << offset;
12041 pub mod R {}
12042 pub mod W {}
12043 pub mod RW {
12044 #[doc = "low(50MHz)"]
12045 pub const SPEED_0_LOW_50MHZ: u32 = 0;
12046 #[doc = "medium(100MHz)"]
12047 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
12048 #[doc = "medium(100MHz)"]
12049 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
12050 #[doc = "max(200MHz)"]
12051 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
12052 }
12053 }
12054 #[doc = "Open Drain Enable Field"]
12055 pub mod ODE {
12056 pub const offset: u32 = 11;
12057 pub const mask: u32 = 0x01 << offset;
12058 pub mod R {}
12059 pub mod W {}
12060 pub mod RW {
12061 #[doc = "Open Drain Disabled"]
12062 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
12063 #[doc = "Open Drain Enabled"]
12064 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
12065 }
12066 }
12067 #[doc = "Pull / Keep Enable Field"]
12068 pub mod PKE {
12069 pub const offset: u32 = 12;
12070 pub const mask: u32 = 0x01 << offset;
12071 pub mod R {}
12072 pub mod W {}
12073 pub mod RW {
12074 #[doc = "Pull/Keeper Disabled"]
12075 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
12076 #[doc = "Pull/Keeper Enabled"]
12077 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
12078 }
12079 }
12080 #[doc = "Pull / Keep Select Field"]
12081 pub mod PUE {
12082 pub const offset: u32 = 13;
12083 pub const mask: u32 = 0x01 << offset;
12084 pub mod R {}
12085 pub mod W {}
12086 pub mod RW {
12087 #[doc = "Keeper"]
12088 pub const PUE_0_KEEPER: u32 = 0;
12089 #[doc = "Pull"]
12090 pub const PUE_1_PULL: u32 = 0x01;
12091 }
12092 }
12093 #[doc = "Pull Up / Down Config. Field"]
12094 pub mod PUS {
12095 pub const offset: u32 = 14;
12096 pub const mask: u32 = 0x03 << offset;
12097 pub mod R {}
12098 pub mod W {}
12099 pub mod RW {
12100 #[doc = "100K Ohm Pull Down"]
12101 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
12102 #[doc = "47K Ohm Pull Up"]
12103 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
12104 #[doc = "100K Ohm Pull Up"]
12105 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
12106 #[doc = "22K Ohm Pull Up"]
12107 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
12108 }
12109 }
12110 #[doc = "Hyst. Enable Field"]
12111 pub mod HYS {
12112 pub const offset: u32 = 16;
12113 pub const mask: u32 = 0x01 << offset;
12114 pub mod R {}
12115 pub mod W {}
12116 pub mod RW {
12117 #[doc = "Hysteresis Disabled"]
12118 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
12119 #[doc = "Hysteresis Enabled"]
12120 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
12121 }
12122 }
12123}
12124#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_06 SW PAD Control Register"]
12125pub mod SW_PAD_CTL_PAD_GPIO_AD_B0_06 {
12126 #[doc = "Slew Rate Field"]
12127 pub mod SRE {
12128 pub const offset: u32 = 0;
12129 pub const mask: u32 = 0x01 << offset;
12130 pub mod R {}
12131 pub mod W {}
12132 pub mod RW {
12133 #[doc = "Slow Slew Rate"]
12134 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
12135 #[doc = "Fast Slew Rate"]
12136 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
12137 }
12138 }
12139 #[doc = "Drive Strength Field"]
12140 pub mod DSE {
12141 pub const offset: u32 = 3;
12142 pub const mask: u32 = 0x07 << offset;
12143 pub mod R {}
12144 pub mod W {}
12145 pub mod RW {
12146 #[doc = "output driver disabled;"]
12147 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
12148 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
12149 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
12150 #[doc = "R0/2"]
12151 pub const DSE_2_R0_2: u32 = 0x02;
12152 #[doc = "R0/3"]
12153 pub const DSE_3_R0_3: u32 = 0x03;
12154 #[doc = "R0/4"]
12155 pub const DSE_4_R0_4: u32 = 0x04;
12156 #[doc = "R0/5"]
12157 pub const DSE_5_R0_5: u32 = 0x05;
12158 #[doc = "R0/6"]
12159 pub const DSE_6_R0_6: u32 = 0x06;
12160 #[doc = "R0/7"]
12161 pub const DSE_7_R0_7: u32 = 0x07;
12162 }
12163 }
12164 #[doc = "Speed Field"]
12165 pub mod SPEED {
12166 pub const offset: u32 = 6;
12167 pub const mask: u32 = 0x03 << offset;
12168 pub mod R {}
12169 pub mod W {}
12170 pub mod RW {
12171 #[doc = "low(50MHz)"]
12172 pub const SPEED_0_LOW_50MHZ: u32 = 0;
12173 #[doc = "medium(100MHz)"]
12174 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
12175 #[doc = "medium(100MHz)"]
12176 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
12177 #[doc = "max(200MHz)"]
12178 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
12179 }
12180 }
12181 #[doc = "Open Drain Enable Field"]
12182 pub mod ODE {
12183 pub const offset: u32 = 11;
12184 pub const mask: u32 = 0x01 << offset;
12185 pub mod R {}
12186 pub mod W {}
12187 pub mod RW {
12188 #[doc = "Open Drain Disabled"]
12189 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
12190 #[doc = "Open Drain Enabled"]
12191 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
12192 }
12193 }
12194 #[doc = "Pull / Keep Enable Field"]
12195 pub mod PKE {
12196 pub const offset: u32 = 12;
12197 pub const mask: u32 = 0x01 << offset;
12198 pub mod R {}
12199 pub mod W {}
12200 pub mod RW {
12201 #[doc = "Pull/Keeper Disabled"]
12202 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
12203 #[doc = "Pull/Keeper Enabled"]
12204 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
12205 }
12206 }
12207 #[doc = "Pull / Keep Select Field"]
12208 pub mod PUE {
12209 pub const offset: u32 = 13;
12210 pub const mask: u32 = 0x01 << offset;
12211 pub mod R {}
12212 pub mod W {}
12213 pub mod RW {
12214 #[doc = "Keeper"]
12215 pub const PUE_0_KEEPER: u32 = 0;
12216 #[doc = "Pull"]
12217 pub const PUE_1_PULL: u32 = 0x01;
12218 }
12219 }
12220 #[doc = "Pull Up / Down Config. Field"]
12221 pub mod PUS {
12222 pub const offset: u32 = 14;
12223 pub const mask: u32 = 0x03 << offset;
12224 pub mod R {}
12225 pub mod W {}
12226 pub mod RW {
12227 #[doc = "100K Ohm Pull Down"]
12228 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
12229 #[doc = "47K Ohm Pull Up"]
12230 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
12231 #[doc = "100K Ohm Pull Up"]
12232 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
12233 #[doc = "22K Ohm Pull Up"]
12234 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
12235 }
12236 }
12237 #[doc = "Hyst. Enable Field"]
12238 pub mod HYS {
12239 pub const offset: u32 = 16;
12240 pub const mask: u32 = 0x01 << offset;
12241 pub mod R {}
12242 pub mod W {}
12243 pub mod RW {
12244 #[doc = "Hysteresis Disabled"]
12245 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
12246 #[doc = "Hysteresis Enabled"]
12247 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
12248 }
12249 }
12250}
12251#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_07 SW PAD Control Register"]
12252pub mod SW_PAD_CTL_PAD_GPIO_AD_B0_07 {
12253 #[doc = "Slew Rate Field"]
12254 pub mod SRE {
12255 pub const offset: u32 = 0;
12256 pub const mask: u32 = 0x01 << offset;
12257 pub mod R {}
12258 pub mod W {}
12259 pub mod RW {
12260 #[doc = "Slow Slew Rate"]
12261 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
12262 #[doc = "Fast Slew Rate"]
12263 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
12264 }
12265 }
12266 #[doc = "Drive Strength Field"]
12267 pub mod DSE {
12268 pub const offset: u32 = 3;
12269 pub const mask: u32 = 0x07 << offset;
12270 pub mod R {}
12271 pub mod W {}
12272 pub mod RW {
12273 #[doc = "output driver disabled;"]
12274 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
12275 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
12276 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
12277 #[doc = "R0/2"]
12278 pub const DSE_2_R0_2: u32 = 0x02;
12279 #[doc = "R0/3"]
12280 pub const DSE_3_R0_3: u32 = 0x03;
12281 #[doc = "R0/4"]
12282 pub const DSE_4_R0_4: u32 = 0x04;
12283 #[doc = "R0/5"]
12284 pub const DSE_5_R0_5: u32 = 0x05;
12285 #[doc = "R0/6"]
12286 pub const DSE_6_R0_6: u32 = 0x06;
12287 #[doc = "R0/7"]
12288 pub const DSE_7_R0_7: u32 = 0x07;
12289 }
12290 }
12291 #[doc = "Speed Field"]
12292 pub mod SPEED {
12293 pub const offset: u32 = 6;
12294 pub const mask: u32 = 0x03 << offset;
12295 pub mod R {}
12296 pub mod W {}
12297 pub mod RW {
12298 #[doc = "low(50MHz)"]
12299 pub const SPEED_0_LOW_50MHZ: u32 = 0;
12300 #[doc = "medium(100MHz)"]
12301 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
12302 #[doc = "medium(100MHz)"]
12303 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
12304 #[doc = "max(200MHz)"]
12305 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
12306 }
12307 }
12308 #[doc = "Open Drain Enable Field"]
12309 pub mod ODE {
12310 pub const offset: u32 = 11;
12311 pub const mask: u32 = 0x01 << offset;
12312 pub mod R {}
12313 pub mod W {}
12314 pub mod RW {
12315 #[doc = "Open Drain Disabled"]
12316 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
12317 #[doc = "Open Drain Enabled"]
12318 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
12319 }
12320 }
12321 #[doc = "Pull / Keep Enable Field"]
12322 pub mod PKE {
12323 pub const offset: u32 = 12;
12324 pub const mask: u32 = 0x01 << offset;
12325 pub mod R {}
12326 pub mod W {}
12327 pub mod RW {
12328 #[doc = "Pull/Keeper Disabled"]
12329 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
12330 #[doc = "Pull/Keeper Enabled"]
12331 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
12332 }
12333 }
12334 #[doc = "Pull / Keep Select Field"]
12335 pub mod PUE {
12336 pub const offset: u32 = 13;
12337 pub const mask: u32 = 0x01 << offset;
12338 pub mod R {}
12339 pub mod W {}
12340 pub mod RW {
12341 #[doc = "Keeper"]
12342 pub const PUE_0_KEEPER: u32 = 0;
12343 #[doc = "Pull"]
12344 pub const PUE_1_PULL: u32 = 0x01;
12345 }
12346 }
12347 #[doc = "Pull Up / Down Config. Field"]
12348 pub mod PUS {
12349 pub const offset: u32 = 14;
12350 pub const mask: u32 = 0x03 << offset;
12351 pub mod R {}
12352 pub mod W {}
12353 pub mod RW {
12354 #[doc = "100K Ohm Pull Down"]
12355 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
12356 #[doc = "47K Ohm Pull Up"]
12357 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
12358 #[doc = "100K Ohm Pull Up"]
12359 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
12360 #[doc = "22K Ohm Pull Up"]
12361 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
12362 }
12363 }
12364 #[doc = "Hyst. Enable Field"]
12365 pub mod HYS {
12366 pub const offset: u32 = 16;
12367 pub const mask: u32 = 0x01 << offset;
12368 pub mod R {}
12369 pub mod W {}
12370 pub mod RW {
12371 #[doc = "Hysteresis Disabled"]
12372 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
12373 #[doc = "Hysteresis Enabled"]
12374 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
12375 }
12376 }
12377}
12378#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_08 SW PAD Control Register"]
12379pub mod SW_PAD_CTL_PAD_GPIO_AD_B0_08 {
12380 #[doc = "Slew Rate Field"]
12381 pub mod SRE {
12382 pub const offset: u32 = 0;
12383 pub const mask: u32 = 0x01 << offset;
12384 pub mod R {}
12385 pub mod W {}
12386 pub mod RW {
12387 #[doc = "Slow Slew Rate"]
12388 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
12389 #[doc = "Fast Slew Rate"]
12390 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
12391 }
12392 }
12393 #[doc = "Drive Strength Field"]
12394 pub mod DSE {
12395 pub const offset: u32 = 3;
12396 pub const mask: u32 = 0x07 << offset;
12397 pub mod R {}
12398 pub mod W {}
12399 pub mod RW {
12400 #[doc = "output driver disabled;"]
12401 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
12402 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
12403 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
12404 #[doc = "R0/2"]
12405 pub const DSE_2_R0_2: u32 = 0x02;
12406 #[doc = "R0/3"]
12407 pub const DSE_3_R0_3: u32 = 0x03;
12408 #[doc = "R0/4"]
12409 pub const DSE_4_R0_4: u32 = 0x04;
12410 #[doc = "R0/5"]
12411 pub const DSE_5_R0_5: u32 = 0x05;
12412 #[doc = "R0/6"]
12413 pub const DSE_6_R0_6: u32 = 0x06;
12414 #[doc = "R0/7"]
12415 pub const DSE_7_R0_7: u32 = 0x07;
12416 }
12417 }
12418 #[doc = "Speed Field"]
12419 pub mod SPEED {
12420 pub const offset: u32 = 6;
12421 pub const mask: u32 = 0x03 << offset;
12422 pub mod R {}
12423 pub mod W {}
12424 pub mod RW {
12425 #[doc = "low(50MHz)"]
12426 pub const SPEED_0_LOW_50MHZ: u32 = 0;
12427 #[doc = "medium(100MHz)"]
12428 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
12429 #[doc = "medium(100MHz)"]
12430 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
12431 #[doc = "max(200MHz)"]
12432 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
12433 }
12434 }
12435 #[doc = "Open Drain Enable Field"]
12436 pub mod ODE {
12437 pub const offset: u32 = 11;
12438 pub const mask: u32 = 0x01 << offset;
12439 pub mod R {}
12440 pub mod W {}
12441 pub mod RW {
12442 #[doc = "Open Drain Disabled"]
12443 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
12444 #[doc = "Open Drain Enabled"]
12445 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
12446 }
12447 }
12448 #[doc = "Pull / Keep Enable Field"]
12449 pub mod PKE {
12450 pub const offset: u32 = 12;
12451 pub const mask: u32 = 0x01 << offset;
12452 pub mod R {}
12453 pub mod W {}
12454 pub mod RW {
12455 #[doc = "Pull/Keeper Disabled"]
12456 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
12457 #[doc = "Pull/Keeper Enabled"]
12458 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
12459 }
12460 }
12461 #[doc = "Pull / Keep Select Field"]
12462 pub mod PUE {
12463 pub const offset: u32 = 13;
12464 pub const mask: u32 = 0x01 << offset;
12465 pub mod R {}
12466 pub mod W {}
12467 pub mod RW {
12468 #[doc = "Keeper"]
12469 pub const PUE_0_KEEPER: u32 = 0;
12470 #[doc = "Pull"]
12471 pub const PUE_1_PULL: u32 = 0x01;
12472 }
12473 }
12474 #[doc = "Pull Up / Down Config. Field"]
12475 pub mod PUS {
12476 pub const offset: u32 = 14;
12477 pub const mask: u32 = 0x03 << offset;
12478 pub mod R {}
12479 pub mod W {}
12480 pub mod RW {
12481 #[doc = "100K Ohm Pull Down"]
12482 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
12483 #[doc = "47K Ohm Pull Up"]
12484 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
12485 #[doc = "100K Ohm Pull Up"]
12486 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
12487 #[doc = "22K Ohm Pull Up"]
12488 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
12489 }
12490 }
12491 #[doc = "Hyst. Enable Field"]
12492 pub mod HYS {
12493 pub const offset: u32 = 16;
12494 pub const mask: u32 = 0x01 << offset;
12495 pub mod R {}
12496 pub mod W {}
12497 pub mod RW {
12498 #[doc = "Hysteresis Disabled"]
12499 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
12500 #[doc = "Hysteresis Enabled"]
12501 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
12502 }
12503 }
12504}
12505#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_09 SW PAD Control Register"]
12506pub mod SW_PAD_CTL_PAD_GPIO_AD_B0_09 {
12507 #[doc = "Slew Rate Field"]
12508 pub mod SRE {
12509 pub const offset: u32 = 0;
12510 pub const mask: u32 = 0x01 << offset;
12511 pub mod R {}
12512 pub mod W {}
12513 pub mod RW {
12514 #[doc = "Slow Slew Rate"]
12515 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
12516 #[doc = "Fast Slew Rate"]
12517 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
12518 }
12519 }
12520 #[doc = "Drive Strength Field"]
12521 pub mod DSE {
12522 pub const offset: u32 = 3;
12523 pub const mask: u32 = 0x07 << offset;
12524 pub mod R {}
12525 pub mod W {}
12526 pub mod RW {
12527 #[doc = "output driver disabled;"]
12528 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
12529 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
12530 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
12531 #[doc = "R0/2"]
12532 pub const DSE_2_R0_2: u32 = 0x02;
12533 #[doc = "R0/3"]
12534 pub const DSE_3_R0_3: u32 = 0x03;
12535 #[doc = "R0/4"]
12536 pub const DSE_4_R0_4: u32 = 0x04;
12537 #[doc = "R0/5"]
12538 pub const DSE_5_R0_5: u32 = 0x05;
12539 #[doc = "R0/6"]
12540 pub const DSE_6_R0_6: u32 = 0x06;
12541 #[doc = "R0/7"]
12542 pub const DSE_7_R0_7: u32 = 0x07;
12543 }
12544 }
12545 #[doc = "Speed Field"]
12546 pub mod SPEED {
12547 pub const offset: u32 = 6;
12548 pub const mask: u32 = 0x03 << offset;
12549 pub mod R {}
12550 pub mod W {}
12551 pub mod RW {
12552 #[doc = "low(50MHz)"]
12553 pub const SPEED_0_LOW_50MHZ: u32 = 0;
12554 #[doc = "medium(100MHz)"]
12555 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
12556 #[doc = "medium(100MHz)"]
12557 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
12558 #[doc = "max(200MHz)"]
12559 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
12560 }
12561 }
12562 #[doc = "Open Drain Enable Field"]
12563 pub mod ODE {
12564 pub const offset: u32 = 11;
12565 pub const mask: u32 = 0x01 << offset;
12566 pub mod R {}
12567 pub mod W {}
12568 pub mod RW {
12569 #[doc = "Open Drain Disabled"]
12570 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
12571 #[doc = "Open Drain Enabled"]
12572 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
12573 }
12574 }
12575 #[doc = "Pull / Keep Enable Field"]
12576 pub mod PKE {
12577 pub const offset: u32 = 12;
12578 pub const mask: u32 = 0x01 << offset;
12579 pub mod R {}
12580 pub mod W {}
12581 pub mod RW {
12582 #[doc = "Pull/Keeper Disabled"]
12583 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
12584 #[doc = "Pull/Keeper Enabled"]
12585 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
12586 }
12587 }
12588 #[doc = "Pull / Keep Select Field"]
12589 pub mod PUE {
12590 pub const offset: u32 = 13;
12591 pub const mask: u32 = 0x01 << offset;
12592 pub mod R {}
12593 pub mod W {}
12594 pub mod RW {
12595 #[doc = "Keeper"]
12596 pub const PUE_0_KEEPER: u32 = 0;
12597 #[doc = "Pull"]
12598 pub const PUE_1_PULL: u32 = 0x01;
12599 }
12600 }
12601 #[doc = "Pull Up / Down Config. Field"]
12602 pub mod PUS {
12603 pub const offset: u32 = 14;
12604 pub const mask: u32 = 0x03 << offset;
12605 pub mod R {}
12606 pub mod W {}
12607 pub mod RW {
12608 #[doc = "100K Ohm Pull Down"]
12609 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
12610 #[doc = "47K Ohm Pull Up"]
12611 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
12612 #[doc = "100K Ohm Pull Up"]
12613 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
12614 #[doc = "22K Ohm Pull Up"]
12615 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
12616 }
12617 }
12618 #[doc = "Hyst. Enable Field"]
12619 pub mod HYS {
12620 pub const offset: u32 = 16;
12621 pub const mask: u32 = 0x01 << offset;
12622 pub mod R {}
12623 pub mod W {}
12624 pub mod RW {
12625 #[doc = "Hysteresis Disabled"]
12626 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
12627 #[doc = "Hysteresis Enabled"]
12628 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
12629 }
12630 }
12631}
12632#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_10 SW PAD Control Register"]
12633pub mod SW_PAD_CTL_PAD_GPIO_AD_B0_10 {
12634 #[doc = "Slew Rate Field"]
12635 pub mod SRE {
12636 pub const offset: u32 = 0;
12637 pub const mask: u32 = 0x01 << offset;
12638 pub mod R {}
12639 pub mod W {}
12640 pub mod RW {
12641 #[doc = "Slow Slew Rate"]
12642 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
12643 #[doc = "Fast Slew Rate"]
12644 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
12645 }
12646 }
12647 #[doc = "Drive Strength Field"]
12648 pub mod DSE {
12649 pub const offset: u32 = 3;
12650 pub const mask: u32 = 0x07 << offset;
12651 pub mod R {}
12652 pub mod W {}
12653 pub mod RW {
12654 #[doc = "output driver disabled;"]
12655 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
12656 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
12657 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
12658 #[doc = "R0/2"]
12659 pub const DSE_2_R0_2: u32 = 0x02;
12660 #[doc = "R0/3"]
12661 pub const DSE_3_R0_3: u32 = 0x03;
12662 #[doc = "R0/4"]
12663 pub const DSE_4_R0_4: u32 = 0x04;
12664 #[doc = "R0/5"]
12665 pub const DSE_5_R0_5: u32 = 0x05;
12666 #[doc = "R0/6"]
12667 pub const DSE_6_R0_6: u32 = 0x06;
12668 #[doc = "R0/7"]
12669 pub const DSE_7_R0_7: u32 = 0x07;
12670 }
12671 }
12672 #[doc = "Speed Field"]
12673 pub mod SPEED {
12674 pub const offset: u32 = 6;
12675 pub const mask: u32 = 0x03 << offset;
12676 pub mod R {}
12677 pub mod W {}
12678 pub mod RW {
12679 #[doc = "low(50MHz)"]
12680 pub const SPEED_0_LOW_50MHZ: u32 = 0;
12681 #[doc = "medium(100MHz)"]
12682 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
12683 #[doc = "medium(100MHz)"]
12684 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
12685 #[doc = "max(200MHz)"]
12686 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
12687 }
12688 }
12689 #[doc = "Open Drain Enable Field"]
12690 pub mod ODE {
12691 pub const offset: u32 = 11;
12692 pub const mask: u32 = 0x01 << offset;
12693 pub mod R {}
12694 pub mod W {}
12695 pub mod RW {
12696 #[doc = "Open Drain Disabled"]
12697 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
12698 #[doc = "Open Drain Enabled"]
12699 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
12700 }
12701 }
12702 #[doc = "Pull / Keep Enable Field"]
12703 pub mod PKE {
12704 pub const offset: u32 = 12;
12705 pub const mask: u32 = 0x01 << offset;
12706 pub mod R {}
12707 pub mod W {}
12708 pub mod RW {
12709 #[doc = "Pull/Keeper Disabled"]
12710 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
12711 #[doc = "Pull/Keeper Enabled"]
12712 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
12713 }
12714 }
12715 #[doc = "Pull / Keep Select Field"]
12716 pub mod PUE {
12717 pub const offset: u32 = 13;
12718 pub const mask: u32 = 0x01 << offset;
12719 pub mod R {}
12720 pub mod W {}
12721 pub mod RW {
12722 #[doc = "Keeper"]
12723 pub const PUE_0_KEEPER: u32 = 0;
12724 #[doc = "Pull"]
12725 pub const PUE_1_PULL: u32 = 0x01;
12726 }
12727 }
12728 #[doc = "Pull Up / Down Config. Field"]
12729 pub mod PUS {
12730 pub const offset: u32 = 14;
12731 pub const mask: u32 = 0x03 << offset;
12732 pub mod R {}
12733 pub mod W {}
12734 pub mod RW {
12735 #[doc = "100K Ohm Pull Down"]
12736 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
12737 #[doc = "47K Ohm Pull Up"]
12738 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
12739 #[doc = "100K Ohm Pull Up"]
12740 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
12741 #[doc = "22K Ohm Pull Up"]
12742 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
12743 }
12744 }
12745 #[doc = "Hyst. Enable Field"]
12746 pub mod HYS {
12747 pub const offset: u32 = 16;
12748 pub const mask: u32 = 0x01 << offset;
12749 pub mod R {}
12750 pub mod W {}
12751 pub mod RW {
12752 #[doc = "Hysteresis Disabled"]
12753 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
12754 #[doc = "Hysteresis Enabled"]
12755 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
12756 }
12757 }
12758}
12759#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_11 SW PAD Control Register"]
12760pub mod SW_PAD_CTL_PAD_GPIO_AD_B0_11 {
12761 #[doc = "Slew Rate Field"]
12762 pub mod SRE {
12763 pub const offset: u32 = 0;
12764 pub const mask: u32 = 0x01 << offset;
12765 pub mod R {}
12766 pub mod W {}
12767 pub mod RW {
12768 #[doc = "Slow Slew Rate"]
12769 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
12770 #[doc = "Fast Slew Rate"]
12771 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
12772 }
12773 }
12774 #[doc = "Drive Strength Field"]
12775 pub mod DSE {
12776 pub const offset: u32 = 3;
12777 pub const mask: u32 = 0x07 << offset;
12778 pub mod R {}
12779 pub mod W {}
12780 pub mod RW {
12781 #[doc = "output driver disabled;"]
12782 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
12783 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
12784 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
12785 #[doc = "R0/2"]
12786 pub const DSE_2_R0_2: u32 = 0x02;
12787 #[doc = "R0/3"]
12788 pub const DSE_3_R0_3: u32 = 0x03;
12789 #[doc = "R0/4"]
12790 pub const DSE_4_R0_4: u32 = 0x04;
12791 #[doc = "R0/5"]
12792 pub const DSE_5_R0_5: u32 = 0x05;
12793 #[doc = "R0/6"]
12794 pub const DSE_6_R0_6: u32 = 0x06;
12795 #[doc = "R0/7"]
12796 pub const DSE_7_R0_7: u32 = 0x07;
12797 }
12798 }
12799 #[doc = "Speed Field"]
12800 pub mod SPEED {
12801 pub const offset: u32 = 6;
12802 pub const mask: u32 = 0x03 << offset;
12803 pub mod R {}
12804 pub mod W {}
12805 pub mod RW {
12806 #[doc = "low(50MHz)"]
12807 pub const SPEED_0_LOW_50MHZ: u32 = 0;
12808 #[doc = "medium(100MHz)"]
12809 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
12810 #[doc = "medium(100MHz)"]
12811 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
12812 #[doc = "max(200MHz)"]
12813 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
12814 }
12815 }
12816 #[doc = "Open Drain Enable Field"]
12817 pub mod ODE {
12818 pub const offset: u32 = 11;
12819 pub const mask: u32 = 0x01 << offset;
12820 pub mod R {}
12821 pub mod W {}
12822 pub mod RW {
12823 #[doc = "Open Drain Disabled"]
12824 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
12825 #[doc = "Open Drain Enabled"]
12826 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
12827 }
12828 }
12829 #[doc = "Pull / Keep Enable Field"]
12830 pub mod PKE {
12831 pub const offset: u32 = 12;
12832 pub const mask: u32 = 0x01 << offset;
12833 pub mod R {}
12834 pub mod W {}
12835 pub mod RW {
12836 #[doc = "Pull/Keeper Disabled"]
12837 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
12838 #[doc = "Pull/Keeper Enabled"]
12839 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
12840 }
12841 }
12842 #[doc = "Pull / Keep Select Field"]
12843 pub mod PUE {
12844 pub const offset: u32 = 13;
12845 pub const mask: u32 = 0x01 << offset;
12846 pub mod R {}
12847 pub mod W {}
12848 pub mod RW {
12849 #[doc = "Keeper"]
12850 pub const PUE_0_KEEPER: u32 = 0;
12851 #[doc = "Pull"]
12852 pub const PUE_1_PULL: u32 = 0x01;
12853 }
12854 }
12855 #[doc = "Pull Up / Down Config. Field"]
12856 pub mod PUS {
12857 pub const offset: u32 = 14;
12858 pub const mask: u32 = 0x03 << offset;
12859 pub mod R {}
12860 pub mod W {}
12861 pub mod RW {
12862 #[doc = "100K Ohm Pull Down"]
12863 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
12864 #[doc = "47K Ohm Pull Up"]
12865 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
12866 #[doc = "100K Ohm Pull Up"]
12867 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
12868 #[doc = "22K Ohm Pull Up"]
12869 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
12870 }
12871 }
12872 #[doc = "Hyst. Enable Field"]
12873 pub mod HYS {
12874 pub const offset: u32 = 16;
12875 pub const mask: u32 = 0x01 << offset;
12876 pub mod R {}
12877 pub mod W {}
12878 pub mod RW {
12879 #[doc = "Hysteresis Disabled"]
12880 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
12881 #[doc = "Hysteresis Enabled"]
12882 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
12883 }
12884 }
12885}
12886#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_12 SW PAD Control Register"]
12887pub mod SW_PAD_CTL_PAD_GPIO_AD_B0_12 {
12888 #[doc = "Slew Rate Field"]
12889 pub mod SRE {
12890 pub const offset: u32 = 0;
12891 pub const mask: u32 = 0x01 << offset;
12892 pub mod R {}
12893 pub mod W {}
12894 pub mod RW {
12895 #[doc = "Slow Slew Rate"]
12896 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
12897 #[doc = "Fast Slew Rate"]
12898 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
12899 }
12900 }
12901 #[doc = "Drive Strength Field"]
12902 pub mod DSE {
12903 pub const offset: u32 = 3;
12904 pub const mask: u32 = 0x07 << offset;
12905 pub mod R {}
12906 pub mod W {}
12907 pub mod RW {
12908 #[doc = "output driver disabled;"]
12909 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
12910 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
12911 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
12912 #[doc = "R0/2"]
12913 pub const DSE_2_R0_2: u32 = 0x02;
12914 #[doc = "R0/3"]
12915 pub const DSE_3_R0_3: u32 = 0x03;
12916 #[doc = "R0/4"]
12917 pub const DSE_4_R0_4: u32 = 0x04;
12918 #[doc = "R0/5"]
12919 pub const DSE_5_R0_5: u32 = 0x05;
12920 #[doc = "R0/6"]
12921 pub const DSE_6_R0_6: u32 = 0x06;
12922 #[doc = "R0/7"]
12923 pub const DSE_7_R0_7: u32 = 0x07;
12924 }
12925 }
12926 #[doc = "Speed Field"]
12927 pub mod SPEED {
12928 pub const offset: u32 = 6;
12929 pub const mask: u32 = 0x03 << offset;
12930 pub mod R {}
12931 pub mod W {}
12932 pub mod RW {
12933 #[doc = "low(50MHz)"]
12934 pub const SPEED_0_LOW_50MHZ: u32 = 0;
12935 #[doc = "medium(100MHz)"]
12936 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
12937 #[doc = "medium(100MHz)"]
12938 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
12939 #[doc = "max(200MHz)"]
12940 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
12941 }
12942 }
12943 #[doc = "Open Drain Enable Field"]
12944 pub mod ODE {
12945 pub const offset: u32 = 11;
12946 pub const mask: u32 = 0x01 << offset;
12947 pub mod R {}
12948 pub mod W {}
12949 pub mod RW {
12950 #[doc = "Open Drain Disabled"]
12951 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
12952 #[doc = "Open Drain Enabled"]
12953 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
12954 }
12955 }
12956 #[doc = "Pull / Keep Enable Field"]
12957 pub mod PKE {
12958 pub const offset: u32 = 12;
12959 pub const mask: u32 = 0x01 << offset;
12960 pub mod R {}
12961 pub mod W {}
12962 pub mod RW {
12963 #[doc = "Pull/Keeper Disabled"]
12964 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
12965 #[doc = "Pull/Keeper Enabled"]
12966 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
12967 }
12968 }
12969 #[doc = "Pull / Keep Select Field"]
12970 pub mod PUE {
12971 pub const offset: u32 = 13;
12972 pub const mask: u32 = 0x01 << offset;
12973 pub mod R {}
12974 pub mod W {}
12975 pub mod RW {
12976 #[doc = "Keeper"]
12977 pub const PUE_0_KEEPER: u32 = 0;
12978 #[doc = "Pull"]
12979 pub const PUE_1_PULL: u32 = 0x01;
12980 }
12981 }
12982 #[doc = "Pull Up / Down Config. Field"]
12983 pub mod PUS {
12984 pub const offset: u32 = 14;
12985 pub const mask: u32 = 0x03 << offset;
12986 pub mod R {}
12987 pub mod W {}
12988 pub mod RW {
12989 #[doc = "100K Ohm Pull Down"]
12990 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
12991 #[doc = "47K Ohm Pull Up"]
12992 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
12993 #[doc = "100K Ohm Pull Up"]
12994 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
12995 #[doc = "22K Ohm Pull Up"]
12996 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
12997 }
12998 }
12999 #[doc = "Hyst. Enable Field"]
13000 pub mod HYS {
13001 pub const offset: u32 = 16;
13002 pub const mask: u32 = 0x01 << offset;
13003 pub mod R {}
13004 pub mod W {}
13005 pub mod RW {
13006 #[doc = "Hysteresis Disabled"]
13007 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
13008 #[doc = "Hysteresis Enabled"]
13009 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
13010 }
13011 }
13012}
13013#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_13 SW PAD Control Register"]
13014pub mod SW_PAD_CTL_PAD_GPIO_AD_B0_13 {
13015 #[doc = "Slew Rate Field"]
13016 pub mod SRE {
13017 pub const offset: u32 = 0;
13018 pub const mask: u32 = 0x01 << offset;
13019 pub mod R {}
13020 pub mod W {}
13021 pub mod RW {
13022 #[doc = "Slow Slew Rate"]
13023 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
13024 #[doc = "Fast Slew Rate"]
13025 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
13026 }
13027 }
13028 #[doc = "Drive Strength Field"]
13029 pub mod DSE {
13030 pub const offset: u32 = 3;
13031 pub const mask: u32 = 0x07 << offset;
13032 pub mod R {}
13033 pub mod W {}
13034 pub mod RW {
13035 #[doc = "output driver disabled;"]
13036 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
13037 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
13038 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
13039 #[doc = "R0/2"]
13040 pub const DSE_2_R0_2: u32 = 0x02;
13041 #[doc = "R0/3"]
13042 pub const DSE_3_R0_3: u32 = 0x03;
13043 #[doc = "R0/4"]
13044 pub const DSE_4_R0_4: u32 = 0x04;
13045 #[doc = "R0/5"]
13046 pub const DSE_5_R0_5: u32 = 0x05;
13047 #[doc = "R0/6"]
13048 pub const DSE_6_R0_6: u32 = 0x06;
13049 #[doc = "R0/7"]
13050 pub const DSE_7_R0_7: u32 = 0x07;
13051 }
13052 }
13053 #[doc = "Speed Field"]
13054 pub mod SPEED {
13055 pub const offset: u32 = 6;
13056 pub const mask: u32 = 0x03 << offset;
13057 pub mod R {}
13058 pub mod W {}
13059 pub mod RW {
13060 #[doc = "low(50MHz)"]
13061 pub const SPEED_0_LOW_50MHZ: u32 = 0;
13062 #[doc = "medium(100MHz)"]
13063 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
13064 #[doc = "medium(100MHz)"]
13065 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
13066 #[doc = "max(200MHz)"]
13067 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
13068 }
13069 }
13070 #[doc = "Open Drain Enable Field"]
13071 pub mod ODE {
13072 pub const offset: u32 = 11;
13073 pub const mask: u32 = 0x01 << offset;
13074 pub mod R {}
13075 pub mod W {}
13076 pub mod RW {
13077 #[doc = "Open Drain Disabled"]
13078 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
13079 #[doc = "Open Drain Enabled"]
13080 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
13081 }
13082 }
13083 #[doc = "Pull / Keep Enable Field"]
13084 pub mod PKE {
13085 pub const offset: u32 = 12;
13086 pub const mask: u32 = 0x01 << offset;
13087 pub mod R {}
13088 pub mod W {}
13089 pub mod RW {
13090 #[doc = "Pull/Keeper Disabled"]
13091 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
13092 #[doc = "Pull/Keeper Enabled"]
13093 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
13094 }
13095 }
13096 #[doc = "Pull / Keep Select Field"]
13097 pub mod PUE {
13098 pub const offset: u32 = 13;
13099 pub const mask: u32 = 0x01 << offset;
13100 pub mod R {}
13101 pub mod W {}
13102 pub mod RW {
13103 #[doc = "Keeper"]
13104 pub const PUE_0_KEEPER: u32 = 0;
13105 #[doc = "Pull"]
13106 pub const PUE_1_PULL: u32 = 0x01;
13107 }
13108 }
13109 #[doc = "Pull Up / Down Config. Field"]
13110 pub mod PUS {
13111 pub const offset: u32 = 14;
13112 pub const mask: u32 = 0x03 << offset;
13113 pub mod R {}
13114 pub mod W {}
13115 pub mod RW {
13116 #[doc = "100K Ohm Pull Down"]
13117 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
13118 #[doc = "47K Ohm Pull Up"]
13119 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
13120 #[doc = "100K Ohm Pull Up"]
13121 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
13122 #[doc = "22K Ohm Pull Up"]
13123 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
13124 }
13125 }
13126 #[doc = "Hyst. Enable Field"]
13127 pub mod HYS {
13128 pub const offset: u32 = 16;
13129 pub const mask: u32 = 0x01 << offset;
13130 pub mod R {}
13131 pub mod W {}
13132 pub mod RW {
13133 #[doc = "Hysteresis Disabled"]
13134 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
13135 #[doc = "Hysteresis Enabled"]
13136 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
13137 }
13138 }
13139}
13140#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_14 SW PAD Control Register"]
13141pub mod SW_PAD_CTL_PAD_GPIO_AD_B0_14 {
13142 #[doc = "Slew Rate Field"]
13143 pub mod SRE {
13144 pub const offset: u32 = 0;
13145 pub const mask: u32 = 0x01 << offset;
13146 pub mod R {}
13147 pub mod W {}
13148 pub mod RW {
13149 #[doc = "Slow Slew Rate"]
13150 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
13151 #[doc = "Fast Slew Rate"]
13152 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
13153 }
13154 }
13155 #[doc = "Drive Strength Field"]
13156 pub mod DSE {
13157 pub const offset: u32 = 3;
13158 pub const mask: u32 = 0x07 << offset;
13159 pub mod R {}
13160 pub mod W {}
13161 pub mod RW {
13162 #[doc = "output driver disabled;"]
13163 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
13164 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
13165 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
13166 #[doc = "R0/2"]
13167 pub const DSE_2_R0_2: u32 = 0x02;
13168 #[doc = "R0/3"]
13169 pub const DSE_3_R0_3: u32 = 0x03;
13170 #[doc = "R0/4"]
13171 pub const DSE_4_R0_4: u32 = 0x04;
13172 #[doc = "R0/5"]
13173 pub const DSE_5_R0_5: u32 = 0x05;
13174 #[doc = "R0/6"]
13175 pub const DSE_6_R0_6: u32 = 0x06;
13176 #[doc = "R0/7"]
13177 pub const DSE_7_R0_7: u32 = 0x07;
13178 }
13179 }
13180 #[doc = "Speed Field"]
13181 pub mod SPEED {
13182 pub const offset: u32 = 6;
13183 pub const mask: u32 = 0x03 << offset;
13184 pub mod R {}
13185 pub mod W {}
13186 pub mod RW {
13187 #[doc = "low(50MHz)"]
13188 pub const SPEED_0_LOW_50MHZ: u32 = 0;
13189 #[doc = "medium(100MHz)"]
13190 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
13191 #[doc = "medium(100MHz)"]
13192 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
13193 #[doc = "max(200MHz)"]
13194 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
13195 }
13196 }
13197 #[doc = "Open Drain Enable Field"]
13198 pub mod ODE {
13199 pub const offset: u32 = 11;
13200 pub const mask: u32 = 0x01 << offset;
13201 pub mod R {}
13202 pub mod W {}
13203 pub mod RW {
13204 #[doc = "Open Drain Disabled"]
13205 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
13206 #[doc = "Open Drain Enabled"]
13207 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
13208 }
13209 }
13210 #[doc = "Pull / Keep Enable Field"]
13211 pub mod PKE {
13212 pub const offset: u32 = 12;
13213 pub const mask: u32 = 0x01 << offset;
13214 pub mod R {}
13215 pub mod W {}
13216 pub mod RW {
13217 #[doc = "Pull/Keeper Disabled"]
13218 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
13219 #[doc = "Pull/Keeper Enabled"]
13220 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
13221 }
13222 }
13223 #[doc = "Pull / Keep Select Field"]
13224 pub mod PUE {
13225 pub const offset: u32 = 13;
13226 pub const mask: u32 = 0x01 << offset;
13227 pub mod R {}
13228 pub mod W {}
13229 pub mod RW {
13230 #[doc = "Keeper"]
13231 pub const PUE_0_KEEPER: u32 = 0;
13232 #[doc = "Pull"]
13233 pub const PUE_1_PULL: u32 = 0x01;
13234 }
13235 }
13236 #[doc = "Pull Up / Down Config. Field"]
13237 pub mod PUS {
13238 pub const offset: u32 = 14;
13239 pub const mask: u32 = 0x03 << offset;
13240 pub mod R {}
13241 pub mod W {}
13242 pub mod RW {
13243 #[doc = "100K Ohm Pull Down"]
13244 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
13245 #[doc = "47K Ohm Pull Up"]
13246 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
13247 #[doc = "100K Ohm Pull Up"]
13248 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
13249 #[doc = "22K Ohm Pull Up"]
13250 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
13251 }
13252 }
13253 #[doc = "Hyst. Enable Field"]
13254 pub mod HYS {
13255 pub const offset: u32 = 16;
13256 pub const mask: u32 = 0x01 << offset;
13257 pub mod R {}
13258 pub mod W {}
13259 pub mod RW {
13260 #[doc = "Hysteresis Disabled"]
13261 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
13262 #[doc = "Hysteresis Enabled"]
13263 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
13264 }
13265 }
13266}
13267#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B0_15 SW PAD Control Register"]
13268pub mod SW_PAD_CTL_PAD_GPIO_AD_B0_15 {
13269 #[doc = "Slew Rate Field"]
13270 pub mod SRE {
13271 pub const offset: u32 = 0;
13272 pub const mask: u32 = 0x01 << offset;
13273 pub mod R {}
13274 pub mod W {}
13275 pub mod RW {
13276 #[doc = "Slow Slew Rate"]
13277 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
13278 #[doc = "Fast Slew Rate"]
13279 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
13280 }
13281 }
13282 #[doc = "Drive Strength Field"]
13283 pub mod DSE {
13284 pub const offset: u32 = 3;
13285 pub const mask: u32 = 0x07 << offset;
13286 pub mod R {}
13287 pub mod W {}
13288 pub mod RW {
13289 #[doc = "output driver disabled;"]
13290 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
13291 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
13292 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
13293 #[doc = "R0/2"]
13294 pub const DSE_2_R0_2: u32 = 0x02;
13295 #[doc = "R0/3"]
13296 pub const DSE_3_R0_3: u32 = 0x03;
13297 #[doc = "R0/4"]
13298 pub const DSE_4_R0_4: u32 = 0x04;
13299 #[doc = "R0/5"]
13300 pub const DSE_5_R0_5: u32 = 0x05;
13301 #[doc = "R0/6"]
13302 pub const DSE_6_R0_6: u32 = 0x06;
13303 #[doc = "R0/7"]
13304 pub const DSE_7_R0_7: u32 = 0x07;
13305 }
13306 }
13307 #[doc = "Speed Field"]
13308 pub mod SPEED {
13309 pub const offset: u32 = 6;
13310 pub const mask: u32 = 0x03 << offset;
13311 pub mod R {}
13312 pub mod W {}
13313 pub mod RW {
13314 #[doc = "low(50MHz)"]
13315 pub const SPEED_0_LOW_50MHZ: u32 = 0;
13316 #[doc = "medium(100MHz)"]
13317 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
13318 #[doc = "medium(100MHz)"]
13319 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
13320 #[doc = "max(200MHz)"]
13321 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
13322 }
13323 }
13324 #[doc = "Open Drain Enable Field"]
13325 pub mod ODE {
13326 pub const offset: u32 = 11;
13327 pub const mask: u32 = 0x01 << offset;
13328 pub mod R {}
13329 pub mod W {}
13330 pub mod RW {
13331 #[doc = "Open Drain Disabled"]
13332 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
13333 #[doc = "Open Drain Enabled"]
13334 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
13335 }
13336 }
13337 #[doc = "Pull / Keep Enable Field"]
13338 pub mod PKE {
13339 pub const offset: u32 = 12;
13340 pub const mask: u32 = 0x01 << offset;
13341 pub mod R {}
13342 pub mod W {}
13343 pub mod RW {
13344 #[doc = "Pull/Keeper Disabled"]
13345 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
13346 #[doc = "Pull/Keeper Enabled"]
13347 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
13348 }
13349 }
13350 #[doc = "Pull / Keep Select Field"]
13351 pub mod PUE {
13352 pub const offset: u32 = 13;
13353 pub const mask: u32 = 0x01 << offset;
13354 pub mod R {}
13355 pub mod W {}
13356 pub mod RW {
13357 #[doc = "Keeper"]
13358 pub const PUE_0_KEEPER: u32 = 0;
13359 #[doc = "Pull"]
13360 pub const PUE_1_PULL: u32 = 0x01;
13361 }
13362 }
13363 #[doc = "Pull Up / Down Config. Field"]
13364 pub mod PUS {
13365 pub const offset: u32 = 14;
13366 pub const mask: u32 = 0x03 << offset;
13367 pub mod R {}
13368 pub mod W {}
13369 pub mod RW {
13370 #[doc = "100K Ohm Pull Down"]
13371 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
13372 #[doc = "47K Ohm Pull Up"]
13373 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
13374 #[doc = "100K Ohm Pull Up"]
13375 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
13376 #[doc = "22K Ohm Pull Up"]
13377 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
13378 }
13379 }
13380 #[doc = "Hyst. Enable Field"]
13381 pub mod HYS {
13382 pub const offset: u32 = 16;
13383 pub const mask: u32 = 0x01 << offset;
13384 pub mod R {}
13385 pub mod W {}
13386 pub mod RW {
13387 #[doc = "Hysteresis Disabled"]
13388 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
13389 #[doc = "Hysteresis Enabled"]
13390 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
13391 }
13392 }
13393}
13394#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_00 SW PAD Control Register"]
13395pub mod SW_PAD_CTL_PAD_GPIO_AD_B1_00 {
13396 #[doc = "Slew Rate Field"]
13397 pub mod SRE {
13398 pub const offset: u32 = 0;
13399 pub const mask: u32 = 0x01 << offset;
13400 pub mod R {}
13401 pub mod W {}
13402 pub mod RW {
13403 #[doc = "Slow Slew Rate"]
13404 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
13405 #[doc = "Fast Slew Rate"]
13406 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
13407 }
13408 }
13409 #[doc = "Drive Strength Field"]
13410 pub mod DSE {
13411 pub const offset: u32 = 3;
13412 pub const mask: u32 = 0x07 << offset;
13413 pub mod R {}
13414 pub mod W {}
13415 pub mod RW {
13416 #[doc = "output driver disabled;"]
13417 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
13418 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
13419 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
13420 #[doc = "R0/2"]
13421 pub const DSE_2_R0_2: u32 = 0x02;
13422 #[doc = "R0/3"]
13423 pub const DSE_3_R0_3: u32 = 0x03;
13424 #[doc = "R0/4"]
13425 pub const DSE_4_R0_4: u32 = 0x04;
13426 #[doc = "R0/5"]
13427 pub const DSE_5_R0_5: u32 = 0x05;
13428 #[doc = "R0/6"]
13429 pub const DSE_6_R0_6: u32 = 0x06;
13430 #[doc = "R0/7"]
13431 pub const DSE_7_R0_7: u32 = 0x07;
13432 }
13433 }
13434 #[doc = "Speed Field"]
13435 pub mod SPEED {
13436 pub const offset: u32 = 6;
13437 pub const mask: u32 = 0x03 << offset;
13438 pub mod R {}
13439 pub mod W {}
13440 pub mod RW {
13441 #[doc = "low(50MHz)"]
13442 pub const SPEED_0_LOW_50MHZ: u32 = 0;
13443 #[doc = "medium(100MHz)"]
13444 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
13445 #[doc = "medium(100MHz)"]
13446 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
13447 #[doc = "max(200MHz)"]
13448 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
13449 }
13450 }
13451 #[doc = "Open Drain Enable Field"]
13452 pub mod ODE {
13453 pub const offset: u32 = 11;
13454 pub const mask: u32 = 0x01 << offset;
13455 pub mod R {}
13456 pub mod W {}
13457 pub mod RW {
13458 #[doc = "Open Drain Disabled"]
13459 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
13460 #[doc = "Open Drain Enabled"]
13461 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
13462 }
13463 }
13464 #[doc = "Pull / Keep Enable Field"]
13465 pub mod PKE {
13466 pub const offset: u32 = 12;
13467 pub const mask: u32 = 0x01 << offset;
13468 pub mod R {}
13469 pub mod W {}
13470 pub mod RW {
13471 #[doc = "Pull/Keeper Disabled"]
13472 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
13473 #[doc = "Pull/Keeper Enabled"]
13474 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
13475 }
13476 }
13477 #[doc = "Pull / Keep Select Field"]
13478 pub mod PUE {
13479 pub const offset: u32 = 13;
13480 pub const mask: u32 = 0x01 << offset;
13481 pub mod R {}
13482 pub mod W {}
13483 pub mod RW {
13484 #[doc = "Keeper"]
13485 pub const PUE_0_KEEPER: u32 = 0;
13486 #[doc = "Pull"]
13487 pub const PUE_1_PULL: u32 = 0x01;
13488 }
13489 }
13490 #[doc = "Pull Up / Down Config. Field"]
13491 pub mod PUS {
13492 pub const offset: u32 = 14;
13493 pub const mask: u32 = 0x03 << offset;
13494 pub mod R {}
13495 pub mod W {}
13496 pub mod RW {
13497 #[doc = "100K Ohm Pull Down"]
13498 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
13499 #[doc = "47K Ohm Pull Up"]
13500 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
13501 #[doc = "100K Ohm Pull Up"]
13502 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
13503 #[doc = "22K Ohm Pull Up"]
13504 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
13505 }
13506 }
13507 #[doc = "Hyst. Enable Field"]
13508 pub mod HYS {
13509 pub const offset: u32 = 16;
13510 pub const mask: u32 = 0x01 << offset;
13511 pub mod R {}
13512 pub mod W {}
13513 pub mod RW {
13514 #[doc = "Hysteresis Disabled"]
13515 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
13516 #[doc = "Hysteresis Enabled"]
13517 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
13518 }
13519 }
13520}
13521#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_01 SW PAD Control Register"]
13522pub mod SW_PAD_CTL_PAD_GPIO_AD_B1_01 {
13523 #[doc = "Slew Rate Field"]
13524 pub mod SRE {
13525 pub const offset: u32 = 0;
13526 pub const mask: u32 = 0x01 << offset;
13527 pub mod R {}
13528 pub mod W {}
13529 pub mod RW {
13530 #[doc = "Slow Slew Rate"]
13531 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
13532 #[doc = "Fast Slew Rate"]
13533 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
13534 }
13535 }
13536 #[doc = "Drive Strength Field"]
13537 pub mod DSE {
13538 pub const offset: u32 = 3;
13539 pub const mask: u32 = 0x07 << offset;
13540 pub mod R {}
13541 pub mod W {}
13542 pub mod RW {
13543 #[doc = "output driver disabled;"]
13544 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
13545 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
13546 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
13547 #[doc = "R0/2"]
13548 pub const DSE_2_R0_2: u32 = 0x02;
13549 #[doc = "R0/3"]
13550 pub const DSE_3_R0_3: u32 = 0x03;
13551 #[doc = "R0/4"]
13552 pub const DSE_4_R0_4: u32 = 0x04;
13553 #[doc = "R0/5"]
13554 pub const DSE_5_R0_5: u32 = 0x05;
13555 #[doc = "R0/6"]
13556 pub const DSE_6_R0_6: u32 = 0x06;
13557 #[doc = "R0/7"]
13558 pub const DSE_7_R0_7: u32 = 0x07;
13559 }
13560 }
13561 #[doc = "Speed Field"]
13562 pub mod SPEED {
13563 pub const offset: u32 = 6;
13564 pub const mask: u32 = 0x03 << offset;
13565 pub mod R {}
13566 pub mod W {}
13567 pub mod RW {
13568 #[doc = "low(50MHz)"]
13569 pub const SPEED_0_LOW_50MHZ: u32 = 0;
13570 #[doc = "medium(100MHz)"]
13571 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
13572 #[doc = "medium(100MHz)"]
13573 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
13574 #[doc = "max(200MHz)"]
13575 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
13576 }
13577 }
13578 #[doc = "Open Drain Enable Field"]
13579 pub mod ODE {
13580 pub const offset: u32 = 11;
13581 pub const mask: u32 = 0x01 << offset;
13582 pub mod R {}
13583 pub mod W {}
13584 pub mod RW {
13585 #[doc = "Open Drain Disabled"]
13586 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
13587 #[doc = "Open Drain Enabled"]
13588 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
13589 }
13590 }
13591 #[doc = "Pull / Keep Enable Field"]
13592 pub mod PKE {
13593 pub const offset: u32 = 12;
13594 pub const mask: u32 = 0x01 << offset;
13595 pub mod R {}
13596 pub mod W {}
13597 pub mod RW {
13598 #[doc = "Pull/Keeper Disabled"]
13599 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
13600 #[doc = "Pull/Keeper Enabled"]
13601 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
13602 }
13603 }
13604 #[doc = "Pull / Keep Select Field"]
13605 pub mod PUE {
13606 pub const offset: u32 = 13;
13607 pub const mask: u32 = 0x01 << offset;
13608 pub mod R {}
13609 pub mod W {}
13610 pub mod RW {
13611 #[doc = "Keeper"]
13612 pub const PUE_0_KEEPER: u32 = 0;
13613 #[doc = "Pull"]
13614 pub const PUE_1_PULL: u32 = 0x01;
13615 }
13616 }
13617 #[doc = "Pull Up / Down Config. Field"]
13618 pub mod PUS {
13619 pub const offset: u32 = 14;
13620 pub const mask: u32 = 0x03 << offset;
13621 pub mod R {}
13622 pub mod W {}
13623 pub mod RW {
13624 #[doc = "100K Ohm Pull Down"]
13625 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
13626 #[doc = "47K Ohm Pull Up"]
13627 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
13628 #[doc = "100K Ohm Pull Up"]
13629 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
13630 #[doc = "22K Ohm Pull Up"]
13631 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
13632 }
13633 }
13634 #[doc = "Hyst. Enable Field"]
13635 pub mod HYS {
13636 pub const offset: u32 = 16;
13637 pub const mask: u32 = 0x01 << offset;
13638 pub mod R {}
13639 pub mod W {}
13640 pub mod RW {
13641 #[doc = "Hysteresis Disabled"]
13642 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
13643 #[doc = "Hysteresis Enabled"]
13644 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
13645 }
13646 }
13647}
13648#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_02 SW PAD Control Register"]
13649pub mod SW_PAD_CTL_PAD_GPIO_AD_B1_02 {
13650 #[doc = "Slew Rate Field"]
13651 pub mod SRE {
13652 pub const offset: u32 = 0;
13653 pub const mask: u32 = 0x01 << offset;
13654 pub mod R {}
13655 pub mod W {}
13656 pub mod RW {
13657 #[doc = "Slow Slew Rate"]
13658 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
13659 #[doc = "Fast Slew Rate"]
13660 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
13661 }
13662 }
13663 #[doc = "Drive Strength Field"]
13664 pub mod DSE {
13665 pub const offset: u32 = 3;
13666 pub const mask: u32 = 0x07 << offset;
13667 pub mod R {}
13668 pub mod W {}
13669 pub mod RW {
13670 #[doc = "output driver disabled;"]
13671 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
13672 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
13673 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
13674 #[doc = "R0/2"]
13675 pub const DSE_2_R0_2: u32 = 0x02;
13676 #[doc = "R0/3"]
13677 pub const DSE_3_R0_3: u32 = 0x03;
13678 #[doc = "R0/4"]
13679 pub const DSE_4_R0_4: u32 = 0x04;
13680 #[doc = "R0/5"]
13681 pub const DSE_5_R0_5: u32 = 0x05;
13682 #[doc = "R0/6"]
13683 pub const DSE_6_R0_6: u32 = 0x06;
13684 #[doc = "R0/7"]
13685 pub const DSE_7_R0_7: u32 = 0x07;
13686 }
13687 }
13688 #[doc = "Speed Field"]
13689 pub mod SPEED {
13690 pub const offset: u32 = 6;
13691 pub const mask: u32 = 0x03 << offset;
13692 pub mod R {}
13693 pub mod W {}
13694 pub mod RW {
13695 #[doc = "low(50MHz)"]
13696 pub const SPEED_0_LOW_50MHZ: u32 = 0;
13697 #[doc = "medium(100MHz)"]
13698 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
13699 #[doc = "medium(100MHz)"]
13700 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
13701 #[doc = "max(200MHz)"]
13702 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
13703 }
13704 }
13705 #[doc = "Open Drain Enable Field"]
13706 pub mod ODE {
13707 pub const offset: u32 = 11;
13708 pub const mask: u32 = 0x01 << offset;
13709 pub mod R {}
13710 pub mod W {}
13711 pub mod RW {
13712 #[doc = "Open Drain Disabled"]
13713 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
13714 #[doc = "Open Drain Enabled"]
13715 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
13716 }
13717 }
13718 #[doc = "Pull / Keep Enable Field"]
13719 pub mod PKE {
13720 pub const offset: u32 = 12;
13721 pub const mask: u32 = 0x01 << offset;
13722 pub mod R {}
13723 pub mod W {}
13724 pub mod RW {
13725 #[doc = "Pull/Keeper Disabled"]
13726 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
13727 #[doc = "Pull/Keeper Enabled"]
13728 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
13729 }
13730 }
13731 #[doc = "Pull / Keep Select Field"]
13732 pub mod PUE {
13733 pub const offset: u32 = 13;
13734 pub const mask: u32 = 0x01 << offset;
13735 pub mod R {}
13736 pub mod W {}
13737 pub mod RW {
13738 #[doc = "Keeper"]
13739 pub const PUE_0_KEEPER: u32 = 0;
13740 #[doc = "Pull"]
13741 pub const PUE_1_PULL: u32 = 0x01;
13742 }
13743 }
13744 #[doc = "Pull Up / Down Config. Field"]
13745 pub mod PUS {
13746 pub const offset: u32 = 14;
13747 pub const mask: u32 = 0x03 << offset;
13748 pub mod R {}
13749 pub mod W {}
13750 pub mod RW {
13751 #[doc = "100K Ohm Pull Down"]
13752 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
13753 #[doc = "47K Ohm Pull Up"]
13754 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
13755 #[doc = "100K Ohm Pull Up"]
13756 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
13757 #[doc = "22K Ohm Pull Up"]
13758 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
13759 }
13760 }
13761 #[doc = "Hyst. Enable Field"]
13762 pub mod HYS {
13763 pub const offset: u32 = 16;
13764 pub const mask: u32 = 0x01 << offset;
13765 pub mod R {}
13766 pub mod W {}
13767 pub mod RW {
13768 #[doc = "Hysteresis Disabled"]
13769 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
13770 #[doc = "Hysteresis Enabled"]
13771 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
13772 }
13773 }
13774}
13775#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_03 SW PAD Control Register"]
13776pub mod SW_PAD_CTL_PAD_GPIO_AD_B1_03 {
13777 #[doc = "Slew Rate Field"]
13778 pub mod SRE {
13779 pub const offset: u32 = 0;
13780 pub const mask: u32 = 0x01 << offset;
13781 pub mod R {}
13782 pub mod W {}
13783 pub mod RW {
13784 #[doc = "Slow Slew Rate"]
13785 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
13786 #[doc = "Fast Slew Rate"]
13787 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
13788 }
13789 }
13790 #[doc = "Drive Strength Field"]
13791 pub mod DSE {
13792 pub const offset: u32 = 3;
13793 pub const mask: u32 = 0x07 << offset;
13794 pub mod R {}
13795 pub mod W {}
13796 pub mod RW {
13797 #[doc = "output driver disabled;"]
13798 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
13799 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
13800 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
13801 #[doc = "R0/2"]
13802 pub const DSE_2_R0_2: u32 = 0x02;
13803 #[doc = "R0/3"]
13804 pub const DSE_3_R0_3: u32 = 0x03;
13805 #[doc = "R0/4"]
13806 pub const DSE_4_R0_4: u32 = 0x04;
13807 #[doc = "R0/5"]
13808 pub const DSE_5_R0_5: u32 = 0x05;
13809 #[doc = "R0/6"]
13810 pub const DSE_6_R0_6: u32 = 0x06;
13811 #[doc = "R0/7"]
13812 pub const DSE_7_R0_7: u32 = 0x07;
13813 }
13814 }
13815 #[doc = "Speed Field"]
13816 pub mod SPEED {
13817 pub const offset: u32 = 6;
13818 pub const mask: u32 = 0x03 << offset;
13819 pub mod R {}
13820 pub mod W {}
13821 pub mod RW {
13822 #[doc = "low(50MHz)"]
13823 pub const SPEED_0_LOW_50MHZ: u32 = 0;
13824 #[doc = "medium(100MHz)"]
13825 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
13826 #[doc = "medium(100MHz)"]
13827 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
13828 #[doc = "max(200MHz)"]
13829 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
13830 }
13831 }
13832 #[doc = "Open Drain Enable Field"]
13833 pub mod ODE {
13834 pub const offset: u32 = 11;
13835 pub const mask: u32 = 0x01 << offset;
13836 pub mod R {}
13837 pub mod W {}
13838 pub mod RW {
13839 #[doc = "Open Drain Disabled"]
13840 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
13841 #[doc = "Open Drain Enabled"]
13842 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
13843 }
13844 }
13845 #[doc = "Pull / Keep Enable Field"]
13846 pub mod PKE {
13847 pub const offset: u32 = 12;
13848 pub const mask: u32 = 0x01 << offset;
13849 pub mod R {}
13850 pub mod W {}
13851 pub mod RW {
13852 #[doc = "Pull/Keeper Disabled"]
13853 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
13854 #[doc = "Pull/Keeper Enabled"]
13855 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
13856 }
13857 }
13858 #[doc = "Pull / Keep Select Field"]
13859 pub mod PUE {
13860 pub const offset: u32 = 13;
13861 pub const mask: u32 = 0x01 << offset;
13862 pub mod R {}
13863 pub mod W {}
13864 pub mod RW {
13865 #[doc = "Keeper"]
13866 pub const PUE_0_KEEPER: u32 = 0;
13867 #[doc = "Pull"]
13868 pub const PUE_1_PULL: u32 = 0x01;
13869 }
13870 }
13871 #[doc = "Pull Up / Down Config. Field"]
13872 pub mod PUS {
13873 pub const offset: u32 = 14;
13874 pub const mask: u32 = 0x03 << offset;
13875 pub mod R {}
13876 pub mod W {}
13877 pub mod RW {
13878 #[doc = "100K Ohm Pull Down"]
13879 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
13880 #[doc = "47K Ohm Pull Up"]
13881 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
13882 #[doc = "100K Ohm Pull Up"]
13883 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
13884 #[doc = "22K Ohm Pull Up"]
13885 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
13886 }
13887 }
13888 #[doc = "Hyst. Enable Field"]
13889 pub mod HYS {
13890 pub const offset: u32 = 16;
13891 pub const mask: u32 = 0x01 << offset;
13892 pub mod R {}
13893 pub mod W {}
13894 pub mod RW {
13895 #[doc = "Hysteresis Disabled"]
13896 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
13897 #[doc = "Hysteresis Enabled"]
13898 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
13899 }
13900 }
13901}
13902#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_04 SW PAD Control Register"]
13903pub mod SW_PAD_CTL_PAD_GPIO_AD_B1_04 {
13904 #[doc = "Slew Rate Field"]
13905 pub mod SRE {
13906 pub const offset: u32 = 0;
13907 pub const mask: u32 = 0x01 << offset;
13908 pub mod R {}
13909 pub mod W {}
13910 pub mod RW {
13911 #[doc = "Slow Slew Rate"]
13912 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
13913 #[doc = "Fast Slew Rate"]
13914 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
13915 }
13916 }
13917 #[doc = "Drive Strength Field"]
13918 pub mod DSE {
13919 pub const offset: u32 = 3;
13920 pub const mask: u32 = 0x07 << offset;
13921 pub mod R {}
13922 pub mod W {}
13923 pub mod RW {
13924 #[doc = "output driver disabled;"]
13925 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
13926 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
13927 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
13928 #[doc = "R0/2"]
13929 pub const DSE_2_R0_2: u32 = 0x02;
13930 #[doc = "R0/3"]
13931 pub const DSE_3_R0_3: u32 = 0x03;
13932 #[doc = "R0/4"]
13933 pub const DSE_4_R0_4: u32 = 0x04;
13934 #[doc = "R0/5"]
13935 pub const DSE_5_R0_5: u32 = 0x05;
13936 #[doc = "R0/6"]
13937 pub const DSE_6_R0_6: u32 = 0x06;
13938 #[doc = "R0/7"]
13939 pub const DSE_7_R0_7: u32 = 0x07;
13940 }
13941 }
13942 #[doc = "Speed Field"]
13943 pub mod SPEED {
13944 pub const offset: u32 = 6;
13945 pub const mask: u32 = 0x03 << offset;
13946 pub mod R {}
13947 pub mod W {}
13948 pub mod RW {
13949 #[doc = "low(50MHz)"]
13950 pub const SPEED_0_LOW_50MHZ: u32 = 0;
13951 #[doc = "medium(100MHz)"]
13952 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
13953 #[doc = "medium(100MHz)"]
13954 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
13955 #[doc = "max(200MHz)"]
13956 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
13957 }
13958 }
13959 #[doc = "Open Drain Enable Field"]
13960 pub mod ODE {
13961 pub const offset: u32 = 11;
13962 pub const mask: u32 = 0x01 << offset;
13963 pub mod R {}
13964 pub mod W {}
13965 pub mod RW {
13966 #[doc = "Open Drain Disabled"]
13967 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
13968 #[doc = "Open Drain Enabled"]
13969 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
13970 }
13971 }
13972 #[doc = "Pull / Keep Enable Field"]
13973 pub mod PKE {
13974 pub const offset: u32 = 12;
13975 pub const mask: u32 = 0x01 << offset;
13976 pub mod R {}
13977 pub mod W {}
13978 pub mod RW {
13979 #[doc = "Pull/Keeper Disabled"]
13980 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
13981 #[doc = "Pull/Keeper Enabled"]
13982 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
13983 }
13984 }
13985 #[doc = "Pull / Keep Select Field"]
13986 pub mod PUE {
13987 pub const offset: u32 = 13;
13988 pub const mask: u32 = 0x01 << offset;
13989 pub mod R {}
13990 pub mod W {}
13991 pub mod RW {
13992 #[doc = "Keeper"]
13993 pub const PUE_0_KEEPER: u32 = 0;
13994 #[doc = "Pull"]
13995 pub const PUE_1_PULL: u32 = 0x01;
13996 }
13997 }
13998 #[doc = "Pull Up / Down Config. Field"]
13999 pub mod PUS {
14000 pub const offset: u32 = 14;
14001 pub const mask: u32 = 0x03 << offset;
14002 pub mod R {}
14003 pub mod W {}
14004 pub mod RW {
14005 #[doc = "100K Ohm Pull Down"]
14006 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
14007 #[doc = "47K Ohm Pull Up"]
14008 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
14009 #[doc = "100K Ohm Pull Up"]
14010 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
14011 #[doc = "22K Ohm Pull Up"]
14012 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
14013 }
14014 }
14015 #[doc = "Hyst. Enable Field"]
14016 pub mod HYS {
14017 pub const offset: u32 = 16;
14018 pub const mask: u32 = 0x01 << offset;
14019 pub mod R {}
14020 pub mod W {}
14021 pub mod RW {
14022 #[doc = "Hysteresis Disabled"]
14023 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
14024 #[doc = "Hysteresis Enabled"]
14025 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
14026 }
14027 }
14028}
14029#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_05 SW PAD Control Register"]
14030pub mod SW_PAD_CTL_PAD_GPIO_AD_B1_05 {
14031 #[doc = "Slew Rate Field"]
14032 pub mod SRE {
14033 pub const offset: u32 = 0;
14034 pub const mask: u32 = 0x01 << offset;
14035 pub mod R {}
14036 pub mod W {}
14037 pub mod RW {
14038 #[doc = "Slow Slew Rate"]
14039 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
14040 #[doc = "Fast Slew Rate"]
14041 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
14042 }
14043 }
14044 #[doc = "Drive Strength Field"]
14045 pub mod DSE {
14046 pub const offset: u32 = 3;
14047 pub const mask: u32 = 0x07 << offset;
14048 pub mod R {}
14049 pub mod W {}
14050 pub mod RW {
14051 #[doc = "output driver disabled;"]
14052 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
14053 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
14054 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
14055 #[doc = "R0/2"]
14056 pub const DSE_2_R0_2: u32 = 0x02;
14057 #[doc = "R0/3"]
14058 pub const DSE_3_R0_3: u32 = 0x03;
14059 #[doc = "R0/4"]
14060 pub const DSE_4_R0_4: u32 = 0x04;
14061 #[doc = "R0/5"]
14062 pub const DSE_5_R0_5: u32 = 0x05;
14063 #[doc = "R0/6"]
14064 pub const DSE_6_R0_6: u32 = 0x06;
14065 #[doc = "R0/7"]
14066 pub const DSE_7_R0_7: u32 = 0x07;
14067 }
14068 }
14069 #[doc = "Speed Field"]
14070 pub mod SPEED {
14071 pub const offset: u32 = 6;
14072 pub const mask: u32 = 0x03 << offset;
14073 pub mod R {}
14074 pub mod W {}
14075 pub mod RW {
14076 #[doc = "low(50MHz)"]
14077 pub const SPEED_0_LOW_50MHZ: u32 = 0;
14078 #[doc = "medium(100MHz)"]
14079 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
14080 #[doc = "medium(100MHz)"]
14081 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
14082 #[doc = "max(200MHz)"]
14083 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
14084 }
14085 }
14086 #[doc = "Open Drain Enable Field"]
14087 pub mod ODE {
14088 pub const offset: u32 = 11;
14089 pub const mask: u32 = 0x01 << offset;
14090 pub mod R {}
14091 pub mod W {}
14092 pub mod RW {
14093 #[doc = "Open Drain Disabled"]
14094 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
14095 #[doc = "Open Drain Enabled"]
14096 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
14097 }
14098 }
14099 #[doc = "Pull / Keep Enable Field"]
14100 pub mod PKE {
14101 pub const offset: u32 = 12;
14102 pub const mask: u32 = 0x01 << offset;
14103 pub mod R {}
14104 pub mod W {}
14105 pub mod RW {
14106 #[doc = "Pull/Keeper Disabled"]
14107 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
14108 #[doc = "Pull/Keeper Enabled"]
14109 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
14110 }
14111 }
14112 #[doc = "Pull / Keep Select Field"]
14113 pub mod PUE {
14114 pub const offset: u32 = 13;
14115 pub const mask: u32 = 0x01 << offset;
14116 pub mod R {}
14117 pub mod W {}
14118 pub mod RW {
14119 #[doc = "Keeper"]
14120 pub const PUE_0_KEEPER: u32 = 0;
14121 #[doc = "Pull"]
14122 pub const PUE_1_PULL: u32 = 0x01;
14123 }
14124 }
14125 #[doc = "Pull Up / Down Config. Field"]
14126 pub mod PUS {
14127 pub const offset: u32 = 14;
14128 pub const mask: u32 = 0x03 << offset;
14129 pub mod R {}
14130 pub mod W {}
14131 pub mod RW {
14132 #[doc = "100K Ohm Pull Down"]
14133 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
14134 #[doc = "47K Ohm Pull Up"]
14135 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
14136 #[doc = "100K Ohm Pull Up"]
14137 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
14138 #[doc = "22K Ohm Pull Up"]
14139 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
14140 }
14141 }
14142 #[doc = "Hyst. Enable Field"]
14143 pub mod HYS {
14144 pub const offset: u32 = 16;
14145 pub const mask: u32 = 0x01 << offset;
14146 pub mod R {}
14147 pub mod W {}
14148 pub mod RW {
14149 #[doc = "Hysteresis Disabled"]
14150 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
14151 #[doc = "Hysteresis Enabled"]
14152 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
14153 }
14154 }
14155}
14156#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_06 SW PAD Control Register"]
14157pub mod SW_PAD_CTL_PAD_GPIO_AD_B1_06 {
14158 #[doc = "Slew Rate Field"]
14159 pub mod SRE {
14160 pub const offset: u32 = 0;
14161 pub const mask: u32 = 0x01 << offset;
14162 pub mod R {}
14163 pub mod W {}
14164 pub mod RW {
14165 #[doc = "Slow Slew Rate"]
14166 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
14167 #[doc = "Fast Slew Rate"]
14168 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
14169 }
14170 }
14171 #[doc = "Drive Strength Field"]
14172 pub mod DSE {
14173 pub const offset: u32 = 3;
14174 pub const mask: u32 = 0x07 << offset;
14175 pub mod R {}
14176 pub mod W {}
14177 pub mod RW {
14178 #[doc = "output driver disabled;"]
14179 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
14180 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
14181 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
14182 #[doc = "R0/2"]
14183 pub const DSE_2_R0_2: u32 = 0x02;
14184 #[doc = "R0/3"]
14185 pub const DSE_3_R0_3: u32 = 0x03;
14186 #[doc = "R0/4"]
14187 pub const DSE_4_R0_4: u32 = 0x04;
14188 #[doc = "R0/5"]
14189 pub const DSE_5_R0_5: u32 = 0x05;
14190 #[doc = "R0/6"]
14191 pub const DSE_6_R0_6: u32 = 0x06;
14192 #[doc = "R0/7"]
14193 pub const DSE_7_R0_7: u32 = 0x07;
14194 }
14195 }
14196 #[doc = "Speed Field"]
14197 pub mod SPEED {
14198 pub const offset: u32 = 6;
14199 pub const mask: u32 = 0x03 << offset;
14200 pub mod R {}
14201 pub mod W {}
14202 pub mod RW {
14203 #[doc = "low(50MHz)"]
14204 pub const SPEED_0_LOW_50MHZ: u32 = 0;
14205 #[doc = "medium(100MHz)"]
14206 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
14207 #[doc = "medium(100MHz)"]
14208 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
14209 #[doc = "max(200MHz)"]
14210 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
14211 }
14212 }
14213 #[doc = "Open Drain Enable Field"]
14214 pub mod ODE {
14215 pub const offset: u32 = 11;
14216 pub const mask: u32 = 0x01 << offset;
14217 pub mod R {}
14218 pub mod W {}
14219 pub mod RW {
14220 #[doc = "Open Drain Disabled"]
14221 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
14222 #[doc = "Open Drain Enabled"]
14223 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
14224 }
14225 }
14226 #[doc = "Pull / Keep Enable Field"]
14227 pub mod PKE {
14228 pub const offset: u32 = 12;
14229 pub const mask: u32 = 0x01 << offset;
14230 pub mod R {}
14231 pub mod W {}
14232 pub mod RW {
14233 #[doc = "Pull/Keeper Disabled"]
14234 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
14235 #[doc = "Pull/Keeper Enabled"]
14236 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
14237 }
14238 }
14239 #[doc = "Pull / Keep Select Field"]
14240 pub mod PUE {
14241 pub const offset: u32 = 13;
14242 pub const mask: u32 = 0x01 << offset;
14243 pub mod R {}
14244 pub mod W {}
14245 pub mod RW {
14246 #[doc = "Keeper"]
14247 pub const PUE_0_KEEPER: u32 = 0;
14248 #[doc = "Pull"]
14249 pub const PUE_1_PULL: u32 = 0x01;
14250 }
14251 }
14252 #[doc = "Pull Up / Down Config. Field"]
14253 pub mod PUS {
14254 pub const offset: u32 = 14;
14255 pub const mask: u32 = 0x03 << offset;
14256 pub mod R {}
14257 pub mod W {}
14258 pub mod RW {
14259 #[doc = "100K Ohm Pull Down"]
14260 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
14261 #[doc = "47K Ohm Pull Up"]
14262 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
14263 #[doc = "100K Ohm Pull Up"]
14264 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
14265 #[doc = "22K Ohm Pull Up"]
14266 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
14267 }
14268 }
14269 #[doc = "Hyst. Enable Field"]
14270 pub mod HYS {
14271 pub const offset: u32 = 16;
14272 pub const mask: u32 = 0x01 << offset;
14273 pub mod R {}
14274 pub mod W {}
14275 pub mod RW {
14276 #[doc = "Hysteresis Disabled"]
14277 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
14278 #[doc = "Hysteresis Enabled"]
14279 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
14280 }
14281 }
14282}
14283#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_07 SW PAD Control Register"]
14284pub mod SW_PAD_CTL_PAD_GPIO_AD_B1_07 {
14285 #[doc = "Slew Rate Field"]
14286 pub mod SRE {
14287 pub const offset: u32 = 0;
14288 pub const mask: u32 = 0x01 << offset;
14289 pub mod R {}
14290 pub mod W {}
14291 pub mod RW {
14292 #[doc = "Slow Slew Rate"]
14293 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
14294 #[doc = "Fast Slew Rate"]
14295 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
14296 }
14297 }
14298 #[doc = "Drive Strength Field"]
14299 pub mod DSE {
14300 pub const offset: u32 = 3;
14301 pub const mask: u32 = 0x07 << offset;
14302 pub mod R {}
14303 pub mod W {}
14304 pub mod RW {
14305 #[doc = "output driver disabled;"]
14306 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
14307 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
14308 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
14309 #[doc = "R0/2"]
14310 pub const DSE_2_R0_2: u32 = 0x02;
14311 #[doc = "R0/3"]
14312 pub const DSE_3_R0_3: u32 = 0x03;
14313 #[doc = "R0/4"]
14314 pub const DSE_4_R0_4: u32 = 0x04;
14315 #[doc = "R0/5"]
14316 pub const DSE_5_R0_5: u32 = 0x05;
14317 #[doc = "R0/6"]
14318 pub const DSE_6_R0_6: u32 = 0x06;
14319 #[doc = "R0/7"]
14320 pub const DSE_7_R0_7: u32 = 0x07;
14321 }
14322 }
14323 #[doc = "Speed Field"]
14324 pub mod SPEED {
14325 pub const offset: u32 = 6;
14326 pub const mask: u32 = 0x03 << offset;
14327 pub mod R {}
14328 pub mod W {}
14329 pub mod RW {
14330 #[doc = "low(50MHz)"]
14331 pub const SPEED_0_LOW_50MHZ: u32 = 0;
14332 #[doc = "medium(100MHz)"]
14333 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
14334 #[doc = "medium(100MHz)"]
14335 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
14336 #[doc = "max(200MHz)"]
14337 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
14338 }
14339 }
14340 #[doc = "Open Drain Enable Field"]
14341 pub mod ODE {
14342 pub const offset: u32 = 11;
14343 pub const mask: u32 = 0x01 << offset;
14344 pub mod R {}
14345 pub mod W {}
14346 pub mod RW {
14347 #[doc = "Open Drain Disabled"]
14348 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
14349 #[doc = "Open Drain Enabled"]
14350 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
14351 }
14352 }
14353 #[doc = "Pull / Keep Enable Field"]
14354 pub mod PKE {
14355 pub const offset: u32 = 12;
14356 pub const mask: u32 = 0x01 << offset;
14357 pub mod R {}
14358 pub mod W {}
14359 pub mod RW {
14360 #[doc = "Pull/Keeper Disabled"]
14361 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
14362 #[doc = "Pull/Keeper Enabled"]
14363 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
14364 }
14365 }
14366 #[doc = "Pull / Keep Select Field"]
14367 pub mod PUE {
14368 pub const offset: u32 = 13;
14369 pub const mask: u32 = 0x01 << offset;
14370 pub mod R {}
14371 pub mod W {}
14372 pub mod RW {
14373 #[doc = "Keeper"]
14374 pub const PUE_0_KEEPER: u32 = 0;
14375 #[doc = "Pull"]
14376 pub const PUE_1_PULL: u32 = 0x01;
14377 }
14378 }
14379 #[doc = "Pull Up / Down Config. Field"]
14380 pub mod PUS {
14381 pub const offset: u32 = 14;
14382 pub const mask: u32 = 0x03 << offset;
14383 pub mod R {}
14384 pub mod W {}
14385 pub mod RW {
14386 #[doc = "100K Ohm Pull Down"]
14387 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
14388 #[doc = "47K Ohm Pull Up"]
14389 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
14390 #[doc = "100K Ohm Pull Up"]
14391 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
14392 #[doc = "22K Ohm Pull Up"]
14393 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
14394 }
14395 }
14396 #[doc = "Hyst. Enable Field"]
14397 pub mod HYS {
14398 pub const offset: u32 = 16;
14399 pub const mask: u32 = 0x01 << offset;
14400 pub mod R {}
14401 pub mod W {}
14402 pub mod RW {
14403 #[doc = "Hysteresis Disabled"]
14404 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
14405 #[doc = "Hysteresis Enabled"]
14406 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
14407 }
14408 }
14409}
14410#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_08 SW PAD Control Register"]
14411pub mod SW_PAD_CTL_PAD_GPIO_AD_B1_08 {
14412 #[doc = "Slew Rate Field"]
14413 pub mod SRE {
14414 pub const offset: u32 = 0;
14415 pub const mask: u32 = 0x01 << offset;
14416 pub mod R {}
14417 pub mod W {}
14418 pub mod RW {
14419 #[doc = "Slow Slew Rate"]
14420 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
14421 #[doc = "Fast Slew Rate"]
14422 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
14423 }
14424 }
14425 #[doc = "Drive Strength Field"]
14426 pub mod DSE {
14427 pub const offset: u32 = 3;
14428 pub const mask: u32 = 0x07 << offset;
14429 pub mod R {}
14430 pub mod W {}
14431 pub mod RW {
14432 #[doc = "output driver disabled;"]
14433 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
14434 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
14435 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
14436 #[doc = "R0/2"]
14437 pub const DSE_2_R0_2: u32 = 0x02;
14438 #[doc = "R0/3"]
14439 pub const DSE_3_R0_3: u32 = 0x03;
14440 #[doc = "R0/4"]
14441 pub const DSE_4_R0_4: u32 = 0x04;
14442 #[doc = "R0/5"]
14443 pub const DSE_5_R0_5: u32 = 0x05;
14444 #[doc = "R0/6"]
14445 pub const DSE_6_R0_6: u32 = 0x06;
14446 #[doc = "R0/7"]
14447 pub const DSE_7_R0_7: u32 = 0x07;
14448 }
14449 }
14450 #[doc = "Speed Field"]
14451 pub mod SPEED {
14452 pub const offset: u32 = 6;
14453 pub const mask: u32 = 0x03 << offset;
14454 pub mod R {}
14455 pub mod W {}
14456 pub mod RW {
14457 #[doc = "low(50MHz)"]
14458 pub const SPEED_0_LOW_50MHZ: u32 = 0;
14459 #[doc = "medium(100MHz)"]
14460 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
14461 #[doc = "medium(100MHz)"]
14462 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
14463 #[doc = "max(200MHz)"]
14464 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
14465 }
14466 }
14467 #[doc = "Open Drain Enable Field"]
14468 pub mod ODE {
14469 pub const offset: u32 = 11;
14470 pub const mask: u32 = 0x01 << offset;
14471 pub mod R {}
14472 pub mod W {}
14473 pub mod RW {
14474 #[doc = "Open Drain Disabled"]
14475 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
14476 #[doc = "Open Drain Enabled"]
14477 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
14478 }
14479 }
14480 #[doc = "Pull / Keep Enable Field"]
14481 pub mod PKE {
14482 pub const offset: u32 = 12;
14483 pub const mask: u32 = 0x01 << offset;
14484 pub mod R {}
14485 pub mod W {}
14486 pub mod RW {
14487 #[doc = "Pull/Keeper Disabled"]
14488 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
14489 #[doc = "Pull/Keeper Enabled"]
14490 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
14491 }
14492 }
14493 #[doc = "Pull / Keep Select Field"]
14494 pub mod PUE {
14495 pub const offset: u32 = 13;
14496 pub const mask: u32 = 0x01 << offset;
14497 pub mod R {}
14498 pub mod W {}
14499 pub mod RW {
14500 #[doc = "Keeper"]
14501 pub const PUE_0_KEEPER: u32 = 0;
14502 #[doc = "Pull"]
14503 pub const PUE_1_PULL: u32 = 0x01;
14504 }
14505 }
14506 #[doc = "Pull Up / Down Config. Field"]
14507 pub mod PUS {
14508 pub const offset: u32 = 14;
14509 pub const mask: u32 = 0x03 << offset;
14510 pub mod R {}
14511 pub mod W {}
14512 pub mod RW {
14513 #[doc = "100K Ohm Pull Down"]
14514 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
14515 #[doc = "47K Ohm Pull Up"]
14516 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
14517 #[doc = "100K Ohm Pull Up"]
14518 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
14519 #[doc = "22K Ohm Pull Up"]
14520 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
14521 }
14522 }
14523 #[doc = "Hyst. Enable Field"]
14524 pub mod HYS {
14525 pub const offset: u32 = 16;
14526 pub const mask: u32 = 0x01 << offset;
14527 pub mod R {}
14528 pub mod W {}
14529 pub mod RW {
14530 #[doc = "Hysteresis Disabled"]
14531 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
14532 #[doc = "Hysteresis Enabled"]
14533 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
14534 }
14535 }
14536}
14537#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_09 SW PAD Control Register"]
14538pub mod SW_PAD_CTL_PAD_GPIO_AD_B1_09 {
14539 #[doc = "Slew Rate Field"]
14540 pub mod SRE {
14541 pub const offset: u32 = 0;
14542 pub const mask: u32 = 0x01 << offset;
14543 pub mod R {}
14544 pub mod W {}
14545 pub mod RW {
14546 #[doc = "Slow Slew Rate"]
14547 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
14548 #[doc = "Fast Slew Rate"]
14549 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
14550 }
14551 }
14552 #[doc = "Drive Strength Field"]
14553 pub mod DSE {
14554 pub const offset: u32 = 3;
14555 pub const mask: u32 = 0x07 << offset;
14556 pub mod R {}
14557 pub mod W {}
14558 pub mod RW {
14559 #[doc = "output driver disabled;"]
14560 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
14561 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
14562 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
14563 #[doc = "R0/2"]
14564 pub const DSE_2_R0_2: u32 = 0x02;
14565 #[doc = "R0/3"]
14566 pub const DSE_3_R0_3: u32 = 0x03;
14567 #[doc = "R0/4"]
14568 pub const DSE_4_R0_4: u32 = 0x04;
14569 #[doc = "R0/5"]
14570 pub const DSE_5_R0_5: u32 = 0x05;
14571 #[doc = "R0/6"]
14572 pub const DSE_6_R0_6: u32 = 0x06;
14573 #[doc = "R0/7"]
14574 pub const DSE_7_R0_7: u32 = 0x07;
14575 }
14576 }
14577 #[doc = "Speed Field"]
14578 pub mod SPEED {
14579 pub const offset: u32 = 6;
14580 pub const mask: u32 = 0x03 << offset;
14581 pub mod R {}
14582 pub mod W {}
14583 pub mod RW {
14584 #[doc = "low(50MHz)"]
14585 pub const SPEED_0_LOW_50MHZ: u32 = 0;
14586 #[doc = "medium(100MHz)"]
14587 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
14588 #[doc = "medium(100MHz)"]
14589 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
14590 #[doc = "max(200MHz)"]
14591 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
14592 }
14593 }
14594 #[doc = "Open Drain Enable Field"]
14595 pub mod ODE {
14596 pub const offset: u32 = 11;
14597 pub const mask: u32 = 0x01 << offset;
14598 pub mod R {}
14599 pub mod W {}
14600 pub mod RW {
14601 #[doc = "Open Drain Disabled"]
14602 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
14603 #[doc = "Open Drain Enabled"]
14604 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
14605 }
14606 }
14607 #[doc = "Pull / Keep Enable Field"]
14608 pub mod PKE {
14609 pub const offset: u32 = 12;
14610 pub const mask: u32 = 0x01 << offset;
14611 pub mod R {}
14612 pub mod W {}
14613 pub mod RW {
14614 #[doc = "Pull/Keeper Disabled"]
14615 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
14616 #[doc = "Pull/Keeper Enabled"]
14617 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
14618 }
14619 }
14620 #[doc = "Pull / Keep Select Field"]
14621 pub mod PUE {
14622 pub const offset: u32 = 13;
14623 pub const mask: u32 = 0x01 << offset;
14624 pub mod R {}
14625 pub mod W {}
14626 pub mod RW {
14627 #[doc = "Keeper"]
14628 pub const PUE_0_KEEPER: u32 = 0;
14629 #[doc = "Pull"]
14630 pub const PUE_1_PULL: u32 = 0x01;
14631 }
14632 }
14633 #[doc = "Pull Up / Down Config. Field"]
14634 pub mod PUS {
14635 pub const offset: u32 = 14;
14636 pub const mask: u32 = 0x03 << offset;
14637 pub mod R {}
14638 pub mod W {}
14639 pub mod RW {
14640 #[doc = "100K Ohm Pull Down"]
14641 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
14642 #[doc = "47K Ohm Pull Up"]
14643 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
14644 #[doc = "100K Ohm Pull Up"]
14645 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
14646 #[doc = "22K Ohm Pull Up"]
14647 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
14648 }
14649 }
14650 #[doc = "Hyst. Enable Field"]
14651 pub mod HYS {
14652 pub const offset: u32 = 16;
14653 pub const mask: u32 = 0x01 << offset;
14654 pub mod R {}
14655 pub mod W {}
14656 pub mod RW {
14657 #[doc = "Hysteresis Disabled"]
14658 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
14659 #[doc = "Hysteresis Enabled"]
14660 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
14661 }
14662 }
14663}
14664#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_10 SW PAD Control Register"]
14665pub mod SW_PAD_CTL_PAD_GPIO_AD_B1_10 {
14666 #[doc = "Slew Rate Field"]
14667 pub mod SRE {
14668 pub const offset: u32 = 0;
14669 pub const mask: u32 = 0x01 << offset;
14670 pub mod R {}
14671 pub mod W {}
14672 pub mod RW {
14673 #[doc = "Slow Slew Rate"]
14674 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
14675 #[doc = "Fast Slew Rate"]
14676 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
14677 }
14678 }
14679 #[doc = "Drive Strength Field"]
14680 pub mod DSE {
14681 pub const offset: u32 = 3;
14682 pub const mask: u32 = 0x07 << offset;
14683 pub mod R {}
14684 pub mod W {}
14685 pub mod RW {
14686 #[doc = "output driver disabled;"]
14687 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
14688 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
14689 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
14690 #[doc = "R0/2"]
14691 pub const DSE_2_R0_2: u32 = 0x02;
14692 #[doc = "R0/3"]
14693 pub const DSE_3_R0_3: u32 = 0x03;
14694 #[doc = "R0/4"]
14695 pub const DSE_4_R0_4: u32 = 0x04;
14696 #[doc = "R0/5"]
14697 pub const DSE_5_R0_5: u32 = 0x05;
14698 #[doc = "R0/6"]
14699 pub const DSE_6_R0_6: u32 = 0x06;
14700 #[doc = "R0/7"]
14701 pub const DSE_7_R0_7: u32 = 0x07;
14702 }
14703 }
14704 #[doc = "Speed Field"]
14705 pub mod SPEED {
14706 pub const offset: u32 = 6;
14707 pub const mask: u32 = 0x03 << offset;
14708 pub mod R {}
14709 pub mod W {}
14710 pub mod RW {
14711 #[doc = "low(50MHz)"]
14712 pub const SPEED_0_LOW_50MHZ: u32 = 0;
14713 #[doc = "medium(100MHz)"]
14714 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
14715 #[doc = "medium(100MHz)"]
14716 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
14717 #[doc = "max(200MHz)"]
14718 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
14719 }
14720 }
14721 #[doc = "Open Drain Enable Field"]
14722 pub mod ODE {
14723 pub const offset: u32 = 11;
14724 pub const mask: u32 = 0x01 << offset;
14725 pub mod R {}
14726 pub mod W {}
14727 pub mod RW {
14728 #[doc = "Open Drain Disabled"]
14729 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
14730 #[doc = "Open Drain Enabled"]
14731 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
14732 }
14733 }
14734 #[doc = "Pull / Keep Enable Field"]
14735 pub mod PKE {
14736 pub const offset: u32 = 12;
14737 pub const mask: u32 = 0x01 << offset;
14738 pub mod R {}
14739 pub mod W {}
14740 pub mod RW {
14741 #[doc = "Pull/Keeper Disabled"]
14742 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
14743 #[doc = "Pull/Keeper Enabled"]
14744 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
14745 }
14746 }
14747 #[doc = "Pull / Keep Select Field"]
14748 pub mod PUE {
14749 pub const offset: u32 = 13;
14750 pub const mask: u32 = 0x01 << offset;
14751 pub mod R {}
14752 pub mod W {}
14753 pub mod RW {
14754 #[doc = "Keeper"]
14755 pub const PUE_0_KEEPER: u32 = 0;
14756 #[doc = "Pull"]
14757 pub const PUE_1_PULL: u32 = 0x01;
14758 }
14759 }
14760 #[doc = "Pull Up / Down Config. Field"]
14761 pub mod PUS {
14762 pub const offset: u32 = 14;
14763 pub const mask: u32 = 0x03 << offset;
14764 pub mod R {}
14765 pub mod W {}
14766 pub mod RW {
14767 #[doc = "100K Ohm Pull Down"]
14768 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
14769 #[doc = "47K Ohm Pull Up"]
14770 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
14771 #[doc = "100K Ohm Pull Up"]
14772 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
14773 #[doc = "22K Ohm Pull Up"]
14774 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
14775 }
14776 }
14777 #[doc = "Hyst. Enable Field"]
14778 pub mod HYS {
14779 pub const offset: u32 = 16;
14780 pub const mask: u32 = 0x01 << offset;
14781 pub mod R {}
14782 pub mod W {}
14783 pub mod RW {
14784 #[doc = "Hysteresis Disabled"]
14785 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
14786 #[doc = "Hysteresis Enabled"]
14787 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
14788 }
14789 }
14790}
14791#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_11 SW PAD Control Register"]
14792pub mod SW_PAD_CTL_PAD_GPIO_AD_B1_11 {
14793 #[doc = "Slew Rate Field"]
14794 pub mod SRE {
14795 pub const offset: u32 = 0;
14796 pub const mask: u32 = 0x01 << offset;
14797 pub mod R {}
14798 pub mod W {}
14799 pub mod RW {
14800 #[doc = "Slow Slew Rate"]
14801 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
14802 #[doc = "Fast Slew Rate"]
14803 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
14804 }
14805 }
14806 #[doc = "Drive Strength Field"]
14807 pub mod DSE {
14808 pub const offset: u32 = 3;
14809 pub const mask: u32 = 0x07 << offset;
14810 pub mod R {}
14811 pub mod W {}
14812 pub mod RW {
14813 #[doc = "output driver disabled;"]
14814 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
14815 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
14816 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
14817 #[doc = "R0/2"]
14818 pub const DSE_2_R0_2: u32 = 0x02;
14819 #[doc = "R0/3"]
14820 pub const DSE_3_R0_3: u32 = 0x03;
14821 #[doc = "R0/4"]
14822 pub const DSE_4_R0_4: u32 = 0x04;
14823 #[doc = "R0/5"]
14824 pub const DSE_5_R0_5: u32 = 0x05;
14825 #[doc = "R0/6"]
14826 pub const DSE_6_R0_6: u32 = 0x06;
14827 #[doc = "R0/7"]
14828 pub const DSE_7_R0_7: u32 = 0x07;
14829 }
14830 }
14831 #[doc = "Speed Field"]
14832 pub mod SPEED {
14833 pub const offset: u32 = 6;
14834 pub const mask: u32 = 0x03 << offset;
14835 pub mod R {}
14836 pub mod W {}
14837 pub mod RW {
14838 #[doc = "low(50MHz)"]
14839 pub const SPEED_0_LOW_50MHZ: u32 = 0;
14840 #[doc = "medium(100MHz)"]
14841 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
14842 #[doc = "medium(100MHz)"]
14843 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
14844 #[doc = "max(200MHz)"]
14845 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
14846 }
14847 }
14848 #[doc = "Open Drain Enable Field"]
14849 pub mod ODE {
14850 pub const offset: u32 = 11;
14851 pub const mask: u32 = 0x01 << offset;
14852 pub mod R {}
14853 pub mod W {}
14854 pub mod RW {
14855 #[doc = "Open Drain Disabled"]
14856 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
14857 #[doc = "Open Drain Enabled"]
14858 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
14859 }
14860 }
14861 #[doc = "Pull / Keep Enable Field"]
14862 pub mod PKE {
14863 pub const offset: u32 = 12;
14864 pub const mask: u32 = 0x01 << offset;
14865 pub mod R {}
14866 pub mod W {}
14867 pub mod RW {
14868 #[doc = "Pull/Keeper Disabled"]
14869 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
14870 #[doc = "Pull/Keeper Enabled"]
14871 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
14872 }
14873 }
14874 #[doc = "Pull / Keep Select Field"]
14875 pub mod PUE {
14876 pub const offset: u32 = 13;
14877 pub const mask: u32 = 0x01 << offset;
14878 pub mod R {}
14879 pub mod W {}
14880 pub mod RW {
14881 #[doc = "Keeper"]
14882 pub const PUE_0_KEEPER: u32 = 0;
14883 #[doc = "Pull"]
14884 pub const PUE_1_PULL: u32 = 0x01;
14885 }
14886 }
14887 #[doc = "Pull Up / Down Config. Field"]
14888 pub mod PUS {
14889 pub const offset: u32 = 14;
14890 pub const mask: u32 = 0x03 << offset;
14891 pub mod R {}
14892 pub mod W {}
14893 pub mod RW {
14894 #[doc = "100K Ohm Pull Down"]
14895 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
14896 #[doc = "47K Ohm Pull Up"]
14897 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
14898 #[doc = "100K Ohm Pull Up"]
14899 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
14900 #[doc = "22K Ohm Pull Up"]
14901 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
14902 }
14903 }
14904 #[doc = "Hyst. Enable Field"]
14905 pub mod HYS {
14906 pub const offset: u32 = 16;
14907 pub const mask: u32 = 0x01 << offset;
14908 pub mod R {}
14909 pub mod W {}
14910 pub mod RW {
14911 #[doc = "Hysteresis Disabled"]
14912 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
14913 #[doc = "Hysteresis Enabled"]
14914 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
14915 }
14916 }
14917}
14918#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_12 SW PAD Control Register"]
14919pub mod SW_PAD_CTL_PAD_GPIO_AD_B1_12 {
14920 #[doc = "Slew Rate Field"]
14921 pub mod SRE {
14922 pub const offset: u32 = 0;
14923 pub const mask: u32 = 0x01 << offset;
14924 pub mod R {}
14925 pub mod W {}
14926 pub mod RW {
14927 #[doc = "Slow Slew Rate"]
14928 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
14929 #[doc = "Fast Slew Rate"]
14930 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
14931 }
14932 }
14933 #[doc = "Drive Strength Field"]
14934 pub mod DSE {
14935 pub const offset: u32 = 3;
14936 pub const mask: u32 = 0x07 << offset;
14937 pub mod R {}
14938 pub mod W {}
14939 pub mod RW {
14940 #[doc = "output driver disabled;"]
14941 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
14942 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
14943 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
14944 #[doc = "R0/2"]
14945 pub const DSE_2_R0_2: u32 = 0x02;
14946 #[doc = "R0/3"]
14947 pub const DSE_3_R0_3: u32 = 0x03;
14948 #[doc = "R0/4"]
14949 pub const DSE_4_R0_4: u32 = 0x04;
14950 #[doc = "R0/5"]
14951 pub const DSE_5_R0_5: u32 = 0x05;
14952 #[doc = "R0/6"]
14953 pub const DSE_6_R0_6: u32 = 0x06;
14954 #[doc = "R0/7"]
14955 pub const DSE_7_R0_7: u32 = 0x07;
14956 }
14957 }
14958 #[doc = "Speed Field"]
14959 pub mod SPEED {
14960 pub const offset: u32 = 6;
14961 pub const mask: u32 = 0x03 << offset;
14962 pub mod R {}
14963 pub mod W {}
14964 pub mod RW {
14965 #[doc = "low(50MHz)"]
14966 pub const SPEED_0_LOW_50MHZ: u32 = 0;
14967 #[doc = "medium(100MHz)"]
14968 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
14969 #[doc = "medium(100MHz)"]
14970 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
14971 #[doc = "max(200MHz)"]
14972 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
14973 }
14974 }
14975 #[doc = "Open Drain Enable Field"]
14976 pub mod ODE {
14977 pub const offset: u32 = 11;
14978 pub const mask: u32 = 0x01 << offset;
14979 pub mod R {}
14980 pub mod W {}
14981 pub mod RW {
14982 #[doc = "Open Drain Disabled"]
14983 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
14984 #[doc = "Open Drain Enabled"]
14985 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
14986 }
14987 }
14988 #[doc = "Pull / Keep Enable Field"]
14989 pub mod PKE {
14990 pub const offset: u32 = 12;
14991 pub const mask: u32 = 0x01 << offset;
14992 pub mod R {}
14993 pub mod W {}
14994 pub mod RW {
14995 #[doc = "Pull/Keeper Disabled"]
14996 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
14997 #[doc = "Pull/Keeper Enabled"]
14998 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
14999 }
15000 }
15001 #[doc = "Pull / Keep Select Field"]
15002 pub mod PUE {
15003 pub const offset: u32 = 13;
15004 pub const mask: u32 = 0x01 << offset;
15005 pub mod R {}
15006 pub mod W {}
15007 pub mod RW {
15008 #[doc = "Keeper"]
15009 pub const PUE_0_KEEPER: u32 = 0;
15010 #[doc = "Pull"]
15011 pub const PUE_1_PULL: u32 = 0x01;
15012 }
15013 }
15014 #[doc = "Pull Up / Down Config. Field"]
15015 pub mod PUS {
15016 pub const offset: u32 = 14;
15017 pub const mask: u32 = 0x03 << offset;
15018 pub mod R {}
15019 pub mod W {}
15020 pub mod RW {
15021 #[doc = "100K Ohm Pull Down"]
15022 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
15023 #[doc = "47K Ohm Pull Up"]
15024 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
15025 #[doc = "100K Ohm Pull Up"]
15026 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
15027 #[doc = "22K Ohm Pull Up"]
15028 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
15029 }
15030 }
15031 #[doc = "Hyst. Enable Field"]
15032 pub mod HYS {
15033 pub const offset: u32 = 16;
15034 pub const mask: u32 = 0x01 << offset;
15035 pub mod R {}
15036 pub mod W {}
15037 pub mod RW {
15038 #[doc = "Hysteresis Disabled"]
15039 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
15040 #[doc = "Hysteresis Enabled"]
15041 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
15042 }
15043 }
15044}
15045#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_13 SW PAD Control Register"]
15046pub mod SW_PAD_CTL_PAD_GPIO_AD_B1_13 {
15047 #[doc = "Slew Rate Field"]
15048 pub mod SRE {
15049 pub const offset: u32 = 0;
15050 pub const mask: u32 = 0x01 << offset;
15051 pub mod R {}
15052 pub mod W {}
15053 pub mod RW {
15054 #[doc = "Slow Slew Rate"]
15055 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
15056 #[doc = "Fast Slew Rate"]
15057 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
15058 }
15059 }
15060 #[doc = "Drive Strength Field"]
15061 pub mod DSE {
15062 pub const offset: u32 = 3;
15063 pub const mask: u32 = 0x07 << offset;
15064 pub mod R {}
15065 pub mod W {}
15066 pub mod RW {
15067 #[doc = "output driver disabled;"]
15068 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
15069 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
15070 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
15071 #[doc = "R0/2"]
15072 pub const DSE_2_R0_2: u32 = 0x02;
15073 #[doc = "R0/3"]
15074 pub const DSE_3_R0_3: u32 = 0x03;
15075 #[doc = "R0/4"]
15076 pub const DSE_4_R0_4: u32 = 0x04;
15077 #[doc = "R0/5"]
15078 pub const DSE_5_R0_5: u32 = 0x05;
15079 #[doc = "R0/6"]
15080 pub const DSE_6_R0_6: u32 = 0x06;
15081 #[doc = "R0/7"]
15082 pub const DSE_7_R0_7: u32 = 0x07;
15083 }
15084 }
15085 #[doc = "Speed Field"]
15086 pub mod SPEED {
15087 pub const offset: u32 = 6;
15088 pub const mask: u32 = 0x03 << offset;
15089 pub mod R {}
15090 pub mod W {}
15091 pub mod RW {
15092 #[doc = "low(50MHz)"]
15093 pub const SPEED_0_LOW_50MHZ: u32 = 0;
15094 #[doc = "medium(100MHz)"]
15095 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
15096 #[doc = "medium(100MHz)"]
15097 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
15098 #[doc = "max(200MHz)"]
15099 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
15100 }
15101 }
15102 #[doc = "Open Drain Enable Field"]
15103 pub mod ODE {
15104 pub const offset: u32 = 11;
15105 pub const mask: u32 = 0x01 << offset;
15106 pub mod R {}
15107 pub mod W {}
15108 pub mod RW {
15109 #[doc = "Open Drain Disabled"]
15110 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
15111 #[doc = "Open Drain Enabled"]
15112 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
15113 }
15114 }
15115 #[doc = "Pull / Keep Enable Field"]
15116 pub mod PKE {
15117 pub const offset: u32 = 12;
15118 pub const mask: u32 = 0x01 << offset;
15119 pub mod R {}
15120 pub mod W {}
15121 pub mod RW {
15122 #[doc = "Pull/Keeper Disabled"]
15123 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
15124 #[doc = "Pull/Keeper Enabled"]
15125 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
15126 }
15127 }
15128 #[doc = "Pull / Keep Select Field"]
15129 pub mod PUE {
15130 pub const offset: u32 = 13;
15131 pub const mask: u32 = 0x01 << offset;
15132 pub mod R {}
15133 pub mod W {}
15134 pub mod RW {
15135 #[doc = "Keeper"]
15136 pub const PUE_0_KEEPER: u32 = 0;
15137 #[doc = "Pull"]
15138 pub const PUE_1_PULL: u32 = 0x01;
15139 }
15140 }
15141 #[doc = "Pull Up / Down Config. Field"]
15142 pub mod PUS {
15143 pub const offset: u32 = 14;
15144 pub const mask: u32 = 0x03 << offset;
15145 pub mod R {}
15146 pub mod W {}
15147 pub mod RW {
15148 #[doc = "100K Ohm Pull Down"]
15149 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
15150 #[doc = "47K Ohm Pull Up"]
15151 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
15152 #[doc = "100K Ohm Pull Up"]
15153 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
15154 #[doc = "22K Ohm Pull Up"]
15155 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
15156 }
15157 }
15158 #[doc = "Hyst. Enable Field"]
15159 pub mod HYS {
15160 pub const offset: u32 = 16;
15161 pub const mask: u32 = 0x01 << offset;
15162 pub mod R {}
15163 pub mod W {}
15164 pub mod RW {
15165 #[doc = "Hysteresis Disabled"]
15166 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
15167 #[doc = "Hysteresis Enabled"]
15168 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
15169 }
15170 }
15171}
15172#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_14 SW PAD Control Register"]
15173pub mod SW_PAD_CTL_PAD_GPIO_AD_B1_14 {
15174 #[doc = "Slew Rate Field"]
15175 pub mod SRE {
15176 pub const offset: u32 = 0;
15177 pub const mask: u32 = 0x01 << offset;
15178 pub mod R {}
15179 pub mod W {}
15180 pub mod RW {
15181 #[doc = "Slow Slew Rate"]
15182 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
15183 #[doc = "Fast Slew Rate"]
15184 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
15185 }
15186 }
15187 #[doc = "Drive Strength Field"]
15188 pub mod DSE {
15189 pub const offset: u32 = 3;
15190 pub const mask: u32 = 0x07 << offset;
15191 pub mod R {}
15192 pub mod W {}
15193 pub mod RW {
15194 #[doc = "output driver disabled;"]
15195 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
15196 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
15197 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
15198 #[doc = "R0/2"]
15199 pub const DSE_2_R0_2: u32 = 0x02;
15200 #[doc = "R0/3"]
15201 pub const DSE_3_R0_3: u32 = 0x03;
15202 #[doc = "R0/4"]
15203 pub const DSE_4_R0_4: u32 = 0x04;
15204 #[doc = "R0/5"]
15205 pub const DSE_5_R0_5: u32 = 0x05;
15206 #[doc = "R0/6"]
15207 pub const DSE_6_R0_6: u32 = 0x06;
15208 #[doc = "R0/7"]
15209 pub const DSE_7_R0_7: u32 = 0x07;
15210 }
15211 }
15212 #[doc = "Speed Field"]
15213 pub mod SPEED {
15214 pub const offset: u32 = 6;
15215 pub const mask: u32 = 0x03 << offset;
15216 pub mod R {}
15217 pub mod W {}
15218 pub mod RW {
15219 #[doc = "low(50MHz)"]
15220 pub const SPEED_0_LOW_50MHZ: u32 = 0;
15221 #[doc = "medium(100MHz)"]
15222 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
15223 #[doc = "medium(100MHz)"]
15224 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
15225 #[doc = "max(200MHz)"]
15226 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
15227 }
15228 }
15229 #[doc = "Open Drain Enable Field"]
15230 pub mod ODE {
15231 pub const offset: u32 = 11;
15232 pub const mask: u32 = 0x01 << offset;
15233 pub mod R {}
15234 pub mod W {}
15235 pub mod RW {
15236 #[doc = "Open Drain Disabled"]
15237 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
15238 #[doc = "Open Drain Enabled"]
15239 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
15240 }
15241 }
15242 #[doc = "Pull / Keep Enable Field"]
15243 pub mod PKE {
15244 pub const offset: u32 = 12;
15245 pub const mask: u32 = 0x01 << offset;
15246 pub mod R {}
15247 pub mod W {}
15248 pub mod RW {
15249 #[doc = "Pull/Keeper Disabled"]
15250 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
15251 #[doc = "Pull/Keeper Enabled"]
15252 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
15253 }
15254 }
15255 #[doc = "Pull / Keep Select Field"]
15256 pub mod PUE {
15257 pub const offset: u32 = 13;
15258 pub const mask: u32 = 0x01 << offset;
15259 pub mod R {}
15260 pub mod W {}
15261 pub mod RW {
15262 #[doc = "Keeper"]
15263 pub const PUE_0_KEEPER: u32 = 0;
15264 #[doc = "Pull"]
15265 pub const PUE_1_PULL: u32 = 0x01;
15266 }
15267 }
15268 #[doc = "Pull Up / Down Config. Field"]
15269 pub mod PUS {
15270 pub const offset: u32 = 14;
15271 pub const mask: u32 = 0x03 << offset;
15272 pub mod R {}
15273 pub mod W {}
15274 pub mod RW {
15275 #[doc = "100K Ohm Pull Down"]
15276 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
15277 #[doc = "47K Ohm Pull Up"]
15278 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
15279 #[doc = "100K Ohm Pull Up"]
15280 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
15281 #[doc = "22K Ohm Pull Up"]
15282 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
15283 }
15284 }
15285 #[doc = "Hyst. Enable Field"]
15286 pub mod HYS {
15287 pub const offset: u32 = 16;
15288 pub const mask: u32 = 0x01 << offset;
15289 pub mod R {}
15290 pub mod W {}
15291 pub mod RW {
15292 #[doc = "Hysteresis Disabled"]
15293 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
15294 #[doc = "Hysteresis Enabled"]
15295 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
15296 }
15297 }
15298}
15299#[doc = "SW_PAD_CTL_PAD_GPIO_AD_B1_15 SW PAD Control Register"]
15300pub mod SW_PAD_CTL_PAD_GPIO_AD_B1_15 {
15301 #[doc = "Slew Rate Field"]
15302 pub mod SRE {
15303 pub const offset: u32 = 0;
15304 pub const mask: u32 = 0x01 << offset;
15305 pub mod R {}
15306 pub mod W {}
15307 pub mod RW {
15308 #[doc = "Slow Slew Rate"]
15309 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
15310 #[doc = "Fast Slew Rate"]
15311 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
15312 }
15313 }
15314 #[doc = "Drive Strength Field"]
15315 pub mod DSE {
15316 pub const offset: u32 = 3;
15317 pub const mask: u32 = 0x07 << offset;
15318 pub mod R {}
15319 pub mod W {}
15320 pub mod RW {
15321 #[doc = "output driver disabled;"]
15322 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
15323 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
15324 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
15325 #[doc = "R0/2"]
15326 pub const DSE_2_R0_2: u32 = 0x02;
15327 #[doc = "R0/3"]
15328 pub const DSE_3_R0_3: u32 = 0x03;
15329 #[doc = "R0/4"]
15330 pub const DSE_4_R0_4: u32 = 0x04;
15331 #[doc = "R0/5"]
15332 pub const DSE_5_R0_5: u32 = 0x05;
15333 #[doc = "R0/6"]
15334 pub const DSE_6_R0_6: u32 = 0x06;
15335 #[doc = "R0/7"]
15336 pub const DSE_7_R0_7: u32 = 0x07;
15337 }
15338 }
15339 #[doc = "Speed Field"]
15340 pub mod SPEED {
15341 pub const offset: u32 = 6;
15342 pub const mask: u32 = 0x03 << offset;
15343 pub mod R {}
15344 pub mod W {}
15345 pub mod RW {
15346 #[doc = "low(50MHz)"]
15347 pub const SPEED_0_LOW_50MHZ: u32 = 0;
15348 #[doc = "medium(100MHz)"]
15349 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
15350 #[doc = "medium(100MHz)"]
15351 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
15352 #[doc = "max(200MHz)"]
15353 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
15354 }
15355 }
15356 #[doc = "Open Drain Enable Field"]
15357 pub mod ODE {
15358 pub const offset: u32 = 11;
15359 pub const mask: u32 = 0x01 << offset;
15360 pub mod R {}
15361 pub mod W {}
15362 pub mod RW {
15363 #[doc = "Open Drain Disabled"]
15364 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
15365 #[doc = "Open Drain Enabled"]
15366 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
15367 }
15368 }
15369 #[doc = "Pull / Keep Enable Field"]
15370 pub mod PKE {
15371 pub const offset: u32 = 12;
15372 pub const mask: u32 = 0x01 << offset;
15373 pub mod R {}
15374 pub mod W {}
15375 pub mod RW {
15376 #[doc = "Pull/Keeper Disabled"]
15377 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
15378 #[doc = "Pull/Keeper Enabled"]
15379 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
15380 }
15381 }
15382 #[doc = "Pull / Keep Select Field"]
15383 pub mod PUE {
15384 pub const offset: u32 = 13;
15385 pub const mask: u32 = 0x01 << offset;
15386 pub mod R {}
15387 pub mod W {}
15388 pub mod RW {
15389 #[doc = "Keeper"]
15390 pub const PUE_0_KEEPER: u32 = 0;
15391 #[doc = "Pull"]
15392 pub const PUE_1_PULL: u32 = 0x01;
15393 }
15394 }
15395 #[doc = "Pull Up / Down Config. Field"]
15396 pub mod PUS {
15397 pub const offset: u32 = 14;
15398 pub const mask: u32 = 0x03 << offset;
15399 pub mod R {}
15400 pub mod W {}
15401 pub mod RW {
15402 #[doc = "100K Ohm Pull Down"]
15403 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
15404 #[doc = "47K Ohm Pull Up"]
15405 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
15406 #[doc = "100K Ohm Pull Up"]
15407 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
15408 #[doc = "22K Ohm Pull Up"]
15409 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
15410 }
15411 }
15412 #[doc = "Hyst. Enable Field"]
15413 pub mod HYS {
15414 pub const offset: u32 = 16;
15415 pub const mask: u32 = 0x01 << offset;
15416 pub mod R {}
15417 pub mod W {}
15418 pub mod RW {
15419 #[doc = "Hysteresis Disabled"]
15420 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
15421 #[doc = "Hysteresis Enabled"]
15422 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
15423 }
15424 }
15425}
15426#[doc = "SW_PAD_CTL_PAD_GPIO_B0_00 SW PAD Control Register"]
15427pub mod SW_PAD_CTL_PAD_GPIO_B0_00 {
15428 #[doc = "Slew Rate Field"]
15429 pub mod SRE {
15430 pub const offset: u32 = 0;
15431 pub const mask: u32 = 0x01 << offset;
15432 pub mod R {}
15433 pub mod W {}
15434 pub mod RW {
15435 #[doc = "Slow Slew Rate"]
15436 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
15437 #[doc = "Fast Slew Rate"]
15438 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
15439 }
15440 }
15441 #[doc = "Drive Strength Field"]
15442 pub mod DSE {
15443 pub const offset: u32 = 3;
15444 pub const mask: u32 = 0x07 << offset;
15445 pub mod R {}
15446 pub mod W {}
15447 pub mod RW {
15448 #[doc = "output driver disabled;"]
15449 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
15450 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
15451 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
15452 #[doc = "R0/2"]
15453 pub const DSE_2_R0_2: u32 = 0x02;
15454 #[doc = "R0/3"]
15455 pub const DSE_3_R0_3: u32 = 0x03;
15456 #[doc = "R0/4"]
15457 pub const DSE_4_R0_4: u32 = 0x04;
15458 #[doc = "R0/5"]
15459 pub const DSE_5_R0_5: u32 = 0x05;
15460 #[doc = "R0/6"]
15461 pub const DSE_6_R0_6: u32 = 0x06;
15462 #[doc = "R0/7"]
15463 pub const DSE_7_R0_7: u32 = 0x07;
15464 }
15465 }
15466 #[doc = "Speed Field"]
15467 pub mod SPEED {
15468 pub const offset: u32 = 6;
15469 pub const mask: u32 = 0x03 << offset;
15470 pub mod R {}
15471 pub mod W {}
15472 pub mod RW {
15473 #[doc = "low(50MHz)"]
15474 pub const SPEED_0_LOW_50MHZ: u32 = 0;
15475 #[doc = "medium(100MHz)"]
15476 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
15477 #[doc = "medium(100MHz)"]
15478 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
15479 #[doc = "max(200MHz)"]
15480 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
15481 }
15482 }
15483 #[doc = "Open Drain Enable Field"]
15484 pub mod ODE {
15485 pub const offset: u32 = 11;
15486 pub const mask: u32 = 0x01 << offset;
15487 pub mod R {}
15488 pub mod W {}
15489 pub mod RW {
15490 #[doc = "Open Drain Disabled"]
15491 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
15492 #[doc = "Open Drain Enabled"]
15493 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
15494 }
15495 }
15496 #[doc = "Pull / Keep Enable Field"]
15497 pub mod PKE {
15498 pub const offset: u32 = 12;
15499 pub const mask: u32 = 0x01 << offset;
15500 pub mod R {}
15501 pub mod W {}
15502 pub mod RW {
15503 #[doc = "Pull/Keeper Disabled"]
15504 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
15505 #[doc = "Pull/Keeper Enabled"]
15506 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
15507 }
15508 }
15509 #[doc = "Pull / Keep Select Field"]
15510 pub mod PUE {
15511 pub const offset: u32 = 13;
15512 pub const mask: u32 = 0x01 << offset;
15513 pub mod R {}
15514 pub mod W {}
15515 pub mod RW {
15516 #[doc = "Keeper"]
15517 pub const PUE_0_KEEPER: u32 = 0;
15518 #[doc = "Pull"]
15519 pub const PUE_1_PULL: u32 = 0x01;
15520 }
15521 }
15522 #[doc = "Pull Up / Down Config. Field"]
15523 pub mod PUS {
15524 pub const offset: u32 = 14;
15525 pub const mask: u32 = 0x03 << offset;
15526 pub mod R {}
15527 pub mod W {}
15528 pub mod RW {
15529 #[doc = "100K Ohm Pull Down"]
15530 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
15531 #[doc = "47K Ohm Pull Up"]
15532 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
15533 #[doc = "100K Ohm Pull Up"]
15534 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
15535 #[doc = "22K Ohm Pull Up"]
15536 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
15537 }
15538 }
15539 #[doc = "Hyst. Enable Field"]
15540 pub mod HYS {
15541 pub const offset: u32 = 16;
15542 pub const mask: u32 = 0x01 << offset;
15543 pub mod R {}
15544 pub mod W {}
15545 pub mod RW {
15546 #[doc = "Hysteresis Disabled"]
15547 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
15548 #[doc = "Hysteresis Enabled"]
15549 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
15550 }
15551 }
15552}
15553#[doc = "SW_PAD_CTL_PAD_GPIO_B0_01 SW PAD Control Register"]
15554pub mod SW_PAD_CTL_PAD_GPIO_B0_01 {
15555 #[doc = "Slew Rate Field"]
15556 pub mod SRE {
15557 pub const offset: u32 = 0;
15558 pub const mask: u32 = 0x01 << offset;
15559 pub mod R {}
15560 pub mod W {}
15561 pub mod RW {
15562 #[doc = "Slow Slew Rate"]
15563 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
15564 #[doc = "Fast Slew Rate"]
15565 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
15566 }
15567 }
15568 #[doc = "Drive Strength Field"]
15569 pub mod DSE {
15570 pub const offset: u32 = 3;
15571 pub const mask: u32 = 0x07 << offset;
15572 pub mod R {}
15573 pub mod W {}
15574 pub mod RW {
15575 #[doc = "output driver disabled;"]
15576 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
15577 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
15578 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
15579 #[doc = "R0/2"]
15580 pub const DSE_2_R0_2: u32 = 0x02;
15581 #[doc = "R0/3"]
15582 pub const DSE_3_R0_3: u32 = 0x03;
15583 #[doc = "R0/4"]
15584 pub const DSE_4_R0_4: u32 = 0x04;
15585 #[doc = "R0/5"]
15586 pub const DSE_5_R0_5: u32 = 0x05;
15587 #[doc = "R0/6"]
15588 pub const DSE_6_R0_6: u32 = 0x06;
15589 #[doc = "R0/7"]
15590 pub const DSE_7_R0_7: u32 = 0x07;
15591 }
15592 }
15593 #[doc = "Speed Field"]
15594 pub mod SPEED {
15595 pub const offset: u32 = 6;
15596 pub const mask: u32 = 0x03 << offset;
15597 pub mod R {}
15598 pub mod W {}
15599 pub mod RW {
15600 #[doc = "low(50MHz)"]
15601 pub const SPEED_0_LOW_50MHZ: u32 = 0;
15602 #[doc = "medium(100MHz)"]
15603 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
15604 #[doc = "medium(100MHz)"]
15605 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
15606 #[doc = "max(200MHz)"]
15607 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
15608 }
15609 }
15610 #[doc = "Open Drain Enable Field"]
15611 pub mod ODE {
15612 pub const offset: u32 = 11;
15613 pub const mask: u32 = 0x01 << offset;
15614 pub mod R {}
15615 pub mod W {}
15616 pub mod RW {
15617 #[doc = "Open Drain Disabled"]
15618 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
15619 #[doc = "Open Drain Enabled"]
15620 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
15621 }
15622 }
15623 #[doc = "Pull / Keep Enable Field"]
15624 pub mod PKE {
15625 pub const offset: u32 = 12;
15626 pub const mask: u32 = 0x01 << offset;
15627 pub mod R {}
15628 pub mod W {}
15629 pub mod RW {
15630 #[doc = "Pull/Keeper Disabled"]
15631 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
15632 #[doc = "Pull/Keeper Enabled"]
15633 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
15634 }
15635 }
15636 #[doc = "Pull / Keep Select Field"]
15637 pub mod PUE {
15638 pub const offset: u32 = 13;
15639 pub const mask: u32 = 0x01 << offset;
15640 pub mod R {}
15641 pub mod W {}
15642 pub mod RW {
15643 #[doc = "Keeper"]
15644 pub const PUE_0_KEEPER: u32 = 0;
15645 #[doc = "Pull"]
15646 pub const PUE_1_PULL: u32 = 0x01;
15647 }
15648 }
15649 #[doc = "Pull Up / Down Config. Field"]
15650 pub mod PUS {
15651 pub const offset: u32 = 14;
15652 pub const mask: u32 = 0x03 << offset;
15653 pub mod R {}
15654 pub mod W {}
15655 pub mod RW {
15656 #[doc = "100K Ohm Pull Down"]
15657 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
15658 #[doc = "47K Ohm Pull Up"]
15659 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
15660 #[doc = "100K Ohm Pull Up"]
15661 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
15662 #[doc = "22K Ohm Pull Up"]
15663 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
15664 }
15665 }
15666 #[doc = "Hyst. Enable Field"]
15667 pub mod HYS {
15668 pub const offset: u32 = 16;
15669 pub const mask: u32 = 0x01 << offset;
15670 pub mod R {}
15671 pub mod W {}
15672 pub mod RW {
15673 #[doc = "Hysteresis Disabled"]
15674 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
15675 #[doc = "Hysteresis Enabled"]
15676 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
15677 }
15678 }
15679}
15680#[doc = "SW_PAD_CTL_PAD_GPIO_B0_02 SW PAD Control Register"]
15681pub mod SW_PAD_CTL_PAD_GPIO_B0_02 {
15682 #[doc = "Slew Rate Field"]
15683 pub mod SRE {
15684 pub const offset: u32 = 0;
15685 pub const mask: u32 = 0x01 << offset;
15686 pub mod R {}
15687 pub mod W {}
15688 pub mod RW {
15689 #[doc = "Slow Slew Rate"]
15690 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
15691 #[doc = "Fast Slew Rate"]
15692 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
15693 }
15694 }
15695 #[doc = "Drive Strength Field"]
15696 pub mod DSE {
15697 pub const offset: u32 = 3;
15698 pub const mask: u32 = 0x07 << offset;
15699 pub mod R {}
15700 pub mod W {}
15701 pub mod RW {
15702 #[doc = "output driver disabled;"]
15703 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
15704 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
15705 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
15706 #[doc = "R0/2"]
15707 pub const DSE_2_R0_2: u32 = 0x02;
15708 #[doc = "R0/3"]
15709 pub const DSE_3_R0_3: u32 = 0x03;
15710 #[doc = "R0/4"]
15711 pub const DSE_4_R0_4: u32 = 0x04;
15712 #[doc = "R0/5"]
15713 pub const DSE_5_R0_5: u32 = 0x05;
15714 #[doc = "R0/6"]
15715 pub const DSE_6_R0_6: u32 = 0x06;
15716 #[doc = "R0/7"]
15717 pub const DSE_7_R0_7: u32 = 0x07;
15718 }
15719 }
15720 #[doc = "Speed Field"]
15721 pub mod SPEED {
15722 pub const offset: u32 = 6;
15723 pub const mask: u32 = 0x03 << offset;
15724 pub mod R {}
15725 pub mod W {}
15726 pub mod RW {
15727 #[doc = "low(50MHz)"]
15728 pub const SPEED_0_LOW_50MHZ: u32 = 0;
15729 #[doc = "medium(100MHz)"]
15730 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
15731 #[doc = "medium(100MHz)"]
15732 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
15733 #[doc = "max(200MHz)"]
15734 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
15735 }
15736 }
15737 #[doc = "Open Drain Enable Field"]
15738 pub mod ODE {
15739 pub const offset: u32 = 11;
15740 pub const mask: u32 = 0x01 << offset;
15741 pub mod R {}
15742 pub mod W {}
15743 pub mod RW {
15744 #[doc = "Open Drain Disabled"]
15745 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
15746 #[doc = "Open Drain Enabled"]
15747 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
15748 }
15749 }
15750 #[doc = "Pull / Keep Enable Field"]
15751 pub mod PKE {
15752 pub const offset: u32 = 12;
15753 pub const mask: u32 = 0x01 << offset;
15754 pub mod R {}
15755 pub mod W {}
15756 pub mod RW {
15757 #[doc = "Pull/Keeper Disabled"]
15758 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
15759 #[doc = "Pull/Keeper Enabled"]
15760 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
15761 }
15762 }
15763 #[doc = "Pull / Keep Select Field"]
15764 pub mod PUE {
15765 pub const offset: u32 = 13;
15766 pub const mask: u32 = 0x01 << offset;
15767 pub mod R {}
15768 pub mod W {}
15769 pub mod RW {
15770 #[doc = "Keeper"]
15771 pub const PUE_0_KEEPER: u32 = 0;
15772 #[doc = "Pull"]
15773 pub const PUE_1_PULL: u32 = 0x01;
15774 }
15775 }
15776 #[doc = "Pull Up / Down Config. Field"]
15777 pub mod PUS {
15778 pub const offset: u32 = 14;
15779 pub const mask: u32 = 0x03 << offset;
15780 pub mod R {}
15781 pub mod W {}
15782 pub mod RW {
15783 #[doc = "100K Ohm Pull Down"]
15784 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
15785 #[doc = "47K Ohm Pull Up"]
15786 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
15787 #[doc = "100K Ohm Pull Up"]
15788 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
15789 #[doc = "22K Ohm Pull Up"]
15790 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
15791 }
15792 }
15793 #[doc = "Hyst. Enable Field"]
15794 pub mod HYS {
15795 pub const offset: u32 = 16;
15796 pub const mask: u32 = 0x01 << offset;
15797 pub mod R {}
15798 pub mod W {}
15799 pub mod RW {
15800 #[doc = "Hysteresis Disabled"]
15801 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
15802 #[doc = "Hysteresis Enabled"]
15803 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
15804 }
15805 }
15806}
15807#[doc = "SW_PAD_CTL_PAD_GPIO_B0_03 SW PAD Control Register"]
15808pub mod SW_PAD_CTL_PAD_GPIO_B0_03 {
15809 #[doc = "Slew Rate Field"]
15810 pub mod SRE {
15811 pub const offset: u32 = 0;
15812 pub const mask: u32 = 0x01 << offset;
15813 pub mod R {}
15814 pub mod W {}
15815 pub mod RW {
15816 #[doc = "Slow Slew Rate"]
15817 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
15818 #[doc = "Fast Slew Rate"]
15819 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
15820 }
15821 }
15822 #[doc = "Drive Strength Field"]
15823 pub mod DSE {
15824 pub const offset: u32 = 3;
15825 pub const mask: u32 = 0x07 << offset;
15826 pub mod R {}
15827 pub mod W {}
15828 pub mod RW {
15829 #[doc = "output driver disabled;"]
15830 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
15831 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
15832 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
15833 #[doc = "R0/2"]
15834 pub const DSE_2_R0_2: u32 = 0x02;
15835 #[doc = "R0/3"]
15836 pub const DSE_3_R0_3: u32 = 0x03;
15837 #[doc = "R0/4"]
15838 pub const DSE_4_R0_4: u32 = 0x04;
15839 #[doc = "R0/5"]
15840 pub const DSE_5_R0_5: u32 = 0x05;
15841 #[doc = "R0/6"]
15842 pub const DSE_6_R0_6: u32 = 0x06;
15843 #[doc = "R0/7"]
15844 pub const DSE_7_R0_7: u32 = 0x07;
15845 }
15846 }
15847 #[doc = "Speed Field"]
15848 pub mod SPEED {
15849 pub const offset: u32 = 6;
15850 pub const mask: u32 = 0x03 << offset;
15851 pub mod R {}
15852 pub mod W {}
15853 pub mod RW {
15854 #[doc = "low(50MHz)"]
15855 pub const SPEED_0_LOW_50MHZ: u32 = 0;
15856 #[doc = "medium(100MHz)"]
15857 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
15858 #[doc = "medium(100MHz)"]
15859 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
15860 #[doc = "max(200MHz)"]
15861 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
15862 }
15863 }
15864 #[doc = "Open Drain Enable Field"]
15865 pub mod ODE {
15866 pub const offset: u32 = 11;
15867 pub const mask: u32 = 0x01 << offset;
15868 pub mod R {}
15869 pub mod W {}
15870 pub mod RW {
15871 #[doc = "Open Drain Disabled"]
15872 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
15873 #[doc = "Open Drain Enabled"]
15874 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
15875 }
15876 }
15877 #[doc = "Pull / Keep Enable Field"]
15878 pub mod PKE {
15879 pub const offset: u32 = 12;
15880 pub const mask: u32 = 0x01 << offset;
15881 pub mod R {}
15882 pub mod W {}
15883 pub mod RW {
15884 #[doc = "Pull/Keeper Disabled"]
15885 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
15886 #[doc = "Pull/Keeper Enabled"]
15887 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
15888 }
15889 }
15890 #[doc = "Pull / Keep Select Field"]
15891 pub mod PUE {
15892 pub const offset: u32 = 13;
15893 pub const mask: u32 = 0x01 << offset;
15894 pub mod R {}
15895 pub mod W {}
15896 pub mod RW {
15897 #[doc = "Keeper"]
15898 pub const PUE_0_KEEPER: u32 = 0;
15899 #[doc = "Pull"]
15900 pub const PUE_1_PULL: u32 = 0x01;
15901 }
15902 }
15903 #[doc = "Pull Up / Down Config. Field"]
15904 pub mod PUS {
15905 pub const offset: u32 = 14;
15906 pub const mask: u32 = 0x03 << offset;
15907 pub mod R {}
15908 pub mod W {}
15909 pub mod RW {
15910 #[doc = "100K Ohm Pull Down"]
15911 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
15912 #[doc = "47K Ohm Pull Up"]
15913 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
15914 #[doc = "100K Ohm Pull Up"]
15915 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
15916 #[doc = "22K Ohm Pull Up"]
15917 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
15918 }
15919 }
15920 #[doc = "Hyst. Enable Field"]
15921 pub mod HYS {
15922 pub const offset: u32 = 16;
15923 pub const mask: u32 = 0x01 << offset;
15924 pub mod R {}
15925 pub mod W {}
15926 pub mod RW {
15927 #[doc = "Hysteresis Disabled"]
15928 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
15929 #[doc = "Hysteresis Enabled"]
15930 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
15931 }
15932 }
15933}
15934#[doc = "SW_PAD_CTL_PAD_GPIO_B0_04 SW PAD Control Register"]
15935pub mod SW_PAD_CTL_PAD_GPIO_B0_04 {
15936 #[doc = "Slew Rate Field"]
15937 pub mod SRE {
15938 pub const offset: u32 = 0;
15939 pub const mask: u32 = 0x01 << offset;
15940 pub mod R {}
15941 pub mod W {}
15942 pub mod RW {
15943 #[doc = "Slow Slew Rate"]
15944 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
15945 #[doc = "Fast Slew Rate"]
15946 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
15947 }
15948 }
15949 #[doc = "Drive Strength Field"]
15950 pub mod DSE {
15951 pub const offset: u32 = 3;
15952 pub const mask: u32 = 0x07 << offset;
15953 pub mod R {}
15954 pub mod W {}
15955 pub mod RW {
15956 #[doc = "output driver disabled;"]
15957 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
15958 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
15959 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
15960 #[doc = "R0/2"]
15961 pub const DSE_2_R0_2: u32 = 0x02;
15962 #[doc = "R0/3"]
15963 pub const DSE_3_R0_3: u32 = 0x03;
15964 #[doc = "R0/4"]
15965 pub const DSE_4_R0_4: u32 = 0x04;
15966 #[doc = "R0/5"]
15967 pub const DSE_5_R0_5: u32 = 0x05;
15968 #[doc = "R0/6"]
15969 pub const DSE_6_R0_6: u32 = 0x06;
15970 #[doc = "R0/7"]
15971 pub const DSE_7_R0_7: u32 = 0x07;
15972 }
15973 }
15974 #[doc = "Speed Field"]
15975 pub mod SPEED {
15976 pub const offset: u32 = 6;
15977 pub const mask: u32 = 0x03 << offset;
15978 pub mod R {}
15979 pub mod W {}
15980 pub mod RW {
15981 #[doc = "low(50MHz)"]
15982 pub const SPEED_0_LOW_50MHZ: u32 = 0;
15983 #[doc = "medium(100MHz)"]
15984 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
15985 #[doc = "medium(100MHz)"]
15986 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
15987 #[doc = "max(200MHz)"]
15988 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
15989 }
15990 }
15991 #[doc = "Open Drain Enable Field"]
15992 pub mod ODE {
15993 pub const offset: u32 = 11;
15994 pub const mask: u32 = 0x01 << offset;
15995 pub mod R {}
15996 pub mod W {}
15997 pub mod RW {
15998 #[doc = "Open Drain Disabled"]
15999 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
16000 #[doc = "Open Drain Enabled"]
16001 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
16002 }
16003 }
16004 #[doc = "Pull / Keep Enable Field"]
16005 pub mod PKE {
16006 pub const offset: u32 = 12;
16007 pub const mask: u32 = 0x01 << offset;
16008 pub mod R {}
16009 pub mod W {}
16010 pub mod RW {
16011 #[doc = "Pull/Keeper Disabled"]
16012 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
16013 #[doc = "Pull/Keeper Enabled"]
16014 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
16015 }
16016 }
16017 #[doc = "Pull / Keep Select Field"]
16018 pub mod PUE {
16019 pub const offset: u32 = 13;
16020 pub const mask: u32 = 0x01 << offset;
16021 pub mod R {}
16022 pub mod W {}
16023 pub mod RW {
16024 #[doc = "Keeper"]
16025 pub const PUE_0_KEEPER: u32 = 0;
16026 #[doc = "Pull"]
16027 pub const PUE_1_PULL: u32 = 0x01;
16028 }
16029 }
16030 #[doc = "Pull Up / Down Config. Field"]
16031 pub mod PUS {
16032 pub const offset: u32 = 14;
16033 pub const mask: u32 = 0x03 << offset;
16034 pub mod R {}
16035 pub mod W {}
16036 pub mod RW {
16037 #[doc = "100K Ohm Pull Down"]
16038 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
16039 #[doc = "47K Ohm Pull Up"]
16040 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
16041 #[doc = "100K Ohm Pull Up"]
16042 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
16043 #[doc = "22K Ohm Pull Up"]
16044 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
16045 }
16046 }
16047 #[doc = "Hyst. Enable Field"]
16048 pub mod HYS {
16049 pub const offset: u32 = 16;
16050 pub const mask: u32 = 0x01 << offset;
16051 pub mod R {}
16052 pub mod W {}
16053 pub mod RW {
16054 #[doc = "Hysteresis Disabled"]
16055 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
16056 #[doc = "Hysteresis Enabled"]
16057 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
16058 }
16059 }
16060}
16061#[doc = "SW_PAD_CTL_PAD_GPIO_B0_05 SW PAD Control Register"]
16062pub mod SW_PAD_CTL_PAD_GPIO_B0_05 {
16063 #[doc = "Slew Rate Field"]
16064 pub mod SRE {
16065 pub const offset: u32 = 0;
16066 pub const mask: u32 = 0x01 << offset;
16067 pub mod R {}
16068 pub mod W {}
16069 pub mod RW {
16070 #[doc = "Slow Slew Rate"]
16071 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
16072 #[doc = "Fast Slew Rate"]
16073 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
16074 }
16075 }
16076 #[doc = "Drive Strength Field"]
16077 pub mod DSE {
16078 pub const offset: u32 = 3;
16079 pub const mask: u32 = 0x07 << offset;
16080 pub mod R {}
16081 pub mod W {}
16082 pub mod RW {
16083 #[doc = "output driver disabled;"]
16084 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
16085 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
16086 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
16087 #[doc = "R0/2"]
16088 pub const DSE_2_R0_2: u32 = 0x02;
16089 #[doc = "R0/3"]
16090 pub const DSE_3_R0_3: u32 = 0x03;
16091 #[doc = "R0/4"]
16092 pub const DSE_4_R0_4: u32 = 0x04;
16093 #[doc = "R0/5"]
16094 pub const DSE_5_R0_5: u32 = 0x05;
16095 #[doc = "R0/6"]
16096 pub const DSE_6_R0_6: u32 = 0x06;
16097 #[doc = "R0/7"]
16098 pub const DSE_7_R0_7: u32 = 0x07;
16099 }
16100 }
16101 #[doc = "Speed Field"]
16102 pub mod SPEED {
16103 pub const offset: u32 = 6;
16104 pub const mask: u32 = 0x03 << offset;
16105 pub mod R {}
16106 pub mod W {}
16107 pub mod RW {
16108 #[doc = "low(50MHz)"]
16109 pub const SPEED_0_LOW_50MHZ: u32 = 0;
16110 #[doc = "medium(100MHz)"]
16111 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
16112 #[doc = "medium(100MHz)"]
16113 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
16114 #[doc = "max(200MHz)"]
16115 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
16116 }
16117 }
16118 #[doc = "Open Drain Enable Field"]
16119 pub mod ODE {
16120 pub const offset: u32 = 11;
16121 pub const mask: u32 = 0x01 << offset;
16122 pub mod R {}
16123 pub mod W {}
16124 pub mod RW {
16125 #[doc = "Open Drain Disabled"]
16126 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
16127 #[doc = "Open Drain Enabled"]
16128 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
16129 }
16130 }
16131 #[doc = "Pull / Keep Enable Field"]
16132 pub mod PKE {
16133 pub const offset: u32 = 12;
16134 pub const mask: u32 = 0x01 << offset;
16135 pub mod R {}
16136 pub mod W {}
16137 pub mod RW {
16138 #[doc = "Pull/Keeper Disabled"]
16139 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
16140 #[doc = "Pull/Keeper Enabled"]
16141 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
16142 }
16143 }
16144 #[doc = "Pull / Keep Select Field"]
16145 pub mod PUE {
16146 pub const offset: u32 = 13;
16147 pub const mask: u32 = 0x01 << offset;
16148 pub mod R {}
16149 pub mod W {}
16150 pub mod RW {
16151 #[doc = "Keeper"]
16152 pub const PUE_0_KEEPER: u32 = 0;
16153 #[doc = "Pull"]
16154 pub const PUE_1_PULL: u32 = 0x01;
16155 }
16156 }
16157 #[doc = "Pull Up / Down Config. Field"]
16158 pub mod PUS {
16159 pub const offset: u32 = 14;
16160 pub const mask: u32 = 0x03 << offset;
16161 pub mod R {}
16162 pub mod W {}
16163 pub mod RW {
16164 #[doc = "100K Ohm Pull Down"]
16165 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
16166 #[doc = "47K Ohm Pull Up"]
16167 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
16168 #[doc = "100K Ohm Pull Up"]
16169 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
16170 #[doc = "22K Ohm Pull Up"]
16171 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
16172 }
16173 }
16174 #[doc = "Hyst. Enable Field"]
16175 pub mod HYS {
16176 pub const offset: u32 = 16;
16177 pub const mask: u32 = 0x01 << offset;
16178 pub mod R {}
16179 pub mod W {}
16180 pub mod RW {
16181 #[doc = "Hysteresis Disabled"]
16182 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
16183 #[doc = "Hysteresis Enabled"]
16184 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
16185 }
16186 }
16187}
16188#[doc = "SW_PAD_CTL_PAD_GPIO_B0_06 SW PAD Control Register"]
16189pub mod SW_PAD_CTL_PAD_GPIO_B0_06 {
16190 #[doc = "Slew Rate Field"]
16191 pub mod SRE {
16192 pub const offset: u32 = 0;
16193 pub const mask: u32 = 0x01 << offset;
16194 pub mod R {}
16195 pub mod W {}
16196 pub mod RW {
16197 #[doc = "Slow Slew Rate"]
16198 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
16199 #[doc = "Fast Slew Rate"]
16200 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
16201 }
16202 }
16203 #[doc = "Drive Strength Field"]
16204 pub mod DSE {
16205 pub const offset: u32 = 3;
16206 pub const mask: u32 = 0x07 << offset;
16207 pub mod R {}
16208 pub mod W {}
16209 pub mod RW {
16210 #[doc = "output driver disabled;"]
16211 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
16212 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
16213 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
16214 #[doc = "R0/2"]
16215 pub const DSE_2_R0_2: u32 = 0x02;
16216 #[doc = "R0/3"]
16217 pub const DSE_3_R0_3: u32 = 0x03;
16218 #[doc = "R0/4"]
16219 pub const DSE_4_R0_4: u32 = 0x04;
16220 #[doc = "R0/5"]
16221 pub const DSE_5_R0_5: u32 = 0x05;
16222 #[doc = "R0/6"]
16223 pub const DSE_6_R0_6: u32 = 0x06;
16224 #[doc = "R0/7"]
16225 pub const DSE_7_R0_7: u32 = 0x07;
16226 }
16227 }
16228 #[doc = "Speed Field"]
16229 pub mod SPEED {
16230 pub const offset: u32 = 6;
16231 pub const mask: u32 = 0x03 << offset;
16232 pub mod R {}
16233 pub mod W {}
16234 pub mod RW {
16235 #[doc = "low(50MHz)"]
16236 pub const SPEED_0_LOW_50MHZ: u32 = 0;
16237 #[doc = "medium(100MHz)"]
16238 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
16239 #[doc = "medium(100MHz)"]
16240 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
16241 #[doc = "max(200MHz)"]
16242 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
16243 }
16244 }
16245 #[doc = "Open Drain Enable Field"]
16246 pub mod ODE {
16247 pub const offset: u32 = 11;
16248 pub const mask: u32 = 0x01 << offset;
16249 pub mod R {}
16250 pub mod W {}
16251 pub mod RW {
16252 #[doc = "Open Drain Disabled"]
16253 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
16254 #[doc = "Open Drain Enabled"]
16255 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
16256 }
16257 }
16258 #[doc = "Pull / Keep Enable Field"]
16259 pub mod PKE {
16260 pub const offset: u32 = 12;
16261 pub const mask: u32 = 0x01 << offset;
16262 pub mod R {}
16263 pub mod W {}
16264 pub mod RW {
16265 #[doc = "Pull/Keeper Disabled"]
16266 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
16267 #[doc = "Pull/Keeper Enabled"]
16268 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
16269 }
16270 }
16271 #[doc = "Pull / Keep Select Field"]
16272 pub mod PUE {
16273 pub const offset: u32 = 13;
16274 pub const mask: u32 = 0x01 << offset;
16275 pub mod R {}
16276 pub mod W {}
16277 pub mod RW {
16278 #[doc = "Keeper"]
16279 pub const PUE_0_KEEPER: u32 = 0;
16280 #[doc = "Pull"]
16281 pub const PUE_1_PULL: u32 = 0x01;
16282 }
16283 }
16284 #[doc = "Pull Up / Down Config. Field"]
16285 pub mod PUS {
16286 pub const offset: u32 = 14;
16287 pub const mask: u32 = 0x03 << offset;
16288 pub mod R {}
16289 pub mod W {}
16290 pub mod RW {
16291 #[doc = "100K Ohm Pull Down"]
16292 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
16293 #[doc = "47K Ohm Pull Up"]
16294 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
16295 #[doc = "100K Ohm Pull Up"]
16296 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
16297 #[doc = "22K Ohm Pull Up"]
16298 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
16299 }
16300 }
16301 #[doc = "Hyst. Enable Field"]
16302 pub mod HYS {
16303 pub const offset: u32 = 16;
16304 pub const mask: u32 = 0x01 << offset;
16305 pub mod R {}
16306 pub mod W {}
16307 pub mod RW {
16308 #[doc = "Hysteresis Disabled"]
16309 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
16310 #[doc = "Hysteresis Enabled"]
16311 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
16312 }
16313 }
16314}
16315#[doc = "SW_PAD_CTL_PAD_GPIO_B0_07 SW PAD Control Register"]
16316pub mod SW_PAD_CTL_PAD_GPIO_B0_07 {
16317 #[doc = "Slew Rate Field"]
16318 pub mod SRE {
16319 pub const offset: u32 = 0;
16320 pub const mask: u32 = 0x01 << offset;
16321 pub mod R {}
16322 pub mod W {}
16323 pub mod RW {
16324 #[doc = "Slow Slew Rate"]
16325 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
16326 #[doc = "Fast Slew Rate"]
16327 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
16328 }
16329 }
16330 #[doc = "Drive Strength Field"]
16331 pub mod DSE {
16332 pub const offset: u32 = 3;
16333 pub const mask: u32 = 0x07 << offset;
16334 pub mod R {}
16335 pub mod W {}
16336 pub mod RW {
16337 #[doc = "output driver disabled;"]
16338 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
16339 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
16340 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
16341 #[doc = "R0/2"]
16342 pub const DSE_2_R0_2: u32 = 0x02;
16343 #[doc = "R0/3"]
16344 pub const DSE_3_R0_3: u32 = 0x03;
16345 #[doc = "R0/4"]
16346 pub const DSE_4_R0_4: u32 = 0x04;
16347 #[doc = "R0/5"]
16348 pub const DSE_5_R0_5: u32 = 0x05;
16349 #[doc = "R0/6"]
16350 pub const DSE_6_R0_6: u32 = 0x06;
16351 #[doc = "R0/7"]
16352 pub const DSE_7_R0_7: u32 = 0x07;
16353 }
16354 }
16355 #[doc = "Speed Field"]
16356 pub mod SPEED {
16357 pub const offset: u32 = 6;
16358 pub const mask: u32 = 0x03 << offset;
16359 pub mod R {}
16360 pub mod W {}
16361 pub mod RW {
16362 #[doc = "low(50MHz)"]
16363 pub const SPEED_0_LOW_50MHZ: u32 = 0;
16364 #[doc = "medium(100MHz)"]
16365 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
16366 #[doc = "medium(100MHz)"]
16367 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
16368 #[doc = "max(200MHz)"]
16369 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
16370 }
16371 }
16372 #[doc = "Open Drain Enable Field"]
16373 pub mod ODE {
16374 pub const offset: u32 = 11;
16375 pub const mask: u32 = 0x01 << offset;
16376 pub mod R {}
16377 pub mod W {}
16378 pub mod RW {
16379 #[doc = "Open Drain Disabled"]
16380 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
16381 #[doc = "Open Drain Enabled"]
16382 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
16383 }
16384 }
16385 #[doc = "Pull / Keep Enable Field"]
16386 pub mod PKE {
16387 pub const offset: u32 = 12;
16388 pub const mask: u32 = 0x01 << offset;
16389 pub mod R {}
16390 pub mod W {}
16391 pub mod RW {
16392 #[doc = "Pull/Keeper Disabled"]
16393 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
16394 #[doc = "Pull/Keeper Enabled"]
16395 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
16396 }
16397 }
16398 #[doc = "Pull / Keep Select Field"]
16399 pub mod PUE {
16400 pub const offset: u32 = 13;
16401 pub const mask: u32 = 0x01 << offset;
16402 pub mod R {}
16403 pub mod W {}
16404 pub mod RW {
16405 #[doc = "Keeper"]
16406 pub const PUE_0_KEEPER: u32 = 0;
16407 #[doc = "Pull"]
16408 pub const PUE_1_PULL: u32 = 0x01;
16409 }
16410 }
16411 #[doc = "Pull Up / Down Config. Field"]
16412 pub mod PUS {
16413 pub const offset: u32 = 14;
16414 pub const mask: u32 = 0x03 << offset;
16415 pub mod R {}
16416 pub mod W {}
16417 pub mod RW {
16418 #[doc = "100K Ohm Pull Down"]
16419 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
16420 #[doc = "47K Ohm Pull Up"]
16421 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
16422 #[doc = "100K Ohm Pull Up"]
16423 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
16424 #[doc = "22K Ohm Pull Up"]
16425 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
16426 }
16427 }
16428 #[doc = "Hyst. Enable Field"]
16429 pub mod HYS {
16430 pub const offset: u32 = 16;
16431 pub const mask: u32 = 0x01 << offset;
16432 pub mod R {}
16433 pub mod W {}
16434 pub mod RW {
16435 #[doc = "Hysteresis Disabled"]
16436 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
16437 #[doc = "Hysteresis Enabled"]
16438 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
16439 }
16440 }
16441}
16442#[doc = "SW_PAD_CTL_PAD_GPIO_B0_08 SW PAD Control Register"]
16443pub mod SW_PAD_CTL_PAD_GPIO_B0_08 {
16444 #[doc = "Slew Rate Field"]
16445 pub mod SRE {
16446 pub const offset: u32 = 0;
16447 pub const mask: u32 = 0x01 << offset;
16448 pub mod R {}
16449 pub mod W {}
16450 pub mod RW {
16451 #[doc = "Slow Slew Rate"]
16452 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
16453 #[doc = "Fast Slew Rate"]
16454 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
16455 }
16456 }
16457 #[doc = "Drive Strength Field"]
16458 pub mod DSE {
16459 pub const offset: u32 = 3;
16460 pub const mask: u32 = 0x07 << offset;
16461 pub mod R {}
16462 pub mod W {}
16463 pub mod RW {
16464 #[doc = "output driver disabled;"]
16465 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
16466 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
16467 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
16468 #[doc = "R0/2"]
16469 pub const DSE_2_R0_2: u32 = 0x02;
16470 #[doc = "R0/3"]
16471 pub const DSE_3_R0_3: u32 = 0x03;
16472 #[doc = "R0/4"]
16473 pub const DSE_4_R0_4: u32 = 0x04;
16474 #[doc = "R0/5"]
16475 pub const DSE_5_R0_5: u32 = 0x05;
16476 #[doc = "R0/6"]
16477 pub const DSE_6_R0_6: u32 = 0x06;
16478 #[doc = "R0/7"]
16479 pub const DSE_7_R0_7: u32 = 0x07;
16480 }
16481 }
16482 #[doc = "Speed Field"]
16483 pub mod SPEED {
16484 pub const offset: u32 = 6;
16485 pub const mask: u32 = 0x03 << offset;
16486 pub mod R {}
16487 pub mod W {}
16488 pub mod RW {
16489 #[doc = "low(50MHz)"]
16490 pub const SPEED_0_LOW_50MHZ: u32 = 0;
16491 #[doc = "medium(100MHz)"]
16492 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
16493 #[doc = "medium(100MHz)"]
16494 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
16495 #[doc = "max(200MHz)"]
16496 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
16497 }
16498 }
16499 #[doc = "Open Drain Enable Field"]
16500 pub mod ODE {
16501 pub const offset: u32 = 11;
16502 pub const mask: u32 = 0x01 << offset;
16503 pub mod R {}
16504 pub mod W {}
16505 pub mod RW {
16506 #[doc = "Open Drain Disabled"]
16507 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
16508 #[doc = "Open Drain Enabled"]
16509 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
16510 }
16511 }
16512 #[doc = "Pull / Keep Enable Field"]
16513 pub mod PKE {
16514 pub const offset: u32 = 12;
16515 pub const mask: u32 = 0x01 << offset;
16516 pub mod R {}
16517 pub mod W {}
16518 pub mod RW {
16519 #[doc = "Pull/Keeper Disabled"]
16520 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
16521 #[doc = "Pull/Keeper Enabled"]
16522 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
16523 }
16524 }
16525 #[doc = "Pull / Keep Select Field"]
16526 pub mod PUE {
16527 pub const offset: u32 = 13;
16528 pub const mask: u32 = 0x01 << offset;
16529 pub mod R {}
16530 pub mod W {}
16531 pub mod RW {
16532 #[doc = "Keeper"]
16533 pub const PUE_0_KEEPER: u32 = 0;
16534 #[doc = "Pull"]
16535 pub const PUE_1_PULL: u32 = 0x01;
16536 }
16537 }
16538 #[doc = "Pull Up / Down Config. Field"]
16539 pub mod PUS {
16540 pub const offset: u32 = 14;
16541 pub const mask: u32 = 0x03 << offset;
16542 pub mod R {}
16543 pub mod W {}
16544 pub mod RW {
16545 #[doc = "100K Ohm Pull Down"]
16546 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
16547 #[doc = "47K Ohm Pull Up"]
16548 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
16549 #[doc = "100K Ohm Pull Up"]
16550 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
16551 #[doc = "22K Ohm Pull Up"]
16552 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
16553 }
16554 }
16555 #[doc = "Hyst. Enable Field"]
16556 pub mod HYS {
16557 pub const offset: u32 = 16;
16558 pub const mask: u32 = 0x01 << offset;
16559 pub mod R {}
16560 pub mod W {}
16561 pub mod RW {
16562 #[doc = "Hysteresis Disabled"]
16563 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
16564 #[doc = "Hysteresis Enabled"]
16565 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
16566 }
16567 }
16568}
16569#[doc = "SW_PAD_CTL_PAD_GPIO_B0_09 SW PAD Control Register"]
16570pub mod SW_PAD_CTL_PAD_GPIO_B0_09 {
16571 #[doc = "Slew Rate Field"]
16572 pub mod SRE {
16573 pub const offset: u32 = 0;
16574 pub const mask: u32 = 0x01 << offset;
16575 pub mod R {}
16576 pub mod W {}
16577 pub mod RW {
16578 #[doc = "Slow Slew Rate"]
16579 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
16580 #[doc = "Fast Slew Rate"]
16581 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
16582 }
16583 }
16584 #[doc = "Drive Strength Field"]
16585 pub mod DSE {
16586 pub const offset: u32 = 3;
16587 pub const mask: u32 = 0x07 << offset;
16588 pub mod R {}
16589 pub mod W {}
16590 pub mod RW {
16591 #[doc = "output driver disabled;"]
16592 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
16593 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
16594 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
16595 #[doc = "R0/2"]
16596 pub const DSE_2_R0_2: u32 = 0x02;
16597 #[doc = "R0/3"]
16598 pub const DSE_3_R0_3: u32 = 0x03;
16599 #[doc = "R0/4"]
16600 pub const DSE_4_R0_4: u32 = 0x04;
16601 #[doc = "R0/5"]
16602 pub const DSE_5_R0_5: u32 = 0x05;
16603 #[doc = "R0/6"]
16604 pub const DSE_6_R0_6: u32 = 0x06;
16605 #[doc = "R0/7"]
16606 pub const DSE_7_R0_7: u32 = 0x07;
16607 }
16608 }
16609 #[doc = "Speed Field"]
16610 pub mod SPEED {
16611 pub const offset: u32 = 6;
16612 pub const mask: u32 = 0x03 << offset;
16613 pub mod R {}
16614 pub mod W {}
16615 pub mod RW {
16616 #[doc = "low(50MHz)"]
16617 pub const SPEED_0_LOW_50MHZ: u32 = 0;
16618 #[doc = "medium(100MHz)"]
16619 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
16620 #[doc = "medium(100MHz)"]
16621 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
16622 #[doc = "max(200MHz)"]
16623 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
16624 }
16625 }
16626 #[doc = "Open Drain Enable Field"]
16627 pub mod ODE {
16628 pub const offset: u32 = 11;
16629 pub const mask: u32 = 0x01 << offset;
16630 pub mod R {}
16631 pub mod W {}
16632 pub mod RW {
16633 #[doc = "Open Drain Disabled"]
16634 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
16635 #[doc = "Open Drain Enabled"]
16636 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
16637 }
16638 }
16639 #[doc = "Pull / Keep Enable Field"]
16640 pub mod PKE {
16641 pub const offset: u32 = 12;
16642 pub const mask: u32 = 0x01 << offset;
16643 pub mod R {}
16644 pub mod W {}
16645 pub mod RW {
16646 #[doc = "Pull/Keeper Disabled"]
16647 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
16648 #[doc = "Pull/Keeper Enabled"]
16649 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
16650 }
16651 }
16652 #[doc = "Pull / Keep Select Field"]
16653 pub mod PUE {
16654 pub const offset: u32 = 13;
16655 pub const mask: u32 = 0x01 << offset;
16656 pub mod R {}
16657 pub mod W {}
16658 pub mod RW {
16659 #[doc = "Keeper"]
16660 pub const PUE_0_KEEPER: u32 = 0;
16661 #[doc = "Pull"]
16662 pub const PUE_1_PULL: u32 = 0x01;
16663 }
16664 }
16665 #[doc = "Pull Up / Down Config. Field"]
16666 pub mod PUS {
16667 pub const offset: u32 = 14;
16668 pub const mask: u32 = 0x03 << offset;
16669 pub mod R {}
16670 pub mod W {}
16671 pub mod RW {
16672 #[doc = "100K Ohm Pull Down"]
16673 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
16674 #[doc = "47K Ohm Pull Up"]
16675 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
16676 #[doc = "100K Ohm Pull Up"]
16677 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
16678 #[doc = "22K Ohm Pull Up"]
16679 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
16680 }
16681 }
16682 #[doc = "Hyst. Enable Field"]
16683 pub mod HYS {
16684 pub const offset: u32 = 16;
16685 pub const mask: u32 = 0x01 << offset;
16686 pub mod R {}
16687 pub mod W {}
16688 pub mod RW {
16689 #[doc = "Hysteresis Disabled"]
16690 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
16691 #[doc = "Hysteresis Enabled"]
16692 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
16693 }
16694 }
16695}
16696#[doc = "SW_PAD_CTL_PAD_GPIO_B0_10 SW PAD Control Register"]
16697pub mod SW_PAD_CTL_PAD_GPIO_B0_10 {
16698 #[doc = "Slew Rate Field"]
16699 pub mod SRE {
16700 pub const offset: u32 = 0;
16701 pub const mask: u32 = 0x01 << offset;
16702 pub mod R {}
16703 pub mod W {}
16704 pub mod RW {
16705 #[doc = "Slow Slew Rate"]
16706 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
16707 #[doc = "Fast Slew Rate"]
16708 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
16709 }
16710 }
16711 #[doc = "Drive Strength Field"]
16712 pub mod DSE {
16713 pub const offset: u32 = 3;
16714 pub const mask: u32 = 0x07 << offset;
16715 pub mod R {}
16716 pub mod W {}
16717 pub mod RW {
16718 #[doc = "output driver disabled;"]
16719 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
16720 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
16721 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
16722 #[doc = "R0/2"]
16723 pub const DSE_2_R0_2: u32 = 0x02;
16724 #[doc = "R0/3"]
16725 pub const DSE_3_R0_3: u32 = 0x03;
16726 #[doc = "R0/4"]
16727 pub const DSE_4_R0_4: u32 = 0x04;
16728 #[doc = "R0/5"]
16729 pub const DSE_5_R0_5: u32 = 0x05;
16730 #[doc = "R0/6"]
16731 pub const DSE_6_R0_6: u32 = 0x06;
16732 #[doc = "R0/7"]
16733 pub const DSE_7_R0_7: u32 = 0x07;
16734 }
16735 }
16736 #[doc = "Speed Field"]
16737 pub mod SPEED {
16738 pub const offset: u32 = 6;
16739 pub const mask: u32 = 0x03 << offset;
16740 pub mod R {}
16741 pub mod W {}
16742 pub mod RW {
16743 #[doc = "low(50MHz)"]
16744 pub const SPEED_0_LOW_50MHZ: u32 = 0;
16745 #[doc = "medium(100MHz)"]
16746 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
16747 #[doc = "medium(100MHz)"]
16748 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
16749 #[doc = "max(200MHz)"]
16750 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
16751 }
16752 }
16753 #[doc = "Open Drain Enable Field"]
16754 pub mod ODE {
16755 pub const offset: u32 = 11;
16756 pub const mask: u32 = 0x01 << offset;
16757 pub mod R {}
16758 pub mod W {}
16759 pub mod RW {
16760 #[doc = "Open Drain Disabled"]
16761 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
16762 #[doc = "Open Drain Enabled"]
16763 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
16764 }
16765 }
16766 #[doc = "Pull / Keep Enable Field"]
16767 pub mod PKE {
16768 pub const offset: u32 = 12;
16769 pub const mask: u32 = 0x01 << offset;
16770 pub mod R {}
16771 pub mod W {}
16772 pub mod RW {
16773 #[doc = "Pull/Keeper Disabled"]
16774 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
16775 #[doc = "Pull/Keeper Enabled"]
16776 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
16777 }
16778 }
16779 #[doc = "Pull / Keep Select Field"]
16780 pub mod PUE {
16781 pub const offset: u32 = 13;
16782 pub const mask: u32 = 0x01 << offset;
16783 pub mod R {}
16784 pub mod W {}
16785 pub mod RW {
16786 #[doc = "Keeper"]
16787 pub const PUE_0_KEEPER: u32 = 0;
16788 #[doc = "Pull"]
16789 pub const PUE_1_PULL: u32 = 0x01;
16790 }
16791 }
16792 #[doc = "Pull Up / Down Config. Field"]
16793 pub mod PUS {
16794 pub const offset: u32 = 14;
16795 pub const mask: u32 = 0x03 << offset;
16796 pub mod R {}
16797 pub mod W {}
16798 pub mod RW {
16799 #[doc = "100K Ohm Pull Down"]
16800 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
16801 #[doc = "47K Ohm Pull Up"]
16802 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
16803 #[doc = "100K Ohm Pull Up"]
16804 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
16805 #[doc = "22K Ohm Pull Up"]
16806 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
16807 }
16808 }
16809 #[doc = "Hyst. Enable Field"]
16810 pub mod HYS {
16811 pub const offset: u32 = 16;
16812 pub const mask: u32 = 0x01 << offset;
16813 pub mod R {}
16814 pub mod W {}
16815 pub mod RW {
16816 #[doc = "Hysteresis Disabled"]
16817 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
16818 #[doc = "Hysteresis Enabled"]
16819 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
16820 }
16821 }
16822}
16823#[doc = "SW_PAD_CTL_PAD_GPIO_B0_11 SW PAD Control Register"]
16824pub mod SW_PAD_CTL_PAD_GPIO_B0_11 {
16825 #[doc = "Slew Rate Field"]
16826 pub mod SRE {
16827 pub const offset: u32 = 0;
16828 pub const mask: u32 = 0x01 << offset;
16829 pub mod R {}
16830 pub mod W {}
16831 pub mod RW {
16832 #[doc = "Slow Slew Rate"]
16833 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
16834 #[doc = "Fast Slew Rate"]
16835 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
16836 }
16837 }
16838 #[doc = "Drive Strength Field"]
16839 pub mod DSE {
16840 pub const offset: u32 = 3;
16841 pub const mask: u32 = 0x07 << offset;
16842 pub mod R {}
16843 pub mod W {}
16844 pub mod RW {
16845 #[doc = "output driver disabled;"]
16846 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
16847 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
16848 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
16849 #[doc = "R0/2"]
16850 pub const DSE_2_R0_2: u32 = 0x02;
16851 #[doc = "R0/3"]
16852 pub const DSE_3_R0_3: u32 = 0x03;
16853 #[doc = "R0/4"]
16854 pub const DSE_4_R0_4: u32 = 0x04;
16855 #[doc = "R0/5"]
16856 pub const DSE_5_R0_5: u32 = 0x05;
16857 #[doc = "R0/6"]
16858 pub const DSE_6_R0_6: u32 = 0x06;
16859 #[doc = "R0/7"]
16860 pub const DSE_7_R0_7: u32 = 0x07;
16861 }
16862 }
16863 #[doc = "Speed Field"]
16864 pub mod SPEED {
16865 pub const offset: u32 = 6;
16866 pub const mask: u32 = 0x03 << offset;
16867 pub mod R {}
16868 pub mod W {}
16869 pub mod RW {
16870 #[doc = "low(50MHz)"]
16871 pub const SPEED_0_LOW_50MHZ: u32 = 0;
16872 #[doc = "medium(100MHz)"]
16873 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
16874 #[doc = "medium(100MHz)"]
16875 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
16876 #[doc = "max(200MHz)"]
16877 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
16878 }
16879 }
16880 #[doc = "Open Drain Enable Field"]
16881 pub mod ODE {
16882 pub const offset: u32 = 11;
16883 pub const mask: u32 = 0x01 << offset;
16884 pub mod R {}
16885 pub mod W {}
16886 pub mod RW {
16887 #[doc = "Open Drain Disabled"]
16888 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
16889 #[doc = "Open Drain Enabled"]
16890 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
16891 }
16892 }
16893 #[doc = "Pull / Keep Enable Field"]
16894 pub mod PKE {
16895 pub const offset: u32 = 12;
16896 pub const mask: u32 = 0x01 << offset;
16897 pub mod R {}
16898 pub mod W {}
16899 pub mod RW {
16900 #[doc = "Pull/Keeper Disabled"]
16901 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
16902 #[doc = "Pull/Keeper Enabled"]
16903 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
16904 }
16905 }
16906 #[doc = "Pull / Keep Select Field"]
16907 pub mod PUE {
16908 pub const offset: u32 = 13;
16909 pub const mask: u32 = 0x01 << offset;
16910 pub mod R {}
16911 pub mod W {}
16912 pub mod RW {
16913 #[doc = "Keeper"]
16914 pub const PUE_0_KEEPER: u32 = 0;
16915 #[doc = "Pull"]
16916 pub const PUE_1_PULL: u32 = 0x01;
16917 }
16918 }
16919 #[doc = "Pull Up / Down Config. Field"]
16920 pub mod PUS {
16921 pub const offset: u32 = 14;
16922 pub const mask: u32 = 0x03 << offset;
16923 pub mod R {}
16924 pub mod W {}
16925 pub mod RW {
16926 #[doc = "100K Ohm Pull Down"]
16927 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
16928 #[doc = "47K Ohm Pull Up"]
16929 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
16930 #[doc = "100K Ohm Pull Up"]
16931 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
16932 #[doc = "22K Ohm Pull Up"]
16933 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
16934 }
16935 }
16936 #[doc = "Hyst. Enable Field"]
16937 pub mod HYS {
16938 pub const offset: u32 = 16;
16939 pub const mask: u32 = 0x01 << offset;
16940 pub mod R {}
16941 pub mod W {}
16942 pub mod RW {
16943 #[doc = "Hysteresis Disabled"]
16944 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
16945 #[doc = "Hysteresis Enabled"]
16946 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
16947 }
16948 }
16949}
16950#[doc = "SW_PAD_CTL_PAD_GPIO_B0_12 SW PAD Control Register"]
16951pub mod SW_PAD_CTL_PAD_GPIO_B0_12 {
16952 #[doc = "Slew Rate Field"]
16953 pub mod SRE {
16954 pub const offset: u32 = 0;
16955 pub const mask: u32 = 0x01 << offset;
16956 pub mod R {}
16957 pub mod W {}
16958 pub mod RW {
16959 #[doc = "Slow Slew Rate"]
16960 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
16961 #[doc = "Fast Slew Rate"]
16962 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
16963 }
16964 }
16965 #[doc = "Drive Strength Field"]
16966 pub mod DSE {
16967 pub const offset: u32 = 3;
16968 pub const mask: u32 = 0x07 << offset;
16969 pub mod R {}
16970 pub mod W {}
16971 pub mod RW {
16972 #[doc = "output driver disabled;"]
16973 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
16974 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
16975 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
16976 #[doc = "R0/2"]
16977 pub const DSE_2_R0_2: u32 = 0x02;
16978 #[doc = "R0/3"]
16979 pub const DSE_3_R0_3: u32 = 0x03;
16980 #[doc = "R0/4"]
16981 pub const DSE_4_R0_4: u32 = 0x04;
16982 #[doc = "R0/5"]
16983 pub const DSE_5_R0_5: u32 = 0x05;
16984 #[doc = "R0/6"]
16985 pub const DSE_6_R0_6: u32 = 0x06;
16986 #[doc = "R0/7"]
16987 pub const DSE_7_R0_7: u32 = 0x07;
16988 }
16989 }
16990 #[doc = "Speed Field"]
16991 pub mod SPEED {
16992 pub const offset: u32 = 6;
16993 pub const mask: u32 = 0x03 << offset;
16994 pub mod R {}
16995 pub mod W {}
16996 pub mod RW {
16997 #[doc = "low(50MHz)"]
16998 pub const SPEED_0_LOW_50MHZ: u32 = 0;
16999 #[doc = "medium(100MHz)"]
17000 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
17001 #[doc = "medium(100MHz)"]
17002 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
17003 #[doc = "max(200MHz)"]
17004 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
17005 }
17006 }
17007 #[doc = "Open Drain Enable Field"]
17008 pub mod ODE {
17009 pub const offset: u32 = 11;
17010 pub const mask: u32 = 0x01 << offset;
17011 pub mod R {}
17012 pub mod W {}
17013 pub mod RW {
17014 #[doc = "Open Drain Disabled"]
17015 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
17016 #[doc = "Open Drain Enabled"]
17017 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
17018 }
17019 }
17020 #[doc = "Pull / Keep Enable Field"]
17021 pub mod PKE {
17022 pub const offset: u32 = 12;
17023 pub const mask: u32 = 0x01 << offset;
17024 pub mod R {}
17025 pub mod W {}
17026 pub mod RW {
17027 #[doc = "Pull/Keeper Disabled"]
17028 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
17029 #[doc = "Pull/Keeper Enabled"]
17030 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
17031 }
17032 }
17033 #[doc = "Pull / Keep Select Field"]
17034 pub mod PUE {
17035 pub const offset: u32 = 13;
17036 pub const mask: u32 = 0x01 << offset;
17037 pub mod R {}
17038 pub mod W {}
17039 pub mod RW {
17040 #[doc = "Keeper"]
17041 pub const PUE_0_KEEPER: u32 = 0;
17042 #[doc = "Pull"]
17043 pub const PUE_1_PULL: u32 = 0x01;
17044 }
17045 }
17046 #[doc = "Pull Up / Down Config. Field"]
17047 pub mod PUS {
17048 pub const offset: u32 = 14;
17049 pub const mask: u32 = 0x03 << offset;
17050 pub mod R {}
17051 pub mod W {}
17052 pub mod RW {
17053 #[doc = "100K Ohm Pull Down"]
17054 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
17055 #[doc = "47K Ohm Pull Up"]
17056 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
17057 #[doc = "100K Ohm Pull Up"]
17058 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
17059 #[doc = "22K Ohm Pull Up"]
17060 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
17061 }
17062 }
17063 #[doc = "Hyst. Enable Field"]
17064 pub mod HYS {
17065 pub const offset: u32 = 16;
17066 pub const mask: u32 = 0x01 << offset;
17067 pub mod R {}
17068 pub mod W {}
17069 pub mod RW {
17070 #[doc = "Hysteresis Disabled"]
17071 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
17072 #[doc = "Hysteresis Enabled"]
17073 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
17074 }
17075 }
17076}
17077#[doc = "SW_PAD_CTL_PAD_GPIO_B0_13 SW PAD Control Register"]
17078pub mod SW_PAD_CTL_PAD_GPIO_B0_13 {
17079 #[doc = "Slew Rate Field"]
17080 pub mod SRE {
17081 pub const offset: u32 = 0;
17082 pub const mask: u32 = 0x01 << offset;
17083 pub mod R {}
17084 pub mod W {}
17085 pub mod RW {
17086 #[doc = "Slow Slew Rate"]
17087 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
17088 #[doc = "Fast Slew Rate"]
17089 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
17090 }
17091 }
17092 #[doc = "Drive Strength Field"]
17093 pub mod DSE {
17094 pub const offset: u32 = 3;
17095 pub const mask: u32 = 0x07 << offset;
17096 pub mod R {}
17097 pub mod W {}
17098 pub mod RW {
17099 #[doc = "output driver disabled;"]
17100 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
17101 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
17102 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
17103 #[doc = "R0/2"]
17104 pub const DSE_2_R0_2: u32 = 0x02;
17105 #[doc = "R0/3"]
17106 pub const DSE_3_R0_3: u32 = 0x03;
17107 #[doc = "R0/4"]
17108 pub const DSE_4_R0_4: u32 = 0x04;
17109 #[doc = "R0/5"]
17110 pub const DSE_5_R0_5: u32 = 0x05;
17111 #[doc = "R0/6"]
17112 pub const DSE_6_R0_6: u32 = 0x06;
17113 #[doc = "R0/7"]
17114 pub const DSE_7_R0_7: u32 = 0x07;
17115 }
17116 }
17117 #[doc = "Speed Field"]
17118 pub mod SPEED {
17119 pub const offset: u32 = 6;
17120 pub const mask: u32 = 0x03 << offset;
17121 pub mod R {}
17122 pub mod W {}
17123 pub mod RW {
17124 #[doc = "low(50MHz)"]
17125 pub const SPEED_0_LOW_50MHZ: u32 = 0;
17126 #[doc = "medium(100MHz)"]
17127 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
17128 #[doc = "medium(100MHz)"]
17129 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
17130 #[doc = "max(200MHz)"]
17131 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
17132 }
17133 }
17134 #[doc = "Open Drain Enable Field"]
17135 pub mod ODE {
17136 pub const offset: u32 = 11;
17137 pub const mask: u32 = 0x01 << offset;
17138 pub mod R {}
17139 pub mod W {}
17140 pub mod RW {
17141 #[doc = "Open Drain Disabled"]
17142 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
17143 #[doc = "Open Drain Enabled"]
17144 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
17145 }
17146 }
17147 #[doc = "Pull / Keep Enable Field"]
17148 pub mod PKE {
17149 pub const offset: u32 = 12;
17150 pub const mask: u32 = 0x01 << offset;
17151 pub mod R {}
17152 pub mod W {}
17153 pub mod RW {
17154 #[doc = "Pull/Keeper Disabled"]
17155 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
17156 #[doc = "Pull/Keeper Enabled"]
17157 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
17158 }
17159 }
17160 #[doc = "Pull / Keep Select Field"]
17161 pub mod PUE {
17162 pub const offset: u32 = 13;
17163 pub const mask: u32 = 0x01 << offset;
17164 pub mod R {}
17165 pub mod W {}
17166 pub mod RW {
17167 #[doc = "Keeper"]
17168 pub const PUE_0_KEEPER: u32 = 0;
17169 #[doc = "Pull"]
17170 pub const PUE_1_PULL: u32 = 0x01;
17171 }
17172 }
17173 #[doc = "Pull Up / Down Config. Field"]
17174 pub mod PUS {
17175 pub const offset: u32 = 14;
17176 pub const mask: u32 = 0x03 << offset;
17177 pub mod R {}
17178 pub mod W {}
17179 pub mod RW {
17180 #[doc = "100K Ohm Pull Down"]
17181 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
17182 #[doc = "47K Ohm Pull Up"]
17183 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
17184 #[doc = "100K Ohm Pull Up"]
17185 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
17186 #[doc = "22K Ohm Pull Up"]
17187 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
17188 }
17189 }
17190 #[doc = "Hyst. Enable Field"]
17191 pub mod HYS {
17192 pub const offset: u32 = 16;
17193 pub const mask: u32 = 0x01 << offset;
17194 pub mod R {}
17195 pub mod W {}
17196 pub mod RW {
17197 #[doc = "Hysteresis Disabled"]
17198 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
17199 #[doc = "Hysteresis Enabled"]
17200 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
17201 }
17202 }
17203}
17204#[doc = "SW_PAD_CTL_PAD_GPIO_B0_14 SW PAD Control Register"]
17205pub mod SW_PAD_CTL_PAD_GPIO_B0_14 {
17206 #[doc = "Slew Rate Field"]
17207 pub mod SRE {
17208 pub const offset: u32 = 0;
17209 pub const mask: u32 = 0x01 << offset;
17210 pub mod R {}
17211 pub mod W {}
17212 pub mod RW {
17213 #[doc = "Slow Slew Rate"]
17214 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
17215 #[doc = "Fast Slew Rate"]
17216 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
17217 }
17218 }
17219 #[doc = "Drive Strength Field"]
17220 pub mod DSE {
17221 pub const offset: u32 = 3;
17222 pub const mask: u32 = 0x07 << offset;
17223 pub mod R {}
17224 pub mod W {}
17225 pub mod RW {
17226 #[doc = "output driver disabled;"]
17227 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
17228 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
17229 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
17230 #[doc = "R0/2"]
17231 pub const DSE_2_R0_2: u32 = 0x02;
17232 #[doc = "R0/3"]
17233 pub const DSE_3_R0_3: u32 = 0x03;
17234 #[doc = "R0/4"]
17235 pub const DSE_4_R0_4: u32 = 0x04;
17236 #[doc = "R0/5"]
17237 pub const DSE_5_R0_5: u32 = 0x05;
17238 #[doc = "R0/6"]
17239 pub const DSE_6_R0_6: u32 = 0x06;
17240 #[doc = "R0/7"]
17241 pub const DSE_7_R0_7: u32 = 0x07;
17242 }
17243 }
17244 #[doc = "Speed Field"]
17245 pub mod SPEED {
17246 pub const offset: u32 = 6;
17247 pub const mask: u32 = 0x03 << offset;
17248 pub mod R {}
17249 pub mod W {}
17250 pub mod RW {
17251 #[doc = "low(50MHz)"]
17252 pub const SPEED_0_LOW_50MHZ: u32 = 0;
17253 #[doc = "medium(100MHz)"]
17254 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
17255 #[doc = "medium(100MHz)"]
17256 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
17257 #[doc = "max(200MHz)"]
17258 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
17259 }
17260 }
17261 #[doc = "Open Drain Enable Field"]
17262 pub mod ODE {
17263 pub const offset: u32 = 11;
17264 pub const mask: u32 = 0x01 << offset;
17265 pub mod R {}
17266 pub mod W {}
17267 pub mod RW {
17268 #[doc = "Open Drain Disabled"]
17269 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
17270 #[doc = "Open Drain Enabled"]
17271 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
17272 }
17273 }
17274 #[doc = "Pull / Keep Enable Field"]
17275 pub mod PKE {
17276 pub const offset: u32 = 12;
17277 pub const mask: u32 = 0x01 << offset;
17278 pub mod R {}
17279 pub mod W {}
17280 pub mod RW {
17281 #[doc = "Pull/Keeper Disabled"]
17282 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
17283 #[doc = "Pull/Keeper Enabled"]
17284 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
17285 }
17286 }
17287 #[doc = "Pull / Keep Select Field"]
17288 pub mod PUE {
17289 pub const offset: u32 = 13;
17290 pub const mask: u32 = 0x01 << offset;
17291 pub mod R {}
17292 pub mod W {}
17293 pub mod RW {
17294 #[doc = "Keeper"]
17295 pub const PUE_0_KEEPER: u32 = 0;
17296 #[doc = "Pull"]
17297 pub const PUE_1_PULL: u32 = 0x01;
17298 }
17299 }
17300 #[doc = "Pull Up / Down Config. Field"]
17301 pub mod PUS {
17302 pub const offset: u32 = 14;
17303 pub const mask: u32 = 0x03 << offset;
17304 pub mod R {}
17305 pub mod W {}
17306 pub mod RW {
17307 #[doc = "100K Ohm Pull Down"]
17308 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
17309 #[doc = "47K Ohm Pull Up"]
17310 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
17311 #[doc = "100K Ohm Pull Up"]
17312 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
17313 #[doc = "22K Ohm Pull Up"]
17314 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
17315 }
17316 }
17317 #[doc = "Hyst. Enable Field"]
17318 pub mod HYS {
17319 pub const offset: u32 = 16;
17320 pub const mask: u32 = 0x01 << offset;
17321 pub mod R {}
17322 pub mod W {}
17323 pub mod RW {
17324 #[doc = "Hysteresis Disabled"]
17325 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
17326 #[doc = "Hysteresis Enabled"]
17327 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
17328 }
17329 }
17330}
17331#[doc = "SW_PAD_CTL_PAD_GPIO_B0_15 SW PAD Control Register"]
17332pub mod SW_PAD_CTL_PAD_GPIO_B0_15 {
17333 #[doc = "Slew Rate Field"]
17334 pub mod SRE {
17335 pub const offset: u32 = 0;
17336 pub const mask: u32 = 0x01 << offset;
17337 pub mod R {}
17338 pub mod W {}
17339 pub mod RW {
17340 #[doc = "Slow Slew Rate"]
17341 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
17342 #[doc = "Fast Slew Rate"]
17343 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
17344 }
17345 }
17346 #[doc = "Drive Strength Field"]
17347 pub mod DSE {
17348 pub const offset: u32 = 3;
17349 pub const mask: u32 = 0x07 << offset;
17350 pub mod R {}
17351 pub mod W {}
17352 pub mod RW {
17353 #[doc = "output driver disabled;"]
17354 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
17355 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
17356 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
17357 #[doc = "R0/2"]
17358 pub const DSE_2_R0_2: u32 = 0x02;
17359 #[doc = "R0/3"]
17360 pub const DSE_3_R0_3: u32 = 0x03;
17361 #[doc = "R0/4"]
17362 pub const DSE_4_R0_4: u32 = 0x04;
17363 #[doc = "R0/5"]
17364 pub const DSE_5_R0_5: u32 = 0x05;
17365 #[doc = "R0/6"]
17366 pub const DSE_6_R0_6: u32 = 0x06;
17367 #[doc = "R0/7"]
17368 pub const DSE_7_R0_7: u32 = 0x07;
17369 }
17370 }
17371 #[doc = "Speed Field"]
17372 pub mod SPEED {
17373 pub const offset: u32 = 6;
17374 pub const mask: u32 = 0x03 << offset;
17375 pub mod R {}
17376 pub mod W {}
17377 pub mod RW {
17378 #[doc = "low(50MHz)"]
17379 pub const SPEED_0_LOW_50MHZ: u32 = 0;
17380 #[doc = "medium(100MHz)"]
17381 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
17382 #[doc = "medium(100MHz)"]
17383 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
17384 #[doc = "max(200MHz)"]
17385 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
17386 }
17387 }
17388 #[doc = "Open Drain Enable Field"]
17389 pub mod ODE {
17390 pub const offset: u32 = 11;
17391 pub const mask: u32 = 0x01 << offset;
17392 pub mod R {}
17393 pub mod W {}
17394 pub mod RW {
17395 #[doc = "Open Drain Disabled"]
17396 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
17397 #[doc = "Open Drain Enabled"]
17398 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
17399 }
17400 }
17401 #[doc = "Pull / Keep Enable Field"]
17402 pub mod PKE {
17403 pub const offset: u32 = 12;
17404 pub const mask: u32 = 0x01 << offset;
17405 pub mod R {}
17406 pub mod W {}
17407 pub mod RW {
17408 #[doc = "Pull/Keeper Disabled"]
17409 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
17410 #[doc = "Pull/Keeper Enabled"]
17411 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
17412 }
17413 }
17414 #[doc = "Pull / Keep Select Field"]
17415 pub mod PUE {
17416 pub const offset: u32 = 13;
17417 pub const mask: u32 = 0x01 << offset;
17418 pub mod R {}
17419 pub mod W {}
17420 pub mod RW {
17421 #[doc = "Keeper"]
17422 pub const PUE_0_KEEPER: u32 = 0;
17423 #[doc = "Pull"]
17424 pub const PUE_1_PULL: u32 = 0x01;
17425 }
17426 }
17427 #[doc = "Pull Up / Down Config. Field"]
17428 pub mod PUS {
17429 pub const offset: u32 = 14;
17430 pub const mask: u32 = 0x03 << offset;
17431 pub mod R {}
17432 pub mod W {}
17433 pub mod RW {
17434 #[doc = "100K Ohm Pull Down"]
17435 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
17436 #[doc = "47K Ohm Pull Up"]
17437 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
17438 #[doc = "100K Ohm Pull Up"]
17439 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
17440 #[doc = "22K Ohm Pull Up"]
17441 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
17442 }
17443 }
17444 #[doc = "Hyst. Enable Field"]
17445 pub mod HYS {
17446 pub const offset: u32 = 16;
17447 pub const mask: u32 = 0x01 << offset;
17448 pub mod R {}
17449 pub mod W {}
17450 pub mod RW {
17451 #[doc = "Hysteresis Disabled"]
17452 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
17453 #[doc = "Hysteresis Enabled"]
17454 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
17455 }
17456 }
17457}
17458#[doc = "SW_PAD_CTL_PAD_GPIO_B1_00 SW PAD Control Register"]
17459pub mod SW_PAD_CTL_PAD_GPIO_B1_00 {
17460 #[doc = "Slew Rate Field"]
17461 pub mod SRE {
17462 pub const offset: u32 = 0;
17463 pub const mask: u32 = 0x01 << offset;
17464 pub mod R {}
17465 pub mod W {}
17466 pub mod RW {
17467 #[doc = "Slow Slew Rate"]
17468 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
17469 #[doc = "Fast Slew Rate"]
17470 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
17471 }
17472 }
17473 #[doc = "Drive Strength Field"]
17474 pub mod DSE {
17475 pub const offset: u32 = 3;
17476 pub const mask: u32 = 0x07 << offset;
17477 pub mod R {}
17478 pub mod W {}
17479 pub mod RW {
17480 #[doc = "output driver disabled;"]
17481 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
17482 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
17483 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
17484 #[doc = "R0/2"]
17485 pub const DSE_2_R0_2: u32 = 0x02;
17486 #[doc = "R0/3"]
17487 pub const DSE_3_R0_3: u32 = 0x03;
17488 #[doc = "R0/4"]
17489 pub const DSE_4_R0_4: u32 = 0x04;
17490 #[doc = "R0/5"]
17491 pub const DSE_5_R0_5: u32 = 0x05;
17492 #[doc = "R0/6"]
17493 pub const DSE_6_R0_6: u32 = 0x06;
17494 #[doc = "R0/7"]
17495 pub const DSE_7_R0_7: u32 = 0x07;
17496 }
17497 }
17498 #[doc = "Speed Field"]
17499 pub mod SPEED {
17500 pub const offset: u32 = 6;
17501 pub const mask: u32 = 0x03 << offset;
17502 pub mod R {}
17503 pub mod W {}
17504 pub mod RW {
17505 #[doc = "low(50MHz)"]
17506 pub const SPEED_0_LOW_50MHZ: u32 = 0;
17507 #[doc = "medium(100MHz)"]
17508 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
17509 #[doc = "medium(100MHz)"]
17510 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
17511 #[doc = "max(200MHz)"]
17512 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
17513 }
17514 }
17515 #[doc = "Open Drain Enable Field"]
17516 pub mod ODE {
17517 pub const offset: u32 = 11;
17518 pub const mask: u32 = 0x01 << offset;
17519 pub mod R {}
17520 pub mod W {}
17521 pub mod RW {
17522 #[doc = "Open Drain Disabled"]
17523 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
17524 #[doc = "Open Drain Enabled"]
17525 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
17526 }
17527 }
17528 #[doc = "Pull / Keep Enable Field"]
17529 pub mod PKE {
17530 pub const offset: u32 = 12;
17531 pub const mask: u32 = 0x01 << offset;
17532 pub mod R {}
17533 pub mod W {}
17534 pub mod RW {
17535 #[doc = "Pull/Keeper Disabled"]
17536 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
17537 #[doc = "Pull/Keeper Enabled"]
17538 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
17539 }
17540 }
17541 #[doc = "Pull / Keep Select Field"]
17542 pub mod PUE {
17543 pub const offset: u32 = 13;
17544 pub const mask: u32 = 0x01 << offset;
17545 pub mod R {}
17546 pub mod W {}
17547 pub mod RW {
17548 #[doc = "Keeper"]
17549 pub const PUE_0_KEEPER: u32 = 0;
17550 #[doc = "Pull"]
17551 pub const PUE_1_PULL: u32 = 0x01;
17552 }
17553 }
17554 #[doc = "Pull Up / Down Config. Field"]
17555 pub mod PUS {
17556 pub const offset: u32 = 14;
17557 pub const mask: u32 = 0x03 << offset;
17558 pub mod R {}
17559 pub mod W {}
17560 pub mod RW {
17561 #[doc = "100K Ohm Pull Down"]
17562 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
17563 #[doc = "47K Ohm Pull Up"]
17564 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
17565 #[doc = "100K Ohm Pull Up"]
17566 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
17567 #[doc = "22K Ohm Pull Up"]
17568 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
17569 }
17570 }
17571 #[doc = "Hyst. Enable Field"]
17572 pub mod HYS {
17573 pub const offset: u32 = 16;
17574 pub const mask: u32 = 0x01 << offset;
17575 pub mod R {}
17576 pub mod W {}
17577 pub mod RW {
17578 #[doc = "Hysteresis Disabled"]
17579 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
17580 #[doc = "Hysteresis Enabled"]
17581 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
17582 }
17583 }
17584}
17585#[doc = "SW_PAD_CTL_PAD_GPIO_B1_01 SW PAD Control Register"]
17586pub mod SW_PAD_CTL_PAD_GPIO_B1_01 {
17587 #[doc = "Slew Rate Field"]
17588 pub mod SRE {
17589 pub const offset: u32 = 0;
17590 pub const mask: u32 = 0x01 << offset;
17591 pub mod R {}
17592 pub mod W {}
17593 pub mod RW {
17594 #[doc = "Slow Slew Rate"]
17595 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
17596 #[doc = "Fast Slew Rate"]
17597 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
17598 }
17599 }
17600 #[doc = "Drive Strength Field"]
17601 pub mod DSE {
17602 pub const offset: u32 = 3;
17603 pub const mask: u32 = 0x07 << offset;
17604 pub mod R {}
17605 pub mod W {}
17606 pub mod RW {
17607 #[doc = "output driver disabled;"]
17608 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
17609 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
17610 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
17611 #[doc = "R0/2"]
17612 pub const DSE_2_R0_2: u32 = 0x02;
17613 #[doc = "R0/3"]
17614 pub const DSE_3_R0_3: u32 = 0x03;
17615 #[doc = "R0/4"]
17616 pub const DSE_4_R0_4: u32 = 0x04;
17617 #[doc = "R0/5"]
17618 pub const DSE_5_R0_5: u32 = 0x05;
17619 #[doc = "R0/6"]
17620 pub const DSE_6_R0_6: u32 = 0x06;
17621 #[doc = "R0/7"]
17622 pub const DSE_7_R0_7: u32 = 0x07;
17623 }
17624 }
17625 #[doc = "Speed Field"]
17626 pub mod SPEED {
17627 pub const offset: u32 = 6;
17628 pub const mask: u32 = 0x03 << offset;
17629 pub mod R {}
17630 pub mod W {}
17631 pub mod RW {
17632 #[doc = "low(50MHz)"]
17633 pub const SPEED_0_LOW_50MHZ: u32 = 0;
17634 #[doc = "medium(100MHz)"]
17635 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
17636 #[doc = "medium(100MHz)"]
17637 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
17638 #[doc = "max(200MHz)"]
17639 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
17640 }
17641 }
17642 #[doc = "Open Drain Enable Field"]
17643 pub mod ODE {
17644 pub const offset: u32 = 11;
17645 pub const mask: u32 = 0x01 << offset;
17646 pub mod R {}
17647 pub mod W {}
17648 pub mod RW {
17649 #[doc = "Open Drain Disabled"]
17650 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
17651 #[doc = "Open Drain Enabled"]
17652 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
17653 }
17654 }
17655 #[doc = "Pull / Keep Enable Field"]
17656 pub mod PKE {
17657 pub const offset: u32 = 12;
17658 pub const mask: u32 = 0x01 << offset;
17659 pub mod R {}
17660 pub mod W {}
17661 pub mod RW {
17662 #[doc = "Pull/Keeper Disabled"]
17663 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
17664 #[doc = "Pull/Keeper Enabled"]
17665 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
17666 }
17667 }
17668 #[doc = "Pull / Keep Select Field"]
17669 pub mod PUE {
17670 pub const offset: u32 = 13;
17671 pub const mask: u32 = 0x01 << offset;
17672 pub mod R {}
17673 pub mod W {}
17674 pub mod RW {
17675 #[doc = "Keeper"]
17676 pub const PUE_0_KEEPER: u32 = 0;
17677 #[doc = "Pull"]
17678 pub const PUE_1_PULL: u32 = 0x01;
17679 }
17680 }
17681 #[doc = "Pull Up / Down Config. Field"]
17682 pub mod PUS {
17683 pub const offset: u32 = 14;
17684 pub const mask: u32 = 0x03 << offset;
17685 pub mod R {}
17686 pub mod W {}
17687 pub mod RW {
17688 #[doc = "100K Ohm Pull Down"]
17689 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
17690 #[doc = "47K Ohm Pull Up"]
17691 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
17692 #[doc = "100K Ohm Pull Up"]
17693 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
17694 #[doc = "22K Ohm Pull Up"]
17695 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
17696 }
17697 }
17698 #[doc = "Hyst. Enable Field"]
17699 pub mod HYS {
17700 pub const offset: u32 = 16;
17701 pub const mask: u32 = 0x01 << offset;
17702 pub mod R {}
17703 pub mod W {}
17704 pub mod RW {
17705 #[doc = "Hysteresis Disabled"]
17706 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
17707 #[doc = "Hysteresis Enabled"]
17708 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
17709 }
17710 }
17711}
17712#[doc = "SW_PAD_CTL_PAD_GPIO_B1_02 SW PAD Control Register"]
17713pub mod SW_PAD_CTL_PAD_GPIO_B1_02 {
17714 #[doc = "Slew Rate Field"]
17715 pub mod SRE {
17716 pub const offset: u32 = 0;
17717 pub const mask: u32 = 0x01 << offset;
17718 pub mod R {}
17719 pub mod W {}
17720 pub mod RW {
17721 #[doc = "Slow Slew Rate"]
17722 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
17723 #[doc = "Fast Slew Rate"]
17724 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
17725 }
17726 }
17727 #[doc = "Drive Strength Field"]
17728 pub mod DSE {
17729 pub const offset: u32 = 3;
17730 pub const mask: u32 = 0x07 << offset;
17731 pub mod R {}
17732 pub mod W {}
17733 pub mod RW {
17734 #[doc = "output driver disabled;"]
17735 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
17736 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
17737 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
17738 #[doc = "R0/2"]
17739 pub const DSE_2_R0_2: u32 = 0x02;
17740 #[doc = "R0/3"]
17741 pub const DSE_3_R0_3: u32 = 0x03;
17742 #[doc = "R0/4"]
17743 pub const DSE_4_R0_4: u32 = 0x04;
17744 #[doc = "R0/5"]
17745 pub const DSE_5_R0_5: u32 = 0x05;
17746 #[doc = "R0/6"]
17747 pub const DSE_6_R0_6: u32 = 0x06;
17748 #[doc = "R0/7"]
17749 pub const DSE_7_R0_7: u32 = 0x07;
17750 }
17751 }
17752 #[doc = "Speed Field"]
17753 pub mod SPEED {
17754 pub const offset: u32 = 6;
17755 pub const mask: u32 = 0x03 << offset;
17756 pub mod R {}
17757 pub mod W {}
17758 pub mod RW {
17759 #[doc = "low(50MHz)"]
17760 pub const SPEED_0_LOW_50MHZ: u32 = 0;
17761 #[doc = "medium(100MHz)"]
17762 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
17763 #[doc = "medium(100MHz)"]
17764 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
17765 #[doc = "max(200MHz)"]
17766 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
17767 }
17768 }
17769 #[doc = "Open Drain Enable Field"]
17770 pub mod ODE {
17771 pub const offset: u32 = 11;
17772 pub const mask: u32 = 0x01 << offset;
17773 pub mod R {}
17774 pub mod W {}
17775 pub mod RW {
17776 #[doc = "Open Drain Disabled"]
17777 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
17778 #[doc = "Open Drain Enabled"]
17779 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
17780 }
17781 }
17782 #[doc = "Pull / Keep Enable Field"]
17783 pub mod PKE {
17784 pub const offset: u32 = 12;
17785 pub const mask: u32 = 0x01 << offset;
17786 pub mod R {}
17787 pub mod W {}
17788 pub mod RW {
17789 #[doc = "Pull/Keeper Disabled"]
17790 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
17791 #[doc = "Pull/Keeper Enabled"]
17792 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
17793 }
17794 }
17795 #[doc = "Pull / Keep Select Field"]
17796 pub mod PUE {
17797 pub const offset: u32 = 13;
17798 pub const mask: u32 = 0x01 << offset;
17799 pub mod R {}
17800 pub mod W {}
17801 pub mod RW {
17802 #[doc = "Keeper"]
17803 pub const PUE_0_KEEPER: u32 = 0;
17804 #[doc = "Pull"]
17805 pub const PUE_1_PULL: u32 = 0x01;
17806 }
17807 }
17808 #[doc = "Pull Up / Down Config. Field"]
17809 pub mod PUS {
17810 pub const offset: u32 = 14;
17811 pub const mask: u32 = 0x03 << offset;
17812 pub mod R {}
17813 pub mod W {}
17814 pub mod RW {
17815 #[doc = "100K Ohm Pull Down"]
17816 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
17817 #[doc = "47K Ohm Pull Up"]
17818 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
17819 #[doc = "100K Ohm Pull Up"]
17820 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
17821 #[doc = "22K Ohm Pull Up"]
17822 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
17823 }
17824 }
17825 #[doc = "Hyst. Enable Field"]
17826 pub mod HYS {
17827 pub const offset: u32 = 16;
17828 pub const mask: u32 = 0x01 << offset;
17829 pub mod R {}
17830 pub mod W {}
17831 pub mod RW {
17832 #[doc = "Hysteresis Disabled"]
17833 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
17834 #[doc = "Hysteresis Enabled"]
17835 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
17836 }
17837 }
17838}
17839#[doc = "SW_PAD_CTL_PAD_GPIO_B1_03 SW PAD Control Register"]
17840pub mod SW_PAD_CTL_PAD_GPIO_B1_03 {
17841 #[doc = "Slew Rate Field"]
17842 pub mod SRE {
17843 pub const offset: u32 = 0;
17844 pub const mask: u32 = 0x01 << offset;
17845 pub mod R {}
17846 pub mod W {}
17847 pub mod RW {
17848 #[doc = "Slow Slew Rate"]
17849 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
17850 #[doc = "Fast Slew Rate"]
17851 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
17852 }
17853 }
17854 #[doc = "Drive Strength Field"]
17855 pub mod DSE {
17856 pub const offset: u32 = 3;
17857 pub const mask: u32 = 0x07 << offset;
17858 pub mod R {}
17859 pub mod W {}
17860 pub mod RW {
17861 #[doc = "output driver disabled;"]
17862 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
17863 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
17864 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
17865 #[doc = "R0/2"]
17866 pub const DSE_2_R0_2: u32 = 0x02;
17867 #[doc = "R0/3"]
17868 pub const DSE_3_R0_3: u32 = 0x03;
17869 #[doc = "R0/4"]
17870 pub const DSE_4_R0_4: u32 = 0x04;
17871 #[doc = "R0/5"]
17872 pub const DSE_5_R0_5: u32 = 0x05;
17873 #[doc = "R0/6"]
17874 pub const DSE_6_R0_6: u32 = 0x06;
17875 #[doc = "R0/7"]
17876 pub const DSE_7_R0_7: u32 = 0x07;
17877 }
17878 }
17879 #[doc = "Speed Field"]
17880 pub mod SPEED {
17881 pub const offset: u32 = 6;
17882 pub const mask: u32 = 0x03 << offset;
17883 pub mod R {}
17884 pub mod W {}
17885 pub mod RW {
17886 #[doc = "low(50MHz)"]
17887 pub const SPEED_0_LOW_50MHZ: u32 = 0;
17888 #[doc = "medium(100MHz)"]
17889 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
17890 #[doc = "medium(100MHz)"]
17891 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
17892 #[doc = "max(200MHz)"]
17893 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
17894 }
17895 }
17896 #[doc = "Open Drain Enable Field"]
17897 pub mod ODE {
17898 pub const offset: u32 = 11;
17899 pub const mask: u32 = 0x01 << offset;
17900 pub mod R {}
17901 pub mod W {}
17902 pub mod RW {
17903 #[doc = "Open Drain Disabled"]
17904 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
17905 #[doc = "Open Drain Enabled"]
17906 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
17907 }
17908 }
17909 #[doc = "Pull / Keep Enable Field"]
17910 pub mod PKE {
17911 pub const offset: u32 = 12;
17912 pub const mask: u32 = 0x01 << offset;
17913 pub mod R {}
17914 pub mod W {}
17915 pub mod RW {
17916 #[doc = "Pull/Keeper Disabled"]
17917 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
17918 #[doc = "Pull/Keeper Enabled"]
17919 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
17920 }
17921 }
17922 #[doc = "Pull / Keep Select Field"]
17923 pub mod PUE {
17924 pub const offset: u32 = 13;
17925 pub const mask: u32 = 0x01 << offset;
17926 pub mod R {}
17927 pub mod W {}
17928 pub mod RW {
17929 #[doc = "Keeper"]
17930 pub const PUE_0_KEEPER: u32 = 0;
17931 #[doc = "Pull"]
17932 pub const PUE_1_PULL: u32 = 0x01;
17933 }
17934 }
17935 #[doc = "Pull Up / Down Config. Field"]
17936 pub mod PUS {
17937 pub const offset: u32 = 14;
17938 pub const mask: u32 = 0x03 << offset;
17939 pub mod R {}
17940 pub mod W {}
17941 pub mod RW {
17942 #[doc = "100K Ohm Pull Down"]
17943 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
17944 #[doc = "47K Ohm Pull Up"]
17945 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
17946 #[doc = "100K Ohm Pull Up"]
17947 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
17948 #[doc = "22K Ohm Pull Up"]
17949 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
17950 }
17951 }
17952 #[doc = "Hyst. Enable Field"]
17953 pub mod HYS {
17954 pub const offset: u32 = 16;
17955 pub const mask: u32 = 0x01 << offset;
17956 pub mod R {}
17957 pub mod W {}
17958 pub mod RW {
17959 #[doc = "Hysteresis Disabled"]
17960 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
17961 #[doc = "Hysteresis Enabled"]
17962 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
17963 }
17964 }
17965}
17966#[doc = "SW_PAD_CTL_PAD_GPIO_B1_04 SW PAD Control Register"]
17967pub mod SW_PAD_CTL_PAD_GPIO_B1_04 {
17968 #[doc = "Slew Rate Field"]
17969 pub mod SRE {
17970 pub const offset: u32 = 0;
17971 pub const mask: u32 = 0x01 << offset;
17972 pub mod R {}
17973 pub mod W {}
17974 pub mod RW {
17975 #[doc = "Slow Slew Rate"]
17976 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
17977 #[doc = "Fast Slew Rate"]
17978 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
17979 }
17980 }
17981 #[doc = "Drive Strength Field"]
17982 pub mod DSE {
17983 pub const offset: u32 = 3;
17984 pub const mask: u32 = 0x07 << offset;
17985 pub mod R {}
17986 pub mod W {}
17987 pub mod RW {
17988 #[doc = "output driver disabled;"]
17989 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
17990 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
17991 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
17992 #[doc = "R0/2"]
17993 pub const DSE_2_R0_2: u32 = 0x02;
17994 #[doc = "R0/3"]
17995 pub const DSE_3_R0_3: u32 = 0x03;
17996 #[doc = "R0/4"]
17997 pub const DSE_4_R0_4: u32 = 0x04;
17998 #[doc = "R0/5"]
17999 pub const DSE_5_R0_5: u32 = 0x05;
18000 #[doc = "R0/6"]
18001 pub const DSE_6_R0_6: u32 = 0x06;
18002 #[doc = "R0/7"]
18003 pub const DSE_7_R0_7: u32 = 0x07;
18004 }
18005 }
18006 #[doc = "Speed Field"]
18007 pub mod SPEED {
18008 pub const offset: u32 = 6;
18009 pub const mask: u32 = 0x03 << offset;
18010 pub mod R {}
18011 pub mod W {}
18012 pub mod RW {
18013 #[doc = "low(50MHz)"]
18014 pub const SPEED_0_LOW_50MHZ: u32 = 0;
18015 #[doc = "medium(100MHz)"]
18016 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
18017 #[doc = "medium(100MHz)"]
18018 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
18019 #[doc = "max(200MHz)"]
18020 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
18021 }
18022 }
18023 #[doc = "Open Drain Enable Field"]
18024 pub mod ODE {
18025 pub const offset: u32 = 11;
18026 pub const mask: u32 = 0x01 << offset;
18027 pub mod R {}
18028 pub mod W {}
18029 pub mod RW {
18030 #[doc = "Open Drain Disabled"]
18031 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
18032 #[doc = "Open Drain Enabled"]
18033 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
18034 }
18035 }
18036 #[doc = "Pull / Keep Enable Field"]
18037 pub mod PKE {
18038 pub const offset: u32 = 12;
18039 pub const mask: u32 = 0x01 << offset;
18040 pub mod R {}
18041 pub mod W {}
18042 pub mod RW {
18043 #[doc = "Pull/Keeper Disabled"]
18044 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
18045 #[doc = "Pull/Keeper Enabled"]
18046 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
18047 }
18048 }
18049 #[doc = "Pull / Keep Select Field"]
18050 pub mod PUE {
18051 pub const offset: u32 = 13;
18052 pub const mask: u32 = 0x01 << offset;
18053 pub mod R {}
18054 pub mod W {}
18055 pub mod RW {
18056 #[doc = "Keeper"]
18057 pub const PUE_0_KEEPER: u32 = 0;
18058 #[doc = "Pull"]
18059 pub const PUE_1_PULL: u32 = 0x01;
18060 }
18061 }
18062 #[doc = "Pull Up / Down Config. Field"]
18063 pub mod PUS {
18064 pub const offset: u32 = 14;
18065 pub const mask: u32 = 0x03 << offset;
18066 pub mod R {}
18067 pub mod W {}
18068 pub mod RW {
18069 #[doc = "100K Ohm Pull Down"]
18070 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
18071 #[doc = "47K Ohm Pull Up"]
18072 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
18073 #[doc = "100K Ohm Pull Up"]
18074 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
18075 #[doc = "22K Ohm Pull Up"]
18076 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
18077 }
18078 }
18079 #[doc = "Hyst. Enable Field"]
18080 pub mod HYS {
18081 pub const offset: u32 = 16;
18082 pub const mask: u32 = 0x01 << offset;
18083 pub mod R {}
18084 pub mod W {}
18085 pub mod RW {
18086 #[doc = "Hysteresis Disabled"]
18087 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
18088 #[doc = "Hysteresis Enabled"]
18089 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
18090 }
18091 }
18092}
18093#[doc = "SW_PAD_CTL_PAD_GPIO_B1_05 SW PAD Control Register"]
18094pub mod SW_PAD_CTL_PAD_GPIO_B1_05 {
18095 #[doc = "Slew Rate Field"]
18096 pub mod SRE {
18097 pub const offset: u32 = 0;
18098 pub const mask: u32 = 0x01 << offset;
18099 pub mod R {}
18100 pub mod W {}
18101 pub mod RW {
18102 #[doc = "Slow Slew Rate"]
18103 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
18104 #[doc = "Fast Slew Rate"]
18105 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
18106 }
18107 }
18108 #[doc = "Drive Strength Field"]
18109 pub mod DSE {
18110 pub const offset: u32 = 3;
18111 pub const mask: u32 = 0x07 << offset;
18112 pub mod R {}
18113 pub mod W {}
18114 pub mod RW {
18115 #[doc = "output driver disabled;"]
18116 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
18117 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
18118 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
18119 #[doc = "R0/2"]
18120 pub const DSE_2_R0_2: u32 = 0x02;
18121 #[doc = "R0/3"]
18122 pub const DSE_3_R0_3: u32 = 0x03;
18123 #[doc = "R0/4"]
18124 pub const DSE_4_R0_4: u32 = 0x04;
18125 #[doc = "R0/5"]
18126 pub const DSE_5_R0_5: u32 = 0x05;
18127 #[doc = "R0/6"]
18128 pub const DSE_6_R0_6: u32 = 0x06;
18129 #[doc = "R0/7"]
18130 pub const DSE_7_R0_7: u32 = 0x07;
18131 }
18132 }
18133 #[doc = "Speed Field"]
18134 pub mod SPEED {
18135 pub const offset: u32 = 6;
18136 pub const mask: u32 = 0x03 << offset;
18137 pub mod R {}
18138 pub mod W {}
18139 pub mod RW {
18140 #[doc = "low(50MHz)"]
18141 pub const SPEED_0_LOW_50MHZ: u32 = 0;
18142 #[doc = "medium(100MHz)"]
18143 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
18144 #[doc = "medium(100MHz)"]
18145 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
18146 #[doc = "max(200MHz)"]
18147 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
18148 }
18149 }
18150 #[doc = "Open Drain Enable Field"]
18151 pub mod ODE {
18152 pub const offset: u32 = 11;
18153 pub const mask: u32 = 0x01 << offset;
18154 pub mod R {}
18155 pub mod W {}
18156 pub mod RW {
18157 #[doc = "Open Drain Disabled"]
18158 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
18159 #[doc = "Open Drain Enabled"]
18160 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
18161 }
18162 }
18163 #[doc = "Pull / Keep Enable Field"]
18164 pub mod PKE {
18165 pub const offset: u32 = 12;
18166 pub const mask: u32 = 0x01 << offset;
18167 pub mod R {}
18168 pub mod W {}
18169 pub mod RW {
18170 #[doc = "Pull/Keeper Disabled"]
18171 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
18172 #[doc = "Pull/Keeper Enabled"]
18173 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
18174 }
18175 }
18176 #[doc = "Pull / Keep Select Field"]
18177 pub mod PUE {
18178 pub const offset: u32 = 13;
18179 pub const mask: u32 = 0x01 << offset;
18180 pub mod R {}
18181 pub mod W {}
18182 pub mod RW {
18183 #[doc = "Keeper"]
18184 pub const PUE_0_KEEPER: u32 = 0;
18185 #[doc = "Pull"]
18186 pub const PUE_1_PULL: u32 = 0x01;
18187 }
18188 }
18189 #[doc = "Pull Up / Down Config. Field"]
18190 pub mod PUS {
18191 pub const offset: u32 = 14;
18192 pub const mask: u32 = 0x03 << offset;
18193 pub mod R {}
18194 pub mod W {}
18195 pub mod RW {
18196 #[doc = "100K Ohm Pull Down"]
18197 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
18198 #[doc = "47K Ohm Pull Up"]
18199 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
18200 #[doc = "100K Ohm Pull Up"]
18201 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
18202 #[doc = "22K Ohm Pull Up"]
18203 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
18204 }
18205 }
18206 #[doc = "Hyst. Enable Field"]
18207 pub mod HYS {
18208 pub const offset: u32 = 16;
18209 pub const mask: u32 = 0x01 << offset;
18210 pub mod R {}
18211 pub mod W {}
18212 pub mod RW {
18213 #[doc = "Hysteresis Disabled"]
18214 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
18215 #[doc = "Hysteresis Enabled"]
18216 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
18217 }
18218 }
18219}
18220#[doc = "SW_PAD_CTL_PAD_GPIO_B1_06 SW PAD Control Register"]
18221pub mod SW_PAD_CTL_PAD_GPIO_B1_06 {
18222 #[doc = "Slew Rate Field"]
18223 pub mod SRE {
18224 pub const offset: u32 = 0;
18225 pub const mask: u32 = 0x01 << offset;
18226 pub mod R {}
18227 pub mod W {}
18228 pub mod RW {
18229 #[doc = "Slow Slew Rate"]
18230 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
18231 #[doc = "Fast Slew Rate"]
18232 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
18233 }
18234 }
18235 #[doc = "Drive Strength Field"]
18236 pub mod DSE {
18237 pub const offset: u32 = 3;
18238 pub const mask: u32 = 0x07 << offset;
18239 pub mod R {}
18240 pub mod W {}
18241 pub mod RW {
18242 #[doc = "output driver disabled;"]
18243 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
18244 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
18245 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
18246 #[doc = "R0/2"]
18247 pub const DSE_2_R0_2: u32 = 0x02;
18248 #[doc = "R0/3"]
18249 pub const DSE_3_R0_3: u32 = 0x03;
18250 #[doc = "R0/4"]
18251 pub const DSE_4_R0_4: u32 = 0x04;
18252 #[doc = "R0/5"]
18253 pub const DSE_5_R0_5: u32 = 0x05;
18254 #[doc = "R0/6"]
18255 pub const DSE_6_R0_6: u32 = 0x06;
18256 #[doc = "R0/7"]
18257 pub const DSE_7_R0_7: u32 = 0x07;
18258 }
18259 }
18260 #[doc = "Speed Field"]
18261 pub mod SPEED {
18262 pub const offset: u32 = 6;
18263 pub const mask: u32 = 0x03 << offset;
18264 pub mod R {}
18265 pub mod W {}
18266 pub mod RW {
18267 #[doc = "low(50MHz)"]
18268 pub const SPEED_0_LOW_50MHZ: u32 = 0;
18269 #[doc = "medium(100MHz)"]
18270 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
18271 #[doc = "medium(100MHz)"]
18272 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
18273 #[doc = "max(200MHz)"]
18274 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
18275 }
18276 }
18277 #[doc = "Open Drain Enable Field"]
18278 pub mod ODE {
18279 pub const offset: u32 = 11;
18280 pub const mask: u32 = 0x01 << offset;
18281 pub mod R {}
18282 pub mod W {}
18283 pub mod RW {
18284 #[doc = "Open Drain Disabled"]
18285 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
18286 #[doc = "Open Drain Enabled"]
18287 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
18288 }
18289 }
18290 #[doc = "Pull / Keep Enable Field"]
18291 pub mod PKE {
18292 pub const offset: u32 = 12;
18293 pub const mask: u32 = 0x01 << offset;
18294 pub mod R {}
18295 pub mod W {}
18296 pub mod RW {
18297 #[doc = "Pull/Keeper Disabled"]
18298 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
18299 #[doc = "Pull/Keeper Enabled"]
18300 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
18301 }
18302 }
18303 #[doc = "Pull / Keep Select Field"]
18304 pub mod PUE {
18305 pub const offset: u32 = 13;
18306 pub const mask: u32 = 0x01 << offset;
18307 pub mod R {}
18308 pub mod W {}
18309 pub mod RW {
18310 #[doc = "Keeper"]
18311 pub const PUE_0_KEEPER: u32 = 0;
18312 #[doc = "Pull"]
18313 pub const PUE_1_PULL: u32 = 0x01;
18314 }
18315 }
18316 #[doc = "Pull Up / Down Config. Field"]
18317 pub mod PUS {
18318 pub const offset: u32 = 14;
18319 pub const mask: u32 = 0x03 << offset;
18320 pub mod R {}
18321 pub mod W {}
18322 pub mod RW {
18323 #[doc = "100K Ohm Pull Down"]
18324 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
18325 #[doc = "47K Ohm Pull Up"]
18326 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
18327 #[doc = "100K Ohm Pull Up"]
18328 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
18329 #[doc = "22K Ohm Pull Up"]
18330 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
18331 }
18332 }
18333 #[doc = "Hyst. Enable Field"]
18334 pub mod HYS {
18335 pub const offset: u32 = 16;
18336 pub const mask: u32 = 0x01 << offset;
18337 pub mod R {}
18338 pub mod W {}
18339 pub mod RW {
18340 #[doc = "Hysteresis Disabled"]
18341 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
18342 #[doc = "Hysteresis Enabled"]
18343 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
18344 }
18345 }
18346}
18347#[doc = "SW_PAD_CTL_PAD_GPIO_B1_07 SW PAD Control Register"]
18348pub mod SW_PAD_CTL_PAD_GPIO_B1_07 {
18349 #[doc = "Slew Rate Field"]
18350 pub mod SRE {
18351 pub const offset: u32 = 0;
18352 pub const mask: u32 = 0x01 << offset;
18353 pub mod R {}
18354 pub mod W {}
18355 pub mod RW {
18356 #[doc = "Slow Slew Rate"]
18357 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
18358 #[doc = "Fast Slew Rate"]
18359 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
18360 }
18361 }
18362 #[doc = "Drive Strength Field"]
18363 pub mod DSE {
18364 pub const offset: u32 = 3;
18365 pub const mask: u32 = 0x07 << offset;
18366 pub mod R {}
18367 pub mod W {}
18368 pub mod RW {
18369 #[doc = "output driver disabled;"]
18370 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
18371 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
18372 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
18373 #[doc = "R0/2"]
18374 pub const DSE_2_R0_2: u32 = 0x02;
18375 #[doc = "R0/3"]
18376 pub const DSE_3_R0_3: u32 = 0x03;
18377 #[doc = "R0/4"]
18378 pub const DSE_4_R0_4: u32 = 0x04;
18379 #[doc = "R0/5"]
18380 pub const DSE_5_R0_5: u32 = 0x05;
18381 #[doc = "R0/6"]
18382 pub const DSE_6_R0_6: u32 = 0x06;
18383 #[doc = "R0/7"]
18384 pub const DSE_7_R0_7: u32 = 0x07;
18385 }
18386 }
18387 #[doc = "Speed Field"]
18388 pub mod SPEED {
18389 pub const offset: u32 = 6;
18390 pub const mask: u32 = 0x03 << offset;
18391 pub mod R {}
18392 pub mod W {}
18393 pub mod RW {
18394 #[doc = "low(50MHz)"]
18395 pub const SPEED_0_LOW_50MHZ: u32 = 0;
18396 #[doc = "medium(100MHz)"]
18397 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
18398 #[doc = "medium(100MHz)"]
18399 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
18400 #[doc = "max(200MHz)"]
18401 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
18402 }
18403 }
18404 #[doc = "Open Drain Enable Field"]
18405 pub mod ODE {
18406 pub const offset: u32 = 11;
18407 pub const mask: u32 = 0x01 << offset;
18408 pub mod R {}
18409 pub mod W {}
18410 pub mod RW {
18411 #[doc = "Open Drain Disabled"]
18412 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
18413 #[doc = "Open Drain Enabled"]
18414 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
18415 }
18416 }
18417 #[doc = "Pull / Keep Enable Field"]
18418 pub mod PKE {
18419 pub const offset: u32 = 12;
18420 pub const mask: u32 = 0x01 << offset;
18421 pub mod R {}
18422 pub mod W {}
18423 pub mod RW {
18424 #[doc = "Pull/Keeper Disabled"]
18425 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
18426 #[doc = "Pull/Keeper Enabled"]
18427 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
18428 }
18429 }
18430 #[doc = "Pull / Keep Select Field"]
18431 pub mod PUE {
18432 pub const offset: u32 = 13;
18433 pub const mask: u32 = 0x01 << offset;
18434 pub mod R {}
18435 pub mod W {}
18436 pub mod RW {
18437 #[doc = "Keeper"]
18438 pub const PUE_0_KEEPER: u32 = 0;
18439 #[doc = "Pull"]
18440 pub const PUE_1_PULL: u32 = 0x01;
18441 }
18442 }
18443 #[doc = "Pull Up / Down Config. Field"]
18444 pub mod PUS {
18445 pub const offset: u32 = 14;
18446 pub const mask: u32 = 0x03 << offset;
18447 pub mod R {}
18448 pub mod W {}
18449 pub mod RW {
18450 #[doc = "100K Ohm Pull Down"]
18451 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
18452 #[doc = "47K Ohm Pull Up"]
18453 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
18454 #[doc = "100K Ohm Pull Up"]
18455 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
18456 #[doc = "22K Ohm Pull Up"]
18457 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
18458 }
18459 }
18460 #[doc = "Hyst. Enable Field"]
18461 pub mod HYS {
18462 pub const offset: u32 = 16;
18463 pub const mask: u32 = 0x01 << offset;
18464 pub mod R {}
18465 pub mod W {}
18466 pub mod RW {
18467 #[doc = "Hysteresis Disabled"]
18468 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
18469 #[doc = "Hysteresis Enabled"]
18470 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
18471 }
18472 }
18473}
18474#[doc = "SW_PAD_CTL_PAD_GPIO_B1_08 SW PAD Control Register"]
18475pub mod SW_PAD_CTL_PAD_GPIO_B1_08 {
18476 #[doc = "Slew Rate Field"]
18477 pub mod SRE {
18478 pub const offset: u32 = 0;
18479 pub const mask: u32 = 0x01 << offset;
18480 pub mod R {}
18481 pub mod W {}
18482 pub mod RW {
18483 #[doc = "Slow Slew Rate"]
18484 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
18485 #[doc = "Fast Slew Rate"]
18486 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
18487 }
18488 }
18489 #[doc = "Drive Strength Field"]
18490 pub mod DSE {
18491 pub const offset: u32 = 3;
18492 pub const mask: u32 = 0x07 << offset;
18493 pub mod R {}
18494 pub mod W {}
18495 pub mod RW {
18496 #[doc = "output driver disabled;"]
18497 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
18498 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
18499 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
18500 #[doc = "R0/2"]
18501 pub const DSE_2_R0_2: u32 = 0x02;
18502 #[doc = "R0/3"]
18503 pub const DSE_3_R0_3: u32 = 0x03;
18504 #[doc = "R0/4"]
18505 pub const DSE_4_R0_4: u32 = 0x04;
18506 #[doc = "R0/5"]
18507 pub const DSE_5_R0_5: u32 = 0x05;
18508 #[doc = "R0/6"]
18509 pub const DSE_6_R0_6: u32 = 0x06;
18510 #[doc = "R0/7"]
18511 pub const DSE_7_R0_7: u32 = 0x07;
18512 }
18513 }
18514 #[doc = "Speed Field"]
18515 pub mod SPEED {
18516 pub const offset: u32 = 6;
18517 pub const mask: u32 = 0x03 << offset;
18518 pub mod R {}
18519 pub mod W {}
18520 pub mod RW {
18521 #[doc = "low(50MHz)"]
18522 pub const SPEED_0_LOW_50MHZ: u32 = 0;
18523 #[doc = "medium(100MHz)"]
18524 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
18525 #[doc = "medium(100MHz)"]
18526 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
18527 #[doc = "max(200MHz)"]
18528 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
18529 }
18530 }
18531 #[doc = "Open Drain Enable Field"]
18532 pub mod ODE {
18533 pub const offset: u32 = 11;
18534 pub const mask: u32 = 0x01 << offset;
18535 pub mod R {}
18536 pub mod W {}
18537 pub mod RW {
18538 #[doc = "Open Drain Disabled"]
18539 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
18540 #[doc = "Open Drain Enabled"]
18541 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
18542 }
18543 }
18544 #[doc = "Pull / Keep Enable Field"]
18545 pub mod PKE {
18546 pub const offset: u32 = 12;
18547 pub const mask: u32 = 0x01 << offset;
18548 pub mod R {}
18549 pub mod W {}
18550 pub mod RW {
18551 #[doc = "Pull/Keeper Disabled"]
18552 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
18553 #[doc = "Pull/Keeper Enabled"]
18554 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
18555 }
18556 }
18557 #[doc = "Pull / Keep Select Field"]
18558 pub mod PUE {
18559 pub const offset: u32 = 13;
18560 pub const mask: u32 = 0x01 << offset;
18561 pub mod R {}
18562 pub mod W {}
18563 pub mod RW {
18564 #[doc = "Keeper"]
18565 pub const PUE_0_KEEPER: u32 = 0;
18566 #[doc = "Pull"]
18567 pub const PUE_1_PULL: u32 = 0x01;
18568 }
18569 }
18570 #[doc = "Pull Up / Down Config. Field"]
18571 pub mod PUS {
18572 pub const offset: u32 = 14;
18573 pub const mask: u32 = 0x03 << offset;
18574 pub mod R {}
18575 pub mod W {}
18576 pub mod RW {
18577 #[doc = "100K Ohm Pull Down"]
18578 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
18579 #[doc = "47K Ohm Pull Up"]
18580 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
18581 #[doc = "100K Ohm Pull Up"]
18582 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
18583 #[doc = "22K Ohm Pull Up"]
18584 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
18585 }
18586 }
18587 #[doc = "Hyst. Enable Field"]
18588 pub mod HYS {
18589 pub const offset: u32 = 16;
18590 pub const mask: u32 = 0x01 << offset;
18591 pub mod R {}
18592 pub mod W {}
18593 pub mod RW {
18594 #[doc = "Hysteresis Disabled"]
18595 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
18596 #[doc = "Hysteresis Enabled"]
18597 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
18598 }
18599 }
18600}
18601#[doc = "SW_PAD_CTL_PAD_GPIO_B1_09 SW PAD Control Register"]
18602pub mod SW_PAD_CTL_PAD_GPIO_B1_09 {
18603 #[doc = "Slew Rate Field"]
18604 pub mod SRE {
18605 pub const offset: u32 = 0;
18606 pub const mask: u32 = 0x01 << offset;
18607 pub mod R {}
18608 pub mod W {}
18609 pub mod RW {
18610 #[doc = "Slow Slew Rate"]
18611 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
18612 #[doc = "Fast Slew Rate"]
18613 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
18614 }
18615 }
18616 #[doc = "Drive Strength Field"]
18617 pub mod DSE {
18618 pub const offset: u32 = 3;
18619 pub const mask: u32 = 0x07 << offset;
18620 pub mod R {}
18621 pub mod W {}
18622 pub mod RW {
18623 #[doc = "output driver disabled;"]
18624 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
18625 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
18626 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
18627 #[doc = "R0/2"]
18628 pub const DSE_2_R0_2: u32 = 0x02;
18629 #[doc = "R0/3"]
18630 pub const DSE_3_R0_3: u32 = 0x03;
18631 #[doc = "R0/4"]
18632 pub const DSE_4_R0_4: u32 = 0x04;
18633 #[doc = "R0/5"]
18634 pub const DSE_5_R0_5: u32 = 0x05;
18635 #[doc = "R0/6"]
18636 pub const DSE_6_R0_6: u32 = 0x06;
18637 #[doc = "R0/7"]
18638 pub const DSE_7_R0_7: u32 = 0x07;
18639 }
18640 }
18641 #[doc = "Speed Field"]
18642 pub mod SPEED {
18643 pub const offset: u32 = 6;
18644 pub const mask: u32 = 0x03 << offset;
18645 pub mod R {}
18646 pub mod W {}
18647 pub mod RW {
18648 #[doc = "low(50MHz)"]
18649 pub const SPEED_0_LOW_50MHZ: u32 = 0;
18650 #[doc = "medium(100MHz)"]
18651 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
18652 #[doc = "medium(100MHz)"]
18653 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
18654 #[doc = "max(200MHz)"]
18655 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
18656 }
18657 }
18658 #[doc = "Open Drain Enable Field"]
18659 pub mod ODE {
18660 pub const offset: u32 = 11;
18661 pub const mask: u32 = 0x01 << offset;
18662 pub mod R {}
18663 pub mod W {}
18664 pub mod RW {
18665 #[doc = "Open Drain Disabled"]
18666 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
18667 #[doc = "Open Drain Enabled"]
18668 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
18669 }
18670 }
18671 #[doc = "Pull / Keep Enable Field"]
18672 pub mod PKE {
18673 pub const offset: u32 = 12;
18674 pub const mask: u32 = 0x01 << offset;
18675 pub mod R {}
18676 pub mod W {}
18677 pub mod RW {
18678 #[doc = "Pull/Keeper Disabled"]
18679 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
18680 #[doc = "Pull/Keeper Enabled"]
18681 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
18682 }
18683 }
18684 #[doc = "Pull / Keep Select Field"]
18685 pub mod PUE {
18686 pub const offset: u32 = 13;
18687 pub const mask: u32 = 0x01 << offset;
18688 pub mod R {}
18689 pub mod W {}
18690 pub mod RW {
18691 #[doc = "Keeper"]
18692 pub const PUE_0_KEEPER: u32 = 0;
18693 #[doc = "Pull"]
18694 pub const PUE_1_PULL: u32 = 0x01;
18695 }
18696 }
18697 #[doc = "Pull Up / Down Config. Field"]
18698 pub mod PUS {
18699 pub const offset: u32 = 14;
18700 pub const mask: u32 = 0x03 << offset;
18701 pub mod R {}
18702 pub mod W {}
18703 pub mod RW {
18704 #[doc = "100K Ohm Pull Down"]
18705 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
18706 #[doc = "47K Ohm Pull Up"]
18707 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
18708 #[doc = "100K Ohm Pull Up"]
18709 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
18710 #[doc = "22K Ohm Pull Up"]
18711 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
18712 }
18713 }
18714 #[doc = "Hyst. Enable Field"]
18715 pub mod HYS {
18716 pub const offset: u32 = 16;
18717 pub const mask: u32 = 0x01 << offset;
18718 pub mod R {}
18719 pub mod W {}
18720 pub mod RW {
18721 #[doc = "Hysteresis Disabled"]
18722 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
18723 #[doc = "Hysteresis Enabled"]
18724 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
18725 }
18726 }
18727}
18728#[doc = "SW_PAD_CTL_PAD_GPIO_B1_10 SW PAD Control Register"]
18729pub mod SW_PAD_CTL_PAD_GPIO_B1_10 {
18730 #[doc = "Slew Rate Field"]
18731 pub mod SRE {
18732 pub const offset: u32 = 0;
18733 pub const mask: u32 = 0x01 << offset;
18734 pub mod R {}
18735 pub mod W {}
18736 pub mod RW {
18737 #[doc = "Slow Slew Rate"]
18738 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
18739 #[doc = "Fast Slew Rate"]
18740 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
18741 }
18742 }
18743 #[doc = "Drive Strength Field"]
18744 pub mod DSE {
18745 pub const offset: u32 = 3;
18746 pub const mask: u32 = 0x07 << offset;
18747 pub mod R {}
18748 pub mod W {}
18749 pub mod RW {
18750 #[doc = "output driver disabled;"]
18751 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
18752 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
18753 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
18754 #[doc = "R0/2"]
18755 pub const DSE_2_R0_2: u32 = 0x02;
18756 #[doc = "R0/3"]
18757 pub const DSE_3_R0_3: u32 = 0x03;
18758 #[doc = "R0/4"]
18759 pub const DSE_4_R0_4: u32 = 0x04;
18760 #[doc = "R0/5"]
18761 pub const DSE_5_R0_5: u32 = 0x05;
18762 #[doc = "R0/6"]
18763 pub const DSE_6_R0_6: u32 = 0x06;
18764 #[doc = "R0/7"]
18765 pub const DSE_7_R0_7: u32 = 0x07;
18766 }
18767 }
18768 #[doc = "Speed Field"]
18769 pub mod SPEED {
18770 pub const offset: u32 = 6;
18771 pub const mask: u32 = 0x03 << offset;
18772 pub mod R {}
18773 pub mod W {}
18774 pub mod RW {
18775 #[doc = "low(50MHz)"]
18776 pub const SPEED_0_LOW_50MHZ: u32 = 0;
18777 #[doc = "medium(100MHz)"]
18778 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
18779 #[doc = "medium(100MHz)"]
18780 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
18781 #[doc = "max(200MHz)"]
18782 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
18783 }
18784 }
18785 #[doc = "Open Drain Enable Field"]
18786 pub mod ODE {
18787 pub const offset: u32 = 11;
18788 pub const mask: u32 = 0x01 << offset;
18789 pub mod R {}
18790 pub mod W {}
18791 pub mod RW {
18792 #[doc = "Open Drain Disabled"]
18793 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
18794 #[doc = "Open Drain Enabled"]
18795 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
18796 }
18797 }
18798 #[doc = "Pull / Keep Enable Field"]
18799 pub mod PKE {
18800 pub const offset: u32 = 12;
18801 pub const mask: u32 = 0x01 << offset;
18802 pub mod R {}
18803 pub mod W {}
18804 pub mod RW {
18805 #[doc = "Pull/Keeper Disabled"]
18806 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
18807 #[doc = "Pull/Keeper Enabled"]
18808 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
18809 }
18810 }
18811 #[doc = "Pull / Keep Select Field"]
18812 pub mod PUE {
18813 pub const offset: u32 = 13;
18814 pub const mask: u32 = 0x01 << offset;
18815 pub mod R {}
18816 pub mod W {}
18817 pub mod RW {
18818 #[doc = "Keeper"]
18819 pub const PUE_0_KEEPER: u32 = 0;
18820 #[doc = "Pull"]
18821 pub const PUE_1_PULL: u32 = 0x01;
18822 }
18823 }
18824 #[doc = "Pull Up / Down Config. Field"]
18825 pub mod PUS {
18826 pub const offset: u32 = 14;
18827 pub const mask: u32 = 0x03 << offset;
18828 pub mod R {}
18829 pub mod W {}
18830 pub mod RW {
18831 #[doc = "100K Ohm Pull Down"]
18832 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
18833 #[doc = "47K Ohm Pull Up"]
18834 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
18835 #[doc = "100K Ohm Pull Up"]
18836 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
18837 #[doc = "22K Ohm Pull Up"]
18838 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
18839 }
18840 }
18841 #[doc = "Hyst. Enable Field"]
18842 pub mod HYS {
18843 pub const offset: u32 = 16;
18844 pub const mask: u32 = 0x01 << offset;
18845 pub mod R {}
18846 pub mod W {}
18847 pub mod RW {
18848 #[doc = "Hysteresis Disabled"]
18849 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
18850 #[doc = "Hysteresis Enabled"]
18851 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
18852 }
18853 }
18854}
18855#[doc = "SW_PAD_CTL_PAD_GPIO_B1_11 SW PAD Control Register"]
18856pub mod SW_PAD_CTL_PAD_GPIO_B1_11 {
18857 #[doc = "Slew Rate Field"]
18858 pub mod SRE {
18859 pub const offset: u32 = 0;
18860 pub const mask: u32 = 0x01 << offset;
18861 pub mod R {}
18862 pub mod W {}
18863 pub mod RW {
18864 #[doc = "Slow Slew Rate"]
18865 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
18866 #[doc = "Fast Slew Rate"]
18867 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
18868 }
18869 }
18870 #[doc = "Drive Strength Field"]
18871 pub mod DSE {
18872 pub const offset: u32 = 3;
18873 pub const mask: u32 = 0x07 << offset;
18874 pub mod R {}
18875 pub mod W {}
18876 pub mod RW {
18877 #[doc = "output driver disabled;"]
18878 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
18879 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
18880 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
18881 #[doc = "R0/2"]
18882 pub const DSE_2_R0_2: u32 = 0x02;
18883 #[doc = "R0/3"]
18884 pub const DSE_3_R0_3: u32 = 0x03;
18885 #[doc = "R0/4"]
18886 pub const DSE_4_R0_4: u32 = 0x04;
18887 #[doc = "R0/5"]
18888 pub const DSE_5_R0_5: u32 = 0x05;
18889 #[doc = "R0/6"]
18890 pub const DSE_6_R0_6: u32 = 0x06;
18891 #[doc = "R0/7"]
18892 pub const DSE_7_R0_7: u32 = 0x07;
18893 }
18894 }
18895 #[doc = "Speed Field"]
18896 pub mod SPEED {
18897 pub const offset: u32 = 6;
18898 pub const mask: u32 = 0x03 << offset;
18899 pub mod R {}
18900 pub mod W {}
18901 pub mod RW {
18902 #[doc = "low(50MHz)"]
18903 pub const SPEED_0_LOW_50MHZ: u32 = 0;
18904 #[doc = "medium(100MHz)"]
18905 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
18906 #[doc = "medium(100MHz)"]
18907 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
18908 #[doc = "max(200MHz)"]
18909 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
18910 }
18911 }
18912 #[doc = "Open Drain Enable Field"]
18913 pub mod ODE {
18914 pub const offset: u32 = 11;
18915 pub const mask: u32 = 0x01 << offset;
18916 pub mod R {}
18917 pub mod W {}
18918 pub mod RW {
18919 #[doc = "Open Drain Disabled"]
18920 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
18921 #[doc = "Open Drain Enabled"]
18922 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
18923 }
18924 }
18925 #[doc = "Pull / Keep Enable Field"]
18926 pub mod PKE {
18927 pub const offset: u32 = 12;
18928 pub const mask: u32 = 0x01 << offset;
18929 pub mod R {}
18930 pub mod W {}
18931 pub mod RW {
18932 #[doc = "Pull/Keeper Disabled"]
18933 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
18934 #[doc = "Pull/Keeper Enabled"]
18935 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
18936 }
18937 }
18938 #[doc = "Pull / Keep Select Field"]
18939 pub mod PUE {
18940 pub const offset: u32 = 13;
18941 pub const mask: u32 = 0x01 << offset;
18942 pub mod R {}
18943 pub mod W {}
18944 pub mod RW {
18945 #[doc = "Keeper"]
18946 pub const PUE_0_KEEPER: u32 = 0;
18947 #[doc = "Pull"]
18948 pub const PUE_1_PULL: u32 = 0x01;
18949 }
18950 }
18951 #[doc = "Pull Up / Down Config. Field"]
18952 pub mod PUS {
18953 pub const offset: u32 = 14;
18954 pub const mask: u32 = 0x03 << offset;
18955 pub mod R {}
18956 pub mod W {}
18957 pub mod RW {
18958 #[doc = "100K Ohm Pull Down"]
18959 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
18960 #[doc = "47K Ohm Pull Up"]
18961 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
18962 #[doc = "100K Ohm Pull Up"]
18963 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
18964 #[doc = "22K Ohm Pull Up"]
18965 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
18966 }
18967 }
18968 #[doc = "Hyst. Enable Field"]
18969 pub mod HYS {
18970 pub const offset: u32 = 16;
18971 pub const mask: u32 = 0x01 << offset;
18972 pub mod R {}
18973 pub mod W {}
18974 pub mod RW {
18975 #[doc = "Hysteresis Disabled"]
18976 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
18977 #[doc = "Hysteresis Enabled"]
18978 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
18979 }
18980 }
18981}
18982#[doc = "SW_PAD_CTL_PAD_GPIO_B1_12 SW PAD Control Register"]
18983pub mod SW_PAD_CTL_PAD_GPIO_B1_12 {
18984 #[doc = "Slew Rate Field"]
18985 pub mod SRE {
18986 pub const offset: u32 = 0;
18987 pub const mask: u32 = 0x01 << offset;
18988 pub mod R {}
18989 pub mod W {}
18990 pub mod RW {
18991 #[doc = "Slow Slew Rate"]
18992 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
18993 #[doc = "Fast Slew Rate"]
18994 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
18995 }
18996 }
18997 #[doc = "Drive Strength Field"]
18998 pub mod DSE {
18999 pub const offset: u32 = 3;
19000 pub const mask: u32 = 0x07 << offset;
19001 pub mod R {}
19002 pub mod W {}
19003 pub mod RW {
19004 #[doc = "output driver disabled;"]
19005 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
19006 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
19007 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
19008 #[doc = "R0/2"]
19009 pub const DSE_2_R0_2: u32 = 0x02;
19010 #[doc = "R0/3"]
19011 pub const DSE_3_R0_3: u32 = 0x03;
19012 #[doc = "R0/4"]
19013 pub const DSE_4_R0_4: u32 = 0x04;
19014 #[doc = "R0/5"]
19015 pub const DSE_5_R0_5: u32 = 0x05;
19016 #[doc = "R0/6"]
19017 pub const DSE_6_R0_6: u32 = 0x06;
19018 #[doc = "R0/7"]
19019 pub const DSE_7_R0_7: u32 = 0x07;
19020 }
19021 }
19022 #[doc = "Speed Field"]
19023 pub mod SPEED {
19024 pub const offset: u32 = 6;
19025 pub const mask: u32 = 0x03 << offset;
19026 pub mod R {}
19027 pub mod W {}
19028 pub mod RW {
19029 #[doc = "low(50MHz)"]
19030 pub const SPEED_0_LOW_50MHZ: u32 = 0;
19031 #[doc = "medium(100MHz)"]
19032 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
19033 #[doc = "medium(100MHz)"]
19034 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
19035 #[doc = "max(200MHz)"]
19036 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
19037 }
19038 }
19039 #[doc = "Open Drain Enable Field"]
19040 pub mod ODE {
19041 pub const offset: u32 = 11;
19042 pub const mask: u32 = 0x01 << offset;
19043 pub mod R {}
19044 pub mod W {}
19045 pub mod RW {
19046 #[doc = "Open Drain Disabled"]
19047 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
19048 #[doc = "Open Drain Enabled"]
19049 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
19050 }
19051 }
19052 #[doc = "Pull / Keep Enable Field"]
19053 pub mod PKE {
19054 pub const offset: u32 = 12;
19055 pub const mask: u32 = 0x01 << offset;
19056 pub mod R {}
19057 pub mod W {}
19058 pub mod RW {
19059 #[doc = "Pull/Keeper Disabled"]
19060 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
19061 #[doc = "Pull/Keeper Enabled"]
19062 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
19063 }
19064 }
19065 #[doc = "Pull / Keep Select Field"]
19066 pub mod PUE {
19067 pub const offset: u32 = 13;
19068 pub const mask: u32 = 0x01 << offset;
19069 pub mod R {}
19070 pub mod W {}
19071 pub mod RW {
19072 #[doc = "Keeper"]
19073 pub const PUE_0_KEEPER: u32 = 0;
19074 #[doc = "Pull"]
19075 pub const PUE_1_PULL: u32 = 0x01;
19076 }
19077 }
19078 #[doc = "Pull Up / Down Config. Field"]
19079 pub mod PUS {
19080 pub const offset: u32 = 14;
19081 pub const mask: u32 = 0x03 << offset;
19082 pub mod R {}
19083 pub mod W {}
19084 pub mod RW {
19085 #[doc = "100K Ohm Pull Down"]
19086 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
19087 #[doc = "47K Ohm Pull Up"]
19088 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
19089 #[doc = "100K Ohm Pull Up"]
19090 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
19091 #[doc = "22K Ohm Pull Up"]
19092 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
19093 }
19094 }
19095 #[doc = "Hyst. Enable Field"]
19096 pub mod HYS {
19097 pub const offset: u32 = 16;
19098 pub const mask: u32 = 0x01 << offset;
19099 pub mod R {}
19100 pub mod W {}
19101 pub mod RW {
19102 #[doc = "Hysteresis Disabled"]
19103 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
19104 #[doc = "Hysteresis Enabled"]
19105 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
19106 }
19107 }
19108}
19109#[doc = "SW_PAD_CTL_PAD_GPIO_B1_13 SW PAD Control Register"]
19110pub mod SW_PAD_CTL_PAD_GPIO_B1_13 {
19111 #[doc = "Slew Rate Field"]
19112 pub mod SRE {
19113 pub const offset: u32 = 0;
19114 pub const mask: u32 = 0x01 << offset;
19115 pub mod R {}
19116 pub mod W {}
19117 pub mod RW {
19118 #[doc = "Slow Slew Rate"]
19119 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
19120 #[doc = "Fast Slew Rate"]
19121 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
19122 }
19123 }
19124 #[doc = "Drive Strength Field"]
19125 pub mod DSE {
19126 pub const offset: u32 = 3;
19127 pub const mask: u32 = 0x07 << offset;
19128 pub mod R {}
19129 pub mod W {}
19130 pub mod RW {
19131 #[doc = "output driver disabled;"]
19132 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
19133 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
19134 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
19135 #[doc = "R0/2"]
19136 pub const DSE_2_R0_2: u32 = 0x02;
19137 #[doc = "R0/3"]
19138 pub const DSE_3_R0_3: u32 = 0x03;
19139 #[doc = "R0/4"]
19140 pub const DSE_4_R0_4: u32 = 0x04;
19141 #[doc = "R0/5"]
19142 pub const DSE_5_R0_5: u32 = 0x05;
19143 #[doc = "R0/6"]
19144 pub const DSE_6_R0_6: u32 = 0x06;
19145 #[doc = "R0/7"]
19146 pub const DSE_7_R0_7: u32 = 0x07;
19147 }
19148 }
19149 #[doc = "Speed Field"]
19150 pub mod SPEED {
19151 pub const offset: u32 = 6;
19152 pub const mask: u32 = 0x03 << offset;
19153 pub mod R {}
19154 pub mod W {}
19155 pub mod RW {
19156 #[doc = "low(50MHz)"]
19157 pub const SPEED_0_LOW_50MHZ: u32 = 0;
19158 #[doc = "medium(100MHz)"]
19159 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
19160 #[doc = "medium(100MHz)"]
19161 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
19162 #[doc = "max(200MHz)"]
19163 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
19164 }
19165 }
19166 #[doc = "Open Drain Enable Field"]
19167 pub mod ODE {
19168 pub const offset: u32 = 11;
19169 pub const mask: u32 = 0x01 << offset;
19170 pub mod R {}
19171 pub mod W {}
19172 pub mod RW {
19173 #[doc = "Open Drain Disabled"]
19174 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
19175 #[doc = "Open Drain Enabled"]
19176 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
19177 }
19178 }
19179 #[doc = "Pull / Keep Enable Field"]
19180 pub mod PKE {
19181 pub const offset: u32 = 12;
19182 pub const mask: u32 = 0x01 << offset;
19183 pub mod R {}
19184 pub mod W {}
19185 pub mod RW {
19186 #[doc = "Pull/Keeper Disabled"]
19187 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
19188 #[doc = "Pull/Keeper Enabled"]
19189 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
19190 }
19191 }
19192 #[doc = "Pull / Keep Select Field"]
19193 pub mod PUE {
19194 pub const offset: u32 = 13;
19195 pub const mask: u32 = 0x01 << offset;
19196 pub mod R {}
19197 pub mod W {}
19198 pub mod RW {
19199 #[doc = "Keeper"]
19200 pub const PUE_0_KEEPER: u32 = 0;
19201 #[doc = "Pull"]
19202 pub const PUE_1_PULL: u32 = 0x01;
19203 }
19204 }
19205 #[doc = "Pull Up / Down Config. Field"]
19206 pub mod PUS {
19207 pub const offset: u32 = 14;
19208 pub const mask: u32 = 0x03 << offset;
19209 pub mod R {}
19210 pub mod W {}
19211 pub mod RW {
19212 #[doc = "100K Ohm Pull Down"]
19213 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
19214 #[doc = "47K Ohm Pull Up"]
19215 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
19216 #[doc = "100K Ohm Pull Up"]
19217 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
19218 #[doc = "22K Ohm Pull Up"]
19219 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
19220 }
19221 }
19222 #[doc = "Hyst. Enable Field"]
19223 pub mod HYS {
19224 pub const offset: u32 = 16;
19225 pub const mask: u32 = 0x01 << offset;
19226 pub mod R {}
19227 pub mod W {}
19228 pub mod RW {
19229 #[doc = "Hysteresis Disabled"]
19230 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
19231 #[doc = "Hysteresis Enabled"]
19232 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
19233 }
19234 }
19235}
19236#[doc = "SW_PAD_CTL_PAD_GPIO_B1_14 SW PAD Control Register"]
19237pub mod SW_PAD_CTL_PAD_GPIO_B1_14 {
19238 #[doc = "Slew Rate Field"]
19239 pub mod SRE {
19240 pub const offset: u32 = 0;
19241 pub const mask: u32 = 0x01 << offset;
19242 pub mod R {}
19243 pub mod W {}
19244 pub mod RW {
19245 #[doc = "Slow Slew Rate"]
19246 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
19247 #[doc = "Fast Slew Rate"]
19248 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
19249 }
19250 }
19251 #[doc = "Drive Strength Field"]
19252 pub mod DSE {
19253 pub const offset: u32 = 3;
19254 pub const mask: u32 = 0x07 << offset;
19255 pub mod R {}
19256 pub mod W {}
19257 pub mod RW {
19258 #[doc = "output driver disabled;"]
19259 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
19260 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
19261 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
19262 #[doc = "R0/2"]
19263 pub const DSE_2_R0_2: u32 = 0x02;
19264 #[doc = "R0/3"]
19265 pub const DSE_3_R0_3: u32 = 0x03;
19266 #[doc = "R0/4"]
19267 pub const DSE_4_R0_4: u32 = 0x04;
19268 #[doc = "R0/5"]
19269 pub const DSE_5_R0_5: u32 = 0x05;
19270 #[doc = "R0/6"]
19271 pub const DSE_6_R0_6: u32 = 0x06;
19272 #[doc = "R0/7"]
19273 pub const DSE_7_R0_7: u32 = 0x07;
19274 }
19275 }
19276 #[doc = "Speed Field"]
19277 pub mod SPEED {
19278 pub const offset: u32 = 6;
19279 pub const mask: u32 = 0x03 << offset;
19280 pub mod R {}
19281 pub mod W {}
19282 pub mod RW {
19283 #[doc = "low(50MHz)"]
19284 pub const SPEED_0_LOW_50MHZ: u32 = 0;
19285 #[doc = "medium(100MHz)"]
19286 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
19287 #[doc = "medium(100MHz)"]
19288 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
19289 #[doc = "max(200MHz)"]
19290 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
19291 }
19292 }
19293 #[doc = "Open Drain Enable Field"]
19294 pub mod ODE {
19295 pub const offset: u32 = 11;
19296 pub const mask: u32 = 0x01 << offset;
19297 pub mod R {}
19298 pub mod W {}
19299 pub mod RW {
19300 #[doc = "Open Drain Disabled"]
19301 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
19302 #[doc = "Open Drain Enabled"]
19303 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
19304 }
19305 }
19306 #[doc = "Pull / Keep Enable Field"]
19307 pub mod PKE {
19308 pub const offset: u32 = 12;
19309 pub const mask: u32 = 0x01 << offset;
19310 pub mod R {}
19311 pub mod W {}
19312 pub mod RW {
19313 #[doc = "Pull/Keeper Disabled"]
19314 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
19315 #[doc = "Pull/Keeper Enabled"]
19316 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
19317 }
19318 }
19319 #[doc = "Pull / Keep Select Field"]
19320 pub mod PUE {
19321 pub const offset: u32 = 13;
19322 pub const mask: u32 = 0x01 << offset;
19323 pub mod R {}
19324 pub mod W {}
19325 pub mod RW {
19326 #[doc = "Keeper"]
19327 pub const PUE_0_KEEPER: u32 = 0;
19328 #[doc = "Pull"]
19329 pub const PUE_1_PULL: u32 = 0x01;
19330 }
19331 }
19332 #[doc = "Pull Up / Down Config. Field"]
19333 pub mod PUS {
19334 pub const offset: u32 = 14;
19335 pub const mask: u32 = 0x03 << offset;
19336 pub mod R {}
19337 pub mod W {}
19338 pub mod RW {
19339 #[doc = "100K Ohm Pull Down"]
19340 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
19341 #[doc = "47K Ohm Pull Up"]
19342 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
19343 #[doc = "100K Ohm Pull Up"]
19344 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
19345 #[doc = "22K Ohm Pull Up"]
19346 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
19347 }
19348 }
19349 #[doc = "Hyst. Enable Field"]
19350 pub mod HYS {
19351 pub const offset: u32 = 16;
19352 pub const mask: u32 = 0x01 << offset;
19353 pub mod R {}
19354 pub mod W {}
19355 pub mod RW {
19356 #[doc = "Hysteresis Disabled"]
19357 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
19358 #[doc = "Hysteresis Enabled"]
19359 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
19360 }
19361 }
19362}
19363#[doc = "SW_PAD_CTL_PAD_GPIO_B1_15 SW PAD Control Register"]
19364pub mod SW_PAD_CTL_PAD_GPIO_B1_15 {
19365 #[doc = "Slew Rate Field"]
19366 pub mod SRE {
19367 pub const offset: u32 = 0;
19368 pub const mask: u32 = 0x01 << offset;
19369 pub mod R {}
19370 pub mod W {}
19371 pub mod RW {
19372 #[doc = "Slow Slew Rate"]
19373 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
19374 #[doc = "Fast Slew Rate"]
19375 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
19376 }
19377 }
19378 #[doc = "Drive Strength Field"]
19379 pub mod DSE {
19380 pub const offset: u32 = 3;
19381 pub const mask: u32 = 0x07 << offset;
19382 pub mod R {}
19383 pub mod W {}
19384 pub mod RW {
19385 #[doc = "output driver disabled;"]
19386 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
19387 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
19388 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
19389 #[doc = "R0/2"]
19390 pub const DSE_2_R0_2: u32 = 0x02;
19391 #[doc = "R0/3"]
19392 pub const DSE_3_R0_3: u32 = 0x03;
19393 #[doc = "R0/4"]
19394 pub const DSE_4_R0_4: u32 = 0x04;
19395 #[doc = "R0/5"]
19396 pub const DSE_5_R0_5: u32 = 0x05;
19397 #[doc = "R0/6"]
19398 pub const DSE_6_R0_6: u32 = 0x06;
19399 #[doc = "R0/7"]
19400 pub const DSE_7_R0_7: u32 = 0x07;
19401 }
19402 }
19403 #[doc = "Speed Field"]
19404 pub mod SPEED {
19405 pub const offset: u32 = 6;
19406 pub const mask: u32 = 0x03 << offset;
19407 pub mod R {}
19408 pub mod W {}
19409 pub mod RW {
19410 #[doc = "low(50MHz)"]
19411 pub const SPEED_0_LOW_50MHZ: u32 = 0;
19412 #[doc = "medium(100MHz)"]
19413 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
19414 #[doc = "medium(100MHz)"]
19415 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
19416 #[doc = "max(200MHz)"]
19417 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
19418 }
19419 }
19420 #[doc = "Open Drain Enable Field"]
19421 pub mod ODE {
19422 pub const offset: u32 = 11;
19423 pub const mask: u32 = 0x01 << offset;
19424 pub mod R {}
19425 pub mod W {}
19426 pub mod RW {
19427 #[doc = "Open Drain Disabled"]
19428 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
19429 #[doc = "Open Drain Enabled"]
19430 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
19431 }
19432 }
19433 #[doc = "Pull / Keep Enable Field"]
19434 pub mod PKE {
19435 pub const offset: u32 = 12;
19436 pub const mask: u32 = 0x01 << offset;
19437 pub mod R {}
19438 pub mod W {}
19439 pub mod RW {
19440 #[doc = "Pull/Keeper Disabled"]
19441 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
19442 #[doc = "Pull/Keeper Enabled"]
19443 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
19444 }
19445 }
19446 #[doc = "Pull / Keep Select Field"]
19447 pub mod PUE {
19448 pub const offset: u32 = 13;
19449 pub const mask: u32 = 0x01 << offset;
19450 pub mod R {}
19451 pub mod W {}
19452 pub mod RW {
19453 #[doc = "Keeper"]
19454 pub const PUE_0_KEEPER: u32 = 0;
19455 #[doc = "Pull"]
19456 pub const PUE_1_PULL: u32 = 0x01;
19457 }
19458 }
19459 #[doc = "Pull Up / Down Config. Field"]
19460 pub mod PUS {
19461 pub const offset: u32 = 14;
19462 pub const mask: u32 = 0x03 << offset;
19463 pub mod R {}
19464 pub mod W {}
19465 pub mod RW {
19466 #[doc = "100K Ohm Pull Down"]
19467 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
19468 #[doc = "47K Ohm Pull Up"]
19469 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
19470 #[doc = "100K Ohm Pull Up"]
19471 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
19472 #[doc = "22K Ohm Pull Up"]
19473 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
19474 }
19475 }
19476 #[doc = "Hyst. Enable Field"]
19477 pub mod HYS {
19478 pub const offset: u32 = 16;
19479 pub const mask: u32 = 0x01 << offset;
19480 pub mod R {}
19481 pub mod W {}
19482 pub mod RW {
19483 #[doc = "Hysteresis Disabled"]
19484 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
19485 #[doc = "Hysteresis Enabled"]
19486 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
19487 }
19488 }
19489}
19490#[doc = "SW_PAD_CTL_PAD_GPIO_SD_B0_00 SW PAD Control Register"]
19491pub mod SW_PAD_CTL_PAD_GPIO_SD_B0_00 {
19492 #[doc = "Slew Rate Field"]
19493 pub mod SRE {
19494 pub const offset: u32 = 0;
19495 pub const mask: u32 = 0x01 << offset;
19496 pub mod R {}
19497 pub mod W {}
19498 pub mod RW {
19499 #[doc = "Slow Slew Rate"]
19500 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
19501 #[doc = "Fast Slew Rate"]
19502 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
19503 }
19504 }
19505 #[doc = "Drive Strength Field"]
19506 pub mod DSE {
19507 pub const offset: u32 = 3;
19508 pub const mask: u32 = 0x07 << offset;
19509 pub mod R {}
19510 pub mod W {}
19511 pub mod RW {
19512 #[doc = "output driver disabled;"]
19513 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
19514 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
19515 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
19516 #[doc = "R0/2"]
19517 pub const DSE_2_R0_2: u32 = 0x02;
19518 #[doc = "R0/3"]
19519 pub const DSE_3_R0_3: u32 = 0x03;
19520 #[doc = "R0/4"]
19521 pub const DSE_4_R0_4: u32 = 0x04;
19522 #[doc = "R0/5"]
19523 pub const DSE_5_R0_5: u32 = 0x05;
19524 #[doc = "R0/6"]
19525 pub const DSE_6_R0_6: u32 = 0x06;
19526 #[doc = "R0/7"]
19527 pub const DSE_7_R0_7: u32 = 0x07;
19528 }
19529 }
19530 #[doc = "Speed Field"]
19531 pub mod SPEED {
19532 pub const offset: u32 = 6;
19533 pub const mask: u32 = 0x03 << offset;
19534 pub mod R {}
19535 pub mod W {}
19536 pub mod RW {
19537 #[doc = "low(50MHz)"]
19538 pub const SPEED_0_LOW_50MHZ: u32 = 0;
19539 #[doc = "medium(100MHz)"]
19540 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
19541 #[doc = "medium(100MHz)"]
19542 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
19543 #[doc = "max(200MHz)"]
19544 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
19545 }
19546 }
19547 #[doc = "Open Drain Enable Field"]
19548 pub mod ODE {
19549 pub const offset: u32 = 11;
19550 pub const mask: u32 = 0x01 << offset;
19551 pub mod R {}
19552 pub mod W {}
19553 pub mod RW {
19554 #[doc = "Open Drain Disabled"]
19555 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
19556 #[doc = "Open Drain Enabled"]
19557 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
19558 }
19559 }
19560 #[doc = "Pull / Keep Enable Field"]
19561 pub mod PKE {
19562 pub const offset: u32 = 12;
19563 pub const mask: u32 = 0x01 << offset;
19564 pub mod R {}
19565 pub mod W {}
19566 pub mod RW {
19567 #[doc = "Pull/Keeper Disabled"]
19568 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
19569 #[doc = "Pull/Keeper Enabled"]
19570 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
19571 }
19572 }
19573 #[doc = "Pull / Keep Select Field"]
19574 pub mod PUE {
19575 pub const offset: u32 = 13;
19576 pub const mask: u32 = 0x01 << offset;
19577 pub mod R {}
19578 pub mod W {}
19579 pub mod RW {
19580 #[doc = "Keeper"]
19581 pub const PUE_0_KEEPER: u32 = 0;
19582 #[doc = "Pull"]
19583 pub const PUE_1_PULL: u32 = 0x01;
19584 }
19585 }
19586 #[doc = "Pull Up / Down Config. Field"]
19587 pub mod PUS {
19588 pub const offset: u32 = 14;
19589 pub const mask: u32 = 0x03 << offset;
19590 pub mod R {}
19591 pub mod W {}
19592 pub mod RW {
19593 #[doc = "100K Ohm Pull Down"]
19594 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
19595 #[doc = "47K Ohm Pull Up"]
19596 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
19597 #[doc = "100K Ohm Pull Up"]
19598 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
19599 #[doc = "22K Ohm Pull Up"]
19600 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
19601 }
19602 }
19603 #[doc = "Hyst. Enable Field"]
19604 pub mod HYS {
19605 pub const offset: u32 = 16;
19606 pub const mask: u32 = 0x01 << offset;
19607 pub mod R {}
19608 pub mod W {}
19609 pub mod RW {
19610 #[doc = "Hysteresis Disabled"]
19611 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
19612 #[doc = "Hysteresis Enabled"]
19613 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
19614 }
19615 }
19616}
19617#[doc = "SW_PAD_CTL_PAD_GPIO_SD_B0_01 SW PAD Control Register"]
19618pub mod SW_PAD_CTL_PAD_GPIO_SD_B0_01 {
19619 #[doc = "Slew Rate Field"]
19620 pub mod SRE {
19621 pub const offset: u32 = 0;
19622 pub const mask: u32 = 0x01 << offset;
19623 pub mod R {}
19624 pub mod W {}
19625 pub mod RW {
19626 #[doc = "Slow Slew Rate"]
19627 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
19628 #[doc = "Fast Slew Rate"]
19629 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
19630 }
19631 }
19632 #[doc = "Drive Strength Field"]
19633 pub mod DSE {
19634 pub const offset: u32 = 3;
19635 pub const mask: u32 = 0x07 << offset;
19636 pub mod R {}
19637 pub mod W {}
19638 pub mod RW {
19639 #[doc = "output driver disabled;"]
19640 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
19641 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
19642 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
19643 #[doc = "R0/2"]
19644 pub const DSE_2_R0_2: u32 = 0x02;
19645 #[doc = "R0/3"]
19646 pub const DSE_3_R0_3: u32 = 0x03;
19647 #[doc = "R0/4"]
19648 pub const DSE_4_R0_4: u32 = 0x04;
19649 #[doc = "R0/5"]
19650 pub const DSE_5_R0_5: u32 = 0x05;
19651 #[doc = "R0/6"]
19652 pub const DSE_6_R0_6: u32 = 0x06;
19653 #[doc = "R0/7"]
19654 pub const DSE_7_R0_7: u32 = 0x07;
19655 }
19656 }
19657 #[doc = "Speed Field"]
19658 pub mod SPEED {
19659 pub const offset: u32 = 6;
19660 pub const mask: u32 = 0x03 << offset;
19661 pub mod R {}
19662 pub mod W {}
19663 pub mod RW {
19664 #[doc = "low(50MHz)"]
19665 pub const SPEED_0_LOW_50MHZ: u32 = 0;
19666 #[doc = "medium(100MHz)"]
19667 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
19668 #[doc = "medium(100MHz)"]
19669 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
19670 #[doc = "max(200MHz)"]
19671 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
19672 }
19673 }
19674 #[doc = "Open Drain Enable Field"]
19675 pub mod ODE {
19676 pub const offset: u32 = 11;
19677 pub const mask: u32 = 0x01 << offset;
19678 pub mod R {}
19679 pub mod W {}
19680 pub mod RW {
19681 #[doc = "Open Drain Disabled"]
19682 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
19683 #[doc = "Open Drain Enabled"]
19684 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
19685 }
19686 }
19687 #[doc = "Pull / Keep Enable Field"]
19688 pub mod PKE {
19689 pub const offset: u32 = 12;
19690 pub const mask: u32 = 0x01 << offset;
19691 pub mod R {}
19692 pub mod W {}
19693 pub mod RW {
19694 #[doc = "Pull/Keeper Disabled"]
19695 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
19696 #[doc = "Pull/Keeper Enabled"]
19697 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
19698 }
19699 }
19700 #[doc = "Pull / Keep Select Field"]
19701 pub mod PUE {
19702 pub const offset: u32 = 13;
19703 pub const mask: u32 = 0x01 << offset;
19704 pub mod R {}
19705 pub mod W {}
19706 pub mod RW {
19707 #[doc = "Keeper"]
19708 pub const PUE_0_KEEPER: u32 = 0;
19709 #[doc = "Pull"]
19710 pub const PUE_1_PULL: u32 = 0x01;
19711 }
19712 }
19713 #[doc = "Pull Up / Down Config. Field"]
19714 pub mod PUS {
19715 pub const offset: u32 = 14;
19716 pub const mask: u32 = 0x03 << offset;
19717 pub mod R {}
19718 pub mod W {}
19719 pub mod RW {
19720 #[doc = "100K Ohm Pull Down"]
19721 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
19722 #[doc = "47K Ohm Pull Up"]
19723 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
19724 #[doc = "100K Ohm Pull Up"]
19725 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
19726 #[doc = "22K Ohm Pull Up"]
19727 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
19728 }
19729 }
19730 #[doc = "Hyst. Enable Field"]
19731 pub mod HYS {
19732 pub const offset: u32 = 16;
19733 pub const mask: u32 = 0x01 << offset;
19734 pub mod R {}
19735 pub mod W {}
19736 pub mod RW {
19737 #[doc = "Hysteresis Disabled"]
19738 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
19739 #[doc = "Hysteresis Enabled"]
19740 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
19741 }
19742 }
19743}
19744#[doc = "SW_PAD_CTL_PAD_GPIO_SD_B0_02 SW PAD Control Register"]
19745pub mod SW_PAD_CTL_PAD_GPIO_SD_B0_02 {
19746 #[doc = "Slew Rate Field"]
19747 pub mod SRE {
19748 pub const offset: u32 = 0;
19749 pub const mask: u32 = 0x01 << offset;
19750 pub mod R {}
19751 pub mod W {}
19752 pub mod RW {
19753 #[doc = "Slow Slew Rate"]
19754 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
19755 #[doc = "Fast Slew Rate"]
19756 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
19757 }
19758 }
19759 #[doc = "Drive Strength Field"]
19760 pub mod DSE {
19761 pub const offset: u32 = 3;
19762 pub const mask: u32 = 0x07 << offset;
19763 pub mod R {}
19764 pub mod W {}
19765 pub mod RW {
19766 #[doc = "output driver disabled;"]
19767 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
19768 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
19769 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
19770 #[doc = "R0/2"]
19771 pub const DSE_2_R0_2: u32 = 0x02;
19772 #[doc = "R0/3"]
19773 pub const DSE_3_R0_3: u32 = 0x03;
19774 #[doc = "R0/4"]
19775 pub const DSE_4_R0_4: u32 = 0x04;
19776 #[doc = "R0/5"]
19777 pub const DSE_5_R0_5: u32 = 0x05;
19778 #[doc = "R0/6"]
19779 pub const DSE_6_R0_6: u32 = 0x06;
19780 #[doc = "R0/7"]
19781 pub const DSE_7_R0_7: u32 = 0x07;
19782 }
19783 }
19784 #[doc = "Speed Field"]
19785 pub mod SPEED {
19786 pub const offset: u32 = 6;
19787 pub const mask: u32 = 0x03 << offset;
19788 pub mod R {}
19789 pub mod W {}
19790 pub mod RW {
19791 #[doc = "low(50MHz)"]
19792 pub const SPEED_0_LOW_50MHZ: u32 = 0;
19793 #[doc = "medium(100MHz)"]
19794 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
19795 #[doc = "medium(100MHz)"]
19796 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
19797 #[doc = "max(200MHz)"]
19798 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
19799 }
19800 }
19801 #[doc = "Open Drain Enable Field"]
19802 pub mod ODE {
19803 pub const offset: u32 = 11;
19804 pub const mask: u32 = 0x01 << offset;
19805 pub mod R {}
19806 pub mod W {}
19807 pub mod RW {
19808 #[doc = "Open Drain Disabled"]
19809 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
19810 #[doc = "Open Drain Enabled"]
19811 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
19812 }
19813 }
19814 #[doc = "Pull / Keep Enable Field"]
19815 pub mod PKE {
19816 pub const offset: u32 = 12;
19817 pub const mask: u32 = 0x01 << offset;
19818 pub mod R {}
19819 pub mod W {}
19820 pub mod RW {
19821 #[doc = "Pull/Keeper Disabled"]
19822 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
19823 #[doc = "Pull/Keeper Enabled"]
19824 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
19825 }
19826 }
19827 #[doc = "Pull / Keep Select Field"]
19828 pub mod PUE {
19829 pub const offset: u32 = 13;
19830 pub const mask: u32 = 0x01 << offset;
19831 pub mod R {}
19832 pub mod W {}
19833 pub mod RW {
19834 #[doc = "Keeper"]
19835 pub const PUE_0_KEEPER: u32 = 0;
19836 #[doc = "Pull"]
19837 pub const PUE_1_PULL: u32 = 0x01;
19838 }
19839 }
19840 #[doc = "Pull Up / Down Config. Field"]
19841 pub mod PUS {
19842 pub const offset: u32 = 14;
19843 pub const mask: u32 = 0x03 << offset;
19844 pub mod R {}
19845 pub mod W {}
19846 pub mod RW {
19847 #[doc = "100K Ohm Pull Down"]
19848 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
19849 #[doc = "47K Ohm Pull Up"]
19850 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
19851 #[doc = "100K Ohm Pull Up"]
19852 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
19853 #[doc = "22K Ohm Pull Up"]
19854 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
19855 }
19856 }
19857 #[doc = "Hyst. Enable Field"]
19858 pub mod HYS {
19859 pub const offset: u32 = 16;
19860 pub const mask: u32 = 0x01 << offset;
19861 pub mod R {}
19862 pub mod W {}
19863 pub mod RW {
19864 #[doc = "Hysteresis Disabled"]
19865 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
19866 #[doc = "Hysteresis Enabled"]
19867 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
19868 }
19869 }
19870}
19871#[doc = "SW_PAD_CTL_PAD_GPIO_SD_B0_03 SW PAD Control Register"]
19872pub mod SW_PAD_CTL_PAD_GPIO_SD_B0_03 {
19873 #[doc = "Slew Rate Field"]
19874 pub mod SRE {
19875 pub const offset: u32 = 0;
19876 pub const mask: u32 = 0x01 << offset;
19877 pub mod R {}
19878 pub mod W {}
19879 pub mod RW {
19880 #[doc = "Slow Slew Rate"]
19881 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
19882 #[doc = "Fast Slew Rate"]
19883 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
19884 }
19885 }
19886 #[doc = "Drive Strength Field"]
19887 pub mod DSE {
19888 pub const offset: u32 = 3;
19889 pub const mask: u32 = 0x07 << offset;
19890 pub mod R {}
19891 pub mod W {}
19892 pub mod RW {
19893 #[doc = "output driver disabled;"]
19894 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
19895 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
19896 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
19897 #[doc = "R0/2"]
19898 pub const DSE_2_R0_2: u32 = 0x02;
19899 #[doc = "R0/3"]
19900 pub const DSE_3_R0_3: u32 = 0x03;
19901 #[doc = "R0/4"]
19902 pub const DSE_4_R0_4: u32 = 0x04;
19903 #[doc = "R0/5"]
19904 pub const DSE_5_R0_5: u32 = 0x05;
19905 #[doc = "R0/6"]
19906 pub const DSE_6_R0_6: u32 = 0x06;
19907 #[doc = "R0/7"]
19908 pub const DSE_7_R0_7: u32 = 0x07;
19909 }
19910 }
19911 #[doc = "Speed Field"]
19912 pub mod SPEED {
19913 pub const offset: u32 = 6;
19914 pub const mask: u32 = 0x03 << offset;
19915 pub mod R {}
19916 pub mod W {}
19917 pub mod RW {
19918 #[doc = "low(50MHz)"]
19919 pub const SPEED_0_LOW_50MHZ: u32 = 0;
19920 #[doc = "medium(100MHz)"]
19921 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
19922 #[doc = "medium(100MHz)"]
19923 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
19924 #[doc = "max(200MHz)"]
19925 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
19926 }
19927 }
19928 #[doc = "Open Drain Enable Field"]
19929 pub mod ODE {
19930 pub const offset: u32 = 11;
19931 pub const mask: u32 = 0x01 << offset;
19932 pub mod R {}
19933 pub mod W {}
19934 pub mod RW {
19935 #[doc = "Open Drain Disabled"]
19936 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
19937 #[doc = "Open Drain Enabled"]
19938 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
19939 }
19940 }
19941 #[doc = "Pull / Keep Enable Field"]
19942 pub mod PKE {
19943 pub const offset: u32 = 12;
19944 pub const mask: u32 = 0x01 << offset;
19945 pub mod R {}
19946 pub mod W {}
19947 pub mod RW {
19948 #[doc = "Pull/Keeper Disabled"]
19949 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
19950 #[doc = "Pull/Keeper Enabled"]
19951 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
19952 }
19953 }
19954 #[doc = "Pull / Keep Select Field"]
19955 pub mod PUE {
19956 pub const offset: u32 = 13;
19957 pub const mask: u32 = 0x01 << offset;
19958 pub mod R {}
19959 pub mod W {}
19960 pub mod RW {
19961 #[doc = "Keeper"]
19962 pub const PUE_0_KEEPER: u32 = 0;
19963 #[doc = "Pull"]
19964 pub const PUE_1_PULL: u32 = 0x01;
19965 }
19966 }
19967 #[doc = "Pull Up / Down Config. Field"]
19968 pub mod PUS {
19969 pub const offset: u32 = 14;
19970 pub const mask: u32 = 0x03 << offset;
19971 pub mod R {}
19972 pub mod W {}
19973 pub mod RW {
19974 #[doc = "100K Ohm Pull Down"]
19975 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
19976 #[doc = "47K Ohm Pull Up"]
19977 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
19978 #[doc = "100K Ohm Pull Up"]
19979 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
19980 #[doc = "22K Ohm Pull Up"]
19981 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
19982 }
19983 }
19984 #[doc = "Hyst. Enable Field"]
19985 pub mod HYS {
19986 pub const offset: u32 = 16;
19987 pub const mask: u32 = 0x01 << offset;
19988 pub mod R {}
19989 pub mod W {}
19990 pub mod RW {
19991 #[doc = "Hysteresis Disabled"]
19992 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
19993 #[doc = "Hysteresis Enabled"]
19994 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
19995 }
19996 }
19997}
19998#[doc = "SW_PAD_CTL_PAD_GPIO_SD_B0_04 SW PAD Control Register"]
19999pub mod SW_PAD_CTL_PAD_GPIO_SD_B0_04 {
20000 #[doc = "Slew Rate Field"]
20001 pub mod SRE {
20002 pub const offset: u32 = 0;
20003 pub const mask: u32 = 0x01 << offset;
20004 pub mod R {}
20005 pub mod W {}
20006 pub mod RW {
20007 #[doc = "Slow Slew Rate"]
20008 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
20009 #[doc = "Fast Slew Rate"]
20010 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
20011 }
20012 }
20013 #[doc = "Drive Strength Field"]
20014 pub mod DSE {
20015 pub const offset: u32 = 3;
20016 pub const mask: u32 = 0x07 << offset;
20017 pub mod R {}
20018 pub mod W {}
20019 pub mod RW {
20020 #[doc = "output driver disabled;"]
20021 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
20022 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
20023 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
20024 #[doc = "R0/2"]
20025 pub const DSE_2_R0_2: u32 = 0x02;
20026 #[doc = "R0/3"]
20027 pub const DSE_3_R0_3: u32 = 0x03;
20028 #[doc = "R0/4"]
20029 pub const DSE_4_R0_4: u32 = 0x04;
20030 #[doc = "R0/5"]
20031 pub const DSE_5_R0_5: u32 = 0x05;
20032 #[doc = "R0/6"]
20033 pub const DSE_6_R0_6: u32 = 0x06;
20034 #[doc = "R0/7"]
20035 pub const DSE_7_R0_7: u32 = 0x07;
20036 }
20037 }
20038 #[doc = "Speed Field"]
20039 pub mod SPEED {
20040 pub const offset: u32 = 6;
20041 pub const mask: u32 = 0x03 << offset;
20042 pub mod R {}
20043 pub mod W {}
20044 pub mod RW {
20045 #[doc = "low(50MHz)"]
20046 pub const SPEED_0_LOW_50MHZ: u32 = 0;
20047 #[doc = "medium(100MHz)"]
20048 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
20049 #[doc = "medium(100MHz)"]
20050 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
20051 #[doc = "max(200MHz)"]
20052 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
20053 }
20054 }
20055 #[doc = "Open Drain Enable Field"]
20056 pub mod ODE {
20057 pub const offset: u32 = 11;
20058 pub const mask: u32 = 0x01 << offset;
20059 pub mod R {}
20060 pub mod W {}
20061 pub mod RW {
20062 #[doc = "Open Drain Disabled"]
20063 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
20064 #[doc = "Open Drain Enabled"]
20065 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
20066 }
20067 }
20068 #[doc = "Pull / Keep Enable Field"]
20069 pub mod PKE {
20070 pub const offset: u32 = 12;
20071 pub const mask: u32 = 0x01 << offset;
20072 pub mod R {}
20073 pub mod W {}
20074 pub mod RW {
20075 #[doc = "Pull/Keeper Disabled"]
20076 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
20077 #[doc = "Pull/Keeper Enabled"]
20078 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
20079 }
20080 }
20081 #[doc = "Pull / Keep Select Field"]
20082 pub mod PUE {
20083 pub const offset: u32 = 13;
20084 pub const mask: u32 = 0x01 << offset;
20085 pub mod R {}
20086 pub mod W {}
20087 pub mod RW {
20088 #[doc = "Keeper"]
20089 pub const PUE_0_KEEPER: u32 = 0;
20090 #[doc = "Pull"]
20091 pub const PUE_1_PULL: u32 = 0x01;
20092 }
20093 }
20094 #[doc = "Pull Up / Down Config. Field"]
20095 pub mod PUS {
20096 pub const offset: u32 = 14;
20097 pub const mask: u32 = 0x03 << offset;
20098 pub mod R {}
20099 pub mod W {}
20100 pub mod RW {
20101 #[doc = "100K Ohm Pull Down"]
20102 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
20103 #[doc = "47K Ohm Pull Up"]
20104 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
20105 #[doc = "100K Ohm Pull Up"]
20106 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
20107 #[doc = "22K Ohm Pull Up"]
20108 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
20109 }
20110 }
20111 #[doc = "Hyst. Enable Field"]
20112 pub mod HYS {
20113 pub const offset: u32 = 16;
20114 pub const mask: u32 = 0x01 << offset;
20115 pub mod R {}
20116 pub mod W {}
20117 pub mod RW {
20118 #[doc = "Hysteresis Disabled"]
20119 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
20120 #[doc = "Hysteresis Enabled"]
20121 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
20122 }
20123 }
20124}
20125#[doc = "SW_PAD_CTL_PAD_GPIO_SD_B0_05 SW PAD Control Register"]
20126pub mod SW_PAD_CTL_PAD_GPIO_SD_B0_05 {
20127 #[doc = "Slew Rate Field"]
20128 pub mod SRE {
20129 pub const offset: u32 = 0;
20130 pub const mask: u32 = 0x01 << offset;
20131 pub mod R {}
20132 pub mod W {}
20133 pub mod RW {
20134 #[doc = "Slow Slew Rate"]
20135 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
20136 #[doc = "Fast Slew Rate"]
20137 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
20138 }
20139 }
20140 #[doc = "Drive Strength Field"]
20141 pub mod DSE {
20142 pub const offset: u32 = 3;
20143 pub const mask: u32 = 0x07 << offset;
20144 pub mod R {}
20145 pub mod W {}
20146 pub mod RW {
20147 #[doc = "output driver disabled;"]
20148 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
20149 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
20150 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
20151 #[doc = "R0/2"]
20152 pub const DSE_2_R0_2: u32 = 0x02;
20153 #[doc = "R0/3"]
20154 pub const DSE_3_R0_3: u32 = 0x03;
20155 #[doc = "R0/4"]
20156 pub const DSE_4_R0_4: u32 = 0x04;
20157 #[doc = "R0/5"]
20158 pub const DSE_5_R0_5: u32 = 0x05;
20159 #[doc = "R0/6"]
20160 pub const DSE_6_R0_6: u32 = 0x06;
20161 #[doc = "R0/7"]
20162 pub const DSE_7_R0_7: u32 = 0x07;
20163 }
20164 }
20165 #[doc = "Speed Field"]
20166 pub mod SPEED {
20167 pub const offset: u32 = 6;
20168 pub const mask: u32 = 0x03 << offset;
20169 pub mod R {}
20170 pub mod W {}
20171 pub mod RW {
20172 #[doc = "low(50MHz)"]
20173 pub const SPEED_0_LOW_50MHZ: u32 = 0;
20174 #[doc = "medium(100MHz)"]
20175 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
20176 #[doc = "medium(100MHz)"]
20177 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
20178 #[doc = "max(200MHz)"]
20179 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
20180 }
20181 }
20182 #[doc = "Open Drain Enable Field"]
20183 pub mod ODE {
20184 pub const offset: u32 = 11;
20185 pub const mask: u32 = 0x01 << offset;
20186 pub mod R {}
20187 pub mod W {}
20188 pub mod RW {
20189 #[doc = "Open Drain Disabled"]
20190 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
20191 #[doc = "Open Drain Enabled"]
20192 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
20193 }
20194 }
20195 #[doc = "Pull / Keep Enable Field"]
20196 pub mod PKE {
20197 pub const offset: u32 = 12;
20198 pub const mask: u32 = 0x01 << offset;
20199 pub mod R {}
20200 pub mod W {}
20201 pub mod RW {
20202 #[doc = "Pull/Keeper Disabled"]
20203 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
20204 #[doc = "Pull/Keeper Enabled"]
20205 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
20206 }
20207 }
20208 #[doc = "Pull / Keep Select Field"]
20209 pub mod PUE {
20210 pub const offset: u32 = 13;
20211 pub const mask: u32 = 0x01 << offset;
20212 pub mod R {}
20213 pub mod W {}
20214 pub mod RW {
20215 #[doc = "Keeper"]
20216 pub const PUE_0_KEEPER: u32 = 0;
20217 #[doc = "Pull"]
20218 pub const PUE_1_PULL: u32 = 0x01;
20219 }
20220 }
20221 #[doc = "Pull Up / Down Config. Field"]
20222 pub mod PUS {
20223 pub const offset: u32 = 14;
20224 pub const mask: u32 = 0x03 << offset;
20225 pub mod R {}
20226 pub mod W {}
20227 pub mod RW {
20228 #[doc = "100K Ohm Pull Down"]
20229 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
20230 #[doc = "47K Ohm Pull Up"]
20231 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
20232 #[doc = "100K Ohm Pull Up"]
20233 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
20234 #[doc = "22K Ohm Pull Up"]
20235 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
20236 }
20237 }
20238 #[doc = "Hyst. Enable Field"]
20239 pub mod HYS {
20240 pub const offset: u32 = 16;
20241 pub const mask: u32 = 0x01 << offset;
20242 pub mod R {}
20243 pub mod W {}
20244 pub mod RW {
20245 #[doc = "Hysteresis Disabled"]
20246 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
20247 #[doc = "Hysteresis Enabled"]
20248 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
20249 }
20250 }
20251}
20252#[doc = "SW_PAD_CTL_PAD_GPIO_SD_B1_00 SW PAD Control Register"]
20253pub mod SW_PAD_CTL_PAD_GPIO_SD_B1_00 {
20254 #[doc = "Slew Rate Field"]
20255 pub mod SRE {
20256 pub const offset: u32 = 0;
20257 pub const mask: u32 = 0x01 << offset;
20258 pub mod R {}
20259 pub mod W {}
20260 pub mod RW {
20261 #[doc = "Slow Slew Rate"]
20262 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
20263 #[doc = "Fast Slew Rate"]
20264 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
20265 }
20266 }
20267 #[doc = "Drive Strength Field"]
20268 pub mod DSE {
20269 pub const offset: u32 = 3;
20270 pub const mask: u32 = 0x07 << offset;
20271 pub mod R {}
20272 pub mod W {}
20273 pub mod RW {
20274 #[doc = "output driver disabled;"]
20275 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
20276 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
20277 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
20278 #[doc = "R0/2"]
20279 pub const DSE_2_R0_2: u32 = 0x02;
20280 #[doc = "R0/3"]
20281 pub const DSE_3_R0_3: u32 = 0x03;
20282 #[doc = "R0/4"]
20283 pub const DSE_4_R0_4: u32 = 0x04;
20284 #[doc = "R0/5"]
20285 pub const DSE_5_R0_5: u32 = 0x05;
20286 #[doc = "R0/6"]
20287 pub const DSE_6_R0_6: u32 = 0x06;
20288 #[doc = "R0/7"]
20289 pub const DSE_7_R0_7: u32 = 0x07;
20290 }
20291 }
20292 #[doc = "Speed Field"]
20293 pub mod SPEED {
20294 pub const offset: u32 = 6;
20295 pub const mask: u32 = 0x03 << offset;
20296 pub mod R {}
20297 pub mod W {}
20298 pub mod RW {
20299 #[doc = "low(50MHz)"]
20300 pub const SPEED_0_LOW_50MHZ: u32 = 0;
20301 #[doc = "medium(100MHz)"]
20302 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
20303 #[doc = "medium(100MHz)"]
20304 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
20305 #[doc = "max(200MHz)"]
20306 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
20307 }
20308 }
20309 #[doc = "Open Drain Enable Field"]
20310 pub mod ODE {
20311 pub const offset: u32 = 11;
20312 pub const mask: u32 = 0x01 << offset;
20313 pub mod R {}
20314 pub mod W {}
20315 pub mod RW {
20316 #[doc = "Open Drain Disabled"]
20317 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
20318 #[doc = "Open Drain Enabled"]
20319 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
20320 }
20321 }
20322 #[doc = "Pull / Keep Enable Field"]
20323 pub mod PKE {
20324 pub const offset: u32 = 12;
20325 pub const mask: u32 = 0x01 << offset;
20326 pub mod R {}
20327 pub mod W {}
20328 pub mod RW {
20329 #[doc = "Pull/Keeper Disabled"]
20330 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
20331 #[doc = "Pull/Keeper Enabled"]
20332 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
20333 }
20334 }
20335 #[doc = "Pull / Keep Select Field"]
20336 pub mod PUE {
20337 pub const offset: u32 = 13;
20338 pub const mask: u32 = 0x01 << offset;
20339 pub mod R {}
20340 pub mod W {}
20341 pub mod RW {
20342 #[doc = "Keeper"]
20343 pub const PUE_0_KEEPER: u32 = 0;
20344 #[doc = "Pull"]
20345 pub const PUE_1_PULL: u32 = 0x01;
20346 }
20347 }
20348 #[doc = "Pull Up / Down Config. Field"]
20349 pub mod PUS {
20350 pub const offset: u32 = 14;
20351 pub const mask: u32 = 0x03 << offset;
20352 pub mod R {}
20353 pub mod W {}
20354 pub mod RW {
20355 #[doc = "100K Ohm Pull Down"]
20356 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
20357 #[doc = "47K Ohm Pull Up"]
20358 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
20359 #[doc = "100K Ohm Pull Up"]
20360 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
20361 #[doc = "22K Ohm Pull Up"]
20362 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
20363 }
20364 }
20365 #[doc = "Hyst. Enable Field"]
20366 pub mod HYS {
20367 pub const offset: u32 = 16;
20368 pub const mask: u32 = 0x01 << offset;
20369 pub mod R {}
20370 pub mod W {}
20371 pub mod RW {
20372 #[doc = "Hysteresis Disabled"]
20373 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
20374 #[doc = "Hysteresis Enabled"]
20375 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
20376 }
20377 }
20378}
20379#[doc = "SW_PAD_CTL_PAD_GPIO_SD_B1_01 SW PAD Control Register"]
20380pub mod SW_PAD_CTL_PAD_GPIO_SD_B1_01 {
20381 #[doc = "Slew Rate Field"]
20382 pub mod SRE {
20383 pub const offset: u32 = 0;
20384 pub const mask: u32 = 0x01 << offset;
20385 pub mod R {}
20386 pub mod W {}
20387 pub mod RW {
20388 #[doc = "Slow Slew Rate"]
20389 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
20390 #[doc = "Fast Slew Rate"]
20391 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
20392 }
20393 }
20394 #[doc = "Drive Strength Field"]
20395 pub mod DSE {
20396 pub const offset: u32 = 3;
20397 pub const mask: u32 = 0x07 << offset;
20398 pub mod R {}
20399 pub mod W {}
20400 pub mod RW {
20401 #[doc = "output driver disabled;"]
20402 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
20403 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
20404 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
20405 #[doc = "R0/2"]
20406 pub const DSE_2_R0_2: u32 = 0x02;
20407 #[doc = "R0/3"]
20408 pub const DSE_3_R0_3: u32 = 0x03;
20409 #[doc = "R0/4"]
20410 pub const DSE_4_R0_4: u32 = 0x04;
20411 #[doc = "R0/5"]
20412 pub const DSE_5_R0_5: u32 = 0x05;
20413 #[doc = "R0/6"]
20414 pub const DSE_6_R0_6: u32 = 0x06;
20415 #[doc = "R0/7"]
20416 pub const DSE_7_R0_7: u32 = 0x07;
20417 }
20418 }
20419 #[doc = "Speed Field"]
20420 pub mod SPEED {
20421 pub const offset: u32 = 6;
20422 pub const mask: u32 = 0x03 << offset;
20423 pub mod R {}
20424 pub mod W {}
20425 pub mod RW {
20426 #[doc = "low(50MHz)"]
20427 pub const SPEED_0_LOW_50MHZ: u32 = 0;
20428 #[doc = "medium(100MHz)"]
20429 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
20430 #[doc = "medium(100MHz)"]
20431 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
20432 #[doc = "max(200MHz)"]
20433 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
20434 }
20435 }
20436 #[doc = "Open Drain Enable Field"]
20437 pub mod ODE {
20438 pub const offset: u32 = 11;
20439 pub const mask: u32 = 0x01 << offset;
20440 pub mod R {}
20441 pub mod W {}
20442 pub mod RW {
20443 #[doc = "Open Drain Disabled"]
20444 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
20445 #[doc = "Open Drain Enabled"]
20446 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
20447 }
20448 }
20449 #[doc = "Pull / Keep Enable Field"]
20450 pub mod PKE {
20451 pub const offset: u32 = 12;
20452 pub const mask: u32 = 0x01 << offset;
20453 pub mod R {}
20454 pub mod W {}
20455 pub mod RW {
20456 #[doc = "Pull/Keeper Disabled"]
20457 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
20458 #[doc = "Pull/Keeper Enabled"]
20459 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
20460 }
20461 }
20462 #[doc = "Pull / Keep Select Field"]
20463 pub mod PUE {
20464 pub const offset: u32 = 13;
20465 pub const mask: u32 = 0x01 << offset;
20466 pub mod R {}
20467 pub mod W {}
20468 pub mod RW {
20469 #[doc = "Keeper"]
20470 pub const PUE_0_KEEPER: u32 = 0;
20471 #[doc = "Pull"]
20472 pub const PUE_1_PULL: u32 = 0x01;
20473 }
20474 }
20475 #[doc = "Pull Up / Down Config. Field"]
20476 pub mod PUS {
20477 pub const offset: u32 = 14;
20478 pub const mask: u32 = 0x03 << offset;
20479 pub mod R {}
20480 pub mod W {}
20481 pub mod RW {
20482 #[doc = "100K Ohm Pull Down"]
20483 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
20484 #[doc = "47K Ohm Pull Up"]
20485 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
20486 #[doc = "100K Ohm Pull Up"]
20487 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
20488 #[doc = "22K Ohm Pull Up"]
20489 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
20490 }
20491 }
20492 #[doc = "Hyst. Enable Field"]
20493 pub mod HYS {
20494 pub const offset: u32 = 16;
20495 pub const mask: u32 = 0x01 << offset;
20496 pub mod R {}
20497 pub mod W {}
20498 pub mod RW {
20499 #[doc = "Hysteresis Disabled"]
20500 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
20501 #[doc = "Hysteresis Enabled"]
20502 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
20503 }
20504 }
20505}
20506#[doc = "SW_PAD_CTL_PAD_GPIO_SD_B1_02 SW PAD Control Register"]
20507pub mod SW_PAD_CTL_PAD_GPIO_SD_B1_02 {
20508 #[doc = "Slew Rate Field"]
20509 pub mod SRE {
20510 pub const offset: u32 = 0;
20511 pub const mask: u32 = 0x01 << offset;
20512 pub mod R {}
20513 pub mod W {}
20514 pub mod RW {
20515 #[doc = "Slow Slew Rate"]
20516 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
20517 #[doc = "Fast Slew Rate"]
20518 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
20519 }
20520 }
20521 #[doc = "Drive Strength Field"]
20522 pub mod DSE {
20523 pub const offset: u32 = 3;
20524 pub const mask: u32 = 0x07 << offset;
20525 pub mod R {}
20526 pub mod W {}
20527 pub mod RW {
20528 #[doc = "output driver disabled;"]
20529 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
20530 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
20531 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
20532 #[doc = "R0/2"]
20533 pub const DSE_2_R0_2: u32 = 0x02;
20534 #[doc = "R0/3"]
20535 pub const DSE_3_R0_3: u32 = 0x03;
20536 #[doc = "R0/4"]
20537 pub const DSE_4_R0_4: u32 = 0x04;
20538 #[doc = "R0/5"]
20539 pub const DSE_5_R0_5: u32 = 0x05;
20540 #[doc = "R0/6"]
20541 pub const DSE_6_R0_6: u32 = 0x06;
20542 #[doc = "R0/7"]
20543 pub const DSE_7_R0_7: u32 = 0x07;
20544 }
20545 }
20546 #[doc = "Speed Field"]
20547 pub mod SPEED {
20548 pub const offset: u32 = 6;
20549 pub const mask: u32 = 0x03 << offset;
20550 pub mod R {}
20551 pub mod W {}
20552 pub mod RW {
20553 #[doc = "low(50MHz)"]
20554 pub const SPEED_0_LOW_50MHZ: u32 = 0;
20555 #[doc = "medium(100MHz)"]
20556 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
20557 #[doc = "medium(100MHz)"]
20558 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
20559 #[doc = "max(200MHz)"]
20560 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
20561 }
20562 }
20563 #[doc = "Open Drain Enable Field"]
20564 pub mod ODE {
20565 pub const offset: u32 = 11;
20566 pub const mask: u32 = 0x01 << offset;
20567 pub mod R {}
20568 pub mod W {}
20569 pub mod RW {
20570 #[doc = "Open Drain Disabled"]
20571 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
20572 #[doc = "Open Drain Enabled"]
20573 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
20574 }
20575 }
20576 #[doc = "Pull / Keep Enable Field"]
20577 pub mod PKE {
20578 pub const offset: u32 = 12;
20579 pub const mask: u32 = 0x01 << offset;
20580 pub mod R {}
20581 pub mod W {}
20582 pub mod RW {
20583 #[doc = "Pull/Keeper Disabled"]
20584 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
20585 #[doc = "Pull/Keeper Enabled"]
20586 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
20587 }
20588 }
20589 #[doc = "Pull / Keep Select Field"]
20590 pub mod PUE {
20591 pub const offset: u32 = 13;
20592 pub const mask: u32 = 0x01 << offset;
20593 pub mod R {}
20594 pub mod W {}
20595 pub mod RW {
20596 #[doc = "Keeper"]
20597 pub const PUE_0_KEEPER: u32 = 0;
20598 #[doc = "Pull"]
20599 pub const PUE_1_PULL: u32 = 0x01;
20600 }
20601 }
20602 #[doc = "Pull Up / Down Config. Field"]
20603 pub mod PUS {
20604 pub const offset: u32 = 14;
20605 pub const mask: u32 = 0x03 << offset;
20606 pub mod R {}
20607 pub mod W {}
20608 pub mod RW {
20609 #[doc = "100K Ohm Pull Down"]
20610 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
20611 #[doc = "47K Ohm Pull Up"]
20612 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
20613 #[doc = "100K Ohm Pull Up"]
20614 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
20615 #[doc = "22K Ohm Pull Up"]
20616 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
20617 }
20618 }
20619 #[doc = "Hyst. Enable Field"]
20620 pub mod HYS {
20621 pub const offset: u32 = 16;
20622 pub const mask: u32 = 0x01 << offset;
20623 pub mod R {}
20624 pub mod W {}
20625 pub mod RW {
20626 #[doc = "Hysteresis Disabled"]
20627 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
20628 #[doc = "Hysteresis Enabled"]
20629 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
20630 }
20631 }
20632}
20633#[doc = "SW_PAD_CTL_PAD_GPIO_SD_B1_03 SW PAD Control Register"]
20634pub mod SW_PAD_CTL_PAD_GPIO_SD_B1_03 {
20635 #[doc = "Slew Rate Field"]
20636 pub mod SRE {
20637 pub const offset: u32 = 0;
20638 pub const mask: u32 = 0x01 << offset;
20639 pub mod R {}
20640 pub mod W {}
20641 pub mod RW {
20642 #[doc = "Slow Slew Rate"]
20643 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
20644 #[doc = "Fast Slew Rate"]
20645 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
20646 }
20647 }
20648 #[doc = "Drive Strength Field"]
20649 pub mod DSE {
20650 pub const offset: u32 = 3;
20651 pub const mask: u32 = 0x07 << offset;
20652 pub mod R {}
20653 pub mod W {}
20654 pub mod RW {
20655 #[doc = "output driver disabled;"]
20656 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
20657 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
20658 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
20659 #[doc = "R0/2"]
20660 pub const DSE_2_R0_2: u32 = 0x02;
20661 #[doc = "R0/3"]
20662 pub const DSE_3_R0_3: u32 = 0x03;
20663 #[doc = "R0/4"]
20664 pub const DSE_4_R0_4: u32 = 0x04;
20665 #[doc = "R0/5"]
20666 pub const DSE_5_R0_5: u32 = 0x05;
20667 #[doc = "R0/6"]
20668 pub const DSE_6_R0_6: u32 = 0x06;
20669 #[doc = "R0/7"]
20670 pub const DSE_7_R0_7: u32 = 0x07;
20671 }
20672 }
20673 #[doc = "Speed Field"]
20674 pub mod SPEED {
20675 pub const offset: u32 = 6;
20676 pub const mask: u32 = 0x03 << offset;
20677 pub mod R {}
20678 pub mod W {}
20679 pub mod RW {
20680 #[doc = "low(50MHz)"]
20681 pub const SPEED_0_LOW_50MHZ: u32 = 0;
20682 #[doc = "medium(100MHz)"]
20683 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
20684 #[doc = "medium(100MHz)"]
20685 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
20686 #[doc = "max(200MHz)"]
20687 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
20688 }
20689 }
20690 #[doc = "Open Drain Enable Field"]
20691 pub mod ODE {
20692 pub const offset: u32 = 11;
20693 pub const mask: u32 = 0x01 << offset;
20694 pub mod R {}
20695 pub mod W {}
20696 pub mod RW {
20697 #[doc = "Open Drain Disabled"]
20698 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
20699 #[doc = "Open Drain Enabled"]
20700 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
20701 }
20702 }
20703 #[doc = "Pull / Keep Enable Field"]
20704 pub mod PKE {
20705 pub const offset: u32 = 12;
20706 pub const mask: u32 = 0x01 << offset;
20707 pub mod R {}
20708 pub mod W {}
20709 pub mod RW {
20710 #[doc = "Pull/Keeper Disabled"]
20711 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
20712 #[doc = "Pull/Keeper Enabled"]
20713 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
20714 }
20715 }
20716 #[doc = "Pull / Keep Select Field"]
20717 pub mod PUE {
20718 pub const offset: u32 = 13;
20719 pub const mask: u32 = 0x01 << offset;
20720 pub mod R {}
20721 pub mod W {}
20722 pub mod RW {
20723 #[doc = "Keeper"]
20724 pub const PUE_0_KEEPER: u32 = 0;
20725 #[doc = "Pull"]
20726 pub const PUE_1_PULL: u32 = 0x01;
20727 }
20728 }
20729 #[doc = "Pull Up / Down Config. Field"]
20730 pub mod PUS {
20731 pub const offset: u32 = 14;
20732 pub const mask: u32 = 0x03 << offset;
20733 pub mod R {}
20734 pub mod W {}
20735 pub mod RW {
20736 #[doc = "100K Ohm Pull Down"]
20737 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
20738 #[doc = "47K Ohm Pull Up"]
20739 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
20740 #[doc = "100K Ohm Pull Up"]
20741 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
20742 #[doc = "22K Ohm Pull Up"]
20743 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
20744 }
20745 }
20746 #[doc = "Hyst. Enable Field"]
20747 pub mod HYS {
20748 pub const offset: u32 = 16;
20749 pub const mask: u32 = 0x01 << offset;
20750 pub mod R {}
20751 pub mod W {}
20752 pub mod RW {
20753 #[doc = "Hysteresis Disabled"]
20754 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
20755 #[doc = "Hysteresis Enabled"]
20756 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
20757 }
20758 }
20759}
20760#[doc = "SW_PAD_CTL_PAD_GPIO_SD_B1_04 SW PAD Control Register"]
20761pub mod SW_PAD_CTL_PAD_GPIO_SD_B1_04 {
20762 #[doc = "Slew Rate Field"]
20763 pub mod SRE {
20764 pub const offset: u32 = 0;
20765 pub const mask: u32 = 0x01 << offset;
20766 pub mod R {}
20767 pub mod W {}
20768 pub mod RW {
20769 #[doc = "Slow Slew Rate"]
20770 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
20771 #[doc = "Fast Slew Rate"]
20772 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
20773 }
20774 }
20775 #[doc = "Drive Strength Field"]
20776 pub mod DSE {
20777 pub const offset: u32 = 3;
20778 pub const mask: u32 = 0x07 << offset;
20779 pub mod R {}
20780 pub mod W {}
20781 pub mod RW {
20782 #[doc = "output driver disabled;"]
20783 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
20784 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
20785 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
20786 #[doc = "R0/2"]
20787 pub const DSE_2_R0_2: u32 = 0x02;
20788 #[doc = "R0/3"]
20789 pub const DSE_3_R0_3: u32 = 0x03;
20790 #[doc = "R0/4"]
20791 pub const DSE_4_R0_4: u32 = 0x04;
20792 #[doc = "R0/5"]
20793 pub const DSE_5_R0_5: u32 = 0x05;
20794 #[doc = "R0/6"]
20795 pub const DSE_6_R0_6: u32 = 0x06;
20796 #[doc = "R0/7"]
20797 pub const DSE_7_R0_7: u32 = 0x07;
20798 }
20799 }
20800 #[doc = "Speed Field"]
20801 pub mod SPEED {
20802 pub const offset: u32 = 6;
20803 pub const mask: u32 = 0x03 << offset;
20804 pub mod R {}
20805 pub mod W {}
20806 pub mod RW {
20807 #[doc = "low(50MHz)"]
20808 pub const SPEED_0_LOW_50MHZ: u32 = 0;
20809 #[doc = "medium(100MHz)"]
20810 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
20811 #[doc = "medium(100MHz)"]
20812 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
20813 #[doc = "max(200MHz)"]
20814 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
20815 }
20816 }
20817 #[doc = "Open Drain Enable Field"]
20818 pub mod ODE {
20819 pub const offset: u32 = 11;
20820 pub const mask: u32 = 0x01 << offset;
20821 pub mod R {}
20822 pub mod W {}
20823 pub mod RW {
20824 #[doc = "Open Drain Disabled"]
20825 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
20826 #[doc = "Open Drain Enabled"]
20827 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
20828 }
20829 }
20830 #[doc = "Pull / Keep Enable Field"]
20831 pub mod PKE {
20832 pub const offset: u32 = 12;
20833 pub const mask: u32 = 0x01 << offset;
20834 pub mod R {}
20835 pub mod W {}
20836 pub mod RW {
20837 #[doc = "Pull/Keeper Disabled"]
20838 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
20839 #[doc = "Pull/Keeper Enabled"]
20840 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
20841 }
20842 }
20843 #[doc = "Pull / Keep Select Field"]
20844 pub mod PUE {
20845 pub const offset: u32 = 13;
20846 pub const mask: u32 = 0x01 << offset;
20847 pub mod R {}
20848 pub mod W {}
20849 pub mod RW {
20850 #[doc = "Keeper"]
20851 pub const PUE_0_KEEPER: u32 = 0;
20852 #[doc = "Pull"]
20853 pub const PUE_1_PULL: u32 = 0x01;
20854 }
20855 }
20856 #[doc = "Pull Up / Down Config. Field"]
20857 pub mod PUS {
20858 pub const offset: u32 = 14;
20859 pub const mask: u32 = 0x03 << offset;
20860 pub mod R {}
20861 pub mod W {}
20862 pub mod RW {
20863 #[doc = "100K Ohm Pull Down"]
20864 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
20865 #[doc = "47K Ohm Pull Up"]
20866 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
20867 #[doc = "100K Ohm Pull Up"]
20868 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
20869 #[doc = "22K Ohm Pull Up"]
20870 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
20871 }
20872 }
20873 #[doc = "Hyst. Enable Field"]
20874 pub mod HYS {
20875 pub const offset: u32 = 16;
20876 pub const mask: u32 = 0x01 << offset;
20877 pub mod R {}
20878 pub mod W {}
20879 pub mod RW {
20880 #[doc = "Hysteresis Disabled"]
20881 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
20882 #[doc = "Hysteresis Enabled"]
20883 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
20884 }
20885 }
20886}
20887#[doc = "SW_PAD_CTL_PAD_GPIO_SD_B1_05 SW PAD Control Register"]
20888pub mod SW_PAD_CTL_PAD_GPIO_SD_B1_05 {
20889 #[doc = "Slew Rate Field"]
20890 pub mod SRE {
20891 pub const offset: u32 = 0;
20892 pub const mask: u32 = 0x01 << offset;
20893 pub mod R {}
20894 pub mod W {}
20895 pub mod RW {
20896 #[doc = "Slow Slew Rate"]
20897 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
20898 #[doc = "Fast Slew Rate"]
20899 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
20900 }
20901 }
20902 #[doc = "Drive Strength Field"]
20903 pub mod DSE {
20904 pub const offset: u32 = 3;
20905 pub const mask: u32 = 0x07 << offset;
20906 pub mod R {}
20907 pub mod W {}
20908 pub mod RW {
20909 #[doc = "output driver disabled;"]
20910 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
20911 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
20912 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
20913 #[doc = "R0/2"]
20914 pub const DSE_2_R0_2: u32 = 0x02;
20915 #[doc = "R0/3"]
20916 pub const DSE_3_R0_3: u32 = 0x03;
20917 #[doc = "R0/4"]
20918 pub const DSE_4_R0_4: u32 = 0x04;
20919 #[doc = "R0/5"]
20920 pub const DSE_5_R0_5: u32 = 0x05;
20921 #[doc = "R0/6"]
20922 pub const DSE_6_R0_6: u32 = 0x06;
20923 #[doc = "R0/7"]
20924 pub const DSE_7_R0_7: u32 = 0x07;
20925 }
20926 }
20927 #[doc = "Speed Field"]
20928 pub mod SPEED {
20929 pub const offset: u32 = 6;
20930 pub const mask: u32 = 0x03 << offset;
20931 pub mod R {}
20932 pub mod W {}
20933 pub mod RW {
20934 #[doc = "low(50MHz)"]
20935 pub const SPEED_0_LOW_50MHZ: u32 = 0;
20936 #[doc = "medium(100MHz)"]
20937 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
20938 #[doc = "medium(100MHz)"]
20939 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
20940 #[doc = "max(200MHz)"]
20941 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
20942 }
20943 }
20944 #[doc = "Open Drain Enable Field"]
20945 pub mod ODE {
20946 pub const offset: u32 = 11;
20947 pub const mask: u32 = 0x01 << offset;
20948 pub mod R {}
20949 pub mod W {}
20950 pub mod RW {
20951 #[doc = "Open Drain Disabled"]
20952 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
20953 #[doc = "Open Drain Enabled"]
20954 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
20955 }
20956 }
20957 #[doc = "Pull / Keep Enable Field"]
20958 pub mod PKE {
20959 pub const offset: u32 = 12;
20960 pub const mask: u32 = 0x01 << offset;
20961 pub mod R {}
20962 pub mod W {}
20963 pub mod RW {
20964 #[doc = "Pull/Keeper Disabled"]
20965 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
20966 #[doc = "Pull/Keeper Enabled"]
20967 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
20968 }
20969 }
20970 #[doc = "Pull / Keep Select Field"]
20971 pub mod PUE {
20972 pub const offset: u32 = 13;
20973 pub const mask: u32 = 0x01 << offset;
20974 pub mod R {}
20975 pub mod W {}
20976 pub mod RW {
20977 #[doc = "Keeper"]
20978 pub const PUE_0_KEEPER: u32 = 0;
20979 #[doc = "Pull"]
20980 pub const PUE_1_PULL: u32 = 0x01;
20981 }
20982 }
20983 #[doc = "Pull Up / Down Config. Field"]
20984 pub mod PUS {
20985 pub const offset: u32 = 14;
20986 pub const mask: u32 = 0x03 << offset;
20987 pub mod R {}
20988 pub mod W {}
20989 pub mod RW {
20990 #[doc = "100K Ohm Pull Down"]
20991 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
20992 #[doc = "47K Ohm Pull Up"]
20993 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
20994 #[doc = "100K Ohm Pull Up"]
20995 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
20996 #[doc = "22K Ohm Pull Up"]
20997 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
20998 }
20999 }
21000 #[doc = "Hyst. Enable Field"]
21001 pub mod HYS {
21002 pub const offset: u32 = 16;
21003 pub const mask: u32 = 0x01 << offset;
21004 pub mod R {}
21005 pub mod W {}
21006 pub mod RW {
21007 #[doc = "Hysteresis Disabled"]
21008 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
21009 #[doc = "Hysteresis Enabled"]
21010 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
21011 }
21012 }
21013}
21014#[doc = "SW_PAD_CTL_PAD_GPIO_SD_B1_06 SW PAD Control Register"]
21015pub mod SW_PAD_CTL_PAD_GPIO_SD_B1_06 {
21016 #[doc = "Slew Rate Field"]
21017 pub mod SRE {
21018 pub const offset: u32 = 0;
21019 pub const mask: u32 = 0x01 << offset;
21020 pub mod R {}
21021 pub mod W {}
21022 pub mod RW {
21023 #[doc = "Slow Slew Rate"]
21024 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
21025 #[doc = "Fast Slew Rate"]
21026 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
21027 }
21028 }
21029 #[doc = "Drive Strength Field"]
21030 pub mod DSE {
21031 pub const offset: u32 = 3;
21032 pub const mask: u32 = 0x07 << offset;
21033 pub mod R {}
21034 pub mod W {}
21035 pub mod RW {
21036 #[doc = "output driver disabled;"]
21037 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
21038 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
21039 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
21040 #[doc = "R0/2"]
21041 pub const DSE_2_R0_2: u32 = 0x02;
21042 #[doc = "R0/3"]
21043 pub const DSE_3_R0_3: u32 = 0x03;
21044 #[doc = "R0/4"]
21045 pub const DSE_4_R0_4: u32 = 0x04;
21046 #[doc = "R0/5"]
21047 pub const DSE_5_R0_5: u32 = 0x05;
21048 #[doc = "R0/6"]
21049 pub const DSE_6_R0_6: u32 = 0x06;
21050 #[doc = "R0/7"]
21051 pub const DSE_7_R0_7: u32 = 0x07;
21052 }
21053 }
21054 #[doc = "Speed Field"]
21055 pub mod SPEED {
21056 pub const offset: u32 = 6;
21057 pub const mask: u32 = 0x03 << offset;
21058 pub mod R {}
21059 pub mod W {}
21060 pub mod RW {
21061 #[doc = "low(50MHz)"]
21062 pub const SPEED_0_LOW_50MHZ: u32 = 0;
21063 #[doc = "medium(100MHz)"]
21064 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
21065 #[doc = "medium(100MHz)"]
21066 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
21067 #[doc = "max(200MHz)"]
21068 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
21069 }
21070 }
21071 #[doc = "Open Drain Enable Field"]
21072 pub mod ODE {
21073 pub const offset: u32 = 11;
21074 pub const mask: u32 = 0x01 << offset;
21075 pub mod R {}
21076 pub mod W {}
21077 pub mod RW {
21078 #[doc = "Open Drain Disabled"]
21079 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
21080 #[doc = "Open Drain Enabled"]
21081 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
21082 }
21083 }
21084 #[doc = "Pull / Keep Enable Field"]
21085 pub mod PKE {
21086 pub const offset: u32 = 12;
21087 pub const mask: u32 = 0x01 << offset;
21088 pub mod R {}
21089 pub mod W {}
21090 pub mod RW {
21091 #[doc = "Pull/Keeper Disabled"]
21092 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
21093 #[doc = "Pull/Keeper Enabled"]
21094 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
21095 }
21096 }
21097 #[doc = "Pull / Keep Select Field"]
21098 pub mod PUE {
21099 pub const offset: u32 = 13;
21100 pub const mask: u32 = 0x01 << offset;
21101 pub mod R {}
21102 pub mod W {}
21103 pub mod RW {
21104 #[doc = "Keeper"]
21105 pub const PUE_0_KEEPER: u32 = 0;
21106 #[doc = "Pull"]
21107 pub const PUE_1_PULL: u32 = 0x01;
21108 }
21109 }
21110 #[doc = "Pull Up / Down Config. Field"]
21111 pub mod PUS {
21112 pub const offset: u32 = 14;
21113 pub const mask: u32 = 0x03 << offset;
21114 pub mod R {}
21115 pub mod W {}
21116 pub mod RW {
21117 #[doc = "100K Ohm Pull Down"]
21118 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
21119 #[doc = "47K Ohm Pull Up"]
21120 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
21121 #[doc = "100K Ohm Pull Up"]
21122 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
21123 #[doc = "22K Ohm Pull Up"]
21124 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
21125 }
21126 }
21127 #[doc = "Hyst. Enable Field"]
21128 pub mod HYS {
21129 pub const offset: u32 = 16;
21130 pub const mask: u32 = 0x01 << offset;
21131 pub mod R {}
21132 pub mod W {}
21133 pub mod RW {
21134 #[doc = "Hysteresis Disabled"]
21135 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
21136 #[doc = "Hysteresis Enabled"]
21137 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
21138 }
21139 }
21140}
21141#[doc = "SW_PAD_CTL_PAD_GPIO_SD_B1_07 SW PAD Control Register"]
21142pub mod SW_PAD_CTL_PAD_GPIO_SD_B1_07 {
21143 #[doc = "Slew Rate Field"]
21144 pub mod SRE {
21145 pub const offset: u32 = 0;
21146 pub const mask: u32 = 0x01 << offset;
21147 pub mod R {}
21148 pub mod W {}
21149 pub mod RW {
21150 #[doc = "Slow Slew Rate"]
21151 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
21152 #[doc = "Fast Slew Rate"]
21153 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
21154 }
21155 }
21156 #[doc = "Drive Strength Field"]
21157 pub mod DSE {
21158 pub const offset: u32 = 3;
21159 pub const mask: u32 = 0x07 << offset;
21160 pub mod R {}
21161 pub mod W {}
21162 pub mod RW {
21163 #[doc = "output driver disabled;"]
21164 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
21165 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
21166 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
21167 #[doc = "R0/2"]
21168 pub const DSE_2_R0_2: u32 = 0x02;
21169 #[doc = "R0/3"]
21170 pub const DSE_3_R0_3: u32 = 0x03;
21171 #[doc = "R0/4"]
21172 pub const DSE_4_R0_4: u32 = 0x04;
21173 #[doc = "R0/5"]
21174 pub const DSE_5_R0_5: u32 = 0x05;
21175 #[doc = "R0/6"]
21176 pub const DSE_6_R0_6: u32 = 0x06;
21177 #[doc = "R0/7"]
21178 pub const DSE_7_R0_7: u32 = 0x07;
21179 }
21180 }
21181 #[doc = "Speed Field"]
21182 pub mod SPEED {
21183 pub const offset: u32 = 6;
21184 pub const mask: u32 = 0x03 << offset;
21185 pub mod R {}
21186 pub mod W {}
21187 pub mod RW {
21188 #[doc = "low(50MHz)"]
21189 pub const SPEED_0_LOW_50MHZ: u32 = 0;
21190 #[doc = "medium(100MHz)"]
21191 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
21192 #[doc = "medium(100MHz)"]
21193 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
21194 #[doc = "max(200MHz)"]
21195 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
21196 }
21197 }
21198 #[doc = "Open Drain Enable Field"]
21199 pub mod ODE {
21200 pub const offset: u32 = 11;
21201 pub const mask: u32 = 0x01 << offset;
21202 pub mod R {}
21203 pub mod W {}
21204 pub mod RW {
21205 #[doc = "Open Drain Disabled"]
21206 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
21207 #[doc = "Open Drain Enabled"]
21208 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
21209 }
21210 }
21211 #[doc = "Pull / Keep Enable Field"]
21212 pub mod PKE {
21213 pub const offset: u32 = 12;
21214 pub const mask: u32 = 0x01 << offset;
21215 pub mod R {}
21216 pub mod W {}
21217 pub mod RW {
21218 #[doc = "Pull/Keeper Disabled"]
21219 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
21220 #[doc = "Pull/Keeper Enabled"]
21221 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
21222 }
21223 }
21224 #[doc = "Pull / Keep Select Field"]
21225 pub mod PUE {
21226 pub const offset: u32 = 13;
21227 pub const mask: u32 = 0x01 << offset;
21228 pub mod R {}
21229 pub mod W {}
21230 pub mod RW {
21231 #[doc = "Keeper"]
21232 pub const PUE_0_KEEPER: u32 = 0;
21233 #[doc = "Pull"]
21234 pub const PUE_1_PULL: u32 = 0x01;
21235 }
21236 }
21237 #[doc = "Pull Up / Down Config. Field"]
21238 pub mod PUS {
21239 pub const offset: u32 = 14;
21240 pub const mask: u32 = 0x03 << offset;
21241 pub mod R {}
21242 pub mod W {}
21243 pub mod RW {
21244 #[doc = "100K Ohm Pull Down"]
21245 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
21246 #[doc = "47K Ohm Pull Up"]
21247 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
21248 #[doc = "100K Ohm Pull Up"]
21249 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
21250 #[doc = "22K Ohm Pull Up"]
21251 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
21252 }
21253 }
21254 #[doc = "Hyst. Enable Field"]
21255 pub mod HYS {
21256 pub const offset: u32 = 16;
21257 pub const mask: u32 = 0x01 << offset;
21258 pub mod R {}
21259 pub mod W {}
21260 pub mod RW {
21261 #[doc = "Hysteresis Disabled"]
21262 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
21263 #[doc = "Hysteresis Enabled"]
21264 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
21265 }
21266 }
21267}
21268#[doc = "SW_PAD_CTL_PAD_GPIO_SD_B1_08 SW PAD Control Register"]
21269pub mod SW_PAD_CTL_PAD_GPIO_SD_B1_08 {
21270 #[doc = "Slew Rate Field"]
21271 pub mod SRE {
21272 pub const offset: u32 = 0;
21273 pub const mask: u32 = 0x01 << offset;
21274 pub mod R {}
21275 pub mod W {}
21276 pub mod RW {
21277 #[doc = "Slow Slew Rate"]
21278 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
21279 #[doc = "Fast Slew Rate"]
21280 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
21281 }
21282 }
21283 #[doc = "Drive Strength Field"]
21284 pub mod DSE {
21285 pub const offset: u32 = 3;
21286 pub const mask: u32 = 0x07 << offset;
21287 pub mod R {}
21288 pub mod W {}
21289 pub mod RW {
21290 #[doc = "output driver disabled;"]
21291 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
21292 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
21293 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
21294 #[doc = "R0/2"]
21295 pub const DSE_2_R0_2: u32 = 0x02;
21296 #[doc = "R0/3"]
21297 pub const DSE_3_R0_3: u32 = 0x03;
21298 #[doc = "R0/4"]
21299 pub const DSE_4_R0_4: u32 = 0x04;
21300 #[doc = "R0/5"]
21301 pub const DSE_5_R0_5: u32 = 0x05;
21302 #[doc = "R0/6"]
21303 pub const DSE_6_R0_6: u32 = 0x06;
21304 #[doc = "R0/7"]
21305 pub const DSE_7_R0_7: u32 = 0x07;
21306 }
21307 }
21308 #[doc = "Speed Field"]
21309 pub mod SPEED {
21310 pub const offset: u32 = 6;
21311 pub const mask: u32 = 0x03 << offset;
21312 pub mod R {}
21313 pub mod W {}
21314 pub mod RW {
21315 #[doc = "low(50MHz)"]
21316 pub const SPEED_0_LOW_50MHZ: u32 = 0;
21317 #[doc = "medium(100MHz)"]
21318 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
21319 #[doc = "medium(100MHz)"]
21320 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
21321 #[doc = "max(200MHz)"]
21322 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
21323 }
21324 }
21325 #[doc = "Open Drain Enable Field"]
21326 pub mod ODE {
21327 pub const offset: u32 = 11;
21328 pub const mask: u32 = 0x01 << offset;
21329 pub mod R {}
21330 pub mod W {}
21331 pub mod RW {
21332 #[doc = "Open Drain Disabled"]
21333 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
21334 #[doc = "Open Drain Enabled"]
21335 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
21336 }
21337 }
21338 #[doc = "Pull / Keep Enable Field"]
21339 pub mod PKE {
21340 pub const offset: u32 = 12;
21341 pub const mask: u32 = 0x01 << offset;
21342 pub mod R {}
21343 pub mod W {}
21344 pub mod RW {
21345 #[doc = "Pull/Keeper Disabled"]
21346 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
21347 #[doc = "Pull/Keeper Enabled"]
21348 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
21349 }
21350 }
21351 #[doc = "Pull / Keep Select Field"]
21352 pub mod PUE {
21353 pub const offset: u32 = 13;
21354 pub const mask: u32 = 0x01 << offset;
21355 pub mod R {}
21356 pub mod W {}
21357 pub mod RW {
21358 #[doc = "Keeper"]
21359 pub const PUE_0_KEEPER: u32 = 0;
21360 #[doc = "Pull"]
21361 pub const PUE_1_PULL: u32 = 0x01;
21362 }
21363 }
21364 #[doc = "Pull Up / Down Config. Field"]
21365 pub mod PUS {
21366 pub const offset: u32 = 14;
21367 pub const mask: u32 = 0x03 << offset;
21368 pub mod R {}
21369 pub mod W {}
21370 pub mod RW {
21371 #[doc = "100K Ohm Pull Down"]
21372 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
21373 #[doc = "47K Ohm Pull Up"]
21374 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
21375 #[doc = "100K Ohm Pull Up"]
21376 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
21377 #[doc = "22K Ohm Pull Up"]
21378 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
21379 }
21380 }
21381 #[doc = "Hyst. Enable Field"]
21382 pub mod HYS {
21383 pub const offset: u32 = 16;
21384 pub const mask: u32 = 0x01 << offset;
21385 pub mod R {}
21386 pub mod W {}
21387 pub mod RW {
21388 #[doc = "Hysteresis Disabled"]
21389 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
21390 #[doc = "Hysteresis Enabled"]
21391 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
21392 }
21393 }
21394}
21395#[doc = "SW_PAD_CTL_PAD_GPIO_SD_B1_09 SW PAD Control Register"]
21396pub mod SW_PAD_CTL_PAD_GPIO_SD_B1_09 {
21397 #[doc = "Slew Rate Field"]
21398 pub mod SRE {
21399 pub const offset: u32 = 0;
21400 pub const mask: u32 = 0x01 << offset;
21401 pub mod R {}
21402 pub mod W {}
21403 pub mod RW {
21404 #[doc = "Slow Slew Rate"]
21405 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
21406 #[doc = "Fast Slew Rate"]
21407 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
21408 }
21409 }
21410 #[doc = "Drive Strength Field"]
21411 pub mod DSE {
21412 pub const offset: u32 = 3;
21413 pub const mask: u32 = 0x07 << offset;
21414 pub mod R {}
21415 pub mod W {}
21416 pub mod RW {
21417 #[doc = "output driver disabled;"]
21418 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
21419 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
21420 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
21421 #[doc = "R0/2"]
21422 pub const DSE_2_R0_2: u32 = 0x02;
21423 #[doc = "R0/3"]
21424 pub const DSE_3_R0_3: u32 = 0x03;
21425 #[doc = "R0/4"]
21426 pub const DSE_4_R0_4: u32 = 0x04;
21427 #[doc = "R0/5"]
21428 pub const DSE_5_R0_5: u32 = 0x05;
21429 #[doc = "R0/6"]
21430 pub const DSE_6_R0_6: u32 = 0x06;
21431 #[doc = "R0/7"]
21432 pub const DSE_7_R0_7: u32 = 0x07;
21433 }
21434 }
21435 #[doc = "Speed Field"]
21436 pub mod SPEED {
21437 pub const offset: u32 = 6;
21438 pub const mask: u32 = 0x03 << offset;
21439 pub mod R {}
21440 pub mod W {}
21441 pub mod RW {
21442 #[doc = "low(50MHz)"]
21443 pub const SPEED_0_LOW_50MHZ: u32 = 0;
21444 #[doc = "medium(100MHz)"]
21445 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
21446 #[doc = "medium(100MHz)"]
21447 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
21448 #[doc = "max(200MHz)"]
21449 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
21450 }
21451 }
21452 #[doc = "Open Drain Enable Field"]
21453 pub mod ODE {
21454 pub const offset: u32 = 11;
21455 pub const mask: u32 = 0x01 << offset;
21456 pub mod R {}
21457 pub mod W {}
21458 pub mod RW {
21459 #[doc = "Open Drain Disabled"]
21460 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
21461 #[doc = "Open Drain Enabled"]
21462 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
21463 }
21464 }
21465 #[doc = "Pull / Keep Enable Field"]
21466 pub mod PKE {
21467 pub const offset: u32 = 12;
21468 pub const mask: u32 = 0x01 << offset;
21469 pub mod R {}
21470 pub mod W {}
21471 pub mod RW {
21472 #[doc = "Pull/Keeper Disabled"]
21473 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
21474 #[doc = "Pull/Keeper Enabled"]
21475 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
21476 }
21477 }
21478 #[doc = "Pull / Keep Select Field"]
21479 pub mod PUE {
21480 pub const offset: u32 = 13;
21481 pub const mask: u32 = 0x01 << offset;
21482 pub mod R {}
21483 pub mod W {}
21484 pub mod RW {
21485 #[doc = "Keeper"]
21486 pub const PUE_0_KEEPER: u32 = 0;
21487 #[doc = "Pull"]
21488 pub const PUE_1_PULL: u32 = 0x01;
21489 }
21490 }
21491 #[doc = "Pull Up / Down Config. Field"]
21492 pub mod PUS {
21493 pub const offset: u32 = 14;
21494 pub const mask: u32 = 0x03 << offset;
21495 pub mod R {}
21496 pub mod W {}
21497 pub mod RW {
21498 #[doc = "100K Ohm Pull Down"]
21499 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
21500 #[doc = "47K Ohm Pull Up"]
21501 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
21502 #[doc = "100K Ohm Pull Up"]
21503 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
21504 #[doc = "22K Ohm Pull Up"]
21505 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
21506 }
21507 }
21508 #[doc = "Hyst. Enable Field"]
21509 pub mod HYS {
21510 pub const offset: u32 = 16;
21511 pub const mask: u32 = 0x01 << offset;
21512 pub mod R {}
21513 pub mod W {}
21514 pub mod RW {
21515 #[doc = "Hysteresis Disabled"]
21516 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
21517 #[doc = "Hysteresis Enabled"]
21518 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
21519 }
21520 }
21521}
21522#[doc = "SW_PAD_CTL_PAD_GPIO_SD_B1_10 SW PAD Control Register"]
21523pub mod SW_PAD_CTL_PAD_GPIO_SD_B1_10 {
21524 #[doc = "Slew Rate Field"]
21525 pub mod SRE {
21526 pub const offset: u32 = 0;
21527 pub const mask: u32 = 0x01 << offset;
21528 pub mod R {}
21529 pub mod W {}
21530 pub mod RW {
21531 #[doc = "Slow Slew Rate"]
21532 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
21533 #[doc = "Fast Slew Rate"]
21534 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
21535 }
21536 }
21537 #[doc = "Drive Strength Field"]
21538 pub mod DSE {
21539 pub const offset: u32 = 3;
21540 pub const mask: u32 = 0x07 << offset;
21541 pub mod R {}
21542 pub mod W {}
21543 pub mod RW {
21544 #[doc = "output driver disabled;"]
21545 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
21546 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
21547 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
21548 #[doc = "R0/2"]
21549 pub const DSE_2_R0_2: u32 = 0x02;
21550 #[doc = "R0/3"]
21551 pub const DSE_3_R0_3: u32 = 0x03;
21552 #[doc = "R0/4"]
21553 pub const DSE_4_R0_4: u32 = 0x04;
21554 #[doc = "R0/5"]
21555 pub const DSE_5_R0_5: u32 = 0x05;
21556 #[doc = "R0/6"]
21557 pub const DSE_6_R0_6: u32 = 0x06;
21558 #[doc = "R0/7"]
21559 pub const DSE_7_R0_7: u32 = 0x07;
21560 }
21561 }
21562 #[doc = "Speed Field"]
21563 pub mod SPEED {
21564 pub const offset: u32 = 6;
21565 pub const mask: u32 = 0x03 << offset;
21566 pub mod R {}
21567 pub mod W {}
21568 pub mod RW {
21569 #[doc = "low(50MHz)"]
21570 pub const SPEED_0_LOW_50MHZ: u32 = 0;
21571 #[doc = "medium(100MHz)"]
21572 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
21573 #[doc = "medium(100MHz)"]
21574 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
21575 #[doc = "max(200MHz)"]
21576 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
21577 }
21578 }
21579 #[doc = "Open Drain Enable Field"]
21580 pub mod ODE {
21581 pub const offset: u32 = 11;
21582 pub const mask: u32 = 0x01 << offset;
21583 pub mod R {}
21584 pub mod W {}
21585 pub mod RW {
21586 #[doc = "Open Drain Disabled"]
21587 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
21588 #[doc = "Open Drain Enabled"]
21589 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
21590 }
21591 }
21592 #[doc = "Pull / Keep Enable Field"]
21593 pub mod PKE {
21594 pub const offset: u32 = 12;
21595 pub const mask: u32 = 0x01 << offset;
21596 pub mod R {}
21597 pub mod W {}
21598 pub mod RW {
21599 #[doc = "Pull/Keeper Disabled"]
21600 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
21601 #[doc = "Pull/Keeper Enabled"]
21602 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
21603 }
21604 }
21605 #[doc = "Pull / Keep Select Field"]
21606 pub mod PUE {
21607 pub const offset: u32 = 13;
21608 pub const mask: u32 = 0x01 << offset;
21609 pub mod R {}
21610 pub mod W {}
21611 pub mod RW {
21612 #[doc = "Keeper"]
21613 pub const PUE_0_KEEPER: u32 = 0;
21614 #[doc = "Pull"]
21615 pub const PUE_1_PULL: u32 = 0x01;
21616 }
21617 }
21618 #[doc = "Pull Up / Down Config. Field"]
21619 pub mod PUS {
21620 pub const offset: u32 = 14;
21621 pub const mask: u32 = 0x03 << offset;
21622 pub mod R {}
21623 pub mod W {}
21624 pub mod RW {
21625 #[doc = "100K Ohm Pull Down"]
21626 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
21627 #[doc = "47K Ohm Pull Up"]
21628 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
21629 #[doc = "100K Ohm Pull Up"]
21630 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
21631 #[doc = "22K Ohm Pull Up"]
21632 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
21633 }
21634 }
21635 #[doc = "Hyst. Enable Field"]
21636 pub mod HYS {
21637 pub const offset: u32 = 16;
21638 pub const mask: u32 = 0x01 << offset;
21639 pub mod R {}
21640 pub mod W {}
21641 pub mod RW {
21642 #[doc = "Hysteresis Disabled"]
21643 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
21644 #[doc = "Hysteresis Enabled"]
21645 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
21646 }
21647 }
21648}
21649#[doc = "SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register"]
21650pub mod SW_PAD_CTL_PAD_GPIO_SD_B1_11 {
21651 #[doc = "Slew Rate Field"]
21652 pub mod SRE {
21653 pub const offset: u32 = 0;
21654 pub const mask: u32 = 0x01 << offset;
21655 pub mod R {}
21656 pub mod W {}
21657 pub mod RW {
21658 #[doc = "Slow Slew Rate"]
21659 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
21660 #[doc = "Fast Slew Rate"]
21661 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
21662 }
21663 }
21664 #[doc = "Drive Strength Field"]
21665 pub mod DSE {
21666 pub const offset: u32 = 3;
21667 pub const mask: u32 = 0x07 << offset;
21668 pub mod R {}
21669 pub mod W {}
21670 pub mod RW {
21671 #[doc = "output driver disabled;"]
21672 pub const DSE_0_OUTPUT_DRIVER_DISABLED: u32 = 0;
21673 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
21674 pub const DSE_1_R0_150_OHM_3_3V_260_OHM_1_8V: u32 = 0x01;
21675 #[doc = "R0/2"]
21676 pub const DSE_2_R0_2: u32 = 0x02;
21677 #[doc = "R0/3"]
21678 pub const DSE_3_R0_3: u32 = 0x03;
21679 #[doc = "R0/4"]
21680 pub const DSE_4_R0_4: u32 = 0x04;
21681 #[doc = "R0/5"]
21682 pub const DSE_5_R0_5: u32 = 0x05;
21683 #[doc = "R0/6"]
21684 pub const DSE_6_R0_6: u32 = 0x06;
21685 #[doc = "R0/7"]
21686 pub const DSE_7_R0_7: u32 = 0x07;
21687 }
21688 }
21689 #[doc = "Speed Field"]
21690 pub mod SPEED {
21691 pub const offset: u32 = 6;
21692 pub const mask: u32 = 0x03 << offset;
21693 pub mod R {}
21694 pub mod W {}
21695 pub mod RW {
21696 #[doc = "low(50MHz)"]
21697 pub const SPEED_0_LOW_50MHZ: u32 = 0;
21698 #[doc = "medium(100MHz)"]
21699 pub const SPEED_1_MEDIUM_100MHZ: u32 = 0x01;
21700 #[doc = "medium(100MHz)"]
21701 pub const SPEED_2_MEDIUM_100MHZ: u32 = 0x02;
21702 #[doc = "max(200MHz)"]
21703 pub const SPEED_3_MAX_200MHZ: u32 = 0x03;
21704 }
21705 }
21706 #[doc = "Open Drain Enable Field"]
21707 pub mod ODE {
21708 pub const offset: u32 = 11;
21709 pub const mask: u32 = 0x01 << offset;
21710 pub mod R {}
21711 pub mod W {}
21712 pub mod RW {
21713 #[doc = "Open Drain Disabled"]
21714 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
21715 #[doc = "Open Drain Enabled"]
21716 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
21717 }
21718 }
21719 #[doc = "Pull / Keep Enable Field"]
21720 pub mod PKE {
21721 pub const offset: u32 = 12;
21722 pub const mask: u32 = 0x01 << offset;
21723 pub mod R {}
21724 pub mod W {}
21725 pub mod RW {
21726 #[doc = "Pull/Keeper Disabled"]
21727 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
21728 #[doc = "Pull/Keeper Enabled"]
21729 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
21730 }
21731 }
21732 #[doc = "Pull / Keep Select Field"]
21733 pub mod PUE {
21734 pub const offset: u32 = 13;
21735 pub const mask: u32 = 0x01 << offset;
21736 pub mod R {}
21737 pub mod W {}
21738 pub mod RW {
21739 #[doc = "Keeper"]
21740 pub const PUE_0_KEEPER: u32 = 0;
21741 #[doc = "Pull"]
21742 pub const PUE_1_PULL: u32 = 0x01;
21743 }
21744 }
21745 #[doc = "Pull Up / Down Config. Field"]
21746 pub mod PUS {
21747 pub const offset: u32 = 14;
21748 pub const mask: u32 = 0x03 << offset;
21749 pub mod R {}
21750 pub mod W {}
21751 pub mod RW {
21752 #[doc = "100K Ohm Pull Down"]
21753 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
21754 #[doc = "47K Ohm Pull Up"]
21755 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
21756 #[doc = "100K Ohm Pull Up"]
21757 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
21758 #[doc = "22K Ohm Pull Up"]
21759 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
21760 }
21761 }
21762 #[doc = "Hyst. Enable Field"]
21763 pub mod HYS {
21764 pub const offset: u32 = 16;
21765 pub const mask: u32 = 0x01 << offset;
21766 pub mod R {}
21767 pub mod W {}
21768 pub mod RW {
21769 #[doc = "Hysteresis Disabled"]
21770 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
21771 #[doc = "Hysteresis Enabled"]
21772 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
21773 }
21774 }
21775}
21776#[doc = "ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register"]
21777pub mod ANATOP_USB_OTG1_ID_SELECT_INPUT {
21778 #[doc = "Selecting Pads Involved in Daisy Chain."]
21779 pub mod DAISY {
21780 pub const offset: u32 = 0;
21781 pub const mask: u32 = 0x01 << offset;
21782 pub mod R {}
21783 pub mod W {}
21784 pub mod RW {
21785 #[doc = "Selecting Pad: GPIO_AD_B0_01 for Mode: ALT3"]
21786 pub const GPIO_AD_B0_01_ALT3: u32 = 0;
21787 #[doc = "Selecting Pad: GPIO_AD_B1_02 for Mode: ALT0"]
21788 pub const GPIO_AD_B1_02_ALT0: u32 = 0x01;
21789 }
21790 }
21791}
21792#[doc = "ANATOP_USB_OTG2_ID_SELECT_INPUT DAISY Register"]
21793pub mod ANATOP_USB_OTG2_ID_SELECT_INPUT {
21794 #[doc = "Selecting Pads Involved in Daisy Chain."]
21795 pub mod DAISY {
21796 pub const offset: u32 = 0;
21797 pub const mask: u32 = 0x01 << offset;
21798 pub mod R {}
21799 pub mod W {}
21800 pub mod RW {
21801 #[doc = "Selecting Pad: GPIO_AD_B0_00 for Mode: ALT3"]
21802 pub const GPIO_AD_B0_00_ALT3: u32 = 0;
21803 #[doc = "Selecting Pad: GPIO_AD_B1_00 for Mode: ALT0"]
21804 pub const GPIO_AD_B1_00_ALT0: u32 = 0x01;
21805 }
21806 }
21807}
21808#[doc = "CCM_PMIC_READY_SELECT_INPUT DAISY Register"]
21809pub mod CCM_PMIC_READY_SELECT_INPUT {
21810 #[doc = "Selecting Pads Involved in Daisy Chain."]
21811 pub mod DAISY {
21812 pub const offset: u32 = 0;
21813 pub const mask: u32 = 0x07 << offset;
21814 pub mod R {}
21815 pub mod W {}
21816 pub mod RW {
21817 #[doc = "Selecting Pad: GPIO_SD_B1_03 for Mode: ALT6"]
21818 pub const GPIO_SD_B1_03_ALT6: u32 = 0;
21819 #[doc = "Selecting Pad: GPIO_AD_B0_12 for Mode: ALT1"]
21820 pub const GPIO_AD_B0_12_ALT1: u32 = 0x01;
21821 #[doc = "Selecting Pad: GPIO_AD_B1_01 for Mode: ALT4"]
21822 pub const GPIO_AD_B1_01_ALT4: u32 = 0x02;
21823 #[doc = "Selecting Pad: GPIO_AD_B1_08 for Mode: ALT3"]
21824 pub const GPIO_AD_B1_08_ALT3: u32 = 0x03;
21825 #[doc = "Selecting Pad: GPIO_EMC_32 for Mode: ALT3"]
21826 pub const GPIO_EMC_32_ALT3: u32 = 0x04;
21827 }
21828 }
21829}
21830#[doc = "CSI_DATA02_SELECT_INPUT DAISY Register"]
21831pub mod CSI_DATA02_SELECT_INPUT {
21832 #[doc = "Selecting Pads Involved in Daisy Chain."]
21833 pub mod DAISY {
21834 pub const offset: u32 = 0;
21835 pub const mask: u32 = 0x01 << offset;
21836 pub mod R {}
21837 pub mod W {}
21838 pub mod RW {
21839 #[doc = "Selecting Pad: GPIO_AD_B1_15 for Mode: ALT4"]
21840 pub const GPIO_AD_B1_15_ALT4: u32 = 0;
21841 #[doc = "Selecting Pad: GPIO_AD_B0_11 for Mode: ALT4"]
21842 pub const GPIO_AD_B0_11_ALT4: u32 = 0x01;
21843 }
21844 }
21845}
21846#[doc = "CSI_DATA03_SELECT_INPUT DAISY Register"]
21847pub mod CSI_DATA03_SELECT_INPUT {
21848 #[doc = "Selecting Pads Involved in Daisy Chain."]
21849 pub mod DAISY {
21850 pub const offset: u32 = 0;
21851 pub const mask: u32 = 0x01 << offset;
21852 pub mod R {}
21853 pub mod W {}
21854 pub mod RW {
21855 #[doc = "Selecting Pad: GPIO_AD_B1_14 for Mode: ALT4"]
21856 pub const GPIO_AD_B1_14_ALT4: u32 = 0;
21857 #[doc = "Selecting Pad: GPIO_AD_B0_10 for Mode: ALT4"]
21858 pub const GPIO_AD_B0_10_ALT4: u32 = 0x01;
21859 }
21860 }
21861}
21862#[doc = "CSI_DATA04_SELECT_INPUT DAISY Register"]
21863pub mod CSI_DATA04_SELECT_INPUT {
21864 #[doc = "Selecting Pads Involved in Daisy Chain."]
21865 pub mod DAISY {
21866 pub const offset: u32 = 0;
21867 pub const mask: u32 = 0x01 << offset;
21868 pub mod R {}
21869 pub mod W {}
21870 pub mod RW {
21871 #[doc = "Selecting Pad: GPIO_AD_B1_13 for Mode: ALT4"]
21872 pub const GPIO_AD_B1_13_ALT4: u32 = 0;
21873 #[doc = "Selecting Pad: GPIO_AD_B0_09 for Mode: ALT4"]
21874 pub const GPIO_AD_B0_09_ALT4: u32 = 0x01;
21875 }
21876 }
21877}
21878#[doc = "CSI_DATA05_SELECT_INPUT DAISY Register"]
21879pub mod CSI_DATA05_SELECT_INPUT {
21880 #[doc = "Selecting Pads Involved in Daisy Chain."]
21881 pub mod DAISY {
21882 pub const offset: u32 = 0;
21883 pub const mask: u32 = 0x01 << offset;
21884 pub mod R {}
21885 pub mod W {}
21886 pub mod RW {
21887 #[doc = "Selecting Pad: GPIO_AD_B1_12 for Mode: ALT4"]
21888 pub const GPIO_AD_B1_12_ALT4: u32 = 0;
21889 #[doc = "Selecting Pad: GPIO_AD_B0_08 for Mode: ALT4"]
21890 pub const GPIO_AD_B0_08_ALT4: u32 = 0x01;
21891 }
21892 }
21893}
21894#[doc = "CSI_DATA06_SELECT_INPUT DAISY Register"]
21895pub mod CSI_DATA06_SELECT_INPUT {
21896 #[doc = "Selecting Pads Involved in Daisy Chain."]
21897 pub mod DAISY {
21898 pub const offset: u32 = 0;
21899 pub const mask: u32 = 0x01 << offset;
21900 pub mod R {}
21901 pub mod W {}
21902 pub mod RW {
21903 #[doc = "Selecting Pad: GPIO_AD_B1_11 for Mode: ALT4"]
21904 pub const GPIO_AD_B1_11_ALT4: u32 = 0;
21905 #[doc = "Selecting Pad: GPIO_AD_B0_07 for Mode: ALT4"]
21906 pub const GPIO_AD_B0_07_ALT4: u32 = 0x01;
21907 }
21908 }
21909}
21910#[doc = "CSI_DATA07_SELECT_INPUT DAISY Register"]
21911pub mod CSI_DATA07_SELECT_INPUT {
21912 #[doc = "Selecting Pads Involved in Daisy Chain."]
21913 pub mod DAISY {
21914 pub const offset: u32 = 0;
21915 pub const mask: u32 = 0x01 << offset;
21916 pub mod R {}
21917 pub mod W {}
21918 pub mod RW {
21919 #[doc = "Selecting Pad: GPIO_AD_B1_10 for Mode: ALT4"]
21920 pub const GPIO_AD_B1_10_ALT4: u32 = 0;
21921 #[doc = "Selecting Pad: GPIO_AD_B0_06 for Mode: ALT4"]
21922 pub const GPIO_AD_B0_06_ALT4: u32 = 0x01;
21923 }
21924 }
21925}
21926#[doc = "CSI_DATA08_SELECT_INPUT DAISY Register"]
21927pub mod CSI_DATA08_SELECT_INPUT {
21928 #[doc = "Selecting Pads Involved in Daisy Chain."]
21929 pub mod DAISY {
21930 pub const offset: u32 = 0;
21931 pub const mask: u32 = 0x01 << offset;
21932 pub mod R {}
21933 pub mod W {}
21934 pub mod RW {
21935 #[doc = "Selecting Pad: GPIO_AD_B1_09 for Mode: ALT4"]
21936 pub const GPIO_AD_B1_09_ALT4: u32 = 0;
21937 #[doc = "Selecting Pad: GPIO_AD_B0_05 for Mode: ALT4"]
21938 pub const GPIO_AD_B0_05_ALT4: u32 = 0x01;
21939 }
21940 }
21941}
21942#[doc = "CSI_DATA09_SELECT_INPUT DAISY Register"]
21943pub mod CSI_DATA09_SELECT_INPUT {
21944 #[doc = "Selecting Pads Involved in Daisy Chain."]
21945 pub mod DAISY {
21946 pub const offset: u32 = 0;
21947 pub const mask: u32 = 0x01 << offset;
21948 pub mod R {}
21949 pub mod W {}
21950 pub mod RW {
21951 #[doc = "Selecting Pad: GPIO_AD_B1_08 for Mode: ALT4"]
21952 pub const GPIO_AD_B1_08_ALT4: u32 = 0;
21953 #[doc = "Selecting Pad: GPIO_AD_B0_04 for Mode: ALT4"]
21954 pub const GPIO_AD_B0_04_ALT4: u32 = 0x01;
21955 }
21956 }
21957}
21958#[doc = "CSI_HSYNC_SELECT_INPUT DAISY Register"]
21959pub mod CSI_HSYNC_SELECT_INPUT {
21960 #[doc = "Selecting Pads Involved in Daisy Chain."]
21961 pub mod DAISY {
21962 pub const offset: u32 = 0;
21963 pub const mask: u32 = 0x03 << offset;
21964 pub mod R {}
21965 pub mod W {}
21966 pub mod RW {
21967 #[doc = "Selecting Pad: GPIO_AD_B0_15 for Mode: ALT4"]
21968 pub const GPIO_AD_B0_15_ALT4: u32 = 0;
21969 #[doc = "Selecting Pad: GPIO_AD_B1_07 for Mode: ALT4"]
21970 pub const GPIO_AD_B1_07_ALT4: u32 = 0x01;
21971 #[doc = "Selecting Pad: GPIO_B1_14 for Mode: ALT2"]
21972 pub const GPIO_B1_14_ALT2: u32 = 0x02;
21973 }
21974 }
21975}
21976#[doc = "CSI_PIXCLK_SELECT_INPUT DAISY Register"]
21977pub mod CSI_PIXCLK_SELECT_INPUT {
21978 #[doc = "Selecting Pads Involved in Daisy Chain."]
21979 pub mod DAISY {
21980 pub const offset: u32 = 0;
21981 pub const mask: u32 = 0x01 << offset;
21982 pub mod R {}
21983 pub mod W {}
21984 pub mod RW {
21985 #[doc = "Selecting Pad: GPIO_AD_B1_04 for Mode: ALT4"]
21986 pub const GPIO_AD_B1_04_ALT4: u32 = 0;
21987 #[doc = "Selecting Pad: GPIO_B1_12 for Mode: ALT2"]
21988 pub const GPIO_B1_12_ALT2: u32 = 0x01;
21989 }
21990 }
21991}
21992#[doc = "CSI_VSYNC_SELECT_INPUT DAISY Register"]
21993pub mod CSI_VSYNC_SELECT_INPUT {
21994 #[doc = "Selecting Pads Involved in Daisy Chain."]
21995 pub mod DAISY {
21996 pub const offset: u32 = 0;
21997 pub const mask: u32 = 0x03 << offset;
21998 pub mod R {}
21999 pub mod W {}
22000 pub mod RW {
22001 #[doc = "Selecting Pad: GPIO_AD_B0_14 for Mode: ALT4"]
22002 pub const GPIO_AD_B0_14_ALT4: u32 = 0;
22003 #[doc = "Selecting Pad: GPIO_AD_B1_06 for Mode: ALT4"]
22004 pub const GPIO_AD_B1_06_ALT4: u32 = 0x01;
22005 #[doc = "Selecting Pad: GPIO_B1_13 for Mode: ALT2"]
22006 pub const GPIO_B1_13_ALT2: u32 = 0x02;
22007 }
22008 }
22009}
22010#[doc = "ENET_IPG_CLK_RMII_SELECT_INPUT DAISY Register"]
22011pub mod ENET_IPG_CLK_RMII_SELECT_INPUT {
22012 #[doc = "Selecting Pads Involved in Daisy Chain."]
22013 pub mod DAISY {
22014 pub const offset: u32 = 0;
22015 pub const mask: u32 = 0x01 << offset;
22016 pub mod R {}
22017 pub mod W {}
22018 pub mod RW {
22019 #[doc = "Selecting Pad: GPIO_EMC_25 for Mode: ALT4"]
22020 pub const GPIO_EMC_25_ALT4: u32 = 0;
22021 #[doc = "Selecting Pad: GPIO_B1_10 for Mode: ALT6"]
22022 pub const GPIO_B1_10_ALT6: u32 = 0x01;
22023 }
22024 }
22025}
22026#[doc = "ENET_MDIO_SELECT_INPUT DAISY Register"]
22027pub mod ENET_MDIO_SELECT_INPUT {
22028 #[doc = "Selecting Pads Involved in Daisy Chain."]
22029 pub mod DAISY {
22030 pub const offset: u32 = 0;
22031 pub const mask: u32 = 0x03 << offset;
22032 pub mod R {}
22033 pub mod W {}
22034 pub mod RW {
22035 #[doc = "Selecting Pad: GPIO_AD_B1_05 for Mode: ALT1"]
22036 pub const GPIO_AD_B1_05_ALT1: u32 = 0;
22037 #[doc = "Selecting Pad: GPIO_EMC_41 for Mode: ALT4"]
22038 pub const GPIO_EMC_41_ALT4: u32 = 0x01;
22039 #[doc = "Selecting Pad: GPIO_B1_15 for Mode: ALT0"]
22040 pub const GPIO_B1_15_ALT0: u32 = 0x02;
22041 }
22042 }
22043}
22044#[doc = "ENET0_RXDATA_SELECT_INPUT DAISY Register"]
22045pub mod ENET0_RXDATA_SELECT_INPUT {
22046 #[doc = "Selecting Pads Involved in Daisy Chain."]
22047 pub mod DAISY {
22048 pub const offset: u32 = 0;
22049 pub const mask: u32 = 0x01 << offset;
22050 pub mod R {}
22051 pub mod W {}
22052 pub mod RW {
22053 #[doc = "Selecting Pad: GPIO_EMC_20 for Mode: ALT3"]
22054 pub const GPIO_EMC_20_ALT3: u32 = 0;
22055 #[doc = "Selecting Pad: GPIO_B1_04 for Mode: ALT3"]
22056 pub const GPIO_B1_04_ALT3: u32 = 0x01;
22057 }
22058 }
22059}
22060#[doc = "ENET1_RXDATA_SELECT_INPUT DAISY Register"]
22061pub mod ENET1_RXDATA_SELECT_INPUT {
22062 #[doc = "Selecting Pads Involved in Daisy Chain."]
22063 pub mod DAISY {
22064 pub const offset: u32 = 0;
22065 pub const mask: u32 = 0x01 << offset;
22066 pub mod R {}
22067 pub mod W {}
22068 pub mod RW {
22069 #[doc = "Selecting Pad: GPIO_EMC_19 for Mode: ALT3"]
22070 pub const GPIO_EMC_19_ALT3: u32 = 0;
22071 #[doc = "Selecting Pad: GPIO_B1_05 for Mode: ALT3"]
22072 pub const GPIO_B1_05_ALT3: u32 = 0x01;
22073 }
22074 }
22075}
22076#[doc = "ENET_RXEN_SELECT_INPUT DAISY Register"]
22077pub mod ENET_RXEN_SELECT_INPUT {
22078 #[doc = "Selecting Pads Involved in Daisy Chain."]
22079 pub mod DAISY {
22080 pub const offset: u32 = 0;
22081 pub const mask: u32 = 0x01 << offset;
22082 pub mod R {}
22083 pub mod W {}
22084 pub mod RW {
22085 #[doc = "Selecting Pad: GPIO_EMC_23 for Mode: ALT3"]
22086 pub const GPIO_EMC_23_ALT3: u32 = 0;
22087 #[doc = "Selecting Pad: GPIO_B1_06 for Mode: ALT3"]
22088 pub const GPIO_B1_06_ALT3: u32 = 0x01;
22089 }
22090 }
22091}
22092#[doc = "ENET_RXERR_SELECT_INPUT DAISY Register"]
22093pub mod ENET_RXERR_SELECT_INPUT {
22094 #[doc = "Selecting Pads Involved in Daisy Chain."]
22095 pub mod DAISY {
22096 pub const offset: u32 = 0;
22097 pub const mask: u32 = 0x01 << offset;
22098 pub mod R {}
22099 pub mod W {}
22100 pub mod RW {
22101 #[doc = "Selecting Pad: GPIO_EMC_26 for Mode: ALT3"]
22102 pub const GPIO_EMC_26_ALT3: u32 = 0;
22103 #[doc = "Selecting Pad: GPIO_B1_11 for Mode: ALT3"]
22104 pub const GPIO_B1_11_ALT3: u32 = 0x01;
22105 }
22106 }
22107}
22108#[doc = "ENET0_TIMER_SELECT_INPUT DAISY Register"]
22109pub mod ENET0_TIMER_SELECT_INPUT {
22110 #[doc = "Selecting Pads Involved in Daisy Chain."]
22111 pub mod DAISY {
22112 pub const offset: u32 = 0;
22113 pub const mask: u32 = 0x03 << offset;
22114 pub mod R {}
22115 pub mod W {}
22116 pub mod RW {
22117 #[doc = "Selecting Pad: GPIO_AD_B0_15 for Mode: ALT3"]
22118 pub const GPIO_AD_B0_15_ALT3: u32 = 0;
22119 #[doc = "Selecting Pad: GPIO_AD_B0_11 for Mode: ALT7"]
22120 pub const GPIO_AD_B0_11_ALT7: u32 = 0x01;
22121 #[doc = "Selecting Pad: GPIO_B1_12 for Mode: ALT3"]
22122 pub const GPIO_B1_12_ALT3: u32 = 0x02;
22123 }
22124 }
22125}
22126#[doc = "ENET_TXCLK_SELECT_INPUT DAISY Register"]
22127pub mod ENET_TXCLK_SELECT_INPUT {
22128 #[doc = "Selecting Pads Involved in Daisy Chain."]
22129 pub mod DAISY {
22130 pub const offset: u32 = 0;
22131 pub const mask: u32 = 0x01 << offset;
22132 pub mod R {}
22133 pub mod W {}
22134 pub mod RW {
22135 #[doc = "Selecting Pad: GPIO_EMC_25 for Mode: ALT3"]
22136 pub const GPIO_EMC_25_ALT3: u32 = 0;
22137 #[doc = "Selecting Pad: GPIO_B1_10 for Mode: ALT3"]
22138 pub const GPIO_B1_10_ALT3: u32 = 0x01;
22139 }
22140 }
22141}
22142#[doc = "FLEXCAN1_RX_SELECT_INPUT DAISY Register"]
22143pub mod FLEXCAN1_RX_SELECT_INPUT {
22144 #[doc = "Selecting Pads Involved in Daisy Chain."]
22145 pub mod DAISY {
22146 pub const offset: u32 = 0;
22147 pub const mask: u32 = 0x03 << offset;
22148 pub mod R {}
22149 pub mod W {}
22150 pub mod RW {
22151 #[doc = "Selecting Pad: GPIO_SD_B1_03 for Mode: ALT4"]
22152 pub const GPIO_SD_B1_03_ALT4: u32 = 0;
22153 #[doc = "Selecting Pad: GPIO_EMC_18 for Mode: ALT3"]
22154 pub const GPIO_EMC_18_ALT3: u32 = 0x01;
22155 #[doc = "Selecting Pad: GPIO_AD_B1_09 for Mode: ALT2"]
22156 pub const GPIO_AD_B1_09_ALT2: u32 = 0x02;
22157 #[doc = "Selecting Pad: GPIO_B0_03 for Mode: ALT2"]
22158 pub const GPIO_B0_03_ALT2: u32 = 0x03;
22159 }
22160 }
22161}
22162#[doc = "FLEXCAN2_RX_SELECT_INPUT DAISY Register"]
22163pub mod FLEXCAN2_RX_SELECT_INPUT {
22164 #[doc = "Selecting Pads Involved in Daisy Chain."]
22165 pub mod DAISY {
22166 pub const offset: u32 = 0;
22167 pub const mask: u32 = 0x03 << offset;
22168 pub mod R {}
22169 pub mod W {}
22170 pub mod RW {
22171 #[doc = "Selecting Pad: GPIO_EMC_10 for Mode: ALT3"]
22172 pub const GPIO_EMC_10_ALT3: u32 = 0;
22173 #[doc = "Selecting Pad: GPIO_AD_B0_03 for Mode: ALT0"]
22174 pub const GPIO_AD_B0_03_ALT0: u32 = 0x01;
22175 #[doc = "Selecting Pad: GPIO_AD_B0_15 for Mode: ALT6"]
22176 pub const GPIO_AD_B0_15_ALT6: u32 = 0x02;
22177 #[doc = "Selecting Pad: GPIO_B1_09 for Mode: ALT6"]
22178 pub const GPIO_B1_09_ALT6: u32 = 0x03;
22179 }
22180 }
22181}
22182#[doc = "FLEXPWM1_PWMA3_SELECT_INPUT DAISY Register"]
22183pub mod FLEXPWM1_PWMA3_SELECT_INPUT {
22184 #[doc = "Selecting Pads Involved in Daisy Chain."]
22185 pub mod DAISY {
22186 pub const offset: u32 = 0;
22187 pub const mask: u32 = 0x07 << offset;
22188 pub mod R {}
22189 pub mod W {}
22190 pub mod RW {
22191 #[doc = "Selecting Pad: GPIO_SD_B1_00 for Mode: ALT2"]
22192 pub const GPIO_SD_B1_00_ALT2: u32 = 0;
22193 #[doc = "Selecting Pad: GPIO_EMC_12 for Mode: ALT4"]
22194 pub const GPIO_EMC_12_ALT4: u32 = 0x01;
22195 #[doc = "Selecting Pad: GPIO_EMC_38 for Mode: ALT1"]
22196 pub const GPIO_EMC_38_ALT1: u32 = 0x02;
22197 #[doc = "Selecting Pad: GPIO_AD_B0_10 for Mode: ALT1"]
22198 pub const GPIO_AD_B0_10_ALT1: u32 = 0x03;
22199 #[doc = "Selecting Pad: GPIO_B1_00 for Mode: ALT6"]
22200 pub const GPIO_B1_00_ALT6: u32 = 0x04;
22201 }
22202 }
22203}
22204#[doc = "FLEXPWM1_PWMA0_SELECT_INPUT DAISY Register"]
22205pub mod FLEXPWM1_PWMA0_SELECT_INPUT {
22206 #[doc = "Selecting Pads Involved in Daisy Chain."]
22207 pub mod DAISY {
22208 pub const offset: u32 = 0;
22209 pub const mask: u32 = 0x01 << offset;
22210 pub mod R {}
22211 pub mod W {}
22212 pub mod RW {
22213 #[doc = "Selecting Pad: GPIO_EMC_23 for Mode: ALT1"]
22214 pub const GPIO_EMC_23_ALT1: u32 = 0;
22215 #[doc = "Selecting Pad: GPIO_SD_B0_00 for Mode: ALT1"]
22216 pub const GPIO_SD_B0_00_ALT1: u32 = 0x01;
22217 }
22218 }
22219}
22220#[doc = "FLEXPWM1_PWMA1_SELECT_INPUT DAISY Register"]
22221pub mod FLEXPWM1_PWMA1_SELECT_INPUT {
22222 #[doc = "Selecting Pads Involved in Daisy Chain."]
22223 pub mod DAISY {
22224 pub const offset: u32 = 0;
22225 pub const mask: u32 = 0x01 << offset;
22226 pub mod R {}
22227 pub mod W {}
22228 pub mod RW {
22229 #[doc = "Selecting Pad: GPIO_EMC_25 for Mode: ALT1"]
22230 pub const GPIO_EMC_25_ALT1: u32 = 0;
22231 #[doc = "Selecting Pad: GPIO_SD_B0_02 for Mode: ALT1"]
22232 pub const GPIO_SD_B0_02_ALT1: u32 = 0x01;
22233 }
22234 }
22235}
22236#[doc = "FLEXPWM1_PWMA2_SELECT_INPUT DAISY Register"]
22237pub mod FLEXPWM1_PWMA2_SELECT_INPUT {
22238 #[doc = "Selecting Pads Involved in Daisy Chain."]
22239 pub mod DAISY {
22240 pub const offset: u32 = 0;
22241 pub const mask: u32 = 0x01 << offset;
22242 pub mod R {}
22243 pub mod W {}
22244 pub mod RW {
22245 #[doc = "Selecting Pad: GPIO_EMC_27 for Mode: ALT1"]
22246 pub const GPIO_EMC_27_ALT1: u32 = 0;
22247 #[doc = "Selecting Pad: GPIO_SD_B0_04 for Mode: ALT1"]
22248 pub const GPIO_SD_B0_04_ALT1: u32 = 0x01;
22249 }
22250 }
22251}
22252#[doc = "FLEXPWM1_PWMB3_SELECT_INPUT DAISY Register"]
22253pub mod FLEXPWM1_PWMB3_SELECT_INPUT {
22254 #[doc = "Selecting Pads Involved in Daisy Chain."]
22255 pub mod DAISY {
22256 pub const offset: u32 = 0;
22257 pub const mask: u32 = 0x07 << offset;
22258 pub mod R {}
22259 pub mod W {}
22260 pub mod RW {
22261 #[doc = "Selecting Pad: GPIO_SD_B1_01 for Mode: ALT2"]
22262 pub const GPIO_SD_B1_01_ALT2: u32 = 0;
22263 #[doc = "Selecting Pad: GPIO_EMC_13 for Mode: ALT4"]
22264 pub const GPIO_EMC_13_ALT4: u32 = 0x01;
22265 #[doc = "Selecting Pad: GPIO_EMC_39 for Mode: ALT1"]
22266 pub const GPIO_EMC_39_ALT1: u32 = 0x02;
22267 #[doc = "Selecting Pad: GPIO_AD_B0_11 for Mode: ALT1"]
22268 pub const GPIO_AD_B0_11_ALT1: u32 = 0x03;
22269 #[doc = "Selecting Pad: GPIO_B1_01 for Mode: ALT6"]
22270 pub const GPIO_B1_01_ALT6: u32 = 0x04;
22271 }
22272 }
22273}
22274#[doc = "FLEXPWM1_PWMB0_SELECT_INPUT DAISY Register"]
22275pub mod FLEXPWM1_PWMB0_SELECT_INPUT {
22276 #[doc = "Selecting Pads Involved in Daisy Chain."]
22277 pub mod DAISY {
22278 pub const offset: u32 = 0;
22279 pub const mask: u32 = 0x01 << offset;
22280 pub mod R {}
22281 pub mod W {}
22282 pub mod RW {
22283 #[doc = "Selecting Pad: GPIO_EMC_24 for Mode: ALT1"]
22284 pub const GPIO_EMC_24_ALT1: u32 = 0;
22285 #[doc = "Selecting Pad: GPIO_SD_B0_01 for Mode: ALT1"]
22286 pub const GPIO_SD_B0_01_ALT1: u32 = 0x01;
22287 }
22288 }
22289}
22290#[doc = "FLEXPWM1_PWMB1_SELECT_INPUT DAISY Register"]
22291pub mod FLEXPWM1_PWMB1_SELECT_INPUT {
22292 #[doc = "Selecting Pads Involved in Daisy Chain."]
22293 pub mod DAISY {
22294 pub const offset: u32 = 0;
22295 pub const mask: u32 = 0x01 << offset;
22296 pub mod R {}
22297 pub mod W {}
22298 pub mod RW {
22299 #[doc = "Selecting Pad: GPIO_EMC_26 for Mode: ALT1"]
22300 pub const GPIO_EMC_26_ALT1: u32 = 0;
22301 #[doc = "Selecting Pad: GPIO_SD_B0_03 for Mode: ALT1"]
22302 pub const GPIO_SD_B0_03_ALT1: u32 = 0x01;
22303 }
22304 }
22305}
22306#[doc = "FLEXPWM1_PWMB2_SELECT_INPUT DAISY Register"]
22307pub mod FLEXPWM1_PWMB2_SELECT_INPUT {
22308 #[doc = "Selecting Pads Involved in Daisy Chain."]
22309 pub mod DAISY {
22310 pub const offset: u32 = 0;
22311 pub const mask: u32 = 0x01 << offset;
22312 pub mod R {}
22313 pub mod W {}
22314 pub mod RW {
22315 #[doc = "Selecting Pad: GPIO_EMC_28 for Mode: ALT1"]
22316 pub const GPIO_EMC_28_ALT1: u32 = 0;
22317 #[doc = "Selecting Pad: GPIO_SD_B0_05 for Mode: ALT1"]
22318 pub const GPIO_SD_B0_05_ALT1: u32 = 0x01;
22319 }
22320 }
22321}
22322#[doc = "FLEXPWM2_PWMA3_SELECT_INPUT DAISY Register"]
22323pub mod FLEXPWM2_PWMA3_SELECT_INPUT {
22324 #[doc = "Selecting Pads Involved in Daisy Chain."]
22325 pub mod DAISY {
22326 pub const offset: u32 = 0;
22327 pub const mask: u32 = 0x07 << offset;
22328 pub mod R {}
22329 pub mod W {}
22330 pub mod RW {
22331 #[doc = "Selecting Pad: GPIO_SD_B1_02 for Mode: ALT2"]
22332 pub const GPIO_SD_B1_02_ALT2: u32 = 0;
22333 #[doc = "Selecting Pad: GPIO_EMC_19 for Mode: ALT1"]
22334 pub const GPIO_EMC_19_ALT1: u32 = 0x01;
22335 #[doc = "Selecting Pad: GPIO_AD_B0_00 for Mode: ALT0"]
22336 pub const GPIO_AD_B0_00_ALT0: u32 = 0x02;
22337 #[doc = "Selecting Pad: GPIO_AD_B0_09 for Mode: ALT1"]
22338 pub const GPIO_AD_B0_09_ALT1: u32 = 0x03;
22339 #[doc = "Selecting Pad: GPIO_B1_02 for Mode: ALT6"]
22340 pub const GPIO_B1_02_ALT6: u32 = 0x04;
22341 }
22342 }
22343}
22344#[doc = "FLEXPWM2_PWMA0_SELECT_INPUT DAISY Register"]
22345pub mod FLEXPWM2_PWMA0_SELECT_INPUT {
22346 #[doc = "Selecting Pads Involved in Daisy Chain."]
22347 pub mod DAISY {
22348 pub const offset: u32 = 0;
22349 pub const mask: u32 = 0x01 << offset;
22350 pub mod R {}
22351 pub mod W {}
22352 pub mod RW {
22353 #[doc = "Selecting Pad: GPIO_EMC_06 for Mode: ALT1"]
22354 pub const GPIO_EMC_06_ALT1: u32 = 0;
22355 #[doc = "Selecting Pad: GPIO_B0_06 for Mode: ALT2"]
22356 pub const GPIO_B0_06_ALT2: u32 = 0x01;
22357 }
22358 }
22359}
22360#[doc = "FLEXPWM2_PWMA1_SELECT_INPUT DAISY Register"]
22361pub mod FLEXPWM2_PWMA1_SELECT_INPUT {
22362 #[doc = "Selecting Pads Involved in Daisy Chain."]
22363 pub mod DAISY {
22364 pub const offset: u32 = 0;
22365 pub const mask: u32 = 0x01 << offset;
22366 pub mod R {}
22367 pub mod W {}
22368 pub mod RW {
22369 #[doc = "Selecting Pad: GPIO_EMC_08 for Mode: ALT1"]
22370 pub const GPIO_EMC_08_ALT1: u32 = 0;
22371 #[doc = "Selecting Pad: GPIO_B0_08 for Mode: ALT2"]
22372 pub const GPIO_B0_08_ALT2: u32 = 0x01;
22373 }
22374 }
22375}
22376#[doc = "FLEXPWM2_PWMA2_SELECT_INPUT DAISY Register"]
22377pub mod FLEXPWM2_PWMA2_SELECT_INPUT {
22378 #[doc = "Selecting Pads Involved in Daisy Chain."]
22379 pub mod DAISY {
22380 pub const offset: u32 = 0;
22381 pub const mask: u32 = 0x01 << offset;
22382 pub mod R {}
22383 pub mod W {}
22384 pub mod RW {
22385 #[doc = "Selecting Pad: GPIO_EMC_10 for Mode: ALT1"]
22386 pub const GPIO_EMC_10_ALT1: u32 = 0;
22387 #[doc = "Selecting Pad: GPIO_B0_10 for Mode: ALT2"]
22388 pub const GPIO_B0_10_ALT2: u32 = 0x01;
22389 }
22390 }
22391}
22392#[doc = "FLEXPWM2_PWMB3_SELECT_INPUT DAISY Register"]
22393pub mod FLEXPWM2_PWMB3_SELECT_INPUT {
22394 #[doc = "Selecting Pads Involved in Daisy Chain."]
22395 pub mod DAISY {
22396 pub const offset: u32 = 0;
22397 pub const mask: u32 = 0x03 << offset;
22398 pub mod R {}
22399 pub mod W {}
22400 pub mod RW {
22401 #[doc = "Selecting Pad: GPIO_SD_B1_03 for Mode: ALT2"]
22402 pub const GPIO_SD_B1_03_ALT2: u32 = 0;
22403 #[doc = "Selecting Pad: GPIO_EMC_20 for Mode: ALT1"]
22404 pub const GPIO_EMC_20_ALT1: u32 = 0x01;
22405 #[doc = "Selecting Pad: GPIO_AD_B0_01 for Mode: ALT0"]
22406 pub const GPIO_AD_B0_01_ALT0: u32 = 0x02;
22407 #[doc = "Selecting Pad: GPIO_B1_03 for Mode: ALT6"]
22408 pub const GPIO_B1_03_ALT6: u32 = 0x03;
22409 }
22410 }
22411}
22412#[doc = "FLEXPWM2_PWMB0_SELECT_INPUT DAISY Register"]
22413pub mod FLEXPWM2_PWMB0_SELECT_INPUT {
22414 #[doc = "Selecting Pads Involved in Daisy Chain."]
22415 pub mod DAISY {
22416 pub const offset: u32 = 0;
22417 pub const mask: u32 = 0x01 << offset;
22418 pub mod R {}
22419 pub mod W {}
22420 pub mod RW {
22421 #[doc = "Selecting Pad: GPIO_EMC_07 for Mode: ALT1"]
22422 pub const GPIO_EMC_07_ALT1: u32 = 0;
22423 #[doc = "Selecting Pad: GPIO_B0_07 for Mode: ALT2"]
22424 pub const GPIO_B0_07_ALT2: u32 = 0x01;
22425 }
22426 }
22427}
22428#[doc = "FLEXPWM2_PWMB1_SELECT_INPUT DAISY Register"]
22429pub mod FLEXPWM2_PWMB1_SELECT_INPUT {
22430 #[doc = "Selecting Pads Involved in Daisy Chain."]
22431 pub mod DAISY {
22432 pub const offset: u32 = 0;
22433 pub const mask: u32 = 0x01 << offset;
22434 pub mod R {}
22435 pub mod W {}
22436 pub mod RW {
22437 #[doc = "Selecting Pad: GPIO_EMC_09 for Mode: ALT1"]
22438 pub const GPIO_EMC_09_ALT1: u32 = 0;
22439 #[doc = "Selecting Pad: GPIO_B0_09 for Mode: ALT2"]
22440 pub const GPIO_B0_09_ALT2: u32 = 0x01;
22441 }
22442 }
22443}
22444#[doc = "FLEXPWM2_PWMB2_SELECT_INPUT DAISY Register"]
22445pub mod FLEXPWM2_PWMB2_SELECT_INPUT {
22446 #[doc = "Selecting Pads Involved in Daisy Chain."]
22447 pub mod DAISY {
22448 pub const offset: u32 = 0;
22449 pub const mask: u32 = 0x01 << offset;
22450 pub mod R {}
22451 pub mod W {}
22452 pub mod RW {
22453 #[doc = "Selecting Pad: GPIO_EMC_11 for Mode: ALT1"]
22454 pub const GPIO_EMC_11_ALT1: u32 = 0;
22455 #[doc = "Selecting Pad: GPIO_B0_11 for Mode: ALT2"]
22456 pub const GPIO_B0_11_ALT2: u32 = 0x01;
22457 }
22458 }
22459}
22460#[doc = "FLEXPWM4_PWMA0_SELECT_INPUT DAISY Register"]
22461pub mod FLEXPWM4_PWMA0_SELECT_INPUT {
22462 #[doc = "Selecting Pads Involved in Daisy Chain."]
22463 pub mod DAISY {
22464 pub const offset: u32 = 0;
22465 pub const mask: u32 = 0x01 << offset;
22466 pub mod R {}
22467 pub mod W {}
22468 pub mod RW {
22469 #[doc = "Selecting Pad: GPIO_EMC_00 for Mode: ALT1"]
22470 pub const GPIO_EMC_00_ALT1: u32 = 0;
22471 #[doc = "Selecting Pad: GPIO_AD_B1_08 for Mode: ALT1"]
22472 pub const GPIO_AD_B1_08_ALT1: u32 = 0x01;
22473 }
22474 }
22475}
22476#[doc = "FLEXPWM4_PWMA1_SELECT_INPUT DAISY Register"]
22477pub mod FLEXPWM4_PWMA1_SELECT_INPUT {
22478 #[doc = "Selecting Pads Involved in Daisy Chain."]
22479 pub mod DAISY {
22480 pub const offset: u32 = 0;
22481 pub const mask: u32 = 0x01 << offset;
22482 pub mod R {}
22483 pub mod W {}
22484 pub mod RW {
22485 #[doc = "Selecting Pad: GPIO_EMC_02 for Mode: ALT1"]
22486 pub const GPIO_EMC_02_ALT1: u32 = 0;
22487 #[doc = "Selecting Pad: GPIO_AD_B1_09 for Mode: ALT1"]
22488 pub const GPIO_AD_B1_09_ALT1: u32 = 0x01;
22489 }
22490 }
22491}
22492#[doc = "FLEXPWM4_PWMA2_SELECT_INPUT DAISY Register"]
22493pub mod FLEXPWM4_PWMA2_SELECT_INPUT {
22494 #[doc = "Selecting Pads Involved in Daisy Chain."]
22495 pub mod DAISY {
22496 pub const offset: u32 = 0;
22497 pub const mask: u32 = 0x01 << offset;
22498 pub mod R {}
22499 pub mod W {}
22500 pub mod RW {
22501 #[doc = "Selecting Pad: GPIO_EMC_04 for Mode: ALT1"]
22502 pub const GPIO_EMC_04_ALT1: u32 = 0;
22503 #[doc = "Selecting Pad: GPIO_B1_14 for Mode: ALT1"]
22504 pub const GPIO_B1_14_ALT1: u32 = 0x01;
22505 }
22506 }
22507}
22508#[doc = "FLEXPWM4_PWMA3_SELECT_INPUT DAISY Register"]
22509pub mod FLEXPWM4_PWMA3_SELECT_INPUT {
22510 #[doc = "Selecting Pads Involved in Daisy Chain."]
22511 pub mod DAISY {
22512 pub const offset: u32 = 0;
22513 pub const mask: u32 = 0x01 << offset;
22514 pub mod R {}
22515 pub mod W {}
22516 pub mod RW {
22517 #[doc = "Selecting Pad: GPIO_EMC_17 for Mode: ALT1"]
22518 pub const GPIO_EMC_17_ALT1: u32 = 0;
22519 #[doc = "Selecting Pad: GPIO_B1_15 for Mode: ALT1"]
22520 pub const GPIO_B1_15_ALT1: u32 = 0x01;
22521 }
22522 }
22523}
22524#[doc = "FLEXSPIA_DQS_SELECT_INPUT DAISY Register"]
22525pub mod FLEXSPIA_DQS_SELECT_INPUT {
22526 #[doc = "Selecting Pads Involved in Daisy Chain."]
22527 pub mod DAISY {
22528 pub const offset: u32 = 0;
22529 pub const mask: u32 = 0x01 << offset;
22530 pub mod R {}
22531 pub mod W {}
22532 pub mod RW {
22533 #[doc = "Selecting Pad: GPIO_SD_B1_05 for Mode: ALT1"]
22534 pub const GPIO_SD_B1_05_ALT1: u32 = 0;
22535 #[doc = "Selecting Pad: GPIO_AD_B1_09 for Mode: ALT0"]
22536 pub const GPIO_AD_B1_09_ALT0: u32 = 0x01;
22537 }
22538 }
22539}
22540#[doc = "FLEXSPIA_DATA0_SELECT_INPUT DAISY Register"]
22541pub mod FLEXSPIA_DATA0_SELECT_INPUT {
22542 #[doc = "Selecting Pads Involved in Daisy Chain."]
22543 pub mod DAISY {
22544 pub const offset: u32 = 0;
22545 pub const mask: u32 = 0x01 << offset;
22546 pub mod R {}
22547 pub mod W {}
22548 pub mod RW {
22549 #[doc = "Selecting Pad: GPIO_SD_B1_08 for Mode: ALT1"]
22550 pub const GPIO_SD_B1_08_ALT1: u32 = 0;
22551 #[doc = "Selecting Pad: GPIO_AD_B1_13 for Mode: ALT0"]
22552 pub const GPIO_AD_B1_13_ALT0: u32 = 0x01;
22553 }
22554 }
22555}
22556#[doc = "FLEXSPIA_DATA1_SELECT_INPUT DAISY Register"]
22557pub mod FLEXSPIA_DATA1_SELECT_INPUT {
22558 #[doc = "Selecting Pads Involved in Daisy Chain."]
22559 pub mod DAISY {
22560 pub const offset: u32 = 0;
22561 pub const mask: u32 = 0x01 << offset;
22562 pub mod R {}
22563 pub mod W {}
22564 pub mod RW {
22565 #[doc = "Selecting Pad: GPIO_SD_B1_09 for Mode: ALT1"]
22566 pub const GPIO_SD_B1_09_ALT1: u32 = 0;
22567 #[doc = "Selecting Pad: GPIO_AD_B1_12 for Mode: ALT0"]
22568 pub const GPIO_AD_B1_12_ALT0: u32 = 0x01;
22569 }
22570 }
22571}
22572#[doc = "FLEXSPIA_DATA2_SELECT_INPUT DAISY Register"]
22573pub mod FLEXSPIA_DATA2_SELECT_INPUT {
22574 #[doc = "Selecting Pads Involved in Daisy Chain."]
22575 pub mod DAISY {
22576 pub const offset: u32 = 0;
22577 pub const mask: u32 = 0x01 << offset;
22578 pub mod R {}
22579 pub mod W {}
22580 pub mod RW {
22581 #[doc = "Selecting Pad: GPIO_SD_B1_10 for Mode: ALT1"]
22582 pub const GPIO_SD_B1_10_ALT1: u32 = 0;
22583 #[doc = "Selecting Pad: GPIO_AD_B1_11 for Mode: ALT0"]
22584 pub const GPIO_AD_B1_11_ALT0: u32 = 0x01;
22585 }
22586 }
22587}
22588#[doc = "FLEXSPIA_DATA3_SELECT_INPUT DAISY Register"]
22589pub mod FLEXSPIA_DATA3_SELECT_INPUT {
22590 #[doc = "Selecting Pads Involved in Daisy Chain."]
22591 pub mod DAISY {
22592 pub const offset: u32 = 0;
22593 pub const mask: u32 = 0x01 << offset;
22594 pub mod R {}
22595 pub mod W {}
22596 pub mod RW {
22597 #[doc = "Selecting Pad: GPIO_SD_B1_11 for Mode: ALT1"]
22598 pub const GPIO_SD_B1_11_ALT1: u32 = 0;
22599 #[doc = "Selecting Pad: GPIO_AD_B1_10 for Mode: ALT0"]
22600 pub const GPIO_AD_B1_10_ALT0: u32 = 0x01;
22601 }
22602 }
22603}
22604#[doc = "FLEXSPIB_DATA0_SELECT_INPUT DAISY Register"]
22605pub mod FLEXSPIB_DATA0_SELECT_INPUT {
22606 #[doc = "Selecting Pads Involved in Daisy Chain."]
22607 pub mod DAISY {
22608 pub const offset: u32 = 0;
22609 pub const mask: u32 = 0x01 << offset;
22610 pub mod R {}
22611 pub mod W {}
22612 pub mod RW {
22613 #[doc = "Selecting Pad: GPIO_SD_B1_03 for Mode: ALT1"]
22614 pub const GPIO_SD_B1_03_ALT1: u32 = 0;
22615 #[doc = "Selecting Pad: GPIO_AD_B1_07 for Mode: ALT0"]
22616 pub const GPIO_AD_B1_07_ALT0: u32 = 0x01;
22617 }
22618 }
22619}
22620#[doc = "FLEXSPIB_DATA1_SELECT_INPUT DAISY Register"]
22621pub mod FLEXSPIB_DATA1_SELECT_INPUT {
22622 #[doc = "Selecting Pads Involved in Daisy Chain."]
22623 pub mod DAISY {
22624 pub const offset: u32 = 0;
22625 pub const mask: u32 = 0x01 << offset;
22626 pub mod R {}
22627 pub mod W {}
22628 pub mod RW {
22629 #[doc = "Selecting Pad: GPIO_SD_B1_02 for Mode: ALT1"]
22630 pub const GPIO_SD_B1_02_ALT1: u32 = 0;
22631 #[doc = "Selecting Pad: GPIO_AD_B1_06 for Mode: ALT0"]
22632 pub const GPIO_AD_B1_06_ALT0: u32 = 0x01;
22633 }
22634 }
22635}
22636#[doc = "FLEXSPIB_DATA2_SELECT_INPUT DAISY Register"]
22637pub mod FLEXSPIB_DATA2_SELECT_INPUT {
22638 #[doc = "Selecting Pads Involved in Daisy Chain."]
22639 pub mod DAISY {
22640 pub const offset: u32 = 0;
22641 pub const mask: u32 = 0x01 << offset;
22642 pub mod R {}
22643 pub mod W {}
22644 pub mod RW {
22645 #[doc = "Selecting Pad: GPIO_SD_B1_01 for Mode: ALT1"]
22646 pub const GPIO_SD_B1_01_ALT1: u32 = 0;
22647 #[doc = "Selecting Pad: GPIO_AD_B1_05 for Mode: ALT0"]
22648 pub const GPIO_AD_B1_05_ALT0: u32 = 0x01;
22649 }
22650 }
22651}
22652#[doc = "FLEXSPIB_DATA3_SELECT_INPUT DAISY Register"]
22653pub mod FLEXSPIB_DATA3_SELECT_INPUT {
22654 #[doc = "Selecting Pads Involved in Daisy Chain."]
22655 pub mod DAISY {
22656 pub const offset: u32 = 0;
22657 pub const mask: u32 = 0x01 << offset;
22658 pub mod R {}
22659 pub mod W {}
22660 pub mod RW {
22661 #[doc = "Selecting Pad: GPIO_SD_B1_00 for Mode: ALT1"]
22662 pub const GPIO_SD_B1_00_ALT1: u32 = 0;
22663 #[doc = "Selecting Pad: GPIO_AD_B1_04 for Mode: ALT0"]
22664 pub const GPIO_AD_B1_04_ALT0: u32 = 0x01;
22665 }
22666 }
22667}
22668#[doc = "FLEXSPIA_SCK_SELECT_INPUT DAISY Register"]
22669pub mod FLEXSPIA_SCK_SELECT_INPUT {
22670 #[doc = "Selecting Pads Involved in Daisy Chain."]
22671 pub mod DAISY {
22672 pub const offset: u32 = 0;
22673 pub const mask: u32 = 0x01 << offset;
22674 pub mod R {}
22675 pub mod W {}
22676 pub mod RW {
22677 #[doc = "Selecting Pad: GPIO_SD_B1_07 for Mode: ALT1"]
22678 pub const GPIO_SD_B1_07_ALT1: u32 = 0;
22679 #[doc = "Selecting Pad: GPIO_AD_B1_14 for Mode: ALT0"]
22680 pub const GPIO_AD_B1_14_ALT0: u32 = 0x01;
22681 }
22682 }
22683}
22684#[doc = "LPI2C1_SCL_SELECT_INPUT DAISY Register"]
22685pub mod LPI2C1_SCL_SELECT_INPUT {
22686 #[doc = "Selecting Pads Involved in Daisy Chain."]
22687 pub mod DAISY {
22688 pub const offset: u32 = 0;
22689 pub const mask: u32 = 0x01 << offset;
22690 pub mod R {}
22691 pub mod W {}
22692 pub mod RW {
22693 #[doc = "Selecting Pad: GPIO_SD_B1_04 for Mode: ALT2"]
22694 pub const GPIO_SD_B1_04_ALT2: u32 = 0;
22695 #[doc = "Selecting Pad: GPIO_AD_B1_00 for Mode: ALT3"]
22696 pub const GPIO_AD_B1_00_ALT3: u32 = 0x01;
22697 }
22698 }
22699}
22700#[doc = "LPI2C1_SDA_SELECT_INPUT DAISY Register"]
22701pub mod LPI2C1_SDA_SELECT_INPUT {
22702 #[doc = "Selecting Pads Involved in Daisy Chain."]
22703 pub mod DAISY {
22704 pub const offset: u32 = 0;
22705 pub const mask: u32 = 0x01 << offset;
22706 pub mod R {}
22707 pub mod W {}
22708 pub mod RW {
22709 #[doc = "Selecting Pad: GPIO_SD_B1_05 for Mode: ALT2"]
22710 pub const GPIO_SD_B1_05_ALT2: u32 = 0;
22711 #[doc = "Selecting Pad: GPIO_AD_B1_01 for Mode: ALT3"]
22712 pub const GPIO_AD_B1_01_ALT3: u32 = 0x01;
22713 }
22714 }
22715}
22716#[doc = "LPI2C2_SCL_SELECT_INPUT DAISY Register"]
22717pub mod LPI2C2_SCL_SELECT_INPUT {
22718 #[doc = "Selecting Pads Involved in Daisy Chain."]
22719 pub mod DAISY {
22720 pub const offset: u32 = 0;
22721 pub const mask: u32 = 0x01 << offset;
22722 pub mod R {}
22723 pub mod W {}
22724 pub mod RW {
22725 #[doc = "Selecting Pad: GPIO_SD_B1_11 for Mode: ALT3"]
22726 pub const GPIO_SD_B1_11_ALT3: u32 = 0;
22727 #[doc = "Selecting Pad: GPIO_B0_04 for Mode: ALT2"]
22728 pub const GPIO_B0_04_ALT2: u32 = 0x01;
22729 }
22730 }
22731}
22732#[doc = "LPI2C2_SDA_SELECT_INPUT DAISY Register"]
22733pub mod LPI2C2_SDA_SELECT_INPUT {
22734 #[doc = "Selecting Pads Involved in Daisy Chain."]
22735 pub mod DAISY {
22736 pub const offset: u32 = 0;
22737 pub const mask: u32 = 0x01 << offset;
22738 pub mod R {}
22739 pub mod W {}
22740 pub mod RW {
22741 #[doc = "Selecting Pad: GPIO_SD_B1_10 for Mode: ALT3"]
22742 pub const GPIO_SD_B1_10_ALT3: u32 = 0;
22743 #[doc = "Selecting Pad: GPIO_B0_05 for Mode: ALT2"]
22744 pub const GPIO_B0_05_ALT2: u32 = 0x01;
22745 }
22746 }
22747}
22748#[doc = "LPI2C3_SCL_SELECT_INPUT DAISY Register"]
22749pub mod LPI2C3_SCL_SELECT_INPUT {
22750 #[doc = "Selecting Pads Involved in Daisy Chain."]
22751 pub mod DAISY {
22752 pub const offset: u32 = 0;
22753 pub const mask: u32 = 0x03 << offset;
22754 pub mod R {}
22755 pub mod W {}
22756 pub mod RW {
22757 #[doc = "Selecting Pad: GPIO_EMC_22 for Mode: ALT2"]
22758 pub const GPIO_EMC_22_ALT2: u32 = 0;
22759 #[doc = "Selecting Pad: GPIO_SD_B0_00 for Mode: ALT2"]
22760 pub const GPIO_SD_B0_00_ALT2: u32 = 0x01;
22761 #[doc = "Selecting Pad: GPIO_AD_B1_07 for Mode: ALT1"]
22762 pub const GPIO_AD_B1_07_ALT1: u32 = 0x02;
22763 }
22764 }
22765}
22766#[doc = "LPI2C3_SDA_SELECT_INPUT DAISY Register"]
22767pub mod LPI2C3_SDA_SELECT_INPUT {
22768 #[doc = "Selecting Pads Involved in Daisy Chain."]
22769 pub mod DAISY {
22770 pub const offset: u32 = 0;
22771 pub const mask: u32 = 0x03 << offset;
22772 pub mod R {}
22773 pub mod W {}
22774 pub mod RW {
22775 #[doc = "Selecting Pad: GPIO_EMC_21 for Mode: ALT2"]
22776 pub const GPIO_EMC_21_ALT2: u32 = 0;
22777 #[doc = "Selecting Pad: GPIO_SD_B0_01 for Mode: ALT2"]
22778 pub const GPIO_SD_B0_01_ALT2: u32 = 0x01;
22779 #[doc = "Selecting Pad: GPIO_AD_B1_06 for Mode: ALT1"]
22780 pub const GPIO_AD_B1_06_ALT1: u32 = 0x02;
22781 }
22782 }
22783}
22784#[doc = "LPI2C4_SCL_SELECT_INPUT DAISY Register"]
22785pub mod LPI2C4_SCL_SELECT_INPUT {
22786 #[doc = "Selecting Pads Involved in Daisy Chain."]
22787 pub mod DAISY {
22788 pub const offset: u32 = 0;
22789 pub const mask: u32 = 0x01 << offset;
22790 pub mod R {}
22791 pub mod W {}
22792 pub mod RW {
22793 #[doc = "Selecting Pad: GPIO_EMC_12 for Mode: ALT2"]
22794 pub const GPIO_EMC_12_ALT2: u32 = 0;
22795 #[doc = "Selecting Pad: GPIO_AD_B0_12 for Mode: ALT0"]
22796 pub const GPIO_AD_B0_12_ALT0: u32 = 0x01;
22797 }
22798 }
22799}
22800#[doc = "LPI2C4_SDA_SELECT_INPUT DAISY Register"]
22801pub mod LPI2C4_SDA_SELECT_INPUT {
22802 #[doc = "Selecting Pads Involved in Daisy Chain."]
22803 pub mod DAISY {
22804 pub const offset: u32 = 0;
22805 pub const mask: u32 = 0x01 << offset;
22806 pub mod R {}
22807 pub mod W {}
22808 pub mod RW {
22809 #[doc = "Selecting Pad: GPIO_EMC_11 for Mode: ALT2"]
22810 pub const GPIO_EMC_11_ALT2: u32 = 0;
22811 #[doc = "Selecting Pad: GPIO_AD_B0_13 for Mode: ALT0"]
22812 pub const GPIO_AD_B0_13_ALT0: u32 = 0x01;
22813 }
22814 }
22815}
22816#[doc = "LPSPI1_PCS0_SELECT_INPUT DAISY Register"]
22817pub mod LPSPI1_PCS0_SELECT_INPUT {
22818 #[doc = "Selecting Pads Involved in Daisy Chain."]
22819 pub mod DAISY {
22820 pub const offset: u32 = 0;
22821 pub const mask: u32 = 0x01 << offset;
22822 pub mod R {}
22823 pub mod W {}
22824 pub mod RW {
22825 #[doc = "Selecting Pad: GPIO_SD_B0_01 for Mode: ALT4"]
22826 pub const GPIO_SD_B0_01_ALT4: u32 = 0;
22827 #[doc = "Selecting Pad: GPIO_EMC_30 for Mode: ALT3"]
22828 pub const GPIO_EMC_30_ALT3: u32 = 0x01;
22829 }
22830 }
22831}
22832#[doc = "LPSPI1_SCK_SELECT_INPUT DAISY Register"]
22833pub mod LPSPI1_SCK_SELECT_INPUT {
22834 #[doc = "Selecting Pads Involved in Daisy Chain."]
22835 pub mod DAISY {
22836 pub const offset: u32 = 0;
22837 pub const mask: u32 = 0x01 << offset;
22838 pub mod R {}
22839 pub mod W {}
22840 pub mod RW {
22841 #[doc = "Selecting Pad: GPIO_EMC_27 for Mode: ALT3"]
22842 pub const GPIO_EMC_27_ALT3: u32 = 0;
22843 #[doc = "Selecting Pad: GPIO_SD_B0_00 for Mode: ALT4"]
22844 pub const GPIO_SD_B0_00_ALT4: u32 = 0x01;
22845 }
22846 }
22847}
22848#[doc = "LPSPI1_SDI_SELECT_INPUT DAISY Register"]
22849pub mod LPSPI1_SDI_SELECT_INPUT {
22850 #[doc = "Selecting Pads Involved in Daisy Chain."]
22851 pub mod DAISY {
22852 pub const offset: u32 = 0;
22853 pub const mask: u32 = 0x01 << offset;
22854 pub mod R {}
22855 pub mod W {}
22856 pub mod RW {
22857 #[doc = "Selecting Pad: GPIO_EMC_29 for Mode: ALT3"]
22858 pub const GPIO_EMC_29_ALT3: u32 = 0;
22859 #[doc = "Selecting Pad: GPIO_AD_B0_03 for Mode: ALT4"]
22860 pub const GPIO_SD_B0_03_ALT4: u32 = 0x01;
22861 }
22862 }
22863}
22864#[doc = "LPSPI1_SDO_SELECT_INPUT DAISY Register"]
22865pub mod LPSPI1_SDO_SELECT_INPUT {
22866 #[doc = "Selecting Pads Involved in Daisy Chain."]
22867 pub mod DAISY {
22868 pub const offset: u32 = 0;
22869 pub const mask: u32 = 0x01 << offset;
22870 pub mod R {}
22871 pub mod W {}
22872 pub mod RW {
22873 #[doc = "Selecting Pad: GPIO_EMC_28 for Mode: ALT3"]
22874 pub const GPIO_EMC_28_ALT3: u32 = 0;
22875 #[doc = "Selecting Pad: GPIO_SD_B0_02 for Mode: ALT4"]
22876 pub const GPIO_SD_B0_02_ALT4: u32 = 0x01;
22877 }
22878 }
22879}
22880#[doc = "LPSPI2_PCS0_SELECT_INPUT DAISY Register"]
22881pub mod LPSPI2_PCS0_SELECT_INPUT {
22882 #[doc = "Selecting Pads Involved in Daisy Chain."]
22883 pub mod DAISY {
22884 pub const offset: u32 = 0;
22885 pub const mask: u32 = 0x01 << offset;
22886 pub mod R {}
22887 pub mod W {}
22888 pub mod RW {
22889 #[doc = "Selecting Pad: GPIO_SD_B1_06 for Mode: ALT4"]
22890 pub const GPIO_SD_B1_06_ALT4: u32 = 0;
22891 #[doc = "Selecting Pad: GPIO_EMC_01 for Mode: ALT2"]
22892 pub const GPIO_EMC_01_ALT2: u32 = 0x01;
22893 }
22894 }
22895}
22896#[doc = "LPSPI2_SCK_SELECT_INPUT DAISY Register"]
22897pub mod LPSPI2_SCK_SELECT_INPUT {
22898 #[doc = "Selecting Pads Involved in Daisy Chain."]
22899 pub mod DAISY {
22900 pub const offset: u32 = 0;
22901 pub const mask: u32 = 0x01 << offset;
22902 pub mod R {}
22903 pub mod W {}
22904 pub mod RW {
22905 #[doc = "Selecting Pad: GPIO_SD_B1_07 for Mode: ALT4"]
22906 pub const GPIO_SD_B1_07_ALT4: u32 = 0;
22907 #[doc = "Selecting Pad: GPIO_EMC_00 for Mode: ALT2"]
22908 pub const GPIO_EMC_00_ALT2: u32 = 0x01;
22909 }
22910 }
22911}
22912#[doc = "LPSPI2_SDI_SELECT_INPUT DAISY Register"]
22913pub mod LPSPI2_SDI_SELECT_INPUT {
22914 #[doc = "Selecting Pads Involved in Daisy Chain."]
22915 pub mod DAISY {
22916 pub const offset: u32 = 0;
22917 pub const mask: u32 = 0x01 << offset;
22918 pub mod R {}
22919 pub mod W {}
22920 pub mod RW {
22921 #[doc = "Selecting Pad: GPIO_SD_B1_09 for Mode: ALT4"]
22922 pub const GPIO_SD_B1_09_ALT4: u32 = 0;
22923 #[doc = "Selecting Pad: GPIO_EMC_03 for Mode: ALT2"]
22924 pub const GPIO_EMC_03_ALT2: u32 = 0x01;
22925 }
22926 }
22927}
22928#[doc = "LPSPI2_SDO_SELECT_INPUT DAISY Register"]
22929pub mod LPSPI2_SDO_SELECT_INPUT {
22930 #[doc = "Selecting Pads Involved in Daisy Chain."]
22931 pub mod DAISY {
22932 pub const offset: u32 = 0;
22933 pub const mask: u32 = 0x01 << offset;
22934 pub mod R {}
22935 pub mod W {}
22936 pub mod RW {
22937 #[doc = "Selecting Pad: GPIO_SD_B1_08 for Mode: ALT4"]
22938 pub const GPIO_SD_B1_08_ALT4: u32 = 0;
22939 #[doc = "Selecting Pad: GPIO_EMC_02 for Mode: ALT2"]
22940 pub const GPIO_EMC_02_ALT2: u32 = 0x01;
22941 }
22942 }
22943}
22944#[doc = "LPSPI3_PCS0_SELECT_INPUT DAISY Register"]
22945pub mod LPSPI3_PCS0_SELECT_INPUT {
22946 #[doc = "Selecting Pads Involved in Daisy Chain."]
22947 pub mod DAISY {
22948 pub const offset: u32 = 0;
22949 pub const mask: u32 = 0x01 << offset;
22950 pub mod R {}
22951 pub mod W {}
22952 pub mod RW {
22953 #[doc = "Selecting Pad: GPIO_AD_B0_03 for Mode: ALT7"]
22954 pub const GPIO_AD_B0_03_ALT7: u32 = 0;
22955 #[doc = "Selecting Pad: GPIO_AD_B1_12 for Mode: ALT2"]
22956 pub const GPIO_AD_B1_12_ALT2: u32 = 0x01;
22957 }
22958 }
22959}
22960#[doc = "LPSPI3_SCK_SELECT_INPUT DAISY Register"]
22961pub mod LPSPI3_SCK_SELECT_INPUT {
22962 #[doc = "Selecting Pads Involved in Daisy Chain."]
22963 pub mod DAISY {
22964 pub const offset: u32 = 0;
22965 pub const mask: u32 = 0x01 << offset;
22966 pub mod R {}
22967 pub mod W {}
22968 pub mod RW {
22969 #[doc = "Selecting Pad: GPIO_AD_B0_00 for Mode: ALT7"]
22970 pub const GPIO_AD_B0_00_ALT7: u32 = 0;
22971 #[doc = "Selecting Pad: GPIO_AD_B1_15 for Mode: ALT2"]
22972 pub const GPIO_AD_B1_15: u32 = 0x01;
22973 }
22974 }
22975}
22976#[doc = "LPSPI3_SDI_SELECT_INPUT DAISY Register"]
22977pub mod LPSPI3_SDI_SELECT_INPUT {
22978 #[doc = "Selecting Pads Involved in Daisy Chain."]
22979 pub mod DAISY {
22980 pub const offset: u32 = 0;
22981 pub const mask: u32 = 0x01 << offset;
22982 pub mod R {}
22983 pub mod W {}
22984 pub mod RW {
22985 #[doc = "Selecting Pad: GPIO_AD_B0_02 for Mode: ALT7"]
22986 pub const GPIO_AD_B0_02_ALT7: u32 = 0;
22987 #[doc = "Selecting Pad: GPIO_AD_B1_13 for Mode: ALT2"]
22988 pub const GPIO_AD_B1_13_ALT2: u32 = 0x01;
22989 }
22990 }
22991}
22992#[doc = "LPSPI3_SDO_SELECT_INPUT DAISY Register"]
22993pub mod LPSPI3_SDO_SELECT_INPUT {
22994 #[doc = "Selecting Pads Involved in Daisy Chain."]
22995 pub mod DAISY {
22996 pub const offset: u32 = 0;
22997 pub const mask: u32 = 0x01 << offset;
22998 pub mod R {}
22999 pub mod W {}
23000 pub mod RW {
23001 #[doc = "Selecting Pad: GPIO_AD_B0_01 for Mode: ALT7"]
23002 pub const GPIO_AD_B0_01_ALT7: u32 = 0;
23003 #[doc = "Selecting Pad: GPIO_AD_B1_14 for Mode: ALT2"]
23004 pub const GPIO_AD_B1_14_ALT2: u32 = 0x01;
23005 }
23006 }
23007}
23008#[doc = "LPSPI4_PCS0_SELECT_INPUT DAISY Register"]
23009pub mod LPSPI4_PCS0_SELECT_INPUT {
23010 #[doc = "Selecting Pads Involved in Daisy Chain."]
23011 pub mod DAISY {
23012 pub const offset: u32 = 0;
23013 pub const mask: u32 = 0x01 << offset;
23014 pub mod R {}
23015 pub mod W {}
23016 pub mod RW {
23017 #[doc = "Selecting Pad: GPIO_B0_00 for Mode: ALT3"]
23018 pub const GPIO_B0_00_ALT3: u32 = 0;
23019 #[doc = "Selecting Pad:GPIO_B1_04 for Mode: ALT1"]
23020 pub const GPIO_B1_04_ALT1: u32 = 0x01;
23021 }
23022 }
23023}
23024#[doc = "LPSPI4_SCK_SELECT_INPUT DAISY Register"]
23025pub mod LPSPI4_SCK_SELECT_INPUT {
23026 #[doc = "Selecting Pads Involved in Daisy Chain."]
23027 pub mod DAISY {
23028 pub const offset: u32 = 0;
23029 pub const mask: u32 = 0x01 << offset;
23030 pub mod R {}
23031 pub mod W {}
23032 pub mod RW {
23033 #[doc = "Selecting Pad: GPIO_B0_03 for Mode: ALT3"]
23034 pub const GPIO_B0_03_ALT3: u32 = 0;
23035 #[doc = "Selecting Pad: GPIO_B1_07 for Mode: ALT1"]
23036 pub const GPIO_B1_07_ALT1: u32 = 0x01;
23037 }
23038 }
23039}
23040#[doc = "LPSPI4_SDI_SELECT_INPUT DAISY Register"]
23041pub mod LPSPI4_SDI_SELECT_INPUT {
23042 #[doc = "Selecting Pads Involved in Daisy Chain."]
23043 pub mod DAISY {
23044 pub const offset: u32 = 0;
23045 pub const mask: u32 = 0x01 << offset;
23046 pub mod R {}
23047 pub mod W {}
23048 pub mod RW {
23049 #[doc = "Selecting Pad: GPIO_B0_01 for Mode: ALT3"]
23050 pub const GPIO_B0_01_ALT3: u32 = 0;
23051 #[doc = "Selecting Pad: GPIO_B1_05 for Mode: ALT1"]
23052 pub const GPIO_B1_05_ALT1: u32 = 0x01;
23053 }
23054 }
23055}
23056#[doc = "LPSPI4_SDO_SELECT_INPUT DAISY Register"]
23057pub mod LPSPI4_SDO_SELECT_INPUT {
23058 #[doc = "Selecting Pads Involved in Daisy Chain."]
23059 pub mod DAISY {
23060 pub const offset: u32 = 0;
23061 pub const mask: u32 = 0x01 << offset;
23062 pub mod R {}
23063 pub mod W {}
23064 pub mod RW {
23065 #[doc = "Selecting Pad: GPIO_B0_02 for Mode: ALT3"]
23066 pub const GPIO_B0_02_ALT3: u32 = 0;
23067 #[doc = "Selecting Pad: GPIO_B1_06 for Mode: ALT1"]
23068 pub const GPIO_B1_06_ALT1: u32 = 0x01;
23069 }
23070 }
23071}
23072#[doc = "LPUART2_RX_SELECT_INPUT DAISY Register"]
23073pub mod LPUART2_RX_SELECT_INPUT {
23074 #[doc = "Selecting Pads Involved in Daisy Chain."]
23075 pub mod DAISY {
23076 pub const offset: u32 = 0;
23077 pub const mask: u32 = 0x01 << offset;
23078 pub mod R {}
23079 pub mod W {}
23080 pub mod RW {
23081 #[doc = "Selecting Pad: GPIO_SD_B1_10 for Mode: ALT2"]
23082 pub const GPIO_SD_B1_10_ALT2: u32 = 0;
23083 #[doc = "Selecting Pad: GPIO_AD_B1_03 for Mode: ALT2"]
23084 pub const GPIO_AD_B1_03_ALT2: u32 = 0x01;
23085 }
23086 }
23087}
23088#[doc = "LPUART2_TX_SELECT_INPUT DAISY Register"]
23089pub mod LPUART2_TX_SELECT_INPUT {
23090 #[doc = "Selecting Pads Involved in Daisy Chain."]
23091 pub mod DAISY {
23092 pub const offset: u32 = 0;
23093 pub const mask: u32 = 0x01 << offset;
23094 pub mod R {}
23095 pub mod W {}
23096 pub mod RW {
23097 #[doc = "Selecting Pad: GPIO_SD_B1_11 for Mode: ALT2"]
23098 pub const GPIO_SD_B1_11_ALT2: u32 = 0;
23099 #[doc = "Selecting Pad: GPIO_AD_B1_02 for Mode: ALT2"]
23100 pub const GPIO_AD_B1_02_ALT2: u32 = 0x01;
23101 }
23102 }
23103}
23104#[doc = "LPUART3_CTS_B_SELECT_INPUT DAISY Register"]
23105pub mod LPUART3_CTS_B_SELECT_INPUT {
23106 #[doc = "Selecting Pads Involved in Daisy Chain."]
23107 pub mod DAISY {
23108 pub const offset: u32 = 0;
23109 pub const mask: u32 = 0x01 << offset;
23110 pub mod R {}
23111 pub mod W {}
23112 pub mod RW {
23113 #[doc = "Selecting Pad: GPIO_EMC_15 for Mode: ALT2"]
23114 pub const GPIO_EMC_15_ALT2: u32 = 0;
23115 #[doc = "Selecting Pad: GPIO_AD_B1_04 for Mode: ALT2"]
23116 pub const GPIO_AD_B1_04_ALT2: u32 = 0x01;
23117 }
23118 }
23119}
23120#[doc = "LPUART3_RX_SELECT_INPUT DAISY Register"]
23121pub mod LPUART3_RX_SELECT_INPUT {
23122 #[doc = "Selecting Pads Involved in Daisy Chain."]
23123 pub mod DAISY {
23124 pub const offset: u32 = 0;
23125 pub const mask: u32 = 0x03 << offset;
23126 pub mod R {}
23127 pub mod W {}
23128 pub mod RW {
23129 #[doc = "Selecting Pad: GPIO_AD_B1_07 for Mode: ALT2"]
23130 pub const GPIO_AD_B1_07_ALT2: u32 = 0;
23131 #[doc = "Selecting Pad: GPIO_EMC_14 for Mode: ALT2"]
23132 pub const GPIO_EMC_14_ALT2: u32 = 0x01;
23133 #[doc = "Selecting Pad: GPIO_B0_09 for Mode: ALT3"]
23134 pub const GPIO_B0_09_ALT3: u32 = 0x02;
23135 }
23136 }
23137}
23138#[doc = "LPUART3_TX_SELECT_INPUT DAISY Register"]
23139pub mod LPUART3_TX_SELECT_INPUT {
23140 #[doc = "Selecting Pads Involved in Daisy Chain."]
23141 pub mod DAISY {
23142 pub const offset: u32 = 0;
23143 pub const mask: u32 = 0x03 << offset;
23144 pub mod R {}
23145 pub mod W {}
23146 pub mod RW {
23147 #[doc = "Selecting Pad: GPIO_AD_B1_06 for Mode: ALT2"]
23148 pub const GPIO_AD_B1_06_ALT2: u32 = 0;
23149 #[doc = "Selecting Pad: GPIO_EMC_13 for Mode: ALT2"]
23150 pub const GPIO_EMC_13_ALT2: u32 = 0x01;
23151 #[doc = "Selecting Pad: GPIO_B0_08 for Mode: ALT3"]
23152 pub const GPIO_B0_08_ALT3: u32 = 0x02;
23153 }
23154 }
23155}
23156#[doc = "LPUART4_RX_SELECT_INPUT DAISY Register"]
23157pub mod LPUART4_RX_SELECT_INPUT {
23158 #[doc = "Selecting Pads Involved in Daisy Chain."]
23159 pub mod DAISY {
23160 pub const offset: u32 = 0;
23161 pub const mask: u32 = 0x03 << offset;
23162 pub mod R {}
23163 pub mod W {}
23164 pub mod RW {
23165 #[doc = "Selecting Pad: GPIO_SD_B1_01 for Mode: ALT4"]
23166 pub const GPIO_SD_B1_01_ALT4: u32 = 0;
23167 #[doc = "Selecting Pad: GPIO_EMC_20 for Mode: ALT2"]
23168 pub const GPIO_EMC_20_ALT2: u32 = 0x01;
23169 #[doc = "Selecting Pad: GPIO_B1_01 for Mode: ALT2"]
23170 pub const GPIO_B1_01_ALT2: u32 = 0x02;
23171 }
23172 }
23173}
23174#[doc = "LPUART4_TX_SELECT_INPUT DAISY Register"]
23175pub mod LPUART4_TX_SELECT_INPUT {
23176 #[doc = "Selecting Pads Involved in Daisy Chain."]
23177 pub mod DAISY {
23178 pub const offset: u32 = 0;
23179 pub const mask: u32 = 0x03 << offset;
23180 pub mod R {}
23181 pub mod W {}
23182 pub mod RW {
23183 #[doc = "Selecting Pad: GPIO_SD_B1_00 for Mode: ALT4"]
23184 pub const GPIO_SD_B1_00_ALT4: u32 = 0;
23185 #[doc = "Selecting Pad: GPIO_EMC_19 for Mode: ALT2"]
23186 pub const GPIO_EMC_19_ALT2: u32 = 0x01;
23187 #[doc = "Selecting Pad: GPIO_B1_00 for Mode: ALT2"]
23188 pub const GPIO_B1_00_ALT2: u32 = 0x02;
23189 }
23190 }
23191}
23192#[doc = "LPUART5_RX_SELECT_INPUT DAISY Register"]
23193pub mod LPUART5_RX_SELECT_INPUT {
23194 #[doc = "Selecting Pads Involved in Daisy Chain."]
23195 pub mod DAISY {
23196 pub const offset: u32 = 0;
23197 pub const mask: u32 = 0x01 << offset;
23198 pub mod R {}
23199 pub mod W {}
23200 pub mod RW {
23201 #[doc = "Selecting Pad: GPIO_EMC_24 for Mode: ALT2"]
23202 pub const GPIO_EMC_24_ALT2: u32 = 0;
23203 #[doc = "Selecting Pad: GPIO_B1_13 for Mode: ALT1"]
23204 pub const GPIO_B1_13_ALT1: u32 = 0x01;
23205 }
23206 }
23207}
23208#[doc = "LPUART5_TX_SELECT_INPUT DAISY Register"]
23209pub mod LPUART5_TX_SELECT_INPUT {
23210 #[doc = "Selecting Pads Involved in Daisy Chain."]
23211 pub mod DAISY {
23212 pub const offset: u32 = 0;
23213 pub const mask: u32 = 0x01 << offset;
23214 pub mod R {}
23215 pub mod W {}
23216 pub mod RW {
23217 #[doc = "Selecting Pad: GPIO_EMC_23 for Mode: ALT2"]
23218 pub const GPIO_EMC_23_ALT2: u32 = 0;
23219 #[doc = "Selecting Pad: GPIO_B1_12 for Mode: ALT1"]
23220 pub const GPIO_B1_12_ALT1: u32 = 0x01;
23221 }
23222 }
23223}
23224#[doc = "LPUART6_RX_SELECT_INPUT DAISY Register"]
23225pub mod LPUART6_RX_SELECT_INPUT {
23226 #[doc = "Selecting Pads Involved in Daisy Chain."]
23227 pub mod DAISY {
23228 pub const offset: u32 = 0;
23229 pub const mask: u32 = 0x01 << offset;
23230 pub mod R {}
23231 pub mod W {}
23232 pub mod RW {
23233 #[doc = "Selecting Pad: GPIO_EMC_26 for Mode: ALT2"]
23234 pub const GPIO_EMC_26_ALT2: u32 = 0;
23235 #[doc = "Selecting Pad: GPIO_AD_B0_03 for Mode: ALT2"]
23236 pub const GPIO_AD_B0_03_ALT2: u32 = 0x01;
23237 }
23238 }
23239}
23240#[doc = "LPUART6_TX_SELECT_INPUT DAISY Register"]
23241pub mod LPUART6_TX_SELECT_INPUT {
23242 #[doc = "Selecting Pads Involved in Daisy Chain."]
23243 pub mod DAISY {
23244 pub const offset: u32 = 0;
23245 pub const mask: u32 = 0x01 << offset;
23246 pub mod R {}
23247 pub mod W {}
23248 pub mod RW {
23249 #[doc = "Selecting Pad: GPIO_EMC_25 for Mode: ALT2"]
23250 pub const GPIO_EMC_25_ALT2: u32 = 0;
23251 #[doc = "Selecting Pad: GPIO_AD_B0_02 for Mode: ALT2"]
23252 pub const GPIO_AD_B0_02_ALT2: u32 = 0x01;
23253 }
23254 }
23255}
23256#[doc = "LPUART7_RX_SELECT_INPUT DAISY Register"]
23257pub mod LPUART7_RX_SELECT_INPUT {
23258 #[doc = "Selecting Pads Involved in Daisy Chain."]
23259 pub mod DAISY {
23260 pub const offset: u32 = 0;
23261 pub const mask: u32 = 0x01 << offset;
23262 pub mod R {}
23263 pub mod W {}
23264 pub mod RW {
23265 #[doc = "Selecting Pad: GPIO_SD_B1_09 for Mode: ALT2"]
23266 pub const GPIO_SD_B1_09_ALT2: u32 = 0;
23267 #[doc = "Selecting Pad: GPIO_EMC_32 for Mode: ALT2"]
23268 pub const GPIO_EMC_32_ALT2: u32 = 0x01;
23269 }
23270 }
23271}
23272#[doc = "LPUART7_TX_SELECT_INPUT DAISY Register"]
23273pub mod LPUART7_TX_SELECT_INPUT {
23274 #[doc = "Selecting Pads Involved in Daisy Chain."]
23275 pub mod DAISY {
23276 pub const offset: u32 = 0;
23277 pub const mask: u32 = 0x01 << offset;
23278 pub mod R {}
23279 pub mod W {}
23280 pub mod RW {
23281 #[doc = "Selecting Pad: GPIO_SD_B1_08 for Mode: ALT2"]
23282 pub const GPIO_SD_B1_08_ALT2: u32 = 0;
23283 #[doc = "Selecting Pad:GPIO_EMC_31 for Mode: ALT2"]
23284 pub const GPIO_EMC_31_ALT2: u32 = 0x01;
23285 }
23286 }
23287}
23288#[doc = "LPUART8_RX_SELECT_INPUT DAISY Register"]
23289pub mod LPUART8_RX_SELECT_INPUT {
23290 #[doc = "Selecting Pads Involved in Daisy Chain."]
23291 pub mod DAISY {
23292 pub const offset: u32 = 0;
23293 pub const mask: u32 = 0x03 << offset;
23294 pub mod R {}
23295 pub mod W {}
23296 pub mod RW {
23297 #[doc = "Selecting Pad: GPIO_SD_B0_05 for Mode: ALT2"]
23298 pub const GPIO_SD_B0_05_ALT2: u32 = 0;
23299 #[doc = "Selecting Pad: GPIO_AD_B1_11 for Mode: ALT2"]
23300 pub const GPIO_AD_B1_11_ALT2: u32 = 0x01;
23301 #[doc = "Selecting Pad: GPIO_EMC_39 for Mode: ALT2"]
23302 pub const GPIO_EMC_39_ALT2: u32 = 0x02;
23303 }
23304 }
23305}
23306#[doc = "LPUART8_TX_SELECT_INPUT DAISY Register"]
23307pub mod LPUART8_TX_SELECT_INPUT {
23308 #[doc = "Selecting Pads Involved in Daisy Chain."]
23309 pub mod DAISY {
23310 pub const offset: u32 = 0;
23311 pub const mask: u32 = 0x03 << offset;
23312 pub mod R {}
23313 pub mod W {}
23314 pub mod RW {
23315 #[doc = "Selecting Pad: GPIO_SD_B0_04 for Mode: ALT2"]
23316 pub const GPIO_SD_B0_04_ALT2: u32 = 0;
23317 #[doc = "Selecting Pad: GPIO_AD_B1_10 for Mode: ALT2"]
23318 pub const GPIO_AD_B1_10_ALT2: u32 = 0x01;
23319 #[doc = "Selecting Pad: GPIO_EMC_38 for Mode: ALT2"]
23320 pub const GPIO_EMC_38_ALT2: u32 = 0x02;
23321 }
23322 }
23323}
23324#[doc = "NMI_GLUE_NMI_SELECT_INPUT DAISY Register"]
23325pub mod NMI_SELECT_INPUT {
23326 #[doc = "Selecting Pads Involved in Daisy Chain."]
23327 pub mod DAISY {
23328 pub const offset: u32 = 0;
23329 pub const mask: u32 = 0x01 << offset;
23330 pub mod R {}
23331 pub mod W {}
23332 pub mod RW {
23333 #[doc = "Selecting Pad: GPIO_AD_B0_12 for Mode: ALT7"]
23334 pub const GPIO_AD_B0_12_ALT7: u32 = 0;
23335 #[doc = "Selecting Pad: WAKEUP for Mode: ALT7"]
23336 pub const WAKEUP_ALT7: u32 = 0x01;
23337 }
23338 }
23339}
23340#[doc = "QTIMER2_TIMER0_SELECT_INPUT DAISY Register"]
23341pub mod QTIMER2_TIMER0_SELECT_INPUT {
23342 #[doc = "Selecting Pads Involved in Daisy Chain."]
23343 pub mod DAISY {
23344 pub const offset: u32 = 0;
23345 pub const mask: u32 = 0x01 << offset;
23346 pub mod R {}
23347 pub mod W {}
23348 pub mod RW {
23349 #[doc = "Selecting Pad: GPIO_EMC_19 for Mode: ALT4"]
23350 pub const GPIO_EMC_19_ALT4: u32 = 0;
23351 #[doc = "Selecting Pad: GPIO_B0_03 for Mode: ALT1"]
23352 pub const GPIO_B0_03_ALT1: u32 = 0x01;
23353 }
23354 }
23355}
23356#[doc = "QTIMER2_TIMER1_SELECT_INPUT DAISY Register"]
23357pub mod QTIMER2_TIMER1_SELECT_INPUT {
23358 #[doc = "Selecting Pads Involved in Daisy Chain."]
23359 pub mod DAISY {
23360 pub const offset: u32 = 0;
23361 pub const mask: u32 = 0x01 << offset;
23362 pub mod R {}
23363 pub mod W {}
23364 pub mod RW {
23365 #[doc = "Selecting Pad: GPIO_EMC_20 for Mode: ALT4"]
23366 pub const GPIO_EMC_20_ALT4: u32 = 0;
23367 #[doc = "Selecting Pad: GPIO_B0_04 for Mode: ALT1"]
23368 pub const GPIO_B0_04_ALT1: u32 = 0x01;
23369 }
23370 }
23371}
23372#[doc = "QTIMER2_TIMER2_SELECT_INPUT DAISY Register"]
23373pub mod QTIMER2_TIMER2_SELECT_INPUT {
23374 #[doc = "Selecting Pads Involved in Daisy Chain."]
23375 pub mod DAISY {
23376 pub const offset: u32 = 0;
23377 pub const mask: u32 = 0x01 << offset;
23378 pub mod R {}
23379 pub mod W {}
23380 pub mod RW {
23381 #[doc = "Selecting Pad: GPIO_EMC_21 for Mode: ALT4"]
23382 pub const GPIO_EMC_21_ALT4: u32 = 0;
23383 #[doc = "Selecting Pad: GPIO_B0_05 for Mode: ALT1"]
23384 pub const GPIO_B0_05_ALT1: u32 = 0x01;
23385 }
23386 }
23387}
23388#[doc = "QTIMER2_TIMER3_SELECT_INPUT DAISY Register"]
23389pub mod QTIMER2_TIMER3_SELECT_INPUT {
23390 #[doc = "Selecting Pads Involved in Daisy Chain."]
23391 pub mod DAISY {
23392 pub const offset: u32 = 0;
23393 pub const mask: u32 = 0x01 << offset;
23394 pub mod R {}
23395 pub mod W {}
23396 pub mod RW {
23397 #[doc = "Selecting Pad: GPIO_EMC_22 for Mode: ALT4"]
23398 pub const GPIO_EMC_22_ALT4: u32 = 0;
23399 #[doc = "Selecting Pad: GPIO_B1_09 for Mode: ALT1"]
23400 pub const GPIO_B1_09_ALT1: u32 = 0x01;
23401 }
23402 }
23403}
23404#[doc = "QTIMER3_TIMER0_SELECT_INPUT DAISY Register"]
23405pub mod QTIMER3_TIMER0_SELECT_INPUT {
23406 #[doc = "Selecting Pads Involved in Daisy Chain."]
23407 pub mod DAISY {
23408 pub const offset: u32 = 0;
23409 pub const mask: u32 = 0x03 << offset;
23410 pub mod R {}
23411 pub mod W {}
23412 pub mod RW {
23413 #[doc = "Selecting Pad: GPIO_EMC_15 for Mode: ALT4"]
23414 pub const GPIO_EMC_15_ALT4: u32 = 0;
23415 #[doc = "Selecting Pad: GPIO_AD_B1_00 for Mode: ALT1"]
23416 pub const GPIO_AD_B1_00_ALT1: u32 = 0x01;
23417 #[doc = "Selecting Pad: GPIO_B0_06 for Mode: ALT1"]
23418 pub const GPIO_B0_06_ALT1: u32 = 0x02;
23419 }
23420 }
23421}
23422#[doc = "QTIMER3_TIMER1_SELECT_INPUT DAISY Register"]
23423pub mod QTIMER3_TIMER1_SELECT_INPUT {
23424 #[doc = "Selecting Pads Involved in Daisy Chain."]
23425 pub mod DAISY {
23426 pub const offset: u32 = 0;
23427 pub const mask: u32 = 0x03 << offset;
23428 pub mod R {}
23429 pub mod W {}
23430 pub mod RW {
23431 #[doc = "Selecting Pad: GPIO_AD_B1_01 for Mode: ALT1"]
23432 pub const GPIO_AD_B1_01_ALT1: u32 = 0;
23433 #[doc = "Selecting Pad: GPIO_EMC_16 for Mode: ALT4"]
23434 pub const GPIO_EMC_16_ALT4: u32 = 0x01;
23435 #[doc = "Selecting Pad: GPIO_B0_07 for Mode: ALT1"]
23436 pub const GPIO_B0_07_ALT1: u32 = 0x02;
23437 }
23438 }
23439}
23440#[doc = "QTIMER3_TIMER2_SELECT_INPUT DAISY Register"]
23441pub mod QTIMER3_TIMER2_SELECT_INPUT {
23442 #[doc = "Selecting Pads Involved in Daisy Chain."]
23443 pub mod DAISY {
23444 pub const offset: u32 = 0;
23445 pub const mask: u32 = 0x03 << offset;
23446 pub mod R {}
23447 pub mod W {}
23448 pub mod RW {
23449 #[doc = "Selecting Pad: GPIO_EMC_17 for Mode: ALT4"]
23450 pub const GPIO_EMC_17_ALT4: u32 = 0;
23451 #[doc = "Selecting Pad: GPIO_AD_B1_02 for Mode: ALT1"]
23452 pub const GPIO_AD_B1_02_ALT1: u32 = 0x01;
23453 #[doc = "Selecting Pad: GPIO_B0_08 for Mode: ALT1"]
23454 pub const GPIO_B0_08_ALT1: u32 = 0x02;
23455 }
23456 }
23457}
23458#[doc = "QTIMER3_TIMER3_SELECT_INPUT DAISY Register"]
23459pub mod QTIMER3_TIMER3_SELECT_INPUT {
23460 #[doc = "Selecting Pads Involved in Daisy Chain."]
23461 pub mod DAISY {
23462 pub const offset: u32 = 0;
23463 pub const mask: u32 = 0x03 << offset;
23464 pub mod R {}
23465 pub mod W {}
23466 pub mod RW {
23467 #[doc = "Selecting Pad: GPIO_EMC_18 for Mode: ALT4"]
23468 pub const GPIO_EMC_18_ALT4: u32 = 0;
23469 #[doc = "Selecting Pad: GPIO_AD_B1_03 for Mode: ALT1"]
23470 pub const GPIO_AD_B1_03_ALT1: u32 = 0x01;
23471 #[doc = "Selecting Pad: GPIO_B1_10 for Mode: ALT1"]
23472 pub const GPIO_B1_10_ALT1: u32 = 0x02;
23473 }
23474 }
23475}
23476#[doc = "SAI1_MCLK2_SELECT_INPUT DAISY Register"]
23477pub mod SAI1_MCLK2_SELECT_INPUT {
23478 #[doc = "Selecting Pads Involved in Daisy Chain."]
23479 pub mod DAISY {
23480 pub const offset: u32 = 0;
23481 pub const mask: u32 = 0x03 << offset;
23482 pub mod R {}
23483 pub mod W {}
23484 pub mod RW {
23485 #[doc = "Selecting Pad: GPIO_SD_B1_03 for Mode: ALT3"]
23486 pub const GPIO_SD_B1_03_ALT3: u32 = 0;
23487 #[doc = "Selecting Pad: GPIO_AD_B1_09 for Mode: ALT3"]
23488 pub const GPIO_AD_B1_09_ALT3: u32 = 0x01;
23489 #[doc = "Selecting Pad: GPIO_B0_13 for Mode: ALT3"]
23490 pub const GPIO_B0_13_ALT3: u32 = 0x02;
23491 }
23492 }
23493}
23494#[doc = "SAI1_RX_BCLK_SELECT_INPUT DAISY Register"]
23495pub mod SAI1_RX_BCLK_SELECT_INPUT {
23496 #[doc = "Selecting Pads Involved in Daisy Chain."]
23497 pub mod DAISY {
23498 pub const offset: u32 = 0;
23499 pub const mask: u32 = 0x03 << offset;
23500 pub mod R {}
23501 pub mod W {}
23502 pub mod RW {
23503 #[doc = "Selecting Pad: GPIO_SD_B1_05 for Mode: ALT3"]
23504 pub const GPIO_SD_B1_05_ALT3: u32 = 0;
23505 #[doc = "Selecting Pad: GPIO_AD_B1_11 for Mode: ALT3"]
23506 pub const GPIO_AD_B1_11_ALT3: u32 = 0x01;
23507 #[doc = "Selecting Pad: GPIO_B0_15 for Mode: ALT3"]
23508 pub const GPIO_B0_15_ALT3: u32 = 0x02;
23509 }
23510 }
23511}
23512#[doc = "SAI1_RX_DATA0_SELECT_INPUT DAISY Register"]
23513pub mod SAI1_RX_DATA0_SELECT_INPUT {
23514 #[doc = "Selecting Pads Involved in Daisy Chain."]
23515 pub mod DAISY {
23516 pub const offset: u32 = 0;
23517 pub const mask: u32 = 0x03 << offset;
23518 pub mod R {}
23519 pub mod W {}
23520 pub mod RW {
23521 #[doc = "Selecting Pad: GPIO_SD_B1_06 for Mode: ALT3"]
23522 pub const GPIO_SD_B1_06_ALT3: u32 = 0;
23523 #[doc = "Selecting Pad: GPIO_AD_B1_12 for Mode: ALT3"]
23524 pub const GPIO_AD_B1_12_ALT3: u32 = 0x01;
23525 #[doc = "Selecting Pad: GPIO_B1_00 for Mode: ALT3"]
23526 pub const GPIO_B1_00_ALT3: u32 = 0x02;
23527 }
23528 }
23529}
23530#[doc = "SAI1_RX_DATA1_SELECT_INPUT DAISY Register"]
23531pub mod SAI1_RX_DATA1_SELECT_INPUT {
23532 #[doc = "Selecting Pads Involved in Daisy Chain."]
23533 pub mod DAISY {
23534 pub const offset: u32 = 0;
23535 pub const mask: u32 = 0x01 << offset;
23536 pub mod R {}
23537 pub mod W {}
23538 pub mod RW {
23539 #[doc = "Selecting Pad: GPIO_SD_B1_00 for Mode: ALT3"]
23540 pub const GPIO_SD_B1_00_ALT3: u32 = 0;
23541 #[doc = "Selecting Pad: GPIO_B0_10 for Mode: ALT3"]
23542 pub const GPIO_B0_10_ALT3: u32 = 0x01;
23543 }
23544 }
23545}
23546#[doc = "SAI1_RX_DATA2_SELECT_INPUT DAISY Register"]
23547pub mod SAI1_RX_DATA2_SELECT_INPUT {
23548 #[doc = "Selecting Pads Involved in Daisy Chain."]
23549 pub mod DAISY {
23550 pub const offset: u32 = 0;
23551 pub const mask: u32 = 0x01 << offset;
23552 pub mod R {}
23553 pub mod W {}
23554 pub mod RW {
23555 #[doc = "Selecting Pad: GPIO_SD_B1_01 for Mode: ALT3"]
23556 pub const GPIO_SD_B1_01_ALT3: u32 = 0;
23557 #[doc = "Selecting Pad: GPIO_B0_11 for Mode: ALT3"]
23558 pub const GPIO_B0_11_ALT3: u32 = 0x01;
23559 }
23560 }
23561}
23562#[doc = "SAI1_RX_DATA3_SELECT_INPUT DAISY Register"]
23563pub mod SAI1_RX_DATA3_SELECT_INPUT {
23564 #[doc = "Selecting Pads Involved in Daisy Chain."]
23565 pub mod DAISY {
23566 pub const offset: u32 = 0;
23567 pub const mask: u32 = 0x01 << offset;
23568 pub mod R {}
23569 pub mod W {}
23570 pub mod RW {
23571 #[doc = "Selecting Pad: GPIO_SD_B1_02 for Mode: ALT3"]
23572 pub const GPIO_SD_B1_02_ALT3: u32 = 0;
23573 #[doc = "Selecting Pad: GPIO_B0_12 for Mode: ALT3"]
23574 pub const GPIO_B0_12_ALT3: u32 = 0x01;
23575 }
23576 }
23577}
23578#[doc = "SAI1_RX_SYNC_SELECT_INPUT DAISY Register"]
23579pub mod SAI1_RX_SYNC_SELECT_INPUT {
23580 #[doc = "Selecting Pads Involved in Daisy Chain."]
23581 pub mod DAISY {
23582 pub const offset: u32 = 0;
23583 pub const mask: u32 = 0x03 << offset;
23584 pub mod R {}
23585 pub mod W {}
23586 pub mod RW {
23587 #[doc = "Selecting Pad: GPIO_SD_B1_04 for Mode: ALT3"]
23588 pub const GPIO_SD_B1_04_ALT3: u32 = 0;
23589 #[doc = "Selecting Pad: GPIO_AD_B1_10 for Mode: ALT3"]
23590 pub const GPIO_AD_B1_10_ALT3: u32 = 0x01;
23591 #[doc = "Selecting Pad: GPIO_B0_14 for Mode: ALT3"]
23592 pub const GPIO_B0_14_ALT3: u32 = 0x02;
23593 }
23594 }
23595}
23596#[doc = "SAI1_TX_BCLK_SELECT_INPUT DAISY Register"]
23597pub mod SAI1_TX_BCLK_SELECT_INPUT {
23598 #[doc = "Selecting Pads Involved in Daisy Chain."]
23599 pub mod DAISY {
23600 pub const offset: u32 = 0;
23601 pub const mask: u32 = 0x03 << offset;
23602 pub mod R {}
23603 pub mod W {}
23604 pub mod RW {
23605 #[doc = "Selecting Pad: GPIO_SD_B1_08 for Mode: ALT3"]
23606 pub const GPIO_SD_B1_08_ALT3: u32 = 0;
23607 #[doc = "Selecting Pad: GPIO_AD_B1_14 for Mode: ALT3"]
23608 pub const GPIO_AD_B1_14_ALT3: u32 = 0x01;
23609 #[doc = "Selecting Pad: GPIO_B1_02 for Mode: ALT3"]
23610 pub const GPIO_B1_02_ALT3: u32 = 0x02;
23611 }
23612 }
23613}
23614#[doc = "SAI1_TX_SYNC_SELECT_INPUT DAISY Register"]
23615pub mod SAI1_TX_SYNC_SELECT_INPUT {
23616 #[doc = "Selecting Pads Involved in Daisy Chain."]
23617 pub mod DAISY {
23618 pub const offset: u32 = 0;
23619 pub const mask: u32 = 0x03 << offset;
23620 pub mod R {}
23621 pub mod W {}
23622 pub mod RW {
23623 #[doc = "Selecting Pad: GPIO_SD_B1_09 for Mode: ALT3"]
23624 pub const GPIO_SD_B1_09_ALT3: u32 = 0;
23625 #[doc = "Selecting Pad: GPIO_AD_B1_15 for Mode: ALT3"]
23626 pub const GPIO_AD_B1_15_ALT3: u32 = 0x01;
23627 #[doc = "Selecting Pad: GPIO_B1_03 for Mode: ALT3"]
23628 pub const GPIO_B1_03_ALT3: u32 = 0x02;
23629 }
23630 }
23631}
23632#[doc = "SAI2_MCLK2_SELECT_INPUT DAISY Register"]
23633pub mod SAI2_MCLK2_SELECT_INPUT {
23634 #[doc = "Selecting Pads Involved in Daisy Chain."]
23635 pub mod DAISY {
23636 pub const offset: u32 = 0;
23637 pub const mask: u32 = 0x01 << offset;
23638 pub mod R {}
23639 pub mod W {}
23640 pub mod RW {
23641 #[doc = "Selecting Pad: GPIO_EMC_07 for Mode: ALT2"]
23642 pub const GPIO_EMC_07_ALT2: u32 = 0;
23643 #[doc = "Selecting Pad: GPIO_AD_B0_10 for Mode: ALT3"]
23644 pub const GPIO_AD_B0_10_ALT3: u32 = 0x01;
23645 }
23646 }
23647}
23648#[doc = "SAI2_RX_BCLK_SELECT_INPUT DAISY Register"]
23649pub mod SAI2_RX_BCLK_SELECT_INPUT {
23650 #[doc = "Selecting Pads Involved in Daisy Chain."]
23651 pub mod DAISY {
23652 pub const offset: u32 = 0;
23653 pub const mask: u32 = 0x01 << offset;
23654 pub mod R {}
23655 pub mod W {}
23656 pub mod RW {
23657 #[doc = "Selecting Pad: GPIO_EMC_10 for Mode: ALT2"]
23658 pub const GPIO_EMC_10_ALT2: u32 = 0;
23659 #[doc = "Selecting Pad: GPIO_AD_B0_06 for Mode: ALT3"]
23660 pub const GPIO_AD_B0_06_ALT3: u32 = 0x01;
23661 }
23662 }
23663}
23664#[doc = "SAI2_RX_DATA0_SELECT_INPUT DAISY Register"]
23665pub mod SAI2_RX_DATA0_SELECT_INPUT {
23666 #[doc = "Selecting Pads Involved in Daisy Chain."]
23667 pub mod DAISY {
23668 pub const offset: u32 = 0;
23669 pub const mask: u32 = 0x01 << offset;
23670 pub mod R {}
23671 pub mod W {}
23672 pub mod RW {
23673 #[doc = "Selecting Pad: GPIO_EMC_08 for Mode: ALT2"]
23674 pub const GPIO_EMC_08_ALT2: u32 = 0;
23675 #[doc = "Selecting Pad: GPIO_AD_B0_08 for Mode: ALT3"]
23676 pub const GPIO_AD_B0_08_ALT3: u32 = 0x01;
23677 }
23678 }
23679}
23680#[doc = "SAI2_RX_SYNC_SELECT_INPUT DAISY Register"]
23681pub mod SAI2_RX_SYNC_SELECT_INPUT {
23682 #[doc = "Selecting Pads Involved in Daisy Chain."]
23683 pub mod DAISY {
23684 pub const offset: u32 = 0;
23685 pub const mask: u32 = 0x01 << offset;
23686 pub mod R {}
23687 pub mod W {}
23688 pub mod RW {
23689 #[doc = "Selecting Pad: GPIO_EMC_09 for Mode: ALT2"]
23690 pub const GPIO_EMC_09_ALT2: u32 = 0;
23691 #[doc = "Selecting Pad: GPIO_AD_B0_07 for Mode: ALT3"]
23692 pub const GPIO_AD_B0_07_ALT3: u32 = 0x01;
23693 }
23694 }
23695}
23696#[doc = "SAI2_TX_BCLK_SELECT_INPUT DAISY Register"]
23697pub mod SAI2_TX_BCLK_SELECT_INPUT {
23698 #[doc = "Selecting Pads Involved in Daisy Chain."]
23699 pub mod DAISY {
23700 pub const offset: u32 = 0;
23701 pub const mask: u32 = 0x01 << offset;
23702 pub mod R {}
23703 pub mod W {}
23704 pub mod RW {
23705 #[doc = "Selecting Pad: GPIO_EMC_06 for Mode: ALT2"]
23706 pub const GPIO_EMC_06_ALT2: u32 = 0;
23707 #[doc = "Selecting Pad: GPIO_AD_B0_05 for Mode: ALT3"]
23708 pub const GPIO_AD_B0_05_ALT3: u32 = 0x01;
23709 }
23710 }
23711}
23712#[doc = "SAI2_TX_SYNC_SELECT_INPUT DAISY Register"]
23713pub mod SAI2_TX_SYNC_SELECT_INPUT {
23714 #[doc = "Selecting Pads Involved in Daisy Chain."]
23715 pub mod DAISY {
23716 pub const offset: u32 = 0;
23717 pub const mask: u32 = 0x01 << offset;
23718 pub mod R {}
23719 pub mod W {}
23720 pub mod RW {
23721 #[doc = "Selecting Pad: GPIO_EMC_05 for Mode: ALT2"]
23722 pub const GPIO_EMC_05_ALT2: u32 = 0;
23723 #[doc = "Selecting Pad: GPIO_AD_B0_04 for Mode: ALT3"]
23724 pub const GPIO_AD_B0_04_ALT3: u32 = 0x01;
23725 }
23726 }
23727}
23728#[doc = "SPDIF_IN_SELECT_INPUT DAISY Register"]
23729pub mod SPDIF_IN_SELECT_INPUT {
23730 #[doc = "Selecting Pads Involved in Daisy Chain."]
23731 pub mod DAISY {
23732 pub const offset: u32 = 0;
23733 pub const mask: u32 = 0x01 << offset;
23734 pub mod R {}
23735 pub mod W {}
23736 pub mod RW {
23737 #[doc = "Selecting Pad: GPIO_AD_B1_03 for Mode: ALT3"]
23738 pub const GPIO_AD_B1_03_ALT3: u32 = 0;
23739 #[doc = "Selecting Pad: GPIO_EMC_16 for Mode: ALT3"]
23740 pub const GPIO_EMC_16_ALT3: u32 = 0x01;
23741 }
23742 }
23743}
23744#[doc = "USB_OTG2_OC_SELECT_INPUT DAISY Register"]
23745pub mod USB_OTG2_OC_SELECT_INPUT {
23746 #[doc = "Selecting Pads Involved in Daisy Chain."]
23747 pub mod DAISY {
23748 pub const offset: u32 = 0;
23749 pub const mask: u32 = 0x01 << offset;
23750 pub mod R {}
23751 pub mod W {}
23752 pub mod RW {
23753 #[doc = "Selecting Pad: GPIO_AD_B0_14 for Mode: ALT0"]
23754 pub const GPIO_AD_B0_14_ALT0: u32 = 0;
23755 #[doc = "Selecting Pad: GPIO_EMC_40 for Mode: ALT3"]
23756 pub const GPIO_EMC_40_ALT3: u32 = 0x01;
23757 }
23758 }
23759}
23760#[doc = "USB_OTG1_OC_SELECT_INPUT DAISY Register"]
23761pub mod USB_OTG1_OC_SELECT_INPUT {
23762 #[doc = "Selecting Pads Involved in Daisy Chain."]
23763 pub mod DAISY {
23764 pub const offset: u32 = 0;
23765 pub const mask: u32 = 0x01 << offset;
23766 pub mod R {}
23767 pub mod W {}
23768 pub mod RW {
23769 #[doc = "Selecting Pad: GPIO_AD_B0_03 for Mode: ALT3"]
23770 pub const GPIO_AD_B0_03_ALT3: u32 = 0;
23771 #[doc = "Selecting Pad: GPIO_AD_B1_03 for Mode: ALT0"]
23772 pub const GPIO_AD_B1_03_ALT0: u32 = 0x01;
23773 }
23774 }
23775}
23776#[doc = "USDHC1_CD_B_SELECT_INPUT DAISY Register"]
23777pub mod USDHC1_CD_B_SELECT_INPUT {
23778 #[doc = "Selecting Pads Involved in Daisy Chain."]
23779 pub mod DAISY {
23780 pub const offset: u32 = 0;
23781 pub const mask: u32 = 0x03 << offset;
23782 pub mod R {}
23783 pub mod W {}
23784 pub mod RW {
23785 #[doc = "Selecting Pad: GPIO_EMC_35 for Mode: ALT6"]
23786 pub const GPIO_EMC_35_ALT6: u32 = 0;
23787 #[doc = "Selecting Pad: GPIO_AD_B1_02 for Mode: ALT6"]
23788 pub const GPIO_AD_B1_02_ALT6: u32 = 0x01;
23789 #[doc = "Selecting Pad: GPIO_B1_12 for Mode: ALT6"]
23790 pub const GPIO_B1_12_ALT6: u32 = 0x02;
23791 }
23792 }
23793}
23794#[doc = "USDHC1_WP_SELECT_INPUT DAISY Register"]
23795pub mod USDHC1_WP_SELECT_INPUT {
23796 #[doc = "Selecting Pads Involved in Daisy Chain."]
23797 pub mod DAISY {
23798 pub const offset: u32 = 0;
23799 pub const mask: u32 = 0x03 << offset;
23800 pub mod R {}
23801 pub mod W {}
23802 pub mod RW {
23803 #[doc = "Selecting Pad: GPIO_EMC_12 for Mode: ALT3"]
23804 pub const GPIO_EMC_12_ALT3: u32 = 0;
23805 #[doc = "Selecting Pad: GPIO_EMC_36for Mode: ALT6"]
23806 pub const GPIO_EMC_36_ALT6: u32 = 0x01;
23807 #[doc = "Selecting Pad:GPIO_AD_B1_00 for Mode: ALT6"]
23808 pub const GPIO_AD_B1_00_ALT6: u32 = 0x02;
23809 #[doc = "Selecting Pad: GPIO_B1_13 for Mode: ALT6"]
23810 pub const GPIO_B1_13_ALT6: u32 = 0x03;
23811 }
23812 }
23813}
23814#[doc = "USDHC2_CLK_SELECT_INPUT DAISY Register"]
23815pub mod USDHC2_CLK_SELECT_INPUT {
23816 #[doc = "Selecting Pads Involved in Daisy Chain."]
23817 pub mod DAISY {
23818 pub const offset: u32 = 0;
23819 pub const mask: u32 = 0x01 << offset;
23820 pub mod R {}
23821 pub mod W {}
23822 pub mod RW {
23823 #[doc = "Selecting Pad: GPIO_SD_B1_04 for Mode: ALT0"]
23824 pub const GPIO_SD_B1_04_ALT0: u32 = 0;
23825 #[doc = "Selecting Pad: GPIO_AD_B1_09 for Mode: ALT6"]
23826 pub const GPIO_AD_B1_09_ALT6: u32 = 0x01;
23827 }
23828 }
23829}
23830#[doc = "USDHC2_CD_B_SELECT_INPUT DAISY Register"]
23831pub mod USDHC2_CD_B_SELECT_INPUT {
23832 #[doc = "Selecting Pads Involved in Daisy Chain."]
23833 pub mod DAISY {
23834 pub const offset: u32 = 0;
23835 pub const mask: u32 = 0x01 << offset;
23836 pub mod R {}
23837 pub mod W {}
23838 pub mod RW {
23839 #[doc = "Selecting Pad:GPIO_AD_B1_03 for Mode: ALT6"]
23840 pub const GPIO_AD_B1_03_ALT6: u32 = 0;
23841 #[doc = "Selecting Pad: GPIO_EMC_39 for Mode: ALT6"]
23842 pub const GPIO_EMC_39_ALT6: u32 = 0x01;
23843 }
23844 }
23845}
23846#[doc = "USDHC2_CMD_SELECT_INPUT DAISY Register"]
23847pub mod USDHC2_CMD_SELECT_INPUT {
23848 #[doc = "Selecting Pads Involved in Daisy Chain."]
23849 pub mod DAISY {
23850 pub const offset: u32 = 0;
23851 pub const mask: u32 = 0x01 << offset;
23852 pub mod R {}
23853 pub mod W {}
23854 pub mod RW {
23855 #[doc = "Selecting Pad: GPIO_SD_B1_05 for Mode: ALT0"]
23856 pub const GPIO_SD_B1_05_ALT0: u32 = 0;
23857 #[doc = "Selecting Pad: GPIO_AD_B1_08 for Mode: ALT6"]
23858 pub const GPIO_AD_B1_08_ALT6: u32 = 0x01;
23859 }
23860 }
23861}
23862#[doc = "USDHC2_DATA0_SELECT_INPUT DAISY Register"]
23863pub mod USDHC2_DATA0_SELECT_INPUT {
23864 #[doc = "Selecting Pads Involved in Daisy Chain."]
23865 pub mod DAISY {
23866 pub const offset: u32 = 0;
23867 pub const mask: u32 = 0x01 << offset;
23868 pub mod R {}
23869 pub mod W {}
23870 pub mod RW {
23871 #[doc = "Selecting Pad: GPIO_SD_B1_03 for Mode: ALT0"]
23872 pub const GPIO_SD_B1_03_ALT0: u32 = 0;
23873 #[doc = "Selecting Pad:GPIO_AD_B1_04 for Mode: ALT6"]
23874 pub const GPIO_AD_B1_04_ALT6: u32 = 0x01;
23875 }
23876 }
23877}
23878#[doc = "USDHC2_DATA1_SELECT_INPUT DAISY Register"]
23879pub mod USDHC2_DATA1_SELECT_INPUT {
23880 #[doc = "Selecting Pads Involved in Daisy Chain."]
23881 pub mod DAISY {
23882 pub const offset: u32 = 0;
23883 pub const mask: u32 = 0x01 << offset;
23884 pub mod R {}
23885 pub mod W {}
23886 pub mod RW {
23887 #[doc = "Selecting Pad: GPIO_SD_B1_02 for Mode: ALT0"]
23888 pub const GPIO_SD_B1_02_ALT0: u32 = 0;
23889 #[doc = "Selecting Pad: GPIO_AD_B1_05 for Mode: ALT6"]
23890 pub const GPIO_AD_B1_05_ALT6: u32 = 0x01;
23891 }
23892 }
23893}
23894#[doc = "USDHC2_DATA2_SELECT_INPUT DAISY Register"]
23895pub mod USDHC2_DATA2_SELECT_INPUT {
23896 #[doc = "Selecting Pads Involved in Daisy Chain."]
23897 pub mod DAISY {
23898 pub const offset: u32 = 0;
23899 pub const mask: u32 = 0x01 << offset;
23900 pub mod R {}
23901 pub mod W {}
23902 pub mod RW {
23903 #[doc = "Selecting Pad: GPIO_SD_B1_01 for Mode: ALT0"]
23904 pub const GPIO_SD_B1_01_ALT0: u32 = 0;
23905 #[doc = "Selecting Pad: GPIO_AD_B1_06 for Mode: ALT6"]
23906 pub const GPIO_AD_B1_06_ALT6: u32 = 0x01;
23907 }
23908 }
23909}
23910#[doc = "USDHC2_DATA3_SELECT_INPUT DAISY Register"]
23911pub mod USDHC2_DATA3_SELECT_INPUT {
23912 #[doc = "Selecting Pads Involved in Daisy Chain."]
23913 pub mod DAISY {
23914 pub const offset: u32 = 0;
23915 pub const mask: u32 = 0x01 << offset;
23916 pub mod R {}
23917 pub mod W {}
23918 pub mod RW {
23919 #[doc = "Selecting Pad: GPIO_SD_B1_00 for Mode: ALT0"]
23920 pub const GPIO_SD_B1_00_ALT0: u32 = 0;
23921 #[doc = "Selecting Pad: GPIO_AD_B1_07 for Mode: ALT6"]
23922 pub const GPIO_AD_B1_07_ALT6: u32 = 0x01;
23923 }
23924 }
23925}
23926#[doc = "USDHC2_DATA4_SELECT_INPUT DAISY Register"]
23927pub mod USDHC2_DATA4_SELECT_INPUT {
23928 #[doc = "Selecting Pads Involved in Daisy Chain."]
23929 pub mod DAISY {
23930 pub const offset: u32 = 0;
23931 pub const mask: u32 = 0x01 << offset;
23932 pub mod R {}
23933 pub mod W {}
23934 pub mod RW {
23935 #[doc = "Selecting Pad: GPIO_SD_B1_08 for Mode: ALT0"]
23936 pub const GPIO_SD_B1_08_ALT0: u32 = 0;
23937 #[doc = "Selecting Pad: GPIO_AD_B1_12 for Mode: ALT6"]
23938 pub const GPIO_AD_B1_12_ALT6: u32 = 0x01;
23939 }
23940 }
23941}
23942#[doc = "USDHC2_DATA5_SELECT_INPUT DAISY Register"]
23943pub mod USDHC2_DATA5_SELECT_INPUT {
23944 #[doc = "Selecting Pads Involved in Daisy Chain."]
23945 pub mod DAISY {
23946 pub const offset: u32 = 0;
23947 pub const mask: u32 = 0x01 << offset;
23948 pub mod R {}
23949 pub mod W {}
23950 pub mod RW {
23951 #[doc = "Selecting Pad: GPIO_SD_B1_09 for Mode: ALT0"]
23952 pub const GPIO_SD_B1_09_ALT0: u32 = 0;
23953 #[doc = "Selecting Pad: GPIO_AD_B1_13 for Mode: ALT6"]
23954 pub const GPIO_AD_B1_13_ALT6: u32 = 0x01;
23955 }
23956 }
23957}
23958#[doc = "USDHC2_DATA6_SELECT_INPUT DAISY Register"]
23959pub mod USDHC2_DATA6_SELECT_INPUT {
23960 #[doc = "Selecting Pads Involved in Daisy Chain."]
23961 pub mod DAISY {
23962 pub const offset: u32 = 0;
23963 pub const mask: u32 = 0x01 << offset;
23964 pub mod R {}
23965 pub mod W {}
23966 pub mod RW {
23967 #[doc = "Selecting Pad: GPIO_SD_B1_10 for Mode: ALT0"]
23968 pub const GPIO_SD_B1_10_ALT0: u32 = 0;
23969 #[doc = "Selecting Pad: GPIO_AD_B1_14 for Mode: ALT6"]
23970 pub const GPIO_AD_B1_14_ALT6: u32 = 0x01;
23971 }
23972 }
23973}
23974#[doc = "USDHC2_DATA7_SELECT_INPUT DAISY Register"]
23975pub mod USDHC2_DATA7_SELECT_INPUT {
23976 #[doc = "Selecting Pads Involved in Daisy Chain."]
23977 pub mod DAISY {
23978 pub const offset: u32 = 0;
23979 pub const mask: u32 = 0x01 << offset;
23980 pub mod R {}
23981 pub mod W {}
23982 pub mod RW {
23983 #[doc = "Selecting Pad: GPIO_SD_B1_11 for Mode: ALT0"]
23984 pub const GPIO_SD_B1_11_ALT0: u32 = 0;
23985 #[doc = "Selecting Pad: GPIO_AD_B1_15 for Mode: ALT6"]
23986 pub const GPIO_AD_B1_15_ALT6: u32 = 0x01;
23987 }
23988 }
23989}
23990#[doc = "USDHC2_WP_SELECT_INPUT DAISY Register"]
23991pub mod USDHC2_WP_SELECT_INPUT {
23992 #[doc = "Selecting Pads Involved in Daisy Chain."]
23993 pub mod DAISY {
23994 pub const offset: u32 = 0;
23995 pub const mask: u32 = 0x01 << offset;
23996 pub mod R {}
23997 pub mod W {}
23998 pub mod RW {
23999 #[doc = "Selecting Pad: GPIO_EMC_37 for Mode: ALT6"]
24000 pub const GPIO_EMC_37_ALT6: u32 = 0;
24001 #[doc = "Selecting Pad: GPIO_AD_B1_10 for Mode: ALT6"]
24002 pub const GPIO_AD_B1_10_ALT6: u32 = 0x01;
24003 }
24004 }
24005}
24006#[doc = "XBAR1_IN02_SELECT_INPUT DAISY Register"]
24007pub mod XBAR1_IN02_SELECT_INPUT {
24008 #[doc = "Selecting Pads Involved in Daisy Chain."]
24009 pub mod DAISY {
24010 pub const offset: u32 = 0;
24011 pub const mask: u32 = 0x01 << offset;
24012 pub mod R {}
24013 pub mod W {}
24014 pub mod RW {
24015 #[doc = "Selecting Pad: GPIO_EMC_00 for Mode: ALT3"]
24016 pub const GPIO_EMC_00_ALT3: u32 = 0;
24017 #[doc = "Selecting Pad: GPIO_B1_14 for Mode: ALT3"]
24018 pub const GPIO_B1_14_ALT3: u32 = 0x01;
24019 }
24020 }
24021}
24022#[doc = "XBAR1_IN03_SELECT_INPUT DAISY Register"]
24023pub mod XBAR1_IN03_SELECT_INPUT {
24024 #[doc = "Selecting Pads Involved in Daisy Chain."]
24025 pub mod DAISY {
24026 pub const offset: u32 = 0;
24027 pub const mask: u32 = 0x01 << offset;
24028 pub mod R {}
24029 pub mod W {}
24030 pub mod RW {
24031 #[doc = "Selecting Pad: GPIO_EMC_01 for Mode: ALT3"]
24032 pub const GPIO_EMC_01_ALT3: u32 = 0;
24033 #[doc = "Selecting Pad: GPIO_B1_15 for Mode: ALT3"]
24034 pub const GPIO_B1_15_ALT3: u32 = 0x01;
24035 }
24036 }
24037}
24038#[doc = "XBAR1_IN04_SELECT_INPUT DAISY Register"]
24039pub mod XBAR1_IN04_SELECT_INPUT {
24040 #[doc = "Selecting Pads Involved in Daisy Chain."]
24041 pub mod DAISY {
24042 pub const offset: u32 = 0;
24043 pub const mask: u32 = 0x01 << offset;
24044 pub mod R {}
24045 pub mod W {}
24046 pub mod RW {
24047 #[doc = "Selecting Pad: GPIO_EMC_02 for Mode: ALT3"]
24048 pub const GPIO_EMC_02_ALT3: u32 = 0;
24049 #[doc = "Selecting Pad: GPIO_SD_B0_00 for Mode: ALT3"]
24050 pub const GPIO_SD_B0_00_ALT3: u32 = 0x01;
24051 }
24052 }
24053}
24054#[doc = "XBAR1_IN05_SELECT_INPUT DAISY Register"]
24055pub mod XBAR1_IN05_SELECT_INPUT {
24056 #[doc = "Selecting Pads Involved in Daisy Chain."]
24057 pub mod DAISY {
24058 pub const offset: u32 = 0;
24059 pub const mask: u32 = 0x01 << offset;
24060 pub mod R {}
24061 pub mod W {}
24062 pub mod RW {
24063 #[doc = "Selecting Pad: GPIO_EMC_03 for Mode: ALT3"]
24064 pub const GPIO_EMC_03_ALT3: u32 = 0;
24065 #[doc = "Selecting Pad: GPIO_SD_B0_01 for Mode: ALT3"]
24066 pub const GPIO_SD_B0_01_ALT3: u32 = 0x01;
24067 }
24068 }
24069}
24070#[doc = "XBAR1_IN06_SELECT_INPUT DAISY Register"]
24071pub mod XBAR1_IN06_SELECT_INPUT {
24072 #[doc = "Selecting Pads Involved in Daisy Chain."]
24073 pub mod DAISY {
24074 pub const offset: u32 = 0;
24075 pub const mask: u32 = 0x01 << offset;
24076 pub mod R {}
24077 pub mod W {}
24078 pub mod RW {
24079 #[doc = "Selecting Pad: GPIO_EMC_04 for Mode: ALT3"]
24080 pub const GPIO_EMC_04_ALT3: u32 = 0;
24081 #[doc = "Selecting Pad: GPIO_SD_B0_02 for Mode: ALT3"]
24082 pub const GPIO_SD_B0_02_ALT3: u32 = 0x01;
24083 }
24084 }
24085}
24086#[doc = "XBAR1_IN07_SELECT_INPUT DAISY Register"]
24087pub mod XBAR1_IN07_SELECT_INPUT {
24088 #[doc = "Selecting Pads Involved in Daisy Chain."]
24089 pub mod DAISY {
24090 pub const offset: u32 = 0;
24091 pub const mask: u32 = 0x01 << offset;
24092 pub mod R {}
24093 pub mod W {}
24094 pub mod RW {
24095 #[doc = "Selecting Pad: GPIO_EMC_05 for Mode: ALT3"]
24096 pub const GPIO_EMC_05_ALT3: u32 = 0;
24097 #[doc = "Selecting Pad: GPIO_SD_B0_03 for Mode: ALT3"]
24098 pub const GPIO_SD_B0_03_ALT3: u32 = 0x01;
24099 }
24100 }
24101}
24102#[doc = "XBAR1_IN08_SELECT_INPUT DAISY Register"]
24103pub mod XBAR1_IN08_SELECT_INPUT {
24104 #[doc = "Selecting Pads Involved in Daisy Chain."]
24105 pub mod DAISY {
24106 pub const offset: u32 = 0;
24107 pub const mask: u32 = 0x01 << offset;
24108 pub mod R {}
24109 pub mod W {}
24110 pub mod RW {
24111 #[doc = "Selecting Pad: GPIO_EMC_06 for Mode: ALT3"]
24112 pub const GPIO_EMC_06_ALT3: u32 = 0;
24113 #[doc = "Selecting Pad: GPIO_SD_B0_04 for Mode: ALT3"]
24114 pub const GPIO_SD_B0_04_ALT3: u32 = 0x01;
24115 }
24116 }
24117}
24118#[doc = "XBAR1_IN09_SELECT_INPUT DAISY Register"]
24119pub mod XBAR1_IN09_SELECT_INPUT {
24120 #[doc = "Selecting Pads Involved in Daisy Chain."]
24121 pub mod DAISY {
24122 pub const offset: u32 = 0;
24123 pub const mask: u32 = 0x01 << offset;
24124 pub mod R {}
24125 pub mod W {}
24126 pub mod RW {
24127 #[doc = "Selecting Pad: GPIO_EMC_07 for Mode: ALT3"]
24128 pub const GPIO_EMC_07_ALT3: u32 = 0;
24129 #[doc = "Selecting Pad: GPIO_SD_B0_05 for Mode: ALT3"]
24130 pub const GPIO_SD_B0_05_ALT3: u32 = 0x01;
24131 }
24132 }
24133}
24134#[doc = "XBAR1_IN17_SELECT_INPUT DAISY Register"]
24135pub mod XBAR1_IN17_SELECT_INPUT {
24136 #[doc = "Selecting Pads Involved in Daisy Chain."]
24137 pub mod DAISY {
24138 pub const offset: u32 = 0;
24139 pub const mask: u32 = 0x03 << offset;
24140 pub mod R {}
24141 pub mod W {}
24142 pub mod RW {
24143 #[doc = "Selecting Pad: GPIO_EMC_08 for Mode: ALT3"]
24144 pub const GPIO_EMC_08_ALT3: u32 = 0;
24145 #[doc = "Selecting Pad: GPIO_AD_B0_03 for Mode: ALT1"]
24146 pub const GPIO_AD_B0_03_ALT1: u32 = 0x01;
24147 #[doc = "Selecting Pad: GPIO_AD_B0_05 for Mode: ALT6"]
24148 pub const GPIO_AD_B0_05_ALT6: u32 = 0x02;
24149 #[doc = "Selecting Pad: GPIO_B1_03 for Mode: ALT1"]
24150 pub const GPIO_B1_03_ALT1: u32 = 0x03;
24151 }
24152 }
24153}
24154#[doc = "XBAR1_IN18_SELECT_INPUT DAISY Register"]
24155pub mod XBAR1_IN18_SELECT_INPUT {
24156 #[doc = "Selecting Pads Involved in Daisy Chain."]
24157 pub mod DAISY {
24158 pub const offset: u32 = 0;
24159 pub const mask: u32 = 0x01 << offset;
24160 pub mod R {}
24161 pub mod W {}
24162 pub mod RW {
24163 #[doc = "Selecting Pad: GPIO_EMC_35 for Mode: ALT1"]
24164 pub const GPIO_EMC_35_ALT1: u32 = 0;
24165 #[doc = "Selecting Pad: GPIO_AD_B0_06 for Mode: ALT6"]
24166 pub const GPIO_AD_B0_06_ALT6: u32 = 0x01;
24167 }
24168 }
24169}
24170#[doc = "XBAR1_IN20_SELECT_INPUT DAISY Register"]
24171pub mod XBAR1_IN20_SELECT_INPUT {
24172 #[doc = "Selecting Pads Involved in Daisy Chain."]
24173 pub mod DAISY {
24174 pub const offset: u32 = 0;
24175 pub const mask: u32 = 0x01 << offset;
24176 pub mod R {}
24177 pub mod W {}
24178 pub mod RW {
24179 #[doc = "Selecting Pad: GPIO_EMC_15 for Mode: ALT1"]
24180 pub const GPIO_EMC_15_ALT1: u32 = 0;
24181 #[doc = "Selecting Pad: GPIO_AD_B0_08 for Mode: ALT6"]
24182 pub const GPIO_AD_B0_08_ALT6: u32 = 0x01;
24183 }
24184 }
24185}
24186#[doc = "XBAR1_IN22_SELECT_INPUT DAISY Register"]
24187pub mod XBAR1_IN22_SELECT_INPUT {
24188 #[doc = "Selecting Pads Involved in Daisy Chain."]
24189 pub mod DAISY {
24190 pub const offset: u32 = 0;
24191 pub const mask: u32 = 0x01 << offset;
24192 pub mod R {}
24193 pub mod W {}
24194 pub mod RW {
24195 #[doc = "Selecting Pad: GPIO_EMC_36 for Mode: ALT1"]
24196 pub const GPIO_EMC_36_ALT1: u32 = 0;
24197 #[doc = "Selecting Pad: GPIO_AD_B0_10 for Mode: ALT6"]
24198 pub const GPIO_AD_B0_10_ALT6: u32 = 0x01;
24199 }
24200 }
24201}
24202#[doc = "XBAR1_IN23_SELECT_INPUT DAISY Register"]
24203pub mod XBAR1_IN23_SELECT_INPUT {
24204 #[doc = "Selecting Pads Involved in Daisy Chain."]
24205 pub mod DAISY {
24206 pub const offset: u32 = 0;
24207 pub const mask: u32 = 0x01 << offset;
24208 pub mod R {}
24209 pub mod W {}
24210 pub mod RW {
24211 #[doc = "Selecting Pad: GPIO_EMC_37 for Mode: ALT1"]
24212 pub const GPIO_EMC_37_ALT1: u32 = 0;
24213 #[doc = "Selecting Pad: GPIO_AD_B0_11 for Mode: ALT6"]
24214 pub const GPIO_AD_B0_11_ALT6: u32 = 0x01;
24215 }
24216 }
24217}
24218#[doc = "XBAR1_IN24_SELECT_INPUT DAISY Register"]
24219pub mod XBAR1_IN24_SELECT_INPUT {
24220 #[doc = "Selecting Pads Involved in Daisy Chain."]
24221 pub mod DAISY {
24222 pub const offset: u32 = 0;
24223 pub const mask: u32 = 0x01 << offset;
24224 pub mod R {}
24225 pub mod W {}
24226 pub mod RW {
24227 #[doc = "Selecting Pad: GPIO_EMC_12 for Mode: ALT1"]
24228 pub const GPIO_EMC_12_ALT1: u32 = 0;
24229 #[doc = "Selecting Pad: GPIO_AD_B0_14 for Mode: ALT1"]
24230 pub const GPIO_AD_B0_14_ALT1: u32 = 0x01;
24231 }
24232 }
24233}
24234#[doc = "XBAR1_IN14_SELECT_INPUT DAISY Register"]
24235pub mod XBAR1_IN14_SELECT_INPUT {
24236 #[doc = "Selecting Pads Involved in Daisy Chain."]
24237 pub mod DAISY {
24238 pub const offset: u32 = 0;
24239 pub const mask: u32 = 0x01 << offset;
24240 pub mod R {}
24241 pub mod W {}
24242 pub mod RW {
24243 #[doc = "Selecting Pad: GPIO_AD_B0_00 for Mode: ALT1"]
24244 pub const GPIO_AD_B0_00_ALT1: u32 = 0;
24245 #[doc = "Selecting Pad:GPIO_B1_00 for Mode: ALT1"]
24246 pub const GPIO_B1_00_ALT1: u32 = 0x01;
24247 }
24248 }
24249}
24250#[doc = "XBAR1_IN15_SELECT_INPUT DAISY Register"]
24251pub mod XBAR1_IN15_SELECT_INPUT {
24252 #[doc = "Selecting Pads Involved in Daisy Chain."]
24253 pub mod DAISY {
24254 pub const offset: u32 = 0;
24255 pub const mask: u32 = 0x01 << offset;
24256 pub mod R {}
24257 pub mod W {}
24258 pub mod RW {
24259 #[doc = "Selecting Pad: GPIO_AD_B0_01 for Mode: ALT1"]
24260 pub const GPIO_AD_B0_01_ALT1: u32 = 0;
24261 #[doc = "Selecting Pad: GPIO_B1_01 for Mode: ALT1"]
24262 pub const GPIO_B1_01_ALT1: u32 = 0x01;
24263 }
24264 }
24265}
24266#[doc = "XBAR1_IN16_SELECT_INPUT DAISY Register"]
24267pub mod XBAR1_IN16_SELECT_INPUT {
24268 #[doc = "Selecting Pads Involved in Daisy Chain."]
24269 pub mod DAISY {
24270 pub const offset: u32 = 0;
24271 pub const mask: u32 = 0x01 << offset;
24272 pub mod R {}
24273 pub mod W {}
24274 pub mod RW {
24275 #[doc = "Selecting Pad: GPIO_AD_B0_02 for Mode: ALT1"]
24276 pub const GPIO_AD_B0_02_ALT1: u32 = 0;
24277 #[doc = "Selecting Pad: GPIO_B1_02 for Mode: ALT1"]
24278 pub const GPIO_B1_02_ALT1: u32 = 0x01;
24279 }
24280 }
24281}
24282#[doc = "XBAR1_IN25_SELECT_INPUT DAISY Register"]
24283pub mod XBAR1_IN25_SELECT_INPUT {
24284 #[doc = "Selecting Pads Involved in Daisy Chain."]
24285 pub mod DAISY {
24286 pub const offset: u32 = 0;
24287 pub const mask: u32 = 0x01 << offset;
24288 pub mod R {}
24289 pub mod W {}
24290 pub mod RW {
24291 #[doc = "Selecting Pad: GPIO_AD_B0_15 for Mode: ALT1"]
24292 pub const GPIO_AD_B0_15_ALT1: u32 = 0;
24293 #[doc = "Selecting Pad: GPIO_EMC_13 for Mode: ALT1"]
24294 pub const GPIO_EMC_13_ALT1: u32 = 0x01;
24295 }
24296 }
24297}
24298#[doc = "XBAR1_IN19_SELECT_INPUT DAISY Register"]
24299pub mod XBAR1_IN19_SELECT_INPUT {
24300 #[doc = "Selecting Pads Involved in Daisy Chain."]
24301 pub mod DAISY {
24302 pub const offset: u32 = 0;
24303 pub const mask: u32 = 0x01 << offset;
24304 pub mod R {}
24305 pub mod W {}
24306 pub mod RW {
24307 #[doc = "Selecting Pad: GPIO_EMC_14 for Mode: ALT1"]
24308 pub const GPIO_EMC_14_ALT1: u32 = 0;
24309 #[doc = "Selecting Pad: GPIO_AD_B0_07 for Mode: ALT6"]
24310 pub const GPIO_AD_B0_07_ALT6: u32 = 0x01;
24311 }
24312 }
24313}
24314#[doc = "XBAR1_IN23_SELECT_INPUT DAISY Register"]
24315pub mod XBAR1_IN21_SELECT_INPUT {
24316 #[doc = "Selecting Pads Involved in Daisy Chain."]
24317 pub mod DAISY {
24318 pub const offset: u32 = 0;
24319 pub const mask: u32 = 0x01 << offset;
24320 pub mod R {}
24321 pub mod W {}
24322 pub mod RW {
24323 #[doc = "Selecting Pad: GPIO_EMC_16 for Mode: ALT1"]
24324 pub const GPIO_EMC_16_ALT1: u32 = 0;
24325 #[doc = "Selecting Pad: GPIO_AD_B0_09 for Mode: ALT6"]
24326 pub const GPIO_AD_B0_09_ALT6: u32 = 0x01;
24327 }
24328 }
24329}
24330#[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B0_00 SW MUX Control Register"]
24331pub mod SW_MUX_CTL_PAD_GPIO_SPI_B0_00 {
24332 #[doc = "Software Input On Field."]
24333 pub mod SION {
24334 pub const offset: u32 = 4;
24335 pub const mask: u32 = 0x01 << offset;
24336 pub mod R {}
24337 pub mod W {}
24338 pub mod RW {
24339 #[doc = "Input Path is determined by functionality"]
24340 pub const DISABLED: u32 = 0;
24341 #[doc = "Force input path of pad GPIO_SPI_B0_00"]
24342 pub const ENABLED: u32 = 0x01;
24343 }
24344 }
24345}
24346#[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B0_01 SW MUX Control Register"]
24347pub mod SW_MUX_CTL_PAD_GPIO_SPI_B0_01 {
24348 #[doc = "MUX Mode Select Field."]
24349 pub mod MUX_MODE {
24350 pub const offset: u32 = 0;
24351 pub const mask: u32 = 0x07 << offset;
24352 pub mod R {}
24353 pub mod W {}
24354 pub mod RW {
24355 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_B_SCLK of instance: flexspi2"]
24356 pub const ALT0: u32 = 0;
24357 }
24358 }
24359 #[doc = "Software Input On Field."]
24360 pub mod SION {
24361 pub const offset: u32 = 4;
24362 pub const mask: u32 = 0x01 << offset;
24363 pub mod R {}
24364 pub mod W {}
24365 pub mod RW {
24366 #[doc = "Input Path is determined by functionality"]
24367 pub const DISABLED: u32 = 0;
24368 #[doc = "Force input path of pad GPIO_SPI_B0_01"]
24369 pub const ENABLED: u32 = 0x01;
24370 }
24371 }
24372}
24373#[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B0_02 SW MUX Control Register"]
24374pub mod SW_MUX_CTL_PAD_GPIO_SPI_B0_02 {
24375 #[doc = "MUX Mode Select Field."]
24376 pub mod MUX_MODE {
24377 pub const offset: u32 = 0;
24378 pub const mask: u32 = 0x07 << offset;
24379 pub mod R {}
24380 pub mod W {}
24381 pub mod RW {
24382 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_A_DATA00 of instance: flexspi2"]
24383 pub const ALT0: u32 = 0;
24384 }
24385 }
24386 #[doc = "Software Input On Field."]
24387 pub mod SION {
24388 pub const offset: u32 = 4;
24389 pub const mask: u32 = 0x01 << offset;
24390 pub mod R {}
24391 pub mod W {}
24392 pub mod RW {
24393 #[doc = "Input Path is determined by functionality"]
24394 pub const DISABLED: u32 = 0;
24395 #[doc = "Force input path of pad GPIO_SPI_B0_02"]
24396 pub const ENABLED: u32 = 0x01;
24397 }
24398 }
24399}
24400#[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B0_03 SW MUX Control Register"]
24401pub mod SW_MUX_CTL_PAD_GPIO_SPI_B0_03 {
24402 #[doc = "MUX Mode Select Field."]
24403 pub mod MUX_MODE {
24404 pub const offset: u32 = 0;
24405 pub const mask: u32 = 0x07 << offset;
24406 pub mod R {}
24407 pub mod W {}
24408 pub mod RW {
24409 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_B_DATA02 of instance: flexspi2"]
24410 pub const ALT0: u32 = 0;
24411 }
24412 }
24413 #[doc = "Software Input On Field."]
24414 pub mod SION {
24415 pub const offset: u32 = 4;
24416 pub const mask: u32 = 0x01 << offset;
24417 pub mod R {}
24418 pub mod W {}
24419 pub mod RW {
24420 #[doc = "Input Path is determined by functionality"]
24421 pub const DISABLED: u32 = 0;
24422 #[doc = "Force input path of pad GPIO_SPI_B0_03"]
24423 pub const ENABLED: u32 = 0x01;
24424 }
24425 }
24426}
24427#[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B0_04 SW MUX Control Register"]
24428pub mod SW_MUX_CTL_PAD_GPIO_SPI_B0_04 {
24429 #[doc = "MUX Mode Select Field."]
24430 pub mod MUX_MODE {
24431 pub const offset: u32 = 0;
24432 pub const mask: u32 = 0x07 << offset;
24433 pub mod R {}
24434 pub mod W {}
24435 pub mod RW {
24436 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_B_DATA03 of instance: flexspi2"]
24437 pub const ALT0: u32 = 0;
24438 }
24439 }
24440 #[doc = "Software Input On Field."]
24441 pub mod SION {
24442 pub const offset: u32 = 4;
24443 pub const mask: u32 = 0x01 << offset;
24444 pub mod R {}
24445 pub mod W {}
24446 pub mod RW {
24447 #[doc = "Input Path is determined by functionality"]
24448 pub const DISABLED: u32 = 0;
24449 #[doc = "Force input path of pad GPIO_SPI_B0_04"]
24450 pub const ENABLED: u32 = 0x01;
24451 }
24452 }
24453}
24454#[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B0_05 SW MUX Control Register"]
24455pub mod SW_MUX_CTL_PAD_GPIO_SPI_B0_05 {
24456 #[doc = "MUX Mode Select Field."]
24457 pub mod MUX_MODE {
24458 pub const offset: u32 = 0;
24459 pub const mask: u32 = 0x07 << offset;
24460 pub mod R {}
24461 pub mod W {}
24462 pub mod RW {
24463 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_A_SS0_B of instance: flexspi2"]
24464 pub const ALT0: u32 = 0;
24465 }
24466 }
24467 #[doc = "Software Input On Field."]
24468 pub mod SION {
24469 pub const offset: u32 = 4;
24470 pub const mask: u32 = 0x01 << offset;
24471 pub mod R {}
24472 pub mod W {}
24473 pub mod RW {
24474 #[doc = "Input Path is determined by functionality"]
24475 pub const DISABLED: u32 = 0;
24476 #[doc = "Force input path of pad GPIO_SPI_B0_05"]
24477 pub const ENABLED: u32 = 0x01;
24478 }
24479 }
24480}
24481#[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B0_06 SW MUX Control Register"]
24482pub mod SW_MUX_CTL_PAD_GPIO_SPI_B0_06 {
24483 #[doc = "MUX Mode Select Field."]
24484 pub mod MUX_MODE {
24485 pub const offset: u32 = 0;
24486 pub const mask: u32 = 0x07 << offset;
24487 pub mod R {}
24488 pub mod W {}
24489 pub mod RW {
24490 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_A_DATA02 of instance: flexspi2"]
24491 pub const ALT0: u32 = 0;
24492 }
24493 }
24494 #[doc = "Software Input On Field."]
24495 pub mod SION {
24496 pub const offset: u32 = 4;
24497 pub const mask: u32 = 0x01 << offset;
24498 pub mod R {}
24499 pub mod W {}
24500 pub mod RW {
24501 #[doc = "Input Path is determined by functionality"]
24502 pub const DISABLED: u32 = 0;
24503 #[doc = "Force input path of pad GPIO_SPI_B0_06"]
24504 pub const ENABLED: u32 = 0x01;
24505 }
24506 }
24507}
24508#[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B0_07 SW MUX Control Register"]
24509pub mod SW_MUX_CTL_PAD_GPIO_SPI_B0_07 {
24510 #[doc = "MUX Mode Select Field."]
24511 pub mod MUX_MODE {
24512 pub const offset: u32 = 0;
24513 pub const mask: u32 = 0x07 << offset;
24514 pub mod R {}
24515 pub mod W {}
24516 pub mod RW {
24517 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_B_DATA01 of instance: flexspi2"]
24518 pub const ALT0: u32 = 0;
24519 }
24520 }
24521 #[doc = "Software Input On Field."]
24522 pub mod SION {
24523 pub const offset: u32 = 4;
24524 pub const mask: u32 = 0x01 << offset;
24525 pub mod R {}
24526 pub mod W {}
24527 pub mod RW {
24528 #[doc = "Input Path is determined by functionality"]
24529 pub const DISABLED: u32 = 0;
24530 #[doc = "Force input path of pad GPIO_SPI_B0_07"]
24531 pub const ENABLED: u32 = 0x01;
24532 }
24533 }
24534}
24535#[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B0_08 SW MUX Control Register"]
24536pub mod SW_MUX_CTL_PAD_GPIO_SPI_B0_08 {
24537 #[doc = "MUX Mode Select Field."]
24538 pub mod MUX_MODE {
24539 pub const offset: u32 = 0;
24540 pub const mask: u32 = 0x07 << offset;
24541 pub mod R {}
24542 pub mod W {}
24543 pub mod RW {
24544 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_A_SCLK of instance: flexspi2"]
24545 pub const ALT0: u32 = 0;
24546 }
24547 }
24548 #[doc = "Software Input On Field."]
24549 pub mod SION {
24550 pub const offset: u32 = 4;
24551 pub const mask: u32 = 0x01 << offset;
24552 pub mod R {}
24553 pub mod W {}
24554 pub mod RW {
24555 #[doc = "Input Path is determined by functionality"]
24556 pub const DISABLED: u32 = 0;
24557 #[doc = "Force input path of pad GPIO_SPI_B0_08"]
24558 pub const ENABLED: u32 = 0x01;
24559 }
24560 }
24561}
24562#[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B0_09 SW MUX Control Register"]
24563pub mod SW_MUX_CTL_PAD_GPIO_SPI_B0_09 {
24564 #[doc = "MUX Mode Select Field."]
24565 pub mod MUX_MODE {
24566 pub const offset: u32 = 0;
24567 pub const mask: u32 = 0x07 << offset;
24568 pub mod R {}
24569 pub mod W {}
24570 pub mod RW {
24571 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_A_DQS of instance: flexspi2"]
24572 pub const ALT0: u32 = 0;
24573 }
24574 }
24575 #[doc = "Software Input On Field."]
24576 pub mod SION {
24577 pub const offset: u32 = 4;
24578 pub const mask: u32 = 0x01 << offset;
24579 pub mod R {}
24580 pub mod W {}
24581 pub mod RW {
24582 #[doc = "Input Path is determined by functionality"]
24583 pub const DISABLED: u32 = 0;
24584 #[doc = "Force input path of pad GPIO_SPI_B0_09"]
24585 pub const ENABLED: u32 = 0x01;
24586 }
24587 }
24588}
24589#[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B0_10 SW MUX Control Register"]
24590pub mod SW_MUX_CTL_PAD_GPIO_SPI_B0_10 {
24591 #[doc = "MUX Mode Select Field."]
24592 pub mod MUX_MODE {
24593 pub const offset: u32 = 0;
24594 pub const mask: u32 = 0x07 << offset;
24595 pub mod R {}
24596 pub mod W {}
24597 pub mod RW {
24598 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_A_DATA03 of instance: flexspi2"]
24599 pub const ALT0: u32 = 0;
24600 }
24601 }
24602 #[doc = "Software Input On Field."]
24603 pub mod SION {
24604 pub const offset: u32 = 4;
24605 pub const mask: u32 = 0x01 << offset;
24606 pub mod R {}
24607 pub mod W {}
24608 pub mod RW {
24609 #[doc = "Input Path is determined by functionality"]
24610 pub const DISABLED: u32 = 0;
24611 #[doc = "Force input path of pad GPIO_SPI_B0_10"]
24612 pub const ENABLED: u32 = 0x01;
24613 }
24614 }
24615}
24616#[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B0_11 SW MUX Control Register"]
24617pub mod SW_MUX_CTL_PAD_GPIO_SPI_B0_11 {
24618 #[doc = "MUX Mode Select Field."]
24619 pub mod MUX_MODE {
24620 pub const offset: u32 = 0;
24621 pub const mask: u32 = 0x07 << offset;
24622 pub mod R {}
24623 pub mod W {}
24624 pub mod RW {
24625 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_B_DATA00 of instance: flexspi2"]
24626 pub const ALT0: u32 = 0;
24627 }
24628 }
24629 #[doc = "Software Input On Field."]
24630 pub mod SION {
24631 pub const offset: u32 = 4;
24632 pub const mask: u32 = 0x01 << offset;
24633 pub mod R {}
24634 pub mod W {}
24635 pub mod RW {
24636 #[doc = "Input Path is determined by functionality"]
24637 pub const DISABLED: u32 = 0;
24638 #[doc = "Force input path of pad GPIO_SPI_B0_11"]
24639 pub const ENABLED: u32 = 0x01;
24640 }
24641 }
24642}
24643#[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B0_12 SW MUX Control Register"]
24644pub mod SW_MUX_CTL_PAD_GPIO_SPI_B0_12 {
24645 #[doc = "MUX Mode Select Field."]
24646 pub mod MUX_MODE {
24647 pub const offset: u32 = 0;
24648 pub const mask: u32 = 0x07 << offset;
24649 pub mod R {}
24650 pub mod W {}
24651 pub mod RW {
24652 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_A_DATA01 of instance: flexspi2"]
24653 pub const ALT0: u32 = 0;
24654 }
24655 }
24656 #[doc = "Software Input On Field."]
24657 pub mod SION {
24658 pub const offset: u32 = 4;
24659 pub const mask: u32 = 0x01 << offset;
24660 pub mod R {}
24661 pub mod W {}
24662 pub mod RW {
24663 #[doc = "Input Path is determined by functionality"]
24664 pub const DISABLED: u32 = 0;
24665 #[doc = "Force input path of pad GPIO_SPI_B0_12"]
24666 pub const ENABLED: u32 = 0x01;
24667 }
24668 }
24669}
24670#[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B0_13 SW MUX Control Register"]
24671pub mod SW_MUX_CTL_PAD_GPIO_SPI_B0_13 {
24672 #[doc = "Software Input On Field."]
24673 pub mod SION {
24674 pub const offset: u32 = 4;
24675 pub const mask: u32 = 0x01 << offset;
24676 pub mod R {}
24677 pub mod W {}
24678 pub mod RW {
24679 #[doc = "Input Path is determined by functionality"]
24680 pub const DISABLED: u32 = 0;
24681 #[doc = "Force input path of pad GPIO_SPI_B0_13"]
24682 pub const ENABLED: u32 = 0x01;
24683 }
24684 }
24685}
24686#[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B1_00 SW MUX Control Register"]
24687pub mod SW_MUX_CTL_PAD_GPIO_SPI_B1_00 {
24688 #[doc = "MUX Mode Select Field."]
24689 pub mod MUX_MODE {
24690 pub const offset: u32 = 0;
24691 pub const mask: u32 = 0x07 << offset;
24692 pub mod R {}
24693 pub mod W {}
24694 pub mod RW {
24695 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_A_DQS of instance: flexspi2"]
24696 pub const ALT0: u32 = 0;
24697 }
24698 }
24699 #[doc = "Software Input On Field."]
24700 pub mod SION {
24701 pub const offset: u32 = 4;
24702 pub const mask: u32 = 0x01 << offset;
24703 pub mod R {}
24704 pub mod W {}
24705 pub mod RW {
24706 #[doc = "Input Path is determined by functionality"]
24707 pub const DISABLED: u32 = 0;
24708 #[doc = "Force input path of pad GPIO_SPI_B1_00"]
24709 pub const ENABLED: u32 = 0x01;
24710 }
24711 }
24712}
24713#[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B1_01 SW MUX Control Register"]
24714pub mod SW_MUX_CTL_PAD_GPIO_SPI_B1_01 {
24715 #[doc = "MUX Mode Select Field."]
24716 pub mod MUX_MODE {
24717 pub const offset: u32 = 0;
24718 pub const mask: u32 = 0x07 << offset;
24719 pub mod R {}
24720 pub mod W {}
24721 pub mod RW {
24722 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_A_DATA03 of instance: flexspi2"]
24723 pub const ALT0: u32 = 0;
24724 }
24725 }
24726 #[doc = "Software Input On Field."]
24727 pub mod SION {
24728 pub const offset: u32 = 4;
24729 pub const mask: u32 = 0x01 << offset;
24730 pub mod R {}
24731 pub mod W {}
24732 pub mod RW {
24733 #[doc = "Input Path is determined by functionality"]
24734 pub const DISABLED: u32 = 0;
24735 #[doc = "Force input path of pad GPIO_SPI_B1_01"]
24736 pub const ENABLED: u32 = 0x01;
24737 }
24738 }
24739}
24740#[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B1_02 SW MUX Control Register"]
24741pub mod SW_MUX_CTL_PAD_GPIO_SPI_B1_02 {
24742 #[doc = "MUX Mode Select Field."]
24743 pub mod MUX_MODE {
24744 pub const offset: u32 = 0;
24745 pub const mask: u32 = 0x07 << offset;
24746 pub mod R {}
24747 pub mod W {}
24748 pub mod RW {
24749 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_A_DATA02 of instance: flexspi2"]
24750 pub const ALT0: u32 = 0;
24751 }
24752 }
24753 #[doc = "Software Input On Field."]
24754 pub mod SION {
24755 pub const offset: u32 = 4;
24756 pub const mask: u32 = 0x01 << offset;
24757 pub mod R {}
24758 pub mod W {}
24759 pub mod RW {
24760 #[doc = "Input Path is determined by functionality"]
24761 pub const DISABLED: u32 = 0;
24762 #[doc = "Force input path of pad GPIO_SPI_B1_02"]
24763 pub const ENABLED: u32 = 0x01;
24764 }
24765 }
24766}
24767#[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B1_03 SW MUX Control Register"]
24768pub mod SW_MUX_CTL_PAD_GPIO_SPI_B1_03 {
24769 #[doc = "MUX Mode Select Field."]
24770 pub mod MUX_MODE {
24771 pub const offset: u32 = 0;
24772 pub const mask: u32 = 0x07 << offset;
24773 pub mod R {}
24774 pub mod W {}
24775 pub mod RW {
24776 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_A_DATA01 of instance: flexspi2"]
24777 pub const ALT0: u32 = 0;
24778 }
24779 }
24780 #[doc = "Software Input On Field."]
24781 pub mod SION {
24782 pub const offset: u32 = 4;
24783 pub const mask: u32 = 0x01 << offset;
24784 pub mod R {}
24785 pub mod W {}
24786 pub mod RW {
24787 #[doc = "Input Path is determined by functionality"]
24788 pub const DISABLED: u32 = 0;
24789 #[doc = "Force input path of pad GPIO_SPI_B1_03"]
24790 pub const ENABLED: u32 = 0x01;
24791 }
24792 }
24793}
24794#[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B1_04 SW MUX Control Register"]
24795pub mod SW_MUX_CTL_PAD_GPIO_SPI_B1_04 {
24796 #[doc = "MUX Mode Select Field."]
24797 pub mod MUX_MODE {
24798 pub const offset: u32 = 0;
24799 pub const mask: u32 = 0x07 << offset;
24800 pub mod R {}
24801 pub mod W {}
24802 pub mod RW {
24803 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_A_DATA00 of instance: flexspi2"]
24804 pub const ALT0: u32 = 0;
24805 }
24806 }
24807 #[doc = "Software Input On Field."]
24808 pub mod SION {
24809 pub const offset: u32 = 4;
24810 pub const mask: u32 = 0x01 << offset;
24811 pub mod R {}
24812 pub mod W {}
24813 pub mod RW {
24814 #[doc = "Input Path is determined by functionality"]
24815 pub const DISABLED: u32 = 0;
24816 #[doc = "Force input path of pad GPIO_SPI_B1_04"]
24817 pub const ENABLED: u32 = 0x01;
24818 }
24819 }
24820}
24821#[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B1_05 SW MUX Control Register"]
24822pub mod SW_MUX_CTL_PAD_GPIO_SPI_B1_05 {
24823 #[doc = "MUX Mode Select Field."]
24824 pub mod MUX_MODE {
24825 pub const offset: u32 = 0;
24826 pub const mask: u32 = 0x07 << offset;
24827 pub mod R {}
24828 pub mod W {}
24829 pub mod RW {
24830 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_A_SCLK of instance: flexspi2"]
24831 pub const ALT0: u32 = 0;
24832 }
24833 }
24834 #[doc = "Software Input On Field."]
24835 pub mod SION {
24836 pub const offset: u32 = 4;
24837 pub const mask: u32 = 0x01 << offset;
24838 pub mod R {}
24839 pub mod W {}
24840 pub mod RW {
24841 #[doc = "Input Path is determined by functionality"]
24842 pub const DISABLED: u32 = 0;
24843 #[doc = "Force input path of pad GPIO_SPI_B1_05"]
24844 pub const ENABLED: u32 = 0x01;
24845 }
24846 }
24847}
24848#[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B1_06 SW MUX Control Register"]
24849pub mod SW_MUX_CTL_PAD_GPIO_SPI_B1_06 {
24850 #[doc = "MUX Mode Select Field."]
24851 pub mod MUX_MODE {
24852 pub const offset: u32 = 0;
24853 pub const mask: u32 = 0x07 << offset;
24854 pub mod R {}
24855 pub mod W {}
24856 pub mod RW {
24857 #[doc = "Select mux mode: ALT0 mux port: FLEXSPI2_A_SS0_B of instance: flexspi2"]
24858 pub const ALT0: u32 = 0;
24859 }
24860 }
24861 #[doc = "Software Input On Field."]
24862 pub mod SION {
24863 pub const offset: u32 = 4;
24864 pub const mask: u32 = 0x01 << offset;
24865 pub mod R {}
24866 pub mod W {}
24867 pub mod RW {
24868 #[doc = "Input Path is determined by functionality"]
24869 pub const DISABLED: u32 = 0;
24870 #[doc = "Force input path of pad GPIO_SPI_B1_06"]
24871 pub const ENABLED: u32 = 0x01;
24872 }
24873 }
24874}
24875#[doc = "SW_MUX_CTL_PAD_GPIO_SPI_B1_07 SW MUX Control Register"]
24876pub mod SW_MUX_CTL_PAD_GPIO_SPI_B1_07 {
24877 #[doc = "Software Input On Field."]
24878 pub mod SION {
24879 pub const offset: u32 = 4;
24880 pub const mask: u32 = 0x01 << offset;
24881 pub mod R {}
24882 pub mod W {}
24883 pub mod RW {
24884 #[doc = "Input Path is determined by functionality"]
24885 pub const DISABLED: u32 = 0;
24886 #[doc = "Force input path of pad GPIO_SPI_B1_07"]
24887 pub const ENABLED: u32 = 0x01;
24888 }
24889 }
24890}
24891#[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B0_00 SW PAD Control Register"]
24892pub mod SW_PAD_CTL_PAD_GPIO_SPI_B0_00 {
24893 #[doc = "Slew Rate Field"]
24894 pub mod SRE {
24895 pub const offset: u32 = 0;
24896 pub const mask: u32 = 0x01 << offset;
24897 pub mod R {}
24898 pub mod W {}
24899 pub mod RW {
24900 #[doc = "Slow Slew Rate"]
24901 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
24902 #[doc = "Fast Slew Rate"]
24903 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
24904 }
24905 }
24906 #[doc = "Drive Strength Field"]
24907 pub mod DSE {
24908 pub const offset: u32 = 3;
24909 pub const mask: u32 = 0x07 << offset;
24910 pub mod R {}
24911 pub mod W {}
24912 pub mod RW {
24913 #[doc = "output driver disabled;"]
24914 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
24915 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
24916 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V_: u32 = 0x01;
24917 #[doc = "R0/2"]
24918 pub const DSE_2_R0_2: u32 = 0x02;
24919 #[doc = "R0/3"]
24920 pub const DSE_3_R0_3: u32 = 0x03;
24921 #[doc = "R0/4"]
24922 pub const DSE_4_R0_4: u32 = 0x04;
24923 #[doc = "R0/5"]
24924 pub const DSE_5_R0_5: u32 = 0x05;
24925 #[doc = "R0/6"]
24926 pub const DSE_6_R0_6: u32 = 0x06;
24927 #[doc = "R0/7"]
24928 pub const DSE_7_R0_7: u32 = 0x07;
24929 }
24930 }
24931 #[doc = "Speed Field"]
24932 pub mod SPEED {
24933 pub const offset: u32 = 6;
24934 pub const mask: u32 = 0x03 << offset;
24935 pub mod R {}
24936 pub mod W {}
24937 pub mod RW {
24938 #[doc = "low(50MHz)"]
24939 pub const SPEED_0_LOW_50MHZ_: u32 = 0;
24940 #[doc = "medium(100MHz)"]
24941 pub const SPEED_1_MEDIUM_100MHZ_: u32 = 0x01;
24942 #[doc = "medium(100MHz)"]
24943 pub const SPEED_2_MEDIUM_100MHZ_: u32 = 0x02;
24944 #[doc = "max(200MHz)"]
24945 pub const SPEED_3_MAX_200MHZ_: u32 = 0x03;
24946 }
24947 }
24948 #[doc = "Open Drain Enable Field"]
24949 pub mod ODE {
24950 pub const offset: u32 = 11;
24951 pub const mask: u32 = 0x01 << offset;
24952 pub mod R {}
24953 pub mod W {}
24954 pub mod RW {
24955 #[doc = "Open Drain Disabled"]
24956 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
24957 #[doc = "Open Drain Enabled"]
24958 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
24959 }
24960 }
24961 #[doc = "Pull / Keep Enable Field"]
24962 pub mod PKE {
24963 pub const offset: u32 = 12;
24964 pub const mask: u32 = 0x01 << offset;
24965 pub mod R {}
24966 pub mod W {}
24967 pub mod RW {
24968 #[doc = "Pull/Keeper Disabled"]
24969 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
24970 #[doc = "Pull/Keeper Enabled"]
24971 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
24972 }
24973 }
24974 #[doc = "Pull / Keep Select Field"]
24975 pub mod PUE {
24976 pub const offset: u32 = 13;
24977 pub const mask: u32 = 0x01 << offset;
24978 pub mod R {}
24979 pub mod W {}
24980 pub mod RW {
24981 #[doc = "Keeper"]
24982 pub const PUE_0_KEEPER: u32 = 0;
24983 #[doc = "Pull"]
24984 pub const PUE_1_PULL: u32 = 0x01;
24985 }
24986 }
24987 #[doc = "Pull Up / Down Config. Field"]
24988 pub mod PUS {
24989 pub const offset: u32 = 14;
24990 pub const mask: u32 = 0x03 << offset;
24991 pub mod R {}
24992 pub mod W {}
24993 pub mod RW {
24994 #[doc = "100K Ohm Pull Down"]
24995 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
24996 #[doc = "47K Ohm Pull Up"]
24997 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
24998 #[doc = "100K Ohm Pull Up"]
24999 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
25000 #[doc = "22K Ohm Pull Up"]
25001 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
25002 }
25003 }
25004 #[doc = "Hyst. Enable Field"]
25005 pub mod HYS {
25006 pub const offset: u32 = 16;
25007 pub const mask: u32 = 0x01 << offset;
25008 pub mod R {}
25009 pub mod W {}
25010 pub mod RW {
25011 #[doc = "Hysteresis Disabled"]
25012 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
25013 #[doc = "Hysteresis Enabled"]
25014 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
25015 }
25016 }
25017}
25018#[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B0_01 SW PAD Control Register"]
25019pub mod SW_PAD_CTL_PAD_GPIO_SPI_B0_01 {
25020 #[doc = "Slew Rate Field"]
25021 pub mod SRE {
25022 pub const offset: u32 = 0;
25023 pub const mask: u32 = 0x01 << offset;
25024 pub mod R {}
25025 pub mod W {}
25026 pub mod RW {
25027 #[doc = "Slow Slew Rate"]
25028 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
25029 #[doc = "Fast Slew Rate"]
25030 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
25031 }
25032 }
25033 #[doc = "Drive Strength Field"]
25034 pub mod DSE {
25035 pub const offset: u32 = 3;
25036 pub const mask: u32 = 0x07 << offset;
25037 pub mod R {}
25038 pub mod W {}
25039 pub mod RW {
25040 #[doc = "output driver disabled;"]
25041 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
25042 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
25043 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V_: u32 = 0x01;
25044 #[doc = "R0/2"]
25045 pub const DSE_2_R0_2: u32 = 0x02;
25046 #[doc = "R0/3"]
25047 pub const DSE_3_R0_3: u32 = 0x03;
25048 #[doc = "R0/4"]
25049 pub const DSE_4_R0_4: u32 = 0x04;
25050 #[doc = "R0/5"]
25051 pub const DSE_5_R0_5: u32 = 0x05;
25052 #[doc = "R0/6"]
25053 pub const DSE_6_R0_6: u32 = 0x06;
25054 #[doc = "R0/7"]
25055 pub const DSE_7_R0_7: u32 = 0x07;
25056 }
25057 }
25058 #[doc = "Speed Field"]
25059 pub mod SPEED {
25060 pub const offset: u32 = 6;
25061 pub const mask: u32 = 0x03 << offset;
25062 pub mod R {}
25063 pub mod W {}
25064 pub mod RW {
25065 #[doc = "low(50MHz)"]
25066 pub const SPEED_0_LOW_50MHZ_: u32 = 0;
25067 #[doc = "medium(100MHz)"]
25068 pub const SPEED_1_MEDIUM_100MHZ_: u32 = 0x01;
25069 #[doc = "medium(100MHz)"]
25070 pub const SPEED_2_MEDIUM_100MHZ_: u32 = 0x02;
25071 #[doc = "max(200MHz)"]
25072 pub const SPEED_3_MAX_200MHZ_: u32 = 0x03;
25073 }
25074 }
25075 #[doc = "Open Drain Enable Field"]
25076 pub mod ODE {
25077 pub const offset: u32 = 11;
25078 pub const mask: u32 = 0x01 << offset;
25079 pub mod R {}
25080 pub mod W {}
25081 pub mod RW {
25082 #[doc = "Open Drain Disabled"]
25083 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
25084 #[doc = "Open Drain Enabled"]
25085 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
25086 }
25087 }
25088 #[doc = "Pull / Keep Enable Field"]
25089 pub mod PKE {
25090 pub const offset: u32 = 12;
25091 pub const mask: u32 = 0x01 << offset;
25092 pub mod R {}
25093 pub mod W {}
25094 pub mod RW {
25095 #[doc = "Pull/Keeper Disabled"]
25096 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
25097 #[doc = "Pull/Keeper Enabled"]
25098 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
25099 }
25100 }
25101 #[doc = "Pull / Keep Select Field"]
25102 pub mod PUE {
25103 pub const offset: u32 = 13;
25104 pub const mask: u32 = 0x01 << offset;
25105 pub mod R {}
25106 pub mod W {}
25107 pub mod RW {
25108 #[doc = "Keeper"]
25109 pub const PUE_0_KEEPER: u32 = 0;
25110 #[doc = "Pull"]
25111 pub const PUE_1_PULL: u32 = 0x01;
25112 }
25113 }
25114 #[doc = "Pull Up / Down Config. Field"]
25115 pub mod PUS {
25116 pub const offset: u32 = 14;
25117 pub const mask: u32 = 0x03 << offset;
25118 pub mod R {}
25119 pub mod W {}
25120 pub mod RW {
25121 #[doc = "100K Ohm Pull Down"]
25122 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
25123 #[doc = "47K Ohm Pull Up"]
25124 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
25125 #[doc = "100K Ohm Pull Up"]
25126 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
25127 #[doc = "22K Ohm Pull Up"]
25128 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
25129 }
25130 }
25131 #[doc = "Hyst. Enable Field"]
25132 pub mod HYS {
25133 pub const offset: u32 = 16;
25134 pub const mask: u32 = 0x01 << offset;
25135 pub mod R {}
25136 pub mod W {}
25137 pub mod RW {
25138 #[doc = "Hysteresis Disabled"]
25139 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
25140 #[doc = "Hysteresis Enabled"]
25141 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
25142 }
25143 }
25144}
25145#[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B0_02 SW PAD Control Register"]
25146pub mod SW_PAD_CTL_PAD_GPIO_SPI_B0_02 {
25147 #[doc = "Slew Rate Field"]
25148 pub mod SRE {
25149 pub const offset: u32 = 0;
25150 pub const mask: u32 = 0x01 << offset;
25151 pub mod R {}
25152 pub mod W {}
25153 pub mod RW {
25154 #[doc = "Slow Slew Rate"]
25155 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
25156 #[doc = "Fast Slew Rate"]
25157 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
25158 }
25159 }
25160 #[doc = "Drive Strength Field"]
25161 pub mod DSE {
25162 pub const offset: u32 = 3;
25163 pub const mask: u32 = 0x07 << offset;
25164 pub mod R {}
25165 pub mod W {}
25166 pub mod RW {
25167 #[doc = "output driver disabled;"]
25168 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
25169 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
25170 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V_: u32 = 0x01;
25171 #[doc = "R0/2"]
25172 pub const DSE_2_R0_2: u32 = 0x02;
25173 #[doc = "R0/3"]
25174 pub const DSE_3_R0_3: u32 = 0x03;
25175 #[doc = "R0/4"]
25176 pub const DSE_4_R0_4: u32 = 0x04;
25177 #[doc = "R0/5"]
25178 pub const DSE_5_R0_5: u32 = 0x05;
25179 #[doc = "R0/6"]
25180 pub const DSE_6_R0_6: u32 = 0x06;
25181 #[doc = "R0/7"]
25182 pub const DSE_7_R0_7: u32 = 0x07;
25183 }
25184 }
25185 #[doc = "Speed Field"]
25186 pub mod SPEED {
25187 pub const offset: u32 = 6;
25188 pub const mask: u32 = 0x03 << offset;
25189 pub mod R {}
25190 pub mod W {}
25191 pub mod RW {
25192 #[doc = "low(50MHz)"]
25193 pub const SPEED_0_LOW_50MHZ_: u32 = 0;
25194 #[doc = "medium(100MHz)"]
25195 pub const SPEED_1_MEDIUM_100MHZ_: u32 = 0x01;
25196 #[doc = "medium(100MHz)"]
25197 pub const SPEED_2_MEDIUM_100MHZ_: u32 = 0x02;
25198 #[doc = "max(200MHz)"]
25199 pub const SPEED_3_MAX_200MHZ_: u32 = 0x03;
25200 }
25201 }
25202 #[doc = "Open Drain Enable Field"]
25203 pub mod ODE {
25204 pub const offset: u32 = 11;
25205 pub const mask: u32 = 0x01 << offset;
25206 pub mod R {}
25207 pub mod W {}
25208 pub mod RW {
25209 #[doc = "Open Drain Disabled"]
25210 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
25211 #[doc = "Open Drain Enabled"]
25212 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
25213 }
25214 }
25215 #[doc = "Pull / Keep Enable Field"]
25216 pub mod PKE {
25217 pub const offset: u32 = 12;
25218 pub const mask: u32 = 0x01 << offset;
25219 pub mod R {}
25220 pub mod W {}
25221 pub mod RW {
25222 #[doc = "Pull/Keeper Disabled"]
25223 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
25224 #[doc = "Pull/Keeper Enabled"]
25225 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
25226 }
25227 }
25228 #[doc = "Pull / Keep Select Field"]
25229 pub mod PUE {
25230 pub const offset: u32 = 13;
25231 pub const mask: u32 = 0x01 << offset;
25232 pub mod R {}
25233 pub mod W {}
25234 pub mod RW {
25235 #[doc = "Keeper"]
25236 pub const PUE_0_KEEPER: u32 = 0;
25237 #[doc = "Pull"]
25238 pub const PUE_1_PULL: u32 = 0x01;
25239 }
25240 }
25241 #[doc = "Pull Up / Down Config. Field"]
25242 pub mod PUS {
25243 pub const offset: u32 = 14;
25244 pub const mask: u32 = 0x03 << offset;
25245 pub mod R {}
25246 pub mod W {}
25247 pub mod RW {
25248 #[doc = "100K Ohm Pull Down"]
25249 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
25250 #[doc = "47K Ohm Pull Up"]
25251 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
25252 #[doc = "100K Ohm Pull Up"]
25253 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
25254 #[doc = "22K Ohm Pull Up"]
25255 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
25256 }
25257 }
25258 #[doc = "Hyst. Enable Field"]
25259 pub mod HYS {
25260 pub const offset: u32 = 16;
25261 pub const mask: u32 = 0x01 << offset;
25262 pub mod R {}
25263 pub mod W {}
25264 pub mod RW {
25265 #[doc = "Hysteresis Disabled"]
25266 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
25267 #[doc = "Hysteresis Enabled"]
25268 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
25269 }
25270 }
25271}
25272#[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B0_03 SW PAD Control Register"]
25273pub mod SW_PAD_CTL_PAD_GPIO_SPI_B0_03 {
25274 #[doc = "Slew Rate Field"]
25275 pub mod SRE {
25276 pub const offset: u32 = 0;
25277 pub const mask: u32 = 0x01 << offset;
25278 pub mod R {}
25279 pub mod W {}
25280 pub mod RW {
25281 #[doc = "Slow Slew Rate"]
25282 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
25283 #[doc = "Fast Slew Rate"]
25284 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
25285 }
25286 }
25287 #[doc = "Drive Strength Field"]
25288 pub mod DSE {
25289 pub const offset: u32 = 3;
25290 pub const mask: u32 = 0x07 << offset;
25291 pub mod R {}
25292 pub mod W {}
25293 pub mod RW {
25294 #[doc = "output driver disabled;"]
25295 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
25296 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
25297 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V_: u32 = 0x01;
25298 #[doc = "R0/2"]
25299 pub const DSE_2_R0_2: u32 = 0x02;
25300 #[doc = "R0/3"]
25301 pub const DSE_3_R0_3: u32 = 0x03;
25302 #[doc = "R0/4"]
25303 pub const DSE_4_R0_4: u32 = 0x04;
25304 #[doc = "R0/5"]
25305 pub const DSE_5_R0_5: u32 = 0x05;
25306 #[doc = "R0/6"]
25307 pub const DSE_6_R0_6: u32 = 0x06;
25308 #[doc = "R0/7"]
25309 pub const DSE_7_R0_7: u32 = 0x07;
25310 }
25311 }
25312 #[doc = "Speed Field"]
25313 pub mod SPEED {
25314 pub const offset: u32 = 6;
25315 pub const mask: u32 = 0x03 << offset;
25316 pub mod R {}
25317 pub mod W {}
25318 pub mod RW {
25319 #[doc = "low(50MHz)"]
25320 pub const SPEED_0_LOW_50MHZ_: u32 = 0;
25321 #[doc = "medium(100MHz)"]
25322 pub const SPEED_1_MEDIUM_100MHZ_: u32 = 0x01;
25323 #[doc = "medium(100MHz)"]
25324 pub const SPEED_2_MEDIUM_100MHZ_: u32 = 0x02;
25325 #[doc = "max(200MHz)"]
25326 pub const SPEED_3_MAX_200MHZ_: u32 = 0x03;
25327 }
25328 }
25329 #[doc = "Open Drain Enable Field"]
25330 pub mod ODE {
25331 pub const offset: u32 = 11;
25332 pub const mask: u32 = 0x01 << offset;
25333 pub mod R {}
25334 pub mod W {}
25335 pub mod RW {
25336 #[doc = "Open Drain Disabled"]
25337 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
25338 #[doc = "Open Drain Enabled"]
25339 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
25340 }
25341 }
25342 #[doc = "Pull / Keep Enable Field"]
25343 pub mod PKE {
25344 pub const offset: u32 = 12;
25345 pub const mask: u32 = 0x01 << offset;
25346 pub mod R {}
25347 pub mod W {}
25348 pub mod RW {
25349 #[doc = "Pull/Keeper Disabled"]
25350 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
25351 #[doc = "Pull/Keeper Enabled"]
25352 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
25353 }
25354 }
25355 #[doc = "Pull / Keep Select Field"]
25356 pub mod PUE {
25357 pub const offset: u32 = 13;
25358 pub const mask: u32 = 0x01 << offset;
25359 pub mod R {}
25360 pub mod W {}
25361 pub mod RW {
25362 #[doc = "Keeper"]
25363 pub const PUE_0_KEEPER: u32 = 0;
25364 #[doc = "Pull"]
25365 pub const PUE_1_PULL: u32 = 0x01;
25366 }
25367 }
25368 #[doc = "Pull Up / Down Config. Field"]
25369 pub mod PUS {
25370 pub const offset: u32 = 14;
25371 pub const mask: u32 = 0x03 << offset;
25372 pub mod R {}
25373 pub mod W {}
25374 pub mod RW {
25375 #[doc = "100K Ohm Pull Down"]
25376 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
25377 #[doc = "47K Ohm Pull Up"]
25378 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
25379 #[doc = "100K Ohm Pull Up"]
25380 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
25381 #[doc = "22K Ohm Pull Up"]
25382 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
25383 }
25384 }
25385 #[doc = "Hyst. Enable Field"]
25386 pub mod HYS {
25387 pub const offset: u32 = 16;
25388 pub const mask: u32 = 0x01 << offset;
25389 pub mod R {}
25390 pub mod W {}
25391 pub mod RW {
25392 #[doc = "Hysteresis Disabled"]
25393 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
25394 #[doc = "Hysteresis Enabled"]
25395 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
25396 }
25397 }
25398}
25399#[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B0_04 SW PAD Control Register"]
25400pub mod SW_PAD_CTL_PAD_GPIO_SPI_B0_04 {
25401 #[doc = "Slew Rate Field"]
25402 pub mod SRE {
25403 pub const offset: u32 = 0;
25404 pub const mask: u32 = 0x01 << offset;
25405 pub mod R {}
25406 pub mod W {}
25407 pub mod RW {
25408 #[doc = "Slow Slew Rate"]
25409 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
25410 #[doc = "Fast Slew Rate"]
25411 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
25412 }
25413 }
25414 #[doc = "Drive Strength Field"]
25415 pub mod DSE {
25416 pub const offset: u32 = 3;
25417 pub const mask: u32 = 0x07 << offset;
25418 pub mod R {}
25419 pub mod W {}
25420 pub mod RW {
25421 #[doc = "output driver disabled;"]
25422 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
25423 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
25424 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V_: u32 = 0x01;
25425 #[doc = "R0/2"]
25426 pub const DSE_2_R0_2: u32 = 0x02;
25427 #[doc = "R0/3"]
25428 pub const DSE_3_R0_3: u32 = 0x03;
25429 #[doc = "R0/4"]
25430 pub const DSE_4_R0_4: u32 = 0x04;
25431 #[doc = "R0/5"]
25432 pub const DSE_5_R0_5: u32 = 0x05;
25433 #[doc = "R0/6"]
25434 pub const DSE_6_R0_6: u32 = 0x06;
25435 #[doc = "R0/7"]
25436 pub const DSE_7_R0_7: u32 = 0x07;
25437 }
25438 }
25439 #[doc = "Speed Field"]
25440 pub mod SPEED {
25441 pub const offset: u32 = 6;
25442 pub const mask: u32 = 0x03 << offset;
25443 pub mod R {}
25444 pub mod W {}
25445 pub mod RW {
25446 #[doc = "low(50MHz)"]
25447 pub const SPEED_0_LOW_50MHZ_: u32 = 0;
25448 #[doc = "medium(100MHz)"]
25449 pub const SPEED_1_MEDIUM_100MHZ_: u32 = 0x01;
25450 #[doc = "medium(100MHz)"]
25451 pub const SPEED_2_MEDIUM_100MHZ_: u32 = 0x02;
25452 #[doc = "max(200MHz)"]
25453 pub const SPEED_3_MAX_200MHZ_: u32 = 0x03;
25454 }
25455 }
25456 #[doc = "Open Drain Enable Field"]
25457 pub mod ODE {
25458 pub const offset: u32 = 11;
25459 pub const mask: u32 = 0x01 << offset;
25460 pub mod R {}
25461 pub mod W {}
25462 pub mod RW {
25463 #[doc = "Open Drain Disabled"]
25464 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
25465 #[doc = "Open Drain Enabled"]
25466 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
25467 }
25468 }
25469 #[doc = "Pull / Keep Enable Field"]
25470 pub mod PKE {
25471 pub const offset: u32 = 12;
25472 pub const mask: u32 = 0x01 << offset;
25473 pub mod R {}
25474 pub mod W {}
25475 pub mod RW {
25476 #[doc = "Pull/Keeper Disabled"]
25477 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
25478 #[doc = "Pull/Keeper Enabled"]
25479 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
25480 }
25481 }
25482 #[doc = "Pull / Keep Select Field"]
25483 pub mod PUE {
25484 pub const offset: u32 = 13;
25485 pub const mask: u32 = 0x01 << offset;
25486 pub mod R {}
25487 pub mod W {}
25488 pub mod RW {
25489 #[doc = "Keeper"]
25490 pub const PUE_0_KEEPER: u32 = 0;
25491 #[doc = "Pull"]
25492 pub const PUE_1_PULL: u32 = 0x01;
25493 }
25494 }
25495 #[doc = "Pull Up / Down Config. Field"]
25496 pub mod PUS {
25497 pub const offset: u32 = 14;
25498 pub const mask: u32 = 0x03 << offset;
25499 pub mod R {}
25500 pub mod W {}
25501 pub mod RW {
25502 #[doc = "100K Ohm Pull Down"]
25503 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
25504 #[doc = "47K Ohm Pull Up"]
25505 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
25506 #[doc = "100K Ohm Pull Up"]
25507 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
25508 #[doc = "22K Ohm Pull Up"]
25509 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
25510 }
25511 }
25512 #[doc = "Hyst. Enable Field"]
25513 pub mod HYS {
25514 pub const offset: u32 = 16;
25515 pub const mask: u32 = 0x01 << offset;
25516 pub mod R {}
25517 pub mod W {}
25518 pub mod RW {
25519 #[doc = "Hysteresis Disabled"]
25520 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
25521 #[doc = "Hysteresis Enabled"]
25522 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
25523 }
25524 }
25525}
25526#[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B0_05 SW PAD Control Register"]
25527pub mod SW_PAD_CTL_PAD_GPIO_SPI_B0_05 {
25528 #[doc = "Slew Rate Field"]
25529 pub mod SRE {
25530 pub const offset: u32 = 0;
25531 pub const mask: u32 = 0x01 << offset;
25532 pub mod R {}
25533 pub mod W {}
25534 pub mod RW {
25535 #[doc = "Slow Slew Rate"]
25536 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
25537 #[doc = "Fast Slew Rate"]
25538 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
25539 }
25540 }
25541 #[doc = "Drive Strength Field"]
25542 pub mod DSE {
25543 pub const offset: u32 = 3;
25544 pub const mask: u32 = 0x07 << offset;
25545 pub mod R {}
25546 pub mod W {}
25547 pub mod RW {
25548 #[doc = "output driver disabled;"]
25549 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
25550 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
25551 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V_: u32 = 0x01;
25552 #[doc = "R0/2"]
25553 pub const DSE_2_R0_2: u32 = 0x02;
25554 #[doc = "R0/3"]
25555 pub const DSE_3_R0_3: u32 = 0x03;
25556 #[doc = "R0/4"]
25557 pub const DSE_4_R0_4: u32 = 0x04;
25558 #[doc = "R0/5"]
25559 pub const DSE_5_R0_5: u32 = 0x05;
25560 #[doc = "R0/6"]
25561 pub const DSE_6_R0_6: u32 = 0x06;
25562 #[doc = "R0/7"]
25563 pub const DSE_7_R0_7: u32 = 0x07;
25564 }
25565 }
25566 #[doc = "Speed Field"]
25567 pub mod SPEED {
25568 pub const offset: u32 = 6;
25569 pub const mask: u32 = 0x03 << offset;
25570 pub mod R {}
25571 pub mod W {}
25572 pub mod RW {
25573 #[doc = "low(50MHz)"]
25574 pub const SPEED_0_LOW_50MHZ_: u32 = 0;
25575 #[doc = "medium(100MHz)"]
25576 pub const SPEED_1_MEDIUM_100MHZ_: u32 = 0x01;
25577 #[doc = "medium(100MHz)"]
25578 pub const SPEED_2_MEDIUM_100MHZ_: u32 = 0x02;
25579 #[doc = "max(200MHz)"]
25580 pub const SPEED_3_MAX_200MHZ_: u32 = 0x03;
25581 }
25582 }
25583 #[doc = "Open Drain Enable Field"]
25584 pub mod ODE {
25585 pub const offset: u32 = 11;
25586 pub const mask: u32 = 0x01 << offset;
25587 pub mod R {}
25588 pub mod W {}
25589 pub mod RW {
25590 #[doc = "Open Drain Disabled"]
25591 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
25592 #[doc = "Open Drain Enabled"]
25593 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
25594 }
25595 }
25596 #[doc = "Pull / Keep Enable Field"]
25597 pub mod PKE {
25598 pub const offset: u32 = 12;
25599 pub const mask: u32 = 0x01 << offset;
25600 pub mod R {}
25601 pub mod W {}
25602 pub mod RW {
25603 #[doc = "Pull/Keeper Disabled"]
25604 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
25605 #[doc = "Pull/Keeper Enabled"]
25606 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
25607 }
25608 }
25609 #[doc = "Pull / Keep Select Field"]
25610 pub mod PUE {
25611 pub const offset: u32 = 13;
25612 pub const mask: u32 = 0x01 << offset;
25613 pub mod R {}
25614 pub mod W {}
25615 pub mod RW {
25616 #[doc = "Keeper"]
25617 pub const PUE_0_KEEPER: u32 = 0;
25618 #[doc = "Pull"]
25619 pub const PUE_1_PULL: u32 = 0x01;
25620 }
25621 }
25622 #[doc = "Pull Up / Down Config. Field"]
25623 pub mod PUS {
25624 pub const offset: u32 = 14;
25625 pub const mask: u32 = 0x03 << offset;
25626 pub mod R {}
25627 pub mod W {}
25628 pub mod RW {
25629 #[doc = "100K Ohm Pull Down"]
25630 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
25631 #[doc = "47K Ohm Pull Up"]
25632 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
25633 #[doc = "100K Ohm Pull Up"]
25634 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
25635 #[doc = "22K Ohm Pull Up"]
25636 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
25637 }
25638 }
25639 #[doc = "Hyst. Enable Field"]
25640 pub mod HYS {
25641 pub const offset: u32 = 16;
25642 pub const mask: u32 = 0x01 << offset;
25643 pub mod R {}
25644 pub mod W {}
25645 pub mod RW {
25646 #[doc = "Hysteresis Disabled"]
25647 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
25648 #[doc = "Hysteresis Enabled"]
25649 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
25650 }
25651 }
25652}
25653#[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B0_06 SW PAD Control Register"]
25654pub mod SW_PAD_CTL_PAD_GPIO_SPI_B0_06 {
25655 #[doc = "Slew Rate Field"]
25656 pub mod SRE {
25657 pub const offset: u32 = 0;
25658 pub const mask: u32 = 0x01 << offset;
25659 pub mod R {}
25660 pub mod W {}
25661 pub mod RW {
25662 #[doc = "Slow Slew Rate"]
25663 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
25664 #[doc = "Fast Slew Rate"]
25665 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
25666 }
25667 }
25668 #[doc = "Drive Strength Field"]
25669 pub mod DSE {
25670 pub const offset: u32 = 3;
25671 pub const mask: u32 = 0x07 << offset;
25672 pub mod R {}
25673 pub mod W {}
25674 pub mod RW {
25675 #[doc = "output driver disabled;"]
25676 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
25677 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
25678 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V_: u32 = 0x01;
25679 #[doc = "R0/2"]
25680 pub const DSE_2_R0_2: u32 = 0x02;
25681 #[doc = "R0/3"]
25682 pub const DSE_3_R0_3: u32 = 0x03;
25683 #[doc = "R0/4"]
25684 pub const DSE_4_R0_4: u32 = 0x04;
25685 #[doc = "R0/5"]
25686 pub const DSE_5_R0_5: u32 = 0x05;
25687 #[doc = "R0/6"]
25688 pub const DSE_6_R0_6: u32 = 0x06;
25689 #[doc = "R0/7"]
25690 pub const DSE_7_R0_7: u32 = 0x07;
25691 }
25692 }
25693 #[doc = "Speed Field"]
25694 pub mod SPEED {
25695 pub const offset: u32 = 6;
25696 pub const mask: u32 = 0x03 << offset;
25697 pub mod R {}
25698 pub mod W {}
25699 pub mod RW {
25700 #[doc = "low(50MHz)"]
25701 pub const SPEED_0_LOW_50MHZ_: u32 = 0;
25702 #[doc = "medium(100MHz)"]
25703 pub const SPEED_1_MEDIUM_100MHZ_: u32 = 0x01;
25704 #[doc = "medium(100MHz)"]
25705 pub const SPEED_2_MEDIUM_100MHZ_: u32 = 0x02;
25706 #[doc = "max(200MHz)"]
25707 pub const SPEED_3_MAX_200MHZ_: u32 = 0x03;
25708 }
25709 }
25710 #[doc = "Open Drain Enable Field"]
25711 pub mod ODE {
25712 pub const offset: u32 = 11;
25713 pub const mask: u32 = 0x01 << offset;
25714 pub mod R {}
25715 pub mod W {}
25716 pub mod RW {
25717 #[doc = "Open Drain Disabled"]
25718 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
25719 #[doc = "Open Drain Enabled"]
25720 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
25721 }
25722 }
25723 #[doc = "Pull / Keep Enable Field"]
25724 pub mod PKE {
25725 pub const offset: u32 = 12;
25726 pub const mask: u32 = 0x01 << offset;
25727 pub mod R {}
25728 pub mod W {}
25729 pub mod RW {
25730 #[doc = "Pull/Keeper Disabled"]
25731 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
25732 #[doc = "Pull/Keeper Enabled"]
25733 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
25734 }
25735 }
25736 #[doc = "Pull / Keep Select Field"]
25737 pub mod PUE {
25738 pub const offset: u32 = 13;
25739 pub const mask: u32 = 0x01 << offset;
25740 pub mod R {}
25741 pub mod W {}
25742 pub mod RW {
25743 #[doc = "Keeper"]
25744 pub const PUE_0_KEEPER: u32 = 0;
25745 #[doc = "Pull"]
25746 pub const PUE_1_PULL: u32 = 0x01;
25747 }
25748 }
25749 #[doc = "Pull Up / Down Config. Field"]
25750 pub mod PUS {
25751 pub const offset: u32 = 14;
25752 pub const mask: u32 = 0x03 << offset;
25753 pub mod R {}
25754 pub mod W {}
25755 pub mod RW {
25756 #[doc = "100K Ohm Pull Down"]
25757 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
25758 #[doc = "47K Ohm Pull Up"]
25759 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
25760 #[doc = "100K Ohm Pull Up"]
25761 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
25762 #[doc = "22K Ohm Pull Up"]
25763 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
25764 }
25765 }
25766 #[doc = "Hyst. Enable Field"]
25767 pub mod HYS {
25768 pub const offset: u32 = 16;
25769 pub const mask: u32 = 0x01 << offset;
25770 pub mod R {}
25771 pub mod W {}
25772 pub mod RW {
25773 #[doc = "Hysteresis Disabled"]
25774 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
25775 #[doc = "Hysteresis Enabled"]
25776 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
25777 }
25778 }
25779}
25780#[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B0_07 SW PAD Control Register"]
25781pub mod SW_PAD_CTL_PAD_GPIO_SPI_B0_07 {
25782 #[doc = "Slew Rate Field"]
25783 pub mod SRE {
25784 pub const offset: u32 = 0;
25785 pub const mask: u32 = 0x01 << offset;
25786 pub mod R {}
25787 pub mod W {}
25788 pub mod RW {
25789 #[doc = "Slow Slew Rate"]
25790 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
25791 #[doc = "Fast Slew Rate"]
25792 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
25793 }
25794 }
25795 #[doc = "Drive Strength Field"]
25796 pub mod DSE {
25797 pub const offset: u32 = 3;
25798 pub const mask: u32 = 0x07 << offset;
25799 pub mod R {}
25800 pub mod W {}
25801 pub mod RW {
25802 #[doc = "output driver disabled;"]
25803 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
25804 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
25805 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V_: u32 = 0x01;
25806 #[doc = "R0/2"]
25807 pub const DSE_2_R0_2: u32 = 0x02;
25808 #[doc = "R0/3"]
25809 pub const DSE_3_R0_3: u32 = 0x03;
25810 #[doc = "R0/4"]
25811 pub const DSE_4_R0_4: u32 = 0x04;
25812 #[doc = "R0/5"]
25813 pub const DSE_5_R0_5: u32 = 0x05;
25814 #[doc = "R0/6"]
25815 pub const DSE_6_R0_6: u32 = 0x06;
25816 #[doc = "R0/7"]
25817 pub const DSE_7_R0_7: u32 = 0x07;
25818 }
25819 }
25820 #[doc = "Speed Field"]
25821 pub mod SPEED {
25822 pub const offset: u32 = 6;
25823 pub const mask: u32 = 0x03 << offset;
25824 pub mod R {}
25825 pub mod W {}
25826 pub mod RW {
25827 #[doc = "low(50MHz)"]
25828 pub const SPEED_0_LOW_50MHZ_: u32 = 0;
25829 #[doc = "medium(100MHz)"]
25830 pub const SPEED_1_MEDIUM_100MHZ_: u32 = 0x01;
25831 #[doc = "medium(100MHz)"]
25832 pub const SPEED_2_MEDIUM_100MHZ_: u32 = 0x02;
25833 #[doc = "max(200MHz)"]
25834 pub const SPEED_3_MAX_200MHZ_: u32 = 0x03;
25835 }
25836 }
25837 #[doc = "Open Drain Enable Field"]
25838 pub mod ODE {
25839 pub const offset: u32 = 11;
25840 pub const mask: u32 = 0x01 << offset;
25841 pub mod R {}
25842 pub mod W {}
25843 pub mod RW {
25844 #[doc = "Open Drain Disabled"]
25845 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
25846 #[doc = "Open Drain Enabled"]
25847 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
25848 }
25849 }
25850 #[doc = "Pull / Keep Enable Field"]
25851 pub mod PKE {
25852 pub const offset: u32 = 12;
25853 pub const mask: u32 = 0x01 << offset;
25854 pub mod R {}
25855 pub mod W {}
25856 pub mod RW {
25857 #[doc = "Pull/Keeper Disabled"]
25858 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
25859 #[doc = "Pull/Keeper Enabled"]
25860 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
25861 }
25862 }
25863 #[doc = "Pull / Keep Select Field"]
25864 pub mod PUE {
25865 pub const offset: u32 = 13;
25866 pub const mask: u32 = 0x01 << offset;
25867 pub mod R {}
25868 pub mod W {}
25869 pub mod RW {
25870 #[doc = "Keeper"]
25871 pub const PUE_0_KEEPER: u32 = 0;
25872 #[doc = "Pull"]
25873 pub const PUE_1_PULL: u32 = 0x01;
25874 }
25875 }
25876 #[doc = "Pull Up / Down Config. Field"]
25877 pub mod PUS {
25878 pub const offset: u32 = 14;
25879 pub const mask: u32 = 0x03 << offset;
25880 pub mod R {}
25881 pub mod W {}
25882 pub mod RW {
25883 #[doc = "100K Ohm Pull Down"]
25884 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
25885 #[doc = "47K Ohm Pull Up"]
25886 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
25887 #[doc = "100K Ohm Pull Up"]
25888 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
25889 #[doc = "22K Ohm Pull Up"]
25890 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
25891 }
25892 }
25893 #[doc = "Hyst. Enable Field"]
25894 pub mod HYS {
25895 pub const offset: u32 = 16;
25896 pub const mask: u32 = 0x01 << offset;
25897 pub mod R {}
25898 pub mod W {}
25899 pub mod RW {
25900 #[doc = "Hysteresis Disabled"]
25901 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
25902 #[doc = "Hysteresis Enabled"]
25903 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
25904 }
25905 }
25906}
25907#[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B0_08 SW PAD Control Register"]
25908pub mod SW_PAD_CTL_PAD_GPIO_SPI_B0_08 {
25909 #[doc = "Slew Rate Field"]
25910 pub mod SRE {
25911 pub const offset: u32 = 0;
25912 pub const mask: u32 = 0x01 << offset;
25913 pub mod R {}
25914 pub mod W {}
25915 pub mod RW {
25916 #[doc = "Slow Slew Rate"]
25917 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
25918 #[doc = "Fast Slew Rate"]
25919 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
25920 }
25921 }
25922 #[doc = "Drive Strength Field"]
25923 pub mod DSE {
25924 pub const offset: u32 = 3;
25925 pub const mask: u32 = 0x07 << offset;
25926 pub mod R {}
25927 pub mod W {}
25928 pub mod RW {
25929 #[doc = "output driver disabled;"]
25930 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
25931 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
25932 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V_: u32 = 0x01;
25933 #[doc = "R0/2"]
25934 pub const DSE_2_R0_2: u32 = 0x02;
25935 #[doc = "R0/3"]
25936 pub const DSE_3_R0_3: u32 = 0x03;
25937 #[doc = "R0/4"]
25938 pub const DSE_4_R0_4: u32 = 0x04;
25939 #[doc = "R0/5"]
25940 pub const DSE_5_R0_5: u32 = 0x05;
25941 #[doc = "R0/6"]
25942 pub const DSE_6_R0_6: u32 = 0x06;
25943 #[doc = "R0/7"]
25944 pub const DSE_7_R0_7: u32 = 0x07;
25945 }
25946 }
25947 #[doc = "Speed Field"]
25948 pub mod SPEED {
25949 pub const offset: u32 = 6;
25950 pub const mask: u32 = 0x03 << offset;
25951 pub mod R {}
25952 pub mod W {}
25953 pub mod RW {
25954 #[doc = "low(50MHz)"]
25955 pub const SPEED_0_LOW_50MHZ_: u32 = 0;
25956 #[doc = "medium(100MHz)"]
25957 pub const SPEED_1_MEDIUM_100MHZ_: u32 = 0x01;
25958 #[doc = "medium(100MHz)"]
25959 pub const SPEED_2_MEDIUM_100MHZ_: u32 = 0x02;
25960 #[doc = "max(200MHz)"]
25961 pub const SPEED_3_MAX_200MHZ_: u32 = 0x03;
25962 }
25963 }
25964 #[doc = "Open Drain Enable Field"]
25965 pub mod ODE {
25966 pub const offset: u32 = 11;
25967 pub const mask: u32 = 0x01 << offset;
25968 pub mod R {}
25969 pub mod W {}
25970 pub mod RW {
25971 #[doc = "Open Drain Disabled"]
25972 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
25973 #[doc = "Open Drain Enabled"]
25974 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
25975 }
25976 }
25977 #[doc = "Pull / Keep Enable Field"]
25978 pub mod PKE {
25979 pub const offset: u32 = 12;
25980 pub const mask: u32 = 0x01 << offset;
25981 pub mod R {}
25982 pub mod W {}
25983 pub mod RW {
25984 #[doc = "Pull/Keeper Disabled"]
25985 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
25986 #[doc = "Pull/Keeper Enabled"]
25987 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
25988 }
25989 }
25990 #[doc = "Pull / Keep Select Field"]
25991 pub mod PUE {
25992 pub const offset: u32 = 13;
25993 pub const mask: u32 = 0x01 << offset;
25994 pub mod R {}
25995 pub mod W {}
25996 pub mod RW {
25997 #[doc = "Keeper"]
25998 pub const PUE_0_KEEPER: u32 = 0;
25999 #[doc = "Pull"]
26000 pub const PUE_1_PULL: u32 = 0x01;
26001 }
26002 }
26003 #[doc = "Pull Up / Down Config. Field"]
26004 pub mod PUS {
26005 pub const offset: u32 = 14;
26006 pub const mask: u32 = 0x03 << offset;
26007 pub mod R {}
26008 pub mod W {}
26009 pub mod RW {
26010 #[doc = "100K Ohm Pull Down"]
26011 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
26012 #[doc = "47K Ohm Pull Up"]
26013 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
26014 #[doc = "100K Ohm Pull Up"]
26015 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
26016 #[doc = "22K Ohm Pull Up"]
26017 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
26018 }
26019 }
26020 #[doc = "Hyst. Enable Field"]
26021 pub mod HYS {
26022 pub const offset: u32 = 16;
26023 pub const mask: u32 = 0x01 << offset;
26024 pub mod R {}
26025 pub mod W {}
26026 pub mod RW {
26027 #[doc = "Hysteresis Disabled"]
26028 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
26029 #[doc = "Hysteresis Enabled"]
26030 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
26031 }
26032 }
26033}
26034#[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B0_09 SW PAD Control Register"]
26035pub mod SW_PAD_CTL_PAD_GPIO_SPI_B0_09 {
26036 #[doc = "Slew Rate Field"]
26037 pub mod SRE {
26038 pub const offset: u32 = 0;
26039 pub const mask: u32 = 0x01 << offset;
26040 pub mod R {}
26041 pub mod W {}
26042 pub mod RW {
26043 #[doc = "Slow Slew Rate"]
26044 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
26045 #[doc = "Fast Slew Rate"]
26046 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
26047 }
26048 }
26049 #[doc = "Drive Strength Field"]
26050 pub mod DSE {
26051 pub const offset: u32 = 3;
26052 pub const mask: u32 = 0x07 << offset;
26053 pub mod R {}
26054 pub mod W {}
26055 pub mod RW {
26056 #[doc = "output driver disabled;"]
26057 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
26058 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
26059 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V_: u32 = 0x01;
26060 #[doc = "R0/2"]
26061 pub const DSE_2_R0_2: u32 = 0x02;
26062 #[doc = "R0/3"]
26063 pub const DSE_3_R0_3: u32 = 0x03;
26064 #[doc = "R0/4"]
26065 pub const DSE_4_R0_4: u32 = 0x04;
26066 #[doc = "R0/5"]
26067 pub const DSE_5_R0_5: u32 = 0x05;
26068 #[doc = "R0/6"]
26069 pub const DSE_6_R0_6: u32 = 0x06;
26070 #[doc = "R0/7"]
26071 pub const DSE_7_R0_7: u32 = 0x07;
26072 }
26073 }
26074 #[doc = "Speed Field"]
26075 pub mod SPEED {
26076 pub const offset: u32 = 6;
26077 pub const mask: u32 = 0x03 << offset;
26078 pub mod R {}
26079 pub mod W {}
26080 pub mod RW {
26081 #[doc = "low(50MHz)"]
26082 pub const SPEED_0_LOW_50MHZ_: u32 = 0;
26083 #[doc = "medium(100MHz)"]
26084 pub const SPEED_1_MEDIUM_100MHZ_: u32 = 0x01;
26085 #[doc = "medium(100MHz)"]
26086 pub const SPEED_2_MEDIUM_100MHZ_: u32 = 0x02;
26087 #[doc = "max(200MHz)"]
26088 pub const SPEED_3_MAX_200MHZ_: u32 = 0x03;
26089 }
26090 }
26091 #[doc = "Open Drain Enable Field"]
26092 pub mod ODE {
26093 pub const offset: u32 = 11;
26094 pub const mask: u32 = 0x01 << offset;
26095 pub mod R {}
26096 pub mod W {}
26097 pub mod RW {
26098 #[doc = "Open Drain Disabled"]
26099 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
26100 #[doc = "Open Drain Enabled"]
26101 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
26102 }
26103 }
26104 #[doc = "Pull / Keep Enable Field"]
26105 pub mod PKE {
26106 pub const offset: u32 = 12;
26107 pub const mask: u32 = 0x01 << offset;
26108 pub mod R {}
26109 pub mod W {}
26110 pub mod RW {
26111 #[doc = "Pull/Keeper Disabled"]
26112 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
26113 #[doc = "Pull/Keeper Enabled"]
26114 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
26115 }
26116 }
26117 #[doc = "Pull / Keep Select Field"]
26118 pub mod PUE {
26119 pub const offset: u32 = 13;
26120 pub const mask: u32 = 0x01 << offset;
26121 pub mod R {}
26122 pub mod W {}
26123 pub mod RW {
26124 #[doc = "Keeper"]
26125 pub const PUE_0_KEEPER: u32 = 0;
26126 #[doc = "Pull"]
26127 pub const PUE_1_PULL: u32 = 0x01;
26128 }
26129 }
26130 #[doc = "Pull Up / Down Config. Field"]
26131 pub mod PUS {
26132 pub const offset: u32 = 14;
26133 pub const mask: u32 = 0x03 << offset;
26134 pub mod R {}
26135 pub mod W {}
26136 pub mod RW {
26137 #[doc = "100K Ohm Pull Down"]
26138 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
26139 #[doc = "47K Ohm Pull Up"]
26140 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
26141 #[doc = "100K Ohm Pull Up"]
26142 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
26143 #[doc = "22K Ohm Pull Up"]
26144 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
26145 }
26146 }
26147 #[doc = "Hyst. Enable Field"]
26148 pub mod HYS {
26149 pub const offset: u32 = 16;
26150 pub const mask: u32 = 0x01 << offset;
26151 pub mod R {}
26152 pub mod W {}
26153 pub mod RW {
26154 #[doc = "Hysteresis Disabled"]
26155 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
26156 #[doc = "Hysteresis Enabled"]
26157 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
26158 }
26159 }
26160}
26161#[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B0_10 SW PAD Control Register"]
26162pub mod SW_PAD_CTL_PAD_GPIO_SPI_B0_10 {
26163 #[doc = "Slew Rate Field"]
26164 pub mod SRE {
26165 pub const offset: u32 = 0;
26166 pub const mask: u32 = 0x01 << offset;
26167 pub mod R {}
26168 pub mod W {}
26169 pub mod RW {
26170 #[doc = "Slow Slew Rate"]
26171 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
26172 #[doc = "Fast Slew Rate"]
26173 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
26174 }
26175 }
26176 #[doc = "Drive Strength Field"]
26177 pub mod DSE {
26178 pub const offset: u32 = 3;
26179 pub const mask: u32 = 0x07 << offset;
26180 pub mod R {}
26181 pub mod W {}
26182 pub mod RW {
26183 #[doc = "output driver disabled;"]
26184 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
26185 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
26186 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V_: u32 = 0x01;
26187 #[doc = "R0/2"]
26188 pub const DSE_2_R0_2: u32 = 0x02;
26189 #[doc = "R0/3"]
26190 pub const DSE_3_R0_3: u32 = 0x03;
26191 #[doc = "R0/4"]
26192 pub const DSE_4_R0_4: u32 = 0x04;
26193 #[doc = "R0/5"]
26194 pub const DSE_5_R0_5: u32 = 0x05;
26195 #[doc = "R0/6"]
26196 pub const DSE_6_R0_6: u32 = 0x06;
26197 #[doc = "R0/7"]
26198 pub const DSE_7_R0_7: u32 = 0x07;
26199 }
26200 }
26201 #[doc = "Speed Field"]
26202 pub mod SPEED {
26203 pub const offset: u32 = 6;
26204 pub const mask: u32 = 0x03 << offset;
26205 pub mod R {}
26206 pub mod W {}
26207 pub mod RW {
26208 #[doc = "low(50MHz)"]
26209 pub const SPEED_0_LOW_50MHZ_: u32 = 0;
26210 #[doc = "medium(100MHz)"]
26211 pub const SPEED_1_MEDIUM_100MHZ_: u32 = 0x01;
26212 #[doc = "medium(100MHz)"]
26213 pub const SPEED_2_MEDIUM_100MHZ_: u32 = 0x02;
26214 #[doc = "max(200MHz)"]
26215 pub const SPEED_3_MAX_200MHZ_: u32 = 0x03;
26216 }
26217 }
26218 #[doc = "Open Drain Enable Field"]
26219 pub mod ODE {
26220 pub const offset: u32 = 11;
26221 pub const mask: u32 = 0x01 << offset;
26222 pub mod R {}
26223 pub mod W {}
26224 pub mod RW {
26225 #[doc = "Open Drain Disabled"]
26226 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
26227 #[doc = "Open Drain Enabled"]
26228 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
26229 }
26230 }
26231 #[doc = "Pull / Keep Enable Field"]
26232 pub mod PKE {
26233 pub const offset: u32 = 12;
26234 pub const mask: u32 = 0x01 << offset;
26235 pub mod R {}
26236 pub mod W {}
26237 pub mod RW {
26238 #[doc = "Pull/Keeper Disabled"]
26239 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
26240 #[doc = "Pull/Keeper Enabled"]
26241 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
26242 }
26243 }
26244 #[doc = "Pull / Keep Select Field"]
26245 pub mod PUE {
26246 pub const offset: u32 = 13;
26247 pub const mask: u32 = 0x01 << offset;
26248 pub mod R {}
26249 pub mod W {}
26250 pub mod RW {
26251 #[doc = "Keeper"]
26252 pub const PUE_0_KEEPER: u32 = 0;
26253 #[doc = "Pull"]
26254 pub const PUE_1_PULL: u32 = 0x01;
26255 }
26256 }
26257 #[doc = "Pull Up / Down Config. Field"]
26258 pub mod PUS {
26259 pub const offset: u32 = 14;
26260 pub const mask: u32 = 0x03 << offset;
26261 pub mod R {}
26262 pub mod W {}
26263 pub mod RW {
26264 #[doc = "100K Ohm Pull Down"]
26265 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
26266 #[doc = "47K Ohm Pull Up"]
26267 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
26268 #[doc = "100K Ohm Pull Up"]
26269 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
26270 #[doc = "22K Ohm Pull Up"]
26271 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
26272 }
26273 }
26274 #[doc = "Hyst. Enable Field"]
26275 pub mod HYS {
26276 pub const offset: u32 = 16;
26277 pub const mask: u32 = 0x01 << offset;
26278 pub mod R {}
26279 pub mod W {}
26280 pub mod RW {
26281 #[doc = "Hysteresis Disabled"]
26282 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
26283 #[doc = "Hysteresis Enabled"]
26284 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
26285 }
26286 }
26287}
26288#[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B0_11 SW PAD Control Register"]
26289pub mod SW_PAD_CTL_PAD_GPIO_SPI_B0_11 {
26290 #[doc = "Slew Rate Field"]
26291 pub mod SRE {
26292 pub const offset: u32 = 0;
26293 pub const mask: u32 = 0x01 << offset;
26294 pub mod R {}
26295 pub mod W {}
26296 pub mod RW {
26297 #[doc = "Slow Slew Rate"]
26298 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
26299 #[doc = "Fast Slew Rate"]
26300 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
26301 }
26302 }
26303 #[doc = "Drive Strength Field"]
26304 pub mod DSE {
26305 pub const offset: u32 = 3;
26306 pub const mask: u32 = 0x07 << offset;
26307 pub mod R {}
26308 pub mod W {}
26309 pub mod RW {
26310 #[doc = "output driver disabled;"]
26311 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
26312 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
26313 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V_: u32 = 0x01;
26314 #[doc = "R0/2"]
26315 pub const DSE_2_R0_2: u32 = 0x02;
26316 #[doc = "R0/3"]
26317 pub const DSE_3_R0_3: u32 = 0x03;
26318 #[doc = "R0/4"]
26319 pub const DSE_4_R0_4: u32 = 0x04;
26320 #[doc = "R0/5"]
26321 pub const DSE_5_R0_5: u32 = 0x05;
26322 #[doc = "R0/6"]
26323 pub const DSE_6_R0_6: u32 = 0x06;
26324 #[doc = "R0/7"]
26325 pub const DSE_7_R0_7: u32 = 0x07;
26326 }
26327 }
26328 #[doc = "Speed Field"]
26329 pub mod SPEED {
26330 pub const offset: u32 = 6;
26331 pub const mask: u32 = 0x03 << offset;
26332 pub mod R {}
26333 pub mod W {}
26334 pub mod RW {
26335 #[doc = "low(50MHz)"]
26336 pub const SPEED_0_LOW_50MHZ_: u32 = 0;
26337 #[doc = "medium(100MHz)"]
26338 pub const SPEED_1_MEDIUM_100MHZ_: u32 = 0x01;
26339 #[doc = "medium(100MHz)"]
26340 pub const SPEED_2_MEDIUM_100MHZ_: u32 = 0x02;
26341 #[doc = "max(200MHz)"]
26342 pub const SPEED_3_MAX_200MHZ_: u32 = 0x03;
26343 }
26344 }
26345 #[doc = "Open Drain Enable Field"]
26346 pub mod ODE {
26347 pub const offset: u32 = 11;
26348 pub const mask: u32 = 0x01 << offset;
26349 pub mod R {}
26350 pub mod W {}
26351 pub mod RW {
26352 #[doc = "Open Drain Disabled"]
26353 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
26354 #[doc = "Open Drain Enabled"]
26355 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
26356 }
26357 }
26358 #[doc = "Pull / Keep Enable Field"]
26359 pub mod PKE {
26360 pub const offset: u32 = 12;
26361 pub const mask: u32 = 0x01 << offset;
26362 pub mod R {}
26363 pub mod W {}
26364 pub mod RW {
26365 #[doc = "Pull/Keeper Disabled"]
26366 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
26367 #[doc = "Pull/Keeper Enabled"]
26368 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
26369 }
26370 }
26371 #[doc = "Pull / Keep Select Field"]
26372 pub mod PUE {
26373 pub const offset: u32 = 13;
26374 pub const mask: u32 = 0x01 << offset;
26375 pub mod R {}
26376 pub mod W {}
26377 pub mod RW {
26378 #[doc = "Keeper"]
26379 pub const PUE_0_KEEPER: u32 = 0;
26380 #[doc = "Pull"]
26381 pub const PUE_1_PULL: u32 = 0x01;
26382 }
26383 }
26384 #[doc = "Pull Up / Down Config. Field"]
26385 pub mod PUS {
26386 pub const offset: u32 = 14;
26387 pub const mask: u32 = 0x03 << offset;
26388 pub mod R {}
26389 pub mod W {}
26390 pub mod RW {
26391 #[doc = "100K Ohm Pull Down"]
26392 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
26393 #[doc = "47K Ohm Pull Up"]
26394 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
26395 #[doc = "100K Ohm Pull Up"]
26396 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
26397 #[doc = "22K Ohm Pull Up"]
26398 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
26399 }
26400 }
26401 #[doc = "Hyst. Enable Field"]
26402 pub mod HYS {
26403 pub const offset: u32 = 16;
26404 pub const mask: u32 = 0x01 << offset;
26405 pub mod R {}
26406 pub mod W {}
26407 pub mod RW {
26408 #[doc = "Hysteresis Disabled"]
26409 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
26410 #[doc = "Hysteresis Enabled"]
26411 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
26412 }
26413 }
26414}
26415#[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B0_12 SW PAD Control Register"]
26416pub mod SW_PAD_CTL_PAD_GPIO_SPI_B0_12 {
26417 #[doc = "Slew Rate Field"]
26418 pub mod SRE {
26419 pub const offset: u32 = 0;
26420 pub const mask: u32 = 0x01 << offset;
26421 pub mod R {}
26422 pub mod W {}
26423 pub mod RW {
26424 #[doc = "Slow Slew Rate"]
26425 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
26426 #[doc = "Fast Slew Rate"]
26427 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
26428 }
26429 }
26430 #[doc = "Drive Strength Field"]
26431 pub mod DSE {
26432 pub const offset: u32 = 3;
26433 pub const mask: u32 = 0x07 << offset;
26434 pub mod R {}
26435 pub mod W {}
26436 pub mod RW {
26437 #[doc = "output driver disabled;"]
26438 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
26439 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
26440 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V_: u32 = 0x01;
26441 #[doc = "R0/2"]
26442 pub const DSE_2_R0_2: u32 = 0x02;
26443 #[doc = "R0/3"]
26444 pub const DSE_3_R0_3: u32 = 0x03;
26445 #[doc = "R0/4"]
26446 pub const DSE_4_R0_4: u32 = 0x04;
26447 #[doc = "R0/5"]
26448 pub const DSE_5_R0_5: u32 = 0x05;
26449 #[doc = "R0/6"]
26450 pub const DSE_6_R0_6: u32 = 0x06;
26451 #[doc = "R0/7"]
26452 pub const DSE_7_R0_7: u32 = 0x07;
26453 }
26454 }
26455 #[doc = "Speed Field"]
26456 pub mod SPEED {
26457 pub const offset: u32 = 6;
26458 pub const mask: u32 = 0x03 << offset;
26459 pub mod R {}
26460 pub mod W {}
26461 pub mod RW {
26462 #[doc = "low(50MHz)"]
26463 pub const SPEED_0_LOW_50MHZ_: u32 = 0;
26464 #[doc = "medium(100MHz)"]
26465 pub const SPEED_1_MEDIUM_100MHZ_: u32 = 0x01;
26466 #[doc = "medium(100MHz)"]
26467 pub const SPEED_2_MEDIUM_100MHZ_: u32 = 0x02;
26468 #[doc = "max(200MHz)"]
26469 pub const SPEED_3_MAX_200MHZ_: u32 = 0x03;
26470 }
26471 }
26472 #[doc = "Open Drain Enable Field"]
26473 pub mod ODE {
26474 pub const offset: u32 = 11;
26475 pub const mask: u32 = 0x01 << offset;
26476 pub mod R {}
26477 pub mod W {}
26478 pub mod RW {
26479 #[doc = "Open Drain Disabled"]
26480 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
26481 #[doc = "Open Drain Enabled"]
26482 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
26483 }
26484 }
26485 #[doc = "Pull / Keep Enable Field"]
26486 pub mod PKE {
26487 pub const offset: u32 = 12;
26488 pub const mask: u32 = 0x01 << offset;
26489 pub mod R {}
26490 pub mod W {}
26491 pub mod RW {
26492 #[doc = "Pull/Keeper Disabled"]
26493 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
26494 #[doc = "Pull/Keeper Enabled"]
26495 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
26496 }
26497 }
26498 #[doc = "Pull / Keep Select Field"]
26499 pub mod PUE {
26500 pub const offset: u32 = 13;
26501 pub const mask: u32 = 0x01 << offset;
26502 pub mod R {}
26503 pub mod W {}
26504 pub mod RW {
26505 #[doc = "Keeper"]
26506 pub const PUE_0_KEEPER: u32 = 0;
26507 #[doc = "Pull"]
26508 pub const PUE_1_PULL: u32 = 0x01;
26509 }
26510 }
26511 #[doc = "Pull Up / Down Config. Field"]
26512 pub mod PUS {
26513 pub const offset: u32 = 14;
26514 pub const mask: u32 = 0x03 << offset;
26515 pub mod R {}
26516 pub mod W {}
26517 pub mod RW {
26518 #[doc = "100K Ohm Pull Down"]
26519 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
26520 #[doc = "47K Ohm Pull Up"]
26521 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
26522 #[doc = "100K Ohm Pull Up"]
26523 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
26524 #[doc = "22K Ohm Pull Up"]
26525 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
26526 }
26527 }
26528 #[doc = "Hyst. Enable Field"]
26529 pub mod HYS {
26530 pub const offset: u32 = 16;
26531 pub const mask: u32 = 0x01 << offset;
26532 pub mod R {}
26533 pub mod W {}
26534 pub mod RW {
26535 #[doc = "Hysteresis Disabled"]
26536 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
26537 #[doc = "Hysteresis Enabled"]
26538 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
26539 }
26540 }
26541}
26542#[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B0_13 SW PAD Control Register"]
26543pub mod SW_PAD_CTL_PAD_GPIO_SPI_B0_13 {
26544 #[doc = "Slew Rate Field"]
26545 pub mod SRE {
26546 pub const offset: u32 = 0;
26547 pub const mask: u32 = 0x01 << offset;
26548 pub mod R {}
26549 pub mod W {}
26550 pub mod RW {
26551 #[doc = "Slow Slew Rate"]
26552 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
26553 #[doc = "Fast Slew Rate"]
26554 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
26555 }
26556 }
26557 #[doc = "Drive Strength Field"]
26558 pub mod DSE {
26559 pub const offset: u32 = 3;
26560 pub const mask: u32 = 0x07 << offset;
26561 pub mod R {}
26562 pub mod W {}
26563 pub mod RW {
26564 #[doc = "output driver disabled;"]
26565 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
26566 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
26567 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V_: u32 = 0x01;
26568 #[doc = "R0/2"]
26569 pub const DSE_2_R0_2: u32 = 0x02;
26570 #[doc = "R0/3"]
26571 pub const DSE_3_R0_3: u32 = 0x03;
26572 #[doc = "R0/4"]
26573 pub const DSE_4_R0_4: u32 = 0x04;
26574 #[doc = "R0/5"]
26575 pub const DSE_5_R0_5: u32 = 0x05;
26576 #[doc = "R0/6"]
26577 pub const DSE_6_R0_6: u32 = 0x06;
26578 #[doc = "R0/7"]
26579 pub const DSE_7_R0_7: u32 = 0x07;
26580 }
26581 }
26582 #[doc = "Speed Field"]
26583 pub mod SPEED {
26584 pub const offset: u32 = 6;
26585 pub const mask: u32 = 0x03 << offset;
26586 pub mod R {}
26587 pub mod W {}
26588 pub mod RW {
26589 #[doc = "low(50MHz)"]
26590 pub const SPEED_0_LOW_50MHZ_: u32 = 0;
26591 #[doc = "medium(100MHz)"]
26592 pub const SPEED_1_MEDIUM_100MHZ_: u32 = 0x01;
26593 #[doc = "medium(100MHz)"]
26594 pub const SPEED_2_MEDIUM_100MHZ_: u32 = 0x02;
26595 #[doc = "max(200MHz)"]
26596 pub const SPEED_3_MAX_200MHZ_: u32 = 0x03;
26597 }
26598 }
26599 #[doc = "Open Drain Enable Field"]
26600 pub mod ODE {
26601 pub const offset: u32 = 11;
26602 pub const mask: u32 = 0x01 << offset;
26603 pub mod R {}
26604 pub mod W {}
26605 pub mod RW {
26606 #[doc = "Open Drain Disabled"]
26607 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
26608 #[doc = "Open Drain Enabled"]
26609 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
26610 }
26611 }
26612 #[doc = "Pull / Keep Enable Field"]
26613 pub mod PKE {
26614 pub const offset: u32 = 12;
26615 pub const mask: u32 = 0x01 << offset;
26616 pub mod R {}
26617 pub mod W {}
26618 pub mod RW {
26619 #[doc = "Pull/Keeper Disabled"]
26620 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
26621 #[doc = "Pull/Keeper Enabled"]
26622 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
26623 }
26624 }
26625 #[doc = "Pull / Keep Select Field"]
26626 pub mod PUE {
26627 pub const offset: u32 = 13;
26628 pub const mask: u32 = 0x01 << offset;
26629 pub mod R {}
26630 pub mod W {}
26631 pub mod RW {
26632 #[doc = "Keeper"]
26633 pub const PUE_0_KEEPER: u32 = 0;
26634 #[doc = "Pull"]
26635 pub const PUE_1_PULL: u32 = 0x01;
26636 }
26637 }
26638 #[doc = "Pull Up / Down Config. Field"]
26639 pub mod PUS {
26640 pub const offset: u32 = 14;
26641 pub const mask: u32 = 0x03 << offset;
26642 pub mod R {}
26643 pub mod W {}
26644 pub mod RW {
26645 #[doc = "100K Ohm Pull Down"]
26646 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
26647 #[doc = "47K Ohm Pull Up"]
26648 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
26649 #[doc = "100K Ohm Pull Up"]
26650 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
26651 #[doc = "22K Ohm Pull Up"]
26652 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
26653 }
26654 }
26655 #[doc = "Hyst. Enable Field"]
26656 pub mod HYS {
26657 pub const offset: u32 = 16;
26658 pub const mask: u32 = 0x01 << offset;
26659 pub mod R {}
26660 pub mod W {}
26661 pub mod RW {
26662 #[doc = "Hysteresis Disabled"]
26663 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
26664 #[doc = "Hysteresis Enabled"]
26665 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
26666 }
26667 }
26668}
26669#[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B1_00 SW PAD Control Register"]
26670pub mod SW_PAD_CTL_PAD_GPIO_SPI_B1_00 {
26671 #[doc = "Slew Rate Field"]
26672 pub mod SRE {
26673 pub const offset: u32 = 0;
26674 pub const mask: u32 = 0x01 << offset;
26675 pub mod R {}
26676 pub mod W {}
26677 pub mod RW {
26678 #[doc = "Slow Slew Rate"]
26679 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
26680 #[doc = "Fast Slew Rate"]
26681 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
26682 }
26683 }
26684 #[doc = "Drive Strength Field"]
26685 pub mod DSE {
26686 pub const offset: u32 = 3;
26687 pub const mask: u32 = 0x07 << offset;
26688 pub mod R {}
26689 pub mod W {}
26690 pub mod RW {
26691 #[doc = "output driver disabled;"]
26692 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
26693 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
26694 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V_: u32 = 0x01;
26695 #[doc = "R0/2"]
26696 pub const DSE_2_R0_2: u32 = 0x02;
26697 #[doc = "R0/3"]
26698 pub const DSE_3_R0_3: u32 = 0x03;
26699 #[doc = "R0/4"]
26700 pub const DSE_4_R0_4: u32 = 0x04;
26701 #[doc = "R0/5"]
26702 pub const DSE_5_R0_5: u32 = 0x05;
26703 #[doc = "R0/6"]
26704 pub const DSE_6_R0_6: u32 = 0x06;
26705 #[doc = "R0/7"]
26706 pub const DSE_7_R0_7: u32 = 0x07;
26707 }
26708 }
26709 #[doc = "Speed Field"]
26710 pub mod SPEED {
26711 pub const offset: u32 = 6;
26712 pub const mask: u32 = 0x03 << offset;
26713 pub mod R {}
26714 pub mod W {}
26715 pub mod RW {
26716 #[doc = "low(50MHz)"]
26717 pub const SPEED_0_LOW_50MHZ_: u32 = 0;
26718 #[doc = "medium(100MHz)"]
26719 pub const SPEED_1_MEDIUM_100MHZ_: u32 = 0x01;
26720 #[doc = "medium(100MHz)"]
26721 pub const SPEED_2_MEDIUM_100MHZ_: u32 = 0x02;
26722 #[doc = "max(200MHz)"]
26723 pub const SPEED_3_MAX_200MHZ_: u32 = 0x03;
26724 }
26725 }
26726 #[doc = "Open Drain Enable Field"]
26727 pub mod ODE {
26728 pub const offset: u32 = 11;
26729 pub const mask: u32 = 0x01 << offset;
26730 pub mod R {}
26731 pub mod W {}
26732 pub mod RW {
26733 #[doc = "Open Drain Disabled"]
26734 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
26735 #[doc = "Open Drain Enabled"]
26736 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
26737 }
26738 }
26739 #[doc = "Pull / Keep Enable Field"]
26740 pub mod PKE {
26741 pub const offset: u32 = 12;
26742 pub const mask: u32 = 0x01 << offset;
26743 pub mod R {}
26744 pub mod W {}
26745 pub mod RW {
26746 #[doc = "Pull/Keeper Disabled"]
26747 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
26748 #[doc = "Pull/Keeper Enabled"]
26749 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
26750 }
26751 }
26752 #[doc = "Pull / Keep Select Field"]
26753 pub mod PUE {
26754 pub const offset: u32 = 13;
26755 pub const mask: u32 = 0x01 << offset;
26756 pub mod R {}
26757 pub mod W {}
26758 pub mod RW {
26759 #[doc = "Keeper"]
26760 pub const PUE_0_KEEPER: u32 = 0;
26761 #[doc = "Pull"]
26762 pub const PUE_1_PULL: u32 = 0x01;
26763 }
26764 }
26765 #[doc = "Pull Up / Down Config. Field"]
26766 pub mod PUS {
26767 pub const offset: u32 = 14;
26768 pub const mask: u32 = 0x03 << offset;
26769 pub mod R {}
26770 pub mod W {}
26771 pub mod RW {
26772 #[doc = "100K Ohm Pull Down"]
26773 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
26774 #[doc = "47K Ohm Pull Up"]
26775 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
26776 #[doc = "100K Ohm Pull Up"]
26777 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
26778 #[doc = "22K Ohm Pull Up"]
26779 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
26780 }
26781 }
26782 #[doc = "Hyst. Enable Field"]
26783 pub mod HYS {
26784 pub const offset: u32 = 16;
26785 pub const mask: u32 = 0x01 << offset;
26786 pub mod R {}
26787 pub mod W {}
26788 pub mod RW {
26789 #[doc = "Hysteresis Disabled"]
26790 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
26791 #[doc = "Hysteresis Enabled"]
26792 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
26793 }
26794 }
26795}
26796#[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B1_01 SW PAD Control Register"]
26797pub mod SW_PAD_CTL_PAD_GPIO_SPI_B1_01 {
26798 #[doc = "Slew Rate Field"]
26799 pub mod SRE {
26800 pub const offset: u32 = 0;
26801 pub const mask: u32 = 0x01 << offset;
26802 pub mod R {}
26803 pub mod W {}
26804 pub mod RW {
26805 #[doc = "Slow Slew Rate"]
26806 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
26807 #[doc = "Fast Slew Rate"]
26808 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
26809 }
26810 }
26811 #[doc = "Drive Strength Field"]
26812 pub mod DSE {
26813 pub const offset: u32 = 3;
26814 pub const mask: u32 = 0x07 << offset;
26815 pub mod R {}
26816 pub mod W {}
26817 pub mod RW {
26818 #[doc = "output driver disabled;"]
26819 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
26820 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
26821 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V_: u32 = 0x01;
26822 #[doc = "R0/2"]
26823 pub const DSE_2_R0_2: u32 = 0x02;
26824 #[doc = "R0/3"]
26825 pub const DSE_3_R0_3: u32 = 0x03;
26826 #[doc = "R0/4"]
26827 pub const DSE_4_R0_4: u32 = 0x04;
26828 #[doc = "R0/5"]
26829 pub const DSE_5_R0_5: u32 = 0x05;
26830 #[doc = "R0/6"]
26831 pub const DSE_6_R0_6: u32 = 0x06;
26832 #[doc = "R0/7"]
26833 pub const DSE_7_R0_7: u32 = 0x07;
26834 }
26835 }
26836 #[doc = "Speed Field"]
26837 pub mod SPEED {
26838 pub const offset: u32 = 6;
26839 pub const mask: u32 = 0x03 << offset;
26840 pub mod R {}
26841 pub mod W {}
26842 pub mod RW {
26843 #[doc = "low(50MHz)"]
26844 pub const SPEED_0_LOW_50MHZ_: u32 = 0;
26845 #[doc = "medium(100MHz)"]
26846 pub const SPEED_1_MEDIUM_100MHZ_: u32 = 0x01;
26847 #[doc = "medium(100MHz)"]
26848 pub const SPEED_2_MEDIUM_100MHZ_: u32 = 0x02;
26849 #[doc = "max(200MHz)"]
26850 pub const SPEED_3_MAX_200MHZ_: u32 = 0x03;
26851 }
26852 }
26853 #[doc = "Open Drain Enable Field"]
26854 pub mod ODE {
26855 pub const offset: u32 = 11;
26856 pub const mask: u32 = 0x01 << offset;
26857 pub mod R {}
26858 pub mod W {}
26859 pub mod RW {
26860 #[doc = "Open Drain Disabled"]
26861 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
26862 #[doc = "Open Drain Enabled"]
26863 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
26864 }
26865 }
26866 #[doc = "Pull / Keep Enable Field"]
26867 pub mod PKE {
26868 pub const offset: u32 = 12;
26869 pub const mask: u32 = 0x01 << offset;
26870 pub mod R {}
26871 pub mod W {}
26872 pub mod RW {
26873 #[doc = "Pull/Keeper Disabled"]
26874 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
26875 #[doc = "Pull/Keeper Enabled"]
26876 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
26877 }
26878 }
26879 #[doc = "Pull / Keep Select Field"]
26880 pub mod PUE {
26881 pub const offset: u32 = 13;
26882 pub const mask: u32 = 0x01 << offset;
26883 pub mod R {}
26884 pub mod W {}
26885 pub mod RW {
26886 #[doc = "Keeper"]
26887 pub const PUE_0_KEEPER: u32 = 0;
26888 #[doc = "Pull"]
26889 pub const PUE_1_PULL: u32 = 0x01;
26890 }
26891 }
26892 #[doc = "Pull Up / Down Config. Field"]
26893 pub mod PUS {
26894 pub const offset: u32 = 14;
26895 pub const mask: u32 = 0x03 << offset;
26896 pub mod R {}
26897 pub mod W {}
26898 pub mod RW {
26899 #[doc = "100K Ohm Pull Down"]
26900 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
26901 #[doc = "47K Ohm Pull Up"]
26902 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
26903 #[doc = "100K Ohm Pull Up"]
26904 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
26905 #[doc = "22K Ohm Pull Up"]
26906 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
26907 }
26908 }
26909 #[doc = "Hyst. Enable Field"]
26910 pub mod HYS {
26911 pub const offset: u32 = 16;
26912 pub const mask: u32 = 0x01 << offset;
26913 pub mod R {}
26914 pub mod W {}
26915 pub mod RW {
26916 #[doc = "Hysteresis Disabled"]
26917 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
26918 #[doc = "Hysteresis Enabled"]
26919 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
26920 }
26921 }
26922}
26923#[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B1_02 SW PAD Control Register"]
26924pub mod SW_PAD_CTL_PAD_GPIO_SPI_B1_02 {
26925 #[doc = "Slew Rate Field"]
26926 pub mod SRE {
26927 pub const offset: u32 = 0;
26928 pub const mask: u32 = 0x01 << offset;
26929 pub mod R {}
26930 pub mod W {}
26931 pub mod RW {
26932 #[doc = "Slow Slew Rate"]
26933 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
26934 #[doc = "Fast Slew Rate"]
26935 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
26936 }
26937 }
26938 #[doc = "Drive Strength Field"]
26939 pub mod DSE {
26940 pub const offset: u32 = 3;
26941 pub const mask: u32 = 0x07 << offset;
26942 pub mod R {}
26943 pub mod W {}
26944 pub mod RW {
26945 #[doc = "output driver disabled;"]
26946 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
26947 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
26948 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V_: u32 = 0x01;
26949 #[doc = "R0/2"]
26950 pub const DSE_2_R0_2: u32 = 0x02;
26951 #[doc = "R0/3"]
26952 pub const DSE_3_R0_3: u32 = 0x03;
26953 #[doc = "R0/4"]
26954 pub const DSE_4_R0_4: u32 = 0x04;
26955 #[doc = "R0/5"]
26956 pub const DSE_5_R0_5: u32 = 0x05;
26957 #[doc = "R0/6"]
26958 pub const DSE_6_R0_6: u32 = 0x06;
26959 #[doc = "R0/7"]
26960 pub const DSE_7_R0_7: u32 = 0x07;
26961 }
26962 }
26963 #[doc = "Speed Field"]
26964 pub mod SPEED {
26965 pub const offset: u32 = 6;
26966 pub const mask: u32 = 0x03 << offset;
26967 pub mod R {}
26968 pub mod W {}
26969 pub mod RW {
26970 #[doc = "low(50MHz)"]
26971 pub const SPEED_0_LOW_50MHZ_: u32 = 0;
26972 #[doc = "medium(100MHz)"]
26973 pub const SPEED_1_MEDIUM_100MHZ_: u32 = 0x01;
26974 #[doc = "medium(100MHz)"]
26975 pub const SPEED_2_MEDIUM_100MHZ_: u32 = 0x02;
26976 #[doc = "max(200MHz)"]
26977 pub const SPEED_3_MAX_200MHZ_: u32 = 0x03;
26978 }
26979 }
26980 #[doc = "Open Drain Enable Field"]
26981 pub mod ODE {
26982 pub const offset: u32 = 11;
26983 pub const mask: u32 = 0x01 << offset;
26984 pub mod R {}
26985 pub mod W {}
26986 pub mod RW {
26987 #[doc = "Open Drain Disabled"]
26988 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
26989 #[doc = "Open Drain Enabled"]
26990 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
26991 }
26992 }
26993 #[doc = "Pull / Keep Enable Field"]
26994 pub mod PKE {
26995 pub const offset: u32 = 12;
26996 pub const mask: u32 = 0x01 << offset;
26997 pub mod R {}
26998 pub mod W {}
26999 pub mod RW {
27000 #[doc = "Pull/Keeper Disabled"]
27001 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
27002 #[doc = "Pull/Keeper Enabled"]
27003 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
27004 }
27005 }
27006 #[doc = "Pull / Keep Select Field"]
27007 pub mod PUE {
27008 pub const offset: u32 = 13;
27009 pub const mask: u32 = 0x01 << offset;
27010 pub mod R {}
27011 pub mod W {}
27012 pub mod RW {
27013 #[doc = "Keeper"]
27014 pub const PUE_0_KEEPER: u32 = 0;
27015 #[doc = "Pull"]
27016 pub const PUE_1_PULL: u32 = 0x01;
27017 }
27018 }
27019 #[doc = "Pull Up / Down Config. Field"]
27020 pub mod PUS {
27021 pub const offset: u32 = 14;
27022 pub const mask: u32 = 0x03 << offset;
27023 pub mod R {}
27024 pub mod W {}
27025 pub mod RW {
27026 #[doc = "100K Ohm Pull Down"]
27027 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
27028 #[doc = "47K Ohm Pull Up"]
27029 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
27030 #[doc = "100K Ohm Pull Up"]
27031 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
27032 #[doc = "22K Ohm Pull Up"]
27033 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
27034 }
27035 }
27036 #[doc = "Hyst. Enable Field"]
27037 pub mod HYS {
27038 pub const offset: u32 = 16;
27039 pub const mask: u32 = 0x01 << offset;
27040 pub mod R {}
27041 pub mod W {}
27042 pub mod RW {
27043 #[doc = "Hysteresis Disabled"]
27044 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
27045 #[doc = "Hysteresis Enabled"]
27046 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
27047 }
27048 }
27049}
27050#[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B1_03 SW PAD Control Register"]
27051pub mod SW_PAD_CTL_PAD_GPIO_SPI_B1_03 {
27052 #[doc = "Slew Rate Field"]
27053 pub mod SRE {
27054 pub const offset: u32 = 0;
27055 pub const mask: u32 = 0x01 << offset;
27056 pub mod R {}
27057 pub mod W {}
27058 pub mod RW {
27059 #[doc = "Slow Slew Rate"]
27060 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
27061 #[doc = "Fast Slew Rate"]
27062 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
27063 }
27064 }
27065 #[doc = "Drive Strength Field"]
27066 pub mod DSE {
27067 pub const offset: u32 = 3;
27068 pub const mask: u32 = 0x07 << offset;
27069 pub mod R {}
27070 pub mod W {}
27071 pub mod RW {
27072 #[doc = "output driver disabled;"]
27073 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
27074 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
27075 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V_: u32 = 0x01;
27076 #[doc = "R0/2"]
27077 pub const DSE_2_R0_2: u32 = 0x02;
27078 #[doc = "R0/3"]
27079 pub const DSE_3_R0_3: u32 = 0x03;
27080 #[doc = "R0/4"]
27081 pub const DSE_4_R0_4: u32 = 0x04;
27082 #[doc = "R0/5"]
27083 pub const DSE_5_R0_5: u32 = 0x05;
27084 #[doc = "R0/6"]
27085 pub const DSE_6_R0_6: u32 = 0x06;
27086 #[doc = "R0/7"]
27087 pub const DSE_7_R0_7: u32 = 0x07;
27088 }
27089 }
27090 #[doc = "Speed Field"]
27091 pub mod SPEED {
27092 pub const offset: u32 = 6;
27093 pub const mask: u32 = 0x03 << offset;
27094 pub mod R {}
27095 pub mod W {}
27096 pub mod RW {
27097 #[doc = "low(50MHz)"]
27098 pub const SPEED_0_LOW_50MHZ_: u32 = 0;
27099 #[doc = "medium(100MHz)"]
27100 pub const SPEED_1_MEDIUM_100MHZ_: u32 = 0x01;
27101 #[doc = "medium(100MHz)"]
27102 pub const SPEED_2_MEDIUM_100MHZ_: u32 = 0x02;
27103 #[doc = "max(200MHz)"]
27104 pub const SPEED_3_MAX_200MHZ_: u32 = 0x03;
27105 }
27106 }
27107 #[doc = "Open Drain Enable Field"]
27108 pub mod ODE {
27109 pub const offset: u32 = 11;
27110 pub const mask: u32 = 0x01 << offset;
27111 pub mod R {}
27112 pub mod W {}
27113 pub mod RW {
27114 #[doc = "Open Drain Disabled"]
27115 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
27116 #[doc = "Open Drain Enabled"]
27117 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
27118 }
27119 }
27120 #[doc = "Pull / Keep Enable Field"]
27121 pub mod PKE {
27122 pub const offset: u32 = 12;
27123 pub const mask: u32 = 0x01 << offset;
27124 pub mod R {}
27125 pub mod W {}
27126 pub mod RW {
27127 #[doc = "Pull/Keeper Disabled"]
27128 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
27129 #[doc = "Pull/Keeper Enabled"]
27130 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
27131 }
27132 }
27133 #[doc = "Pull / Keep Select Field"]
27134 pub mod PUE {
27135 pub const offset: u32 = 13;
27136 pub const mask: u32 = 0x01 << offset;
27137 pub mod R {}
27138 pub mod W {}
27139 pub mod RW {
27140 #[doc = "Keeper"]
27141 pub const PUE_0_KEEPER: u32 = 0;
27142 #[doc = "Pull"]
27143 pub const PUE_1_PULL: u32 = 0x01;
27144 }
27145 }
27146 #[doc = "Pull Up / Down Config. Field"]
27147 pub mod PUS {
27148 pub const offset: u32 = 14;
27149 pub const mask: u32 = 0x03 << offset;
27150 pub mod R {}
27151 pub mod W {}
27152 pub mod RW {
27153 #[doc = "100K Ohm Pull Down"]
27154 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
27155 #[doc = "47K Ohm Pull Up"]
27156 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
27157 #[doc = "100K Ohm Pull Up"]
27158 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
27159 #[doc = "22K Ohm Pull Up"]
27160 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
27161 }
27162 }
27163 #[doc = "Hyst. Enable Field"]
27164 pub mod HYS {
27165 pub const offset: u32 = 16;
27166 pub const mask: u32 = 0x01 << offset;
27167 pub mod R {}
27168 pub mod W {}
27169 pub mod RW {
27170 #[doc = "Hysteresis Disabled"]
27171 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
27172 #[doc = "Hysteresis Enabled"]
27173 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
27174 }
27175 }
27176}
27177#[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B1_04 SW PAD Control Register"]
27178pub mod SW_PAD_CTL_PAD_GPIO_SPI_B1_04 {
27179 #[doc = "Slew Rate Field"]
27180 pub mod SRE {
27181 pub const offset: u32 = 0;
27182 pub const mask: u32 = 0x01 << offset;
27183 pub mod R {}
27184 pub mod W {}
27185 pub mod RW {
27186 #[doc = "Slow Slew Rate"]
27187 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
27188 #[doc = "Fast Slew Rate"]
27189 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
27190 }
27191 }
27192 #[doc = "Drive Strength Field"]
27193 pub mod DSE {
27194 pub const offset: u32 = 3;
27195 pub const mask: u32 = 0x07 << offset;
27196 pub mod R {}
27197 pub mod W {}
27198 pub mod RW {
27199 #[doc = "output driver disabled;"]
27200 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
27201 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
27202 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V_: u32 = 0x01;
27203 #[doc = "R0/2"]
27204 pub const DSE_2_R0_2: u32 = 0x02;
27205 #[doc = "R0/3"]
27206 pub const DSE_3_R0_3: u32 = 0x03;
27207 #[doc = "R0/4"]
27208 pub const DSE_4_R0_4: u32 = 0x04;
27209 #[doc = "R0/5"]
27210 pub const DSE_5_R0_5: u32 = 0x05;
27211 #[doc = "R0/6"]
27212 pub const DSE_6_R0_6: u32 = 0x06;
27213 #[doc = "R0/7"]
27214 pub const DSE_7_R0_7: u32 = 0x07;
27215 }
27216 }
27217 #[doc = "Speed Field"]
27218 pub mod SPEED {
27219 pub const offset: u32 = 6;
27220 pub const mask: u32 = 0x03 << offset;
27221 pub mod R {}
27222 pub mod W {}
27223 pub mod RW {
27224 #[doc = "low(50MHz)"]
27225 pub const SPEED_0_LOW_50MHZ_: u32 = 0;
27226 #[doc = "medium(100MHz)"]
27227 pub const SPEED_1_MEDIUM_100MHZ_: u32 = 0x01;
27228 #[doc = "medium(100MHz)"]
27229 pub const SPEED_2_MEDIUM_100MHZ_: u32 = 0x02;
27230 #[doc = "max(200MHz)"]
27231 pub const SPEED_3_MAX_200MHZ_: u32 = 0x03;
27232 }
27233 }
27234 #[doc = "Open Drain Enable Field"]
27235 pub mod ODE {
27236 pub const offset: u32 = 11;
27237 pub const mask: u32 = 0x01 << offset;
27238 pub mod R {}
27239 pub mod W {}
27240 pub mod RW {
27241 #[doc = "Open Drain Disabled"]
27242 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
27243 #[doc = "Open Drain Enabled"]
27244 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
27245 }
27246 }
27247 #[doc = "Pull / Keep Enable Field"]
27248 pub mod PKE {
27249 pub const offset: u32 = 12;
27250 pub const mask: u32 = 0x01 << offset;
27251 pub mod R {}
27252 pub mod W {}
27253 pub mod RW {
27254 #[doc = "Pull/Keeper Disabled"]
27255 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
27256 #[doc = "Pull/Keeper Enabled"]
27257 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
27258 }
27259 }
27260 #[doc = "Pull / Keep Select Field"]
27261 pub mod PUE {
27262 pub const offset: u32 = 13;
27263 pub const mask: u32 = 0x01 << offset;
27264 pub mod R {}
27265 pub mod W {}
27266 pub mod RW {
27267 #[doc = "Keeper"]
27268 pub const PUE_0_KEEPER: u32 = 0;
27269 #[doc = "Pull"]
27270 pub const PUE_1_PULL: u32 = 0x01;
27271 }
27272 }
27273 #[doc = "Pull Up / Down Config. Field"]
27274 pub mod PUS {
27275 pub const offset: u32 = 14;
27276 pub const mask: u32 = 0x03 << offset;
27277 pub mod R {}
27278 pub mod W {}
27279 pub mod RW {
27280 #[doc = "100K Ohm Pull Down"]
27281 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
27282 #[doc = "47K Ohm Pull Up"]
27283 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
27284 #[doc = "100K Ohm Pull Up"]
27285 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
27286 #[doc = "22K Ohm Pull Up"]
27287 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
27288 }
27289 }
27290 #[doc = "Hyst. Enable Field"]
27291 pub mod HYS {
27292 pub const offset: u32 = 16;
27293 pub const mask: u32 = 0x01 << offset;
27294 pub mod R {}
27295 pub mod W {}
27296 pub mod RW {
27297 #[doc = "Hysteresis Disabled"]
27298 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
27299 #[doc = "Hysteresis Enabled"]
27300 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
27301 }
27302 }
27303}
27304#[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B1_05 SW PAD Control Register"]
27305pub mod SW_PAD_CTL_PAD_GPIO_SPI_B1_05 {
27306 #[doc = "Slew Rate Field"]
27307 pub mod SRE {
27308 pub const offset: u32 = 0;
27309 pub const mask: u32 = 0x01 << offset;
27310 pub mod R {}
27311 pub mod W {}
27312 pub mod RW {
27313 #[doc = "Slow Slew Rate"]
27314 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
27315 #[doc = "Fast Slew Rate"]
27316 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
27317 }
27318 }
27319 #[doc = "Drive Strength Field"]
27320 pub mod DSE {
27321 pub const offset: u32 = 3;
27322 pub const mask: u32 = 0x07 << offset;
27323 pub mod R {}
27324 pub mod W {}
27325 pub mod RW {
27326 #[doc = "output driver disabled;"]
27327 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
27328 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
27329 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V_: u32 = 0x01;
27330 #[doc = "R0/2"]
27331 pub const DSE_2_R0_2: u32 = 0x02;
27332 #[doc = "R0/3"]
27333 pub const DSE_3_R0_3: u32 = 0x03;
27334 #[doc = "R0/4"]
27335 pub const DSE_4_R0_4: u32 = 0x04;
27336 #[doc = "R0/5"]
27337 pub const DSE_5_R0_5: u32 = 0x05;
27338 #[doc = "R0/6"]
27339 pub const DSE_6_R0_6: u32 = 0x06;
27340 #[doc = "R0/7"]
27341 pub const DSE_7_R0_7: u32 = 0x07;
27342 }
27343 }
27344 #[doc = "Speed Field"]
27345 pub mod SPEED {
27346 pub const offset: u32 = 6;
27347 pub const mask: u32 = 0x03 << offset;
27348 pub mod R {}
27349 pub mod W {}
27350 pub mod RW {
27351 #[doc = "low(50MHz)"]
27352 pub const SPEED_0_LOW_50MHZ_: u32 = 0;
27353 #[doc = "medium(100MHz)"]
27354 pub const SPEED_1_MEDIUM_100MHZ_: u32 = 0x01;
27355 #[doc = "medium(100MHz)"]
27356 pub const SPEED_2_MEDIUM_100MHZ_: u32 = 0x02;
27357 #[doc = "max(200MHz)"]
27358 pub const SPEED_3_MAX_200MHZ_: u32 = 0x03;
27359 }
27360 }
27361 #[doc = "Open Drain Enable Field"]
27362 pub mod ODE {
27363 pub const offset: u32 = 11;
27364 pub const mask: u32 = 0x01 << offset;
27365 pub mod R {}
27366 pub mod W {}
27367 pub mod RW {
27368 #[doc = "Open Drain Disabled"]
27369 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
27370 #[doc = "Open Drain Enabled"]
27371 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
27372 }
27373 }
27374 #[doc = "Pull / Keep Enable Field"]
27375 pub mod PKE {
27376 pub const offset: u32 = 12;
27377 pub const mask: u32 = 0x01 << offset;
27378 pub mod R {}
27379 pub mod W {}
27380 pub mod RW {
27381 #[doc = "Pull/Keeper Disabled"]
27382 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
27383 #[doc = "Pull/Keeper Enabled"]
27384 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
27385 }
27386 }
27387 #[doc = "Pull / Keep Select Field"]
27388 pub mod PUE {
27389 pub const offset: u32 = 13;
27390 pub const mask: u32 = 0x01 << offset;
27391 pub mod R {}
27392 pub mod W {}
27393 pub mod RW {
27394 #[doc = "Keeper"]
27395 pub const PUE_0_KEEPER: u32 = 0;
27396 #[doc = "Pull"]
27397 pub const PUE_1_PULL: u32 = 0x01;
27398 }
27399 }
27400 #[doc = "Pull Up / Down Config. Field"]
27401 pub mod PUS {
27402 pub const offset: u32 = 14;
27403 pub const mask: u32 = 0x03 << offset;
27404 pub mod R {}
27405 pub mod W {}
27406 pub mod RW {
27407 #[doc = "100K Ohm Pull Down"]
27408 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
27409 #[doc = "47K Ohm Pull Up"]
27410 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
27411 #[doc = "100K Ohm Pull Up"]
27412 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
27413 #[doc = "22K Ohm Pull Up"]
27414 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
27415 }
27416 }
27417 #[doc = "Hyst. Enable Field"]
27418 pub mod HYS {
27419 pub const offset: u32 = 16;
27420 pub const mask: u32 = 0x01 << offset;
27421 pub mod R {}
27422 pub mod W {}
27423 pub mod RW {
27424 #[doc = "Hysteresis Disabled"]
27425 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
27426 #[doc = "Hysteresis Enabled"]
27427 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
27428 }
27429 }
27430}
27431#[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B1_06 SW PAD Control Register"]
27432pub mod SW_PAD_CTL_PAD_GPIO_SPI_B1_06 {
27433 #[doc = "Slew Rate Field"]
27434 pub mod SRE {
27435 pub const offset: u32 = 0;
27436 pub const mask: u32 = 0x01 << offset;
27437 pub mod R {}
27438 pub mod W {}
27439 pub mod RW {
27440 #[doc = "Slow Slew Rate"]
27441 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
27442 #[doc = "Fast Slew Rate"]
27443 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
27444 }
27445 }
27446 #[doc = "Drive Strength Field"]
27447 pub mod DSE {
27448 pub const offset: u32 = 3;
27449 pub const mask: u32 = 0x07 << offset;
27450 pub mod R {}
27451 pub mod W {}
27452 pub mod RW {
27453 #[doc = "output driver disabled;"]
27454 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
27455 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
27456 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V_: u32 = 0x01;
27457 #[doc = "R0/2"]
27458 pub const DSE_2_R0_2: u32 = 0x02;
27459 #[doc = "R0/3"]
27460 pub const DSE_3_R0_3: u32 = 0x03;
27461 #[doc = "R0/4"]
27462 pub const DSE_4_R0_4: u32 = 0x04;
27463 #[doc = "R0/5"]
27464 pub const DSE_5_R0_5: u32 = 0x05;
27465 #[doc = "R0/6"]
27466 pub const DSE_6_R0_6: u32 = 0x06;
27467 #[doc = "R0/7"]
27468 pub const DSE_7_R0_7: u32 = 0x07;
27469 }
27470 }
27471 #[doc = "Speed Field"]
27472 pub mod SPEED {
27473 pub const offset: u32 = 6;
27474 pub const mask: u32 = 0x03 << offset;
27475 pub mod R {}
27476 pub mod W {}
27477 pub mod RW {
27478 #[doc = "low(50MHz)"]
27479 pub const SPEED_0_LOW_50MHZ_: u32 = 0;
27480 #[doc = "medium(100MHz)"]
27481 pub const SPEED_1_MEDIUM_100MHZ_: u32 = 0x01;
27482 #[doc = "medium(100MHz)"]
27483 pub const SPEED_2_MEDIUM_100MHZ_: u32 = 0x02;
27484 #[doc = "max(200MHz)"]
27485 pub const SPEED_3_MAX_200MHZ_: u32 = 0x03;
27486 }
27487 }
27488 #[doc = "Open Drain Enable Field"]
27489 pub mod ODE {
27490 pub const offset: u32 = 11;
27491 pub const mask: u32 = 0x01 << offset;
27492 pub mod R {}
27493 pub mod W {}
27494 pub mod RW {
27495 #[doc = "Open Drain Disabled"]
27496 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
27497 #[doc = "Open Drain Enabled"]
27498 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
27499 }
27500 }
27501 #[doc = "Pull / Keep Enable Field"]
27502 pub mod PKE {
27503 pub const offset: u32 = 12;
27504 pub const mask: u32 = 0x01 << offset;
27505 pub mod R {}
27506 pub mod W {}
27507 pub mod RW {
27508 #[doc = "Pull/Keeper Disabled"]
27509 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
27510 #[doc = "Pull/Keeper Enabled"]
27511 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
27512 }
27513 }
27514 #[doc = "Pull / Keep Select Field"]
27515 pub mod PUE {
27516 pub const offset: u32 = 13;
27517 pub const mask: u32 = 0x01 << offset;
27518 pub mod R {}
27519 pub mod W {}
27520 pub mod RW {
27521 #[doc = "Keeper"]
27522 pub const PUE_0_KEEPER: u32 = 0;
27523 #[doc = "Pull"]
27524 pub const PUE_1_PULL: u32 = 0x01;
27525 }
27526 }
27527 #[doc = "Pull Up / Down Config. Field"]
27528 pub mod PUS {
27529 pub const offset: u32 = 14;
27530 pub const mask: u32 = 0x03 << offset;
27531 pub mod R {}
27532 pub mod W {}
27533 pub mod RW {
27534 #[doc = "100K Ohm Pull Down"]
27535 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
27536 #[doc = "47K Ohm Pull Up"]
27537 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
27538 #[doc = "100K Ohm Pull Up"]
27539 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
27540 #[doc = "22K Ohm Pull Up"]
27541 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
27542 }
27543 }
27544 #[doc = "Hyst. Enable Field"]
27545 pub mod HYS {
27546 pub const offset: u32 = 16;
27547 pub const mask: u32 = 0x01 << offset;
27548 pub mod R {}
27549 pub mod W {}
27550 pub mod RW {
27551 #[doc = "Hysteresis Disabled"]
27552 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
27553 #[doc = "Hysteresis Enabled"]
27554 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
27555 }
27556 }
27557}
27558#[doc = "SW_PAD_CTL_PAD_GPIO_SPI_B1_07 SW PAD Control Register"]
27559pub mod SW_PAD_CTL_PAD_GPIO_SPI_B1_07 {
27560 #[doc = "Slew Rate Field"]
27561 pub mod SRE {
27562 pub const offset: u32 = 0;
27563 pub const mask: u32 = 0x01 << offset;
27564 pub mod R {}
27565 pub mod W {}
27566 pub mod RW {
27567 #[doc = "Slow Slew Rate"]
27568 pub const SRE_0_SLOW_SLEW_RATE: u32 = 0;
27569 #[doc = "Fast Slew Rate"]
27570 pub const SRE_1_FAST_SLEW_RATE: u32 = 0x01;
27571 }
27572 }
27573 #[doc = "Drive Strength Field"]
27574 pub mod DSE {
27575 pub const offset: u32 = 3;
27576 pub const mask: u32 = 0x07 << offset;
27577 pub mod R {}
27578 pub mod W {}
27579 pub mod RW {
27580 #[doc = "output driver disabled;"]
27581 pub const DSE_0_OUTPUT_DRIVER_DISABLED_: u32 = 0;
27582 #[doc = "R0(150 Ohm @ 3.3V, 260 Ohm@1.8V)"]
27583 pub const DSE_1_R0_150_OHM___3_3V__260_OHM_1_8V_: u32 = 0x01;
27584 #[doc = "R0/2"]
27585 pub const DSE_2_R0_2: u32 = 0x02;
27586 #[doc = "R0/3"]
27587 pub const DSE_3_R0_3: u32 = 0x03;
27588 #[doc = "R0/4"]
27589 pub const DSE_4_R0_4: u32 = 0x04;
27590 #[doc = "R0/5"]
27591 pub const DSE_5_R0_5: u32 = 0x05;
27592 #[doc = "R0/6"]
27593 pub const DSE_6_R0_6: u32 = 0x06;
27594 #[doc = "R0/7"]
27595 pub const DSE_7_R0_7: u32 = 0x07;
27596 }
27597 }
27598 #[doc = "Speed Field"]
27599 pub mod SPEED {
27600 pub const offset: u32 = 6;
27601 pub const mask: u32 = 0x03 << offset;
27602 pub mod R {}
27603 pub mod W {}
27604 pub mod RW {
27605 #[doc = "low(50MHz)"]
27606 pub const SPEED_0_LOW_50MHZ_: u32 = 0;
27607 #[doc = "medium(100MHz)"]
27608 pub const SPEED_1_MEDIUM_100MHZ_: u32 = 0x01;
27609 #[doc = "medium(100MHz)"]
27610 pub const SPEED_2_MEDIUM_100MHZ_: u32 = 0x02;
27611 #[doc = "max(200MHz)"]
27612 pub const SPEED_3_MAX_200MHZ_: u32 = 0x03;
27613 }
27614 }
27615 #[doc = "Open Drain Enable Field"]
27616 pub mod ODE {
27617 pub const offset: u32 = 11;
27618 pub const mask: u32 = 0x01 << offset;
27619 pub mod R {}
27620 pub mod W {}
27621 pub mod RW {
27622 #[doc = "Open Drain Disabled"]
27623 pub const ODE_0_OPEN_DRAIN_DISABLED: u32 = 0;
27624 #[doc = "Open Drain Enabled"]
27625 pub const ODE_1_OPEN_DRAIN_ENABLED: u32 = 0x01;
27626 }
27627 }
27628 #[doc = "Pull / Keep Enable Field"]
27629 pub mod PKE {
27630 pub const offset: u32 = 12;
27631 pub const mask: u32 = 0x01 << offset;
27632 pub mod R {}
27633 pub mod W {}
27634 pub mod RW {
27635 #[doc = "Pull/Keeper Disabled"]
27636 pub const PKE_0_PULL_KEEPER_DISABLED: u32 = 0;
27637 #[doc = "Pull/Keeper Enabled"]
27638 pub const PKE_1_PULL_KEEPER_ENABLED: u32 = 0x01;
27639 }
27640 }
27641 #[doc = "Pull / Keep Select Field"]
27642 pub mod PUE {
27643 pub const offset: u32 = 13;
27644 pub const mask: u32 = 0x01 << offset;
27645 pub mod R {}
27646 pub mod W {}
27647 pub mod RW {
27648 #[doc = "Keeper"]
27649 pub const PUE_0_KEEPER: u32 = 0;
27650 #[doc = "Pull"]
27651 pub const PUE_1_PULL: u32 = 0x01;
27652 }
27653 }
27654 #[doc = "Pull Up / Down Config. Field"]
27655 pub mod PUS {
27656 pub const offset: u32 = 14;
27657 pub const mask: u32 = 0x03 << offset;
27658 pub mod R {}
27659 pub mod W {}
27660 pub mod RW {
27661 #[doc = "100K Ohm Pull Down"]
27662 pub const PUS_0_100K_OHM_PULL_DOWN: u32 = 0;
27663 #[doc = "47K Ohm Pull Up"]
27664 pub const PUS_1_47K_OHM_PULL_UP: u32 = 0x01;
27665 #[doc = "100K Ohm Pull Up"]
27666 pub const PUS_2_100K_OHM_PULL_UP: u32 = 0x02;
27667 #[doc = "22K Ohm Pull Up"]
27668 pub const PUS_3_22K_OHM_PULL_UP: u32 = 0x03;
27669 }
27670 }
27671 #[doc = "Hyst. Enable Field"]
27672 pub mod HYS {
27673 pub const offset: u32 = 16;
27674 pub const mask: u32 = 0x01 << offset;
27675 pub mod R {}
27676 pub mod W {}
27677 pub mod RW {
27678 #[doc = "Hysteresis Disabled"]
27679 pub const HYS_0_HYSTERESIS_DISABLED: u32 = 0;
27680 #[doc = "Hysteresis Enabled"]
27681 pub const HYS_1_HYSTERESIS_ENABLED: u32 = 0x01;
27682 }
27683 }
27684}
27685#[doc = "ENET2_IPG_CLK_RMII_SELECT_INPUT DAISY Register"]
27686pub mod ENET2_IPG_CLK_RMII_SELECT_INPUT {
27687 #[doc = "Selecting Pads Involved in Daisy Chain."]
27688 pub mod DAISY {
27689 pub const offset: u32 = 0;
27690 pub const mask: u32 = 0x03 << offset;
27691 pub mod R {}
27692 pub mod W {}
27693 pub mod RW {
27694 #[doc = "Selecting Pad: GPIO_EMC_33 for Mode: ALT9"]
27695 pub const GPIO_EMC_33_ALT9: u32 = 0;
27696 #[doc = "Selecting Pad: GPIO_SD_B0_01 for Mode: ALT9"]
27697 pub const GPIO_SD_B0_01_ALT9: u32 = 0x01;
27698 #[doc = "Selecting Pad: GPIO_B0_15 for Mode: ALT9"]
27699 pub const GPIO_B0_15_ALT9: u32 = 0x02;
27700 }
27701 }
27702}
27703#[doc = "ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT DAISY Register"]
27704pub mod ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT {
27705 #[doc = "Selecting Pads Involved in Daisy Chain."]
27706 pub mod DAISY {
27707 pub const offset: u32 = 0;
27708 pub const mask: u32 = 0x01 << offset;
27709 pub mod R {}
27710 pub mod W {}
27711 pub mod RW {
27712 #[doc = "Selecting Pad: GPIO_EMC_39 for Mode: ALT8"]
27713 pub const GPIO_EMC_39_ALT8: u32 = 0;
27714 #[doc = "Selecting Pad: GPIO_B0_01 for Mode: ALT8"]
27715 pub const GPIO_B0_01_ALT8: u32 = 0x01;
27716 }
27717 }
27718}
27719#[doc = "ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_0 DAISY Register"]
27720pub mod ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_0 {
27721 #[doc = "Selecting Pads Involved in Daisy Chain."]
27722 pub mod DAISY {
27723 pub const offset: u32 = 0;
27724 pub const mask: u32 = 0x03 << offset;
27725 pub mod R {}
27726 pub mod W {}
27727 pub mod RW {
27728 #[doc = "Selecting Pad: GPIO_EMC_35 for Mode: ALT8"]
27729 pub const GPIO_EMC_35_ALT8: u32 = 0;
27730 #[doc = "Selecting Pad: GPIO_SD_B0_03 for Mode: ALT8"]
27731 pub const GPIO_SD_B0_03_ALT8: u32 = 0x01;
27732 #[doc = "Selecting Pad: GPIO_B1_01 for Mode: ALT8"]
27733 pub const GPIO_B1_01_ALT8: u32 = 0x02;
27734 }
27735 }
27736}
27737#[doc = "ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_1 DAISY Register"]
27738pub mod ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_1 {
27739 #[doc = "Selecting Pads Involved in Daisy Chain."]
27740 pub mod DAISY {
27741 pub const offset: u32 = 0;
27742 pub const mask: u32 = 0x03 << offset;
27743 pub mod R {}
27744 pub mod W {}
27745 pub mod RW {
27746 #[doc = "Selecting Pad: GPIO_EMC_36 for Mode: ALT8"]
27747 pub const GPIO_EMC_36_ALT8: u32 = 0;
27748 #[doc = "Selecting Pad: GPIO_SD_B0_04 for Mode: ALT8"]
27749 pub const GPIO_SD_B0_04_ALT8: u32 = 0x01;
27750 #[doc = "Selecting Pad: GPIO_B1_02 for Mode: ALT8"]
27751 pub const GPIO_B1_02_ALT8: u32 = 0x02;
27752 }
27753 }
27754}
27755#[doc = "ENET2_IPP_IND_MAC0_RXEN_SELECT_INPUT DAISY Register"]
27756pub mod ENET2_IPP_IND_MAC0_RXEN_SELECT_INPUT {
27757 #[doc = "Selecting Pads Involved in Daisy Chain."]
27758 pub mod DAISY {
27759 pub const offset: u32 = 0;
27760 pub const mask: u32 = 0x03 << offset;
27761 pub mod R {}
27762 pub mod W {}
27763 pub mod RW {
27764 #[doc = "Selecting Pad: GPIO_EMC_37 for Mode: ALT8"]
27765 pub const GPIO_EMC_37_ALT8: u32 = 0;
27766 #[doc = "Selecting Pad: GPIO_SD_B0_05 for Mode: ALT8"]
27767 pub const GPIO_SD_B0_05_ALT8: u32 = 0x01;
27768 #[doc = "Selecting Pad: GPIO_B1_03 for Mode: ALT8"]
27769 pub const GPIO_B1_03_ALT8: u32 = 0x02;
27770 }
27771 }
27772}
27773#[doc = "ENET2_IPP_IND_MAC0_RXERR_SELECT_INPUT DAISY Register"]
27774pub mod ENET2_IPP_IND_MAC0_RXERR_SELECT_INPUT {
27775 #[doc = "Selecting Pads Involved in Daisy Chain."]
27776 pub mod DAISY {
27777 pub const offset: u32 = 0;
27778 pub const mask: u32 = 0x03 << offset;
27779 pub mod R {}
27780 pub mod W {}
27781 pub mod RW {
27782 #[doc = "Selecting Pad: GPIO_EMC_34 for Mode: ALT8"]
27783 pub const GPIO_EMC_34_ALT8: u32 = 0;
27784 #[doc = "Selecting Pad: GPIO_SD_B0_02 for Mode: ALT8"]
27785 pub const GPIO_SD_B0_02_ALT8: u32 = 0x01;
27786 #[doc = "Selecting Pad: GPIO_B1_00 for Mode: ALT8"]
27787 pub const GPIO_B1_00_ALT8: u32 = 0x02;
27788 }
27789 }
27790}
27791#[doc = "ENET2_IPP_IND_MAC0_TIMER_SELECT_INPUT_0 DAISY Register"]
27792pub mod ENET2_IPP_IND_MAC0_TIMER_SELECT_INPUT_0 {
27793 #[doc = "Selecting Pads Involved in Daisy Chain."]
27794 pub mod DAISY {
27795 pub const offset: u32 = 0;
27796 pub const mask: u32 = 0x01 << offset;
27797 pub mod R {}
27798 pub mod W {}
27799 pub mod RW {
27800 #[doc = "Selecting Pad: GPIO_AD_B1_01 for Mode: ALT8"]
27801 pub const GPIO_AD_B1_01_ALT8: u32 = 0;
27802 #[doc = "Selecting Pad: GPIO_B0_03 for Mode: ALT8"]
27803 pub const GPIO_B0_03_ALT8: u32 = 0x01;
27804 }
27805 }
27806}
27807#[doc = "ENET2_IPP_IND_MAC0_TXCLK_SELECT_INPUT DAISY Register"]
27808pub mod ENET2_IPP_IND_MAC0_TXCLK_SELECT_INPUT {
27809 #[doc = "Selecting Pads Involved in Daisy Chain."]
27810 pub mod DAISY {
27811 pub const offset: u32 = 0;
27812 pub const mask: u32 = 0x03 << offset;
27813 pub mod R {}
27814 pub mod W {}
27815 pub mod RW {
27816 #[doc = "Selecting Pad: GPIO_EMC_33 for Mode: ALT8"]
27817 pub const GPIO_EMC_33_ALT8: u32 = 0;
27818 #[doc = "Selecting Pad: GPIO_SD_B0_01 for Mode: ALT8"]
27819 pub const GPIO_SD_B0_01_ALT8: u32 = 0x01;
27820 #[doc = "Selecting Pad: GPIO_B0_15 for Mode: ALT8"]
27821 pub const GPIO_B0_15_ALT8: u32 = 0x02;
27822 }
27823 }
27824}
27825#[doc = "FLEXSPI2_IPP_IND_DQS_FA_SELECT_INPUT DAISY Register"]
27826pub mod FLEXSPI2_IPP_IND_DQS_FA_SELECT_INPUT {
27827 #[doc = "Selecting Pads Involved in Daisy Chain."]
27828 pub mod DAISY {
27829 pub const offset: u32 = 0;
27830 pub const mask: u32 = 0x03 << offset;
27831 pub mod R {}
27832 pub mod W {}
27833 pub mod RW {
27834 #[doc = "Selecting Pad: GPIO_SPI_B1_00 for Mode: ALT0"]
27835 pub const GPIO_SPI_B1_00_ALT0: u32 = 0;
27836 #[doc = "Selecting Pad: GPIO_EMC_23 for Mode: ALT8"]
27837 pub const GPIO_EMC_23_ALT8: u32 = 0x01;
27838 #[doc = "Selecting Pad: GPIO_SPI_B0_09 for Mode: ALT0"]
27839 pub const GPIO_SPI_B0_09_ALT0: u32 = 0x02;
27840 }
27841 }
27842}
27843#[doc = "FLEXSPI2_IPP_IND_IO_FA_BIT0_SELECT_INPUT DAISY Register"]
27844pub mod FLEXSPI2_IPP_IND_IO_FA_BIT0_SELECT_INPUT {
27845 #[doc = "Selecting Pads Involved in Daisy Chain."]
27846 pub mod DAISY {
27847 pub const offset: u32 = 0;
27848 pub const mask: u32 = 0x03 << offset;
27849 pub mod R {}
27850 pub mod W {}
27851 pub mod RW {
27852 #[doc = "Selecting Pad: GPIO_SPI_B1_04 for Mode: ALT0"]
27853 pub const GPIO_SPI_B1_04_ALT0: u32 = 0;
27854 #[doc = "Selecting Pad: GPIO_EMC_26 for Mode: ALT8"]
27855 pub const GPIO_EMC_26_ALT8: u32 = 0x01;
27856 #[doc = "Selecting Pad: GPIO_SPI_B0_02 for Mode: ALT0"]
27857 pub const GPIO_SPI_B0_02_ALT0: u32 = 0x02;
27858 }
27859 }
27860}
27861#[doc = "FLEXSPI2_IPP_IND_IO_FA_BIT1_SELECT_INPUT DAISY Register"]
27862pub mod FLEXSPI2_IPP_IND_IO_FA_BIT1_SELECT_INPUT {
27863 #[doc = "Selecting Pads Involved in Daisy Chain."]
27864 pub mod DAISY {
27865 pub const offset: u32 = 0;
27866 pub const mask: u32 = 0x03 << offset;
27867 pub mod R {}
27868 pub mod W {}
27869 pub mod RW {
27870 #[doc = "Selecting Pad: GPIO_SPI_B1_03 for Mode: ALT0"]
27871 pub const GPIO_SPI_B1_03_ALT0: u32 = 0;
27872 #[doc = "Selecting Pad: GPIO_EMC_27 for Mode: ALT8"]
27873 pub const GPIO_EMC_27_ALT8: u32 = 0x01;
27874 #[doc = "Selecting Pad: GPIO_SPI_B0_12 for Mode: ALT0"]
27875 pub const GPIO_SPI_B0_12_ALT0: u32 = 0x02;
27876 }
27877 }
27878}
27879#[doc = "FLEXSPI2_IPP_IND_IO_FA_BIT2_SELECT_INPUT DAISY Register"]
27880pub mod FLEXSPI2_IPP_IND_IO_FA_BIT2_SELECT_INPUT {
27881 #[doc = "Selecting Pads Involved in Daisy Chain."]
27882 pub mod DAISY {
27883 pub const offset: u32 = 0;
27884 pub const mask: u32 = 0x03 << offset;
27885 pub mod R {}
27886 pub mod W {}
27887 pub mod RW {
27888 #[doc = "Selecting Pad: GPIO_SPI_B1_02 for Mode: ALT0"]
27889 pub const GPIO_SPI_B1_02_ALT0: u32 = 0;
27890 #[doc = "Selecting Pad: GPIO_EMC_28 for Mode: ALT8"]
27891 pub const GPIO_EMC_28_ALT8: u32 = 0x01;
27892 #[doc = "Selecting Pad: GPIO_SPI_B0_06 for Mode: ALT0"]
27893 pub const GPIO_SPI_B0_06_ALT0: u32 = 0x02;
27894 }
27895 }
27896}
27897#[doc = "FLEXSPI2_IPP_IND_IO_FA_BIT3_SELECT_INPUT DAISY Register"]
27898pub mod FLEXSPI2_IPP_IND_IO_FA_BIT3_SELECT_INPUT {
27899 #[doc = "Selecting Pads Involved in Daisy Chain."]
27900 pub mod DAISY {
27901 pub const offset: u32 = 0;
27902 pub const mask: u32 = 0x03 << offset;
27903 pub mod R {}
27904 pub mod W {}
27905 pub mod RW {
27906 #[doc = "Selecting Pad: GPIO_SPI_B1_01 for Mode: ALT0"]
27907 pub const GPIO_SPI_B1_01_ALT0: u32 = 0;
27908 #[doc = "Selecting Pad: GPIO_EMC_29 for Mode: ALT8"]
27909 pub const GPIO_EMC_29_ALT8: u32 = 0x01;
27910 #[doc = "Selecting Pad: GPIO_SPI_B0_10 for Mode: ALT0"]
27911 pub const GPIO_SPI_B0_10_ALT0: u32 = 0x02;
27912 }
27913 }
27914}
27915#[doc = "FLEXSPI2_IPP_IND_IO_FB_BIT0_SELECT_INPUT DAISY Register"]
27916pub mod FLEXSPI2_IPP_IND_IO_FB_BIT0_SELECT_INPUT {
27917 #[doc = "Selecting Pads Involved in Daisy Chain."]
27918 pub mod DAISY {
27919 pub const offset: u32 = 0;
27920 pub const mask: u32 = 0x01 << offset;
27921 pub mod R {}
27922 pub mod W {}
27923 pub mod RW {
27924 #[doc = "Selecting Pad: GPIO_EMC_13 for Mode: ALT8"]
27925 pub const GPIO_EMC_13_ALT8: u32 = 0;
27926 #[doc = "Selecting Pad: GPIO_SPI_B0_11 for Mode: ALT0"]
27927 pub const GPIO_SPI_B0_11_ALT0: u32 = 0x01;
27928 }
27929 }
27930}
27931#[doc = "FLEXSPI2_IPP_IND_IO_FB_BIT1_SELECT_INPUT DAISY Register"]
27932pub mod FLEXSPI2_IPP_IND_IO_FB_BIT1_SELECT_INPUT {
27933 #[doc = "Selecting Pads Involved in Daisy Chain."]
27934 pub mod DAISY {
27935 pub const offset: u32 = 0;
27936 pub const mask: u32 = 0x01 << offset;
27937 pub mod R {}
27938 pub mod W {}
27939 pub mod RW {
27940 #[doc = "Selecting Pad: GPIO_EMC_14 for Mode: ALT8"]
27941 pub const GPIO_EMC_14_ALT8: u32 = 0;
27942 #[doc = "Selecting Pad: GPIO_SPI_B0_07 for Mode: ALT0"]
27943 pub const GPIO_SPI_B0_07_ALT0: u32 = 0x01;
27944 }
27945 }
27946}
27947#[doc = "FLEXSPI2_IPP_IND_IO_FB_BIT2_SELECT_INPUT DAISY Register"]
27948pub mod FLEXSPI2_IPP_IND_IO_FB_BIT2_SELECT_INPUT {
27949 #[doc = "Selecting Pads Involved in Daisy Chain."]
27950 pub mod DAISY {
27951 pub const offset: u32 = 0;
27952 pub const mask: u32 = 0x01 << offset;
27953 pub mod R {}
27954 pub mod W {}
27955 pub mod RW {
27956 #[doc = "Selecting Pad: GPIO_EMC_15 for Mode: ALT8"]
27957 pub const GPIO_EMC_15_ALT8: u32 = 0;
27958 #[doc = "Selecting Pad: GPIO_SPI_B0_03 for Mode: ALT0"]
27959 pub const GPIO_SPI_B0_03_ALT0: u32 = 0x01;
27960 }
27961 }
27962}
27963#[doc = "FLEXSPI2_IPP_IND_IO_FB_BIT3_SELECT_INPUT DAISY Register"]
27964pub mod FLEXSPI2_IPP_IND_IO_FB_BIT3_SELECT_INPUT {
27965 #[doc = "Selecting Pads Involved in Daisy Chain."]
27966 pub mod DAISY {
27967 pub const offset: u32 = 0;
27968 pub const mask: u32 = 0x01 << offset;
27969 pub mod R {}
27970 pub mod W {}
27971 pub mod RW {
27972 #[doc = "Selecting Pad: GPIO_EMC_16 for Mode: ALT8"]
27973 pub const GPIO_EMC_16_ALT8: u32 = 0;
27974 #[doc = "Selecting Pad: GPIO_SPI_B0_04 for Mode: ALT0"]
27975 pub const GPIO_SPI_B0_04_ALT0: u32 = 0x01;
27976 }
27977 }
27978}
27979#[doc = "FLEXSPI2_IPP_IND_SCK_FA_SELECT_INPUT DAISY Register"]
27980pub mod FLEXSPI2_IPP_IND_SCK_FA_SELECT_INPUT {
27981 #[doc = "Selecting Pads Involved in Daisy Chain."]
27982 pub mod DAISY {
27983 pub const offset: u32 = 0;
27984 pub const mask: u32 = 0x03 << offset;
27985 pub mod R {}
27986 pub mod W {}
27987 pub mod RW {
27988 #[doc = "Selecting Pad: GPIO_SPI_B1_05 for Mode: ALT0"]
27989 pub const GPIO_SPI_B1_05_ALT0: u32 = 0;
27990 #[doc = "Selecting Pad: GPIO_EMC_25 for Mode: ALT8"]
27991 pub const GPIO_EMC_25_ALT8: u32 = 0x01;
27992 #[doc = "Selecting Pad: GPIO_SPI_B0_08 for Mode: ALT0"]
27993 pub const GPIO_SPI_B0_08_ALT0: u32 = 0x02;
27994 }
27995 }
27996}
27997#[doc = "FLEXSPI2_IPP_IND_SCK_FB_SELECT_INPUT DAISY Register"]
27998pub mod FLEXSPI2_IPP_IND_SCK_FB_SELECT_INPUT {
27999 #[doc = "Selecting Pads Involved in Daisy Chain."]
28000 pub mod DAISY {
28001 pub const offset: u32 = 0;
28002 pub const mask: u32 = 0x01 << offset;
28003 pub mod R {}
28004 pub mod W {}
28005 pub mod RW {
28006 #[doc = "Selecting Pad: GPIO_EMC_12 for Mode: ALT8"]
28007 pub const GPIO_EMC_12_ALT8: u32 = 0;
28008 #[doc = "Selecting Pad: GPIO_SPI_B0_01 for Mode: ALT0"]
28009 pub const GPIO_SPI_B0_01_ALT0: u32 = 0x01;
28010 }
28011 }
28012}
28013#[doc = "GPT1_IPP_IND_CAPIN1_SELECT_INPUT DAISY Register"]
28014pub mod GPT1_IPP_IND_CAPIN1_SELECT_INPUT {
28015 #[doc = "Selecting Pads Involved in Daisy Chain."]
28016 pub mod DAISY {
28017 pub const offset: u32 = 0;
28018 pub const mask: u32 = 0x01 << offset;
28019 pub mod R {}
28020 pub mod W {}
28021 pub mod RW {
28022 #[doc = "Selecting Pad: GPIO_EMC_24 for Mode: ALT4"]
28023 pub const GPIO_EMC_24_ALT4: u32 = 0;
28024 #[doc = "Selecting Pad: GPIO_B1_05 for Mode: ALT8"]
28025 pub const GPIO_B1_05_ALT8: u32 = 0x01;
28026 }
28027 }
28028}
28029#[doc = "GPT1_IPP_IND_CAPIN2_SELECT_INPUT DAISY Register"]
28030pub mod GPT1_IPP_IND_CAPIN2_SELECT_INPUT {
28031 #[doc = "Selecting Pads Involved in Daisy Chain."]
28032 pub mod DAISY {
28033 pub const offset: u32 = 0;
28034 pub const mask: u32 = 0x01 << offset;
28035 pub mod R {}
28036 pub mod W {}
28037 pub mod RW {
28038 #[doc = "Selecting Pad: GPIO_EMC_23 for Mode: ALT4"]
28039 pub const GPIO_EMC_23_ALT4: u32 = 0;
28040 #[doc = "Selecting Pad: GPIO_B1_06 for Mode: ALT8"]
28041 pub const GPIO_B1_06_ALT8: u32 = 0x01;
28042 }
28043 }
28044}
28045#[doc = "GPT1_IPP_IND_CLKIN_SELECT_INPUT DAISY Register"]
28046pub mod GPT1_IPP_IND_CLKIN_SELECT_INPUT {
28047 #[doc = "Selecting Pads Involved in Daisy Chain."]
28048 pub mod DAISY {
28049 pub const offset: u32 = 0;
28050 pub const mask: u32 = 0x01 << offset;
28051 pub mod R {}
28052 pub mod W {}
28053 pub mod RW {
28054 #[doc = "Selecting Pad: GPIO_AD_B0_13 for Mode: ALT1"]
28055 pub const GPIO_AD_B0_13_ALT1: u32 = 0;
28056 #[doc = "Selecting Pad: GPIO_B1_04 for Mode: ALT8"]
28057 pub const GPIO_B1_04_ALT8: u32 = 0x01;
28058 }
28059 }
28060}
28061#[doc = "GPT2_IPP_IND_CAPIN1_SELECT_INPUT DAISY Register"]
28062pub mod GPT2_IPP_IND_CAPIN1_SELECT_INPUT {
28063 #[doc = "Selecting Pads Involved in Daisy Chain."]
28064 pub mod DAISY {
28065 pub const offset: u32 = 0;
28066 pub const mask: u32 = 0x01 << offset;
28067 pub mod R {}
28068 pub mod W {}
28069 pub mod RW {
28070 #[doc = "Selecting Pad: GPIO_EMC_41 for Mode: ALT1"]
28071 pub const GPIO_EMC_41_ALT1: u32 = 0;
28072 #[doc = "Selecting Pad: GPIO_AD_B1_03 for Mode: ALT8"]
28073 pub const GPIO_AD_B1_03_ALT8: u32 = 0x01;
28074 }
28075 }
28076}
28077#[doc = "GPT2_IPP_IND_CAPIN2_SELECT_INPUT DAISY Register"]
28078pub mod GPT2_IPP_IND_CAPIN2_SELECT_INPUT {
28079 #[doc = "Selecting Pads Involved in Daisy Chain."]
28080 pub mod DAISY {
28081 pub const offset: u32 = 0;
28082 pub const mask: u32 = 0x01 << offset;
28083 pub mod R {}
28084 pub mod W {}
28085 pub mod RW {
28086 #[doc = "Selecting Pad: GPIO_EMC_40 for Mode: ALT1"]
28087 pub const GPIO_EMC_40_ALT1: u32 = 0;
28088 #[doc = "Selecting Pad: GPIO_AD_B1_04 for Mode: ALT8"]
28089 pub const GPIO_AD_B1_04_ALT8: u32 = 0x01;
28090 }
28091 }
28092}
28093#[doc = "GPT2_IPP_IND_CLKIN_SELECT_INPUT DAISY Register"]
28094pub mod GPT2_IPP_IND_CLKIN_SELECT_INPUT {
28095 #[doc = "Selecting Pads Involved in Daisy Chain."]
28096 pub mod DAISY {
28097 pub const offset: u32 = 0;
28098 pub const mask: u32 = 0x01 << offset;
28099 pub mod R {}
28100 pub mod W {}
28101 pub mod RW {
28102 #[doc = "Selecting Pad: GPIO_AD_B0_09 for Mode: ALT7"]
28103 pub const GPIO_AD_B0_09_ALT7: u32 = 0;
28104 #[doc = "Selecting Pad: GPIO_AD_B1_02 for Mode: ALT8"]
28105 pub const GPIO_AD_B1_02_ALT8: u32 = 0x01;
28106 }
28107 }
28108}
28109#[doc = "SAI3_IPG_CLK_SAI_MCLK_SELECT_INPUT_2 DAISY Register"]
28110pub mod SAI3_IPG_CLK_SAI_MCLK_SELECT_INPUT_2 {
28111 #[doc = "Selecting Pads Involved in Daisy Chain."]
28112 pub mod DAISY {
28113 pub const offset: u32 = 0;
28114 pub const mask: u32 = 0x01 << offset;
28115 pub mod R {}
28116 pub mod W {}
28117 pub mod RW {
28118 #[doc = "Selecting Pad: GPIO_EMC_37 for Mode: ALT3"]
28119 pub const GPIO_EMC_37_ALT3: u32 = 0;
28120 #[doc = "Selecting Pad: GPIO_SD_B1_04 for Mode: ALT8"]
28121 pub const GPIO_SD_B1_04_ALT8: u32 = 0x01;
28122 }
28123 }
28124}
28125#[doc = "SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT DAISY Register"]
28126pub mod SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT {
28127 #[doc = "Selecting Pads Involved in Daisy Chain."]
28128 pub mod DAISY {
28129 pub const offset: u32 = 0;
28130 pub const mask: u32 = 0x01 << offset;
28131 pub mod R {}
28132 pub mod W {}
28133 pub mod RW {
28134 #[doc = "Selecting Pad: GPIO_EMC_35 for Mode: ALT3"]
28135 pub const GPIO_EMC_35_ALT3: u32 = 0;
28136 #[doc = "Selecting Pad: GPIO_SD_B1_06 for Mode: ALT8"]
28137 pub const GPIO_SD_B1_06_ALT8: u32 = 0x01;
28138 }
28139 }
28140}
28141#[doc = "SAI3_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 DAISY Register"]
28142pub mod SAI3_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 {
28143 #[doc = "Selecting Pads Involved in Daisy Chain."]
28144 pub mod DAISY {
28145 pub const offset: u32 = 0;
28146 pub const mask: u32 = 0x01 << offset;
28147 pub mod R {}
28148 pub mod W {}
28149 pub mod RW {
28150 #[doc = "Selecting Pad: GPIO_EMC_33 for Mode: ALT3"]
28151 pub const GPIO_EMC_33_ALT3: u32 = 0;
28152 #[doc = "Selecting Pad: GPIO_SD_B1_00 for Mode: ALT8"]
28153 pub const GPIO_SD_B1_00_ALT8: u32 = 0x01;
28154 }
28155 }
28156}
28157#[doc = "SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT DAISY Register"]
28158pub mod SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT {
28159 #[doc = "Selecting Pads Involved in Daisy Chain."]
28160 pub mod DAISY {
28161 pub const offset: u32 = 0;
28162 pub const mask: u32 = 0x01 << offset;
28163 pub mod R {}
28164 pub mod W {}
28165 pub mod RW {
28166 #[doc = "Selecting Pad: GPIO_EMC_34 for Mode: ALT3"]
28167 pub const GPIO_EMC_34_ALT3: u32 = 0;
28168 #[doc = "Selecting Pad: GPIO_SD_B1_05 for Mode: ALT8"]
28169 pub const GPIO_SD_B1_05_ALT8: u32 = 0x01;
28170 }
28171 }
28172}
28173#[doc = "SAI3_IPP_IND_SAI_TXBCLK_SELECT_INPUT DAISY Register"]
28174pub mod SAI3_IPP_IND_SAI_TXBCLK_SELECT_INPUT {
28175 #[doc = "Selecting Pads Involved in Daisy Chain."]
28176 pub mod DAISY {
28177 pub const offset: u32 = 0;
28178 pub const mask: u32 = 0x01 << offset;
28179 pub mod R {}
28180 pub mod W {}
28181 pub mod RW {
28182 #[doc = "Selecting Pad: GPIO_EMC_38 for Mode: ALT3"]
28183 pub const GPIO_EMC_38_ALT3: u32 = 0;
28184 #[doc = "Selecting Pad: GPIO_SD_B1_03 for Mode: ALT8"]
28185 pub const GPIO_SD_B1_03_ALT8: u32 = 0x01;
28186 }
28187 }
28188}
28189#[doc = "SAI3_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register"]
28190pub mod SAI3_IPP_IND_SAI_TXSYNC_SELECT_INPUT {
28191 #[doc = "Selecting Pads Involved in Daisy Chain."]
28192 pub mod DAISY {
28193 pub const offset: u32 = 0;
28194 pub const mask: u32 = 0x01 << offset;
28195 pub mod R {}
28196 pub mod W {}
28197 pub mod RW {
28198 #[doc = "Selecting Pad: GPIO_EMC_39 for Mode: ALT3"]
28199 pub const GPIO_EMC_39_ALT3: u32 = 0;
28200 #[doc = "Selecting Pad: GPIO_SD_B1_02 for Mode: ALT8"]
28201 pub const GPIO_SD_B1_02_ALT8: u32 = 0x01;
28202 }
28203 }
28204}
28205#[doc = "SEMC_I_IPP_IND_DQS4_SELECT_INPUT DAISY Register"]
28206pub mod SEMC_I_IPP_IND_DQS4_SELECT_INPUT {
28207 #[doc = "Selecting Pads Involved in Daisy Chain."]
28208 pub mod DAISY {
28209 pub const offset: u32 = 0;
28210 pub const mask: u32 = 0x03 << offset;
28211 pub mod R {}
28212 pub mod W {}
28213 pub mod RW {
28214 #[doc = "Selecting Pad: GPIO_SD_B0_00 for Mode: ALT9"]
28215 pub const GPIO_SD_B0_00_ALT9: u32 = 0;
28216 #[doc = "Selecting Pad: GPIO_EMC_39 for Mode: ALT9"]
28217 pub const GPIO_EMC_39_ALT9: u32 = 0x01;
28218 #[doc = "Selecting Pad: GPIO_AD_B0_09 for Mode: ALT9"]
28219 pub const GPIO_AD_B0_09_ALT9: u32 = 0x02;
28220 #[doc = "Selecting Pad: GPIO_B1_13 for Mode: ALT8"]
28221 pub const GPIO_B1_13_ALT8: u32 = 0x03;
28222 }
28223 }
28224}
28225#[doc = "CANFD_IPP_IND_CANRX_SELECT_INPUT DAISY Register"]
28226pub mod CANFD_IPP_IND_CANRX_SELECT_INPUT {
28227 #[doc = "Selecting Pads Involved in Daisy Chain."]
28228 pub mod DAISY {
28229 pub const offset: u32 = 0;
28230 pub const mask: u32 = 0x03 << offset;
28231 pub mod R {}
28232 pub mod W {}
28233 pub mod RW {
28234 #[doc = "Selecting Pad: GPIO_EMC_37 for Mode: ALT9"]
28235 pub const GPIO_EMC_37_ALT9: u32 = 0;
28236 #[doc = "Selecting Pad: GPIO_AD_B0_15 for Mode: ALT8"]
28237 pub const GPIO_AD_B0_15_ALT8: u32 = 0x01;
28238 #[doc = "Selecting Pad: GPIO_AD_B0_11 for Mode: ALT8"]
28239 pub const GPIO_AD_B0_11_ALT8: u32 = 0x02;
28240 }
28241 }
28242}