imxrt_ral/blocks/imxrt1061/
iomuxc_gpr.rs

1#[doc = "IOMUXC_GPR"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "GPR0 General Purpose Register"]
5    pub GPR0: crate::RORegister<u32>,
6    #[doc = "GPR1 General Purpose Register"]
7    pub GPR1: crate::RWRegister<u32>,
8    #[doc = "GPR2 General Purpose Register"]
9    pub GPR2: crate::RWRegister<u32>,
10    #[doc = "GPR3 General Purpose Register"]
11    pub GPR3: crate::RWRegister<u32>,
12    #[doc = "GPR4 General Purpose Register"]
13    pub GPR4: crate::RWRegister<u32>,
14    #[doc = "GPR5 General Purpose Register"]
15    pub GPR5: crate::RWRegister<u32>,
16    #[doc = "GPR6 General Purpose Register"]
17    pub GPR6: crate::RWRegister<u32>,
18    #[doc = "GPR7 General Purpose Register"]
19    pub GPR7: crate::RWRegister<u32>,
20    #[doc = "GPR8 General Purpose Register"]
21    pub GPR8: crate::RWRegister<u32>,
22    #[doc = "GPR9 General Purpose Register"]
23    pub GPR9: crate::RORegister<u32>,
24    #[doc = "GPR10 General Purpose Register"]
25    pub GPR10: crate::RWRegister<u32>,
26    #[doc = "GPR11 General Purpose Register"]
27    pub GPR11: crate::RWRegister<u32>,
28    #[doc = "GPR12 General Purpose Register"]
29    pub GPR12: crate::RWRegister<u32>,
30    #[doc = "GPR13 General Purpose Register"]
31    pub GPR13: crate::RWRegister<u32>,
32    #[doc = "GPR14 General Purpose Register"]
33    pub GPR14: crate::RWRegister<u32>,
34    #[doc = "GPR15 General Purpose Register"]
35    pub GPR15: crate::RORegister<u32>,
36    #[doc = "GPR16 General Purpose Register"]
37    pub GPR16: crate::RWRegister<u32>,
38    #[doc = "GPR17 General Purpose Register"]
39    pub GPR17: crate::RWRegister<u32>,
40    #[doc = "GPR18 General Purpose Register"]
41    pub GPR18: crate::RWRegister<u32>,
42    #[doc = "GPR19 General Purpose Register"]
43    pub GPR19: crate::RWRegister<u32>,
44    #[doc = "GPR20 General Purpose Register"]
45    pub GPR20: crate::RWRegister<u32>,
46    #[doc = "GPR21 General Purpose Register"]
47    pub GPR21: crate::RWRegister<u32>,
48    #[doc = "GPR22 General Purpose Register"]
49    pub GPR22: crate::RWRegister<u32>,
50    #[doc = "GPR23 General Purpose Register"]
51    pub GPR23: crate::RWRegister<u32>,
52    #[doc = "GPR24 General Purpose Register"]
53    pub GPR24: crate::RWRegister<u32>,
54    #[doc = "GPR25 General Purpose Register"]
55    pub GPR25: crate::RWRegister<u32>,
56    #[doc = "GPR26 General Purpose Register"]
57    pub GPR26: crate::RWRegister<u32>,
58    #[doc = "GPR27 General Purpose Register"]
59    pub GPR27: crate::RWRegister<u32>,
60    #[doc = "GPR28 General Purpose Register"]
61    pub GPR28: crate::RWRegister<u32>,
62    #[doc = "GPR29 General Purpose Register"]
63    pub GPR29: crate::RWRegister<u32>,
64    #[doc = "GPR30 General Purpose Register"]
65    pub GPR30: crate::RWRegister<u32>,
66    #[doc = "GPR31 General Purpose Register"]
67    pub GPR31: crate::RWRegister<u32>,
68    #[doc = "GPR32 General Purpose Register"]
69    pub GPR32: crate::RWRegister<u32>,
70    #[doc = "GPR33 General Purpose Register"]
71    pub GPR33: crate::RWRegister<u32>,
72    #[doc = "GPR34 General Purpose Register"]
73    pub GPR34: crate::RWRegister<u32>,
74}
75#[doc = "GPR1 General Purpose Register"]
76pub mod GPR1 {
77    #[doc = "SAI1 MCLK1 source select"]
78    pub mod SAI1_MCLK1_SEL {
79        pub const offset: u32 = 0;
80        pub const mask: u32 = 0x07 << offset;
81        pub mod R {}
82        pub mod W {}
83        pub mod RW {
84            #[doc = "ccm.ssi1_clk_root"]
85            pub const SAI1_MCLK1_SEL_0: u32 = 0;
86            #[doc = "ccm.ssi2_clk_root"]
87            pub const SAI1_MCLK1_SEL_1: u32 = 0x01;
88            #[doc = "ccm.ssi3_clk_root"]
89            pub const SAI1_MCLK1_SEL_2: u32 = 0x02;
90            #[doc = "iomux.sai1_ipg_clk_sai_mclk"]
91            pub const SAI1_MCLK1_SEL_3: u32 = 0x03;
92            #[doc = "iomux.sai2_ipg_clk_sai_mclk"]
93            pub const SAI1_MCLK1_SEL_4: u32 = 0x04;
94            #[doc = "iomux.sai3_ipg_clk_sai_mclk"]
95            pub const SAI1_MCLK1_SEL_5: u32 = 0x05;
96        }
97    }
98    #[doc = "SAI1 MCLK2 source select"]
99    pub mod SAI1_MCLK2_SEL {
100        pub const offset: u32 = 3;
101        pub const mask: u32 = 0x07 << offset;
102        pub mod R {}
103        pub mod W {}
104        pub mod RW {
105            #[doc = "ccm.ssi1_clk_root"]
106            pub const SAI1_MCLK2_SEL_0: u32 = 0;
107            #[doc = "ccm.ssi2_clk_root"]
108            pub const SAI1_MCLK2_SEL_1: u32 = 0x01;
109            #[doc = "ccm.ssi3_clk_root"]
110            pub const SAI1_MCLK2_SEL_2: u32 = 0x02;
111            #[doc = "iomux.sai1_ipg_clk_sai_mclk"]
112            pub const SAI1_MCLK2_SEL_3: u32 = 0x03;
113            #[doc = "iomux.sai2_ipg_clk_sai_mclk"]
114            pub const SAI1_MCLK2_SEL_4: u32 = 0x04;
115            #[doc = "iomux.sai3_ipg_clk_sai_mclk"]
116            pub const SAI1_MCLK2_SEL_5: u32 = 0x05;
117        }
118    }
119    #[doc = "SAI1 MCLK3 source select"]
120    pub mod SAI1_MCLK3_SEL {
121        pub const offset: u32 = 6;
122        pub const mask: u32 = 0x03 << offset;
123        pub mod R {}
124        pub mod W {}
125        pub mod RW {
126            #[doc = "ccm.spdif0_clk_root"]
127            pub const SAI1_MCLK3_SEL_0: u32 = 0;
128            #[doc = "iomux.spdif_tx_clk2"]
129            pub const SAI1_MCLK3_SEL_1: u32 = 0x01;
130            #[doc = "spdif.spdif_srclk"]
131            pub const SAI1_MCLK3_SEL_2: u32 = 0x02;
132            #[doc = "spdif.spdif_outclock"]
133            pub const SAI1_MCLK3_SEL_3: u32 = 0x03;
134        }
135    }
136    #[doc = "SAI2 MCLK3 source select"]
137    pub mod SAI2_MCLK3_SEL {
138        pub const offset: u32 = 8;
139        pub const mask: u32 = 0x03 << offset;
140        pub mod R {}
141        pub mod W {}
142        pub mod RW {
143            #[doc = "ccm.spdif0_clk_root"]
144            pub const SAI2_MCLK3_SEL_0: u32 = 0;
145            #[doc = "iomux.spdif_tx_clk2"]
146            pub const SAI2_MCLK3_SEL_1: u32 = 0x01;
147            #[doc = "spdif.spdif_srclk"]
148            pub const SAI2_MCLK3_SEL_2: u32 = 0x02;
149            #[doc = "spdif.spdif_outclock"]
150            pub const SAI2_MCLK3_SEL_3: u32 = 0x03;
151        }
152    }
153    #[doc = "SAI3 MCLK3 source select"]
154    pub mod SAI3_MCLK3_SEL {
155        pub const offset: u32 = 10;
156        pub const mask: u32 = 0x03 << offset;
157        pub mod R {}
158        pub mod W {}
159        pub mod RW {
160            #[doc = "ccm.spdif0_clk_root"]
161            pub const SAI3_MCLK3_SEL_0: u32 = 0;
162            #[doc = "iomux.spdif_tx_clk2"]
163            pub const SAI3_MCLK3_SEL_1: u32 = 0x01;
164            #[doc = "spdif.spdif_srclk"]
165            pub const SAI3_MCLK3_SEL_2: u32 = 0x02;
166            #[doc = "spdif.spdif_outclock"]
167            pub const SAI3_MCLK3_SEL_3: u32 = 0x03;
168        }
169    }
170    #[doc = "Global interrupt \"0\" bit (connected to ARM M7 IRQ#0 and GPC)"]
171    pub mod GINT {
172        pub const offset: u32 = 12;
173        pub const mask: u32 = 0x01 << offset;
174        pub mod R {}
175        pub mod W {}
176        pub mod RW {
177            #[doc = "Global interrupt request is not asserted."]
178            pub const GINT_0: u32 = 0;
179            #[doc = "Global interrupt request is asserted."]
180            pub const GINT_1: u32 = 0x01;
181        }
182    }
183    #[doc = "ENET1 reference clock mode select."]
184    pub mod ENET1_CLK_SEL {
185        pub const offset: u32 = 13;
186        pub const mask: u32 = 0x01 << offset;
187        pub mod R {}
188        pub mod W {}
189        pub mod RW {
190            #[doc = "ENET1 TX reference clock driven by ref_enetpll. This clock is also output to pins via the IOMUX. ENET_REF_CLK1 function."]
191            pub const ENET1_CLK_SEL_0: u32 = 0;
192            #[doc = "Gets ENET1 TX reference clock from the ENET1_TX_CLK pin. In this use case, an external OSC provides the clock for both the external PHY and the internal controller."]
193            pub const ENET1_CLK_SEL_1: u32 = 0x01;
194        }
195    }
196    #[doc = "ENET2 reference clock mode select."]
197    pub mod ENET2_CLK_SEL {
198        pub const offset: u32 = 14;
199        pub const mask: u32 = 0x01 << offset;
200        pub mod R {}
201        pub mod W {}
202        pub mod RW {
203            #[doc = "ENET2 TX reference clock driven by ref_enetpll. This clock is also output to pins via the IOMUX. ENET2_REF_CLK function."]
204            pub const ENET2_CLK_SEL_0: u32 = 0;
205            #[doc = "Gets ENET2 TX reference clock from the ENET2_TX_CLK pin. In this use case, an external OSC provides the clock for both the external PHY and the internal controller."]
206            pub const ENET2_CLK_SEL_1: u32 = 0x01;
207        }
208    }
209    #[doc = "USB Exposure mode"]
210    pub mod USB_EXP_MODE {
211        pub const offset: u32 = 15;
212        pub const mask: u32 = 0x01 << offset;
213        pub mod R {}
214        pub mod W {}
215        pub mod RW {
216            #[doc = "Exposure mode is disabled."]
217            pub const USB_EXP_MODE_0: u32 = 0;
218            #[doc = "Exposure mode is enabled."]
219            pub const USB_EXP_MODE_1: u32 = 0x01;
220        }
221    }
222    #[doc = "ENET1_TX_CLK data direction control"]
223    pub mod ENET1_TX_CLK_DIR {
224        pub const offset: u32 = 17;
225        pub const mask: u32 = 0x01 << offset;
226        pub mod R {}
227        pub mod W {}
228        pub mod RW {
229            #[doc = "ENET1_TX_CLK output driver is disabled"]
230            pub const ENET1_TX_CLK_DIR_0: u32 = 0;
231            #[doc = "ENET1_TX_CLK output driver is enabled"]
232            pub const ENET1_TX_CLK_DIR_1: u32 = 0x01;
233        }
234    }
235    #[doc = "ENET2_TX_CLK data direction control"]
236    pub mod ENET2_TX_CLK_DIR {
237        pub const offset: u32 = 18;
238        pub const mask: u32 = 0x01 << offset;
239        pub mod R {}
240        pub mod W {}
241        pub mod RW {
242            #[doc = "ENET2_TX_CLK output driver is disabled"]
243            pub const ENET2_TX_CLK_DIR_0: u32 = 0;
244            #[doc = "ENET2_TX_CLK output driver is enabled"]
245            pub const ENET2_TX_CLK_DIR_1: u32 = 0x01;
246        }
247    }
248    #[doc = "sai1.MCLK signal direction control"]
249    pub mod SAI1_MCLK_DIR {
250        pub const offset: u32 = 19;
251        pub const mask: u32 = 0x01 << offset;
252        pub mod R {}
253        pub mod W {}
254        pub mod RW {
255            #[doc = "sai1.MCLK is input signal"]
256            pub const SAI1_MCLK_DIR_0: u32 = 0;
257            #[doc = "sai1.MCLK is output signal"]
258            pub const SAI1_MCLK_DIR_1: u32 = 0x01;
259        }
260    }
261    #[doc = "sai2.MCLK signal direction control"]
262    pub mod SAI2_MCLK_DIR {
263        pub const offset: u32 = 20;
264        pub const mask: u32 = 0x01 << offset;
265        pub mod R {}
266        pub mod W {}
267        pub mod RW {
268            #[doc = "sai2.MCLK is input signal"]
269            pub const SAI2_MCLK_DIR_0: u32 = 0;
270            #[doc = "sai2.MCLK is output signal"]
271            pub const SAI2_MCLK_DIR_1: u32 = 0x01;
272        }
273    }
274    #[doc = "sai3.MCLK signal direction control"]
275    pub mod SAI3_MCLK_DIR {
276        pub const offset: u32 = 21;
277        pub const mask: u32 = 0x01 << offset;
278        pub mod R {}
279        pub mod W {}
280        pub mod RW {
281            #[doc = "sai3.MCLK is input signal"]
282            pub const SAI3_MCLK_DIR_0: u32 = 0;
283            #[doc = "sai3.MCLK is output signal"]
284            pub const SAI3_MCLK_DIR_1: u32 = 0x01;
285        }
286    }
287    #[doc = "Exclusive monitor response select of illegal command"]
288    pub mod EXC_MON {
289        pub const offset: u32 = 22;
290        pub const mask: u32 = 0x01 << offset;
291        pub mod R {}
292        pub mod W {}
293        pub mod RW {
294            #[doc = "OKAY response"]
295            pub const EXC_MON_0: u32 = 0;
296            #[doc = "SLVError response (default)"]
297            pub const EXC_MON_1: u32 = 0x01;
298        }
299    }
300    #[doc = "ENET and ENET2 ipg_clk_s clock gating enable"]
301    pub mod ENET_IPG_CLK_S_EN {
302        pub const offset: u32 = 23;
303        pub const mask: u32 = 0x01 << offset;
304        pub mod R {}
305        pub mod W {}
306        pub mod RW {
307            #[doc = "ipg_clk_s is gated when there is no IPS access"]
308            pub const ENET_IPG_CLK_S_EN_0: u32 = 0;
309            #[doc = "ipg_clk_s is always on"]
310            pub const ENET_IPG_CLK_S_EN_1: u32 = 0x01;
311        }
312    }
313    #[doc = "ARM CM7 platform AHB clock enable"]
314    pub mod CM7_FORCE_HCLK_EN {
315        pub const offset: u32 = 31;
316        pub const mask: u32 = 0x01 << offset;
317        pub mod R {}
318        pub mod W {}
319        pub mod RW {
320            #[doc = "AHB clock is not running (gated)"]
321            pub const CM7_FORCE_HCLK_EN_0: u32 = 0;
322            #[doc = "AHB clock is running (enabled)"]
323            pub const CM7_FORCE_HCLK_EN_1: u32 = 0x01;
324        }
325    }
326}
327#[doc = "GPR2 General Purpose Register"]
328pub mod GPR2 {
329    #[doc = "AXBS_L AHBXL master has higher priority.Do not set both DMA and AHBXL to high priority."]
330    pub mod AXBS_L_AHBXL_HIGH_PRIORITY {
331        pub const offset: u32 = 0;
332        pub const mask: u32 = 0x01 << offset;
333        pub mod R {}
334        pub mod W {}
335        pub mod RW {
336            #[doc = "AXBS_L AHBXL master does not have high priority"]
337            pub const AXBS_L_AHBXL_HIGH_PRIORITY_0: u32 = 0;
338            #[doc = "AXBS_P AHBXL master has high priority"]
339            pub const AXBS_L_AHBXL_HIGH_PRIORITY_1: u32 = 0x01;
340        }
341    }
342    #[doc = "AXBS_L DMA master has higher priority.Do not set both DMA and AHBXL to high priority."]
343    pub mod AXBS_L_DMA_HIGH_PRIORITY {
344        pub const offset: u32 = 1;
345        pub const mask: u32 = 0x01 << offset;
346        pub mod R {}
347        pub mod W {}
348        pub mod RW {
349            #[doc = "AXBS_L DMA master does not have high priority"]
350            pub const AXBS_L_DMA_HIGH_PRIORITY_0: u32 = 0;
351            #[doc = "AXBS_L DMA master has high priority"]
352            pub const AXBS_L_DMA_HIGH_PRIORITY_1: u32 = 0x01;
353        }
354    }
355    #[doc = "Force Round Robin in AXBS_L"]
356    pub mod AXBS_L_FORCE_ROUND_ROBIN {
357        pub const offset: u32 = 2;
358        pub const mask: u32 = 0x01 << offset;
359        pub mod R {}
360        pub mod W {}
361        pub mod RW {
362            #[doc = "AXBS_L masters are not arbitored in round robin, depending on DMA and AHBXL master priority settings."]
363            pub const AXBS_L_FORCE_ROUND_ROBIN_0: u32 = 0;
364            #[doc = "AXBS_L masters are arbitored in round robin"]
365            pub const AXBS_L_FORCE_ROUND_ROBIN_1: u32 = 0x01;
366        }
367    }
368    #[doc = "AXBS_P M0 master has higher priority.Do not set both M1 and M0 to high priority."]
369    pub mod AXBS_P_M0_HIGH_PRIORITY {
370        pub const offset: u32 = 3;
371        pub const mask: u32 = 0x01 << offset;
372        pub mod R {}
373        pub mod W {}
374        pub mod RW {
375            #[doc = "AXBS_P M0 master doesn't have high priority"]
376            pub const AXBS_P_M0_HIGH_PRIORITY_0: u32 = 0;
377            #[doc = "AXBS_P M0 master has high priority"]
378            pub const AXBS_P_M0_HIGH_PRIORITY_1: u32 = 0x01;
379        }
380    }
381    #[doc = "AXBS_P M1 master has higher priority.Do not set both M1 and M0 to high priority."]
382    pub mod AXBS_P_M1_HIGH_PRIORITY {
383        pub const offset: u32 = 4;
384        pub const mask: u32 = 0x01 << offset;
385        pub mod R {}
386        pub mod W {}
387        pub mod RW {
388            #[doc = "AXBS_P M1 master does not have high priority"]
389            pub const AXBS_P_M1_HIGH_PRIORITY_0: u32 = 0;
390            #[doc = "AXBS_P M1 master has high priority"]
391            pub const AXBS_P_M1_HIGH_PRIORITY_1: u32 = 0x01;
392        }
393    }
394    #[doc = "Force Round Robin in AXBS_P. This bit can override master M0 M1 high priority configuration."]
395    pub mod AXBS_P_FORCE_ROUND_ROBIN {
396        pub const offset: u32 = 5;
397        pub const mask: u32 = 0x01 << offset;
398        pub mod R {}
399        pub mod W {}
400        pub mod RW {
401            #[doc = "AXBS_P masters are not arbitored in round robin, depending on M0/M1 master priority settings."]
402            pub const AXBS_P_FORCE_ROUND_ROBIN_0: u32 = 0;
403            #[doc = "AXBS_P masters are arbitored in round robin"]
404            pub const AXBS_P_FORCE_ROUND_ROBIN_1: u32 = 0x01;
405        }
406    }
407    #[doc = "Disable CANFD filter"]
408    pub mod CANFD_FILTER_BYPASS {
409        pub const offset: u32 = 6;
410        pub const mask: u32 = 0x01 << offset;
411        pub mod R {}
412        pub mod W {}
413        pub mod RW {
414            #[doc = "enable CANFD filter"]
415            pub const CANFD_FILTER_BYPASS_0: u32 = 0;
416            #[doc = "disable CANFD filter"]
417            pub const CANFD_FILTER_BYPASS_1: u32 = 0x01;
418        }
419    }
420    #[doc = "enable power saving features on L2 memory"]
421    pub mod L2_MEM_EN_POWERSAVING {
422        pub const offset: u32 = 12;
423        pub const mask: u32 = 0x01 << offset;
424        pub mod R {}
425        pub mod W {}
426        pub mod RW {
427            #[doc = "none memory power saving features enabled, SHUTDOWN/DEEPSLEEP/LIGHTSLEEP will have no effect"]
428            pub const L2_MEM_EN_POWERSAVING_0: u32 = 0;
429            #[doc = "memory power saving features enabled, set SHUTDOWN/DEEPSLEEP/LIGHTSLEEP (priority high to low) to enable power saving levels"]
430            pub const L2_MEM_EN_POWERSAVING_1: u32 = 0x01;
431        }
432    }
433    #[doc = "Automatically gate off RAM clock when RAM is not accessed."]
434    pub mod RAM_AUTO_CLK_GATING_EN {
435        pub const offset: u32 = 13;
436        pub const mask: u32 = 0x01 << offset;
437        pub mod R {}
438        pub mod W {}
439        pub mod RW {
440            #[doc = "disable automatically gate off RAM clock"]
441            pub const RAM_AUTO_CLK_GATING_EN_0: u32 = 0;
442            #[doc = "enable automatically gate off RAM clock"]
443            pub const RAM_AUTO_CLK_GATING_EN_1: u32 = 0x01;
444        }
445    }
446    #[doc = "control how memory enter Deep Sleep mode (shutdown periphery power, but maintain memory contents, outputs of memory are pulled low)"]
447    pub mod L2_MEM_DEEPSLEEP {
448        pub const offset: u32 = 14;
449        pub const mask: u32 = 0x01 << offset;
450        pub mod R {}
451        pub mod W {}
452        pub mod RW {
453            #[doc = "no force sleep control supported, memory deep sleep mode only entered when whole system in stop mode"]
454            pub const L2_MEM_DEEPSLEEP_0: u32 = 0;
455            #[doc = "force memory into deep sleep mode"]
456            pub const L2_MEM_DEEPSLEEP_1: u32 = 0x01;
457        }
458    }
459    #[doc = "Divider ratio control for mclk from hmclk. mclk frequency = 1/(n+1) * hmclk frequency."]
460    pub mod MQS_CLK_DIV {
461        pub const offset: u32 = 16;
462        pub const mask: u32 = 0xff << offset;
463        pub mod R {}
464        pub mod W {}
465        pub mod RW {
466            #[doc = "mclk frequency = 1/1 * hmclk frequency"]
467            pub const DIVIDE_1: u32 = 0;
468            #[doc = "mclk frequency = 1/2 * hmclk frequency"]
469            pub const DIVIDE_2: u32 = 0x01;
470            #[doc = "mclk frequency = 1/3 * hmclk frequency"]
471            pub const DIVIDE_3: u32 = 0x02;
472            #[doc = "mclk frequency = 1/4 * hmclk frequency"]
473            pub const DIVIDE_4: u32 = 0x03;
474            #[doc = "mclk frequency = 1/5 * hmclk frequency"]
475            pub const DIVIDE_5: u32 = 0x04;
476            #[doc = "mclk frequency = 1/6 * hmclk frequency"]
477            pub const DIVIDE_6: u32 = 0x05;
478            #[doc = "mclk frequency = 1/7 * hmclk frequency"]
479            pub const DIVIDE_7: u32 = 0x06;
480            #[doc = "mclk frequency = 1/8 * hmclk frequency"]
481            pub const DIVIDE_8: u32 = 0x07;
482            #[doc = "mclk frequency = 1/9 * hmclk frequency"]
483            pub const DIVIDE_9: u32 = 0x08;
484            #[doc = "mclk frequency = 1/10 * hmclk frequency"]
485            pub const DIVIDE_10: u32 = 0x09;
486            #[doc = "mclk frequency = 1/11 * hmclk frequency"]
487            pub const DIVIDE_11: u32 = 0x0a;
488            #[doc = "mclk frequency = 1/12 * hmclk frequency"]
489            pub const DIVIDE_12: u32 = 0x0b;
490            #[doc = "mclk frequency = 1/13 * hmclk frequency"]
491            pub const DIVIDE_13: u32 = 0x0c;
492            #[doc = "mclk frequency = 1/14 * hmclk frequency"]
493            pub const DIVIDE_14: u32 = 0x0d;
494            #[doc = "mclk frequency = 1/15 * hmclk frequency"]
495            pub const DIVIDE_15: u32 = 0x0e;
496            #[doc = "mclk frequency = 1/16 * hmclk frequency"]
497            pub const DIVIDE_16: u32 = 0x0f;
498            #[doc = "mclk frequency = 1/17 * hmclk frequency"]
499            pub const DIVIDE_17: u32 = 0x10;
500            #[doc = "mclk frequency = 1/18 * hmclk frequency"]
501            pub const DIVIDE_18: u32 = 0x11;
502            #[doc = "mclk frequency = 1/19 * hmclk frequency"]
503            pub const DIVIDE_19: u32 = 0x12;
504            #[doc = "mclk frequency = 1/20 * hmclk frequency"]
505            pub const DIVIDE_20: u32 = 0x13;
506            #[doc = "mclk frequency = 1/21 * hmclk frequency"]
507            pub const DIVIDE_21: u32 = 0x14;
508            #[doc = "mclk frequency = 1/22 * hmclk frequency"]
509            pub const DIVIDE_22: u32 = 0x15;
510            #[doc = "mclk frequency = 1/23 * hmclk frequency"]
511            pub const DIVIDE_23: u32 = 0x16;
512            #[doc = "mclk frequency = 1/24 * hmclk frequency"]
513            pub const DIVIDE_24: u32 = 0x17;
514            #[doc = "mclk frequency = 1/25 * hmclk frequency"]
515            pub const DIVIDE_25: u32 = 0x18;
516            #[doc = "mclk frequency = 1/26 * hmclk frequency"]
517            pub const DIVIDE_26: u32 = 0x19;
518            #[doc = "mclk frequency = 1/27 * hmclk frequency"]
519            pub const DIVIDE_27: u32 = 0x1a;
520            #[doc = "mclk frequency = 1/28 * hmclk frequency"]
521            pub const DIVIDE_28: u32 = 0x1b;
522            #[doc = "mclk frequency = 1/29 * hmclk frequency"]
523            pub const DIVIDE_29: u32 = 0x1c;
524            #[doc = "mclk frequency = 1/30 * hmclk frequency"]
525            pub const DIVIDE_30: u32 = 0x1d;
526            #[doc = "mclk frequency = 1/31 * hmclk frequency"]
527            pub const DIVIDE_31: u32 = 0x1e;
528            #[doc = "mclk frequency = 1/32 * hmclk frequency"]
529            pub const DIVIDE_32: u32 = 0x1f;
530            #[doc = "mclk frequency = 1/33 * hmclk frequency"]
531            pub const DIVIDE_33: u32 = 0x20;
532            #[doc = "mclk frequency = 1/34 * hmclk frequency"]
533            pub const DIVIDE_34: u32 = 0x21;
534            #[doc = "mclk frequency = 1/35 * hmclk frequency"]
535            pub const DIVIDE_35: u32 = 0x22;
536            #[doc = "mclk frequency = 1/36 * hmclk frequency"]
537            pub const DIVIDE_36: u32 = 0x23;
538            #[doc = "mclk frequency = 1/37 * hmclk frequency"]
539            pub const DIVIDE_37: u32 = 0x24;
540            #[doc = "mclk frequency = 1/38 * hmclk frequency"]
541            pub const DIVIDE_38: u32 = 0x25;
542            #[doc = "mclk frequency = 1/39 * hmclk frequency"]
543            pub const DIVIDE_39: u32 = 0x26;
544            #[doc = "mclk frequency = 1/40 * hmclk frequency"]
545            pub const DIVIDE_40: u32 = 0x27;
546            #[doc = "mclk frequency = 1/41 * hmclk frequency"]
547            pub const DIVIDE_41: u32 = 0x28;
548            #[doc = "mclk frequency = 1/42 * hmclk frequency"]
549            pub const DIVIDE_42: u32 = 0x29;
550            #[doc = "mclk frequency = 1/43 * hmclk frequency"]
551            pub const DIVIDE_43: u32 = 0x2a;
552            #[doc = "mclk frequency = 1/44 * hmclk frequency"]
553            pub const DIVIDE_44: u32 = 0x2b;
554            #[doc = "mclk frequency = 1/45 * hmclk frequency"]
555            pub const DIVIDE_45: u32 = 0x2c;
556            #[doc = "mclk frequency = 1/46 * hmclk frequency"]
557            pub const DIVIDE_46: u32 = 0x2d;
558            #[doc = "mclk frequency = 1/47 * hmclk frequency"]
559            pub const DIVIDE_47: u32 = 0x2e;
560            #[doc = "mclk frequency = 1/48 * hmclk frequency"]
561            pub const DIVIDE_48: u32 = 0x2f;
562            #[doc = "mclk frequency = 1/49 * hmclk frequency"]
563            pub const DIVIDE_49: u32 = 0x30;
564            #[doc = "mclk frequency = 1/50 * hmclk frequency"]
565            pub const DIVIDE_50: u32 = 0x31;
566            #[doc = "mclk frequency = 1/51 * hmclk frequency"]
567            pub const DIVIDE_51: u32 = 0x32;
568            #[doc = "mclk frequency = 1/52 * hmclk frequency"]
569            pub const DIVIDE_52: u32 = 0x33;
570            #[doc = "mclk frequency = 1/53 * hmclk frequency"]
571            pub const DIVIDE_53: u32 = 0x34;
572            #[doc = "mclk frequency = 1/54 * hmclk frequency"]
573            pub const DIVIDE_54: u32 = 0x35;
574            #[doc = "mclk frequency = 1/55 * hmclk frequency"]
575            pub const DIVIDE_55: u32 = 0x36;
576            #[doc = "mclk frequency = 1/56 * hmclk frequency"]
577            pub const DIVIDE_56: u32 = 0x37;
578            #[doc = "mclk frequency = 1/57 * hmclk frequency"]
579            pub const DIVIDE_57: u32 = 0x38;
580            #[doc = "mclk frequency = 1/58 * hmclk frequency"]
581            pub const DIVIDE_58: u32 = 0x39;
582            #[doc = "mclk frequency = 1/59 * hmclk frequency"]
583            pub const DIVIDE_59: u32 = 0x3a;
584            #[doc = "mclk frequency = 1/60 * hmclk frequency"]
585            pub const DIVIDE_60: u32 = 0x3b;
586            #[doc = "mclk frequency = 1/61 * hmclk frequency"]
587            pub const DIVIDE_61: u32 = 0x3c;
588            #[doc = "mclk frequency = 1/62 * hmclk frequency"]
589            pub const DIVIDE_62: u32 = 0x3d;
590            #[doc = "mclk frequency = 1/63 * hmclk frequency"]
591            pub const DIVIDE_63: u32 = 0x3e;
592            #[doc = "mclk frequency = 1/64 * hmclk frequency"]
593            pub const DIVIDE_64: u32 = 0x3f;
594            #[doc = "mclk frequency = 1/65 * hmclk frequency"]
595            pub const DIVIDE_65: u32 = 0x40;
596            #[doc = "mclk frequency = 1/66 * hmclk frequency"]
597            pub const DIVIDE_66: u32 = 0x41;
598            #[doc = "mclk frequency = 1/67 * hmclk frequency"]
599            pub const DIVIDE_67: u32 = 0x42;
600            #[doc = "mclk frequency = 1/68 * hmclk frequency"]
601            pub const DIVIDE_68: u32 = 0x43;
602            #[doc = "mclk frequency = 1/69 * hmclk frequency"]
603            pub const DIVIDE_69: u32 = 0x44;
604            #[doc = "mclk frequency = 1/70 * hmclk frequency"]
605            pub const DIVIDE_70: u32 = 0x45;
606            #[doc = "mclk frequency = 1/71 * hmclk frequency"]
607            pub const DIVIDE_71: u32 = 0x46;
608            #[doc = "mclk frequency = 1/72 * hmclk frequency"]
609            pub const DIVIDE_72: u32 = 0x47;
610            #[doc = "mclk frequency = 1/73 * hmclk frequency"]
611            pub const DIVIDE_73: u32 = 0x48;
612            #[doc = "mclk frequency = 1/74 * hmclk frequency"]
613            pub const DIVIDE_74: u32 = 0x49;
614            #[doc = "mclk frequency = 1/75 * hmclk frequency"]
615            pub const DIVIDE_75: u32 = 0x4a;
616            #[doc = "mclk frequency = 1/76 * hmclk frequency"]
617            pub const DIVIDE_76: u32 = 0x4b;
618            #[doc = "mclk frequency = 1/77 * hmclk frequency"]
619            pub const DIVIDE_77: u32 = 0x4c;
620            #[doc = "mclk frequency = 1/78 * hmclk frequency"]
621            pub const DIVIDE_78: u32 = 0x4d;
622            #[doc = "mclk frequency = 1/79 * hmclk frequency"]
623            pub const DIVIDE_79: u32 = 0x4e;
624            #[doc = "mclk frequency = 1/80 * hmclk frequency"]
625            pub const DIVIDE_80: u32 = 0x4f;
626            #[doc = "mclk frequency = 1/81 * hmclk frequency"]
627            pub const DIVIDE_81: u32 = 0x50;
628            #[doc = "mclk frequency = 1/82 * hmclk frequency"]
629            pub const DIVIDE_82: u32 = 0x51;
630            #[doc = "mclk frequency = 1/83 * hmclk frequency"]
631            pub const DIVIDE_83: u32 = 0x52;
632            #[doc = "mclk frequency = 1/84 * hmclk frequency"]
633            pub const DIVIDE_84: u32 = 0x53;
634            #[doc = "mclk frequency = 1/85 * hmclk frequency"]
635            pub const DIVIDE_85: u32 = 0x54;
636            #[doc = "mclk frequency = 1/86 * hmclk frequency"]
637            pub const DIVIDE_86: u32 = 0x55;
638            #[doc = "mclk frequency = 1/87 * hmclk frequency"]
639            pub const DIVIDE_87: u32 = 0x56;
640            #[doc = "mclk frequency = 1/88 * hmclk frequency"]
641            pub const DIVIDE_88: u32 = 0x57;
642            #[doc = "mclk frequency = 1/89 * hmclk frequency"]
643            pub const DIVIDE_89: u32 = 0x58;
644            #[doc = "mclk frequency = 1/90 * hmclk frequency"]
645            pub const DIVIDE_90: u32 = 0x59;
646            #[doc = "mclk frequency = 1/91 * hmclk frequency"]
647            pub const DIVIDE_91: u32 = 0x5a;
648            #[doc = "mclk frequency = 1/92 * hmclk frequency"]
649            pub const DIVIDE_92: u32 = 0x5b;
650            #[doc = "mclk frequency = 1/93 * hmclk frequency"]
651            pub const DIVIDE_93: u32 = 0x5c;
652            #[doc = "mclk frequency = 1/94 * hmclk frequency"]
653            pub const DIVIDE_94: u32 = 0x5d;
654            #[doc = "mclk frequency = 1/95 * hmclk frequency"]
655            pub const DIVIDE_95: u32 = 0x5e;
656            #[doc = "mclk frequency = 1/96 * hmclk frequency"]
657            pub const DIVIDE_96: u32 = 0x5f;
658            #[doc = "mclk frequency = 1/97 * hmclk frequency"]
659            pub const DIVIDE_97: u32 = 0x60;
660            #[doc = "mclk frequency = 1/98 * hmclk frequency"]
661            pub const DIVIDE_98: u32 = 0x61;
662            #[doc = "mclk frequency = 1/99 * hmclk frequency"]
663            pub const DIVIDE_99: u32 = 0x62;
664            #[doc = "mclk frequency = 1/100 * hmclk frequency"]
665            pub const DIVIDE_100: u32 = 0x63;
666            #[doc = "mclk frequency = 1/101 * hmclk frequency"]
667            pub const DIVIDE_101: u32 = 0x64;
668            #[doc = "mclk frequency = 1/102 * hmclk frequency"]
669            pub const DIVIDE_102: u32 = 0x65;
670            #[doc = "mclk frequency = 1/103 * hmclk frequency"]
671            pub const DIVIDE_103: u32 = 0x66;
672            #[doc = "mclk frequency = 1/104 * hmclk frequency"]
673            pub const DIVIDE_104: u32 = 0x67;
674            #[doc = "mclk frequency = 1/105 * hmclk frequency"]
675            pub const DIVIDE_105: u32 = 0x68;
676            #[doc = "mclk frequency = 1/106 * hmclk frequency"]
677            pub const DIVIDE_106: u32 = 0x69;
678            #[doc = "mclk frequency = 1/107 * hmclk frequency"]
679            pub const DIVIDE_107: u32 = 0x6a;
680            #[doc = "mclk frequency = 1/108 * hmclk frequency"]
681            pub const DIVIDE_108: u32 = 0x6b;
682            #[doc = "mclk frequency = 1/109 * hmclk frequency"]
683            pub const DIVIDE_109: u32 = 0x6c;
684            #[doc = "mclk frequency = 1/110 * hmclk frequency"]
685            pub const DIVIDE_110: u32 = 0x6d;
686            #[doc = "mclk frequency = 1/111 * hmclk frequency"]
687            pub const DIVIDE_111: u32 = 0x6e;
688            #[doc = "mclk frequency = 1/112 * hmclk frequency"]
689            pub const DIVIDE_112: u32 = 0x6f;
690            #[doc = "mclk frequency = 1/113 * hmclk frequency"]
691            pub const DIVIDE_113: u32 = 0x70;
692            #[doc = "mclk frequency = 1/114 * hmclk frequency"]
693            pub const DIVIDE_114: u32 = 0x71;
694            #[doc = "mclk frequency = 1/115 * hmclk frequency"]
695            pub const DIVIDE_115: u32 = 0x72;
696            #[doc = "mclk frequency = 1/116 * hmclk frequency"]
697            pub const DIVIDE_116: u32 = 0x73;
698            #[doc = "mclk frequency = 1/117 * hmclk frequency"]
699            pub const DIVIDE_117: u32 = 0x74;
700            #[doc = "mclk frequency = 1/118 * hmclk frequency"]
701            pub const DIVIDE_118: u32 = 0x75;
702            #[doc = "mclk frequency = 1/119 * hmclk frequency"]
703            pub const DIVIDE_119: u32 = 0x76;
704            #[doc = "mclk frequency = 1/120 * hmclk frequency"]
705            pub const DIVIDE_120: u32 = 0x77;
706            #[doc = "mclk frequency = 1/121 * hmclk frequency"]
707            pub const DIVIDE_121: u32 = 0x78;
708            #[doc = "mclk frequency = 1/122 * hmclk frequency"]
709            pub const DIVIDE_122: u32 = 0x79;
710            #[doc = "mclk frequency = 1/123 * hmclk frequency"]
711            pub const DIVIDE_123: u32 = 0x7a;
712            #[doc = "mclk frequency = 1/124 * hmclk frequency"]
713            pub const DIVIDE_124: u32 = 0x7b;
714            #[doc = "mclk frequency = 1/125 * hmclk frequency"]
715            pub const DIVIDE_125: u32 = 0x7c;
716            #[doc = "mclk frequency = 1/126 * hmclk frequency"]
717            pub const DIVIDE_126: u32 = 0x7d;
718            #[doc = "mclk frequency = 1/127 * hmclk frequency"]
719            pub const DIVIDE_127: u32 = 0x7e;
720            #[doc = "mclk frequency = 1/128 * hmclk frequency"]
721            pub const DIVIDE_128: u32 = 0x7f;
722            #[doc = "mclk frequency = 1/129 * hmclk frequency"]
723            pub const DIVIDE_129: u32 = 0x80;
724            #[doc = "mclk frequency = 1/130 * hmclk frequency"]
725            pub const DIVIDE_130: u32 = 0x81;
726            #[doc = "mclk frequency = 1/131 * hmclk frequency"]
727            pub const DIVIDE_131: u32 = 0x82;
728            #[doc = "mclk frequency = 1/132 * hmclk frequency"]
729            pub const DIVIDE_132: u32 = 0x83;
730            #[doc = "mclk frequency = 1/133 * hmclk frequency"]
731            pub const DIVIDE_133: u32 = 0x84;
732            #[doc = "mclk frequency = 1/134 * hmclk frequency"]
733            pub const DIVIDE_134: u32 = 0x85;
734            #[doc = "mclk frequency = 1/135 * hmclk frequency"]
735            pub const DIVIDE_135: u32 = 0x86;
736            #[doc = "mclk frequency = 1/136 * hmclk frequency"]
737            pub const DIVIDE_136: u32 = 0x87;
738            #[doc = "mclk frequency = 1/137 * hmclk frequency"]
739            pub const DIVIDE_137: u32 = 0x88;
740            #[doc = "mclk frequency = 1/138 * hmclk frequency"]
741            pub const DIVIDE_138: u32 = 0x89;
742            #[doc = "mclk frequency = 1/139 * hmclk frequency"]
743            pub const DIVIDE_139: u32 = 0x8a;
744            #[doc = "mclk frequency = 1/140 * hmclk frequency"]
745            pub const DIVIDE_140: u32 = 0x8b;
746            #[doc = "mclk frequency = 1/141 * hmclk frequency"]
747            pub const DIVIDE_141: u32 = 0x8c;
748            #[doc = "mclk frequency = 1/142 * hmclk frequency"]
749            pub const DIVIDE_142: u32 = 0x8d;
750            #[doc = "mclk frequency = 1/143 * hmclk frequency"]
751            pub const DIVIDE_143: u32 = 0x8e;
752            #[doc = "mclk frequency = 1/144 * hmclk frequency"]
753            pub const DIVIDE_144: u32 = 0x8f;
754            #[doc = "mclk frequency = 1/145 * hmclk frequency"]
755            pub const DIVIDE_145: u32 = 0x90;
756            #[doc = "mclk frequency = 1/146 * hmclk frequency"]
757            pub const DIVIDE_146: u32 = 0x91;
758            #[doc = "mclk frequency = 1/147 * hmclk frequency"]
759            pub const DIVIDE_147: u32 = 0x92;
760            #[doc = "mclk frequency = 1/148 * hmclk frequency"]
761            pub const DIVIDE_148: u32 = 0x93;
762            #[doc = "mclk frequency = 1/149 * hmclk frequency"]
763            pub const DIVIDE_149: u32 = 0x94;
764            #[doc = "mclk frequency = 1/150 * hmclk frequency"]
765            pub const DIVIDE_150: u32 = 0x95;
766            #[doc = "mclk frequency = 1/151 * hmclk frequency"]
767            pub const DIVIDE_151: u32 = 0x96;
768            #[doc = "mclk frequency = 1/152 * hmclk frequency"]
769            pub const DIVIDE_152: u32 = 0x97;
770            #[doc = "mclk frequency = 1/153 * hmclk frequency"]
771            pub const DIVIDE_153: u32 = 0x98;
772            #[doc = "mclk frequency = 1/154 * hmclk frequency"]
773            pub const DIVIDE_154: u32 = 0x99;
774            #[doc = "mclk frequency = 1/155 * hmclk frequency"]
775            pub const DIVIDE_155: u32 = 0x9a;
776            #[doc = "mclk frequency = 1/156 * hmclk frequency"]
777            pub const DIVIDE_156: u32 = 0x9b;
778            #[doc = "mclk frequency = 1/157 * hmclk frequency"]
779            pub const DIVIDE_157: u32 = 0x9c;
780            #[doc = "mclk frequency = 1/158 * hmclk frequency"]
781            pub const DIVIDE_158: u32 = 0x9d;
782            #[doc = "mclk frequency = 1/159 * hmclk frequency"]
783            pub const DIVIDE_159: u32 = 0x9e;
784            #[doc = "mclk frequency = 1/160 * hmclk frequency"]
785            pub const DIVIDE_160: u32 = 0x9f;
786            #[doc = "mclk frequency = 1/161 * hmclk frequency"]
787            pub const DIVIDE_161: u32 = 0xa0;
788            #[doc = "mclk frequency = 1/162 * hmclk frequency"]
789            pub const DIVIDE_162: u32 = 0xa1;
790            #[doc = "mclk frequency = 1/163 * hmclk frequency"]
791            pub const DIVIDE_163: u32 = 0xa2;
792            #[doc = "mclk frequency = 1/164 * hmclk frequency"]
793            pub const DIVIDE_164: u32 = 0xa3;
794            #[doc = "mclk frequency = 1/165 * hmclk frequency"]
795            pub const DIVIDE_165: u32 = 0xa4;
796            #[doc = "mclk frequency = 1/166 * hmclk frequency"]
797            pub const DIVIDE_166: u32 = 0xa5;
798            #[doc = "mclk frequency = 1/167 * hmclk frequency"]
799            pub const DIVIDE_167: u32 = 0xa6;
800            #[doc = "mclk frequency = 1/168 * hmclk frequency"]
801            pub const DIVIDE_168: u32 = 0xa7;
802            #[doc = "mclk frequency = 1/169 * hmclk frequency"]
803            pub const DIVIDE_169: u32 = 0xa8;
804            #[doc = "mclk frequency = 1/170 * hmclk frequency"]
805            pub const DIVIDE_170: u32 = 0xa9;
806            #[doc = "mclk frequency = 1/171 * hmclk frequency"]
807            pub const DIVIDE_171: u32 = 0xaa;
808            #[doc = "mclk frequency = 1/172 * hmclk frequency"]
809            pub const DIVIDE_172: u32 = 0xab;
810            #[doc = "mclk frequency = 1/173 * hmclk frequency"]
811            pub const DIVIDE_173: u32 = 0xac;
812            #[doc = "mclk frequency = 1/174 * hmclk frequency"]
813            pub const DIVIDE_174: u32 = 0xad;
814            #[doc = "mclk frequency = 1/175 * hmclk frequency"]
815            pub const DIVIDE_175: u32 = 0xae;
816            #[doc = "mclk frequency = 1/176 * hmclk frequency"]
817            pub const DIVIDE_176: u32 = 0xaf;
818            #[doc = "mclk frequency = 1/177 * hmclk frequency"]
819            pub const DIVIDE_177: u32 = 0xb0;
820            #[doc = "mclk frequency = 1/178 * hmclk frequency"]
821            pub const DIVIDE_178: u32 = 0xb1;
822            #[doc = "mclk frequency = 1/179 * hmclk frequency"]
823            pub const DIVIDE_179: u32 = 0xb2;
824            #[doc = "mclk frequency = 1/180 * hmclk frequency"]
825            pub const DIVIDE_180: u32 = 0xb3;
826            #[doc = "mclk frequency = 1/181 * hmclk frequency"]
827            pub const DIVIDE_181: u32 = 0xb4;
828            #[doc = "mclk frequency = 1/182 * hmclk frequency"]
829            pub const DIVIDE_182: u32 = 0xb5;
830            #[doc = "mclk frequency = 1/183 * hmclk frequency"]
831            pub const DIVIDE_183: u32 = 0xb6;
832            #[doc = "mclk frequency = 1/184 * hmclk frequency"]
833            pub const DIVIDE_184: u32 = 0xb7;
834            #[doc = "mclk frequency = 1/185 * hmclk frequency"]
835            pub const DIVIDE_185: u32 = 0xb8;
836            #[doc = "mclk frequency = 1/186 * hmclk frequency"]
837            pub const DIVIDE_186: u32 = 0xb9;
838            #[doc = "mclk frequency = 1/187 * hmclk frequency"]
839            pub const DIVIDE_187: u32 = 0xba;
840            #[doc = "mclk frequency = 1/188 * hmclk frequency"]
841            pub const DIVIDE_188: u32 = 0xbb;
842            #[doc = "mclk frequency = 1/189 * hmclk frequency"]
843            pub const DIVIDE_189: u32 = 0xbc;
844            #[doc = "mclk frequency = 1/190 * hmclk frequency"]
845            pub const DIVIDE_190: u32 = 0xbd;
846            #[doc = "mclk frequency = 1/191 * hmclk frequency"]
847            pub const DIVIDE_191: u32 = 0xbe;
848            #[doc = "mclk frequency = 1/192 * hmclk frequency"]
849            pub const DIVIDE_192: u32 = 0xbf;
850            #[doc = "mclk frequency = 1/193 * hmclk frequency"]
851            pub const DIVIDE_193: u32 = 0xc0;
852            #[doc = "mclk frequency = 1/194 * hmclk frequency"]
853            pub const DIVIDE_194: u32 = 0xc1;
854            #[doc = "mclk frequency = 1/195 * hmclk frequency"]
855            pub const DIVIDE_195: u32 = 0xc2;
856            #[doc = "mclk frequency = 1/196 * hmclk frequency"]
857            pub const DIVIDE_196: u32 = 0xc3;
858            #[doc = "mclk frequency = 1/197 * hmclk frequency"]
859            pub const DIVIDE_197: u32 = 0xc4;
860            #[doc = "mclk frequency = 1/198 * hmclk frequency"]
861            pub const DIVIDE_198: u32 = 0xc5;
862            #[doc = "mclk frequency = 1/199 * hmclk frequency"]
863            pub const DIVIDE_199: u32 = 0xc6;
864            #[doc = "mclk frequency = 1/200 * hmclk frequency"]
865            pub const DIVIDE_200: u32 = 0xc7;
866            #[doc = "mclk frequency = 1/201 * hmclk frequency"]
867            pub const DIVIDE_201: u32 = 0xc8;
868            #[doc = "mclk frequency = 1/202 * hmclk frequency"]
869            pub const DIVIDE_202: u32 = 0xc9;
870            #[doc = "mclk frequency = 1/203 * hmclk frequency"]
871            pub const DIVIDE_203: u32 = 0xca;
872            #[doc = "mclk frequency = 1/204 * hmclk frequency"]
873            pub const DIVIDE_204: u32 = 0xcb;
874            #[doc = "mclk frequency = 1/205 * hmclk frequency"]
875            pub const DIVIDE_205: u32 = 0xcc;
876            #[doc = "mclk frequency = 1/206 * hmclk frequency"]
877            pub const DIVIDE_206: u32 = 0xcd;
878            #[doc = "mclk frequency = 1/207 * hmclk frequency"]
879            pub const DIVIDE_207: u32 = 0xce;
880            #[doc = "mclk frequency = 1/208 * hmclk frequency"]
881            pub const DIVIDE_208: u32 = 0xcf;
882            #[doc = "mclk frequency = 1/209 * hmclk frequency"]
883            pub const DIVIDE_209: u32 = 0xd0;
884            #[doc = "mclk frequency = 1/210 * hmclk frequency"]
885            pub const DIVIDE_210: u32 = 0xd1;
886            #[doc = "mclk frequency = 1/211 * hmclk frequency"]
887            pub const DIVIDE_211: u32 = 0xd2;
888            #[doc = "mclk frequency = 1/212 * hmclk frequency"]
889            pub const DIVIDE_212: u32 = 0xd3;
890            #[doc = "mclk frequency = 1/213 * hmclk frequency"]
891            pub const DIVIDE_213: u32 = 0xd4;
892            #[doc = "mclk frequency = 1/214 * hmclk frequency"]
893            pub const DIVIDE_214: u32 = 0xd5;
894            #[doc = "mclk frequency = 1/215 * hmclk frequency"]
895            pub const DIVIDE_215: u32 = 0xd6;
896            #[doc = "mclk frequency = 1/216 * hmclk frequency"]
897            pub const DIVIDE_216: u32 = 0xd7;
898            #[doc = "mclk frequency = 1/217 * hmclk frequency"]
899            pub const DIVIDE_217: u32 = 0xd8;
900            #[doc = "mclk frequency = 1/218 * hmclk frequency"]
901            pub const DIVIDE_218: u32 = 0xd9;
902            #[doc = "mclk frequency = 1/219 * hmclk frequency"]
903            pub const DIVIDE_219: u32 = 0xda;
904            #[doc = "mclk frequency = 1/220 * hmclk frequency"]
905            pub const DIVIDE_220: u32 = 0xdb;
906            #[doc = "mclk frequency = 1/221 * hmclk frequency"]
907            pub const DIVIDE_221: u32 = 0xdc;
908            #[doc = "mclk frequency = 1/222 * hmclk frequency"]
909            pub const DIVIDE_222: u32 = 0xdd;
910            #[doc = "mclk frequency = 1/223 * hmclk frequency"]
911            pub const DIVIDE_223: u32 = 0xde;
912            #[doc = "mclk frequency = 1/224 * hmclk frequency"]
913            pub const DIVIDE_224: u32 = 0xdf;
914            #[doc = "mclk frequency = 1/225 * hmclk frequency"]
915            pub const DIVIDE_225: u32 = 0xe0;
916            #[doc = "mclk frequency = 1/226 * hmclk frequency"]
917            pub const DIVIDE_226: u32 = 0xe1;
918            #[doc = "mclk frequency = 1/227 * hmclk frequency"]
919            pub const DIVIDE_227: u32 = 0xe2;
920            #[doc = "mclk frequency = 1/228 * hmclk frequency"]
921            pub const DIVIDE_228: u32 = 0xe3;
922            #[doc = "mclk frequency = 1/229 * hmclk frequency"]
923            pub const DIVIDE_229: u32 = 0xe4;
924            #[doc = "mclk frequency = 1/230 * hmclk frequency"]
925            pub const DIVIDE_230: u32 = 0xe5;
926            #[doc = "mclk frequency = 1/231 * hmclk frequency"]
927            pub const DIVIDE_231: u32 = 0xe6;
928            #[doc = "mclk frequency = 1/232 * hmclk frequency"]
929            pub const DIVIDE_232: u32 = 0xe7;
930            #[doc = "mclk frequency = 1/233 * hmclk frequency"]
931            pub const DIVIDE_233: u32 = 0xe8;
932            #[doc = "mclk frequency = 1/234 * hmclk frequency"]
933            pub const DIVIDE_234: u32 = 0xe9;
934            #[doc = "mclk frequency = 1/235 * hmclk frequency"]
935            pub const DIVIDE_235: u32 = 0xea;
936            #[doc = "mclk frequency = 1/236 * hmclk frequency"]
937            pub const DIVIDE_236: u32 = 0xeb;
938            #[doc = "mclk frequency = 1/237 * hmclk frequency"]
939            pub const DIVIDE_237: u32 = 0xec;
940            #[doc = "mclk frequency = 1/238 * hmclk frequency"]
941            pub const DIVIDE_238: u32 = 0xed;
942            #[doc = "mclk frequency = 1/239 * hmclk frequency"]
943            pub const DIVIDE_239: u32 = 0xee;
944            #[doc = "mclk frequency = 1/240 * hmclk frequency"]
945            pub const DIVIDE_240: u32 = 0xef;
946            #[doc = "mclk frequency = 1/241 * hmclk frequency"]
947            pub const DIVIDE_241: u32 = 0xf0;
948            #[doc = "mclk frequency = 1/242 * hmclk frequency"]
949            pub const DIVIDE_242: u32 = 0xf1;
950            #[doc = "mclk frequency = 1/243 * hmclk frequency"]
951            pub const DIVIDE_243: u32 = 0xf2;
952            #[doc = "mclk frequency = 1/244 * hmclk frequency"]
953            pub const DIVIDE_244: u32 = 0xf3;
954            #[doc = "mclk frequency = 1/245 * hmclk frequency"]
955            pub const DIVIDE_245: u32 = 0xf4;
956            #[doc = "mclk frequency = 1/246 * hmclk frequency"]
957            pub const DIVIDE_246: u32 = 0xf5;
958            #[doc = "mclk frequency = 1/247 * hmclk frequency"]
959            pub const DIVIDE_247: u32 = 0xf6;
960            #[doc = "mclk frequency = 1/248 * hmclk frequency"]
961            pub const DIVIDE_248: u32 = 0xf7;
962            #[doc = "mclk frequency = 1/249 * hmclk frequency"]
963            pub const DIVIDE_249: u32 = 0xf8;
964            #[doc = "mclk frequency = 1/250 * hmclk frequency"]
965            pub const DIVIDE_250: u32 = 0xf9;
966            #[doc = "mclk frequency = 1/251 * hmclk frequency"]
967            pub const DIVIDE_251: u32 = 0xfa;
968            #[doc = "mclk frequency = 1/252 * hmclk frequency"]
969            pub const DIVIDE_252: u32 = 0xfb;
970            #[doc = "mclk frequency = 1/253 * hmclk frequency"]
971            pub const DIVIDE_253: u32 = 0xfc;
972            #[doc = "mclk frequency = 1/254 * hmclk frequency"]
973            pub const DIVIDE_254: u32 = 0xfd;
974            #[doc = "mclk frequency = 1/255 * hmclk frequency"]
975            pub const DIVIDE_255: u32 = 0xfe;
976            #[doc = "mclk frequency = 1/256 * hmclk frequency"]
977            pub const DIVIDE_256: u32 = 0xff;
978        }
979    }
980    #[doc = "MQS software reset"]
981    pub mod MQS_SW_RST {
982        pub const offset: u32 = 24;
983        pub const mask: u32 = 0x01 << offset;
984        pub mod R {}
985        pub mod W {}
986        pub mod RW {
987            #[doc = "Exit software reset for MQS"]
988            pub const MQS_SW_RST_0: u32 = 0;
989            #[doc = "Enable software reset for MQS"]
990            pub const MQS_SW_RST_1: u32 = 0x01;
991        }
992    }
993    #[doc = "MQS enable."]
994    pub mod MQS_EN {
995        pub const offset: u32 = 25;
996        pub const mask: u32 = 0x01 << offset;
997        pub mod R {}
998        pub mod W {}
999        pub mod RW {
1000            #[doc = "Disable MQS"]
1001            pub const MQS_EN_0: u32 = 0;
1002            #[doc = "Enable MQS"]
1003            pub const MQS_EN_1: u32 = 0x01;
1004        }
1005    }
1006    #[doc = "Used to control the PWM oversampling rate compared with mclk."]
1007    pub mod MQS_OVERSAMPLE {
1008        pub const offset: u32 = 26;
1009        pub const mask: u32 = 0x01 << offset;
1010        pub mod R {}
1011        pub mod W {}
1012        pub mod RW {
1013            #[doc = "32"]
1014            pub const MQS_OVERSAMPLE_0: u32 = 0;
1015            #[doc = "64"]
1016            pub const MQS_OVERSAMPLE_1: u32 = 0x01;
1017        }
1018    }
1019    #[doc = "QTIMER1 timer counter freeze"]
1020    pub mod QTIMER1_TMR_CNTS_FREEZE {
1021        pub const offset: u32 = 28;
1022        pub const mask: u32 = 0x01 << offset;
1023        pub mod R {}
1024        pub mod W {}
1025        pub mod RW {
1026            #[doc = "timer counter work normally"]
1027            pub const QTIMER1_TMR_CNTS_FREEZE_0: u32 = 0;
1028            #[doc = "reset counter and ouput flags"]
1029            pub const QTIMER1_TMR_CNTS_FREEZE_1: u32 = 0x01;
1030        }
1031    }
1032    #[doc = "QTIMER2 timer counter freeze"]
1033    pub mod QTIMER2_TMR_CNTS_FREEZE {
1034        pub const offset: u32 = 29;
1035        pub const mask: u32 = 0x01 << offset;
1036        pub mod R {}
1037        pub mod W {}
1038        pub mod RW {
1039            #[doc = "timer counter work normally"]
1040            pub const QTIMER2_TMR_CNTS_FREEZE_0: u32 = 0;
1041            #[doc = "reset counter and ouput flags"]
1042            pub const QTIMER2_TMR_CNTS_FREEZE_1: u32 = 0x01;
1043        }
1044    }
1045    #[doc = "QTIMER3 timer counter freeze"]
1046    pub mod QTIMER3_TMR_CNTS_FREEZE {
1047        pub const offset: u32 = 30;
1048        pub const mask: u32 = 0x01 << offset;
1049        pub mod R {}
1050        pub mod W {}
1051        pub mod RW {
1052            #[doc = "timer counter work normally"]
1053            pub const QTIMER3_TMR_CNTS_FREEZE_0: u32 = 0;
1054            #[doc = "reset counter and ouput flags"]
1055            pub const QTIMER3_TMR_CNTS_FREEZE_1: u32 = 0x01;
1056        }
1057    }
1058    #[doc = "QTIMER4 timer counter freeze"]
1059    pub mod QTIMER4_TMR_CNTS_FREEZE {
1060        pub const offset: u32 = 31;
1061        pub const mask: u32 = 0x01 << offset;
1062        pub mod R {}
1063        pub mod W {}
1064        pub mod RW {
1065            #[doc = "timer counter work normally"]
1066            pub const QTIMER4_TMR_CNTS_FREEZE_0: u32 = 0;
1067            #[doc = "reset counter and ouput flags"]
1068            pub const QTIMER4_TMR_CNTS_FREEZE_1: u32 = 0x01;
1069        }
1070    }
1071}
1072#[doc = "GPR3 General Purpose Register"]
1073pub mod GPR3 {
1074    #[doc = "OCRAM_CTL\\[3\\] - write address pipeline control bit"]
1075    pub mod OCRAM_CTL {
1076        pub const offset: u32 = 0;
1077        pub const mask: u32 = 0x0f << offset;
1078        pub mod R {}
1079        pub mod W {}
1080        pub mod RW {}
1081    }
1082    #[doc = "Select 128-bit dcp key from 256-bit key from snvs/ocotp"]
1083    pub mod DCP_KEY_SEL {
1084        pub const offset: u32 = 4;
1085        pub const mask: u32 = 0x01 << offset;
1086        pub mod R {}
1087        pub mod W {}
1088        pub mod RW {
1089            #[doc = "Select \\[127:0\\] from snvs/ocotp key as dcp key"]
1090            pub const DCP_KEY_SEL_0: u32 = 0;
1091            #[doc = "Select \\[255:128\\] from snvs/ocotp key as dcp key"]
1092            pub const DCP_KEY_SEL_1: u32 = 0x01;
1093        }
1094    }
1095    #[doc = "OCRAM2_CTL\\[3\\] - write address pipeline control bit"]
1096    pub mod OCRAM2_CTL {
1097        pub const offset: u32 = 8;
1098        pub const mask: u32 = 0x0f << offset;
1099        pub mod R {}
1100        pub mod W {}
1101        pub mod RW {}
1102    }
1103    #[doc = "Request to halt axbs_l"]
1104    pub mod AXBS_L_HALT_REQ {
1105        pub const offset: u32 = 15;
1106        pub const mask: u32 = 0x01 << offset;
1107        pub mod R {}
1108        pub mod W {}
1109        pub mod RW {
1110            #[doc = "axbs_l normal run"]
1111            pub const AXBS_L_HALT_REQ_0: u32 = 0;
1112            #[doc = "request to halt axbs_l"]
1113            pub const AXBS_L_HALT_REQ_1: u32 = 0x01;
1114        }
1115    }
1116    #[doc = "This field shows the OCRAM pipeline settings status, controlled by OCRAM_CTL bits respectively"]
1117    pub mod OCRAM_STATUS {
1118        pub const offset: u32 = 16;
1119        pub const mask: u32 = 0x0f << offset;
1120        pub mod R {}
1121        pub mod W {}
1122        pub mod RW {}
1123    }
1124    #[doc = "This field shows the OCRAM2 pipeline settings status, controlled by OCRAM2_CTL bits respectively"]
1125    pub mod OCRAM2_STATUS {
1126        pub const offset: u32 = 24;
1127        pub const mask: u32 = 0x0f << offset;
1128        pub mod R {}
1129        pub mod W {}
1130        pub mod RW {}
1131    }
1132    #[doc = "This bit shows the status of axbs_l"]
1133    pub mod AXBS_L_HALTED {
1134        pub const offset: u32 = 31;
1135        pub const mask: u32 = 0x01 << offset;
1136        pub mod R {}
1137        pub mod W {}
1138        pub mod RW {
1139            #[doc = "axbs_l is not halted"]
1140            pub const AXBS_L_HALTED_0: u32 = 0;
1141            #[doc = "axbs_l is in halted status"]
1142            pub const AXBS_L_HALTED_1: u32 = 0x01;
1143        }
1144    }
1145}
1146#[doc = "GPR4 General Purpose Register"]
1147pub mod GPR4 {
1148    #[doc = "EDMA stop request."]
1149    pub mod EDMA_STOP_REQ {
1150        pub const offset: u32 = 0;
1151        pub const mask: u32 = 0x01 << offset;
1152        pub mod R {}
1153        pub mod W {}
1154        pub mod RW {
1155            #[doc = "stop request off"]
1156            pub const EDMA_STOP_REQ_0: u32 = 0;
1157            #[doc = "stop request on"]
1158            pub const EDMA_STOP_REQ_1: u32 = 0x01;
1159        }
1160    }
1161    #[doc = "CAN1 stop request."]
1162    pub mod CAN1_STOP_REQ {
1163        pub const offset: u32 = 1;
1164        pub const mask: u32 = 0x01 << offset;
1165        pub mod R {}
1166        pub mod W {}
1167        pub mod RW {
1168            #[doc = "stop request off"]
1169            pub const CAN1_STOP_REQ_0: u32 = 0;
1170            #[doc = "stop request on"]
1171            pub const CAN1_STOP_REQ_1: u32 = 0x01;
1172        }
1173    }
1174    #[doc = "CAN2 stop request."]
1175    pub mod CAN2_STOP_REQ {
1176        pub const offset: u32 = 2;
1177        pub const mask: u32 = 0x01 << offset;
1178        pub mod R {}
1179        pub mod W {}
1180        pub mod RW {
1181            #[doc = "stop request off"]
1182            pub const CAN2_STOP_REQ_0: u32 = 0;
1183            #[doc = "stop request on"]
1184            pub const CAN2_STOP_REQ_1: u32 = 0x01;
1185        }
1186    }
1187    #[doc = "TRNG stop request."]
1188    pub mod TRNG_STOP_REQ {
1189        pub const offset: u32 = 3;
1190        pub const mask: u32 = 0x01 << offset;
1191        pub mod R {}
1192        pub mod W {}
1193        pub mod RW {
1194            #[doc = "stop request off"]
1195            pub const TRNG_STOP_REQ_0: u32 = 0;
1196            #[doc = "stop request on"]
1197            pub const TRNG_STOP_REQ_1: u32 = 0x01;
1198        }
1199    }
1200    #[doc = "ENET stop request."]
1201    pub mod ENET_STOP_REQ {
1202        pub const offset: u32 = 4;
1203        pub const mask: u32 = 0x01 << offset;
1204        pub mod R {}
1205        pub mod W {}
1206        pub mod RW {
1207            #[doc = "stop request off"]
1208            pub const ENET_STOP_REQ_0: u32 = 0;
1209            #[doc = "stop request on"]
1210            pub const ENET_STOP_REQ_1: u32 = 0x01;
1211        }
1212    }
1213    #[doc = "SAI1 stop request."]
1214    pub mod SAI1_STOP_REQ {
1215        pub const offset: u32 = 5;
1216        pub const mask: u32 = 0x01 << offset;
1217        pub mod R {}
1218        pub mod W {}
1219        pub mod RW {
1220            #[doc = "stop request off"]
1221            pub const SAI1_STOP_REQ_0: u32 = 0;
1222            #[doc = "stop request on"]
1223            pub const SAI1_STOP_REQ_1: u32 = 0x01;
1224        }
1225    }
1226    #[doc = "SAI2 stop request."]
1227    pub mod SAI2_STOP_REQ {
1228        pub const offset: u32 = 6;
1229        pub const mask: u32 = 0x01 << offset;
1230        pub mod R {}
1231        pub mod W {}
1232        pub mod RW {
1233            #[doc = "stop request off"]
1234            pub const SAI2_STOP_REQ_0: u32 = 0;
1235            #[doc = "stop request on"]
1236            pub const SAI2_STOP_REQ_1: u32 = 0x01;
1237        }
1238    }
1239    #[doc = "SAI3 stop request."]
1240    pub mod SAI3_STOP_REQ {
1241        pub const offset: u32 = 7;
1242        pub const mask: u32 = 0x01 << offset;
1243        pub mod R {}
1244        pub mod W {}
1245        pub mod RW {
1246            #[doc = "stop request off"]
1247            pub const SAI3_STOP_REQ_0: u32 = 0;
1248            #[doc = "stop request on"]
1249            pub const SAI3_STOP_REQ_1: u32 = 0x01;
1250        }
1251    }
1252    #[doc = "ENET2 stop request."]
1253    pub mod ENET2_STOP_REQ {
1254        pub const offset: u32 = 8;
1255        pub const mask: u32 = 0x01 << offset;
1256        pub mod R {}
1257        pub mod W {}
1258        pub mod RW {
1259            #[doc = "stop request off"]
1260            pub const ENET2_STOP_REQ_0: u32 = 0;
1261            #[doc = "stop request on"]
1262            pub const ENET2_STOP_REQ_1: u32 = 0x01;
1263        }
1264    }
1265    #[doc = "SEMC stop request."]
1266    pub mod SEMC_STOP_REQ {
1267        pub const offset: u32 = 9;
1268        pub const mask: u32 = 0x01 << offset;
1269        pub mod R {}
1270        pub mod W {}
1271        pub mod RW {
1272            #[doc = "stop request off"]
1273            pub const SEMC_STOP_REQ_0: u32 = 0;
1274            #[doc = "stop request on"]
1275            pub const SEMC_STOP_REQ_1: u32 = 0x01;
1276        }
1277    }
1278    #[doc = "PIT stop request."]
1279    pub mod PIT_STOP_REQ {
1280        pub const offset: u32 = 10;
1281        pub const mask: u32 = 0x01 << offset;
1282        pub mod R {}
1283        pub mod W {}
1284        pub mod RW {
1285            #[doc = "stop request off"]
1286            pub const PIT_STOP_REQ_0: u32 = 0;
1287            #[doc = "stop request on"]
1288            pub const PIT_STOP_REQ_1: u32 = 0x01;
1289        }
1290    }
1291    #[doc = "FlexSPI stop request."]
1292    pub mod FLEXSPI_STOP_REQ {
1293        pub const offset: u32 = 11;
1294        pub const mask: u32 = 0x01 << offset;
1295        pub mod R {}
1296        pub mod W {}
1297        pub mod RW {
1298            #[doc = "stop request off"]
1299            pub const FLEXSPI_STOP_REQ_0: u32 = 0;
1300            #[doc = "stop request on"]
1301            pub const FLEXSPI_STOP_REQ_1: u32 = 0x01;
1302        }
1303    }
1304    #[doc = "FlexIO1 stop request."]
1305    pub mod FLEXIO1_STOP_REQ {
1306        pub const offset: u32 = 12;
1307        pub const mask: u32 = 0x01 << offset;
1308        pub mod R {}
1309        pub mod W {}
1310        pub mod RW {
1311            #[doc = "stop request off"]
1312            pub const FLEXIO1_STOP_REQ_0: u32 = 0;
1313            #[doc = "stop request on"]
1314            pub const FLEXIO1_STOP_REQ_1: u32 = 0x01;
1315        }
1316    }
1317    #[doc = "FlexIO2 stop request."]
1318    pub mod FLEXIO2_STOP_REQ {
1319        pub const offset: u32 = 13;
1320        pub const mask: u32 = 0x01 << offset;
1321        pub mod R {}
1322        pub mod W {}
1323        pub mod RW {
1324            #[doc = "stop request off"]
1325            pub const FLEXIO2_STOP_REQ_0: u32 = 0;
1326            #[doc = "stop request on"]
1327            pub const FLEXIO2_STOP_REQ_1: u32 = 0x01;
1328        }
1329    }
1330    #[doc = "On-platform flexio3 stop request."]
1331    pub mod FLEXIO3_STOP_REQ {
1332        pub const offset: u32 = 14;
1333        pub const mask: u32 = 0x01 << offset;
1334        pub mod R {}
1335        pub mod W {}
1336        pub mod RW {
1337            #[doc = "stop request off"]
1338            pub const FLEXIO3_STOP_REQ_0: u32 = 0;
1339            #[doc = "stop request on"]
1340            pub const FLEXIO3_STOP_REQ_1: u32 = 0x01;
1341        }
1342    }
1343    #[doc = "FlexSPI2 stop request."]
1344    pub mod FLEXSPI2_STOP_REQ {
1345        pub const offset: u32 = 15;
1346        pub const mask: u32 = 0x01 << offset;
1347        pub mod R {}
1348        pub mod W {}
1349        pub mod RW {
1350            #[doc = "stop request off"]
1351            pub const FLEXSPI2_STOP_REQ_0: u32 = 0;
1352            #[doc = "stop request on"]
1353            pub const FLEXSPI2_STOP_REQ_1: u32 = 0x01;
1354        }
1355    }
1356    #[doc = "EDMA stop acknowledge. This is a status (read-only) bit"]
1357    pub mod EDMA_STOP_ACK {
1358        pub const offset: u32 = 16;
1359        pub const mask: u32 = 0x01 << offset;
1360        pub mod R {}
1361        pub mod W {}
1362        pub mod RW {
1363            #[doc = "EDMA stop acknowledge is not asserted"]
1364            pub const EDMA_STOP_ACK_0: u32 = 0;
1365            #[doc = "EDMA stop acknowledge is asserted (EDMA is in STOP mode)."]
1366            pub const EDMA_STOP_ACK_1: u32 = 0x01;
1367        }
1368    }
1369    #[doc = "CAN1 stop acknowledge."]
1370    pub mod CAN1_STOP_ACK {
1371        pub const offset: u32 = 17;
1372        pub const mask: u32 = 0x01 << offset;
1373        pub mod R {}
1374        pub mod W {}
1375        pub mod RW {
1376            #[doc = "CAN1 stop acknowledge is not asserted"]
1377            pub const CAN1_STOP_ACK_0: u32 = 0;
1378            #[doc = "CAN1 stop acknowledge is asserted"]
1379            pub const CAN1_STOP_ACK_1: u32 = 0x01;
1380        }
1381    }
1382    #[doc = "CAN2 stop acknowledge."]
1383    pub mod CAN2_STOP_ACK {
1384        pub const offset: u32 = 18;
1385        pub const mask: u32 = 0x01 << offset;
1386        pub mod R {}
1387        pub mod W {}
1388        pub mod RW {
1389            #[doc = "CAN2 stop acknowledge is not asserted"]
1390            pub const CAN2_STOP_ACK_0: u32 = 0;
1391            #[doc = "CAN2 stop acknowledge is asserted"]
1392            pub const CAN2_STOP_ACK_1: u32 = 0x01;
1393        }
1394    }
1395    #[doc = "TRNG stop acknowledge"]
1396    pub mod TRNG_STOP_ACK {
1397        pub const offset: u32 = 19;
1398        pub const mask: u32 = 0x01 << offset;
1399        pub mod R {}
1400        pub mod W {}
1401        pub mod RW {
1402            #[doc = "TRNG stop acknowledge is not asserted"]
1403            pub const TRNG_STOP_ACK_0: u32 = 0;
1404            #[doc = "TRNG stop acknowledge is asserted"]
1405            pub const TRNG_STOP_ACK_1: u32 = 0x01;
1406        }
1407    }
1408    #[doc = "ENET stop acknowledge."]
1409    pub mod ENET_STOP_ACK {
1410        pub const offset: u32 = 20;
1411        pub const mask: u32 = 0x01 << offset;
1412        pub mod R {}
1413        pub mod W {}
1414        pub mod RW {
1415            #[doc = "ENET1 stop acknowledge is not asserted"]
1416            pub const ENET_STOP_ACK_0: u32 = 0;
1417            #[doc = "ENET1 stop acknowledge is asserted"]
1418            pub const ENET_STOP_ACK_1: u32 = 0x01;
1419        }
1420    }
1421    #[doc = "SAI1 stop acknowledge"]
1422    pub mod SAI1_STOP_ACK {
1423        pub const offset: u32 = 21;
1424        pub const mask: u32 = 0x01 << offset;
1425        pub mod R {}
1426        pub mod W {}
1427        pub mod RW {
1428            #[doc = "SAI1 stop acknowledge is not asserted"]
1429            pub const SAI1_STOP_ACK_0: u32 = 0;
1430            #[doc = "SAI1 stop acknowledge is asserted"]
1431            pub const SAI1_STOP_ACK_1: u32 = 0x01;
1432        }
1433    }
1434    #[doc = "SAI2 stop acknowledge"]
1435    pub mod SAI2_STOP_ACK {
1436        pub const offset: u32 = 22;
1437        pub const mask: u32 = 0x01 << offset;
1438        pub mod R {}
1439        pub mod W {}
1440        pub mod RW {
1441            #[doc = "SAI2 stop acknowledge is not asserted"]
1442            pub const SAI2_STOP_ACK_0: u32 = 0;
1443            #[doc = "SAI2 stop acknowledge is asserted"]
1444            pub const SAI2_STOP_ACK_1: u32 = 0x01;
1445        }
1446    }
1447    #[doc = "SAI3 stop acknowledge"]
1448    pub mod SAI3_STOP_ACK {
1449        pub const offset: u32 = 23;
1450        pub const mask: u32 = 0x01 << offset;
1451        pub mod R {}
1452        pub mod W {}
1453        pub mod RW {
1454            #[doc = "SAI3 stop acknowledge is not asserted"]
1455            pub const SAI3_STOP_ACK_0: u32 = 0;
1456            #[doc = "SAI3 stop acknowledge is asserted"]
1457            pub const SAI3_STOP_ACK_1: u32 = 0x01;
1458        }
1459    }
1460    #[doc = "ENET2 stop acknowledge."]
1461    pub mod ENET2_STOP_ACK {
1462        pub const offset: u32 = 24;
1463        pub const mask: u32 = 0x01 << offset;
1464        pub mod R {}
1465        pub mod W {}
1466        pub mod RW {
1467            #[doc = "ENET2 stop acknowledge is not asserted"]
1468            pub const ENET2_STOP_ACK_0: u32 = 0;
1469            #[doc = "ENET2 stop acknowledge is asserted"]
1470            pub const ENET2_STOP_ACK_1: u32 = 0x01;
1471        }
1472    }
1473    #[doc = "SEMC stop acknowledge"]
1474    pub mod SEMC_STOP_ACK {
1475        pub const offset: u32 = 25;
1476        pub const mask: u32 = 0x01 << offset;
1477        pub mod R {}
1478        pub mod W {}
1479        pub mod RW {
1480            #[doc = "SEMC stop acknowledge is not asserted"]
1481            pub const SEMC_STOP_ACK_0: u32 = 0;
1482            #[doc = "SEMC stop acknowledge is asserted"]
1483            pub const SEMC_STOP_ACK_1: u32 = 0x01;
1484        }
1485    }
1486    #[doc = "PIT stop acknowledge"]
1487    pub mod PIT_STOP_ACK {
1488        pub const offset: u32 = 26;
1489        pub const mask: u32 = 0x01 << offset;
1490        pub mod R {}
1491        pub mod W {}
1492        pub mod RW {
1493            #[doc = "PIT stop acknowledge is not asserted"]
1494            pub const PIT_STOP_ACK_0: u32 = 0;
1495            #[doc = "PIT stop acknowledge is asserted"]
1496            pub const PIT_STOP_ACK_1: u32 = 0x01;
1497        }
1498    }
1499    #[doc = "FLEXSPI stop acknowledge"]
1500    pub mod FLEXSPI_STOP_ACK {
1501        pub const offset: u32 = 27;
1502        pub const mask: u32 = 0x01 << offset;
1503        pub mod R {}
1504        pub mod W {}
1505        pub mod RW {
1506            #[doc = "FLEXSPI stop acknowledge is not asserted"]
1507            pub const FLEXSPI_STOP_ACK_0: u32 = 0;
1508            #[doc = "FLEXSPI stop acknowledge is asserted"]
1509            pub const FLEXSPI_STOP_ACK_1: u32 = 0x01;
1510        }
1511    }
1512    #[doc = "FLEXIO1 stop acknowledge"]
1513    pub mod FLEXIO1_STOP_ACK {
1514        pub const offset: u32 = 28;
1515        pub const mask: u32 = 0x01 << offset;
1516        pub mod R {}
1517        pub mod W {}
1518        pub mod RW {
1519            #[doc = "FLEXIO1 stop acknowledge is not asserted"]
1520            pub const FLEXIO1_STOP_ACK_0: u32 = 0;
1521            #[doc = "FLEXIO1 stop acknowledge is asserted"]
1522            pub const FLEXIO1_STOP_ACK_1: u32 = 0x01;
1523        }
1524    }
1525    #[doc = "FLEXIO2 stop acknowledge"]
1526    pub mod FLEXIO2_STOP_ACK {
1527        pub const offset: u32 = 29;
1528        pub const mask: u32 = 0x01 << offset;
1529        pub mod R {}
1530        pub mod W {}
1531        pub mod RW {
1532            #[doc = "FLEXIO2 stop acknowledge is not asserted"]
1533            pub const FLEXIO2_STOP_ACK_0: u32 = 0;
1534            #[doc = "FLEXIO2 stop acknowledge is asserted (FLEXIO2 is in STOP mode)"]
1535            pub const FLEXIO2_STOP_ACK_1: u32 = 0x01;
1536        }
1537    }
1538    #[doc = "On-platform FLEXIO3 stop acknowledge"]
1539    pub mod FLEXIO3_STOP_ACK {
1540        pub const offset: u32 = 30;
1541        pub const mask: u32 = 0x01 << offset;
1542        pub mod R {}
1543        pub mod W {}
1544        pub mod RW {
1545            #[doc = "FLEXIO3 stop acknowledge is not asserted"]
1546            pub const FLEXIO3_STOP_ACK_0: u32 = 0;
1547            #[doc = "FLEXIO3 stop acknowledge is asserted"]
1548            pub const FLEXIO3_STOP_ACK_1: u32 = 0x01;
1549        }
1550    }
1551    #[doc = "FLEXSPI2 stop acknowledge"]
1552    pub mod FLEXSPI2_STOP_ACK {
1553        pub const offset: u32 = 31;
1554        pub const mask: u32 = 0x01 << offset;
1555        pub mod R {}
1556        pub mod W {}
1557        pub mod RW {
1558            #[doc = "FLEXSPI2 stop acknowledge is not asserted"]
1559            pub const FLEXSPI2_STOP_ACK_0: u32 = 0;
1560            #[doc = "FLEXSPI2 stop acknowledge is asserted"]
1561            pub const FLEXSPI2_STOP_ACK_1: u32 = 0x01;
1562        }
1563    }
1564}
1565#[doc = "GPR5 General Purpose Register"]
1566pub mod GPR5 {
1567    #[doc = "WDOG1 Timeout Mask"]
1568    pub mod WDOG1_MASK {
1569        pub const offset: u32 = 6;
1570        pub const mask: u32 = 0x01 << offset;
1571        pub mod R {}
1572        pub mod W {}
1573        pub mod RW {
1574            #[doc = "WDOG1 Timeout behaves normally"]
1575            pub const WDOG1_MASK_0: u32 = 0;
1576            #[doc = "WDOG1 Timeout is masked"]
1577            pub const WDOG1_MASK_1: u32 = 0x01;
1578        }
1579    }
1580    #[doc = "WDOG2 Timeout Mask"]
1581    pub mod WDOG2_MASK {
1582        pub const offset: u32 = 7;
1583        pub const mask: u32 = 0x01 << offset;
1584        pub mod R {}
1585        pub mod W {}
1586        pub mod RW {
1587            #[doc = "WDOG2 Timeout behaves normally"]
1588            pub const WDOG2_MASK_0: u32 = 0;
1589            #[doc = "WDOG2 Timeout is masked"]
1590            pub const WDOG2_MASK_1: u32 = 0x01;
1591        }
1592    }
1593    #[doc = "GPT2 input capture channel 1 source select"]
1594    pub mod GPT2_CAPIN1_SEL {
1595        pub const offset: u32 = 23;
1596        pub const mask: u32 = 0x01 << offset;
1597        pub mod R {}
1598        pub mod W {}
1599        pub mod RW {
1600            #[doc = "source from GPT2_CAPTURE1"]
1601            pub const GPT2_CAPIN1_SEL_0: u32 = 0;
1602            #[doc = "source from ENET_1588_EVENT3_OUT (chnnal 3 of IEEE 1588 timer)"]
1603            pub const GPT2_CAPIN1_SEL_1: u32 = 0x01;
1604        }
1605    }
1606    #[doc = "GPT2 input capture channel 2 source select"]
1607    pub mod GPT2_CAPIN2_SEL {
1608        pub const offset: u32 = 24;
1609        pub const mask: u32 = 0x01 << offset;
1610        pub mod R {}
1611        pub mod W {}
1612        pub mod RW {
1613            #[doc = "source from GPT2_CAPTURE2"]
1614            pub const GPT2_CAPIN2_SEL_0: u32 = 0;
1615            #[doc = "source from ENET2_1588_EVENT3_OUT (chnnal 3 of IEEE 1588 timer)"]
1616            pub const GPT2_CAPIN2_SEL_1: u32 = 0x01;
1617        }
1618    }
1619    #[doc = "ENET input timer event3 source select"]
1620    pub mod ENET_EVENT3IN_SEL {
1621        pub const offset: u32 = 25;
1622        pub const mask: u32 = 0x01 << offset;
1623        pub mod R {}
1624        pub mod W {}
1625        pub mod RW {
1626            #[doc = "event3 source input from ENET_1588_EVENT3_IN"]
1627            pub const ENET_EVENT3IN_SEL_0: u32 = 0;
1628            #[doc = "event3 source input from GPT2.GPT_COMPARE1"]
1629            pub const ENET_EVENT3IN_SEL_1: u32 = 0x01;
1630        }
1631    }
1632    #[doc = "ENET2 input timer event3 source select"]
1633    pub mod ENET2_EVENT3IN_SEL {
1634        pub const offset: u32 = 26;
1635        pub const mask: u32 = 0x01 << offset;
1636        pub mod R {}
1637        pub mod W {}
1638        pub mod RW {
1639            #[doc = "event3 source input from ENET2_1588_EVENT3_IN"]
1640            pub const ENET2_EVENT3IN_SEL_0: u32 = 0;
1641            #[doc = "event3 source input from GPT2.GPT_COMPARE2"]
1642            pub const ENET2_EVENT3IN_SEL_1: u32 = 0x01;
1643        }
1644    }
1645    #[doc = "GPT1 1 MHz clock source select"]
1646    pub mod VREF_1M_CLK_GPT1 {
1647        pub const offset: u32 = 28;
1648        pub const mask: u32 = 0x01 << offset;
1649        pub mod R {}
1650        pub mod W {}
1651        pub mod RW {
1652            #[doc = "GPT1 ipg_clk_highfreq driven by IPG_PERCLK"]
1653            pub const VREF_1M_CLK_GPT1_0: u32 = 0;
1654            #[doc = "GPT1 ipg_clk_highfreq driven by anatop 1 MHz clock"]
1655            pub const VREF_1M_CLK_GPT1_1: u32 = 0x01;
1656        }
1657    }
1658    #[doc = "GPT2 1 MHz clock source select"]
1659    pub mod VREF_1M_CLK_GPT2 {
1660        pub const offset: u32 = 29;
1661        pub const mask: u32 = 0x01 << offset;
1662        pub mod R {}
1663        pub mod W {}
1664        pub mod RW {
1665            #[doc = "GPT2 ipg_clk_highfreq driven by IPG_PERCLK"]
1666            pub const VREF_1M_CLK_GPT2_0: u32 = 0;
1667            #[doc = "GPT2 ipg_clk_highfreq driven by anatop 1 MHz clock"]
1668            pub const VREF_1M_CLK_GPT2_1: u32 = 0x01;
1669        }
1670    }
1671}
1672#[doc = "GPR6 General Purpose Register"]
1673pub mod GPR6 {
1674    #[doc = "QTIMER1 TMR0 input select"]
1675    pub mod QTIMER1_TRM0_INPUT_SEL {
1676        pub const offset: u32 = 0;
1677        pub const mask: u32 = 0x01 << offset;
1678        pub mod R {}
1679        pub mod W {}
1680        pub mod RW {
1681            #[doc = "input from IOMUX"]
1682            pub const QTIMER1_TRM0_INPUT_SEL_0: u32 = 0;
1683            #[doc = "input from XBAR"]
1684            pub const QTIMER1_TRM0_INPUT_SEL_1: u32 = 0x01;
1685        }
1686    }
1687    #[doc = "QTIMER1 TMR1 input select"]
1688    pub mod QTIMER1_TRM1_INPUT_SEL {
1689        pub const offset: u32 = 1;
1690        pub const mask: u32 = 0x01 << offset;
1691        pub mod R {}
1692        pub mod W {}
1693        pub mod RW {
1694            #[doc = "input from IOMUX"]
1695            pub const QTIMER1_TRM1_INPUT_SEL_0: u32 = 0;
1696            #[doc = "input from XBAR"]
1697            pub const QTIMER1_TRM1_INPUT_SEL_1: u32 = 0x01;
1698        }
1699    }
1700    #[doc = "QTIMER1 TMR2 input select"]
1701    pub mod QTIMER1_TRM2_INPUT_SEL {
1702        pub const offset: u32 = 2;
1703        pub const mask: u32 = 0x01 << offset;
1704        pub mod R {}
1705        pub mod W {}
1706        pub mod RW {
1707            #[doc = "input from IOMUX"]
1708            pub const QTIMER1_TRM2_INPUT_SEL_0: u32 = 0;
1709            #[doc = "input from XBAR"]
1710            pub const QTIMER1_TRM2_INPUT_SEL_1: u32 = 0x01;
1711        }
1712    }
1713    #[doc = "QTIMER1 TMR3 input select"]
1714    pub mod QTIMER1_TRM3_INPUT_SEL {
1715        pub const offset: u32 = 3;
1716        pub const mask: u32 = 0x01 << offset;
1717        pub mod R {}
1718        pub mod W {}
1719        pub mod RW {
1720            #[doc = "input from IOMUX"]
1721            pub const QTIMER1_TRM3_INPUT_SEL_0: u32 = 0;
1722            #[doc = "input from XBAR"]
1723            pub const QTIMER1_TRM3_INPUT_SEL_1: u32 = 0x01;
1724        }
1725    }
1726    #[doc = "QTIMER2 TMR0 input select"]
1727    pub mod QTIMER2_TRM0_INPUT_SEL {
1728        pub const offset: u32 = 4;
1729        pub const mask: u32 = 0x01 << offset;
1730        pub mod R {}
1731        pub mod W {}
1732        pub mod RW {
1733            #[doc = "input from IOMUX"]
1734            pub const QTIMER2_TRM0_INPUT_SEL_0: u32 = 0;
1735            #[doc = "input from XBAR"]
1736            pub const QTIMER2_TRM0_INPUT_SEL_1: u32 = 0x01;
1737        }
1738    }
1739    #[doc = "QTIMER2 TMR1 input select"]
1740    pub mod QTIMER2_TRM1_INPUT_SEL {
1741        pub const offset: u32 = 5;
1742        pub const mask: u32 = 0x01 << offset;
1743        pub mod R {}
1744        pub mod W {}
1745        pub mod RW {
1746            #[doc = "input from IOMUX"]
1747            pub const QTIMER2_TRM1_INPUT_SEL_0: u32 = 0;
1748            #[doc = "input from XBAR"]
1749            pub const QTIMER2_TRM1_INPUT_SEL_1: u32 = 0x01;
1750        }
1751    }
1752    #[doc = "QTIMER2 TMR2 input select"]
1753    pub mod QTIMER2_TRM2_INPUT_SEL {
1754        pub const offset: u32 = 6;
1755        pub const mask: u32 = 0x01 << offset;
1756        pub mod R {}
1757        pub mod W {}
1758        pub mod RW {
1759            #[doc = "input from IOMUX"]
1760            pub const QTIMER2_TRM2_INPUT_SEL_0: u32 = 0;
1761            #[doc = "input from XBAR"]
1762            pub const QTIMER2_TRM2_INPUT_SEL_1: u32 = 0x01;
1763        }
1764    }
1765    #[doc = "QTIMER2 TMR3 input select"]
1766    pub mod QTIMER2_TRM3_INPUT_SEL {
1767        pub const offset: u32 = 7;
1768        pub const mask: u32 = 0x01 << offset;
1769        pub mod R {}
1770        pub mod W {}
1771        pub mod RW {
1772            #[doc = "input from IOMUX"]
1773            pub const QTIMER2_TRM3_INPUT_SEL_0: u32 = 0;
1774            #[doc = "input from XBAR"]
1775            pub const QTIMER2_TRM3_INPUT_SEL_1: u32 = 0x01;
1776        }
1777    }
1778    #[doc = "QTIMER3 TMR0 input select"]
1779    pub mod QTIMER3_TRM0_INPUT_SEL {
1780        pub const offset: u32 = 8;
1781        pub const mask: u32 = 0x01 << offset;
1782        pub mod R {}
1783        pub mod W {}
1784        pub mod RW {
1785            #[doc = "input from IOMUX"]
1786            pub const QTIMER3_TRM0_INPUT_SEL_0: u32 = 0;
1787            #[doc = "input from XBAR"]
1788            pub const QTIMER3_TRM0_INPUT_SEL_1: u32 = 0x01;
1789        }
1790    }
1791    #[doc = "QTIMER3 TMR1 input select"]
1792    pub mod QTIMER3_TRM1_INPUT_SEL {
1793        pub const offset: u32 = 9;
1794        pub const mask: u32 = 0x01 << offset;
1795        pub mod R {}
1796        pub mod W {}
1797        pub mod RW {
1798            #[doc = "input from IOMUX"]
1799            pub const QTIMER3_TRM1_INPUT_SEL_0: u32 = 0;
1800            #[doc = "input from XBAR"]
1801            pub const QTIMER3_TRM1_INPUT_SEL_1: u32 = 0x01;
1802        }
1803    }
1804    #[doc = "QTIMER3 TMR2 input select"]
1805    pub mod QTIMER3_TRM2_INPUT_SEL {
1806        pub const offset: u32 = 10;
1807        pub const mask: u32 = 0x01 << offset;
1808        pub mod R {}
1809        pub mod W {}
1810        pub mod RW {
1811            #[doc = "input from IOMUX"]
1812            pub const QTIMER3_TRM2_INPUT_SEL_0: u32 = 0;
1813            #[doc = "input from XBAR"]
1814            pub const QTIMER3_TRM2_INPUT_SEL_1: u32 = 0x01;
1815        }
1816    }
1817    #[doc = "QTIMER3 TMR3 input select"]
1818    pub mod QTIMER3_TRM3_INPUT_SEL {
1819        pub const offset: u32 = 11;
1820        pub const mask: u32 = 0x01 << offset;
1821        pub mod R {}
1822        pub mod W {}
1823        pub mod RW {
1824            #[doc = "input from IOMUX"]
1825            pub const QTIMER3_TRM3_INPUT_SEL_0: u32 = 0;
1826            #[doc = "input from XBAR"]
1827            pub const QTIMER3_TRM3_INPUT_SEL_1: u32 = 0x01;
1828        }
1829    }
1830    #[doc = "QTIMER4 TMR0 input select"]
1831    pub mod QTIMER4_TRM0_INPUT_SEL {
1832        pub const offset: u32 = 12;
1833        pub const mask: u32 = 0x01 << offset;
1834        pub mod R {}
1835        pub mod W {}
1836        pub mod RW {
1837            #[doc = "input from IOMUX"]
1838            pub const QTIMER4_TRM0_INPUT_SEL_0: u32 = 0;
1839            #[doc = "input from XBAR"]
1840            pub const QTIMER4_TRM0_INPUT_SEL_1: u32 = 0x01;
1841        }
1842    }
1843    #[doc = "QTIMER4 TMR1 input select"]
1844    pub mod QTIMER4_TRM1_INPUT_SEL {
1845        pub const offset: u32 = 13;
1846        pub const mask: u32 = 0x01 << offset;
1847        pub mod R {}
1848        pub mod W {}
1849        pub mod RW {
1850            #[doc = "input from IOMUX"]
1851            pub const QTIMER4_TRM1_INPUT_SEL_0: u32 = 0;
1852            #[doc = "input from XBAR"]
1853            pub const QTIMER4_TRM1_INPUT_SEL_1: u32 = 0x01;
1854        }
1855    }
1856    #[doc = "QTIMER4 TMR2 input select"]
1857    pub mod QTIMER4_TRM2_INPUT_SEL {
1858        pub const offset: u32 = 14;
1859        pub const mask: u32 = 0x01 << offset;
1860        pub mod R {}
1861        pub mod W {}
1862        pub mod RW {
1863            #[doc = "input from IOMUX"]
1864            pub const QTIMER4_TRM2_INPUT_SEL_0: u32 = 0;
1865            #[doc = "input from XBAR"]
1866            pub const QTIMER4_TRM2_INPUT_SEL_1: u32 = 0x01;
1867        }
1868    }
1869    #[doc = "QTIMER4 TMR3 input select"]
1870    pub mod QTIMER4_TRM3_INPUT_SEL {
1871        pub const offset: u32 = 15;
1872        pub const mask: u32 = 0x01 << offset;
1873        pub mod R {}
1874        pub mod W {}
1875        pub mod RW {
1876            #[doc = "input from IOMUX"]
1877            pub const QTIMER4_TRM3_INPUT_SEL_0: u32 = 0;
1878            #[doc = "input from XBAR"]
1879            pub const QTIMER4_TRM3_INPUT_SEL_1: u32 = 0x01;
1880        }
1881    }
1882    #[doc = "IOMUXC XBAR_INOUT4 function direction select"]
1883    pub mod IOMUXC_XBAR_DIR_SEL_4 {
1884        pub const offset: u32 = 16;
1885        pub const mask: u32 = 0x01 << offset;
1886        pub mod R {}
1887        pub mod W {}
1888        pub mod RW {
1889            #[doc = "XBAR_INOUT as input"]
1890            pub const IOMUXC_XBAR_DIR_SEL_4_0: u32 = 0;
1891            #[doc = "XBAR_INOUT as output"]
1892            pub const IOMUXC_XBAR_DIR_SEL_4_1: u32 = 0x01;
1893        }
1894    }
1895    #[doc = "IOMUXC XBAR_INOUT5 function direction select"]
1896    pub mod IOMUXC_XBAR_DIR_SEL_5 {
1897        pub const offset: u32 = 17;
1898        pub const mask: u32 = 0x01 << offset;
1899        pub mod R {}
1900        pub mod W {}
1901        pub mod RW {
1902            #[doc = "XBAR_INOUT as input"]
1903            pub const IOMUXC_XBAR_DIR_SEL_5_0: u32 = 0;
1904            #[doc = "XBAR_INOUT as output"]
1905            pub const IOMUXC_XBAR_DIR_SEL_5_1: u32 = 0x01;
1906        }
1907    }
1908    #[doc = "IOMUXC XBAR_INOUT6 function direction select"]
1909    pub mod IOMUXC_XBAR_DIR_SEL_6 {
1910        pub const offset: u32 = 18;
1911        pub const mask: u32 = 0x01 << offset;
1912        pub mod R {}
1913        pub mod W {}
1914        pub mod RW {
1915            #[doc = "XBAR_INOUT as input"]
1916            pub const IOMUXC_XBAR_DIR_SEL_6_0: u32 = 0;
1917            #[doc = "XBAR_INOUT as output"]
1918            pub const IOMUXC_XBAR_DIR_SEL_6_1: u32 = 0x01;
1919        }
1920    }
1921    #[doc = "IOMUXC XBAR_INOUT7 function direction select"]
1922    pub mod IOMUXC_XBAR_DIR_SEL_7 {
1923        pub const offset: u32 = 19;
1924        pub const mask: u32 = 0x01 << offset;
1925        pub mod R {}
1926        pub mod W {}
1927        pub mod RW {
1928            #[doc = "XBAR_INOUT as input"]
1929            pub const IOMUXC_XBAR_DIR_SEL_7_0: u32 = 0;
1930            #[doc = "XBAR_INOUT as output"]
1931            pub const IOMUXC_XBAR_DIR_SEL_7_1: u32 = 0x01;
1932        }
1933    }
1934    #[doc = "IOMUXC XBAR_INOUT8 function direction select"]
1935    pub mod IOMUXC_XBAR_DIR_SEL_8 {
1936        pub const offset: u32 = 20;
1937        pub const mask: u32 = 0x01 << offset;
1938        pub mod R {}
1939        pub mod W {}
1940        pub mod RW {
1941            #[doc = "XBAR_INOUT as input"]
1942            pub const IOMUXC_XBAR_DIR_SEL_8_0: u32 = 0;
1943            #[doc = "XBAR_INOUT as output"]
1944            pub const IOMUXC_XBAR_DIR_SEL_8_1: u32 = 0x01;
1945        }
1946    }
1947    #[doc = "IOMUXC XBAR_INOUT9 function direction select"]
1948    pub mod IOMUXC_XBAR_DIR_SEL_9 {
1949        pub const offset: u32 = 21;
1950        pub const mask: u32 = 0x01 << offset;
1951        pub mod R {}
1952        pub mod W {}
1953        pub mod RW {
1954            #[doc = "XBAR_INOUT as input"]
1955            pub const IOMUXC_XBAR_DIR_SEL_9_0: u32 = 0;
1956            #[doc = "XBAR_INOUT as output"]
1957            pub const IOMUXC_XBAR_DIR_SEL_9_1: u32 = 0x01;
1958        }
1959    }
1960    #[doc = "IOMUXC XBAR_INOUT10 function direction select"]
1961    pub mod IOMUXC_XBAR_DIR_SEL_10 {
1962        pub const offset: u32 = 22;
1963        pub const mask: u32 = 0x01 << offset;
1964        pub mod R {}
1965        pub mod W {}
1966        pub mod RW {
1967            #[doc = "XBAR_INOUT as input"]
1968            pub const IOMUXC_XBAR_DIR_SEL_10_0: u32 = 0;
1969            #[doc = "XBAR_INOUT as output"]
1970            pub const IOMUXC_XBAR_DIR_SEL_10_1: u32 = 0x01;
1971        }
1972    }
1973    #[doc = "IOMUXC XBAR_INOUT11 function direction select"]
1974    pub mod IOMUXC_XBAR_DIR_SEL_11 {
1975        pub const offset: u32 = 23;
1976        pub const mask: u32 = 0x01 << offset;
1977        pub mod R {}
1978        pub mod W {}
1979        pub mod RW {
1980            #[doc = "XBAR_INOUT as input"]
1981            pub const IOMUXC_XBAR_DIR_SEL_11_0: u32 = 0;
1982            #[doc = "XBAR_INOUT as output"]
1983            pub const IOMUXC_XBAR_DIR_SEL_11_1: u32 = 0x01;
1984        }
1985    }
1986    #[doc = "IOMUXC XBAR_INOUT12 function direction select"]
1987    pub mod IOMUXC_XBAR_DIR_SEL_12 {
1988        pub const offset: u32 = 24;
1989        pub const mask: u32 = 0x01 << offset;
1990        pub mod R {}
1991        pub mod W {}
1992        pub mod RW {
1993            #[doc = "XBAR_INOUT as input"]
1994            pub const IOMUXC_XBAR_DIR_SEL_12_0: u32 = 0;
1995            #[doc = "XBAR_INOUT as output"]
1996            pub const IOMUXC_XBAR_DIR_SEL_12_1: u32 = 0x01;
1997        }
1998    }
1999    #[doc = "IOMUXC XBAR_INOUT13 function direction select"]
2000    pub mod IOMUXC_XBAR_DIR_SEL_13 {
2001        pub const offset: u32 = 25;
2002        pub const mask: u32 = 0x01 << offset;
2003        pub mod R {}
2004        pub mod W {}
2005        pub mod RW {
2006            #[doc = "XBAR_INOUT as input"]
2007            pub const IOMUXC_XBAR_DIR_SEL_13_0: u32 = 0;
2008            #[doc = "XBAR_INOUT as output"]
2009            pub const IOMUXC_XBAR_DIR_SEL_13_1: u32 = 0x01;
2010        }
2011    }
2012    #[doc = "IOMUXC XBAR_INOUT14 function direction select"]
2013    pub mod IOMUXC_XBAR_DIR_SEL_14 {
2014        pub const offset: u32 = 26;
2015        pub const mask: u32 = 0x01 << offset;
2016        pub mod R {}
2017        pub mod W {}
2018        pub mod RW {
2019            #[doc = "XBAR_INOUT as input"]
2020            pub const IOMUXC_XBAR_DIR_SEL_14_0: u32 = 0;
2021            #[doc = "XBAR_INOUT as output"]
2022            pub const IOMUXC_XBAR_DIR_SEL_14_1: u32 = 0x01;
2023        }
2024    }
2025    #[doc = "IOMUXC XBAR_INOUT15 function direction select"]
2026    pub mod IOMUXC_XBAR_DIR_SEL_15 {
2027        pub const offset: u32 = 27;
2028        pub const mask: u32 = 0x01 << offset;
2029        pub mod R {}
2030        pub mod W {}
2031        pub mod RW {
2032            #[doc = "XBAR_INOUT as input"]
2033            pub const IOMUXC_XBAR_DIR_SEL_15_0: u32 = 0;
2034            #[doc = "XBAR_INOUT as output"]
2035            pub const IOMUXC_XBAR_DIR_SEL_15_1: u32 = 0x01;
2036        }
2037    }
2038    #[doc = "IOMUXC XBAR_INOUT16 function direction select"]
2039    pub mod IOMUXC_XBAR_DIR_SEL_16 {
2040        pub const offset: u32 = 28;
2041        pub const mask: u32 = 0x01 << offset;
2042        pub mod R {}
2043        pub mod W {}
2044        pub mod RW {
2045            #[doc = "XBAR_INOUT as input"]
2046            pub const IOMUXC_XBAR_DIR_SEL_16_0: u32 = 0;
2047            #[doc = "XBAR_INOUT as output"]
2048            pub const IOMUXC_XBAR_DIR_SEL_16_1: u32 = 0x01;
2049        }
2050    }
2051    #[doc = "IOMUXC XBAR_INOUT17 function direction select"]
2052    pub mod IOMUXC_XBAR_DIR_SEL_17 {
2053        pub const offset: u32 = 29;
2054        pub const mask: u32 = 0x01 << offset;
2055        pub mod R {}
2056        pub mod W {}
2057        pub mod RW {
2058            #[doc = "XBAR_INOUT as input"]
2059            pub const IOMUXC_XBAR_DIR_SEL_17_0: u32 = 0;
2060            #[doc = "XBAR_INOUT as output"]
2061            pub const IOMUXC_XBAR_DIR_SEL_17_1: u32 = 0x01;
2062        }
2063    }
2064    #[doc = "IOMUXC XBAR_INOUT18 function direction select"]
2065    pub mod IOMUXC_XBAR_DIR_SEL_18 {
2066        pub const offset: u32 = 30;
2067        pub const mask: u32 = 0x01 << offset;
2068        pub mod R {}
2069        pub mod W {}
2070        pub mod RW {
2071            #[doc = "XBAR_INOUT as input"]
2072            pub const IOMUXC_XBAR_DIR_SEL_18_0: u32 = 0;
2073            #[doc = "XBAR_INOUT as output"]
2074            pub const IOMUXC_XBAR_DIR_SEL_18_1: u32 = 0x01;
2075        }
2076    }
2077    #[doc = "IOMUXC XBAR_INOUT19 function direction select"]
2078    pub mod IOMUXC_XBAR_DIR_SEL_19 {
2079        pub const offset: u32 = 31;
2080        pub const mask: u32 = 0x01 << offset;
2081        pub mod R {}
2082        pub mod W {}
2083        pub mod RW {
2084            #[doc = "XBAR_INOUT as input"]
2085            pub const IOMUXC_XBAR_DIR_SEL_19_0: u32 = 0;
2086            #[doc = "XBAR_INOUT as output"]
2087            pub const IOMUXC_XBAR_DIR_SEL_19_1: u32 = 0x01;
2088        }
2089    }
2090}
2091#[doc = "GPR7 General Purpose Register"]
2092pub mod GPR7 {
2093    #[doc = "LPI2C1 stop request"]
2094    pub mod LPI2C1_STOP_REQ {
2095        pub const offset: u32 = 0;
2096        pub const mask: u32 = 0x01 << offset;
2097        pub mod R {}
2098        pub mod W {}
2099        pub mod RW {
2100            #[doc = "stop request off"]
2101            pub const LPI2C1_STOP_REQ_0: u32 = 0;
2102            #[doc = "stop request on"]
2103            pub const LPI2C1_STOP_REQ_1: u32 = 0x01;
2104        }
2105    }
2106    #[doc = "LPI2C2 stop request"]
2107    pub mod LPI2C2_STOP_REQ {
2108        pub const offset: u32 = 1;
2109        pub const mask: u32 = 0x01 << offset;
2110        pub mod R {}
2111        pub mod W {}
2112        pub mod RW {
2113            #[doc = "stop request off"]
2114            pub const LPI2C2_STOP_REQ_0: u32 = 0;
2115            #[doc = "stop request on"]
2116            pub const LPI2C2_STOP_REQ_1: u32 = 0x01;
2117        }
2118    }
2119    #[doc = "LPI2C3 stop request"]
2120    pub mod LPI2C3_STOP_REQ {
2121        pub const offset: u32 = 2;
2122        pub const mask: u32 = 0x01 << offset;
2123        pub mod R {}
2124        pub mod W {}
2125        pub mod RW {
2126            #[doc = "stop request off"]
2127            pub const LPI2C3_STOP_REQ_0: u32 = 0;
2128            #[doc = "stop request on"]
2129            pub const LPI2C3_STOP_REQ_1: u32 = 0x01;
2130        }
2131    }
2132    #[doc = "LPI2C4 stop request"]
2133    pub mod LPI2C4_STOP_REQ {
2134        pub const offset: u32 = 3;
2135        pub const mask: u32 = 0x01 << offset;
2136        pub mod R {}
2137        pub mod W {}
2138        pub mod RW {
2139            #[doc = "stop request off"]
2140            pub const LPI2C4_STOP_REQ_0: u32 = 0;
2141            #[doc = "stop request on"]
2142            pub const LPI2C4_STOP_REQ_1: u32 = 0x01;
2143        }
2144    }
2145    #[doc = "LPSPI1 stop request"]
2146    pub mod LPSPI1_STOP_REQ {
2147        pub const offset: u32 = 4;
2148        pub const mask: u32 = 0x01 << offset;
2149        pub mod R {}
2150        pub mod W {}
2151        pub mod RW {
2152            #[doc = "stop request off"]
2153            pub const LPSPI1_STOP_REQ_0: u32 = 0;
2154            #[doc = "stop request on"]
2155            pub const LPSPI1_STOP_REQ_1: u32 = 0x01;
2156        }
2157    }
2158    #[doc = "LPSPI2 stop request"]
2159    pub mod LPSPI2_STOP_REQ {
2160        pub const offset: u32 = 5;
2161        pub const mask: u32 = 0x01 << offset;
2162        pub mod R {}
2163        pub mod W {}
2164        pub mod RW {
2165            #[doc = "stop request off"]
2166            pub const LPSPI2_STOP_REQ_0: u32 = 0;
2167            #[doc = "stop request on"]
2168            pub const LPSPI2_STOP_REQ_1: u32 = 0x01;
2169        }
2170    }
2171    #[doc = "LPSPI3 stop request"]
2172    pub mod LPSPI3_STOP_REQ {
2173        pub const offset: u32 = 6;
2174        pub const mask: u32 = 0x01 << offset;
2175        pub mod R {}
2176        pub mod W {}
2177        pub mod RW {
2178            #[doc = "stop request off"]
2179            pub const LPSPI3_STOP_REQ_0: u32 = 0;
2180            #[doc = "stop request on"]
2181            pub const LPSPI3_STOP_REQ_1: u32 = 0x01;
2182        }
2183    }
2184    #[doc = "LPSPI4 stop request"]
2185    pub mod LPSPI4_STOP_REQ {
2186        pub const offset: u32 = 7;
2187        pub const mask: u32 = 0x01 << offset;
2188        pub mod R {}
2189        pub mod W {}
2190        pub mod RW {
2191            #[doc = "stop request off"]
2192            pub const LPSPI4_STOP_REQ_0: u32 = 0;
2193            #[doc = "stop request on"]
2194            pub const LPSPI4_STOP_REQ_1: u32 = 0x01;
2195        }
2196    }
2197    #[doc = "LPUART1 stop request"]
2198    pub mod LPUART1_STOP_REQ {
2199        pub const offset: u32 = 8;
2200        pub const mask: u32 = 0x01 << offset;
2201        pub mod R {}
2202        pub mod W {}
2203        pub mod RW {
2204            #[doc = "stop request off"]
2205            pub const LPUART1_STOP_REQ_0: u32 = 0;
2206            #[doc = "stop request on"]
2207            pub const LPUART1_STOP_REQ_1: u32 = 0x01;
2208        }
2209    }
2210    #[doc = "LPUART1 stop request"]
2211    pub mod LPUART2_STOP_REQ {
2212        pub const offset: u32 = 9;
2213        pub const mask: u32 = 0x01 << offset;
2214        pub mod R {}
2215        pub mod W {}
2216        pub mod RW {
2217            #[doc = "stop request off"]
2218            pub const LPUART2_STOP_REQ_0: u32 = 0;
2219            #[doc = "stop request on"]
2220            pub const LPUART2_STOP_REQ_1: u32 = 0x01;
2221        }
2222    }
2223    #[doc = "LPUART3 stop request"]
2224    pub mod LPUART3_STOP_REQ {
2225        pub const offset: u32 = 10;
2226        pub const mask: u32 = 0x01 << offset;
2227        pub mod R {}
2228        pub mod W {}
2229        pub mod RW {
2230            #[doc = "stop request off"]
2231            pub const LPUART3_STOP_REQ_0: u32 = 0;
2232            #[doc = "stop request on"]
2233            pub const LPUART3_STOP_REQ_1: u32 = 0x01;
2234        }
2235    }
2236    #[doc = "LPUART4 stop request"]
2237    pub mod LPUART4_STOP_REQ {
2238        pub const offset: u32 = 11;
2239        pub const mask: u32 = 0x01 << offset;
2240        pub mod R {}
2241        pub mod W {}
2242        pub mod RW {
2243            #[doc = "stop request off"]
2244            pub const LPUART4_STOP_REQ_0: u32 = 0;
2245            #[doc = "stop request on"]
2246            pub const LPUART4_STOP_REQ_1: u32 = 0x01;
2247        }
2248    }
2249    #[doc = "LPUART5 stop request"]
2250    pub mod LPUART5_STOP_REQ {
2251        pub const offset: u32 = 12;
2252        pub const mask: u32 = 0x01 << offset;
2253        pub mod R {}
2254        pub mod W {}
2255        pub mod RW {
2256            #[doc = "stop request off"]
2257            pub const LPUART5_STOP_REQ_0: u32 = 0;
2258            #[doc = "stop request on"]
2259            pub const LPUART5_STOP_REQ_1: u32 = 0x01;
2260        }
2261    }
2262    #[doc = "LPUART6 stop request"]
2263    pub mod LPUART6_STOP_REQ {
2264        pub const offset: u32 = 13;
2265        pub const mask: u32 = 0x01 << offset;
2266        pub mod R {}
2267        pub mod W {}
2268        pub mod RW {
2269            #[doc = "stop request off"]
2270            pub const LPUART6_STOP_REQ_0: u32 = 0;
2271            #[doc = "stop request on"]
2272            pub const LPUART6_STOP_REQ_1: u32 = 0x01;
2273        }
2274    }
2275    #[doc = "LPUART7 stop request"]
2276    pub mod LPUART7_STOP_REQ {
2277        pub const offset: u32 = 14;
2278        pub const mask: u32 = 0x01 << offset;
2279        pub mod R {}
2280        pub mod W {}
2281        pub mod RW {
2282            #[doc = "stop request off"]
2283            pub const LPUART7_STOP_REQ_0: u32 = 0;
2284            #[doc = "stop request on"]
2285            pub const LPUART7_STOP_REQ_1: u32 = 0x01;
2286        }
2287    }
2288    #[doc = "LPUART8 stop request"]
2289    pub mod LPUART8_STOP_REQ {
2290        pub const offset: u32 = 15;
2291        pub const mask: u32 = 0x01 << offset;
2292        pub mod R {}
2293        pub mod W {}
2294        pub mod RW {
2295            #[doc = "stop request off"]
2296            pub const LPUART8_STOP_REQ_0: u32 = 0;
2297            #[doc = "stop request on"]
2298            pub const LPUART8_STOP_REQ_1: u32 = 0x01;
2299        }
2300    }
2301    #[doc = "LPI2C1 stop acknowledge"]
2302    pub mod LPI2C1_STOP_ACK {
2303        pub const offset: u32 = 16;
2304        pub const mask: u32 = 0x01 << offset;
2305        pub mod R {}
2306        pub mod W {}
2307        pub mod RW {
2308            #[doc = "stop acknowledge is not asserted"]
2309            pub const LPI2C1_STOP_ACK_0: u32 = 0;
2310            #[doc = "stop acknowledge is asserted (the module is in Stop mode)"]
2311            pub const LPI2C1_STOP_ACK_1: u32 = 0x01;
2312        }
2313    }
2314    #[doc = "LPI2C2 stop acknowledge"]
2315    pub mod LPI2C2_STOP_ACK {
2316        pub const offset: u32 = 17;
2317        pub const mask: u32 = 0x01 << offset;
2318        pub mod R {}
2319        pub mod W {}
2320        pub mod RW {
2321            #[doc = "stop acknowledge is not asserted"]
2322            pub const LPI2C2_STOP_ACK_0: u32 = 0;
2323            #[doc = "stop acknowledge is asserted"]
2324            pub const LPI2C2_STOP_ACK_1: u32 = 0x01;
2325        }
2326    }
2327    #[doc = "LPI2C3 stop acknowledge"]
2328    pub mod LPI2C3_STOP_ACK {
2329        pub const offset: u32 = 18;
2330        pub const mask: u32 = 0x01 << offset;
2331        pub mod R {}
2332        pub mod W {}
2333        pub mod RW {
2334            #[doc = "stop acknowledge is not asserted"]
2335            pub const LPI2C3_STOP_ACK_0: u32 = 0;
2336            #[doc = "stop acknowledge is asserted"]
2337            pub const LPI2C3_STOP_ACK_1: u32 = 0x01;
2338        }
2339    }
2340    #[doc = "LPI2C4 stop acknowledge"]
2341    pub mod LPI2C4_STOP_ACK {
2342        pub const offset: u32 = 19;
2343        pub const mask: u32 = 0x01 << offset;
2344        pub mod R {}
2345        pub mod W {}
2346        pub mod RW {
2347            #[doc = "stop acknowledge is not asserted"]
2348            pub const LPI2C4_STOP_ACK_0: u32 = 0;
2349            #[doc = "stop acknowledge is asserted"]
2350            pub const LPI2C4_STOP_ACK_1: u32 = 0x01;
2351        }
2352    }
2353    #[doc = "LPSPI1 stop acknowledge"]
2354    pub mod LPSPI1_STOP_ACK {
2355        pub const offset: u32 = 20;
2356        pub const mask: u32 = 0x01 << offset;
2357        pub mod R {}
2358        pub mod W {}
2359        pub mod RW {
2360            #[doc = "stop acknowledge is not asserted"]
2361            pub const LPSPI1_STOP_ACK_0: u32 = 0;
2362            #[doc = "stop acknowledge is asserted"]
2363            pub const LPSPI1_STOP_ACK_1: u32 = 0x01;
2364        }
2365    }
2366    #[doc = "LPSPI2 stop acknowledge"]
2367    pub mod LPSPI2_STOP_ACK {
2368        pub const offset: u32 = 21;
2369        pub const mask: u32 = 0x01 << offset;
2370        pub mod R {}
2371        pub mod W {}
2372        pub mod RW {
2373            #[doc = "stop acknowledge is not asserted"]
2374            pub const LPSPI2_STOP_ACK_0: u32 = 0;
2375            #[doc = "stop acknowledge is asserted"]
2376            pub const LPSPI2_STOP_ACK_1: u32 = 0x01;
2377        }
2378    }
2379    #[doc = "LPSPI3 stop acknowledge"]
2380    pub mod LPSPI3_STOP_ACK {
2381        pub const offset: u32 = 22;
2382        pub const mask: u32 = 0x01 << offset;
2383        pub mod R {}
2384        pub mod W {}
2385        pub mod RW {
2386            #[doc = "stop acknowledge is not asserted"]
2387            pub const LPSPI3_STOP_ACK_0: u32 = 0;
2388            #[doc = "stop acknowledge is asserted"]
2389            pub const LPSPI3_STOP_ACK_1: u32 = 0x01;
2390        }
2391    }
2392    #[doc = "LPSPI4 stop acknowledge"]
2393    pub mod LPSPI4_STOP_ACK {
2394        pub const offset: u32 = 23;
2395        pub const mask: u32 = 0x01 << offset;
2396        pub mod R {}
2397        pub mod W {}
2398        pub mod RW {
2399            #[doc = "stop acknowledge is not asserted"]
2400            pub const LPSPI4_STOP_ACK_0: u32 = 0;
2401            #[doc = "stop acknowledge is asserted"]
2402            pub const LPSPI4_STOP_ACK_1: u32 = 0x01;
2403        }
2404    }
2405    #[doc = "LPUART1 stop acknowledge"]
2406    pub mod LPUART1_STOP_ACK {
2407        pub const offset: u32 = 24;
2408        pub const mask: u32 = 0x01 << offset;
2409        pub mod R {}
2410        pub mod W {}
2411        pub mod RW {
2412            #[doc = "stop acknowledge is not asserted"]
2413            pub const LPUART1_STOP_ACK_0: u32 = 0;
2414            #[doc = "stop acknowledge is asserted"]
2415            pub const LPUART1_STOP_ACK_1: u32 = 0x01;
2416        }
2417    }
2418    #[doc = "LPUART1 stop acknowledge"]
2419    pub mod LPUART2_STOP_ACK {
2420        pub const offset: u32 = 25;
2421        pub const mask: u32 = 0x01 << offset;
2422        pub mod R {}
2423        pub mod W {}
2424        pub mod RW {
2425            #[doc = "stop acknowledge is not asserted"]
2426            pub const LPUART2_STOP_ACK_0: u32 = 0;
2427            #[doc = "stop acknowledge is asserted"]
2428            pub const LPUART2_STOP_ACK_1: u32 = 0x01;
2429        }
2430    }
2431    #[doc = "LPUART3 stop acknowledge"]
2432    pub mod LPUART3_STOP_ACK {
2433        pub const offset: u32 = 26;
2434        pub const mask: u32 = 0x01 << offset;
2435        pub mod R {}
2436        pub mod W {}
2437        pub mod RW {
2438            #[doc = "stop acknowledge is not asserted"]
2439            pub const LPUART3_STOP_ACK_0: u32 = 0;
2440            #[doc = "stop acknowledge is asserted"]
2441            pub const LPUART3_STOP_ACK_1: u32 = 0x01;
2442        }
2443    }
2444    #[doc = "LPUART4 stop acknowledge"]
2445    pub mod LPUART4_STOP_ACK {
2446        pub const offset: u32 = 27;
2447        pub const mask: u32 = 0x01 << offset;
2448        pub mod R {}
2449        pub mod W {}
2450        pub mod RW {
2451            #[doc = "stop acknowledge is not asserted"]
2452            pub const LPUART4_STOP_ACK_0: u32 = 0;
2453            #[doc = "stop acknowledge is asserted"]
2454            pub const LPUART4_STOP_ACK_1: u32 = 0x01;
2455        }
2456    }
2457    #[doc = "LPUART5 stop acknowledge"]
2458    pub mod LPUART5_STOP_ACK {
2459        pub const offset: u32 = 28;
2460        pub const mask: u32 = 0x01 << offset;
2461        pub mod R {}
2462        pub mod W {}
2463        pub mod RW {
2464            #[doc = "stop acknowledge is not asserted"]
2465            pub const LPUART5_STOP_ACK_0: u32 = 0;
2466            #[doc = "stop acknowledge is asserted"]
2467            pub const LPUART5_STOP_ACK_1: u32 = 0x01;
2468        }
2469    }
2470    #[doc = "LPUART6 stop acknowledge"]
2471    pub mod LPUART6_STOP_ACK {
2472        pub const offset: u32 = 29;
2473        pub const mask: u32 = 0x01 << offset;
2474        pub mod R {}
2475        pub mod W {}
2476        pub mod RW {
2477            #[doc = "stop acknowledge is not asserted"]
2478            pub const LPUART6_STOP_ACK_0: u32 = 0;
2479            #[doc = "stop acknowledge is asserted"]
2480            pub const LPUART6_STOP_ACK_1: u32 = 0x01;
2481        }
2482    }
2483    #[doc = "LPUART7 stop acknowledge"]
2484    pub mod LPUART7_STOP_ACK {
2485        pub const offset: u32 = 30;
2486        pub const mask: u32 = 0x01 << offset;
2487        pub mod R {}
2488        pub mod W {}
2489        pub mod RW {
2490            #[doc = "stop acknowledge is not asserted"]
2491            pub const LPUART7_STOP_ACK_0: u32 = 0;
2492            #[doc = "stop acknowledge is asserted"]
2493            pub const LPUART7_STOP_ACK_1: u32 = 0x01;
2494        }
2495    }
2496    #[doc = "LPUART8 stop acknowledge"]
2497    pub mod LPUART8_STOP_ACK {
2498        pub const offset: u32 = 31;
2499        pub const mask: u32 = 0x01 << offset;
2500        pub mod R {}
2501        pub mod W {}
2502        pub mod RW {
2503            #[doc = "stop acknowledge is not asserted"]
2504            pub const LPUART8_STOP_ACK_0: u32 = 0;
2505            #[doc = "stop acknowledge is asserted (the module is in Stop mode)"]
2506            pub const LPUART8_STOP_ACK_1: u32 = 0x01;
2507        }
2508    }
2509}
2510#[doc = "GPR8 General Purpose Register"]
2511pub mod GPR8 {
2512    #[doc = "LPI2C1 stop mode selection, cannot change when ipg_stop is asserted."]
2513    pub mod LPI2C1_IPG_STOP_MODE {
2514        pub const offset: u32 = 0;
2515        pub const mask: u32 = 0x01 << offset;
2516        pub mod R {}
2517        pub mod W {}
2518        pub mod RW {
2519            #[doc = "the module is functional in Stop mode"]
2520            pub const LPI2C1_IPG_STOP_MODE_0: u32 = 0;
2521            #[doc = "the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted"]
2522            pub const LPI2C1_IPG_STOP_MODE_1: u32 = 0x01;
2523        }
2524    }
2525    #[doc = "LPI2C1 ipg_doze mode"]
2526    pub mod LPI2C1_IPG_DOZE {
2527        pub const offset: u32 = 1;
2528        pub const mask: u32 = 0x01 << offset;
2529        pub mod R {}
2530        pub mod W {}
2531        pub mod RW {
2532            #[doc = "not in doze mode"]
2533            pub const LPI2C1_IPG_DOZE_0: u32 = 0;
2534            #[doc = "in doze mode"]
2535            pub const LPI2C1_IPG_DOZE_1: u32 = 0x01;
2536        }
2537    }
2538    #[doc = "LPI2C2 stop mode selection, cannot change when ipg_stop is asserted."]
2539    pub mod LPI2C2_IPG_STOP_MODE {
2540        pub const offset: u32 = 2;
2541        pub const mask: u32 = 0x01 << offset;
2542        pub mod R {}
2543        pub mod W {}
2544        pub mod RW {
2545            #[doc = "the module is functional in Stop mode"]
2546            pub const LPI2C2_IPG_STOP_MODE_0: u32 = 0;
2547            #[doc = "the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted"]
2548            pub const LPI2C2_IPG_STOP_MODE_1: u32 = 0x01;
2549        }
2550    }
2551    #[doc = "LPI2C2 ipg_doze mode"]
2552    pub mod LPI2C2_IPG_DOZE {
2553        pub const offset: u32 = 3;
2554        pub const mask: u32 = 0x01 << offset;
2555        pub mod R {}
2556        pub mod W {}
2557        pub mod RW {
2558            #[doc = "not in doze mode"]
2559            pub const LPI2C2_IPG_DOZE_0: u32 = 0;
2560            #[doc = "in doze mode"]
2561            pub const LPI2C2_IPG_DOZE_1: u32 = 0x01;
2562        }
2563    }
2564    #[doc = "LPI2C3 stop mode selection, cannot change when ipg_stop is asserted."]
2565    pub mod LPI2C3_IPG_STOP_MODE {
2566        pub const offset: u32 = 4;
2567        pub const mask: u32 = 0x01 << offset;
2568        pub mod R {}
2569        pub mod W {}
2570        pub mod RW {
2571            #[doc = "the module is functional in Stop mode"]
2572            pub const LPI2C3_IPG_STOP_MODE_0: u32 = 0;
2573            #[doc = "the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted"]
2574            pub const LPI2C3_IPG_STOP_MODE_1: u32 = 0x01;
2575        }
2576    }
2577    #[doc = "LPI2C3 ipg_doze mode"]
2578    pub mod LPI2C3_IPG_DOZE {
2579        pub const offset: u32 = 5;
2580        pub const mask: u32 = 0x01 << offset;
2581        pub mod R {}
2582        pub mod W {}
2583        pub mod RW {
2584            #[doc = "not in doze mode"]
2585            pub const LPI2C3_IPG_DOZE_0: u32 = 0;
2586            #[doc = "in doze mode"]
2587            pub const LPI2C3_IPG_DOZE_1: u32 = 0x01;
2588        }
2589    }
2590    #[doc = "LPI2C4 stop mode selection, cannot change when ipg_stop is asserted."]
2591    pub mod LPI2C4_IPG_STOP_MODE {
2592        pub const offset: u32 = 6;
2593        pub const mask: u32 = 0x01 << offset;
2594        pub mod R {}
2595        pub mod W {}
2596        pub mod RW {
2597            #[doc = "the module is functional in Stop mode"]
2598            pub const LPI2C4_IPG_STOP_MODE_0: u32 = 0;
2599            #[doc = "the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted"]
2600            pub const LPI2C4_IPG_STOP_MODE_1: u32 = 0x01;
2601        }
2602    }
2603    #[doc = "LPI2C4 ipg_doze mode"]
2604    pub mod LPI2C4_IPG_DOZE {
2605        pub const offset: u32 = 7;
2606        pub const mask: u32 = 0x01 << offset;
2607        pub mod R {}
2608        pub mod W {}
2609        pub mod RW {
2610            #[doc = "not in doze mode"]
2611            pub const LPI2C4_IPG_DOZE_0: u32 = 0;
2612            #[doc = "in doze mode"]
2613            pub const LPI2C4_IPG_DOZE_1: u32 = 0x01;
2614        }
2615    }
2616    #[doc = "LPSPI1 stop mode selection, cannot change when ipg_stop is asserted."]
2617    pub mod LPSPI1_IPG_STOP_MODE {
2618        pub const offset: u32 = 8;
2619        pub const mask: u32 = 0x01 << offset;
2620        pub mod R {}
2621        pub mod W {}
2622        pub mod RW {
2623            #[doc = "the module is functional in Stop mode"]
2624            pub const LPSPI1_IPG_STOP_MODE_0: u32 = 0;
2625            #[doc = "the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted"]
2626            pub const LPSPI1_IPG_STOP_MODE_1: u32 = 0x01;
2627        }
2628    }
2629    #[doc = "LPSPI1 ipg_doze mode"]
2630    pub mod LPSPI1_IPG_DOZE {
2631        pub const offset: u32 = 9;
2632        pub const mask: u32 = 0x01 << offset;
2633        pub mod R {}
2634        pub mod W {}
2635        pub mod RW {
2636            #[doc = "not in doze mode"]
2637            pub const LPSPI1_IPG_DOZE_0: u32 = 0;
2638            #[doc = "in doze mode"]
2639            pub const LPSPI1_IPG_DOZE_1: u32 = 0x01;
2640        }
2641    }
2642    #[doc = "LPSPI2 stop mode selection, cannot change when ipg_stop is asserted."]
2643    pub mod LPSPI2_IPG_STOP_MODE {
2644        pub const offset: u32 = 10;
2645        pub const mask: u32 = 0x01 << offset;
2646        pub mod R {}
2647        pub mod W {}
2648        pub mod RW {
2649            #[doc = "the module is functional in Stop mode"]
2650            pub const LPSPI2_IPG_STOP_MODE_0: u32 = 0;
2651            #[doc = "the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted"]
2652            pub const LPSPI2_IPG_STOP_MODE_1: u32 = 0x01;
2653        }
2654    }
2655    #[doc = "LPSPI2 ipg_doze mode"]
2656    pub mod LPSPI2_IPG_DOZE {
2657        pub const offset: u32 = 11;
2658        pub const mask: u32 = 0x01 << offset;
2659        pub mod R {}
2660        pub mod W {}
2661        pub mod RW {
2662            #[doc = "not in doze mode"]
2663            pub const LPSPI2_IPG_DOZE_0: u32 = 0;
2664            #[doc = "in doze mode"]
2665            pub const LPSPI2_IPG_DOZE_1: u32 = 0x01;
2666        }
2667    }
2668    #[doc = "LPSPI3 stop mode selection, cannot change when ipg_stop is asserted."]
2669    pub mod LPSPI3_IPG_STOP_MODE {
2670        pub const offset: u32 = 12;
2671        pub const mask: u32 = 0x01 << offset;
2672        pub mod R {}
2673        pub mod W {}
2674        pub mod RW {
2675            #[doc = "the module is functional in Stop mode"]
2676            pub const LPSPI3_IPG_STOP_MODE_0: u32 = 0;
2677            #[doc = "the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted"]
2678            pub const LPSPI3_IPG_STOP_MODE_1: u32 = 0x01;
2679        }
2680    }
2681    #[doc = "LPSPI3 ipg_doze mode"]
2682    pub mod LPSPI3_IPG_DOZE {
2683        pub const offset: u32 = 13;
2684        pub const mask: u32 = 0x01 << offset;
2685        pub mod R {}
2686        pub mod W {}
2687        pub mod RW {
2688            #[doc = "not in doze mode"]
2689            pub const LPSPI3_IPG_DOZE_0: u32 = 0;
2690            #[doc = "in doze mode"]
2691            pub const LPSPI3_IPG_DOZE_1: u32 = 0x01;
2692        }
2693    }
2694    #[doc = "LPSPI4 stop mode selection, cannot change when ipg_stop is asserted."]
2695    pub mod LPSPI4_IPG_STOP_MODE {
2696        pub const offset: u32 = 14;
2697        pub const mask: u32 = 0x01 << offset;
2698        pub mod R {}
2699        pub mod W {}
2700        pub mod RW {
2701            #[doc = "the module is functional in Stop mode"]
2702            pub const LPSPI4_IPG_STOP_MODE_0: u32 = 0;
2703            #[doc = "the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted"]
2704            pub const LPSPI4_IPG_STOP_MODE_1: u32 = 0x01;
2705        }
2706    }
2707    #[doc = "LPSPI4 ipg_doze mode"]
2708    pub mod LPSPI4_IPG_DOZE {
2709        pub const offset: u32 = 15;
2710        pub const mask: u32 = 0x01 << offset;
2711        pub mod R {}
2712        pub mod W {}
2713        pub mod RW {
2714            #[doc = "not in doze mode"]
2715            pub const LPSPI4_IPG_DOZE_0: u32 = 0;
2716            #[doc = "in doze mode"]
2717            pub const LPSPI4_IPG_DOZE_1: u32 = 0x01;
2718        }
2719    }
2720    #[doc = "LPUART1 stop mode selection, cannot change when ipg_stop is asserted."]
2721    pub mod LPUART1_IPG_STOP_MODE {
2722        pub const offset: u32 = 16;
2723        pub const mask: u32 = 0x01 << offset;
2724        pub mod R {}
2725        pub mod W {}
2726        pub mod RW {
2727            #[doc = "the module is functional in Stop mode"]
2728            pub const LPUART1_IPG_STOP_MODE_0: u32 = 0;
2729            #[doc = "the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted"]
2730            pub const LPUART1_IPG_STOP_MODE_1: u32 = 0x01;
2731        }
2732    }
2733    #[doc = "LPUART1 ipg_doze mode"]
2734    pub mod LPUART1_IPG_DOZE {
2735        pub const offset: u32 = 17;
2736        pub const mask: u32 = 0x01 << offset;
2737        pub mod R {}
2738        pub mod W {}
2739        pub mod RW {
2740            #[doc = "not in doze mode"]
2741            pub const LPUART1_IPG_DOZE_0: u32 = 0;
2742            #[doc = "in doze mode"]
2743            pub const LPUART1_IPG_DOZE_1: u32 = 0x01;
2744        }
2745    }
2746    #[doc = "LPUART2 stop mode selection, cannot change when ipg_stop is asserted."]
2747    pub mod LPUART2_IPG_STOP_MODE {
2748        pub const offset: u32 = 18;
2749        pub const mask: u32 = 0x01 << offset;
2750        pub mod R {}
2751        pub mod W {}
2752        pub mod RW {
2753            #[doc = "the module is functional in Stop mode"]
2754            pub const LPUART2_IPG_STOP_MODE_0: u32 = 0;
2755            #[doc = "the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted"]
2756            pub const LPUART2_IPG_STOP_MODE_1: u32 = 0x01;
2757        }
2758    }
2759    #[doc = "LPUART2 ipg_doze mode"]
2760    pub mod LPUART2_IPG_DOZE {
2761        pub const offset: u32 = 19;
2762        pub const mask: u32 = 0x01 << offset;
2763        pub mod R {}
2764        pub mod W {}
2765        pub mod RW {
2766            #[doc = "not in doze mode"]
2767            pub const LPUART2_IPG_DOZE_0: u32 = 0;
2768            #[doc = "in doze mode"]
2769            pub const LPUART2_IPG_DOZE_1: u32 = 0x01;
2770        }
2771    }
2772    #[doc = "LPUART3 stop mode selection, cannot change when ipg_stop is asserted."]
2773    pub mod LPUART3_IPG_STOP_MODE {
2774        pub const offset: u32 = 20;
2775        pub const mask: u32 = 0x01 << offset;
2776        pub mod R {}
2777        pub mod W {}
2778        pub mod RW {
2779            #[doc = "the module is functional in Stop mode"]
2780            pub const LPUART3_IPG_STOP_MODE_0: u32 = 0;
2781            #[doc = "the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted"]
2782            pub const LPUART3_IPG_STOP_MODE_1: u32 = 0x01;
2783        }
2784    }
2785    #[doc = "LPUART3 ipg_doze mode"]
2786    pub mod LPUART3_IPG_DOZE {
2787        pub const offset: u32 = 21;
2788        pub const mask: u32 = 0x01 << offset;
2789        pub mod R {}
2790        pub mod W {}
2791        pub mod RW {
2792            #[doc = "not in doze mode"]
2793            pub const LPUART3_IPG_DOZE_0: u32 = 0;
2794            #[doc = "in doze mode"]
2795            pub const LPUART3_IPG_DOZE_1: u32 = 0x01;
2796        }
2797    }
2798    #[doc = "LPUART4 stop mode selection, cannot change when ipg_stop is asserted."]
2799    pub mod LPUART4_IPG_STOP_MODE {
2800        pub const offset: u32 = 22;
2801        pub const mask: u32 = 0x01 << offset;
2802        pub mod R {}
2803        pub mod W {}
2804        pub mod RW {
2805            #[doc = "the module is functional in Stop mode"]
2806            pub const LPUART4_IPG_STOP_MODE_0: u32 = 0;
2807            #[doc = "the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted"]
2808            pub const LPUART4_IPG_STOP_MODE_1: u32 = 0x01;
2809        }
2810    }
2811    #[doc = "LPUART4 ipg_doze mode"]
2812    pub mod LPUART4_IPG_DOZE {
2813        pub const offset: u32 = 23;
2814        pub const mask: u32 = 0x01 << offset;
2815        pub mod R {}
2816        pub mod W {}
2817        pub mod RW {
2818            #[doc = "not in doze mode"]
2819            pub const LPUART4_IPG_DOZE_0: u32 = 0;
2820            #[doc = "in doze mode"]
2821            pub const LPUART4_IPG_DOZE_1: u32 = 0x01;
2822        }
2823    }
2824    #[doc = "LPUART5 stop mode selection, cannot change when ipg_stop is asserted."]
2825    pub mod LPUART5_IPG_STOP_MODE {
2826        pub const offset: u32 = 24;
2827        pub const mask: u32 = 0x01 << offset;
2828        pub mod R {}
2829        pub mod W {}
2830        pub mod RW {
2831            #[doc = "the module is functional in Stop mode"]
2832            pub const LPUART5_IPG_STOP_MODE_0: u32 = 0;
2833            #[doc = "the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted"]
2834            pub const LPUART5_IPG_STOP_MODE_1: u32 = 0x01;
2835        }
2836    }
2837    #[doc = "LPUART5 ipg_doze mode"]
2838    pub mod LPUART5_IPG_DOZE {
2839        pub const offset: u32 = 25;
2840        pub const mask: u32 = 0x01 << offset;
2841        pub mod R {}
2842        pub mod W {}
2843        pub mod RW {
2844            #[doc = "not in doze mode"]
2845            pub const LPUART5_IPG_DOZE_0: u32 = 0;
2846            #[doc = "in doze mode"]
2847            pub const LPUART5_IPG_DOZE_1: u32 = 0x01;
2848        }
2849    }
2850    #[doc = "LPUART6 stop mode selection, cannot change when ipg_stop is asserted."]
2851    pub mod LPUART6_IPG_STOP_MODE {
2852        pub const offset: u32 = 26;
2853        pub const mask: u32 = 0x01 << offset;
2854        pub mod R {}
2855        pub mod W {}
2856        pub mod RW {
2857            #[doc = "the module is functional in Stop mode"]
2858            pub const LPUART6_IPG_STOP_MODE_0: u32 = 0;
2859            #[doc = "the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted"]
2860            pub const LPUART6_IPG_STOP_MODE_1: u32 = 0x01;
2861        }
2862    }
2863    #[doc = "LPUART6 ipg_doze mode"]
2864    pub mod LPUART6_IPG_DOZE {
2865        pub const offset: u32 = 27;
2866        pub const mask: u32 = 0x01 << offset;
2867        pub mod R {}
2868        pub mod W {}
2869        pub mod RW {
2870            #[doc = "not in doze mode"]
2871            pub const LPUART6_IPG_DOZE_0: u32 = 0;
2872            #[doc = "in doze mode"]
2873            pub const LPUART6_IPG_DOZE_1: u32 = 0x01;
2874        }
2875    }
2876    #[doc = "LPUART7 stop mode selection, cannot change when ipg_stop is asserted."]
2877    pub mod LPUART7_IPG_STOP_MODE {
2878        pub const offset: u32 = 28;
2879        pub const mask: u32 = 0x01 << offset;
2880        pub mod R {}
2881        pub mod W {}
2882        pub mod RW {
2883            #[doc = "the module is functional in Stop mode"]
2884            pub const LPUART7_IPG_STOP_MODE_0: u32 = 0;
2885            #[doc = "the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted"]
2886            pub const LPUART7_IPG_STOP_MODE_1: u32 = 0x01;
2887        }
2888    }
2889    #[doc = "LPUART7 ipg_doze mode"]
2890    pub mod LPUART7_IPG_DOZE {
2891        pub const offset: u32 = 29;
2892        pub const mask: u32 = 0x01 << offset;
2893        pub mod R {}
2894        pub mod W {}
2895        pub mod RW {
2896            #[doc = "not in doze mode"]
2897            pub const LPUART7_IPG_DOZE_0: u32 = 0;
2898            #[doc = "in doze mode"]
2899            pub const LPUART7_IPG_DOZE_1: u32 = 0x01;
2900        }
2901    }
2902    #[doc = "LPUART8 stop mode selection, cannot change when ipg_stop is asserted."]
2903    pub mod LPUART8_IPG_STOP_MODE {
2904        pub const offset: u32 = 30;
2905        pub const mask: u32 = 0x01 << offset;
2906        pub mod R {}
2907        pub mod W {}
2908        pub mod RW {
2909            #[doc = "the module is functional in Stop mode"]
2910            pub const LPUART8_IPG_STOP_MODE_0: u32 = 0;
2911            #[doc = "the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted"]
2912            pub const LPUART8_IPG_STOP_MODE_1: u32 = 0x01;
2913        }
2914    }
2915    #[doc = "LPUART8 ipg_doze mode"]
2916    pub mod LPUART8_IPG_DOZE {
2917        pub const offset: u32 = 31;
2918        pub const mask: u32 = 0x01 << offset;
2919        pub mod R {}
2920        pub mod W {}
2921        pub mod RW {
2922            #[doc = "not in doze mode"]
2923            pub const LPUART8_IPG_DOZE_0: u32 = 0;
2924            #[doc = "in doze mode"]
2925            pub const LPUART8_IPG_DOZE_1: u32 = 0x01;
2926        }
2927    }
2928}
2929#[doc = "GPR10 General Purpose Register"]
2930pub mod GPR10 {
2931    #[doc = "ARM non-secure (non-invasive) debug enable"]
2932    pub mod NIDEN {
2933        pub const offset: u32 = 0;
2934        pub const mask: u32 = 0x01 << offset;
2935        pub mod R {}
2936        pub mod W {}
2937        pub mod RW {
2938            #[doc = "Debug turned off."]
2939            pub const NIDEN_0: u32 = 0;
2940            #[doc = "Debug enabled (default)."]
2941            pub const NIDEN_1: u32 = 0x01;
2942        }
2943    }
2944    #[doc = "ARM invasive debug enable"]
2945    pub mod DBG_EN {
2946        pub const offset: u32 = 1;
2947        pub const mask: u32 = 0x01 << offset;
2948        pub mod R {}
2949        pub mod W {}
2950        pub mod RW {
2951            #[doc = "Debug turned off."]
2952            pub const DBG_EN_0: u32 = 0;
2953            #[doc = "Debug enabled (default)."]
2954            pub const DBG_EN_1: u32 = 0x01;
2955        }
2956    }
2957    #[doc = "Security error response enable for all security gaskets (on both AHB and AXI buses)"]
2958    pub mod SEC_ERR_RESP {
2959        pub const offset: u32 = 2;
2960        pub const mask: u32 = 0x01 << offset;
2961        pub mod R {}
2962        pub mod W {}
2963        pub mod RW {
2964            #[doc = "OKEY response"]
2965            pub const SEC_ERR_RESP_0: u32 = 0;
2966            #[doc = "SLVError (default)"]
2967            pub const SEC_ERR_RESP_1: u32 = 0x01;
2968        }
2969    }
2970    #[doc = "DCP Key selection bit."]
2971    pub mod DCPKEY_OCOTP_OR_KEYMUX {
2972        pub const offset: u32 = 4;
2973        pub const mask: u32 = 0x01 << offset;
2974        pub mod R {}
2975        pub mod W {}
2976        pub mod RW {
2977            #[doc = "Select key from Key MUX (SNVS/OTPMK)."]
2978            pub const DCPKEY_OCOTP_OR_KEYMUX_0: u32 = 0;
2979            #[doc = "Select key from OCOTP (SW_GP2)."]
2980            pub const DCPKEY_OCOTP_OR_KEYMUX_1: u32 = 0x01;
2981        }
2982    }
2983    #[doc = "OCRAM TrustZone (TZ) enable."]
2984    pub mod OCRAM_TZ_EN {
2985        pub const offset: u32 = 8;
2986        pub const mask: u32 = 0x01 << offset;
2987        pub mod R {}
2988        pub mod W {}
2989        pub mod RW {
2990            #[doc = "The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor)."]
2991            pub const OCRAM_TZ_EN_0: u32 = 0;
2992            #[doc = "The TrustZone feature is enabled. Access to address in the range specified by \\[ENDADDR:STARTADDR\\] follows the execution mode access policy described in CSU chapter."]
2993            pub const OCRAM_TZ_EN_1: u32 = 0x01;
2994        }
2995    }
2996    #[doc = "OCRAM TrustZone (TZ) start address"]
2997    pub mod OCRAM_TZ_ADDR {
2998        pub const offset: u32 = 9;
2999        pub const mask: u32 = 0x7f << offset;
3000        pub mod R {}
3001        pub mod W {}
3002        pub mod RW {}
3003    }
3004    #[doc = "Lock NIDEN field for changes"]
3005    pub mod LOCK_NIDEN {
3006        pub const offset: u32 = 16;
3007        pub const mask: u32 = 0x01 << offset;
3008        pub mod R {}
3009        pub mod W {}
3010        pub mod RW {
3011            #[doc = "Field is not locked"]
3012            pub const LOCK_NIDEN_0: u32 = 0;
3013            #[doc = "Field is locked (read access only)"]
3014            pub const LOCK_NIDEN_1: u32 = 0x01;
3015        }
3016    }
3017    #[doc = "Lock DBG_EN field for changes"]
3018    pub mod LOCK_DBG_EN {
3019        pub const offset: u32 = 17;
3020        pub const mask: u32 = 0x01 << offset;
3021        pub mod R {}
3022        pub mod W {}
3023        pub mod RW {
3024            #[doc = "Field is not locked"]
3025            pub const LOCK_DBG_EN_0: u32 = 0;
3026            #[doc = "Field is locked (read access only)"]
3027            pub const LOCK_DBG_EN_1: u32 = 0x01;
3028        }
3029    }
3030    #[doc = "Lock SEC_ERR_RESP field for changes"]
3031    pub mod LOCK_SEC_ERR_RESP {
3032        pub const offset: u32 = 18;
3033        pub const mask: u32 = 0x01 << offset;
3034        pub mod R {}
3035        pub mod W {}
3036        pub mod RW {
3037            #[doc = "Field is not locked"]
3038            pub const LOCK_SEC_ERR_RESP_0: u32 = 0;
3039            #[doc = "Field is locked (read access only)"]
3040            pub const LOCK_SEC_ERR_RESP_1: u32 = 0x01;
3041        }
3042    }
3043    #[doc = "Lock DCP Key OCOTP/Key MUX selection bit"]
3044    pub mod LOCK_DCPKEY_OCOTP_OR_KEYMUX {
3045        pub const offset: u32 = 20;
3046        pub const mask: u32 = 0x01 << offset;
3047        pub mod R {}
3048        pub mod W {}
3049        pub mod RW {
3050            #[doc = "Field is not locked"]
3051            pub const LOCK_DCPKEY_OCOTP_OR_KEYMUX_0: u32 = 0;
3052            #[doc = "Field is locked (read access only)"]
3053            pub const LOCK_DCPKEY_OCOTP_OR_KEYMUX_1: u32 = 0x01;
3054        }
3055    }
3056    #[doc = "Lock OCRAM_TZ_EN field for changes"]
3057    pub mod LOCK_OCRAM_TZ_EN {
3058        pub const offset: u32 = 24;
3059        pub const mask: u32 = 0x01 << offset;
3060        pub mod R {}
3061        pub mod W {}
3062        pub mod RW {
3063            #[doc = "Field is not locked"]
3064            pub const LOCK_OCRAM_TZ_EN_0: u32 = 0;
3065            #[doc = "Field is locked (read access only)"]
3066            pub const LOCK_OCRAM_TZ_EN_1: u32 = 0x01;
3067        }
3068    }
3069    #[doc = "Lock OCRAM_TZ_ADDR field for changes"]
3070    pub mod LOCK_OCRAM_TZ_ADDR {
3071        pub const offset: u32 = 25;
3072        pub const mask: u32 = 0x7f << offset;
3073        pub mod R {}
3074        pub mod W {}
3075        pub mod RW {
3076            #[doc = "Field is not locked"]
3077            pub const LOCK_OCRAM_TZ_ADDR_0: u32 = 0;
3078            #[doc = "Field is locked (read access only)"]
3079            pub const LOCK_OCRAM_TZ_ADDR_1: u32 = 0x01;
3080        }
3081    }
3082}
3083#[doc = "GPR11 General Purpose Register"]
3084pub mod GPR11 {
3085    #[doc = "Access control of memory region-0"]
3086    pub mod M7_APC_AC_R0_CTRL {
3087        pub const offset: u32 = 0;
3088        pub const mask: u32 = 0x03 << offset;
3089        pub mod R {}
3090        pub mod W {}
3091        pub mod RW {
3092            #[doc = "No access protection"]
3093            pub const M7_APC_AC_R0_CTRL_0: u32 = 0;
3094            #[doc = "M7 debug protection enabled"]
3095            pub const M7_APC_AC_R0_CTRL_1: u32 = 0x01;
3096            #[doc = "FlexSPI access protection"]
3097            pub const M7_APC_AC_R0_CTRL_2: u32 = 0x02;
3098            #[doc = "Both M7 debug and FlexSPI access are protected"]
3099            pub const M7_APC_AC_R0_CTRL_3: u32 = 0x03;
3100        }
3101    }
3102    #[doc = "Access control of memory region-1"]
3103    pub mod M7_APC_AC_R1_CTRL {
3104        pub const offset: u32 = 2;
3105        pub const mask: u32 = 0x03 << offset;
3106        pub mod R {}
3107        pub mod W {}
3108        pub mod RW {
3109            #[doc = "No access protection"]
3110            pub const M7_APC_AC_R1_CTRL_0: u32 = 0;
3111            #[doc = "M7 debug protection enabled"]
3112            pub const M7_APC_AC_R1_CTRL_1: u32 = 0x01;
3113            #[doc = "FlexSPI access protection"]
3114            pub const M7_APC_AC_R1_CTRL_2: u32 = 0x02;
3115            #[doc = "Both M7 debug and FlexSPI access are protected"]
3116            pub const M7_APC_AC_R1_CTRL_3: u32 = 0x03;
3117        }
3118    }
3119    #[doc = "Access control of memory region-2"]
3120    pub mod M7_APC_AC_R2_CTRL {
3121        pub const offset: u32 = 4;
3122        pub const mask: u32 = 0x03 << offset;
3123        pub mod R {}
3124        pub mod W {}
3125        pub mod RW {
3126            #[doc = "No access protection"]
3127            pub const M7_APC_AC_R2_CTRL_0: u32 = 0;
3128            #[doc = "M7 debug protection enabled"]
3129            pub const M7_APC_AC_R2_CTRL_1: u32 = 0x01;
3130            #[doc = "FlexSPI access protection"]
3131            pub const M7_APC_AC_R2_CTRL_2: u32 = 0x02;
3132            #[doc = "Both M7 debug and FlexSPI access are protected"]
3133            pub const M7_APC_AC_R2_CTRL_3: u32 = 0x03;
3134        }
3135    }
3136    #[doc = "Access control of memory region-3"]
3137    pub mod M7_APC_AC_R3_CTRL {
3138        pub const offset: u32 = 6;
3139        pub const mask: u32 = 0x03 << offset;
3140        pub mod R {}
3141        pub mod W {}
3142        pub mod RW {
3143            #[doc = "No access protection"]
3144            pub const M7_APC_AC_R3_CTRL_0: u32 = 0;
3145            #[doc = "M7 debug protection enabled"]
3146            pub const M7_APC_AC_R3_CTRL_1: u32 = 0x01;
3147            #[doc = "FlexSPI access protection"]
3148            pub const M7_APC_AC_R3_CTRL_2: u32 = 0x02;
3149            #[doc = "Both M7 debug and FlexSPI access are protected"]
3150            pub const M7_APC_AC_R3_CTRL_3: u32 = 0x03;
3151        }
3152    }
3153    #[doc = "BEE data decryption of memory region-n (n = 3 to 0)"]
3154    pub mod BEE_DE_RX_EN {
3155        pub const offset: u32 = 8;
3156        pub const mask: u32 = 0x0f << offset;
3157        pub mod R {}
3158        pub mod W {}
3159        pub mod RW {}
3160    }
3161}
3162#[doc = "GPR12 General Purpose Register"]
3163pub mod GPR12 {
3164    #[doc = "FlexIO1 stop mode selection. Cannot change when ipg_stop is asserted."]
3165    pub mod FLEXIO1_IPG_STOP_MODE {
3166        pub const offset: u32 = 0;
3167        pub const mask: u32 = 0x01 << offset;
3168        pub mod R {}
3169        pub mod W {}
3170        pub mod RW {
3171            #[doc = "FlexIO1 is functional in Stop mode."]
3172            pub const FLEXIO1_IPG_STOP_MODE_0: u32 = 0;
3173            #[doc = "When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO1 is not functional in Stop mode."]
3174            pub const FLEXIO1_IPG_STOP_MODE_1: u32 = 0x01;
3175        }
3176    }
3177    #[doc = "FLEXIO1 ipg_doze mode"]
3178    pub mod FLEXIO1_IPG_DOZE {
3179        pub const offset: u32 = 1;
3180        pub const mask: u32 = 0x01 << offset;
3181        pub mod R {}
3182        pub mod W {}
3183        pub mod RW {
3184            #[doc = "FLEXIO1 is not in doze mode"]
3185            pub const FLEXIO1_IPG_DOZE_0: u32 = 0;
3186            #[doc = "FLEXIO1 is in doze mode"]
3187            pub const FLEXIO1_IPG_DOZE_1: u32 = 0x01;
3188        }
3189    }
3190    #[doc = "FlexIO2 stop mode selection. Cannot change when ipg_stop is asserted."]
3191    pub mod FLEXIO2_IPG_STOP_MODE {
3192        pub const offset: u32 = 2;
3193        pub const mask: u32 = 0x01 << offset;
3194        pub mod R {}
3195        pub mod W {}
3196        pub mod RW {
3197            #[doc = "FlexIO2 is functional in Stop mode."]
3198            pub const FLEXIO2_IPG_STOP_MODE_0: u32 = 0;
3199            #[doc = "When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO2 is not functional in Stop mode."]
3200            pub const FLEXIO2_IPG_STOP_MODE_1: u32 = 0x01;
3201        }
3202    }
3203    #[doc = "FLEXIO2 ipg_doze mode"]
3204    pub mod FLEXIO2_IPG_DOZE {
3205        pub const offset: u32 = 3;
3206        pub const mask: u32 = 0x01 << offset;
3207        pub mod R {}
3208        pub mod W {}
3209        pub mod RW {
3210            #[doc = "FLEXIO2 is not in doze mode"]
3211            pub const FLEXIO2_IPG_DOZE_0: u32 = 0;
3212            #[doc = "FLEXIO2 is in doze mode"]
3213            pub const FLEXIO2_IPG_DOZE_1: u32 = 0x01;
3214        }
3215    }
3216    #[doc = "ACMP stop mode selection. Cannot change when ipg_stop is asserted."]
3217    pub mod ACMP_IPG_STOP_MODE {
3218        pub const offset: u32 = 4;
3219        pub const mask: u32 = 0x01 << offset;
3220        pub mod R {}
3221        pub mod W {}
3222        pub mod RW {
3223            #[doc = "ACMP is functional in Stop mode."]
3224            pub const ACMP_IPG_STOP_MODE_0: u32 = 0;
3225            #[doc = "When this bit is equal to 1'b1 and ipg_stop is asserted, ACMP is not functional in Stop mode."]
3226            pub const ACMP_IPG_STOP_MODE_1: u32 = 0x01;
3227        }
3228    }
3229    #[doc = "FlexIO3 stop mode selection. Cannot change when ipg_stop is asserted."]
3230    pub mod FLEXIO3_IPG_STOP_MODE {
3231        pub const offset: u32 = 5;
3232        pub const mask: u32 = 0x01 << offset;
3233        pub mod R {}
3234        pub mod W {}
3235        pub mod RW {
3236            #[doc = "FlexIO3 is functional in Stop mode."]
3237            pub const FLEXIO3_IPG_STOP_MODE_0: u32 = 0;
3238            #[doc = "When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO3 is not functional in Stop mode."]
3239            pub const FLEXIO3_IPG_STOP_MODE_1: u32 = 0x01;
3240        }
3241    }
3242    #[doc = "FLEXIO3 ipg_doze mode"]
3243    pub mod FLEXIO3_IPG_DOZE {
3244        pub const offset: u32 = 6;
3245        pub const mask: u32 = 0x01 << offset;
3246        pub mod R {}
3247        pub mod W {}
3248        pub mod RW {
3249            #[doc = "FLEXIO3 is not in doze mode"]
3250            pub const FLEXIO3_IPG_DOZE_0: u32 = 0;
3251            #[doc = "FLEXIO3 is in doze mode"]
3252            pub const FLEXIO3_IPG_DOZE_1: u32 = 0x01;
3253        }
3254    }
3255}
3256#[doc = "GPR13 General Purpose Register"]
3257pub mod GPR13 {
3258    #[doc = "uSDHC block cacheable attribute value of AXI read transactions"]
3259    pub mod ARCACHE_USDHC {
3260        pub const offset: u32 = 0;
3261        pub const mask: u32 = 0x01 << offset;
3262        pub mod R {}
3263        pub mod W {}
3264        pub mod RW {
3265            #[doc = "Cacheable attribute is off for read transactions."]
3266            pub const ARCACHE_USDHC_0: u32 = 0;
3267            #[doc = "Cacheable attribute is on for read transactions."]
3268            pub const ARCACHE_USDHC_1: u32 = 0x01;
3269        }
3270    }
3271    #[doc = "uSDHC block cacheable attribute value of AXI write transactions"]
3272    pub mod AWCACHE_USDHC {
3273        pub const offset: u32 = 1;
3274        pub const mask: u32 = 0x01 << offset;
3275        pub mod R {}
3276        pub mod W {}
3277        pub mod RW {
3278            #[doc = "Cacheable attribute is off for write transactions."]
3279            pub const AWCACHE_USDHC_0: u32 = 0;
3280            #[doc = "Cacheable attribute is on for write transactions."]
3281            pub const AWCACHE_USDHC_1: u32 = 0x01;
3282        }
3283    }
3284    #[doc = "CANFD stop request."]
3285    pub mod CANFD_STOP_REQ {
3286        pub const offset: u32 = 4;
3287        pub const mask: u32 = 0x01 << offset;
3288        pub mod R {}
3289        pub mod W {}
3290        pub mod RW {
3291            #[doc = "stop request off"]
3292            pub const CANFD_STOP_REQ_0: u32 = 0;
3293            #[doc = "stop request on"]
3294            pub const CANFD_STOP_REQ_1: u32 = 0x01;
3295        }
3296    }
3297    #[doc = "ENET block cacheable attribute value of AXI transactions"]
3298    pub mod CACHE_ENET {
3299        pub const offset: u32 = 7;
3300        pub const mask: u32 = 0x01 << offset;
3301        pub mod R {}
3302        pub mod W {}
3303        pub mod RW {
3304            #[doc = "Cacheable attribute is off for read/write transactions."]
3305            pub const CACHE_ENET_0: u32 = 0;
3306            #[doc = "Cacheable attribute is on for read/write transactions."]
3307            pub const CACHE_ENET_1: u32 = 0x01;
3308        }
3309    }
3310    #[doc = "USB block cacheable attribute value of AXI transactions"]
3311    pub mod CACHE_USB {
3312        pub const offset: u32 = 13;
3313        pub const mask: u32 = 0x01 << offset;
3314        pub mod R {}
3315        pub mod W {}
3316        pub mod RW {
3317            #[doc = "Cacheable attribute is off for read/write transactions."]
3318            pub const CACHE_USB_0: u32 = 0;
3319            #[doc = "Cacheable attribute is on for read/write transactions."]
3320            pub const CACHE_USB_1: u32 = 0x01;
3321        }
3322    }
3323    #[doc = "CANFD stop acknowledge."]
3324    pub mod CANFD_STOP_ACK {
3325        pub const offset: u32 = 20;
3326        pub const mask: u32 = 0x01 << offset;
3327        pub mod R {}
3328        pub mod W {}
3329        pub mod RW {
3330            #[doc = "CANFD stop acknowledge is not asserted"]
3331            pub const CANFD_STOP_ACK_0: u32 = 0;
3332            #[doc = "CANFD stop acknowledge is asserted"]
3333            pub const CANFD_STOP_ACK_1: u32 = 0x01;
3334        }
3335    }
3336}
3337#[doc = "GPR14 General Purpose Register"]
3338pub mod GPR14 {
3339    #[doc = "reduces ACMP1 internal bias current by 30%"]
3340    pub mod ACMP1_CMP_IGEN_TRIM_DN {
3341        pub const offset: u32 = 0;
3342        pub const mask: u32 = 0x01 << offset;
3343        pub mod R {}
3344        pub mod W {}
3345        pub mod RW {
3346            #[doc = "no reduce"]
3347            pub const ACMP1_CMP_IGEN_TRIM_DN_0: u32 = 0;
3348            #[doc = "reduces"]
3349            pub const ACMP1_CMP_IGEN_TRIM_DN_1: u32 = 0x01;
3350        }
3351    }
3352    #[doc = "reduces ACMP2 internal bias current by 30%"]
3353    pub mod ACMP2_CMP_IGEN_TRIM_DN {
3354        pub const offset: u32 = 1;
3355        pub const mask: u32 = 0x01 << offset;
3356        pub mod R {}
3357        pub mod W {}
3358        pub mod RW {
3359            #[doc = "no reduce"]
3360            pub const ACMP2_CMP_IGEN_TRIM_DN_0: u32 = 0;
3361            #[doc = "reduces"]
3362            pub const ACMP2_CMP_IGEN_TRIM_DN_1: u32 = 0x01;
3363        }
3364    }
3365    #[doc = "reduces ACMP3 internal bias current by 30%"]
3366    pub mod ACMP3_CMP_IGEN_TRIM_DN {
3367        pub const offset: u32 = 2;
3368        pub const mask: u32 = 0x01 << offset;
3369        pub mod R {}
3370        pub mod W {}
3371        pub mod RW {
3372            #[doc = "no reduce"]
3373            pub const ACMP3_CMP_IGEN_TRIM_DN_0: u32 = 0;
3374            #[doc = "reduces"]
3375            pub const ACMP3_CMP_IGEN_TRIM_DN_1: u32 = 0x01;
3376        }
3377    }
3378    #[doc = "reduces ACMP4 internal bias current by 30%"]
3379    pub mod ACMP4_CMP_IGEN_TRIM_DN {
3380        pub const offset: u32 = 3;
3381        pub const mask: u32 = 0x01 << offset;
3382        pub mod R {}
3383        pub mod W {}
3384        pub mod RW {
3385            #[doc = "no reduce"]
3386            pub const ACMP4_CMP_IGEN_TRIM_DN_0: u32 = 0;
3387            #[doc = "reduces"]
3388            pub const ACMP4_CMP_IGEN_TRIM_DN_1: u32 = 0x01;
3389        }
3390    }
3391    #[doc = "increases ACMP1 internal bias current by 30%"]
3392    pub mod ACMP1_CMP_IGEN_TRIM_UP {
3393        pub const offset: u32 = 4;
3394        pub const mask: u32 = 0x01 << offset;
3395        pub mod R {}
3396        pub mod W {}
3397        pub mod RW {
3398            #[doc = "no increase"]
3399            pub const ACMP1_CMP_IGEN_TRIM_UP_0: u32 = 0;
3400            #[doc = "increases"]
3401            pub const ACMP1_CMP_IGEN_TRIM_UP_1: u32 = 0x01;
3402        }
3403    }
3404    #[doc = "increases ACMP2 internal bias current by 30%"]
3405    pub mod ACMP2_CMP_IGEN_TRIM_UP {
3406        pub const offset: u32 = 5;
3407        pub const mask: u32 = 0x01 << offset;
3408        pub mod R {}
3409        pub mod W {}
3410        pub mod RW {
3411            #[doc = "no increase"]
3412            pub const ACMP2_CMP_IGEN_TRIM_UP_0: u32 = 0;
3413            #[doc = "increases"]
3414            pub const ACMP2_CMP_IGEN_TRIM_UP_1: u32 = 0x01;
3415        }
3416    }
3417    #[doc = "increases ACMP3 internal bias current by 30%"]
3418    pub mod ACMP3_CMP_IGEN_TRIM_UP {
3419        pub const offset: u32 = 6;
3420        pub const mask: u32 = 0x01 << offset;
3421        pub mod R {}
3422        pub mod W {}
3423        pub mod RW {
3424            #[doc = "no increase"]
3425            pub const ACMP3_CMP_IGEN_TRIM_UP_0: u32 = 0;
3426            #[doc = "increases"]
3427            pub const ACMP3_CMP_IGEN_TRIM_UP_1: u32 = 0x01;
3428        }
3429    }
3430    #[doc = "increases ACMP4 internal bias current by 30%"]
3431    pub mod ACMP4_CMP_IGEN_TRIM_UP {
3432        pub const offset: u32 = 7;
3433        pub const mask: u32 = 0x01 << offset;
3434        pub mod R {}
3435        pub mod W {}
3436        pub mod RW {
3437            #[doc = "no increase"]
3438            pub const ACMP4_CMP_IGEN_TRIM_UP_0: u32 = 0;
3439            #[doc = "increases"]
3440            pub const ACMP4_CMP_IGEN_TRIM_UP_1: u32 = 0x01;
3441        }
3442    }
3443    #[doc = "ACMP1 sample_lv source select"]
3444    pub mod ACMP1_SAMPLE_SYNC_EN {
3445        pub const offset: u32 = 8;
3446        pub const mask: u32 = 0x01 << offset;
3447        pub mod R {}
3448        pub mod W {}
3449        pub mod RW {
3450            #[doc = "select XBAR output"]
3451            pub const ACMP1_SAMPLE_SYNC_EN_0: u32 = 0;
3452            #[doc = "select synced sample_lv"]
3453            pub const ACMP1_SAMPLE_SYNC_EN_1: u32 = 0x01;
3454        }
3455    }
3456    #[doc = "ACMP2 sample_lv source select"]
3457    pub mod ACMP2_SAMPLE_SYNC_EN {
3458        pub const offset: u32 = 9;
3459        pub const mask: u32 = 0x01 << offset;
3460        pub mod R {}
3461        pub mod W {}
3462        pub mod RW {
3463            #[doc = "select XBAR output"]
3464            pub const ACMP2_SAMPLE_SYNC_EN_0: u32 = 0;
3465            #[doc = "select synced sample_lv"]
3466            pub const ACMP2_SAMPLE_SYNC_EN_1: u32 = 0x01;
3467        }
3468    }
3469    #[doc = "ACMP3 sample_lv source select"]
3470    pub mod ACMP3_SAMPLE_SYNC_EN {
3471        pub const offset: u32 = 10;
3472        pub const mask: u32 = 0x01 << offset;
3473        pub mod R {}
3474        pub mod W {}
3475        pub mod RW {
3476            #[doc = "select XBAR output"]
3477            pub const ACMP3_SAMPLE_SYNC_EN_0: u32 = 0;
3478            #[doc = "select synced sample_lv"]
3479            pub const ACMP3_SAMPLE_SYNC_EN_1: u32 = 0x01;
3480        }
3481    }
3482    #[doc = "ACMP4 sample_lv source select"]
3483    pub mod ACMP4_SAMPLE_SYNC_EN {
3484        pub const offset: u32 = 11;
3485        pub const mask: u32 = 0x01 << offset;
3486        pub mod R {}
3487        pub mod W {}
3488        pub mod RW {
3489            #[doc = "select XBAR output"]
3490            pub const ACMP4_SAMPLE_SYNC_EN_0: u32 = 0;
3491            #[doc = "select synced sample_lv"]
3492            pub const ACMP4_SAMPLE_SYNC_EN_1: u32 = 0x01;
3493        }
3494    }
3495    #[doc = "ITCM total size configuration"]
3496    pub mod CM7_CFGITCMSZ {
3497        pub const offset: u32 = 16;
3498        pub const mask: u32 = 0x0f << offset;
3499        pub mod R {}
3500        pub mod W {}
3501        pub mod RW {
3502            #[doc = "0 KB (No ITCM)"]
3503            pub const CM7_CFGITCMSZ_0: u32 = 0;
3504            #[doc = "4 KB"]
3505            pub const CM7_CFGITCMSZ_3: u32 = 0x03;
3506            #[doc = "8 KB"]
3507            pub const CM7_CFGITCMSZ_4: u32 = 0x04;
3508            #[doc = "16 KB"]
3509            pub const CM7_CFGITCMSZ_5: u32 = 0x05;
3510            #[doc = "32 KB"]
3511            pub const CM7_CFGITCMSZ_6: u32 = 0x06;
3512            #[doc = "64 KB"]
3513            pub const CM7_CFGITCMSZ_7: u32 = 0x07;
3514            #[doc = "128 KB"]
3515            pub const CM7_CFGITCMSZ_8: u32 = 0x08;
3516            #[doc = "256 KB"]
3517            pub const CM7_CFGITCMSZ_9: u32 = 0x09;
3518            #[doc = "512 KB"]
3519            pub const CM7_CFGITCMSZ_10: u32 = 0x0a;
3520        }
3521    }
3522    #[doc = "DTCM total size configuration"]
3523    pub mod CM7_CFGDTCMSZ {
3524        pub const offset: u32 = 20;
3525        pub const mask: u32 = 0x0f << offset;
3526        pub mod R {}
3527        pub mod W {}
3528        pub mod RW {
3529            #[doc = "0 KB (No DTCM)"]
3530            pub const CM7_CFGDTCMSZ_0: u32 = 0;
3531            #[doc = "4 KB"]
3532            pub const CM7_CFGDTCMSZ_3: u32 = 0x03;
3533            #[doc = "8 KB"]
3534            pub const CM7_CFGDTCMSZ_4: u32 = 0x04;
3535            #[doc = "16 KB"]
3536            pub const CM7_CFGDTCMSZ_5: u32 = 0x05;
3537            #[doc = "32 KB"]
3538            pub const CM7_CFGDTCMSZ_6: u32 = 0x06;
3539            #[doc = "64 KB"]
3540            pub const CM7_CFGDTCMSZ_7: u32 = 0x07;
3541            #[doc = "128 KB"]
3542            pub const CM7_CFGDTCMSZ_8: u32 = 0x08;
3543            #[doc = "256 KB"]
3544            pub const CM7_CFGDTCMSZ_9: u32 = 0x09;
3545            #[doc = "512 KB"]
3546            pub const CM7_CFGDTCMSZ_10: u32 = 0x0a;
3547        }
3548    }
3549}
3550#[doc = "GPR16 General Purpose Register"]
3551pub mod GPR16 {
3552    #[doc = "ITCM enable initialization out of reset"]
3553    pub mod INIT_ITCM_EN {
3554        pub const offset: u32 = 0;
3555        pub const mask: u32 = 0x01 << offset;
3556        pub mod R {}
3557        pub mod W {}
3558        pub mod RW {
3559            #[doc = "ITCM is disabled"]
3560            pub const INIT_ITCM_EN_0: u32 = 0;
3561            #[doc = "ITCM is enabled"]
3562            pub const INIT_ITCM_EN_1: u32 = 0x01;
3563        }
3564    }
3565    #[doc = "DTCM enable initialization out of reset"]
3566    pub mod INIT_DTCM_EN {
3567        pub const offset: u32 = 1;
3568        pub const mask: u32 = 0x01 << offset;
3569        pub mod R {}
3570        pub mod W {}
3571        pub mod RW {
3572            #[doc = "DTCM is disabled"]
3573            pub const INIT_DTCM_EN_0: u32 = 0;
3574            #[doc = "DTCM is enabled"]
3575            pub const INIT_DTCM_EN_1: u32 = 0x01;
3576        }
3577    }
3578    #[doc = "FlexRAM bank config source select"]
3579    pub mod FLEXRAM_BANK_CFG_SEL {
3580        pub const offset: u32 = 2;
3581        pub const mask: u32 = 0x01 << offset;
3582        pub mod R {}
3583        pub mod W {}
3584        pub mod RW {
3585            #[doc = "use fuse value to config"]
3586            pub const FLEXRAM_BANK_CFG_SEL_0: u32 = 0;
3587            #[doc = "use FLEXRAM_BANK_CFG to config"]
3588            pub const FLEXRAM_BANK_CFG_SEL_1: u32 = 0x01;
3589        }
3590    }
3591}
3592#[doc = "GPR17 General Purpose Register"]
3593pub mod GPR17 {
3594    #[doc = "FlexRAM bank config value"]
3595    pub mod FLEXRAM_BANK_CFG {
3596        pub const offset: u32 = 0;
3597        pub const mask: u32 = 0xffff_ffff << offset;
3598        pub mod R {}
3599        pub mod W {}
3600        pub mod RW {}
3601    }
3602}
3603#[doc = "GPR18 General Purpose Register"]
3604pub mod GPR18 {
3605    #[doc = "lock M7_APC_AC_R0_BOT field for changes"]
3606    pub mod LOCK_M7_APC_AC_R0_BOT {
3607        pub const offset: u32 = 0;
3608        pub const mask: u32 = 0x01 << offset;
3609        pub mod R {}
3610        pub mod W {}
3611        pub mod RW {
3612            #[doc = "Register field \\[31:1\\] is not locked"]
3613            pub const LOCK_M7_APC_AC_R0_BOT_0: u32 = 0;
3614            #[doc = "Register field \\[31:1\\] is locked (read access only)"]
3615            pub const LOCK_M7_APC_AC_R0_BOT_1: u32 = 0x01;
3616        }
3617    }
3618    #[doc = "APC end address of memory region-0"]
3619    pub mod M7_APC_AC_R0_BOT {
3620        pub const offset: u32 = 3;
3621        pub const mask: u32 = 0x1fff_ffff << offset;
3622        pub mod R {}
3623        pub mod W {}
3624        pub mod RW {}
3625    }
3626}
3627#[doc = "GPR19 General Purpose Register"]
3628pub mod GPR19 {
3629    #[doc = "lock M7_APC_AC_R0_TOP field for changes"]
3630    pub mod LOCK_M7_APC_AC_R0_TOP {
3631        pub const offset: u32 = 0;
3632        pub const mask: u32 = 0x01 << offset;
3633        pub mod R {}
3634        pub mod W {}
3635        pub mod RW {
3636            #[doc = "Register field \\[31:1\\] is not locked"]
3637            pub const LOCK_M7_APC_AC_R0_TOP_0: u32 = 0;
3638            #[doc = "Register field \\[31:1\\] is locked (read access only)"]
3639            pub const LOCK_M7_APC_AC_R0_TOP_1: u32 = 0x01;
3640        }
3641    }
3642    #[doc = "APC start address of memory region-0"]
3643    pub mod M7_APC_AC_R0_TOP {
3644        pub const offset: u32 = 3;
3645        pub const mask: u32 = 0x1fff_ffff << offset;
3646        pub mod R {}
3647        pub mod W {}
3648        pub mod RW {}
3649    }
3650}
3651#[doc = "GPR20 General Purpose Register"]
3652pub mod GPR20 {
3653    #[doc = "lock M7_APC_AC_R1_BOT field for changes"]
3654    pub mod LOCK_M7_APC_AC_R1_BOT {
3655        pub const offset: u32 = 0;
3656        pub const mask: u32 = 0x01 << offset;
3657        pub mod R {}
3658        pub mod W {}
3659        pub mod RW {
3660            #[doc = "Register field \\[31:1\\] is not locked"]
3661            pub const LOCK_M7_APC_AC_R1_BOT_0: u32 = 0;
3662            #[doc = "Register field \\[31:1\\] is locked (read access only)"]
3663            pub const LOCK_M7_APC_AC_R1_BOT_1: u32 = 0x01;
3664        }
3665    }
3666    #[doc = "APC end address of memory region-1"]
3667    pub mod M7_APC_AC_R1_BOT {
3668        pub const offset: u32 = 3;
3669        pub const mask: u32 = 0x1fff_ffff << offset;
3670        pub mod R {}
3671        pub mod W {}
3672        pub mod RW {}
3673    }
3674}
3675#[doc = "GPR21 General Purpose Register"]
3676pub mod GPR21 {
3677    #[doc = "lock M7_APC_AC_R1_TOP field for changes"]
3678    pub mod LOCK_M7_APC_AC_R1_TOP {
3679        pub const offset: u32 = 0;
3680        pub const mask: u32 = 0x01 << offset;
3681        pub mod R {}
3682        pub mod W {}
3683        pub mod RW {
3684            #[doc = "Register field \\[31:1\\] is not locked"]
3685            pub const LOCK_M7_APC_AC_R1_TOP_0: u32 = 0;
3686            #[doc = "Register field \\[31:1\\] is locked (read access only)"]
3687            pub const LOCK_M7_APC_AC_R1_TOP_1: u32 = 0x01;
3688        }
3689    }
3690    #[doc = "APC start address of memory region-1"]
3691    pub mod M7_APC_AC_R1_TOP {
3692        pub const offset: u32 = 3;
3693        pub const mask: u32 = 0x1fff_ffff << offset;
3694        pub mod R {}
3695        pub mod W {}
3696        pub mod RW {}
3697    }
3698}
3699#[doc = "GPR22 General Purpose Register"]
3700pub mod GPR22 {
3701    #[doc = "lock M7_APC_AC_R2_BOT field for changes"]
3702    pub mod LOCK_M7_APC_AC_R2_BOT {
3703        pub const offset: u32 = 0;
3704        pub const mask: u32 = 0x01 << offset;
3705        pub mod R {}
3706        pub mod W {}
3707        pub mod RW {
3708            #[doc = "Register field \\[31:1\\] is not locked"]
3709            pub const LOCK_M7_APC_AC_R2_BOT_0: u32 = 0;
3710            #[doc = "Register field \\[31:1\\] is locked (read access only)"]
3711            pub const LOCK_M7_APC_AC_R2_BOT_1: u32 = 0x01;
3712        }
3713    }
3714    #[doc = "APC end address of memory region-2"]
3715    pub mod M7_APC_AC_R2_BOT {
3716        pub const offset: u32 = 3;
3717        pub const mask: u32 = 0x1fff_ffff << offset;
3718        pub mod R {}
3719        pub mod W {}
3720        pub mod RW {}
3721    }
3722}
3723#[doc = "GPR23 General Purpose Register"]
3724pub mod GPR23 {
3725    #[doc = "lock M7_APC_AC_R2_TOP field for changes"]
3726    pub mod LOCK_M7_APC_AC_R2_TOP {
3727        pub const offset: u32 = 0;
3728        pub const mask: u32 = 0x01 << offset;
3729        pub mod R {}
3730        pub mod W {}
3731        pub mod RW {
3732            #[doc = "Register field \\[31:1\\] is not locked"]
3733            pub const LOCK_M7_APC_AC_R2_TOP_0: u32 = 0;
3734            #[doc = "Register field \\[31:1\\] is locked (read access only)"]
3735            pub const LOCK_M7_APC_AC_R2_TOP_1: u32 = 0x01;
3736        }
3737    }
3738    #[doc = "APC start address of memory region-2"]
3739    pub mod M7_APC_AC_R2_TOP {
3740        pub const offset: u32 = 3;
3741        pub const mask: u32 = 0x1fff_ffff << offset;
3742        pub mod R {}
3743        pub mod W {}
3744        pub mod RW {}
3745    }
3746}
3747#[doc = "GPR24 General Purpose Register"]
3748pub mod GPR24 {
3749    #[doc = "lock M7_APC_AC_R3_BOT field for changes"]
3750    pub mod LOCK_M7_APC_AC_R3_BOT {
3751        pub const offset: u32 = 0;
3752        pub const mask: u32 = 0x01 << offset;
3753        pub mod R {}
3754        pub mod W {}
3755        pub mod RW {
3756            #[doc = "Register field \\[31:1\\] is not locked"]
3757            pub const LOCK_M7_APC_AC_R3_BOT_0: u32 = 0;
3758            #[doc = "Register field \\[31:1\\] is locked (read access only)"]
3759            pub const LOCK_M7_APC_AC_R3_BOT_1: u32 = 0x01;
3760        }
3761    }
3762    #[doc = "APC end address of memory region-3"]
3763    pub mod M7_APC_AC_R3_BOT {
3764        pub const offset: u32 = 3;
3765        pub const mask: u32 = 0x1fff_ffff << offset;
3766        pub mod R {}
3767        pub mod W {}
3768        pub mod RW {}
3769    }
3770}
3771#[doc = "GPR25 General Purpose Register"]
3772pub mod GPR25 {
3773    #[doc = "lock M7_APC_AC_R3_TOP field for changes"]
3774    pub mod LOCK_M7_APC_AC_R3_TOP {
3775        pub const offset: u32 = 0;
3776        pub const mask: u32 = 0x01 << offset;
3777        pub mod R {}
3778        pub mod W {}
3779        pub mod RW {
3780            #[doc = "Register field \\[31:1\\] is not locked"]
3781            pub const LOCK_M7_APC_AC_R3_TOP_0: u32 = 0;
3782            #[doc = "Register field \\[31:1\\] is locked (read access only)"]
3783            pub const LOCK_M7_APC_AC_R3_TOP_1: u32 = 0x01;
3784        }
3785    }
3786    #[doc = "APC start address of memory region-3"]
3787    pub mod M7_APC_AC_R3_TOP {
3788        pub const offset: u32 = 3;
3789        pub const mask: u32 = 0x1fff_ffff << offset;
3790        pub mod R {}
3791        pub mod W {}
3792        pub mod RW {}
3793    }
3794}
3795#[doc = "GPR26 General Purpose Register"]
3796pub mod GPR26 {
3797    #[doc = "GPIO1 and GPIO6 share same IO MUX function, GPIO_MUX1 selects one GPIO function."]
3798    pub mod GPIO_MUX1_GPIO_SEL {
3799        pub const offset: u32 = 0;
3800        pub const mask: u32 = 0xffff_ffff << offset;
3801        pub mod R {}
3802        pub mod W {}
3803        pub mod RW {}
3804    }
3805}
3806#[doc = "GPR27 General Purpose Register"]
3807pub mod GPR27 {
3808    #[doc = "GPIO2 and GPIO7 share same IO MUX function, GPIO_MUX2 selects one GPIO function."]
3809    pub mod GPIO_MUX2_GPIO_SEL {
3810        pub const offset: u32 = 0;
3811        pub const mask: u32 = 0xffff_ffff << offset;
3812        pub mod R {}
3813        pub mod W {}
3814        pub mod RW {}
3815    }
3816}
3817#[doc = "GPR28 General Purpose Register"]
3818pub mod GPR28 {
3819    #[doc = "GPIO3 and GPIO8 share same IO MUX function, GPIO_MUX3 selects one GPIO function."]
3820    pub mod GPIO_MUX3_GPIO_SEL {
3821        pub const offset: u32 = 0;
3822        pub const mask: u32 = 0xffff_ffff << offset;
3823        pub mod R {}
3824        pub mod W {}
3825        pub mod RW {}
3826    }
3827}
3828#[doc = "GPR29 General Purpose Register"]
3829pub mod GPR29 {
3830    #[doc = "GPIO4 and GPIO9 share same IO MUX function, GPIO_MUX4 selects one GPIO function."]
3831    pub mod GPIO_MUX4_GPIO_SEL {
3832        pub const offset: u32 = 0;
3833        pub const mask: u32 = 0xffff_ffff << offset;
3834        pub mod R {}
3835        pub mod W {}
3836        pub mod RW {}
3837    }
3838}
3839#[doc = "GPR30 General Purpose Register"]
3840pub mod GPR30 {
3841    #[doc = "Start address of flexspi1 and flexspi2"]
3842    pub mod FLEXSPI_REMAP_ADDR_START {
3843        pub const offset: u32 = 12;
3844        pub const mask: u32 = 0x000f_ffff << offset;
3845        pub mod R {}
3846        pub mod W {}
3847        pub mod RW {}
3848    }
3849}
3850#[doc = "GPR31 General Purpose Register"]
3851pub mod GPR31 {
3852    #[doc = "End address of flexspi1 and flexspi2"]
3853    pub mod FLEXSPI_REMAP_ADDR_END {
3854        pub const offset: u32 = 12;
3855        pub const mask: u32 = 0x000f_ffff << offset;
3856        pub mod R {}
3857        pub mod W {}
3858        pub mod RW {}
3859    }
3860}
3861#[doc = "GPR32 General Purpose Register"]
3862pub mod GPR32 {
3863    #[doc = "Offset address of flexspi1 and flexspi2"]
3864    pub mod FLEXSPI_REMAP_ADDR_OFFSET {
3865        pub const offset: u32 = 12;
3866        pub const mask: u32 = 0x000f_ffff << offset;
3867        pub mod R {}
3868        pub mod W {}
3869        pub mod RW {}
3870    }
3871}
3872#[doc = "GPR33 General Purpose Register"]
3873pub mod GPR33 {
3874    #[doc = "OCRAM2 TrustZone (TZ) enable."]
3875    pub mod OCRAM2_TZ_EN {
3876        pub const offset: u32 = 0;
3877        pub const mask: u32 = 0x01 << offset;
3878        pub mod R {}
3879        pub mod W {}
3880        pub mod RW {
3881            #[doc = "The TrustZone feature is disabled. Entire OCRAM2 space is available for all access types (secure/non-secure/user/supervisor)."]
3882            pub const OCRAM2_TZ_EN_0: u32 = 0;
3883            #[doc = "The TrustZone feature is enabled. Access to address in the range specified by \\[ENDADDR:STARTADDR\\] follows the execution mode access policy described in CSU chapter."]
3884            pub const OCRAM2_TZ_EN_1: u32 = 0x01;
3885        }
3886    }
3887    #[doc = "OCRAM2 TrustZone (TZ) start address"]
3888    pub mod OCRAM2_TZ_ADDR {
3889        pub const offset: u32 = 1;
3890        pub const mask: u32 = 0x7f << offset;
3891        pub mod R {}
3892        pub mod W {}
3893        pub mod RW {}
3894    }
3895    #[doc = "Lock OCRAM2_TZ_EN field for changes"]
3896    pub mod LOCK_OCRAM2_TZ_EN {
3897        pub const offset: u32 = 16;
3898        pub const mask: u32 = 0x01 << offset;
3899        pub mod R {}
3900        pub mod W {}
3901        pub mod RW {
3902            #[doc = "Field is not locked"]
3903            pub const LOCK_OCRAM2_TZ_EN_0: u32 = 0;
3904            #[doc = "Field is locked (read access only)"]
3905            pub const LOCK_OCRAM2_TZ_EN_1: u32 = 0x01;
3906        }
3907    }
3908    #[doc = "Lock OCRAM2_TZ_ADDR field for changes"]
3909    pub mod LOCK_OCRAM2_TZ_ADDR {
3910        pub const offset: u32 = 17;
3911        pub const mask: u32 = 0x7f << offset;
3912        pub mod R {}
3913        pub mod W {}
3914        pub mod RW {
3915            #[doc = "Field is not locked"]
3916            pub const LOCK_OCRAM2_TZ_ADDR_0: u32 = 0;
3917            #[doc = "Field is locked (read access only)"]
3918            pub const LOCK_OCRAM2_TZ_ADDR_1: u32 = 0x01;
3919        }
3920    }
3921}
3922#[doc = "GPR34 General Purpose Register"]
3923pub mod GPR34 {
3924    #[doc = "Boot Pin select in SIP_TEST_MUX"]
3925    pub mod SIP_TEST_MUX_BOOT_PIN_SEL {
3926        pub const offset: u32 = 0;
3927        pub const mask: u32 = 0xff << offset;
3928        pub mod R {}
3929        pub mod W {}
3930        pub mod RW {}
3931    }
3932    #[doc = "Enable SIP_TEST_MUX"]
3933    pub mod SIP_TEST_MUX_QSPI_SIP_EN {
3934        pub const offset: u32 = 8;
3935        pub const mask: u32 = 0x01 << offset;
3936        pub mod R {}
3937        pub mod W {}
3938        pub mod RW {
3939            #[doc = "SIP_TEST_MUX is disabled"]
3940            pub const SIP_TEST_MUX_QSPI_SIP_EN_0: u32 = 0;
3941            #[doc = "SIP_TEST_MUX is enabled"]
3942            pub const SIP_TEST_MUX_QSPI_SIP_EN_1: u32 = 0x01;
3943        }
3944    }
3945}