imxrt_ral/blocks/imxrt1061/
ocotp.rs

1#[doc = "OCOTP"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "OTP Controller Control Register"]
5    pub CTRL: crate::RWRegister<u32>,
6    #[doc = "OTP Controller Control Register"]
7    pub CTRL_SET: crate::RWRegister<u32>,
8    #[doc = "OTP Controller Control Register"]
9    pub CTRL_CLR: crate::RWRegister<u32>,
10    #[doc = "OTP Controller Control Register"]
11    pub CTRL_TOG: crate::RWRegister<u32>,
12    #[doc = "OTP Controller Timing Register"]
13    pub TIMING: crate::RWRegister<u32>,
14    _reserved0: [u8; 0x0c],
15    #[doc = "OTP Controller Write Data Register"]
16    pub DATA: crate::RWRegister<u32>,
17    _reserved1: [u8; 0x0c],
18    #[doc = "OTP Controller Write Data Register"]
19    pub READ_CTRL: crate::RWRegister<u32>,
20    _reserved2: [u8; 0x0c],
21    #[doc = "OTP Controller Read Data Register"]
22    pub READ_FUSE_DATA: crate::RWRegister<u32>,
23    _reserved3: [u8; 0x0c],
24    #[doc = "Sticky bit Register"]
25    pub SW_STICKY: crate::RWRegister<u32>,
26    _reserved4: [u8; 0x0c],
27    #[doc = "Software Controllable Signals Register"]
28    pub SCS: crate::RWRegister<u32>,
29    #[doc = "Software Controllable Signals Register"]
30    pub SCS_SET: crate::RWRegister<u32>,
31    #[doc = "Software Controllable Signals Register"]
32    pub SCS_CLR: crate::RWRegister<u32>,
33    #[doc = "Software Controllable Signals Register"]
34    pub SCS_TOG: crate::RWRegister<u32>,
35    #[doc = "OTP Controller CRC test address"]
36    pub CRC_ADDR: crate::RWRegister<u32>,
37    _reserved5: [u8; 0x0c],
38    #[doc = "OTP Controller CRC Value Register"]
39    pub CRC_VALUE: crate::RWRegister<u32>,
40    _reserved6: [u8; 0x0c],
41    #[doc = "OTP Controller Version Register"]
42    pub VERSION: crate::RORegister<u32>,
43    _reserved7: [u8; 0x6c],
44    #[doc = "OTP Controller Timing Register"]
45    pub TIMING2: crate::RWRegister<u32>,
46    _reserved8: [u8; 0x02fc],
47    #[doc = "Value of OTP Bank0 Word0 (Lock controls)"]
48    pub LOCK: crate::RWRegister<u32>,
49    _reserved9: [u8; 0x0c],
50    #[doc = "Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.)"]
51    pub CFG0: crate::RWRegister<u32>,
52    _reserved10: [u8; 0x0c],
53    #[doc = "Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.)"]
54    pub CFG1: crate::RWRegister<u32>,
55    _reserved11: [u8; 0x0c],
56    #[doc = "Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.)"]
57    pub CFG2: crate::RWRegister<u32>,
58    _reserved12: [u8; 0x0c],
59    #[doc = "Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.)"]
60    pub CFG3: crate::RWRegister<u32>,
61    _reserved13: [u8; 0x0c],
62    #[doc = "Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.)"]
63    pub CFG4: crate::RWRegister<u32>,
64    _reserved14: [u8; 0x0c],
65    #[doc = "Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.)"]
66    pub CFG5: crate::RWRegister<u32>,
67    _reserved15: [u8; 0x0c],
68    #[doc = "Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.)"]
69    pub CFG6: crate::RWRegister<u32>,
70    _reserved16: [u8; 0x0c],
71    #[doc = "Value of OTP Bank1 Word0 (Memory Related Info.)"]
72    pub MEM0: crate::RWRegister<u32>,
73    _reserved17: [u8; 0x0c],
74    #[doc = "Value of OTP Bank1 Word1 (Memory Related Info.)"]
75    pub MEM1: crate::RWRegister<u32>,
76    _reserved18: [u8; 0x0c],
77    #[doc = "Value of OTP Bank1 Word2 (Memory Related Info.)"]
78    pub MEM2: crate::RWRegister<u32>,
79    _reserved19: [u8; 0x0c],
80    #[doc = "Value of OTP Bank1 Word3 (Memory Related Info.)"]
81    pub MEM3: crate::RWRegister<u32>,
82    _reserved20: [u8; 0x0c],
83    #[doc = "Value of OTP Bank1 Word4 (Memory Related Info.)"]
84    pub MEM4: crate::RWRegister<u32>,
85    _reserved21: [u8; 0x0c],
86    #[doc = "Value of OTP Bank1 Word5 (Memory Related Info.)"]
87    pub ANA0: crate::RWRegister<u32>,
88    _reserved22: [u8; 0x0c],
89    #[doc = "Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.)"]
90    pub ANA1: crate::RWRegister<u32>,
91    _reserved23: [u8; 0x0c],
92    #[doc = "Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.)"]
93    pub ANA2: crate::RWRegister<u32>,
94    _reserved24: [u8; 0x0c],
95    #[doc = "Value of OTP Bank2 Word0 (OTPMK Key)"]
96    pub OTPMK0: crate::RWRegister<u32>,
97    _reserved25: [u8; 0x0c],
98    #[doc = "Value of OTP Bank2 Word1 (OTPMK Key)"]
99    pub OTPMK1: crate::RWRegister<u32>,
100    _reserved26: [u8; 0x0c],
101    #[doc = "Value of OTP Bank2 Word2 (OTPMK Key)"]
102    pub OTPMK2: crate::RWRegister<u32>,
103    _reserved27: [u8; 0x0c],
104    #[doc = "Value of OTP Bank2 Word3 (OTPMK Key)"]
105    pub OTPMK3: crate::RWRegister<u32>,
106    _reserved28: [u8; 0x0c],
107    #[doc = "Value of OTP Bank2 Word4 (OTPMK Key)"]
108    pub OTPMK4: crate::RWRegister<u32>,
109    _reserved29: [u8; 0x0c],
110    #[doc = "Value of OTP Bank2 Word5 (OTPMK Key)"]
111    pub OTPMK5: crate::RWRegister<u32>,
112    _reserved30: [u8; 0x0c],
113    #[doc = "Value of OTP Bank2 Word6 (OTPMK Key)"]
114    pub OTPMK6: crate::RWRegister<u32>,
115    _reserved31: [u8; 0x0c],
116    #[doc = "Value of OTP Bank2 Word7 (OTPMK Key)"]
117    pub OTPMK7: crate::RWRegister<u32>,
118    _reserved32: [u8; 0x0c],
119    #[doc = "Shadow Register for OTP Bank3 Word0 (SRK Hash)"]
120    pub SRK0: crate::RWRegister<u32>,
121    _reserved33: [u8; 0x0c],
122    #[doc = "Shadow Register for OTP Bank3 Word1 (SRK Hash)"]
123    pub SRK1: crate::RWRegister<u32>,
124    _reserved34: [u8; 0x0c],
125    #[doc = "Shadow Register for OTP Bank3 Word2 (SRK Hash)"]
126    pub SRK2: crate::RWRegister<u32>,
127    _reserved35: [u8; 0x0c],
128    #[doc = "Shadow Register for OTP Bank3 Word3 (SRK Hash)"]
129    pub SRK3: crate::RWRegister<u32>,
130    _reserved36: [u8; 0x0c],
131    #[doc = "Shadow Register for OTP Bank3 Word4 (SRK Hash)"]
132    pub SRK4: crate::RWRegister<u32>,
133    _reserved37: [u8; 0x0c],
134    #[doc = "Shadow Register for OTP Bank3 Word5 (SRK Hash)"]
135    pub SRK5: crate::RWRegister<u32>,
136    _reserved38: [u8; 0x0c],
137    #[doc = "Shadow Register for OTP Bank3 Word6 (SRK Hash)"]
138    pub SRK6: crate::RWRegister<u32>,
139    _reserved39: [u8; 0x0c],
140    #[doc = "Shadow Register for OTP Bank3 Word7 (SRK Hash)"]
141    pub SRK7: crate::RWRegister<u32>,
142    _reserved40: [u8; 0x0c],
143    #[doc = "Value of OTP Bank4 Word0 (Secure JTAG Response Field)"]
144    pub SJC_RESP0: crate::RWRegister<u32>,
145    _reserved41: [u8; 0x0c],
146    #[doc = "Value of OTP Bank4 Word1 (Secure JTAG Response Field)"]
147    pub SJC_RESP1: crate::RWRegister<u32>,
148    _reserved42: [u8; 0x0c],
149    #[doc = "Value of OTP Bank4 Word2 (MAC Address)"]
150    pub MAC0: crate::RWRegister<u32>,
151    _reserved43: [u8; 0x0c],
152    #[doc = "Value of OTP Bank4 Word3 (MAC Address)"]
153    pub MAC1: crate::RWRegister<u32>,
154    _reserved44: [u8; 0x0c],
155    #[doc = "Value of OTP Bank4 Word4 (MAC2 Address)"]
156    pub MAC2: crate::RWRegister<u32>,
157    _reserved45: [u8; 0x0c],
158    #[doc = "Value of OTP Bank4 Word5 (CRC Key)"]
159    pub OTPMK_CRC32: crate::RWRegister<u32>,
160    _reserved46: [u8; 0x0c],
161    #[doc = "Value of OTP Bank4 Word6 (General Purpose Customer Defined Info)"]
162    pub GP1: crate::RWRegister<u32>,
163    _reserved47: [u8; 0x0c],
164    #[doc = "Value of OTP Bank4 Word7 (General Purpose Customer Defined Info)"]
165    pub GP2: crate::RWRegister<u32>,
166    _reserved48: [u8; 0x0c],
167    #[doc = "Value of OTP Bank5 Word0 (SW GP1)"]
168    pub SW_GP1: crate::RWRegister<u32>,
169    _reserved49: [u8; 0x0c],
170    #[doc = "Value of OTP Bank5 Word1 (SW GP2)"]
171    pub SW_GP20: crate::RWRegister<u32>,
172    _reserved50: [u8; 0x0c],
173    #[doc = "Value of OTP Bank5 Word2 (SW GP2)"]
174    pub SW_GP21: crate::RWRegister<u32>,
175    _reserved51: [u8; 0x0c],
176    #[doc = "Value of OTP Bank5 Word3 (SW GP2)"]
177    pub SW_GP22: crate::RWRegister<u32>,
178    _reserved52: [u8; 0x0c],
179    #[doc = "Value of OTP Bank5 Word4 (SW GP2)"]
180    pub SW_GP23: crate::RWRegister<u32>,
181    _reserved53: [u8; 0x0c],
182    #[doc = "Value of OTP Bank5 Word5 (Misc Conf)"]
183    pub MISC_CONF0: crate::RWRegister<u32>,
184    _reserved54: [u8; 0x0c],
185    #[doc = "Value of OTP Bank5 Word6 (Misc Conf)"]
186    pub MISC_CONF1: crate::RWRegister<u32>,
187    _reserved55: [u8; 0x0c],
188    #[doc = "Value of OTP Bank5 Word7 (SRK Revoke)"]
189    pub SRK_REVOKE: crate::RWRegister<u32>,
190    _reserved56: [u8; 0x010c],
191    #[doc = "Value of OTP Bank6 Word0 (ROM Patch)"]
192    pub ROM_PATCH0: crate::RWRegister<u32>,
193    _reserved57: [u8; 0x0c],
194    #[doc = "Value of OTP Bank6 Word1 (ROM Patch)"]
195    pub ROM_PATCH1: crate::RWRegister<u32>,
196    _reserved58: [u8; 0x0c],
197    #[doc = "Value of OTP Bank6 Word2 (ROM Patch)"]
198    pub ROM_PATCH2: crate::RWRegister<u32>,
199    _reserved59: [u8; 0x0c],
200    #[doc = "Value of OTP Bank6 Word3 (ROM Patch)"]
201    pub ROM_PATCH3: crate::RWRegister<u32>,
202    _reserved60: [u8; 0x0c],
203    #[doc = "Value of OTP Bank6 Word4 (ROM Patch)"]
204    pub ROM_PATCH4: crate::RWRegister<u32>,
205    _reserved61: [u8; 0x0c],
206    #[doc = "Value of OTP Bank6 Word5 (ROM Patch)"]
207    pub ROM_PATCH5: crate::RWRegister<u32>,
208    _reserved62: [u8; 0x0c],
209    #[doc = "Value of OTP Bank6 Word6 (ROM Patch)"]
210    pub ROM_PATCH6: crate::RWRegister<u32>,
211    _reserved63: [u8; 0x0c],
212    #[doc = "Value of OTP Bank6 Word7 (ROM Patch)"]
213    pub ROM_PATCH7: crate::RWRegister<u32>,
214    _reserved64: [u8; 0x0c],
215    #[doc = "Value of OTP Bank7 Word0 (GP3)"]
216    pub GP30: crate::RWRegister<u32>,
217    _reserved65: [u8; 0x0c],
218    #[doc = "Value of OTP Bank7 Word1 (GP3)"]
219    pub GP31: crate::RWRegister<u32>,
220    _reserved66: [u8; 0x0c],
221    #[doc = "Value of OTP Bank7 Word2 (GP3)"]
222    pub GP32: crate::RWRegister<u32>,
223    _reserved67: [u8; 0x0c],
224    #[doc = "Value of OTP Bank7 Word3 (GP3)"]
225    pub GP33: crate::RWRegister<u32>,
226    _reserved68: [u8; 0x0c],
227    #[doc = "Value of OTP Bank7 Word4 (GP4)"]
228    pub GP40: crate::RWRegister<u32>,
229    _reserved69: [u8; 0x0c],
230    #[doc = "Value of OTP Bank7 Word5 (GP4)"]
231    pub GP41: crate::RWRegister<u32>,
232    _reserved70: [u8; 0x0c],
233    #[doc = "Value of OTP Bank7 Word6 (GP4)"]
234    pub GP42: crate::RWRegister<u32>,
235    _reserved71: [u8; 0x0c],
236    #[doc = "Value of OTP Bank7 Word7 (GP4)"]
237    pub GP43: crate::RWRegister<u32>,
238}
239#[doc = "OTP Controller Control Register"]
240pub mod CTRL {
241    #[doc = "ADDR"]
242    pub mod ADDR {
243        pub const offset: u32 = 0;
244        pub const mask: u32 = 0x3f << offset;
245        pub mod R {}
246        pub mod W {}
247        pub mod RW {}
248    }
249    #[doc = "RSVD0"]
250    pub mod RSVD0 {
251        pub const offset: u32 = 6;
252        pub const mask: u32 = 0x03 << offset;
253        pub mod R {}
254        pub mod W {}
255        pub mod RW {}
256    }
257    #[doc = "BUSY"]
258    pub mod BUSY {
259        pub const offset: u32 = 8;
260        pub const mask: u32 = 0x01 << offset;
261        pub mod R {}
262        pub mod W {}
263        pub mod RW {}
264    }
265    #[doc = "ERROR"]
266    pub mod ERROR {
267        pub const offset: u32 = 9;
268        pub const mask: u32 = 0x01 << offset;
269        pub mod R {}
270        pub mod W {}
271        pub mod RW {}
272    }
273    #[doc = "RELOAD_SHADOWS"]
274    pub mod RELOAD_SHADOWS {
275        pub const offset: u32 = 10;
276        pub const mask: u32 = 0x01 << offset;
277        pub mod R {}
278        pub mod W {}
279        pub mod RW {}
280    }
281    #[doc = "CRC_TEST"]
282    pub mod CRC_TEST {
283        pub const offset: u32 = 11;
284        pub const mask: u32 = 0x01 << offset;
285        pub mod R {}
286        pub mod W {}
287        pub mod RW {}
288    }
289    #[doc = "CRC_FAIL"]
290    pub mod CRC_FAIL {
291        pub const offset: u32 = 12;
292        pub const mask: u32 = 0x01 << offset;
293        pub mod R {}
294        pub mod W {}
295        pub mod RW {}
296    }
297    #[doc = "RSVD1"]
298    pub mod RSVD1 {
299        pub const offset: u32 = 13;
300        pub const mask: u32 = 0x07 << offset;
301        pub mod R {}
302        pub mod W {}
303        pub mod RW {}
304    }
305    #[doc = "WR_UNLOCK"]
306    pub mod WR_UNLOCK {
307        pub const offset: u32 = 16;
308        pub const mask: u32 = 0xffff << offset;
309        pub mod R {}
310        pub mod W {}
311        pub mod RW {
312            #[doc = "Key needed to unlock HW_OCOTP_DATA register."]
313            pub const KEY: u32 = 0x3e77;
314        }
315    }
316}
317#[doc = "OTP Controller Control Register"]
318pub mod CTRL_SET {
319    #[doc = "ADDR"]
320    pub mod ADDR {
321        pub const offset: u32 = 0;
322        pub const mask: u32 = 0x3f << offset;
323        pub mod R {}
324        pub mod W {}
325        pub mod RW {}
326    }
327    #[doc = "RSVD0"]
328    pub mod RSVD0 {
329        pub const offset: u32 = 6;
330        pub const mask: u32 = 0x03 << offset;
331        pub mod R {}
332        pub mod W {}
333        pub mod RW {}
334    }
335    #[doc = "BUSY"]
336    pub mod BUSY {
337        pub const offset: u32 = 8;
338        pub const mask: u32 = 0x01 << offset;
339        pub mod R {}
340        pub mod W {}
341        pub mod RW {}
342    }
343    #[doc = "ERROR"]
344    pub mod ERROR {
345        pub const offset: u32 = 9;
346        pub const mask: u32 = 0x01 << offset;
347        pub mod R {}
348        pub mod W {}
349        pub mod RW {}
350    }
351    #[doc = "RELOAD_SHADOWS"]
352    pub mod RELOAD_SHADOWS {
353        pub const offset: u32 = 10;
354        pub const mask: u32 = 0x01 << offset;
355        pub mod R {}
356        pub mod W {}
357        pub mod RW {}
358    }
359    #[doc = "CRC_TEST"]
360    pub mod CRC_TEST {
361        pub const offset: u32 = 11;
362        pub const mask: u32 = 0x01 << offset;
363        pub mod R {}
364        pub mod W {}
365        pub mod RW {}
366    }
367    #[doc = "CRC_FAIL"]
368    pub mod CRC_FAIL {
369        pub const offset: u32 = 12;
370        pub const mask: u32 = 0x01 << offset;
371        pub mod R {}
372        pub mod W {}
373        pub mod RW {}
374    }
375    #[doc = "RSVD1"]
376    pub mod RSVD1 {
377        pub const offset: u32 = 13;
378        pub const mask: u32 = 0x07 << offset;
379        pub mod R {}
380        pub mod W {}
381        pub mod RW {}
382    }
383    #[doc = "WR_UNLOCK"]
384    pub mod WR_UNLOCK {
385        pub const offset: u32 = 16;
386        pub const mask: u32 = 0xffff << offset;
387        pub mod R {}
388        pub mod W {}
389        pub mod RW {}
390    }
391}
392#[doc = "OTP Controller Control Register"]
393pub mod CTRL_CLR {
394    #[doc = "ADDR"]
395    pub mod ADDR {
396        pub const offset: u32 = 0;
397        pub const mask: u32 = 0x3f << offset;
398        pub mod R {}
399        pub mod W {}
400        pub mod RW {}
401    }
402    #[doc = "RSVD0"]
403    pub mod RSVD0 {
404        pub const offset: u32 = 6;
405        pub const mask: u32 = 0x03 << offset;
406        pub mod R {}
407        pub mod W {}
408        pub mod RW {}
409    }
410    #[doc = "BUSY"]
411    pub mod BUSY {
412        pub const offset: u32 = 8;
413        pub const mask: u32 = 0x01 << offset;
414        pub mod R {}
415        pub mod W {}
416        pub mod RW {}
417    }
418    #[doc = "ERROR"]
419    pub mod ERROR {
420        pub const offset: u32 = 9;
421        pub const mask: u32 = 0x01 << offset;
422        pub mod R {}
423        pub mod W {}
424        pub mod RW {}
425    }
426    #[doc = "RELOAD_SHADOWS"]
427    pub mod RELOAD_SHADOWS {
428        pub const offset: u32 = 10;
429        pub const mask: u32 = 0x01 << offset;
430        pub mod R {}
431        pub mod W {}
432        pub mod RW {}
433    }
434    #[doc = "CRC_TEST"]
435    pub mod CRC_TEST {
436        pub const offset: u32 = 11;
437        pub const mask: u32 = 0x01 << offset;
438        pub mod R {}
439        pub mod W {}
440        pub mod RW {}
441    }
442    #[doc = "CRC_FAIL"]
443    pub mod CRC_FAIL {
444        pub const offset: u32 = 12;
445        pub const mask: u32 = 0x01 << offset;
446        pub mod R {}
447        pub mod W {}
448        pub mod RW {}
449    }
450    #[doc = "RSVD1"]
451    pub mod RSVD1 {
452        pub const offset: u32 = 13;
453        pub const mask: u32 = 0x07 << offset;
454        pub mod R {}
455        pub mod W {}
456        pub mod RW {}
457    }
458    #[doc = "WR_UNLOCK"]
459    pub mod WR_UNLOCK {
460        pub const offset: u32 = 16;
461        pub const mask: u32 = 0xffff << offset;
462        pub mod R {}
463        pub mod W {}
464        pub mod RW {}
465    }
466}
467#[doc = "OTP Controller Control Register"]
468pub mod CTRL_TOG {
469    #[doc = "ADDR"]
470    pub mod ADDR {
471        pub const offset: u32 = 0;
472        pub const mask: u32 = 0x3f << offset;
473        pub mod R {}
474        pub mod W {}
475        pub mod RW {}
476    }
477    #[doc = "RSVD0"]
478    pub mod RSVD0 {
479        pub const offset: u32 = 6;
480        pub const mask: u32 = 0x03 << offset;
481        pub mod R {}
482        pub mod W {}
483        pub mod RW {}
484    }
485    #[doc = "BUSY"]
486    pub mod BUSY {
487        pub const offset: u32 = 8;
488        pub const mask: u32 = 0x01 << offset;
489        pub mod R {}
490        pub mod W {}
491        pub mod RW {}
492    }
493    #[doc = "ERROR"]
494    pub mod ERROR {
495        pub const offset: u32 = 9;
496        pub const mask: u32 = 0x01 << offset;
497        pub mod R {}
498        pub mod W {}
499        pub mod RW {}
500    }
501    #[doc = "RELOAD_SHADOWS"]
502    pub mod RELOAD_SHADOWS {
503        pub const offset: u32 = 10;
504        pub const mask: u32 = 0x01 << offset;
505        pub mod R {}
506        pub mod W {}
507        pub mod RW {}
508    }
509    #[doc = "CRC_TEST"]
510    pub mod CRC_TEST {
511        pub const offset: u32 = 11;
512        pub const mask: u32 = 0x01 << offset;
513        pub mod R {}
514        pub mod W {}
515        pub mod RW {}
516    }
517    #[doc = "CRC_FAIL"]
518    pub mod CRC_FAIL {
519        pub const offset: u32 = 12;
520        pub const mask: u32 = 0x01 << offset;
521        pub mod R {}
522        pub mod W {}
523        pub mod RW {}
524    }
525    #[doc = "RSVD1"]
526    pub mod RSVD1 {
527        pub const offset: u32 = 13;
528        pub const mask: u32 = 0x07 << offset;
529        pub mod R {}
530        pub mod W {}
531        pub mod RW {}
532    }
533    #[doc = "WR_UNLOCK"]
534    pub mod WR_UNLOCK {
535        pub const offset: u32 = 16;
536        pub const mask: u32 = 0xffff << offset;
537        pub mod R {}
538        pub mod W {}
539        pub mod RW {}
540    }
541}
542#[doc = "OTP Controller Timing Register"]
543pub mod TIMING {
544    #[doc = "STROBE_PROG"]
545    pub mod STROBE_PROG {
546        pub const offset: u32 = 0;
547        pub const mask: u32 = 0x0fff << offset;
548        pub mod R {}
549        pub mod W {}
550        pub mod RW {}
551    }
552    #[doc = "RELAX"]
553    pub mod RELAX {
554        pub const offset: u32 = 12;
555        pub const mask: u32 = 0x0f << offset;
556        pub mod R {}
557        pub mod W {}
558        pub mod RW {}
559    }
560    #[doc = "STROBE_READ"]
561    pub mod STROBE_READ {
562        pub const offset: u32 = 16;
563        pub const mask: u32 = 0x3f << offset;
564        pub mod R {}
565        pub mod W {}
566        pub mod RW {}
567    }
568    #[doc = "WAIT"]
569    pub mod WAIT {
570        pub const offset: u32 = 22;
571        pub const mask: u32 = 0x3f << offset;
572        pub mod R {}
573        pub mod W {}
574        pub mod RW {}
575    }
576    #[doc = "RSRVD0"]
577    pub mod RSRVD0 {
578        pub const offset: u32 = 28;
579        pub const mask: u32 = 0x0f << offset;
580        pub mod R {}
581        pub mod W {}
582        pub mod RW {}
583    }
584}
585#[doc = "OTP Controller Write Data Register"]
586pub mod DATA {
587    #[doc = "DATA"]
588    pub mod DATA {
589        pub const offset: u32 = 0;
590        pub const mask: u32 = 0xffff_ffff << offset;
591        pub mod R {}
592        pub mod W {}
593        pub mod RW {}
594    }
595}
596#[doc = "OTP Controller Write Data Register"]
597pub mod READ_CTRL {
598    #[doc = "READ_FUSE"]
599    pub mod READ_FUSE {
600        pub const offset: u32 = 0;
601        pub const mask: u32 = 0x01 << offset;
602        pub mod R {}
603        pub mod W {}
604        pub mod RW {}
605    }
606    #[doc = "RSVD0"]
607    pub mod RSVD0 {
608        pub const offset: u32 = 1;
609        pub const mask: u32 = 0x7fff_ffff << offset;
610        pub mod R {}
611        pub mod W {}
612        pub mod RW {}
613    }
614}
615#[doc = "OTP Controller Read Data Register"]
616pub mod READ_FUSE_DATA {
617    #[doc = "DATA"]
618    pub mod DATA {
619        pub const offset: u32 = 0;
620        pub const mask: u32 = 0xffff_ffff << offset;
621        pub mod R {}
622        pub mod W {}
623        pub mod RW {}
624    }
625}
626#[doc = "Sticky bit Register"]
627pub mod SW_STICKY {
628    #[doc = "BLOCK_DTCP_KEY"]
629    pub mod BLOCK_DTCP_KEY {
630        pub const offset: u32 = 0;
631        pub const mask: u32 = 0x01 << offset;
632        pub mod R {}
633        pub mod W {}
634        pub mod RW {}
635    }
636    #[doc = "SRK_REVOKE_LOCK"]
637    pub mod SRK_REVOKE_LOCK {
638        pub const offset: u32 = 1;
639        pub const mask: u32 = 0x01 << offset;
640        pub mod R {}
641        pub mod W {}
642        pub mod RW {}
643    }
644    #[doc = "FIELD_RETURN_LOCK"]
645    pub mod FIELD_RETURN_LOCK {
646        pub const offset: u32 = 2;
647        pub const mask: u32 = 0x01 << offset;
648        pub mod R {}
649        pub mod W {}
650        pub mod RW {}
651    }
652    #[doc = "BLOCK_ROM_PART"]
653    pub mod BLOCK_ROM_PART {
654        pub const offset: u32 = 3;
655        pub const mask: u32 = 0x01 << offset;
656        pub mod R {}
657        pub mod W {}
658        pub mod RW {}
659    }
660    #[doc = "JTAG_BLOCK_RELEASE"]
661    pub mod JTAG_BLOCK_RELEASE {
662        pub const offset: u32 = 4;
663        pub const mask: u32 = 0x01 << offset;
664        pub mod R {}
665        pub mod W {}
666        pub mod RW {}
667    }
668    #[doc = "RSVD0"]
669    pub mod RSVD0 {
670        pub const offset: u32 = 5;
671        pub const mask: u32 = 0x07ff_ffff << offset;
672        pub mod R {}
673        pub mod W {}
674        pub mod RW {}
675    }
676}
677#[doc = "Software Controllable Signals Register"]
678pub mod SCS {
679    #[doc = "HAB_JDE"]
680    pub mod HAB_JDE {
681        pub const offset: u32 = 0;
682        pub const mask: u32 = 0x01 << offset;
683        pub mod R {}
684        pub mod W {}
685        pub mod RW {}
686    }
687    #[doc = "SPARE"]
688    pub mod SPARE {
689        pub const offset: u32 = 1;
690        pub const mask: u32 = 0x3fff_ffff << offset;
691        pub mod R {}
692        pub mod W {}
693        pub mod RW {}
694    }
695    #[doc = "LOCK"]
696    pub mod LOCK {
697        pub const offset: u32 = 31;
698        pub const mask: u32 = 0x01 << offset;
699        pub mod R {}
700        pub mod W {}
701        pub mod RW {}
702    }
703}
704#[doc = "Software Controllable Signals Register"]
705pub mod SCS_SET {
706    #[doc = "HAB_JDE"]
707    pub mod HAB_JDE {
708        pub const offset: u32 = 0;
709        pub const mask: u32 = 0x01 << offset;
710        pub mod R {}
711        pub mod W {}
712        pub mod RW {}
713    }
714    #[doc = "SPARE"]
715    pub mod SPARE {
716        pub const offset: u32 = 1;
717        pub const mask: u32 = 0x3fff_ffff << offset;
718        pub mod R {}
719        pub mod W {}
720        pub mod RW {}
721    }
722    #[doc = "LOCK"]
723    pub mod LOCK {
724        pub const offset: u32 = 31;
725        pub const mask: u32 = 0x01 << offset;
726        pub mod R {}
727        pub mod W {}
728        pub mod RW {}
729    }
730}
731#[doc = "Software Controllable Signals Register"]
732pub mod SCS_CLR {
733    #[doc = "HAB_JDE"]
734    pub mod HAB_JDE {
735        pub const offset: u32 = 0;
736        pub const mask: u32 = 0x01 << offset;
737        pub mod R {}
738        pub mod W {}
739        pub mod RW {}
740    }
741    #[doc = "SPARE"]
742    pub mod SPARE {
743        pub const offset: u32 = 1;
744        pub const mask: u32 = 0x3fff_ffff << offset;
745        pub mod R {}
746        pub mod W {}
747        pub mod RW {}
748    }
749    #[doc = "LOCK"]
750    pub mod LOCK {
751        pub const offset: u32 = 31;
752        pub const mask: u32 = 0x01 << offset;
753        pub mod R {}
754        pub mod W {}
755        pub mod RW {}
756    }
757}
758#[doc = "Software Controllable Signals Register"]
759pub mod SCS_TOG {
760    #[doc = "HAB_JDE"]
761    pub mod HAB_JDE {
762        pub const offset: u32 = 0;
763        pub const mask: u32 = 0x01 << offset;
764        pub mod R {}
765        pub mod W {}
766        pub mod RW {}
767    }
768    #[doc = "SPARE"]
769    pub mod SPARE {
770        pub const offset: u32 = 1;
771        pub const mask: u32 = 0x3fff_ffff << offset;
772        pub mod R {}
773        pub mod W {}
774        pub mod RW {}
775    }
776    #[doc = "LOCK"]
777    pub mod LOCK {
778        pub const offset: u32 = 31;
779        pub const mask: u32 = 0x01 << offset;
780        pub mod R {}
781        pub mod W {}
782        pub mod RW {}
783    }
784}
785#[doc = "OTP Controller CRC test address"]
786pub mod CRC_ADDR {
787    #[doc = "DATA_START_ADDR"]
788    pub mod DATA_START_ADDR {
789        pub const offset: u32 = 0;
790        pub const mask: u32 = 0xff << offset;
791        pub mod R {}
792        pub mod W {}
793        pub mod RW {}
794    }
795    #[doc = "DATA_END_ADDR"]
796    pub mod DATA_END_ADDR {
797        pub const offset: u32 = 8;
798        pub const mask: u32 = 0xff << offset;
799        pub mod R {}
800        pub mod W {}
801        pub mod RW {}
802    }
803    #[doc = "CRC_ADDR"]
804    pub mod CRC_ADDR {
805        pub const offset: u32 = 16;
806        pub const mask: u32 = 0xff << offset;
807        pub mod R {}
808        pub mod W {}
809        pub mod RW {}
810    }
811    #[doc = "OTPMK_CRC"]
812    pub mod OTPMK_CRC {
813        pub const offset: u32 = 24;
814        pub const mask: u32 = 0x01 << offset;
815        pub mod R {}
816        pub mod W {}
817        pub mod RW {}
818    }
819    #[doc = "RSVD0"]
820    pub mod RSVD0 {
821        pub const offset: u32 = 25;
822        pub const mask: u32 = 0x7f << offset;
823        pub mod R {}
824        pub mod W {}
825        pub mod RW {}
826    }
827}
828#[doc = "OTP Controller CRC Value Register"]
829pub mod CRC_VALUE {
830    #[doc = "DATA"]
831    pub mod DATA {
832        pub const offset: u32 = 0;
833        pub const mask: u32 = 0xffff_ffff << offset;
834        pub mod R {}
835        pub mod W {}
836        pub mod RW {}
837    }
838}
839#[doc = "OTP Controller Version Register"]
840pub mod VERSION {
841    #[doc = "STEP"]
842    pub mod STEP {
843        pub const offset: u32 = 0;
844        pub const mask: u32 = 0xffff << offset;
845        pub mod R {}
846        pub mod W {}
847        pub mod RW {}
848    }
849    #[doc = "MINOR"]
850    pub mod MINOR {
851        pub const offset: u32 = 16;
852        pub const mask: u32 = 0xff << offset;
853        pub mod R {}
854        pub mod W {}
855        pub mod RW {}
856    }
857    #[doc = "MAJOR"]
858    pub mod MAJOR {
859        pub const offset: u32 = 24;
860        pub const mask: u32 = 0xff << offset;
861        pub mod R {}
862        pub mod W {}
863        pub mod RW {}
864    }
865}
866#[doc = "OTP Controller Timing Register"]
867pub mod TIMING2 {
868    #[doc = "RELAX_PROG"]
869    pub mod RELAX_PROG {
870        pub const offset: u32 = 0;
871        pub const mask: u32 = 0x0fff << offset;
872        pub mod R {}
873        pub mod W {}
874        pub mod RW {}
875    }
876    #[doc = "RSRVD0"]
877    pub mod RSRVD0 {
878        pub const offset: u32 = 12;
879        pub const mask: u32 = 0x0f << offset;
880        pub mod R {}
881        pub mod W {}
882        pub mod RW {}
883    }
884    #[doc = "RELAX_READ"]
885    pub mod RELAX_READ {
886        pub const offset: u32 = 16;
887        pub const mask: u32 = 0x3f << offset;
888        pub mod R {}
889        pub mod W {}
890        pub mod RW {}
891    }
892    #[doc = "RSRVD0"]
893    pub mod RSRVD1 {
894        pub const offset: u32 = 22;
895        pub const mask: u32 = 0x03ff << offset;
896        pub mod R {}
897        pub mod W {}
898        pub mod RW {}
899    }
900}
901#[doc = "Value of OTP Bank0 Word0 (Lock controls)"]
902pub mod LOCK {
903    #[doc = "TESTER"]
904    pub mod TESTER {
905        pub const offset: u32 = 0;
906        pub const mask: u32 = 0x03 << offset;
907        pub mod R {}
908        pub mod W {}
909        pub mod RW {}
910    }
911    #[doc = "BOOT_CFG"]
912    pub mod BOOT_CFG {
913        pub const offset: u32 = 2;
914        pub const mask: u32 = 0x03 << offset;
915        pub mod R {}
916        pub mod W {}
917        pub mod RW {}
918    }
919    #[doc = "MEM_TRIM"]
920    pub mod MEM_TRIM {
921        pub const offset: u32 = 4;
922        pub const mask: u32 = 0x03 << offset;
923        pub mod R {}
924        pub mod W {}
925        pub mod RW {}
926    }
927    #[doc = "SJC_RESP"]
928    pub mod SJC_RESP {
929        pub const offset: u32 = 6;
930        pub const mask: u32 = 0x01 << offset;
931        pub mod R {}
932        pub mod W {}
933        pub mod RW {}
934    }
935    #[doc = "GP4_RLOCK"]
936    pub mod GP4_RLOCK {
937        pub const offset: u32 = 7;
938        pub const mask: u32 = 0x01 << offset;
939        pub mod R {}
940        pub mod W {}
941        pub mod RW {}
942    }
943    #[doc = "MAC_ADDR"]
944    pub mod MAC_ADDR {
945        pub const offset: u32 = 8;
946        pub const mask: u32 = 0x03 << offset;
947        pub mod R {}
948        pub mod W {}
949        pub mod RW {}
950    }
951    #[doc = "GP1"]
952    pub mod GP1 {
953        pub const offset: u32 = 10;
954        pub const mask: u32 = 0x03 << offset;
955        pub mod R {}
956        pub mod W {}
957        pub mod RW {}
958    }
959    #[doc = "GP2"]
960    pub mod GP2 {
961        pub const offset: u32 = 12;
962        pub const mask: u32 = 0x03 << offset;
963        pub mod R {}
964        pub mod W {}
965        pub mod RW {}
966    }
967    #[doc = "ROM_PATCH"]
968    pub mod ROM_PATCH {
969        pub const offset: u32 = 15;
970        pub const mask: u32 = 0x01 << offset;
971        pub mod R {}
972        pub mod W {}
973        pub mod RW {}
974    }
975    #[doc = "SW_GP1"]
976    pub mod SW_GP1 {
977        pub const offset: u32 = 16;
978        pub const mask: u32 = 0x01 << offset;
979        pub mod R {}
980        pub mod W {}
981        pub mod RW {}
982    }
983    #[doc = "OTPMK"]
984    pub mod OTPMK {
985        pub const offset: u32 = 17;
986        pub const mask: u32 = 0x01 << offset;
987        pub mod R {}
988        pub mod W {}
989        pub mod RW {}
990    }
991    #[doc = "ANALOG"]
992    pub mod ANALOG {
993        pub const offset: u32 = 18;
994        pub const mask: u32 = 0x03 << offset;
995        pub mod R {}
996        pub mod W {}
997        pub mod RW {}
998    }
999    #[doc = "OTPMK_CRC"]
1000    pub mod OTPMK_CRC {
1001        pub const offset: u32 = 20;
1002        pub const mask: u32 = 0x01 << offset;
1003        pub mod R {}
1004        pub mod W {}
1005        pub mod RW {}
1006    }
1007    #[doc = "SW_GP2_LOCK"]
1008    pub mod SW_GP2_LOCK {
1009        pub const offset: u32 = 21;
1010        pub const mask: u32 = 0x01 << offset;
1011        pub mod R {}
1012        pub mod W {}
1013        pub mod RW {}
1014    }
1015    #[doc = "MISC_CONF"]
1016    pub mod MISC_CONF {
1017        pub const offset: u32 = 22;
1018        pub const mask: u32 = 0x01 << offset;
1019        pub mod R {}
1020        pub mod W {}
1021        pub mod RW {}
1022    }
1023    #[doc = "SW_GP2_RLOCK"]
1024    pub mod SW_GP2_RLOCK {
1025        pub const offset: u32 = 23;
1026        pub const mask: u32 = 0x01 << offset;
1027        pub mod R {}
1028        pub mod W {}
1029        pub mod RW {}
1030    }
1031    #[doc = "GP4"]
1032    pub mod GP4 {
1033        pub const offset: u32 = 24;
1034        pub const mask: u32 = 0x03 << offset;
1035        pub mod R {}
1036        pub mod W {}
1037        pub mod RW {}
1038    }
1039    #[doc = "GP3"]
1040    pub mod GP3 {
1041        pub const offset: u32 = 26;
1042        pub const mask: u32 = 0x03 << offset;
1043        pub mod R {}
1044        pub mod W {}
1045        pub mod RW {}
1046    }
1047    #[doc = "FIELD_RETURN"]
1048    pub mod FIELD_RETURN {
1049        pub const offset: u32 = 28;
1050        pub const mask: u32 = 0x0f << offset;
1051        pub mod R {}
1052        pub mod W {}
1053        pub mod RW {}
1054    }
1055}
1056#[doc = "Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.)"]
1057pub mod CFG0 {
1058    #[doc = "BITS"]
1059    pub mod BITS {
1060        pub const offset: u32 = 0;
1061        pub const mask: u32 = 0xffff_ffff << offset;
1062        pub mod R {}
1063        pub mod W {}
1064        pub mod RW {}
1065    }
1066}
1067#[doc = "Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.)"]
1068pub mod CFG1 {
1069    #[doc = "BITS"]
1070    pub mod BITS {
1071        pub const offset: u32 = 0;
1072        pub const mask: u32 = 0xffff_ffff << offset;
1073        pub mod R {}
1074        pub mod W {}
1075        pub mod RW {}
1076    }
1077}
1078#[doc = "Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.)"]
1079pub mod CFG2 {
1080    #[doc = "BITS"]
1081    pub mod BITS {
1082        pub const offset: u32 = 0;
1083        pub const mask: u32 = 0xffff_ffff << offset;
1084        pub mod R {}
1085        pub mod W {}
1086        pub mod RW {}
1087    }
1088}
1089#[doc = "Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.)"]
1090pub mod CFG3 {
1091    #[doc = "BITS"]
1092    pub mod BITS {
1093        pub const offset: u32 = 0;
1094        pub const mask: u32 = 0xffff_ffff << offset;
1095        pub mod R {}
1096        pub mod W {}
1097        pub mod RW {}
1098    }
1099}
1100#[doc = "Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.)"]
1101pub mod CFG4 {
1102    #[doc = "BITS"]
1103    pub mod BITS {
1104        pub const offset: u32 = 0;
1105        pub const mask: u32 = 0xffff_ffff << offset;
1106        pub mod R {}
1107        pub mod W {}
1108        pub mod RW {}
1109    }
1110}
1111#[doc = "Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.)"]
1112pub mod CFG5 {
1113    #[doc = "BITS"]
1114    pub mod BITS {
1115        pub const offset: u32 = 0;
1116        pub const mask: u32 = 0xffff_ffff << offset;
1117        pub mod R {}
1118        pub mod W {}
1119        pub mod RW {}
1120    }
1121}
1122#[doc = "Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.)"]
1123pub mod CFG6 {
1124    #[doc = "BITS"]
1125    pub mod BITS {
1126        pub const offset: u32 = 0;
1127        pub const mask: u32 = 0xffff_ffff << offset;
1128        pub mod R {}
1129        pub mod W {}
1130        pub mod RW {}
1131    }
1132}
1133#[doc = "Value of OTP Bank1 Word0 (Memory Related Info.)"]
1134pub mod MEM0 {
1135    #[doc = "BITS"]
1136    pub mod BITS {
1137        pub const offset: u32 = 0;
1138        pub const mask: u32 = 0xffff_ffff << offset;
1139        pub mod R {}
1140        pub mod W {}
1141        pub mod RW {}
1142    }
1143}
1144#[doc = "Value of OTP Bank1 Word1 (Memory Related Info.)"]
1145pub mod MEM1 {
1146    #[doc = "BITS"]
1147    pub mod BITS {
1148        pub const offset: u32 = 0;
1149        pub const mask: u32 = 0xffff_ffff << offset;
1150        pub mod R {}
1151        pub mod W {}
1152        pub mod RW {}
1153    }
1154}
1155#[doc = "Value of OTP Bank1 Word2 (Memory Related Info.)"]
1156pub mod MEM2 {
1157    #[doc = "BITS"]
1158    pub mod BITS {
1159        pub const offset: u32 = 0;
1160        pub const mask: u32 = 0xffff_ffff << offset;
1161        pub mod R {}
1162        pub mod W {}
1163        pub mod RW {}
1164    }
1165}
1166#[doc = "Value of OTP Bank1 Word3 (Memory Related Info.)"]
1167pub mod MEM3 {
1168    #[doc = "BITS"]
1169    pub mod BITS {
1170        pub const offset: u32 = 0;
1171        pub const mask: u32 = 0xffff_ffff << offset;
1172        pub mod R {}
1173        pub mod W {}
1174        pub mod RW {}
1175    }
1176}
1177#[doc = "Value of OTP Bank1 Word4 (Memory Related Info.)"]
1178pub mod MEM4 {
1179    #[doc = "BITS"]
1180    pub mod BITS {
1181        pub const offset: u32 = 0;
1182        pub const mask: u32 = 0xffff_ffff << offset;
1183        pub mod R {}
1184        pub mod W {}
1185        pub mod RW {}
1186    }
1187}
1188#[doc = "Value of OTP Bank1 Word5 (Memory Related Info.)"]
1189pub mod ANA0 {
1190    #[doc = "BITS"]
1191    pub mod BITS {
1192        pub const offset: u32 = 0;
1193        pub const mask: u32 = 0xffff_ffff << offset;
1194        pub mod R {}
1195        pub mod W {}
1196        pub mod RW {}
1197    }
1198}
1199#[doc = "Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.)"]
1200pub mod ANA1 {
1201    #[doc = "BITS"]
1202    pub mod BITS {
1203        pub const offset: u32 = 0;
1204        pub const mask: u32 = 0xffff_ffff << offset;
1205        pub mod R {}
1206        pub mod W {}
1207        pub mod RW {}
1208    }
1209}
1210#[doc = "Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.)"]
1211pub mod ANA2 {
1212    #[doc = "BITS"]
1213    pub mod BITS {
1214        pub const offset: u32 = 0;
1215        pub const mask: u32 = 0xffff_ffff << offset;
1216        pub mod R {}
1217        pub mod W {}
1218        pub mod RW {}
1219    }
1220}
1221#[doc = "Value of OTP Bank2 Word0 (OTPMK Key)"]
1222pub mod OTPMK0 {
1223    #[doc = "BITS"]
1224    pub mod BITS {
1225        pub const offset: u32 = 0;
1226        pub const mask: u32 = 0xffff_ffff << offset;
1227        pub mod R {}
1228        pub mod W {}
1229        pub mod RW {}
1230    }
1231}
1232#[doc = "Value of OTP Bank2 Word1 (OTPMK Key)"]
1233pub mod OTPMK1 {
1234    #[doc = "BITS"]
1235    pub mod BITS {
1236        pub const offset: u32 = 0;
1237        pub const mask: u32 = 0xffff_ffff << offset;
1238        pub mod R {}
1239        pub mod W {}
1240        pub mod RW {}
1241    }
1242}
1243#[doc = "Value of OTP Bank2 Word2 (OTPMK Key)"]
1244pub mod OTPMK2 {
1245    #[doc = "BITS"]
1246    pub mod BITS {
1247        pub const offset: u32 = 0;
1248        pub const mask: u32 = 0xffff_ffff << offset;
1249        pub mod R {}
1250        pub mod W {}
1251        pub mod RW {}
1252    }
1253}
1254#[doc = "Value of OTP Bank2 Word3 (OTPMK Key)"]
1255pub mod OTPMK3 {
1256    #[doc = "BITS"]
1257    pub mod BITS {
1258        pub const offset: u32 = 0;
1259        pub const mask: u32 = 0xffff_ffff << offset;
1260        pub mod R {}
1261        pub mod W {}
1262        pub mod RW {}
1263    }
1264}
1265#[doc = "Value of OTP Bank2 Word4 (OTPMK Key)"]
1266pub mod OTPMK4 {
1267    #[doc = "BITS"]
1268    pub mod BITS {
1269        pub const offset: u32 = 0;
1270        pub const mask: u32 = 0xffff_ffff << offset;
1271        pub mod R {}
1272        pub mod W {}
1273        pub mod RW {}
1274    }
1275}
1276#[doc = "Value of OTP Bank2 Word5 (OTPMK Key)"]
1277pub mod OTPMK5 {
1278    #[doc = "BITS"]
1279    pub mod BITS {
1280        pub const offset: u32 = 0;
1281        pub const mask: u32 = 0xffff_ffff << offset;
1282        pub mod R {}
1283        pub mod W {}
1284        pub mod RW {}
1285    }
1286}
1287#[doc = "Value of OTP Bank2 Word6 (OTPMK Key)"]
1288pub mod OTPMK6 {
1289    #[doc = "BITS"]
1290    pub mod BITS {
1291        pub const offset: u32 = 0;
1292        pub const mask: u32 = 0xffff_ffff << offset;
1293        pub mod R {}
1294        pub mod W {}
1295        pub mod RW {}
1296    }
1297}
1298#[doc = "Value of OTP Bank2 Word7 (OTPMK Key)"]
1299pub mod OTPMK7 {
1300    #[doc = "BITS"]
1301    pub mod BITS {
1302        pub const offset: u32 = 0;
1303        pub const mask: u32 = 0xffff_ffff << offset;
1304        pub mod R {}
1305        pub mod W {}
1306        pub mod RW {}
1307    }
1308}
1309#[doc = "Shadow Register for OTP Bank3 Word0 (SRK Hash)"]
1310pub mod SRK0 {
1311    #[doc = "BITS"]
1312    pub mod BITS {
1313        pub const offset: u32 = 0;
1314        pub const mask: u32 = 0xffff_ffff << offset;
1315        pub mod R {}
1316        pub mod W {}
1317        pub mod RW {}
1318    }
1319}
1320#[doc = "Shadow Register for OTP Bank3 Word1 (SRK Hash)"]
1321pub mod SRK1 {
1322    #[doc = "BITS"]
1323    pub mod BITS {
1324        pub const offset: u32 = 0;
1325        pub const mask: u32 = 0xffff_ffff << offset;
1326        pub mod R {}
1327        pub mod W {}
1328        pub mod RW {}
1329    }
1330}
1331#[doc = "Shadow Register for OTP Bank3 Word2 (SRK Hash)"]
1332pub mod SRK2 {
1333    #[doc = "BITS"]
1334    pub mod BITS {
1335        pub const offset: u32 = 0;
1336        pub const mask: u32 = 0xffff_ffff << offset;
1337        pub mod R {}
1338        pub mod W {}
1339        pub mod RW {}
1340    }
1341}
1342#[doc = "Shadow Register for OTP Bank3 Word3 (SRK Hash)"]
1343pub mod SRK3 {
1344    #[doc = "BITS"]
1345    pub mod BITS {
1346        pub const offset: u32 = 0;
1347        pub const mask: u32 = 0xffff_ffff << offset;
1348        pub mod R {}
1349        pub mod W {}
1350        pub mod RW {}
1351    }
1352}
1353#[doc = "Shadow Register for OTP Bank3 Word4 (SRK Hash)"]
1354pub mod SRK4 {
1355    #[doc = "BITS"]
1356    pub mod BITS {
1357        pub const offset: u32 = 0;
1358        pub const mask: u32 = 0xffff_ffff << offset;
1359        pub mod R {}
1360        pub mod W {}
1361        pub mod RW {}
1362    }
1363}
1364#[doc = "Shadow Register for OTP Bank3 Word5 (SRK Hash)"]
1365pub mod SRK5 {
1366    #[doc = "BITS"]
1367    pub mod BITS {
1368        pub const offset: u32 = 0;
1369        pub const mask: u32 = 0xffff_ffff << offset;
1370        pub mod R {}
1371        pub mod W {}
1372        pub mod RW {}
1373    }
1374}
1375#[doc = "Shadow Register for OTP Bank3 Word6 (SRK Hash)"]
1376pub mod SRK6 {
1377    #[doc = "BITS"]
1378    pub mod BITS {
1379        pub const offset: u32 = 0;
1380        pub const mask: u32 = 0xffff_ffff << offset;
1381        pub mod R {}
1382        pub mod W {}
1383        pub mod RW {}
1384    }
1385}
1386#[doc = "Shadow Register for OTP Bank3 Word7 (SRK Hash)"]
1387pub mod SRK7 {
1388    #[doc = "BITS"]
1389    pub mod BITS {
1390        pub const offset: u32 = 0;
1391        pub const mask: u32 = 0xffff_ffff << offset;
1392        pub mod R {}
1393        pub mod W {}
1394        pub mod RW {}
1395    }
1396}
1397#[doc = "Value of OTP Bank4 Word0 (Secure JTAG Response Field)"]
1398pub mod SJC_RESP0 {
1399    #[doc = "BITS"]
1400    pub mod BITS {
1401        pub const offset: u32 = 0;
1402        pub const mask: u32 = 0xffff_ffff << offset;
1403        pub mod R {}
1404        pub mod W {}
1405        pub mod RW {}
1406    }
1407}
1408#[doc = "Value of OTP Bank4 Word1 (Secure JTAG Response Field)"]
1409pub mod SJC_RESP1 {
1410    #[doc = "BITS"]
1411    pub mod BITS {
1412        pub const offset: u32 = 0;
1413        pub const mask: u32 = 0xffff_ffff << offset;
1414        pub mod R {}
1415        pub mod W {}
1416        pub mod RW {}
1417    }
1418}
1419#[doc = "Value of OTP Bank4 Word2 (MAC Address)"]
1420pub mod MAC0 {
1421    #[doc = "BITS"]
1422    pub mod BITS {
1423        pub const offset: u32 = 0;
1424        pub const mask: u32 = 0xffff_ffff << offset;
1425        pub mod R {}
1426        pub mod W {}
1427        pub mod RW {}
1428    }
1429}
1430#[doc = "Value of OTP Bank4 Word3 (MAC Address)"]
1431pub mod MAC1 {
1432    #[doc = "BITS"]
1433    pub mod BITS {
1434        pub const offset: u32 = 0;
1435        pub const mask: u32 = 0xffff_ffff << offset;
1436        pub mod R {}
1437        pub mod W {}
1438        pub mod RW {}
1439    }
1440}
1441#[doc = "Value of OTP Bank4 Word4 (MAC2 Address)"]
1442pub mod MAC2 {
1443    #[doc = "BITS"]
1444    pub mod BITS {
1445        pub const offset: u32 = 0;
1446        pub const mask: u32 = 0xffff_ffff << offset;
1447        pub mod R {}
1448        pub mod W {}
1449        pub mod RW {}
1450    }
1451}
1452#[doc = "Value of OTP Bank4 Word5 (CRC Key)"]
1453pub mod OTPMK_CRC32 {
1454    #[doc = "BITS"]
1455    pub mod BITS {
1456        pub const offset: u32 = 0;
1457        pub const mask: u32 = 0xffff_ffff << offset;
1458        pub mod R {}
1459        pub mod W {}
1460        pub mod RW {}
1461    }
1462}
1463#[doc = "Value of OTP Bank4 Word6 (General Purpose Customer Defined Info)"]
1464pub mod GP1 {
1465    #[doc = "BITS"]
1466    pub mod BITS {
1467        pub const offset: u32 = 0;
1468        pub const mask: u32 = 0xffff_ffff << offset;
1469        pub mod R {}
1470        pub mod W {}
1471        pub mod RW {}
1472    }
1473}
1474#[doc = "Value of OTP Bank4 Word7 (General Purpose Customer Defined Info)"]
1475pub mod GP2 {
1476    #[doc = "BITS"]
1477    pub mod BITS {
1478        pub const offset: u32 = 0;
1479        pub const mask: u32 = 0xffff_ffff << offset;
1480        pub mod R {}
1481        pub mod W {}
1482        pub mod RW {}
1483    }
1484}
1485#[doc = "Value of OTP Bank5 Word0 (SW GP1)"]
1486pub mod SW_GP1 {
1487    #[doc = "BITS"]
1488    pub mod BITS {
1489        pub const offset: u32 = 0;
1490        pub const mask: u32 = 0xffff_ffff << offset;
1491        pub mod R {}
1492        pub mod W {}
1493        pub mod RW {}
1494    }
1495}
1496#[doc = "Value of OTP Bank5 Word1 (SW GP2)"]
1497pub mod SW_GP20 {
1498    #[doc = "BITS"]
1499    pub mod BITS {
1500        pub const offset: u32 = 0;
1501        pub const mask: u32 = 0xffff_ffff << offset;
1502        pub mod R {}
1503        pub mod W {}
1504        pub mod RW {}
1505    }
1506}
1507#[doc = "Value of OTP Bank5 Word2 (SW GP2)"]
1508pub mod SW_GP21 {
1509    #[doc = "BITS"]
1510    pub mod BITS {
1511        pub const offset: u32 = 0;
1512        pub const mask: u32 = 0xffff_ffff << offset;
1513        pub mod R {}
1514        pub mod W {}
1515        pub mod RW {}
1516    }
1517}
1518#[doc = "Value of OTP Bank5 Word3 (SW GP2)"]
1519pub mod SW_GP22 {
1520    #[doc = "BITS"]
1521    pub mod BITS {
1522        pub const offset: u32 = 0;
1523        pub const mask: u32 = 0xffff_ffff << offset;
1524        pub mod R {}
1525        pub mod W {}
1526        pub mod RW {}
1527    }
1528}
1529#[doc = "Value of OTP Bank5 Word4 (SW GP2)"]
1530pub mod SW_GP23 {
1531    #[doc = "BITS"]
1532    pub mod BITS {
1533        pub const offset: u32 = 0;
1534        pub const mask: u32 = 0xffff_ffff << offset;
1535        pub mod R {}
1536        pub mod W {}
1537        pub mod RW {}
1538    }
1539}
1540#[doc = "Value of OTP Bank5 Word5 (Misc Conf)"]
1541pub mod MISC_CONF0 {
1542    #[doc = "BITS"]
1543    pub mod BITS {
1544        pub const offset: u32 = 0;
1545        pub const mask: u32 = 0xffff_ffff << offset;
1546        pub mod R {}
1547        pub mod W {}
1548        pub mod RW {}
1549    }
1550}
1551#[doc = "Value of OTP Bank5 Word6 (Misc Conf)"]
1552pub mod MISC_CONF1 {
1553    #[doc = "BITS"]
1554    pub mod BITS {
1555        pub const offset: u32 = 0;
1556        pub const mask: u32 = 0xffff_ffff << offset;
1557        pub mod R {}
1558        pub mod W {}
1559        pub mod RW {}
1560    }
1561}
1562#[doc = "Value of OTP Bank5 Word7 (SRK Revoke)"]
1563pub mod SRK_REVOKE {
1564    #[doc = "BITS"]
1565    pub mod BITS {
1566        pub const offset: u32 = 0;
1567        pub const mask: u32 = 0xffff_ffff << offset;
1568        pub mod R {}
1569        pub mod W {}
1570        pub mod RW {}
1571    }
1572}
1573#[doc = "Value of OTP Bank6 Word0 (ROM Patch)"]
1574pub mod ROM_PATCH0 {
1575    #[doc = "BITS"]
1576    pub mod BITS {
1577        pub const offset: u32 = 0;
1578        pub const mask: u32 = 0xffff_ffff << offset;
1579        pub mod R {}
1580        pub mod W {}
1581        pub mod RW {}
1582    }
1583}
1584#[doc = "Value of OTP Bank6 Word1 (ROM Patch)"]
1585pub mod ROM_PATCH1 {
1586    #[doc = "BITS"]
1587    pub mod BITS {
1588        pub const offset: u32 = 0;
1589        pub const mask: u32 = 0xffff_ffff << offset;
1590        pub mod R {}
1591        pub mod W {}
1592        pub mod RW {}
1593    }
1594}
1595#[doc = "Value of OTP Bank6 Word2 (ROM Patch)"]
1596pub mod ROM_PATCH2 {
1597    #[doc = "BITS"]
1598    pub mod BITS {
1599        pub const offset: u32 = 0;
1600        pub const mask: u32 = 0xffff_ffff << offset;
1601        pub mod R {}
1602        pub mod W {}
1603        pub mod RW {}
1604    }
1605}
1606#[doc = "Value of OTP Bank6 Word3 (ROM Patch)"]
1607pub mod ROM_PATCH3 {
1608    #[doc = "BITS"]
1609    pub mod BITS {
1610        pub const offset: u32 = 0;
1611        pub const mask: u32 = 0xffff_ffff << offset;
1612        pub mod R {}
1613        pub mod W {}
1614        pub mod RW {}
1615    }
1616}
1617#[doc = "Value of OTP Bank6 Word4 (ROM Patch)"]
1618pub mod ROM_PATCH4 {
1619    #[doc = "BITS"]
1620    pub mod BITS {
1621        pub const offset: u32 = 0;
1622        pub const mask: u32 = 0xffff_ffff << offset;
1623        pub mod R {}
1624        pub mod W {}
1625        pub mod RW {}
1626    }
1627}
1628#[doc = "Value of OTP Bank6 Word5 (ROM Patch)"]
1629pub mod ROM_PATCH5 {
1630    #[doc = "BITS"]
1631    pub mod BITS {
1632        pub const offset: u32 = 0;
1633        pub const mask: u32 = 0xffff_ffff << offset;
1634        pub mod R {}
1635        pub mod W {}
1636        pub mod RW {}
1637    }
1638}
1639#[doc = "Value of OTP Bank6 Word6 (ROM Patch)"]
1640pub mod ROM_PATCH6 {
1641    #[doc = "BITS"]
1642    pub mod BITS {
1643        pub const offset: u32 = 0;
1644        pub const mask: u32 = 0xffff_ffff << offset;
1645        pub mod R {}
1646        pub mod W {}
1647        pub mod RW {}
1648    }
1649}
1650#[doc = "Value of OTP Bank6 Word7 (ROM Patch)"]
1651pub mod ROM_PATCH7 {
1652    #[doc = "BITS"]
1653    pub mod BITS {
1654        pub const offset: u32 = 0;
1655        pub const mask: u32 = 0xffff_ffff << offset;
1656        pub mod R {}
1657        pub mod W {}
1658        pub mod RW {}
1659    }
1660}
1661#[doc = "Value of OTP Bank7 Word0 (GP3)"]
1662pub mod GP30 {
1663    #[doc = "BITS"]
1664    pub mod BITS {
1665        pub const offset: u32 = 0;
1666        pub const mask: u32 = 0xffff_ffff << offset;
1667        pub mod R {}
1668        pub mod W {}
1669        pub mod RW {}
1670    }
1671}
1672#[doc = "Value of OTP Bank7 Word1 (GP3)"]
1673pub mod GP31 {
1674    #[doc = "BITS"]
1675    pub mod BITS {
1676        pub const offset: u32 = 0;
1677        pub const mask: u32 = 0xffff_ffff << offset;
1678        pub mod R {}
1679        pub mod W {}
1680        pub mod RW {}
1681    }
1682}
1683#[doc = "Value of OTP Bank7 Word2 (GP3)"]
1684pub mod GP32 {
1685    #[doc = "BITS"]
1686    pub mod BITS {
1687        pub const offset: u32 = 0;
1688        pub const mask: u32 = 0xffff_ffff << offset;
1689        pub mod R {}
1690        pub mod W {}
1691        pub mod RW {}
1692    }
1693}
1694#[doc = "Value of OTP Bank7 Word3 (GP3)"]
1695pub mod GP33 {
1696    #[doc = "BITS"]
1697    pub mod BITS {
1698        pub const offset: u32 = 0;
1699        pub const mask: u32 = 0xffff_ffff << offset;
1700        pub mod R {}
1701        pub mod W {}
1702        pub mod RW {}
1703    }
1704}
1705#[doc = "Value of OTP Bank7 Word4 (GP4)"]
1706pub mod GP40 {
1707    #[doc = "BITS"]
1708    pub mod BITS {
1709        pub const offset: u32 = 0;
1710        pub const mask: u32 = 0xffff_ffff << offset;
1711        pub mod R {}
1712        pub mod W {}
1713        pub mod RW {}
1714    }
1715}
1716#[doc = "Value of OTP Bank7 Word5 (GP4)"]
1717pub mod GP41 {
1718    #[doc = "BITS"]
1719    pub mod BITS {
1720        pub const offset: u32 = 0;
1721        pub const mask: u32 = 0xffff_ffff << offset;
1722        pub mod R {}
1723        pub mod W {}
1724        pub mod RW {}
1725    }
1726}
1727#[doc = "Value of OTP Bank7 Word6 (GP4)"]
1728pub mod GP42 {
1729    #[doc = "BITS"]
1730    pub mod BITS {
1731        pub const offset: u32 = 0;
1732        pub const mask: u32 = 0xffff_ffff << offset;
1733        pub mod R {}
1734        pub mod W {}
1735        pub mod RW {}
1736    }
1737}
1738#[doc = "Value of OTP Bank7 Word7 (GP4)"]
1739pub mod GP43 {
1740    #[doc = "BITS"]
1741    pub mod BITS {
1742        pub const offset: u32 = 0;
1743        pub const mask: u32 = 0xffff_ffff << offset;
1744        pub mod R {}
1745        pub mod W {}
1746        pub mod RW {}
1747    }
1748}
imxrt_ral/blocks/imxrt1061/ocotp.rs

imxrt_ral/blocks/imxrt1061/
ocotp.rs
