imxrt_ral/blocks/imxrt1061/
semc.rs

1#[doc = "SEMC"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "Module Control Register"]
5    pub MCR: crate::RWRegister<u32>,
6    #[doc = "IO Mux Control Register"]
7    pub IOCR: crate::RWRegister<u32>,
8    #[doc = "Master Bus (AXI) Control Register 0"]
9    pub BMCR0: crate::RWRegister<u32>,
10    #[doc = "Master Bus (AXI) Control Register 1"]
11    pub BMCR1: crate::RWRegister<u32>,
12    #[doc = "Base Register 0 (For SDRAM CS0 device)"]
13    pub BR0: crate::RWRegister<u32>,
14    #[doc = "Base Register 1 (For SDRAM CS1 device)"]
15    pub BR1: crate::RWRegister<u32>,
16    #[doc = "Base Register 2 (For SDRAM CS2 device)"]
17    pub BR2: crate::RWRegister<u32>,
18    #[doc = "Base Register 3 (For SDRAM CS3 device)"]
19    pub BR3: crate::RWRegister<u32>,
20    #[doc = "Base Register 4 (For NAND device)"]
21    pub BR4: crate::RWRegister<u32>,
22    #[doc = "Base Register 5 (For NOR device)"]
23    pub BR5: crate::RWRegister<u32>,
24    #[doc = "Base Register 6 (For PSRAM device)"]
25    pub BR6: crate::RWRegister<u32>,
26    #[doc = "Base Register 7 (For DBI-B (MIPI Display Bus Interface Type B) device)"]
27    pub BR7: crate::RWRegister<u32>,
28    #[doc = "Base Register 8 (For NAND device)"]
29    pub BR8: crate::RWRegister<u32>,
30    #[doc = "DLL Control Register"]
31    pub DLLCR: crate::RWRegister<u32>,
32    #[doc = "Interrupt Enable Register"]
33    pub INTEN: crate::RWRegister<u32>,
34    #[doc = "Interrupt Enable Register"]
35    pub INTR: crate::RWRegister<u32>,
36    #[doc = "SDRAM control register 0"]
37    pub SDRAMCR0: crate::RWRegister<u32>,
38    #[doc = "SDRAM control register 1"]
39    pub SDRAMCR1: crate::RWRegister<u32>,
40    #[doc = "SDRAM control register 2"]
41    pub SDRAMCR2: crate::RWRegister<u32>,
42    #[doc = "SDRAM control register 3"]
43    pub SDRAMCR3: crate::RWRegister<u32>,
44    #[doc = "NAND control register 0"]
45    pub NANDCR0: crate::RWRegister<u32>,
46    #[doc = "NAND control register 1"]
47    pub NANDCR1: crate::RWRegister<u32>,
48    #[doc = "NAND control register 2"]
49    pub NANDCR2: crate::RWRegister<u32>,
50    #[doc = "NAND control register 3"]
51    pub NANDCR3: crate::RWRegister<u32>,
52    #[doc = "NOR control register 0"]
53    pub NORCR0: crate::RWRegister<u32>,
54    #[doc = "NOR control register 1"]
55    pub NORCR1: crate::RWRegister<u32>,
56    #[doc = "NOR control register 2"]
57    pub NORCR2: crate::RWRegister<u32>,
58    #[doc = "NOR control register 3"]
59    pub NORCR3: crate::RWRegister<u32>,
60    #[doc = "SRAM control register 0"]
61    pub SRAMCR0: crate::RWRegister<u32>,
62    #[doc = "SRAM control register 1"]
63    pub SRAMCR1: crate::RWRegister<u32>,
64    #[doc = "SRAM control register 2"]
65    pub SRAMCR2: crate::RWRegister<u32>,
66    #[doc = "SRAM control register 3"]
67    pub SRAMCR3: crate::RWRegister<u32>,
68    #[doc = "DBI-B control register 0"]
69    pub DBICR0: crate::RWRegister<u32>,
70    #[doc = "DBI-B control register 1"]
71    pub DBICR1: crate::RWRegister<u32>,
72    _reserved0: [u8; 0x08],
73    #[doc = "IP Command control register 0"]
74    pub IPCR0: crate::RWRegister<u32>,
75    #[doc = "IP Command control register 1"]
76    pub IPCR1: crate::RWRegister<u32>,
77    #[doc = "IP Command control register 2"]
78    pub IPCR2: crate::RWRegister<u32>,
79    #[doc = "IP Command register"]
80    pub IPCMD: crate::RWRegister<u32>,
81    #[doc = "TX DATA register (for IP Command)"]
82    pub IPTXDAT: crate::RWRegister<u32>,
83    _reserved1: [u8; 0x0c],
84    #[doc = "RX DATA register (for IP Command)"]
85    pub IPRXDAT: crate::RORegister<u32>,
86    _reserved2: [u8; 0x0c],
87    #[doc = "Status register 0"]
88    pub STS0: crate::RORegister<u32>,
89    #[doc = "Status register 1"]
90    pub STS1: crate::RORegister<u32>,
91    #[doc = "Status register 2"]
92    pub STS2: crate::RORegister<u32>,
93    #[doc = "Status register 3"]
94    pub STS3: crate::RORegister<u32>,
95    #[doc = "Status register 4"]
96    pub STS4: crate::RORegister<u32>,
97    #[doc = "Status register 5"]
98    pub STS5: crate::RORegister<u32>,
99    #[doc = "Status register 6"]
100    pub STS6: crate::RORegister<u32>,
101    #[doc = "Status register 7"]
102    pub STS7: crate::RORegister<u32>,
103    #[doc = "Status register 8"]
104    pub STS8: crate::RORegister<u32>,
105    #[doc = "Status register 9"]
106    pub STS9: crate::RORegister<u32>,
107    #[doc = "Status register 10"]
108    pub STS10: crate::RORegister<u32>,
109    #[doc = "Status register 11"]
110    pub STS11: crate::RORegister<u32>,
111    #[doc = "Status register 12"]
112    pub STS12: crate::RORegister<u32>,
113    #[doc = "Status register 13"]
114    pub STS13: crate::RORegister<u32>,
115    #[doc = "Status register 14"]
116    pub STS14: crate::RORegister<u32>,
117    #[doc = "Status register 15"]
118    pub STS15: crate::RORegister<u32>,
119}
120#[doc = "Module Control Register"]
121pub mod MCR {
122    #[doc = "Software Reset"]
123    pub mod SWRST {
124        pub const offset: u32 = 0;
125        pub const mask: u32 = 0x01 << offset;
126        pub mod R {}
127        pub mod W {}
128        pub mod RW {}
129    }
130    #[doc = "Module Disable"]
131    pub mod MDIS {
132        pub const offset: u32 = 1;
133        pub const mask: u32 = 0x01 << offset;
134        pub mod R {}
135        pub mod W {}
136        pub mod RW {
137            #[doc = "Module enabled"]
138            pub const MDIS_0: u32 = 0;
139            #[doc = "Master disabled."]
140            pub const MDIS_1: u32 = 0x01;
141        }
142    }
143    #[doc = "DQS (read strobe) mode"]
144    pub mod DQSMD {
145        pub const offset: u32 = 2;
146        pub const mask: u32 = 0x01 << offset;
147        pub mod R {}
148        pub mod W {}
149        pub mod RW {
150            #[doc = "Dummy read strobe loopbacked internally"]
151            pub const DQSMD_0: u32 = 0;
152            #[doc = "Dummy read strobe loopbacked from DQS pad"]
153            pub const DQSMD_1: u32 = 0x01;
154        }
155    }
156    #[doc = "WAIT/RDY# polarity for NOR/PSRAM"]
157    pub mod WPOL0 {
158        pub const offset: u32 = 6;
159        pub const mask: u32 = 0x01 << offset;
160        pub mod R {}
161        pub mod W {}
162        pub mod RW {
163            #[doc = "Low active"]
164            pub const WPOL0_0: u32 = 0;
165            #[doc = "High active"]
166            pub const WPOL0_1: u32 = 0x01;
167        }
168    }
169    #[doc = "WAIT/RDY# polarity for NAND"]
170    pub mod WPOL1 {
171        pub const offset: u32 = 7;
172        pub const mask: u32 = 0x01 << offset;
173        pub mod R {}
174        pub mod W {}
175        pub mod RW {
176            #[doc = "Low active"]
177            pub const WPOL1_0: u32 = 0;
178            #[doc = "High active"]
179            pub const WPOL1_1: u32 = 0x01;
180        }
181    }
182    #[doc = "Select DQS source when DQSMD and DLLSEL both set."]
183    pub mod DQSSEL {
184        pub const offset: u32 = 10;
185        pub const mask: u32 = 0x01 << offset;
186        pub mod R {}
187        pub mod W {}
188        pub mod RW {
189            #[doc = "SDRAM/NOR/SRAM read clock source is from DQS pad in synchronous mode."]
190            pub const DQSSEL_0: u32 = 0;
191            #[doc = "SDRAM/NOR/SRAM read clock source is from DLL delay chain in synchronous mode."]
192            pub const DQSSEL_1: u32 = 0x01;
193        }
194    }
195    #[doc = "Select DLL delay chain clock input."]
196    pub mod DLLSEL {
197        pub const offset: u32 = 11;
198        pub const mask: u32 = 0x01 << offset;
199        pub mod R {}
200        pub mod W {}
201        pub mod RW {
202            #[doc = "DLL delay chain clock input is from NAND device's DQS pad. For NAND synchronous mode only."]
203            pub const DLLSEL_0: u32 = 0;
204            #[doc = "DLL delay chain clock input is from internal clock. For SDRAM, NOR and SRAM synchronous mode only."]
205            pub const DLLSEL_1: u32 = 0x01;
206        }
207    }
208    #[doc = "Command Execution timeout cycles"]
209    pub mod CTO {
210        pub const offset: u32 = 16;
211        pub const mask: u32 = 0xff << offset;
212        pub mod R {}
213        pub mod W {}
214        pub mod RW {}
215    }
216    #[doc = "Bus timeout cycles"]
217    pub mod BTO {
218        pub const offset: u32 = 24;
219        pub const mask: u32 = 0x1f << offset;
220        pub mod R {}
221        pub mod W {}
222        pub mod RW {
223            #[doc = "255*1"]
224            pub const BTO_0: u32 = 0;
225            #[doc = "255*2 - 255*2^30"]
226            pub const BTO_1: u32 = 0x01;
227            #[doc = "255*2 - 255*2^30"]
228            pub const BTO_2: u32 = 0x02;
229            #[doc = "255*2 - 255*2^30"]
230            pub const BTO_3: u32 = 0x03;
231            #[doc = "255*2 - 255*2^30"]
232            pub const BTO_4: u32 = 0x04;
233            #[doc = "255*2 - 255*2^30"]
234            pub const BTO_5: u32 = 0x05;
235            #[doc = "255*2 - 255*2^30"]
236            pub const BTO_6: u32 = 0x06;
237            #[doc = "255*2 - 255*2^30"]
238            pub const BTO_7: u32 = 0x07;
239            #[doc = "255*2 - 255*2^30"]
240            pub const BTO_8: u32 = 0x08;
241            #[doc = "255*2 - 255*2^30"]
242            pub const BTO_9: u32 = 0x09;
243            #[doc = "255*2^31"]
244            pub const BTO_31: u32 = 0x1f;
245        }
246    }
247}
248#[doc = "IO Mux Control Register"]
249pub mod IOCR {
250    #[doc = "SEMC_A8 output selection"]
251    pub mod MUX_A8 {
252        pub const offset: u32 = 0;
253        pub const mask: u32 = 0x07 << offset;
254        pub mod R {}
255        pub mod W {}
256        pub mod RW {
257            #[doc = "SDRAM Address bit (A8)"]
258            pub const MUX_A8_0: u32 = 0;
259            #[doc = "NAND CE#"]
260            pub const MUX_A8_1: u32 = 0x01;
261            #[doc = "NOR CE#"]
262            pub const MUX_A8_2: u32 = 0x02;
263            #[doc = "PSRAM CE#"]
264            pub const MUX_A8_3: u32 = 0x03;
265            #[doc = "DBI CSX"]
266            pub const MUX_A8_4: u32 = 0x04;
267            #[doc = "SDRAM Address bit (A8)"]
268            pub const MUX_A8_5: u32 = 0x05;
269            #[doc = "SDRAM Address bit (A8)"]
270            pub const MUX_A8_6: u32 = 0x06;
271            #[doc = "SDRAM Address bit (A8)"]
272            pub const MUX_A8_7: u32 = 0x07;
273        }
274    }
275    #[doc = "SEMC_CSX0 output selection"]
276    pub mod MUX_CSX0 {
277        pub const offset: u32 = 3;
278        pub const mask: u32 = 0x07 << offset;
279        pub mod R {}
280        pub mod W {}
281        pub mod RW {
282            #[doc = "NOR/PSRAM Address bit 24 (A24)"]
283            pub const MUX_CSX0_0: u32 = 0;
284            #[doc = "SDRAM CS1"]
285            pub const MUX_CSX0_1: u32 = 0x01;
286            #[doc = "SDRAM CS2"]
287            pub const MUX_CSX0_2: u32 = 0x02;
288            #[doc = "SDRAM CS3"]
289            pub const MUX_CSX0_3: u32 = 0x03;
290            #[doc = "NAND CE#"]
291            pub const MUX_CSX0_4: u32 = 0x04;
292            #[doc = "NOR CE#"]
293            pub const MUX_CSX0_5: u32 = 0x05;
294            #[doc = "PSRAM CE#"]
295            pub const MUX_CSX0_6: u32 = 0x06;
296            #[doc = "DBI CSX"]
297            pub const MUX_CSX0_7: u32 = 0x07;
298        }
299    }
300    #[doc = "SEMC_CSX1 output selection"]
301    pub mod MUX_CSX1 {
302        pub const offset: u32 = 6;
303        pub const mask: u32 = 0x07 << offset;
304        pub mod R {}
305        pub mod W {}
306        pub mod RW {
307            #[doc = "NOR/PSRAM Address bit 25 (A25)"]
308            pub const MUX_CSX1_0: u32 = 0;
309            #[doc = "SDRAM CS1"]
310            pub const MUX_CSX1_1: u32 = 0x01;
311            #[doc = "SDRAM CS2"]
312            pub const MUX_CSX1_2: u32 = 0x02;
313            #[doc = "SDRAM CS3"]
314            pub const MUX_CSX1_3: u32 = 0x03;
315            #[doc = "NAND CE#"]
316            pub const MUX_CSX1_4: u32 = 0x04;
317            #[doc = "NOR CE#"]
318            pub const MUX_CSX1_5: u32 = 0x05;
319            #[doc = "PSRAM CE#"]
320            pub const MUX_CSX1_6: u32 = 0x06;
321            #[doc = "DBI CSX"]
322            pub const MUX_CSX1_7: u32 = 0x07;
323        }
324    }
325    #[doc = "SEMC_CSX2 output selection"]
326    pub mod MUX_CSX2 {
327        pub const offset: u32 = 9;
328        pub const mask: u32 = 0x07 << offset;
329        pub mod R {}
330        pub mod W {}
331        pub mod RW {
332            #[doc = "NOR/PSRAM Address bit 26 (A26)"]
333            pub const MUX_CSX2_0: u32 = 0;
334            #[doc = "SDRAM CS1"]
335            pub const MUX_CSX2_1: u32 = 0x01;
336            #[doc = "SDRAM CS2"]
337            pub const MUX_CSX2_2: u32 = 0x02;
338            #[doc = "SDRAM CS3"]
339            pub const MUX_CSX2_3: u32 = 0x03;
340            #[doc = "NAND CE#"]
341            pub const MUX_CSX2_4: u32 = 0x04;
342            #[doc = "NOR CE#"]
343            pub const MUX_CSX2_5: u32 = 0x05;
344            #[doc = "PSRAM CE#"]
345            pub const MUX_CSX2_6: u32 = 0x06;
346            #[doc = "DBI CSX"]
347            pub const MUX_CSX2_7: u32 = 0x07;
348        }
349    }
350    #[doc = "SEMC_CSX3 output selection"]
351    pub mod MUX_CSX3 {
352        pub const offset: u32 = 12;
353        pub const mask: u32 = 0x07 << offset;
354        pub mod R {}
355        pub mod W {}
356        pub mod RW {
357            #[doc = "NOR/PSRAM Address bit 27 (A27)"]
358            pub const MUX_CSX3_0: u32 = 0;
359            #[doc = "SDRAM CS1"]
360            pub const MUX_CSX3_1: u32 = 0x01;
361            #[doc = "SDRAM CS2"]
362            pub const MUX_CSX3_2: u32 = 0x02;
363            #[doc = "SDRAM CS3"]
364            pub const MUX_CSX3_3: u32 = 0x03;
365            #[doc = "NAND CE#"]
366            pub const MUX_CSX3_4: u32 = 0x04;
367            #[doc = "NOR CE#"]
368            pub const MUX_CSX3_5: u32 = 0x05;
369            #[doc = "PSRAM CE#"]
370            pub const MUX_CSX3_6: u32 = 0x06;
371            #[doc = "DBI CSX"]
372            pub const MUX_CSX3_7: u32 = 0x07;
373        }
374    }
375    #[doc = "SEMC_RDY function selection"]
376    pub mod MUX_RDY {
377        pub const offset: u32 = 15;
378        pub const mask: u32 = 0x07 << offset;
379        pub mod R {}
380        pub mod W {}
381        pub mod RW {
382            #[doc = "NAND Ready/Wait# input"]
383            pub const MUX_RDY_0: u32 = 0;
384            #[doc = "SDRAM CS1"]
385            pub const MUX_RDY_1: u32 = 0x01;
386            #[doc = "SDRAM CS2"]
387            pub const MUX_RDY_2: u32 = 0x02;
388            #[doc = "SDRAM CS3"]
389            pub const MUX_RDY_3: u32 = 0x03;
390            #[doc = "NOR CE#"]
391            pub const MUX_RDY_4: u32 = 0x04;
392            #[doc = "PSRAM CE#"]
393            pub const MUX_RDY_5: u32 = 0x05;
394            #[doc = "DBI CSX"]
395            pub const MUX_RDY_6: u32 = 0x06;
396            #[doc = "NOR/PSRAM Address bit 27"]
397            pub const MUX_RDY_7: u32 = 0x07;
398        }
399    }
400    #[doc = "SEMC_CLKX0 function selection"]
401    pub mod MUX_CLKX0 {
402        pub const offset: u32 = 24;
403        pub const mask: u32 = 0x01 << offset;
404        pub mod R {}
405        pub mod W {}
406        pub mod RW {
407            #[doc = "NOR clock"]
408            pub const MUX_CLKX0_0: u32 = 0;
409            #[doc = "SRAM clock"]
410            pub const MUX_CLKX0_1: u32 = 0x01;
411        }
412    }
413    #[doc = "SEMC_CLKX1 function selection"]
414    pub mod MUX_CLKX1 {
415        pub const offset: u32 = 25;
416        pub const mask: u32 = 0x01 << offset;
417        pub mod R {}
418        pub mod W {}
419        pub mod RW {
420            #[doc = "NOR clock"]
421            pub const MUX_CLKX1_0: u32 = 0;
422            #[doc = "SRAM clock"]
423            pub const MUX_CLKX1_1: u32 = 0x01;
424        }
425    }
426}
427#[doc = "Master Bus (AXI) Control Register 0"]
428pub mod BMCR0 {
429    #[doc = "Weight of QoS"]
430    pub mod WQOS {
431        pub const offset: u32 = 0;
432        pub const mask: u32 = 0x0f << offset;
433        pub mod R {}
434        pub mod W {}
435        pub mod RW {}
436    }
437    #[doc = "Weight of Aging"]
438    pub mod WAGE {
439        pub const offset: u32 = 4;
440        pub const mask: u32 = 0x0f << offset;
441        pub mod R {}
442        pub mod W {}
443        pub mod RW {}
444    }
445    #[doc = "Weight of Slave Hit (no read/write switch)"]
446    pub mod WSH {
447        pub const offset: u32 = 8;
448        pub const mask: u32 = 0xff << offset;
449        pub mod R {}
450        pub mod W {}
451        pub mod RW {}
452    }
453    #[doc = "Weight of Slave Hit (Read/Write switch)"]
454    pub mod WRWS {
455        pub const offset: u32 = 16;
456        pub const mask: u32 = 0xff << offset;
457        pub mod R {}
458        pub mod W {}
459        pub mod RW {}
460    }
461}
462#[doc = "Master Bus (AXI) Control Register 1"]
463pub mod BMCR1 {
464    #[doc = "Weight of QoS"]
465    pub mod WQOS {
466        pub const offset: u32 = 0;
467        pub const mask: u32 = 0x0f << offset;
468        pub mod R {}
469        pub mod W {}
470        pub mod RW {}
471    }
472    #[doc = "Weight of Aging"]
473    pub mod WAGE {
474        pub const offset: u32 = 4;
475        pub const mask: u32 = 0x0f << offset;
476        pub mod R {}
477        pub mod W {}
478        pub mod RW {}
479    }
480    #[doc = "Weight of Page Hit"]
481    pub mod WPH {
482        pub const offset: u32 = 8;
483        pub const mask: u32 = 0xff << offset;
484        pub mod R {}
485        pub mod W {}
486        pub mod RW {}
487    }
488    #[doc = "Weight of Read/Write switch"]
489    pub mod WRWS {
490        pub const offset: u32 = 16;
491        pub const mask: u32 = 0xff << offset;
492        pub mod R {}
493        pub mod W {}
494        pub mod RW {}
495    }
496    #[doc = "Weight of Bank Rotation"]
497    pub mod WBR {
498        pub const offset: u32 = 24;
499        pub const mask: u32 = 0xff << offset;
500        pub mod R {}
501        pub mod W {}
502        pub mod RW {}
503    }
504}
505#[doc = "Base Register 0 (For SDRAM CS0 device)"]
506pub mod BR0 {
507    #[doc = "Valid"]
508    pub mod VLD {
509        pub const offset: u32 = 0;
510        pub const mask: u32 = 0x01 << offset;
511        pub mod R {}
512        pub mod W {}
513        pub mod RW {}
514    }
515    #[doc = "Memory size"]
516    pub mod MS {
517        pub const offset: u32 = 1;
518        pub const mask: u32 = 0x1f << offset;
519        pub mod R {}
520        pub mod W {}
521        pub mod RW {
522            #[doc = "4KB"]
523            pub const MS_0: u32 = 0;
524            #[doc = "8KB"]
525            pub const MS_1: u32 = 0x01;
526            #[doc = "16KB"]
527            pub const MS_2: u32 = 0x02;
528            #[doc = "32KB"]
529            pub const MS_3: u32 = 0x03;
530            #[doc = "64KB"]
531            pub const MS_4: u32 = 0x04;
532            #[doc = "128KB"]
533            pub const MS_5: u32 = 0x05;
534            #[doc = "256KB"]
535            pub const MS_6: u32 = 0x06;
536            #[doc = "512KB"]
537            pub const MS_7: u32 = 0x07;
538            #[doc = "1MB"]
539            pub const MS_8: u32 = 0x08;
540            #[doc = "2MB"]
541            pub const MS_9: u32 = 0x09;
542            #[doc = "4MB"]
543            pub const MS_10: u32 = 0x0a;
544            #[doc = "8MB"]
545            pub const MS_11: u32 = 0x0b;
546            #[doc = "16MB"]
547            pub const MS_12: u32 = 0x0c;
548            #[doc = "32MB"]
549            pub const MS_13: u32 = 0x0d;
550            #[doc = "64MB"]
551            pub const MS_14: u32 = 0x0e;
552            #[doc = "128MB"]
553            pub const MS_15: u32 = 0x0f;
554            #[doc = "256MB"]
555            pub const MS_16: u32 = 0x10;
556            #[doc = "512MB"]
557            pub const MS_17: u32 = 0x11;
558            #[doc = "1GB"]
559            pub const MS_18: u32 = 0x12;
560            #[doc = "2GB"]
561            pub const MS_19: u32 = 0x13;
562            #[doc = "4GB"]
563            pub const MS_20: u32 = 0x14;
564            #[doc = "4GB"]
565            pub const MS_21: u32 = 0x15;
566            #[doc = "4GB"]
567            pub const MS_22: u32 = 0x16;
568            #[doc = "4GB"]
569            pub const MS_23: u32 = 0x17;
570            #[doc = "4GB"]
571            pub const MS_24: u32 = 0x18;
572            #[doc = "4GB"]
573            pub const MS_25: u32 = 0x19;
574            #[doc = "4GB"]
575            pub const MS_26: u32 = 0x1a;
576            #[doc = "4GB"]
577            pub const MS_27: u32 = 0x1b;
578            #[doc = "4GB"]
579            pub const MS_28: u32 = 0x1c;
580            #[doc = "4GB"]
581            pub const MS_29: u32 = 0x1d;
582            #[doc = "4GB"]
583            pub const MS_30: u32 = 0x1e;
584            #[doc = "4GB"]
585            pub const MS_31: u32 = 0x1f;
586        }
587    }
588    #[doc = "Base Address"]
589    pub mod BA {
590        pub const offset: u32 = 12;
591        pub const mask: u32 = 0x000f_ffff << offset;
592        pub mod R {}
593        pub mod W {}
594        pub mod RW {}
595    }
596}
597#[doc = "Base Register 1 (For SDRAM CS1 device)"]
598pub mod BR1 {
599    #[doc = "Valid"]
600    pub mod VLD {
601        pub const offset: u32 = 0;
602        pub const mask: u32 = 0x01 << offset;
603        pub mod R {}
604        pub mod W {}
605        pub mod RW {}
606    }
607    #[doc = "Memory size"]
608    pub mod MS {
609        pub const offset: u32 = 1;
610        pub const mask: u32 = 0x1f << offset;
611        pub mod R {}
612        pub mod W {}
613        pub mod RW {
614            #[doc = "4KB"]
615            pub const MS_0: u32 = 0;
616            #[doc = "8KB"]
617            pub const MS_1: u32 = 0x01;
618            #[doc = "16KB"]
619            pub const MS_2: u32 = 0x02;
620            #[doc = "32KB"]
621            pub const MS_3: u32 = 0x03;
622            #[doc = "64KB"]
623            pub const MS_4: u32 = 0x04;
624            #[doc = "128KB"]
625            pub const MS_5: u32 = 0x05;
626            #[doc = "256KB"]
627            pub const MS_6: u32 = 0x06;
628            #[doc = "512KB"]
629            pub const MS_7: u32 = 0x07;
630            #[doc = "1MB"]
631            pub const MS_8: u32 = 0x08;
632            #[doc = "2MB"]
633            pub const MS_9: u32 = 0x09;
634            #[doc = "4MB"]
635            pub const MS_10: u32 = 0x0a;
636            #[doc = "8MB"]
637            pub const MS_11: u32 = 0x0b;
638            #[doc = "16MB"]
639            pub const MS_12: u32 = 0x0c;
640            #[doc = "32MB"]
641            pub const MS_13: u32 = 0x0d;
642            #[doc = "64MB"]
643            pub const MS_14: u32 = 0x0e;
644            #[doc = "128MB"]
645            pub const MS_15: u32 = 0x0f;
646            #[doc = "256MB"]
647            pub const MS_16: u32 = 0x10;
648            #[doc = "512MB"]
649            pub const MS_17: u32 = 0x11;
650            #[doc = "1GB"]
651            pub const MS_18: u32 = 0x12;
652            #[doc = "2GB"]
653            pub const MS_19: u32 = 0x13;
654            #[doc = "4GB"]
655            pub const MS_20: u32 = 0x14;
656            #[doc = "4GB"]
657            pub const MS_21: u32 = 0x15;
658            #[doc = "4GB"]
659            pub const MS_22: u32 = 0x16;
660            #[doc = "4GB"]
661            pub const MS_23: u32 = 0x17;
662            #[doc = "4GB"]
663            pub const MS_24: u32 = 0x18;
664            #[doc = "4GB"]
665            pub const MS_25: u32 = 0x19;
666            #[doc = "4GB"]
667            pub const MS_26: u32 = 0x1a;
668            #[doc = "4GB"]
669            pub const MS_27: u32 = 0x1b;
670            #[doc = "4GB"]
671            pub const MS_28: u32 = 0x1c;
672            #[doc = "4GB"]
673            pub const MS_29: u32 = 0x1d;
674            #[doc = "4GB"]
675            pub const MS_30: u32 = 0x1e;
676            #[doc = "4GB"]
677            pub const MS_31: u32 = 0x1f;
678        }
679    }
680    #[doc = "Base Address"]
681    pub mod BA {
682        pub const offset: u32 = 12;
683        pub const mask: u32 = 0x000f_ffff << offset;
684        pub mod R {}
685        pub mod W {}
686        pub mod RW {}
687    }
688}
689#[doc = "Base Register 2 (For SDRAM CS2 device)"]
690pub mod BR2 {
691    #[doc = "Valid"]
692    pub mod VLD {
693        pub const offset: u32 = 0;
694        pub const mask: u32 = 0x01 << offset;
695        pub mod R {}
696        pub mod W {}
697        pub mod RW {}
698    }
699    #[doc = "Memory size"]
700    pub mod MS {
701        pub const offset: u32 = 1;
702        pub const mask: u32 = 0x1f << offset;
703        pub mod R {}
704        pub mod W {}
705        pub mod RW {
706            #[doc = "4KB"]
707            pub const MS_0: u32 = 0;
708            #[doc = "8KB"]
709            pub const MS_1: u32 = 0x01;
710            #[doc = "16KB"]
711            pub const MS_2: u32 = 0x02;
712            #[doc = "32KB"]
713            pub const MS_3: u32 = 0x03;
714            #[doc = "64KB"]
715            pub const MS_4: u32 = 0x04;
716            #[doc = "128KB"]
717            pub const MS_5: u32 = 0x05;
718            #[doc = "256KB"]
719            pub const MS_6: u32 = 0x06;
720            #[doc = "512KB"]
721            pub const MS_7: u32 = 0x07;
722            #[doc = "1MB"]
723            pub const MS_8: u32 = 0x08;
724            #[doc = "2MB"]
725            pub const MS_9: u32 = 0x09;
726            #[doc = "4MB"]
727            pub const MS_10: u32 = 0x0a;
728            #[doc = "8MB"]
729            pub const MS_11: u32 = 0x0b;
730            #[doc = "16MB"]
731            pub const MS_12: u32 = 0x0c;
732            #[doc = "32MB"]
733            pub const MS_13: u32 = 0x0d;
734            #[doc = "64MB"]
735            pub const MS_14: u32 = 0x0e;
736            #[doc = "128MB"]
737            pub const MS_15: u32 = 0x0f;
738            #[doc = "256MB"]
739            pub const MS_16: u32 = 0x10;
740            #[doc = "512MB"]
741            pub const MS_17: u32 = 0x11;
742            #[doc = "1GB"]
743            pub const MS_18: u32 = 0x12;
744            #[doc = "2GB"]
745            pub const MS_19: u32 = 0x13;
746            #[doc = "4GB"]
747            pub const MS_20: u32 = 0x14;
748            #[doc = "4GB"]
749            pub const MS_21: u32 = 0x15;
750            #[doc = "4GB"]
751            pub const MS_22: u32 = 0x16;
752            #[doc = "4GB"]
753            pub const MS_23: u32 = 0x17;
754            #[doc = "4GB"]
755            pub const MS_24: u32 = 0x18;
756            #[doc = "4GB"]
757            pub const MS_25: u32 = 0x19;
758            #[doc = "4GB"]
759            pub const MS_26: u32 = 0x1a;
760            #[doc = "4GB"]
761            pub const MS_27: u32 = 0x1b;
762            #[doc = "4GB"]
763            pub const MS_28: u32 = 0x1c;
764            #[doc = "4GB"]
765            pub const MS_29: u32 = 0x1d;
766            #[doc = "4GB"]
767            pub const MS_30: u32 = 0x1e;
768            #[doc = "4GB"]
769            pub const MS_31: u32 = 0x1f;
770        }
771    }
772    #[doc = "Base Address"]
773    pub mod BA {
774        pub const offset: u32 = 12;
775        pub const mask: u32 = 0x000f_ffff << offset;
776        pub mod R {}
777        pub mod W {}
778        pub mod RW {}
779    }
780}
781#[doc = "Base Register 3 (For SDRAM CS3 device)"]
782pub mod BR3 {
783    #[doc = "Valid"]
784    pub mod VLD {
785        pub const offset: u32 = 0;
786        pub const mask: u32 = 0x01 << offset;
787        pub mod R {}
788        pub mod W {}
789        pub mod RW {}
790    }
791    #[doc = "Memory size"]
792    pub mod MS {
793        pub const offset: u32 = 1;
794        pub const mask: u32 = 0x1f << offset;
795        pub mod R {}
796        pub mod W {}
797        pub mod RW {
798            #[doc = "4KB"]
799            pub const MS_0: u32 = 0;
800            #[doc = "8KB"]
801            pub const MS_1: u32 = 0x01;
802            #[doc = "16KB"]
803            pub const MS_2: u32 = 0x02;
804            #[doc = "32KB"]
805            pub const MS_3: u32 = 0x03;
806            #[doc = "64KB"]
807            pub const MS_4: u32 = 0x04;
808            #[doc = "128KB"]
809            pub const MS_5: u32 = 0x05;
810            #[doc = "256KB"]
811            pub const MS_6: u32 = 0x06;
812            #[doc = "512KB"]
813            pub const MS_7: u32 = 0x07;
814            #[doc = "1MB"]
815            pub const MS_8: u32 = 0x08;
816            #[doc = "2MB"]
817            pub const MS_9: u32 = 0x09;
818            #[doc = "4MB"]
819            pub const MS_10: u32 = 0x0a;
820            #[doc = "8MB"]
821            pub const MS_11: u32 = 0x0b;
822            #[doc = "16MB"]
823            pub const MS_12: u32 = 0x0c;
824            #[doc = "32MB"]
825            pub const MS_13: u32 = 0x0d;
826            #[doc = "64MB"]
827            pub const MS_14: u32 = 0x0e;
828            #[doc = "128MB"]
829            pub const MS_15: u32 = 0x0f;
830            #[doc = "256MB"]
831            pub const MS_16: u32 = 0x10;
832            #[doc = "512MB"]
833            pub const MS_17: u32 = 0x11;
834            #[doc = "1GB"]
835            pub const MS_18: u32 = 0x12;
836            #[doc = "2GB"]
837            pub const MS_19: u32 = 0x13;
838            #[doc = "4GB"]
839            pub const MS_20: u32 = 0x14;
840            #[doc = "4GB"]
841            pub const MS_21: u32 = 0x15;
842            #[doc = "4GB"]
843            pub const MS_22: u32 = 0x16;
844            #[doc = "4GB"]
845            pub const MS_23: u32 = 0x17;
846            #[doc = "4GB"]
847            pub const MS_24: u32 = 0x18;
848            #[doc = "4GB"]
849            pub const MS_25: u32 = 0x19;
850            #[doc = "4GB"]
851            pub const MS_26: u32 = 0x1a;
852            #[doc = "4GB"]
853            pub const MS_27: u32 = 0x1b;
854            #[doc = "4GB"]
855            pub const MS_28: u32 = 0x1c;
856            #[doc = "4GB"]
857            pub const MS_29: u32 = 0x1d;
858            #[doc = "4GB"]
859            pub const MS_30: u32 = 0x1e;
860            #[doc = "4GB"]
861            pub const MS_31: u32 = 0x1f;
862        }
863    }
864    #[doc = "Base Address"]
865    pub mod BA {
866        pub const offset: u32 = 12;
867        pub const mask: u32 = 0x000f_ffff << offset;
868        pub mod R {}
869        pub mod W {}
870        pub mod RW {}
871    }
872}
873#[doc = "Base Register 4 (For NAND device)"]
874pub mod BR4 {
875    #[doc = "Valid"]
876    pub mod VLD {
877        pub const offset: u32 = 0;
878        pub const mask: u32 = 0x01 << offset;
879        pub mod R {}
880        pub mod W {}
881        pub mod RW {}
882    }
883    #[doc = "Memory size"]
884    pub mod MS {
885        pub const offset: u32 = 1;
886        pub const mask: u32 = 0x1f << offset;
887        pub mod R {}
888        pub mod W {}
889        pub mod RW {
890            #[doc = "4KB"]
891            pub const MS_0: u32 = 0;
892            #[doc = "8KB"]
893            pub const MS_1: u32 = 0x01;
894            #[doc = "16KB"]
895            pub const MS_2: u32 = 0x02;
896            #[doc = "32KB"]
897            pub const MS_3: u32 = 0x03;
898            #[doc = "64KB"]
899            pub const MS_4: u32 = 0x04;
900            #[doc = "128KB"]
901            pub const MS_5: u32 = 0x05;
902            #[doc = "256KB"]
903            pub const MS_6: u32 = 0x06;
904            #[doc = "512KB"]
905            pub const MS_7: u32 = 0x07;
906            #[doc = "1MB"]
907            pub const MS_8: u32 = 0x08;
908            #[doc = "2MB"]
909            pub const MS_9: u32 = 0x09;
910            #[doc = "4MB"]
911            pub const MS_10: u32 = 0x0a;
912            #[doc = "8MB"]
913            pub const MS_11: u32 = 0x0b;
914            #[doc = "16MB"]
915            pub const MS_12: u32 = 0x0c;
916            #[doc = "32MB"]
917            pub const MS_13: u32 = 0x0d;
918            #[doc = "64MB"]
919            pub const MS_14: u32 = 0x0e;
920            #[doc = "128MB"]
921            pub const MS_15: u32 = 0x0f;
922            #[doc = "256MB"]
923            pub const MS_16: u32 = 0x10;
924            #[doc = "512MB"]
925            pub const MS_17: u32 = 0x11;
926            #[doc = "1GB"]
927            pub const MS_18: u32 = 0x12;
928            #[doc = "2GB"]
929            pub const MS_19: u32 = 0x13;
930            #[doc = "4GB"]
931            pub const MS_20: u32 = 0x14;
932            #[doc = "4GB"]
933            pub const MS_21: u32 = 0x15;
934            #[doc = "4GB"]
935            pub const MS_22: u32 = 0x16;
936            #[doc = "4GB"]
937            pub const MS_23: u32 = 0x17;
938            #[doc = "4GB"]
939            pub const MS_24: u32 = 0x18;
940            #[doc = "4GB"]
941            pub const MS_25: u32 = 0x19;
942            #[doc = "4GB"]
943            pub const MS_26: u32 = 0x1a;
944            #[doc = "4GB"]
945            pub const MS_27: u32 = 0x1b;
946            #[doc = "4GB"]
947            pub const MS_28: u32 = 0x1c;
948            #[doc = "4GB"]
949            pub const MS_29: u32 = 0x1d;
950            #[doc = "4GB"]
951            pub const MS_30: u32 = 0x1e;
952            #[doc = "4GB"]
953            pub const MS_31: u32 = 0x1f;
954        }
955    }
956    #[doc = "Base Address"]
957    pub mod BA {
958        pub const offset: u32 = 12;
959        pub const mask: u32 = 0x000f_ffff << offset;
960        pub mod R {}
961        pub mod W {}
962        pub mod RW {}
963    }
964}
965#[doc = "Base Register 5 (For NOR device)"]
966pub mod BR5 {
967    #[doc = "Valid"]
968    pub mod VLD {
969        pub const offset: u32 = 0;
970        pub const mask: u32 = 0x01 << offset;
971        pub mod R {}
972        pub mod W {}
973        pub mod RW {}
974    }
975    #[doc = "Memory size"]
976    pub mod MS {
977        pub const offset: u32 = 1;
978        pub const mask: u32 = 0x1f << offset;
979        pub mod R {}
980        pub mod W {}
981        pub mod RW {
982            #[doc = "4KB"]
983            pub const MS_0: u32 = 0;
984            #[doc = "8KB"]
985            pub const MS_1: u32 = 0x01;
986            #[doc = "16KB"]
987            pub const MS_2: u32 = 0x02;
988            #[doc = "32KB"]
989            pub const MS_3: u32 = 0x03;
990            #[doc = "64KB"]
991            pub const MS_4: u32 = 0x04;
992            #[doc = "128KB"]
993            pub const MS_5: u32 = 0x05;
994            #[doc = "256KB"]
995            pub const MS_6: u32 = 0x06;
996            #[doc = "512KB"]
997            pub const MS_7: u32 = 0x07;
998            #[doc = "1MB"]
999            pub const MS_8: u32 = 0x08;
1000            #[doc = "2MB"]
1001            pub const MS_9: u32 = 0x09;
1002            #[doc = "4MB"]
1003            pub const MS_10: u32 = 0x0a;
1004            #[doc = "8MB"]
1005            pub const MS_11: u32 = 0x0b;
1006            #[doc = "16MB"]
1007            pub const MS_12: u32 = 0x0c;
1008            #[doc = "32MB"]
1009            pub const MS_13: u32 = 0x0d;
1010            #[doc = "64MB"]
1011            pub const MS_14: u32 = 0x0e;
1012            #[doc = "128MB"]
1013            pub const MS_15: u32 = 0x0f;
1014            #[doc = "256MB"]
1015            pub const MS_16: u32 = 0x10;
1016            #[doc = "512MB"]
1017            pub const MS_17: u32 = 0x11;
1018            #[doc = "1GB"]
1019            pub const MS_18: u32 = 0x12;
1020            #[doc = "2GB"]
1021            pub const MS_19: u32 = 0x13;
1022            #[doc = "4GB"]
1023            pub const MS_20: u32 = 0x14;
1024            #[doc = "4GB"]
1025            pub const MS_21: u32 = 0x15;
1026            #[doc = "4GB"]
1027            pub const MS_22: u32 = 0x16;
1028            #[doc = "4GB"]
1029            pub const MS_23: u32 = 0x17;
1030            #[doc = "4GB"]
1031            pub const MS_24: u32 = 0x18;
1032            #[doc = "4GB"]
1033            pub const MS_25: u32 = 0x19;
1034            #[doc = "4GB"]
1035            pub const MS_26: u32 = 0x1a;
1036            #[doc = "4GB"]
1037            pub const MS_27: u32 = 0x1b;
1038            #[doc = "4GB"]
1039            pub const MS_28: u32 = 0x1c;
1040            #[doc = "4GB"]
1041            pub const MS_29: u32 = 0x1d;
1042            #[doc = "4GB"]
1043            pub const MS_30: u32 = 0x1e;
1044            #[doc = "4GB"]
1045            pub const MS_31: u32 = 0x1f;
1046        }
1047    }
1048    #[doc = "Base Address"]
1049    pub mod BA {
1050        pub const offset: u32 = 12;
1051        pub const mask: u32 = 0x000f_ffff << offset;
1052        pub mod R {}
1053        pub mod W {}
1054        pub mod RW {}
1055    }
1056}
1057#[doc = "Base Register 6 (For PSRAM device)"]
1058pub mod BR6 {
1059    #[doc = "Valid"]
1060    pub mod VLD {
1061        pub const offset: u32 = 0;
1062        pub const mask: u32 = 0x01 << offset;
1063        pub mod R {}
1064        pub mod W {}
1065        pub mod RW {}
1066    }
1067    #[doc = "Memory size"]
1068    pub mod MS {
1069        pub const offset: u32 = 1;
1070        pub const mask: u32 = 0x1f << offset;
1071        pub mod R {}
1072        pub mod W {}
1073        pub mod RW {
1074            #[doc = "4KB"]
1075            pub const MS_0: u32 = 0;
1076            #[doc = "8KB"]
1077            pub const MS_1: u32 = 0x01;
1078            #[doc = "16KB"]
1079            pub const MS_2: u32 = 0x02;
1080            #[doc = "32KB"]
1081            pub const MS_3: u32 = 0x03;
1082            #[doc = "64KB"]
1083            pub const MS_4: u32 = 0x04;
1084            #[doc = "128KB"]
1085            pub const MS_5: u32 = 0x05;
1086            #[doc = "256KB"]
1087            pub const MS_6: u32 = 0x06;
1088            #[doc = "512KB"]
1089            pub const MS_7: u32 = 0x07;
1090            #[doc = "1MB"]
1091            pub const MS_8: u32 = 0x08;
1092            #[doc = "2MB"]
1093            pub const MS_9: u32 = 0x09;
1094            #[doc = "4MB"]
1095            pub const MS_10: u32 = 0x0a;
1096            #[doc = "8MB"]
1097            pub const MS_11: u32 = 0x0b;
1098            #[doc = "16MB"]
1099            pub const MS_12: u32 = 0x0c;
1100            #[doc = "32MB"]
1101            pub const MS_13: u32 = 0x0d;
1102            #[doc = "64MB"]
1103            pub const MS_14: u32 = 0x0e;
1104            #[doc = "128MB"]
1105            pub const MS_15: u32 = 0x0f;
1106            #[doc = "256MB"]
1107            pub const MS_16: u32 = 0x10;
1108            #[doc = "512MB"]
1109            pub const MS_17: u32 = 0x11;
1110            #[doc = "1GB"]
1111            pub const MS_18: u32 = 0x12;
1112            #[doc = "2GB"]
1113            pub const MS_19: u32 = 0x13;
1114            #[doc = "4GB"]
1115            pub const MS_20: u32 = 0x14;
1116            #[doc = "4GB"]
1117            pub const MS_21: u32 = 0x15;
1118            #[doc = "4GB"]
1119            pub const MS_22: u32 = 0x16;
1120            #[doc = "4GB"]
1121            pub const MS_23: u32 = 0x17;
1122            #[doc = "4GB"]
1123            pub const MS_24: u32 = 0x18;
1124            #[doc = "4GB"]
1125            pub const MS_25: u32 = 0x19;
1126            #[doc = "4GB"]
1127            pub const MS_26: u32 = 0x1a;
1128            #[doc = "4GB"]
1129            pub const MS_27: u32 = 0x1b;
1130            #[doc = "4GB"]
1131            pub const MS_28: u32 = 0x1c;
1132            #[doc = "4GB"]
1133            pub const MS_29: u32 = 0x1d;
1134            #[doc = "4GB"]
1135            pub const MS_30: u32 = 0x1e;
1136            #[doc = "4GB"]
1137            pub const MS_31: u32 = 0x1f;
1138        }
1139    }
1140    #[doc = "Base Address"]
1141    pub mod BA {
1142        pub const offset: u32 = 12;
1143        pub const mask: u32 = 0x000f_ffff << offset;
1144        pub mod R {}
1145        pub mod W {}
1146        pub mod RW {}
1147    }
1148}
1149#[doc = "Base Register 7 (For DBI-B (MIPI Display Bus Interface Type B) device)"]
1150pub mod BR7 {
1151    #[doc = "Valid"]
1152    pub mod VLD {
1153        pub const offset: u32 = 0;
1154        pub const mask: u32 = 0x01 << offset;
1155        pub mod R {}
1156        pub mod W {}
1157        pub mod RW {}
1158    }
1159    #[doc = "Memory size"]
1160    pub mod MS {
1161        pub const offset: u32 = 1;
1162        pub const mask: u32 = 0x1f << offset;
1163        pub mod R {}
1164        pub mod W {}
1165        pub mod RW {
1166            #[doc = "4KB"]
1167            pub const MS_0: u32 = 0;
1168            #[doc = "8KB"]
1169            pub const MS_1: u32 = 0x01;
1170            #[doc = "16KB"]
1171            pub const MS_2: u32 = 0x02;
1172            #[doc = "32KB"]
1173            pub const MS_3: u32 = 0x03;
1174            #[doc = "64KB"]
1175            pub const MS_4: u32 = 0x04;
1176            #[doc = "128KB"]
1177            pub const MS_5: u32 = 0x05;
1178            #[doc = "256KB"]
1179            pub const MS_6: u32 = 0x06;
1180            #[doc = "512KB"]
1181            pub const MS_7: u32 = 0x07;
1182            #[doc = "1MB"]
1183            pub const MS_8: u32 = 0x08;
1184            #[doc = "2MB"]
1185            pub const MS_9: u32 = 0x09;
1186            #[doc = "4MB"]
1187            pub const MS_10: u32 = 0x0a;
1188            #[doc = "8MB"]
1189            pub const MS_11: u32 = 0x0b;
1190            #[doc = "16MB"]
1191            pub const MS_12: u32 = 0x0c;
1192            #[doc = "32MB"]
1193            pub const MS_13: u32 = 0x0d;
1194            #[doc = "64MB"]
1195            pub const MS_14: u32 = 0x0e;
1196            #[doc = "128MB"]
1197            pub const MS_15: u32 = 0x0f;
1198            #[doc = "256MB"]
1199            pub const MS_16: u32 = 0x10;
1200            #[doc = "512MB"]
1201            pub const MS_17: u32 = 0x11;
1202            #[doc = "1GB"]
1203            pub const MS_18: u32 = 0x12;
1204            #[doc = "2GB"]
1205            pub const MS_19: u32 = 0x13;
1206            #[doc = "4GB"]
1207            pub const MS_20: u32 = 0x14;
1208            #[doc = "4GB"]
1209            pub const MS_21: u32 = 0x15;
1210            #[doc = "4GB"]
1211            pub const MS_22: u32 = 0x16;
1212            #[doc = "4GB"]
1213            pub const MS_23: u32 = 0x17;
1214            #[doc = "4GB"]
1215            pub const MS_24: u32 = 0x18;
1216            #[doc = "4GB"]
1217            pub const MS_25: u32 = 0x19;
1218            #[doc = "4GB"]
1219            pub const MS_26: u32 = 0x1a;
1220            #[doc = "4GB"]
1221            pub const MS_27: u32 = 0x1b;
1222            #[doc = "4GB"]
1223            pub const MS_28: u32 = 0x1c;
1224            #[doc = "4GB"]
1225            pub const MS_29: u32 = 0x1d;
1226            #[doc = "4GB"]
1227            pub const MS_30: u32 = 0x1e;
1228            #[doc = "4GB"]
1229            pub const MS_31: u32 = 0x1f;
1230        }
1231    }
1232    #[doc = "Base Address"]
1233    pub mod BA {
1234        pub const offset: u32 = 12;
1235        pub const mask: u32 = 0x000f_ffff << offset;
1236        pub mod R {}
1237        pub mod W {}
1238        pub mod RW {}
1239    }
1240}
1241#[doc = "Base Register 8 (For NAND device)"]
1242pub mod BR8 {
1243    #[doc = "Valid"]
1244    pub mod VLD {
1245        pub const offset: u32 = 0;
1246        pub const mask: u32 = 0x01 << offset;
1247        pub mod R {}
1248        pub mod W {}
1249        pub mod RW {}
1250    }
1251    #[doc = "Memory size"]
1252    pub mod MS {
1253        pub const offset: u32 = 1;
1254        pub const mask: u32 = 0x1f << offset;
1255        pub mod R {}
1256        pub mod W {}
1257        pub mod RW {
1258            #[doc = "4KB"]
1259            pub const MS_0: u32 = 0;
1260            #[doc = "8KB"]
1261            pub const MS_1: u32 = 0x01;
1262            #[doc = "16KB"]
1263            pub const MS_2: u32 = 0x02;
1264            #[doc = "32KB"]
1265            pub const MS_3: u32 = 0x03;
1266            #[doc = "64KB"]
1267            pub const MS_4: u32 = 0x04;
1268            #[doc = "128KB"]
1269            pub const MS_5: u32 = 0x05;
1270            #[doc = "256KB"]
1271            pub const MS_6: u32 = 0x06;
1272            #[doc = "512KB"]
1273            pub const MS_7: u32 = 0x07;
1274            #[doc = "1MB"]
1275            pub const MS_8: u32 = 0x08;
1276            #[doc = "2MB"]
1277            pub const MS_9: u32 = 0x09;
1278            #[doc = "4MB"]
1279            pub const MS_10: u32 = 0x0a;
1280            #[doc = "8MB"]
1281            pub const MS_11: u32 = 0x0b;
1282            #[doc = "16MB"]
1283            pub const MS_12: u32 = 0x0c;
1284            #[doc = "32MB"]
1285            pub const MS_13: u32 = 0x0d;
1286            #[doc = "64MB"]
1287            pub const MS_14: u32 = 0x0e;
1288            #[doc = "128MB"]
1289            pub const MS_15: u32 = 0x0f;
1290            #[doc = "256MB"]
1291            pub const MS_16: u32 = 0x10;
1292            #[doc = "512MB"]
1293            pub const MS_17: u32 = 0x11;
1294            #[doc = "1GB"]
1295            pub const MS_18: u32 = 0x12;
1296            #[doc = "2GB"]
1297            pub const MS_19: u32 = 0x13;
1298            #[doc = "4GB"]
1299            pub const MS_20: u32 = 0x14;
1300            #[doc = "4GB"]
1301            pub const MS_21: u32 = 0x15;
1302            #[doc = "4GB"]
1303            pub const MS_22: u32 = 0x16;
1304            #[doc = "4GB"]
1305            pub const MS_23: u32 = 0x17;
1306            #[doc = "4GB"]
1307            pub const MS_24: u32 = 0x18;
1308            #[doc = "4GB"]
1309            pub const MS_25: u32 = 0x19;
1310            #[doc = "4GB"]
1311            pub const MS_26: u32 = 0x1a;
1312            #[doc = "4GB"]
1313            pub const MS_27: u32 = 0x1b;
1314            #[doc = "4GB"]
1315            pub const MS_28: u32 = 0x1c;
1316            #[doc = "4GB"]
1317            pub const MS_29: u32 = 0x1d;
1318            #[doc = "4GB"]
1319            pub const MS_30: u32 = 0x1e;
1320            #[doc = "4GB"]
1321            pub const MS_31: u32 = 0x1f;
1322        }
1323    }
1324    #[doc = "Base Address"]
1325    pub mod BA {
1326        pub const offset: u32 = 12;
1327        pub const mask: u32 = 0x000f_ffff << offset;
1328        pub mod R {}
1329        pub mod W {}
1330        pub mod RW {}
1331    }
1332}
1333#[doc = "DLL Control Register"]
1334pub mod DLLCR {
1335    #[doc = "DLL calibration enable."]
1336    pub mod DLLEN {
1337        pub const offset: u32 = 0;
1338        pub const mask: u32 = 0x01 << offset;
1339        pub mod R {}
1340        pub mod W {}
1341        pub mod RW {}
1342    }
1343    #[doc = "Software could force a reset on DLL by setting this field to 0x1. This will cause the DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset action is edge triggered, so software need to clear this bit after set this bit (no delay limitation)."]
1344    pub mod DLLRESET {
1345        pub const offset: u32 = 1;
1346        pub const mask: u32 = 0x01 << offset;
1347        pub mod R {}
1348        pub mod W {}
1349        pub mod RW {}
1350    }
1351    #[doc = "The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (ipgclock)."]
1352    pub mod SLVDLYTARGET {
1353        pub const offset: u32 = 3;
1354        pub const mask: u32 = 0x0f << offset;
1355        pub mod R {}
1356        pub mod W {}
1357        pub mod RW {}
1358    }
1359    #[doc = "Slave clock delay line delay cell number selection override enable."]
1360    pub mod OVRDEN {
1361        pub const offset: u32 = 8;
1362        pub const mask: u32 = 0x01 << offset;
1363        pub mod R {}
1364        pub mod W {}
1365        pub mod RW {}
1366    }
1367    #[doc = "Slave clock delay line delay cell number selection override value."]
1368    pub mod OVRDVAL {
1369        pub const offset: u32 = 9;
1370        pub const mask: u32 = 0x3f << offset;
1371        pub mod R {}
1372        pub mod W {}
1373        pub mod RW {}
1374    }
1375}
1376#[doc = "Interrupt Enable Register"]
1377pub mod INTEN {
1378    #[doc = "IP command done interrupt enable"]
1379    pub mod IPCMDDONEEN {
1380        pub const offset: u32 = 0;
1381        pub const mask: u32 = 0x01 << offset;
1382        pub mod R {}
1383        pub mod W {}
1384        pub mod RW {}
1385    }
1386    #[doc = "IP command error interrupt enable"]
1387    pub mod IPCMDERREN {
1388        pub const offset: u32 = 1;
1389        pub const mask: u32 = 0x01 << offset;
1390        pub mod R {}
1391        pub mod W {}
1392        pub mod RW {}
1393    }
1394    #[doc = "AXI command error interrupt enable"]
1395    pub mod AXICMDERREN {
1396        pub const offset: u32 = 2;
1397        pub const mask: u32 = 0x01 << offset;
1398        pub mod R {}
1399        pub mod W {}
1400        pub mod RW {}
1401    }
1402    #[doc = "AXI bus error interrupt enable"]
1403    pub mod AXIBUSERREN {
1404        pub const offset: u32 = 3;
1405        pub const mask: u32 = 0x01 << offset;
1406        pub mod R {}
1407        pub mod W {}
1408        pub mod RW {}
1409    }
1410    #[doc = "This bit enable/disable the NDPAGEEND interrupt generation."]
1411    pub mod NDPAGEENDEN {
1412        pub const offset: u32 = 4;
1413        pub const mask: u32 = 0x01 << offset;
1414        pub mod R {}
1415        pub mod W {}
1416        pub mod RW {
1417            #[doc = "Disable"]
1418            pub const NDPAGEENDEN_0: u32 = 0;
1419            #[doc = "Enable"]
1420            pub const NDPAGEENDEN_1: u32 = 0x01;
1421        }
1422    }
1423    #[doc = "This bit enable/disable the NDNOPEND interrupt generation."]
1424    pub mod NDNOPENDEN {
1425        pub const offset: u32 = 5;
1426        pub const mask: u32 = 0x01 << offset;
1427        pub mod R {}
1428        pub mod W {}
1429        pub mod RW {
1430            #[doc = "Disable"]
1431            pub const NDNOPENDEN_0: u32 = 0;
1432            #[doc = "Enable"]
1433            pub const NDNOPENDEN_1: u32 = 0x01;
1434        }
1435    }
1436}
1437#[doc = "Interrupt Enable Register"]
1438pub mod INTR {
1439    #[doc = "IP command normal done interrupt"]
1440    pub mod IPCMDDONE {
1441        pub const offset: u32 = 0;
1442        pub const mask: u32 = 0x01 << offset;
1443        pub mod R {}
1444        pub mod W {}
1445        pub mod RW {}
1446    }
1447    #[doc = "IP command error done interrupt"]
1448    pub mod IPCMDERR {
1449        pub const offset: u32 = 1;
1450        pub const mask: u32 = 0x01 << offset;
1451        pub mod R {}
1452        pub mod W {}
1453        pub mod RW {}
1454    }
1455    #[doc = "AXI command error interrupt"]
1456    pub mod AXICMDERR {
1457        pub const offset: u32 = 2;
1458        pub const mask: u32 = 0x01 << offset;
1459        pub mod R {}
1460        pub mod W {}
1461        pub mod RW {}
1462    }
1463    #[doc = "AXI bus error interrupt"]
1464    pub mod AXIBUSERR {
1465        pub const offset: u32 = 3;
1466        pub const mask: u32 = 0x01 << offset;
1467        pub mod R {}
1468        pub mod W {}
1469        pub mod RW {}
1470    }
1471    #[doc = "This interrupt is generated when the last address of one page in NAND device is written by AXI command"]
1472    pub mod NDPAGEEND {
1473        pub const offset: u32 = 4;
1474        pub const mask: u32 = 0x01 << offset;
1475        pub mod R {}
1476        pub mod W {}
1477        pub mod RW {}
1478    }
1479    #[doc = "This interrupt is generated when all pending AXI write command to NAND is finished on NAND interface."]
1480    pub mod NDNOPEND {
1481        pub const offset: u32 = 5;
1482        pub const mask: u32 = 0x01 << offset;
1483        pub mod R {}
1484        pub mod W {}
1485        pub mod RW {}
1486    }
1487}
1488#[doc = "SDRAM control register 0"]
1489pub mod SDRAMCR0 {
1490    #[doc = "Port Size"]
1491    pub mod PS {
1492        pub const offset: u32 = 0;
1493        pub const mask: u32 = 0x01 << offset;
1494        pub mod R {}
1495        pub mod W {}
1496        pub mod RW {
1497            #[doc = "8bit"]
1498            pub const PS_0: u32 = 0;
1499            #[doc = "16bit"]
1500            pub const PS_1: u32 = 0x01;
1501        }
1502    }
1503    #[doc = "Burst Length"]
1504    pub mod BL {
1505        pub const offset: u32 = 4;
1506        pub const mask: u32 = 0x07 << offset;
1507        pub mod R {}
1508        pub mod W {}
1509        pub mod RW {
1510            #[doc = "1"]
1511            pub const BL_0: u32 = 0;
1512            #[doc = "2"]
1513            pub const BL_1: u32 = 0x01;
1514            #[doc = "4"]
1515            pub const BL_2: u32 = 0x02;
1516            #[doc = "8"]
1517            pub const BL_3: u32 = 0x03;
1518            #[doc = "8"]
1519            pub const BL_4: u32 = 0x04;
1520            #[doc = "8"]
1521            pub const BL_5: u32 = 0x05;
1522            #[doc = "8"]
1523            pub const BL_6: u32 = 0x06;
1524            #[doc = "8"]
1525            pub const BL_7: u32 = 0x07;
1526        }
1527    }
1528    #[doc = "Column 8 selection bit"]
1529    pub mod COL8 {
1530        pub const offset: u32 = 7;
1531        pub const mask: u32 = 0x01 << offset;
1532        pub mod R {}
1533        pub mod W {}
1534        pub mod RW {
1535            #[doc = "Column address bit number is decided by COL field."]
1536            pub const COL8_0: u32 = 0;
1537            #[doc = "Column address bit number is 8. COL field is ignored."]
1538            pub const COL8_1: u32 = 0x01;
1539        }
1540    }
1541    #[doc = "Column address bit number"]
1542    pub mod COL {
1543        pub const offset: u32 = 8;
1544        pub const mask: u32 = 0x03 << offset;
1545        pub mod R {}
1546        pub mod W {}
1547        pub mod RW {
1548            #[doc = "12 bit"]
1549            pub const COL_0: u32 = 0;
1550            #[doc = "11 bit"]
1551            pub const COL_1: u32 = 0x01;
1552            #[doc = "10 bit"]
1553            pub const COL_2: u32 = 0x02;
1554            #[doc = "9 bit"]
1555            pub const COL_3: u32 = 0x03;
1556        }
1557    }
1558    #[doc = "CAS Latency"]
1559    pub mod CL {
1560        pub const offset: u32 = 10;
1561        pub const mask: u32 = 0x03 << offset;
1562        pub mod R {}
1563        pub mod W {}
1564        pub mod RW {
1565            #[doc = "1"]
1566            pub const CL_0: u32 = 0;
1567            #[doc = "1"]
1568            pub const CL_1: u32 = 0x01;
1569            #[doc = "2"]
1570            pub const CL_2: u32 = 0x02;
1571            #[doc = "3"]
1572            pub const CL_3: u32 = 0x03;
1573        }
1574    }
1575    #[doc = "2 Bank selection bit"]
1576    pub mod BANK2 {
1577        pub const offset: u32 = 14;
1578        pub const mask: u32 = 0x01 << offset;
1579        pub mod R {}
1580        pub mod W {}
1581        pub mod RW {
1582            #[doc = "SDRAM device has 4 banks."]
1583            pub const BANK2_0: u32 = 0;
1584            #[doc = "SDRAM device has 2 banks."]
1585            pub const BANK2_1: u32 = 0x01;
1586        }
1587    }
1588}
1589#[doc = "SDRAM control register 1"]
1590pub mod SDRAMCR1 {
1591    #[doc = "PRECHARGE to ACT/Refresh wait time"]
1592    pub mod PRE2ACT {
1593        pub const offset: u32 = 0;
1594        pub const mask: u32 = 0x0f << offset;
1595        pub mod R {}
1596        pub mod W {}
1597        pub mod RW {}
1598    }
1599    #[doc = "ACT to Read/Write wait time"]
1600    pub mod ACT2RW {
1601        pub const offset: u32 = 4;
1602        pub const mask: u32 = 0x0f << offset;
1603        pub mod R {}
1604        pub mod W {}
1605        pub mod RW {}
1606    }
1607    #[doc = "Refresh recovery time"]
1608    pub mod RFRC {
1609        pub const offset: u32 = 8;
1610        pub const mask: u32 = 0x1f << offset;
1611        pub mod R {}
1612        pub mod W {}
1613        pub mod RW {}
1614    }
1615    #[doc = "Write recovery time"]
1616    pub mod WRC {
1617        pub const offset: u32 = 13;
1618        pub const mask: u32 = 0x07 << offset;
1619        pub mod R {}
1620        pub mod W {}
1621        pub mod RW {}
1622    }
1623    #[doc = "CKE OFF minimum time"]
1624    pub mod CKEOFF {
1625        pub const offset: u32 = 16;
1626        pub const mask: u32 = 0x0f << offset;
1627        pub mod R {}
1628        pub mod W {}
1629        pub mod RW {}
1630    }
1631    #[doc = "ACT to Precharge minimum time"]
1632    pub mod ACT2PRE {
1633        pub const offset: u32 = 20;
1634        pub const mask: u32 = 0x0f << offset;
1635        pub mod R {}
1636        pub mod W {}
1637        pub mod RW {}
1638    }
1639}
1640#[doc = "SDRAM control register 2"]
1641pub mod SDRAMCR2 {
1642    #[doc = "Self Refresh Recovery time"]
1643    pub mod SRRC {
1644        pub const offset: u32 = 0;
1645        pub const mask: u32 = 0xff << offset;
1646        pub mod R {}
1647        pub mod W {}
1648        pub mod RW {}
1649    }
1650    #[doc = "Refresh to Refresh wait time"]
1651    pub mod REF2REF {
1652        pub const offset: u32 = 8;
1653        pub const mask: u32 = 0xff << offset;
1654        pub mod R {}
1655        pub mod W {}
1656        pub mod RW {}
1657    }
1658    #[doc = "ACT to ACT wait time"]
1659    pub mod ACT2ACT {
1660        pub const offset: u32 = 16;
1661        pub const mask: u32 = 0xff << offset;
1662        pub mod R {}
1663        pub mod W {}
1664        pub mod RW {}
1665    }
1666    #[doc = "SDRAM Idle timeout"]
1667    pub mod ITO {
1668        pub const offset: u32 = 24;
1669        pub const mask: u32 = 0xff << offset;
1670        pub mod R {}
1671        pub mod W {}
1672        pub mod RW {
1673            #[doc = "IDLE timeout period is 256*Prescale period."]
1674            pub const ITO_0: u32 = 0;
1675            #[doc = "IDLE timeout period is ITO*Prescale period."]
1676            pub const ITO_1: u32 = 0x01;
1677            #[doc = "IDLE timeout period is ITO*Prescale period."]
1678            pub const ITO_2: u32 = 0x02;
1679            #[doc = "IDLE timeout period is ITO*Prescale period."]
1680            pub const ITO_3: u32 = 0x03;
1681            #[doc = "IDLE timeout period is ITO*Prescale period."]
1682            pub const ITO_4: u32 = 0x04;
1683            #[doc = "IDLE timeout period is ITO*Prescale period."]
1684            pub const ITO_5: u32 = 0x05;
1685            #[doc = "IDLE timeout period is ITO*Prescale period."]
1686            pub const ITO_6: u32 = 0x06;
1687            #[doc = "IDLE timeout period is ITO*Prescale period."]
1688            pub const ITO_7: u32 = 0x07;
1689            #[doc = "IDLE timeout period is ITO*Prescale period."]
1690            pub const ITO_8: u32 = 0x08;
1691            #[doc = "IDLE timeout period is ITO*Prescale period."]
1692            pub const ITO_9: u32 = 0x09;
1693        }
1694    }
1695}
1696#[doc = "SDRAM control register 3"]
1697pub mod SDRAMCR3 {
1698    #[doc = "Refresh enable"]
1699    pub mod REN {
1700        pub const offset: u32 = 0;
1701        pub const mask: u32 = 0x01 << offset;
1702        pub mod R {}
1703        pub mod W {}
1704        pub mod RW {}
1705    }
1706    #[doc = "Refresh burst length"]
1707    pub mod REBL {
1708        pub const offset: u32 = 1;
1709        pub const mask: u32 = 0x07 << offset;
1710        pub mod R {}
1711        pub mod W {}
1712        pub mod RW {
1713            #[doc = "1"]
1714            pub const REBL_0: u32 = 0;
1715            #[doc = "2"]
1716            pub const REBL_1: u32 = 0x01;
1717            #[doc = "3"]
1718            pub const REBL_2: u32 = 0x02;
1719            #[doc = "4"]
1720            pub const REBL_3: u32 = 0x03;
1721            #[doc = "5"]
1722            pub const REBL_4: u32 = 0x04;
1723            #[doc = "6"]
1724            pub const REBL_5: u32 = 0x05;
1725            #[doc = "7"]
1726            pub const REBL_6: u32 = 0x06;
1727            #[doc = "8"]
1728            pub const REBL_7: u32 = 0x07;
1729        }
1730    }
1731    #[doc = "Prescaler timer period"]
1732    pub mod PRESCALE {
1733        pub const offset: u32 = 8;
1734        pub const mask: u32 = 0xff << offset;
1735        pub mod R {}
1736        pub mod W {}
1737        pub mod RW {
1738            #[doc = "256*16 cycle"]
1739            pub const PRESCALE_0: u32 = 0;
1740            #[doc = "PRESCALE*16 cycle"]
1741            pub const PRESCALE_1: u32 = 0x01;
1742            #[doc = "PRESCALE*16 cycle"]
1743            pub const PRESCALE_2: u32 = 0x02;
1744            #[doc = "PRESCALE*16 cycle"]
1745            pub const PRESCALE_3: u32 = 0x03;
1746            #[doc = "PRESCALE*16 cycle"]
1747            pub const PRESCALE_4: u32 = 0x04;
1748            #[doc = "PRESCALE*16 cycle"]
1749            pub const PRESCALE_5: u32 = 0x05;
1750            #[doc = "PRESCALE*16 cycle"]
1751            pub const PRESCALE_6: u32 = 0x06;
1752            #[doc = "PRESCALE*16 cycle"]
1753            pub const PRESCALE_7: u32 = 0x07;
1754            #[doc = "PRESCALE*16 cycle"]
1755            pub const PRESCALE_8: u32 = 0x08;
1756            #[doc = "PRESCALE*16 cycle"]
1757            pub const PRESCALE_9: u32 = 0x09;
1758        }
1759    }
1760    #[doc = "Refresh timer period"]
1761    pub mod RT {
1762        pub const offset: u32 = 16;
1763        pub const mask: u32 = 0xff << offset;
1764        pub mod R {}
1765        pub mod W {}
1766        pub mod RW {
1767            #[doc = "256*Prescaler period"]
1768            pub const RT_0: u32 = 0;
1769            #[doc = "RT*Prescaler period"]
1770            pub const RT_1: u32 = 0x01;
1771            #[doc = "RT*Prescaler period"]
1772            pub const RT_2: u32 = 0x02;
1773            #[doc = "RT*Prescaler period"]
1774            pub const RT_3: u32 = 0x03;
1775            #[doc = "RT*Prescaler period"]
1776            pub const RT_4: u32 = 0x04;
1777            #[doc = "RT*Prescaler period"]
1778            pub const RT_5: u32 = 0x05;
1779            #[doc = "RT*Prescaler period"]
1780            pub const RT_6: u32 = 0x06;
1781            #[doc = "RT*Prescaler period"]
1782            pub const RT_7: u32 = 0x07;
1783            #[doc = "RT*Prescaler period"]
1784            pub const RT_8: u32 = 0x08;
1785            #[doc = "RT*Prescaler period"]
1786            pub const RT_9: u32 = 0x09;
1787        }
1788    }
1789    #[doc = "Refresh urgent threshold"]
1790    pub mod UT {
1791        pub const offset: u32 = 24;
1792        pub const mask: u32 = 0xff << offset;
1793        pub mod R {}
1794        pub mod W {}
1795        pub mod RW {
1796            #[doc = "256*Prescaler period"]
1797            pub const UT_0: u32 = 0;
1798            #[doc = "UT*Prescaler period"]
1799            pub const UT_1: u32 = 0x01;
1800            #[doc = "UT*Prescaler period"]
1801            pub const UT_2: u32 = 0x02;
1802            #[doc = "UT*Prescaler period"]
1803            pub const UT_3: u32 = 0x03;
1804            #[doc = "UT*Prescaler period"]
1805            pub const UT_4: u32 = 0x04;
1806            #[doc = "UT*Prescaler period"]
1807            pub const UT_5: u32 = 0x05;
1808            #[doc = "UT*Prescaler period"]
1809            pub const UT_6: u32 = 0x06;
1810            #[doc = "UT*Prescaler period"]
1811            pub const UT_7: u32 = 0x07;
1812            #[doc = "UT*Prescaler period"]
1813            pub const UT_8: u32 = 0x08;
1814            #[doc = "UT*Prescaler period"]
1815            pub const UT_9: u32 = 0x09;
1816        }
1817    }
1818}
1819#[doc = "NAND control register 0"]
1820pub mod NANDCR0 {
1821    #[doc = "Port Size"]
1822    pub mod PS {
1823        pub const offset: u32 = 0;
1824        pub const mask: u32 = 0x01 << offset;
1825        pub mod R {}
1826        pub mod W {}
1827        pub mod RW {
1828            #[doc = "8bit"]
1829            pub const PS_0: u32 = 0;
1830            #[doc = "16bit"]
1831            pub const PS_1: u32 = 0x01;
1832        }
1833    }
1834    #[doc = "Select NAND controller mode."]
1835    pub mod SYNCEN {
1836        pub const offset: u32 = 1;
1837        pub const mask: u32 = 0x01 << offset;
1838        pub mod R {}
1839        pub mod W {}
1840        pub mod RW {
1841            #[doc = "Asynchronous mode is enabled."]
1842            pub const SYNCEN_0: u32 = 0;
1843            #[doc = "Synchronous mode is enabled."]
1844            pub const SYNCEN_1: u32 = 0x01;
1845        }
1846    }
1847    #[doc = "Burst Length"]
1848    pub mod BL {
1849        pub const offset: u32 = 4;
1850        pub const mask: u32 = 0x07 << offset;
1851        pub mod R {}
1852        pub mod W {}
1853        pub mod RW {
1854            #[doc = "1"]
1855            pub const BL_0: u32 = 0;
1856            #[doc = "2"]
1857            pub const BL_1: u32 = 0x01;
1858            #[doc = "4"]
1859            pub const BL_2: u32 = 0x02;
1860            #[doc = "8"]
1861            pub const BL_3: u32 = 0x03;
1862            #[doc = "16"]
1863            pub const BL_4: u32 = 0x04;
1864            #[doc = "32"]
1865            pub const BL_5: u32 = 0x05;
1866            #[doc = "64"]
1867            pub const BL_6: u32 = 0x06;
1868            #[doc = "64"]
1869            pub const BL_7: u32 = 0x07;
1870        }
1871    }
1872    #[doc = "EDO mode enabled"]
1873    pub mod EDO {
1874        pub const offset: u32 = 7;
1875        pub const mask: u32 = 0x01 << offset;
1876        pub mod R {}
1877        pub mod W {}
1878        pub mod RW {
1879            #[doc = "EDO mode disabled"]
1880            pub const EDO_0: u32 = 0;
1881            #[doc = "EDO mode enabled"]
1882            pub const EDO_1: u32 = 0x01;
1883        }
1884    }
1885    #[doc = "Column address bit number"]
1886    pub mod COL {
1887        pub const offset: u32 = 8;
1888        pub const mask: u32 = 0x07 << offset;
1889        pub mod R {}
1890        pub mod W {}
1891        pub mod RW {
1892            #[doc = "16"]
1893            pub const COL_0: u32 = 0;
1894            #[doc = "15"]
1895            pub const COL_1: u32 = 0x01;
1896            #[doc = "14"]
1897            pub const COL_2: u32 = 0x02;
1898            #[doc = "13"]
1899            pub const COL_3: u32 = 0x03;
1900            #[doc = "12"]
1901            pub const COL_4: u32 = 0x04;
1902            #[doc = "11"]
1903            pub const COL_5: u32 = 0x05;
1904            #[doc = "10"]
1905            pub const COL_6: u32 = 0x06;
1906            #[doc = "9"]
1907            pub const COL_7: u32 = 0x07;
1908        }
1909    }
1910}
1911#[doc = "NAND control register 1"]
1912pub mod NANDCR1 {
1913    #[doc = "CE setup time"]
1914    pub mod CES {
1915        pub const offset: u32 = 0;
1916        pub const mask: u32 = 0x0f << offset;
1917        pub mod R {}
1918        pub mod W {}
1919        pub mod RW {}
1920    }
1921    #[doc = "CE hold time"]
1922    pub mod CEH {
1923        pub const offset: u32 = 4;
1924        pub const mask: u32 = 0x0f << offset;
1925        pub mod R {}
1926        pub mod W {}
1927        pub mod RW {}
1928    }
1929    #[doc = "WE# LOW time"]
1930    pub mod WEL {
1931        pub const offset: u32 = 8;
1932        pub const mask: u32 = 0x0f << offset;
1933        pub mod R {}
1934        pub mod W {}
1935        pub mod RW {}
1936    }
1937    #[doc = "WE# HIGH time"]
1938    pub mod WEH {
1939        pub const offset: u32 = 12;
1940        pub const mask: u32 = 0x0f << offset;
1941        pub mod R {}
1942        pub mod W {}
1943        pub mod RW {}
1944    }
1945    #[doc = "RE# LOW time"]
1946    pub mod REL {
1947        pub const offset: u32 = 16;
1948        pub const mask: u32 = 0x0f << offset;
1949        pub mod R {}
1950        pub mod W {}
1951        pub mod RW {}
1952    }
1953    #[doc = "RE# HIGH time"]
1954    pub mod REH {
1955        pub const offset: u32 = 20;
1956        pub const mask: u32 = 0x0f << offset;
1957        pub mod R {}
1958        pub mod W {}
1959        pub mod RW {}
1960    }
1961    #[doc = "Turnaround time"]
1962    pub mod TA {
1963        pub const offset: u32 = 24;
1964        pub const mask: u32 = 0x0f << offset;
1965        pub mod R {}
1966        pub mod W {}
1967        pub mod RW {}
1968    }
1969    #[doc = "CE# interval time"]
1970    pub mod CEITV {
1971        pub const offset: u32 = 28;
1972        pub const mask: u32 = 0x0f << offset;
1973        pub mod R {}
1974        pub mod W {}
1975        pub mod RW {}
1976    }
1977}
1978#[doc = "NAND control register 2"]
1979pub mod NANDCR2 {
1980    #[doc = "WE# HIGH to RE# LOW wait time"]
1981    pub mod TWHR {
1982        pub const offset: u32 = 0;
1983        pub const mask: u32 = 0x3f << offset;
1984        pub mod R {}
1985        pub mod W {}
1986        pub mod RW {}
1987    }
1988    #[doc = "RE# HIGH to WE# LOW wait time"]
1989    pub mod TRHW {
1990        pub const offset: u32 = 6;
1991        pub const mask: u32 = 0x3f << offset;
1992        pub mod R {}
1993        pub mod W {}
1994        pub mod RW {}
1995    }
1996    #[doc = "ALE to WRITE Data start wait time"]
1997    pub mod TADL {
1998        pub const offset: u32 = 12;
1999        pub const mask: u32 = 0x3f << offset;
2000        pub mod R {}
2001        pub mod W {}
2002        pub mod RW {}
2003    }
2004    #[doc = "Ready to RE# LOW min wait time"]
2005    pub mod TRR {
2006        pub const offset: u32 = 18;
2007        pub const mask: u32 = 0x3f << offset;
2008        pub mod R {}
2009        pub mod W {}
2010        pub mod RW {}
2011    }
2012    #[doc = "WE# HIGH to busy wait time"]
2013    pub mod TWB {
2014        pub const offset: u32 = 24;
2015        pub const mask: u32 = 0x3f << offset;
2016        pub mod R {}
2017        pub mod W {}
2018        pub mod RW {}
2019    }
2020}
2021#[doc = "NAND control register 3"]
2022pub mod NANDCR3 {
2023    #[doc = "NAND option bit 1"]
2024    pub mod NDOPT1 {
2025        pub const offset: u32 = 0;
2026        pub const mask: u32 = 0x01 << offset;
2027        pub mod R {}
2028        pub mod W {}
2029        pub mod RW {}
2030    }
2031    #[doc = "NAND option bit 2"]
2032    pub mod NDOPT2 {
2033        pub const offset: u32 = 1;
2034        pub const mask: u32 = 0x01 << offset;
2035        pub mod R {}
2036        pub mod W {}
2037        pub mod RW {}
2038    }
2039    #[doc = "NAND option bit 3"]
2040    pub mod NDOPT3 {
2041        pub const offset: u32 = 2;
2042        pub const mask: u32 = 0x01 << offset;
2043        pub mod R {}
2044        pub mod W {}
2045        pub mod RW {}
2046    }
2047    #[doc = "NAND CLE Option"]
2048    pub mod CLE {
2049        pub const offset: u32 = 3;
2050        pub const mask: u32 = 0x01 << offset;
2051        pub mod R {}
2052        pub mod W {}
2053        pub mod RW {}
2054    }
2055    #[doc = "Read Data Setup cycle time."]
2056    pub mod RDS {
2057        pub const offset: u32 = 16;
2058        pub const mask: u32 = 0x0f << offset;
2059        pub mod R {}
2060        pub mod W {}
2061        pub mod RW {}
2062    }
2063    #[doc = "Read Data Hold cycle time."]
2064    pub mod RDH {
2065        pub const offset: u32 = 20;
2066        pub const mask: u32 = 0x0f << offset;
2067        pub mod R {}
2068        pub mod W {}
2069        pub mod RW {}
2070    }
2071    #[doc = "Write Data Setup cycle time."]
2072    pub mod WDS {
2073        pub const offset: u32 = 24;
2074        pub const mask: u32 = 0x0f << offset;
2075        pub mod R {}
2076        pub mod W {}
2077        pub mod RW {}
2078    }
2079    #[doc = "Write Data Hold cycle time."]
2080    pub mod WDH {
2081        pub const offset: u32 = 28;
2082        pub const mask: u32 = 0x0f << offset;
2083        pub mod R {}
2084        pub mod W {}
2085        pub mod RW {}
2086    }
2087}
2088#[doc = "NOR control register 0"]
2089pub mod NORCR0 {
2090    #[doc = "Port Size"]
2091    pub mod PS {
2092        pub const offset: u32 = 0;
2093        pub const mask: u32 = 0x01 << offset;
2094        pub mod R {}
2095        pub mod W {}
2096        pub mod RW {
2097            #[doc = "8bit"]
2098            pub const PS_0: u32 = 0;
2099            #[doc = "16bit"]
2100            pub const PS_1: u32 = 0x01;
2101        }
2102    }
2103    #[doc = "Select NOR controller mode."]
2104    pub mod SYNCEN {
2105        pub const offset: u32 = 1;
2106        pub const mask: u32 = 0x01 << offset;
2107        pub mod R {}
2108        pub mod W {}
2109        pub mod RW {
2110            #[doc = "Asynchronous mode is enabled."]
2111            pub const SYNCEN_0: u32 = 0;
2112            #[doc = "Synchronous mode is enabled."]
2113            pub const SYNCEN_1: u32 = 0x01;
2114        }
2115    }
2116    #[doc = "Burst Length"]
2117    pub mod BL {
2118        pub const offset: u32 = 4;
2119        pub const mask: u32 = 0x07 << offset;
2120        pub mod R {}
2121        pub mod W {}
2122        pub mod RW {
2123            #[doc = "1"]
2124            pub const BL_0: u32 = 0;
2125            #[doc = "2"]
2126            pub const BL_1: u32 = 0x01;
2127            #[doc = "4"]
2128            pub const BL_2: u32 = 0x02;
2129            #[doc = "8"]
2130            pub const BL_3: u32 = 0x03;
2131            #[doc = "16"]
2132            pub const BL_4: u32 = 0x04;
2133            #[doc = "32"]
2134            pub const BL_5: u32 = 0x05;
2135            #[doc = "64"]
2136            pub const BL_6: u32 = 0x06;
2137            #[doc = "64"]
2138            pub const BL_7: u32 = 0x07;
2139        }
2140    }
2141    #[doc = "Address Mode"]
2142    pub mod AM {
2143        pub const offset: u32 = 8;
2144        pub const mask: u32 = 0x03 << offset;
2145        pub mod R {}
2146        pub mod W {}
2147        pub mod RW {
2148            #[doc = "Address/Data MUX mode"]
2149            pub const AM_0: u32 = 0;
2150            #[doc = "Advanced Address/Data MUX mode"]
2151            pub const AM_1: u32 = 0x01;
2152            #[doc = "Address/Data non-MUX mode"]
2153            pub const AM_2: u32 = 0x02;
2154            #[doc = "Address/Data non-MUX mode"]
2155            pub const AM_3: u32 = 0x03;
2156        }
2157    }
2158    #[doc = "ADV# polarity"]
2159    pub mod ADVP {
2160        pub const offset: u32 = 10;
2161        pub const mask: u32 = 0x01 << offset;
2162        pub mod R {}
2163        pub mod W {}
2164        pub mod RW {
2165            #[doc = "ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW."]
2166            pub const ADVP_0: u32 = 0;
2167            #[doc = "ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH."]
2168            pub const ADVP_1: u32 = 0x01;
2169        }
2170    }
2171    #[doc = "ADV# level control during address hold state"]
2172    pub mod ADVH {
2173        pub const offset: u32 = 11;
2174        pub const mask: u32 = 0x01 << offset;
2175        pub mod R {}
2176        pub mod W {}
2177        pub mod RW {
2178            #[doc = "ADV# is high during address hold state."]
2179            pub const ADVH_0: u32 = 0;
2180            #[doc = "ADV# is low during address hold state."]
2181            pub const ADVH_1: u32 = 0x01;
2182        }
2183    }
2184    #[doc = "Column Address bit width"]
2185    pub mod COL {
2186        pub const offset: u32 = 12;
2187        pub const mask: u32 = 0x0f << offset;
2188        pub mod R {}
2189        pub mod W {}
2190        pub mod RW {
2191            #[doc = "12 Bits"]
2192            pub const COL_0: u32 = 0;
2193            #[doc = "11 Bits"]
2194            pub const COL_1: u32 = 0x01;
2195            #[doc = "10 Bits"]
2196            pub const COL_2: u32 = 0x02;
2197            #[doc = "9 Bits"]
2198            pub const COL_3: u32 = 0x03;
2199            #[doc = "8 Bits"]
2200            pub const COL_4: u32 = 0x04;
2201            #[doc = "7 Bits"]
2202            pub const COL_5: u32 = 0x05;
2203            #[doc = "6 Bits"]
2204            pub const COL_6: u32 = 0x06;
2205            #[doc = "5 Bits"]
2206            pub const COL_7: u32 = 0x07;
2207            #[doc = "4 Bits"]
2208            pub const COL_8: u32 = 0x08;
2209            #[doc = "3 Bits"]
2210            pub const COL_9: u32 = 0x09;
2211            #[doc = "2 Bits"]
2212            pub const COL_10: u32 = 0x0a;
2213            #[doc = "12 Bits"]
2214            pub const COL_11: u32 = 0x0b;
2215            #[doc = "12 Bits"]
2216            pub const COL_12: u32 = 0x0c;
2217            #[doc = "12 Bits"]
2218            pub const COL_13: u32 = 0x0d;
2219            #[doc = "12 Bits"]
2220            pub const COL_14: u32 = 0x0e;
2221            #[doc = "12 Bits"]
2222            pub const COL_15: u32 = 0x0f;
2223        }
2224    }
2225}
2226#[doc = "NOR control register 1"]
2227pub mod NORCR1 {
2228    #[doc = "CE setup time cycle"]
2229    pub mod CES {
2230        pub const offset: u32 = 0;
2231        pub const mask: u32 = 0x0f << offset;
2232        pub mod R {}
2233        pub mod W {}
2234        pub mod RW {}
2235    }
2236    #[doc = "CE hold min time (CEH+1) cycle"]
2237    pub mod CEH {
2238        pub const offset: u32 = 4;
2239        pub const mask: u32 = 0x0f << offset;
2240        pub mod R {}
2241        pub mod W {}
2242        pub mod RW {}
2243    }
2244    #[doc = "Address setup time"]
2245    pub mod AS {
2246        pub const offset: u32 = 8;
2247        pub const mask: u32 = 0x0f << offset;
2248        pub mod R {}
2249        pub mod W {}
2250        pub mod RW {}
2251    }
2252    #[doc = "Address hold time"]
2253    pub mod AH {
2254        pub const offset: u32 = 12;
2255        pub const mask: u32 = 0x0f << offset;
2256        pub mod R {}
2257        pub mod W {}
2258        pub mod RW {}
2259    }
2260    #[doc = "WE LOW time (WEL+1) cycle"]
2261    pub mod WEL {
2262        pub const offset: u32 = 16;
2263        pub const mask: u32 = 0x0f << offset;
2264        pub mod R {}
2265        pub mod W {}
2266        pub mod RW {}
2267    }
2268    #[doc = "WE HIGH time (WEH+1) cycle"]
2269    pub mod WEH {
2270        pub const offset: u32 = 20;
2271        pub const mask: u32 = 0x0f << offset;
2272        pub mod R {}
2273        pub mod W {}
2274        pub mod RW {}
2275    }
2276    #[doc = "RE LOW time (REL+1) cycle"]
2277    pub mod REL {
2278        pub const offset: u32 = 24;
2279        pub const mask: u32 = 0x0f << offset;
2280        pub mod R {}
2281        pub mod W {}
2282        pub mod RW {}
2283    }
2284    #[doc = "RE HIGH time (REH+1) cycle"]
2285    pub mod REH {
2286        pub const offset: u32 = 28;
2287        pub const mask: u32 = 0x0f << offset;
2288        pub mod R {}
2289        pub mod W {}
2290        pub mod RW {}
2291    }
2292}
2293#[doc = "NOR control register 2"]
2294pub mod NORCR2 {
2295    #[doc = "Turnaround time cycle"]
2296    pub mod TA {
2297        pub const offset: u32 = 8;
2298        pub const mask: u32 = 0x0f << offset;
2299        pub mod R {}
2300        pub mod W {}
2301        pub mod RW {}
2302    }
2303    #[doc = "Address to write data hold time cycle"]
2304    pub mod AWDH {
2305        pub const offset: u32 = 12;
2306        pub const mask: u32 = 0x0f << offset;
2307        pub mod R {}
2308        pub mod W {}
2309        pub mod RW {}
2310    }
2311    #[doc = "Latency count"]
2312    pub mod LC {
2313        pub const offset: u32 = 16;
2314        pub const mask: u32 = 0x0f << offset;
2315        pub mod R {}
2316        pub mod W {}
2317        pub mod RW {}
2318    }
2319    #[doc = "Read cycle time"]
2320    pub mod RD {
2321        pub const offset: u32 = 20;
2322        pub const mask: u32 = 0x0f << offset;
2323        pub mod R {}
2324        pub mod W {}
2325        pub mod RW {}
2326    }
2327    #[doc = "CE# interval min time"]
2328    pub mod CEITV {
2329        pub const offset: u32 = 24;
2330        pub const mask: u32 = 0x0f << offset;
2331        pub mod R {}
2332        pub mod W {}
2333        pub mod RW {}
2334    }
2335    #[doc = "Read cycle hold time"]
2336    pub mod RDH {
2337        pub const offset: u32 = 28;
2338        pub const mask: u32 = 0x0f << offset;
2339        pub mod R {}
2340        pub mod W {}
2341        pub mod RW {}
2342    }
2343}
2344#[doc = "NOR control register 3"]
2345pub mod NORCR3 {
2346    #[doc = "Address setup time for synchronous read"]
2347    pub mod ASSR {
2348        pub const offset: u32 = 0;
2349        pub const mask: u32 = 0x0f << offset;
2350        pub mod R {}
2351        pub mod W {}
2352        pub mod RW {}
2353    }
2354    #[doc = "Address hold time for synchronous read"]
2355    pub mod AHSR {
2356        pub const offset: u32 = 4;
2357        pub const mask: u32 = 0x0f << offset;
2358        pub mod R {}
2359        pub mod W {}
2360        pub mod RW {}
2361    }
2362}
2363#[doc = "SRAM control register 0"]
2364pub mod SRAMCR0 {
2365    #[doc = "Port Size"]
2366    pub mod PS {
2367        pub const offset: u32 = 0;
2368        pub const mask: u32 = 0x01 << offset;
2369        pub mod R {}
2370        pub mod W {}
2371        pub mod RW {
2372            #[doc = "8bit"]
2373            pub const PS_0: u32 = 0;
2374            #[doc = "16bit"]
2375            pub const PS_1: u32 = 0x01;
2376        }
2377    }
2378    #[doc = "Select SRAM controller mode."]
2379    pub mod SYNCEN {
2380        pub const offset: u32 = 1;
2381        pub const mask: u32 = 0x01 << offset;
2382        pub mod R {}
2383        pub mod W {}
2384        pub mod RW {
2385            #[doc = "Asynchronous mode is enabled."]
2386            pub const SYNCEN_0: u32 = 0;
2387            #[doc = "Synchronous mode is enabled."]
2388            pub const SYNCEN_1: u32 = 0x01;
2389        }
2390    }
2391    #[doc = "Burst Length"]
2392    pub mod BL {
2393        pub const offset: u32 = 4;
2394        pub const mask: u32 = 0x07 << offset;
2395        pub mod R {}
2396        pub mod W {}
2397        pub mod RW {
2398            #[doc = "1"]
2399            pub const BL_0: u32 = 0;
2400            #[doc = "2"]
2401            pub const BL_1: u32 = 0x01;
2402            #[doc = "4"]
2403            pub const BL_2: u32 = 0x02;
2404            #[doc = "8"]
2405            pub const BL_3: u32 = 0x03;
2406            #[doc = "16"]
2407            pub const BL_4: u32 = 0x04;
2408            #[doc = "32"]
2409            pub const BL_5: u32 = 0x05;
2410            #[doc = "64"]
2411            pub const BL_6: u32 = 0x06;
2412            #[doc = "64"]
2413            pub const BL_7: u32 = 0x07;
2414        }
2415    }
2416    #[doc = "Address Mode"]
2417    pub mod AM {
2418        pub const offset: u32 = 8;
2419        pub const mask: u32 = 0x03 << offset;
2420        pub mod R {}
2421        pub mod W {}
2422        pub mod RW {
2423            #[doc = "Address/Data MUX mode"]
2424            pub const AM_0: u32 = 0;
2425            #[doc = "Advanced Address/Data MUX mode"]
2426            pub const AM_1: u32 = 0x01;
2427            #[doc = "Address/Data non-MUX mode"]
2428            pub const AM_2: u32 = 0x02;
2429            #[doc = "Address/Data non-MUX mode"]
2430            pub const AM_3: u32 = 0x03;
2431        }
2432    }
2433    #[doc = "ADV# polarity"]
2434    pub mod ADVP {
2435        pub const offset: u32 = 10;
2436        pub const mask: u32 = 0x01 << offset;
2437        pub mod R {}
2438        pub mod W {}
2439        pub mod RW {
2440            #[doc = "ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW."]
2441            pub const ADVP_0: u32 = 0;
2442            #[doc = "ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH."]
2443            pub const ADVP_1: u32 = 0x01;
2444        }
2445    }
2446    #[doc = "ADV# level control during address hold state"]
2447    pub mod ADVH {
2448        pub const offset: u32 = 11;
2449        pub const mask: u32 = 0x01 << offset;
2450        pub mod R {}
2451        pub mod W {}
2452        pub mod RW {
2453            #[doc = "ADV# is high during address hold state."]
2454            pub const ADVH_0: u32 = 0;
2455            #[doc = "ADV# is low during address hold state."]
2456            pub const ADVH_1: u32 = 0x01;
2457        }
2458    }
2459    #[doc = "Column Address bit width"]
2460    pub mod COL {
2461        pub const offset: u32 = 12;
2462        pub const mask: u32 = 0x0f << offset;
2463        pub mod R {}
2464        pub mod W {}
2465        pub mod RW {
2466            #[doc = "12 Bits"]
2467            pub const COL_0: u32 = 0;
2468            #[doc = "11 Bits"]
2469            pub const COL_1: u32 = 0x01;
2470            #[doc = "10 Bits"]
2471            pub const COL_2: u32 = 0x02;
2472            #[doc = "9 Bits"]
2473            pub const COL_3: u32 = 0x03;
2474            #[doc = "8 Bits"]
2475            pub const COL_4: u32 = 0x04;
2476            #[doc = "7 Bits"]
2477            pub const COL_5: u32 = 0x05;
2478            #[doc = "6 Bits"]
2479            pub const COL_6: u32 = 0x06;
2480            #[doc = "5 Bits"]
2481            pub const COL_7: u32 = 0x07;
2482            #[doc = "4 Bits"]
2483            pub const COL_8: u32 = 0x08;
2484            #[doc = "3 Bits"]
2485            pub const COL_9: u32 = 0x09;
2486            #[doc = "2 Bits"]
2487            pub const COL_10: u32 = 0x0a;
2488            #[doc = "12 Bits"]
2489            pub const COL_11: u32 = 0x0b;
2490            #[doc = "12 Bits"]
2491            pub const COL_12: u32 = 0x0c;
2492            #[doc = "12 Bits"]
2493            pub const COL_13: u32 = 0x0d;
2494            #[doc = "12 Bits"]
2495            pub const COL_14: u32 = 0x0e;
2496            #[doc = "12 Bits"]
2497            pub const COL_15: u32 = 0x0f;
2498        }
2499    }
2500}
2501#[doc = "SRAM control register 1"]
2502pub mod SRAMCR1 {
2503    #[doc = "CE setup time cycle"]
2504    pub mod CES {
2505        pub const offset: u32 = 0;
2506        pub const mask: u32 = 0x0f << offset;
2507        pub mod R {}
2508        pub mod W {}
2509        pub mod RW {}
2510    }
2511    #[doc = "CE hold min time (CEH+1) cycle"]
2512    pub mod CEH {
2513        pub const offset: u32 = 4;
2514        pub const mask: u32 = 0x0f << offset;
2515        pub mod R {}
2516        pub mod W {}
2517        pub mod RW {}
2518    }
2519    #[doc = "Address setup time"]
2520    pub mod AS {
2521        pub const offset: u32 = 8;
2522        pub const mask: u32 = 0x0f << offset;
2523        pub mod R {}
2524        pub mod W {}
2525        pub mod RW {}
2526    }
2527    #[doc = "Address hold time"]
2528    pub mod AH {
2529        pub const offset: u32 = 12;
2530        pub const mask: u32 = 0x0f << offset;
2531        pub mod R {}
2532        pub mod W {}
2533        pub mod RW {}
2534    }
2535    #[doc = "WE LOW time (WEL+1) cycle"]
2536    pub mod WEL {
2537        pub const offset: u32 = 16;
2538        pub const mask: u32 = 0x0f << offset;
2539        pub mod R {}
2540        pub mod W {}
2541        pub mod RW {}
2542    }
2543    #[doc = "WE HIGH time (WEH+1) cycle"]
2544    pub mod WEH {
2545        pub const offset: u32 = 20;
2546        pub const mask: u32 = 0x0f << offset;
2547        pub mod R {}
2548        pub mod W {}
2549        pub mod RW {}
2550    }
2551    #[doc = "RE LOW time (REL+1) cycle"]
2552    pub mod REL {
2553        pub const offset: u32 = 24;
2554        pub const mask: u32 = 0x0f << offset;
2555        pub mod R {}
2556        pub mod W {}
2557        pub mod RW {}
2558    }
2559    #[doc = "RE HIGH time (REH+1) cycle"]
2560    pub mod REH {
2561        pub const offset: u32 = 28;
2562        pub const mask: u32 = 0x0f << offset;
2563        pub mod R {}
2564        pub mod W {}
2565        pub mod RW {}
2566    }
2567}
2568#[doc = "SRAM control register 2"]
2569pub mod SRAMCR2 {
2570    #[doc = "Write Data setup time (WDS+1) cycle"]
2571    pub mod WDS {
2572        pub const offset: u32 = 0;
2573        pub const mask: u32 = 0x0f << offset;
2574        pub mod R {}
2575        pub mod W {}
2576        pub mod RW {}
2577    }
2578    #[doc = "Write Data hold time WDH cycle"]
2579    pub mod WDH {
2580        pub const offset: u32 = 4;
2581        pub const mask: u32 = 0x0f << offset;
2582        pub mod R {}
2583        pub mod W {}
2584        pub mod RW {}
2585    }
2586    #[doc = "Turnaround time cycle"]
2587    pub mod TA {
2588        pub const offset: u32 = 8;
2589        pub const mask: u32 = 0x0f << offset;
2590        pub mod R {}
2591        pub mod W {}
2592        pub mod RW {}
2593    }
2594    #[doc = "Address to write data hold time cycle"]
2595    pub mod AWDH {
2596        pub const offset: u32 = 12;
2597        pub const mask: u32 = 0x0f << offset;
2598        pub mod R {}
2599        pub mod W {}
2600        pub mod RW {}
2601    }
2602    #[doc = "Latency count"]
2603    pub mod LC {
2604        pub const offset: u32 = 16;
2605        pub const mask: u32 = 0x0f << offset;
2606        pub mod R {}
2607        pub mod W {}
2608        pub mod RW {}
2609    }
2610    #[doc = "Read cycle time"]
2611    pub mod RD {
2612        pub const offset: u32 = 20;
2613        pub const mask: u32 = 0x0f << offset;
2614        pub mod R {}
2615        pub mod W {}
2616        pub mod RW {}
2617    }
2618    #[doc = "CE# interval min time"]
2619    pub mod CEITV {
2620        pub const offset: u32 = 24;
2621        pub const mask: u32 = 0x0f << offset;
2622        pub mod R {}
2623        pub mod W {}
2624        pub mod RW {}
2625    }
2626    #[doc = "Read cycle hold time"]
2627    pub mod RDH {
2628        pub const offset: u32 = 28;
2629        pub const mask: u32 = 0x0f << offset;
2630        pub mod R {}
2631        pub mod W {}
2632        pub mod RW {}
2633    }
2634}
2635#[doc = "DBI-B control register 0"]
2636pub mod DBICR0 {
2637    #[doc = "Port Size"]
2638    pub mod PS {
2639        pub const offset: u32 = 0;
2640        pub const mask: u32 = 0x01 << offset;
2641        pub mod R {}
2642        pub mod W {}
2643        pub mod RW {
2644            #[doc = "8bit"]
2645            pub const PS_0: u32 = 0;
2646            #[doc = "16bit"]
2647            pub const PS_1: u32 = 0x01;
2648        }
2649    }
2650    #[doc = "Burst Length"]
2651    pub mod BL {
2652        pub const offset: u32 = 4;
2653        pub const mask: u32 = 0x07 << offset;
2654        pub mod R {}
2655        pub mod W {}
2656        pub mod RW {
2657            #[doc = "1"]
2658            pub const BL_0: u32 = 0;
2659            #[doc = "2"]
2660            pub const BL_1: u32 = 0x01;
2661            #[doc = "4"]
2662            pub const BL_2: u32 = 0x02;
2663            #[doc = "8"]
2664            pub const BL_3: u32 = 0x03;
2665            #[doc = "16"]
2666            pub const BL_4: u32 = 0x04;
2667            #[doc = "32"]
2668            pub const BL_5: u32 = 0x05;
2669            #[doc = "64"]
2670            pub const BL_6: u32 = 0x06;
2671            #[doc = "64"]
2672            pub const BL_7: u32 = 0x07;
2673        }
2674    }
2675    #[doc = "Column Address bit width"]
2676    pub mod COL {
2677        pub const offset: u32 = 12;
2678        pub const mask: u32 = 0x0f << offset;
2679        pub mod R {}
2680        pub mod W {}
2681        pub mod RW {
2682            #[doc = "12 Bits"]
2683            pub const COL_0: u32 = 0;
2684            #[doc = "11 Bits"]
2685            pub const COL_1: u32 = 0x01;
2686            #[doc = "10 Bits"]
2687            pub const COL_2: u32 = 0x02;
2688            #[doc = "9 Bits"]
2689            pub const COL_3: u32 = 0x03;
2690            #[doc = "8 Bits"]
2691            pub const COL_4: u32 = 0x04;
2692            #[doc = "7 Bits"]
2693            pub const COL_5: u32 = 0x05;
2694            #[doc = "6 Bits"]
2695            pub const COL_6: u32 = 0x06;
2696            #[doc = "5 Bits"]
2697            pub const COL_7: u32 = 0x07;
2698            #[doc = "4 Bits"]
2699            pub const COL_8: u32 = 0x08;
2700            #[doc = "3 Bits"]
2701            pub const COL_9: u32 = 0x09;
2702            #[doc = "2 Bits"]
2703            pub const COL_10: u32 = 0x0a;
2704            #[doc = "12 Bits"]
2705            pub const COL_11: u32 = 0x0b;
2706            #[doc = "12 Bits"]
2707            pub const COL_12: u32 = 0x0c;
2708            #[doc = "12 Bits"]
2709            pub const COL_13: u32 = 0x0d;
2710            #[doc = "12 Bits"]
2711            pub const COL_14: u32 = 0x0e;
2712            #[doc = "12 Bits"]
2713            pub const COL_15: u32 = 0x0f;
2714        }
2715    }
2716}
2717#[doc = "DBI-B control register 1"]
2718pub mod DBICR1 {
2719    #[doc = "CSX Setup Time"]
2720    pub mod CES {
2721        pub const offset: u32 = 0;
2722        pub const mask: u32 = 0x0f << offset;
2723        pub mod R {}
2724        pub mod W {}
2725        pub mod RW {}
2726    }
2727    #[doc = "CSX Hold Time"]
2728    pub mod CEH {
2729        pub const offset: u32 = 4;
2730        pub const mask: u32 = 0x0f << offset;
2731        pub mod R {}
2732        pub mod W {}
2733        pub mod RW {}
2734    }
2735    #[doc = "WRX Low Time"]
2736    pub mod WEL {
2737        pub const offset: u32 = 8;
2738        pub const mask: u32 = 0x0f << offset;
2739        pub mod R {}
2740        pub mod W {}
2741        pub mod RW {}
2742    }
2743    #[doc = "WRX High Time"]
2744    pub mod WEH {
2745        pub const offset: u32 = 12;
2746        pub const mask: u32 = 0x0f << offset;
2747        pub mod R {}
2748        pub mod W {}
2749        pub mod RW {}
2750    }
2751    #[doc = "RDX Low Time"]
2752    pub mod REL {
2753        pub const offset: u32 = 16;
2754        pub const mask: u32 = 0x3f << offset;
2755        pub mod R {}
2756        pub mod W {}
2757        pub mod RW {}
2758    }
2759    #[doc = "RDX High Time"]
2760    pub mod REH {
2761        pub const offset: u32 = 22;
2762        pub const mask: u32 = 0x3f << offset;
2763        pub mod R {}
2764        pub mod W {}
2765        pub mod RW {}
2766    }
2767    #[doc = "CSX interval min time"]
2768    pub mod CEITV {
2769        pub const offset: u32 = 28;
2770        pub const mask: u32 = 0x0f << offset;
2771        pub mod R {}
2772        pub mod W {}
2773        pub mod RW {}
2774    }
2775}
2776#[doc = "IP Command control register 0"]
2777pub mod IPCR0 {
2778    #[doc = "Slave address"]
2779    pub mod SA {
2780        pub const offset: u32 = 0;
2781        pub const mask: u32 = 0xffff_ffff << offset;
2782        pub mod R {}
2783        pub mod W {}
2784        pub mod RW {}
2785    }
2786}
2787#[doc = "IP Command control register 1"]
2788pub mod IPCR1 {
2789    #[doc = "Data Size in Byte"]
2790    pub mod DATSZ {
2791        pub const offset: u32 = 0;
2792        pub const mask: u32 = 0x07 << offset;
2793        pub mod R {}
2794        pub mod W {}
2795        pub mod RW {
2796            #[doc = "4"]
2797            pub const DATSZ_0: u32 = 0;
2798            #[doc = "1"]
2799            pub const DATSZ_1: u32 = 0x01;
2800            #[doc = "2"]
2801            pub const DATSZ_2: u32 = 0x02;
2802            #[doc = "3"]
2803            pub const DATSZ_3: u32 = 0x03;
2804            #[doc = "4"]
2805            pub const DATSZ_4: u32 = 0x04;
2806            #[doc = "4"]
2807            pub const DATSZ_5: u32 = 0x05;
2808            #[doc = "4"]
2809            pub const DATSZ_6: u32 = 0x06;
2810            #[doc = "4"]
2811            pub const DATSZ_7: u32 = 0x07;
2812        }
2813    }
2814    #[doc = "NAND Extended Address"]
2815    pub mod NAND_EXT_ADDR {
2816        pub const offset: u32 = 8;
2817        pub const mask: u32 = 0xff << offset;
2818        pub mod R {}
2819        pub mod W {}
2820        pub mod RW {}
2821    }
2822}
2823#[doc = "IP Command control register 2"]
2824pub mod IPCR2 {
2825    #[doc = "Byte Mask for Byte 0 (IPTXD bit 7:0)"]
2826    pub mod BM0 {
2827        pub const offset: u32 = 0;
2828        pub const mask: u32 = 0x01 << offset;
2829        pub mod R {}
2830        pub mod W {}
2831        pub mod RW {
2832            #[doc = "Byte Unmasked"]
2833            pub const BM0_0: u32 = 0;
2834            #[doc = "Byte Masked"]
2835            pub const BM0_1: u32 = 0x01;
2836        }
2837    }
2838    #[doc = "Byte Mask for Byte 1 (IPTXD bit 15:8)"]
2839    pub mod BM1 {
2840        pub const offset: u32 = 1;
2841        pub const mask: u32 = 0x01 << offset;
2842        pub mod R {}
2843        pub mod W {}
2844        pub mod RW {
2845            #[doc = "Byte Unmasked"]
2846            pub const BM1_0: u32 = 0;
2847            #[doc = "Byte Masked"]
2848            pub const BM1_1: u32 = 0x01;
2849        }
2850    }
2851    #[doc = "Byte Mask for Byte 2 (IPTXD bit 23:16)"]
2852    pub mod BM2 {
2853        pub const offset: u32 = 2;
2854        pub const mask: u32 = 0x01 << offset;
2855        pub mod R {}
2856        pub mod W {}
2857        pub mod RW {
2858            #[doc = "Byte Unmasked"]
2859            pub const BM2_0: u32 = 0;
2860            #[doc = "Byte Masked"]
2861            pub const BM2_1: u32 = 0x01;
2862        }
2863    }
2864    #[doc = "Byte Mask for Byte 3 (IPTXD bit 31:24)"]
2865    pub mod BM3 {
2866        pub const offset: u32 = 3;
2867        pub const mask: u32 = 0x01 << offset;
2868        pub mod R {}
2869        pub mod W {}
2870        pub mod RW {
2871            #[doc = "Byte Unmasked"]
2872            pub const BM3_0: u32 = 0;
2873            #[doc = "Byte Masked"]
2874            pub const BM3_1: u32 = 0x01;
2875        }
2876    }
2877}
2878#[doc = "IP Command register"]
2879pub mod IPCMD {
2880    #[doc = "SDRAM Commands: 0x8: READ 0x9: WRITE 0xA: MODESET 0xB: ACTIVE 0xC: AUTO REFRESH 0xD: SELF REFRESH 0xE: PRECHARGE 0xF: PRECHARGE ALL Others: RSVD SELF REFRESH will be sent to all SDRAM devices because they shared same SEMC_CLK pin"]
2881    pub mod CMD {
2882        pub const offset: u32 = 0;
2883        pub const mask: u32 = 0xffff << offset;
2884        pub mod R {}
2885        pub mod W {}
2886        pub mod RW {}
2887    }
2888    #[doc = "This field should be written with 0xA55A when trigging an IP command."]
2889    pub mod KEY {
2890        pub const offset: u32 = 16;
2891        pub const mask: u32 = 0xffff << offset;
2892        pub mod R {}
2893        pub mod W {}
2894        pub mod RW {}
2895    }
2896}
2897#[doc = "TX DATA register (for IP Command)"]
2898pub mod IPTXDAT {
2899    #[doc = "no description available"]
2900    pub mod DAT {
2901        pub const offset: u32 = 0;
2902        pub const mask: u32 = 0xffff_ffff << offset;
2903        pub mod R {}
2904        pub mod W {}
2905        pub mod RW {}
2906    }
2907}
2908#[doc = "RX DATA register (for IP Command)"]
2909pub mod IPRXDAT {
2910    #[doc = "no description available"]
2911    pub mod DAT {
2912        pub const offset: u32 = 0;
2913        pub const mask: u32 = 0xffff_ffff << offset;
2914        pub mod R {}
2915        pub mod W {}
2916        pub mod RW {}
2917    }
2918}
2919#[doc = "Status register 0"]
2920pub mod STS0 {
2921    #[doc = "Indicating whether SEMC is in IDLE state."]
2922    pub mod IDLE {
2923        pub const offset: u32 = 0;
2924        pub const mask: u32 = 0x01 << offset;
2925        pub mod R {}
2926        pub mod W {}
2927        pub mod RW {}
2928    }
2929    #[doc = "Indicating NAND device Ready/WAIT# pin level."]
2930    pub mod NARDY {
2931        pub const offset: u32 = 1;
2932        pub const mask: u32 = 0x01 << offset;
2933        pub mod R {}
2934        pub mod W {}
2935        pub mod RW {
2936            #[doc = "NAND device is not ready"]
2937            pub const NARDY_0: u32 = 0;
2938            #[doc = "NAND device is ready"]
2939            pub const NARDY_1: u32 = 0x01;
2940        }
2941    }
2942}
2943#[doc = "Status register 2"]
2944pub mod STS2 {
2945    #[doc = "This field indicating whether there is pending AXI command (write) to NAND device."]
2946    pub mod NDWRPEND {
2947        pub const offset: u32 = 3;
2948        pub const mask: u32 = 0x01 << offset;
2949        pub mod R {}
2950        pub mod W {}
2951        pub mod RW {
2952            #[doc = "No pending"]
2953            pub const NDWRPEND_0: u32 = 0;
2954            #[doc = "Pending"]
2955            pub const NDWRPEND_1: u32 = 0x01;
2956        }
2957    }
2958}
2959#[doc = "Status register 12"]
2960pub mod STS12 {
2961    #[doc = "This field indicating the last write address (AXI command) to NAND device (without base address in SEMC_BR4)."]
2962    pub mod NDADDR {
2963        pub const offset: u32 = 0;
2964        pub const mask: u32 = 0xffff_ffff << offset;
2965        pub mod R {}
2966        pub mod W {}
2967        pub mod RW {}
2968    }
2969}
2970#[doc = "Status register 13"]
2971pub mod STS13 {
2972    #[doc = "Sample clock slave delay line locked."]
2973    pub mod SLVLOCK {
2974        pub const offset: u32 = 0;
2975        pub const mask: u32 = 0x01 << offset;
2976        pub mod R {}
2977        pub mod W {}
2978        pub mod RW {}
2979    }
2980    #[doc = "Sample clock reference delay line locked."]
2981    pub mod REFLOCK {
2982        pub const offset: u32 = 1;
2983        pub const mask: u32 = 0x01 << offset;
2984        pub mod R {}
2985        pub mod W {}
2986        pub mod RW {}
2987    }
2988    #[doc = "Sample clock slave delay line delay cell number selection ."]
2989    pub mod SLVSEL {
2990        pub const offset: u32 = 2;
2991        pub const mask: u32 = 0x3f << offset;
2992        pub mod R {}
2993        pub mod W {}
2994        pub mod RW {}
2995    }
2996    #[doc = "Sample clock reference delay line delay cell number selection."]
2997    pub mod REFSEL {
2998        pub const offset: u32 = 8;
2999        pub const mask: u32 = 0x3f << offset;
3000        pub mod R {}
3001        pub mod W {}
3002        pub mod RW {}
3003    }
3004}