1#[doc = "LCDIF Register Reference Index"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "LCDIF General Control Register"]
5 pub CTRL: crate::RWRegister<u32>,
6 #[doc = "LCDIF General Control Register"]
7 pub CTRL_SET: crate::RWRegister<u32>,
8 #[doc = "LCDIF General Control Register"]
9 pub CTRL_CLR: crate::RWRegister<u32>,
10 #[doc = "LCDIF General Control Register"]
11 pub CTRL_TOG: crate::RWRegister<u32>,
12 #[doc = "LCDIF General Control1 Register"]
13 pub CTRL1: crate::RWRegister<u32>,
14 #[doc = "LCDIF General Control1 Register"]
15 pub CTRL1_SET: crate::RWRegister<u32>,
16 #[doc = "LCDIF General Control1 Register"]
17 pub CTRL1_CLR: crate::RWRegister<u32>,
18 #[doc = "LCDIF General Control1 Register"]
19 pub CTRL1_TOG: crate::RWRegister<u32>,
20 #[doc = "LCDIF General Control2 Register"]
21 pub CTRL2: crate::RWRegister<u32>,
22 #[doc = "LCDIF General Control2 Register"]
23 pub CTRL2_SET: crate::RWRegister<u32>,
24 #[doc = "LCDIF General Control2 Register"]
25 pub CTRL2_CLR: crate::RWRegister<u32>,
26 #[doc = "LCDIF General Control2 Register"]
27 pub CTRL2_TOG: crate::RWRegister<u32>,
28 #[doc = "LCDIF Horizontal and Vertical Valid Data Count Register"]
29 pub TRANSFER_COUNT: crate::RWRegister<u32>,
30 _reserved0: [u8; 0x0c],
31 #[doc = "LCD Interface Current Buffer Address Register"]
32 pub CUR_BUF: crate::RWRegister<u32>,
33 _reserved1: [u8; 0x0c],
34 #[doc = "LCD Interface Next Buffer Address Register"]
35 pub NEXT_BUF: crate::RWRegister<u32>,
36 _reserved2: [u8; 0x1c],
37 #[doc = "LCDIF VSYNC Mode and Dotclk Mode Control Register0"]
38 pub VDCTRL0: crate::RWRegister<u32>,
39 #[doc = "LCDIF VSYNC Mode and Dotclk Mode Control Register0"]
40 pub VDCTRL0_SET: crate::RWRegister<u32>,
41 #[doc = "LCDIF VSYNC Mode and Dotclk Mode Control Register0"]
42 pub VDCTRL0_CLR: crate::RWRegister<u32>,
43 #[doc = "LCDIF VSYNC Mode and Dotclk Mode Control Register0"]
44 pub VDCTRL0_TOG: crate::RWRegister<u32>,
45 #[doc = "LCDIF VSYNC Mode and Dotclk Mode Control Register1"]
46 pub VDCTRL1: crate::RWRegister<u32>,
47 _reserved3: [u8; 0x0c],
48 #[doc = "LCDIF VSYNC Mode and Dotclk Mode Control Register2"]
49 pub VDCTRL2: crate::RWRegister<u32>,
50 _reserved4: [u8; 0x0c],
51 #[doc = "LCDIF VSYNC Mode and Dotclk Mode Control Register3"]
52 pub VDCTRL3: crate::RWRegister<u32>,
53 _reserved5: [u8; 0x0c],
54 #[doc = "LCDIF VSYNC Mode and Dotclk Mode Control Register4"]
55 pub VDCTRL4: crate::RWRegister<u32>,
56 _reserved6: [u8; 0xdc],
57 #[doc = "Bus Master Error Status Register"]
58 pub BM_ERROR_STAT: crate::RWRegister<u32>,
59 _reserved7: [u8; 0x0c],
60 #[doc = "CRC Status Register"]
61 pub CRC_STAT: crate::RWRegister<u32>,
62 _reserved8: [u8; 0x0c],
63 #[doc = "LCD Interface Status Register"]
64 pub STAT: crate::RORegister<u32>,
65 _reserved9: [u8; 0x01cc],
66 #[doc = "LCDIF Pigeon Mode Control0 Register"]
67 pub PIGEONCTRL0: crate::RWRegister<u32>,
68 #[doc = "LCDIF Pigeon Mode Control0 Register"]
69 pub PIGEONCTRL0_SET: crate::RWRegister<u32>,
70 #[doc = "LCDIF Pigeon Mode Control0 Register"]
71 pub PIGEONCTRL0_CLR: crate::RWRegister<u32>,
72 #[doc = "LCDIF Pigeon Mode Control0 Register"]
73 pub PIGEONCTRL0_TOG: crate::RWRegister<u32>,
74 #[doc = "LCDIF Pigeon Mode Control1 Register"]
75 pub PIGEONCTRL1: crate::RWRegister<u32>,
76 #[doc = "LCDIF Pigeon Mode Control1 Register"]
77 pub PIGEONCTRL1_SET: crate::RWRegister<u32>,
78 #[doc = "LCDIF Pigeon Mode Control1 Register"]
79 pub PIGEONCTRL1_CLR: crate::RWRegister<u32>,
80 #[doc = "LCDIF Pigeon Mode Control1 Register"]
81 pub PIGEONCTRL1_TOG: crate::RWRegister<u32>,
82 #[doc = "LCDIF Pigeon Mode Control2 Register"]
83 pub PIGEONCTRL2: crate::RWRegister<u32>,
84 #[doc = "LCDIF Pigeon Mode Control2 Register"]
85 pub PIGEONCTRL2_SET: crate::RWRegister<u32>,
86 #[doc = "LCDIF Pigeon Mode Control2 Register"]
87 pub PIGEONCTRL2_CLR: crate::RWRegister<u32>,
88 #[doc = "LCDIF Pigeon Mode Control2 Register"]
89 pub PIGEONCTRL2_TOG: crate::RWRegister<u32>,
90 _reserved10: [u8; 0x0450],
91 #[doc = "Panel Interface Signal Generator Register"]
92 pub PIGEON_0_0: crate::RWRegister<u32>,
93 _reserved11: [u8; 0x0c],
94 #[doc = "Panel Interface Signal Generator Register"]
95 pub PIGEON_0_1: crate::RWRegister<u32>,
96 _reserved12: [u8; 0x0c],
97 #[doc = "Panel Interface Signal Generator Register"]
98 pub PIGEON_0_2: crate::RWRegister<u32>,
99 _reserved13: [u8; 0x1c],
100 #[doc = "Panel Interface Signal Generator Register"]
101 pub PIGEON_1_0: crate::RWRegister<u32>,
102 _reserved14: [u8; 0x0c],
103 #[doc = "Panel Interface Signal Generator Register"]
104 pub PIGEON_1_1: crate::RWRegister<u32>,
105 _reserved15: [u8; 0x0c],
106 #[doc = "Panel Interface Signal Generator Register"]
107 pub PIGEON_1_2: crate::RWRegister<u32>,
108 _reserved16: [u8; 0x1c],
109 #[doc = "Panel Interface Signal Generator Register"]
110 pub PIGEON_2_0: crate::RWRegister<u32>,
111 _reserved17: [u8; 0x0c],
112 #[doc = "Panel Interface Signal Generator Register"]
113 pub PIGEON_2_1: crate::RWRegister<u32>,
114 _reserved18: [u8; 0x0c],
115 #[doc = "Panel Interface Signal Generator Register"]
116 pub PIGEON_2_2: crate::RWRegister<u32>,
117 _reserved19: [u8; 0x1c],
118 #[doc = "Panel Interface Signal Generator Register"]
119 pub PIGEON_3_0: crate::RWRegister<u32>,
120 _reserved20: [u8; 0x0c],
121 #[doc = "Panel Interface Signal Generator Register"]
122 pub PIGEON_3_1: crate::RWRegister<u32>,
123 _reserved21: [u8; 0x0c],
124 #[doc = "Panel Interface Signal Generator Register"]
125 pub PIGEON_3_2: crate::RWRegister<u32>,
126 _reserved22: [u8; 0x1c],
127 #[doc = "Panel Interface Signal Generator Register"]
128 pub PIGEON_4_0: crate::RWRegister<u32>,
129 _reserved23: [u8; 0x0c],
130 #[doc = "Panel Interface Signal Generator Register"]
131 pub PIGEON_4_1: crate::RWRegister<u32>,
132 _reserved24: [u8; 0x0c],
133 #[doc = "Panel Interface Signal Generator Register"]
134 pub PIGEON_4_2: crate::RWRegister<u32>,
135 _reserved25: [u8; 0x1c],
136 #[doc = "Panel Interface Signal Generator Register"]
137 pub PIGEON_5_0: crate::RWRegister<u32>,
138 _reserved26: [u8; 0x0c],
139 #[doc = "Panel Interface Signal Generator Register"]
140 pub PIGEON_5_1: crate::RWRegister<u32>,
141 _reserved27: [u8; 0x0c],
142 #[doc = "Panel Interface Signal Generator Register"]
143 pub PIGEON_5_2: crate::RWRegister<u32>,
144 _reserved28: [u8; 0x1c],
145 #[doc = "Panel Interface Signal Generator Register"]
146 pub PIGEON_6_0: crate::RWRegister<u32>,
147 _reserved29: [u8; 0x0c],
148 #[doc = "Panel Interface Signal Generator Register"]
149 pub PIGEON_6_1: crate::RWRegister<u32>,
150 _reserved30: [u8; 0x0c],
151 #[doc = "Panel Interface Signal Generator Register"]
152 pub PIGEON_6_2: crate::RWRegister<u32>,
153 _reserved31: [u8; 0x1c],
154 #[doc = "Panel Interface Signal Generator Register"]
155 pub PIGEON_7_0: crate::RWRegister<u32>,
156 _reserved32: [u8; 0x0c],
157 #[doc = "Panel Interface Signal Generator Register"]
158 pub PIGEON_7_1: crate::RWRegister<u32>,
159 _reserved33: [u8; 0x0c],
160 #[doc = "Panel Interface Signal Generator Register"]
161 pub PIGEON_7_2: crate::RWRegister<u32>,
162 _reserved34: [u8; 0x1c],
163 #[doc = "Panel Interface Signal Generator Register"]
164 pub PIGEON_8_0: crate::RWRegister<u32>,
165 _reserved35: [u8; 0x0c],
166 #[doc = "Panel Interface Signal Generator Register"]
167 pub PIGEON_8_1: crate::RWRegister<u32>,
168 _reserved36: [u8; 0x0c],
169 #[doc = "Panel Interface Signal Generator Register"]
170 pub PIGEON_8_2: crate::RWRegister<u32>,
171 _reserved37: [u8; 0x1c],
172 #[doc = "Panel Interface Signal Generator Register"]
173 pub PIGEON_9_0: crate::RWRegister<u32>,
174 _reserved38: [u8; 0x0c],
175 #[doc = "Panel Interface Signal Generator Register"]
176 pub PIGEON_9_1: crate::RWRegister<u32>,
177 _reserved39: [u8; 0x0c],
178 #[doc = "Panel Interface Signal Generator Register"]
179 pub PIGEON_9_2: crate::RWRegister<u32>,
180 _reserved40: [u8; 0x1c],
181 #[doc = "Panel Interface Signal Generator Register"]
182 pub PIGEON_10_0: crate::RWRegister<u32>,
183 _reserved41: [u8; 0x0c],
184 #[doc = "Panel Interface Signal Generator Register"]
185 pub PIGEON_10_1: crate::RWRegister<u32>,
186 _reserved42: [u8; 0x0c],
187 #[doc = "Panel Interface Signal Generator Register"]
188 pub PIGEON_10_2: crate::RWRegister<u32>,
189 _reserved43: [u8; 0x1c],
190 #[doc = "Panel Interface Signal Generator Register"]
191 pub PIGEON_11_0: crate::RWRegister<u32>,
192 _reserved44: [u8; 0x0c],
193 #[doc = "Panel Interface Signal Generator Register"]
194 pub PIGEON_11_1: crate::RWRegister<u32>,
195 _reserved45: [u8; 0x0c],
196 #[doc = "Panel Interface Signal Generator Register"]
197 pub PIGEON_11_2: crate::RWRegister<u32>,
198 _reserved46: [u8; 0x1c],
199 #[doc = "Lookup Table Data Register."]
200 pub LUT_CTRL: crate::RWRegister<u32>,
201 _reserved47: [u8; 0x0c],
202 #[doc = "Lookup Table Control Register."]
203 pub LUT0_ADDR: crate::RWRegister<u32>,
204 _reserved48: [u8; 0x0c],
205 #[doc = "Lookup Table Data Register."]
206 pub LUT0_DATA: crate::RWRegister<u32>,
207 _reserved49: [u8; 0x0c],
208 #[doc = "Lookup Table Control Register."]
209 pub LUT1_ADDR: crate::RWRegister<u32>,
210 _reserved50: [u8; 0x0c],
211 #[doc = "Lookup Table Data Register."]
212 pub LUT1_DATA: crate::RWRegister<u32>,
213}
214#[doc = "LCDIF General Control Register"]
215pub mod CTRL {
216 #[doc = "When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display"]
217 pub mod RUN {
218 pub const offset: u32 = 0;
219 pub const mask: u32 = 0x01 << offset;
220 pub mod R {}
221 pub mod W {}
222 pub mod RW {}
223 }
224 #[doc = "Used only when WORD_LENGTH = 3, i"]
225 pub mod DATA_FORMAT_24_BIT {
226 pub const offset: u32 = 1;
227 pub const mask: u32 = 0x01 << offset;
228 pub mod R {}
229 pub mod W {}
230 pub mod RW {
231 #[doc = "Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits."]
232 pub const ALL_24_BITS_VALID: u32 = 0;
233 #[doc = "Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped."]
234 pub const DROP_UPPER_2_BITS_PER_BYTE: u32 = 0x01;
235 }
236 }
237 #[doc = "Used only when WORD_LENGTH = 2, i.e. 18-bit."]
238 pub mod DATA_FORMAT_18_BIT {
239 pub const offset: u32 = 2;
240 pub const mask: u32 = 0x01 << offset;
241 pub mod R {}
242 pub mod W {}
243 pub mod RW {
244 #[doc = "Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data."]
245 pub const LOWER_18_BITS_VALID: u32 = 0;
246 #[doc = "Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data."]
247 pub const UPPER_18_BITS_VALID: u32 = 0x01;
248 }
249 }
250 #[doc = "When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format"]
251 pub mod DATA_FORMAT_16_BIT {
252 pub const offset: u32 = 3;
253 pub const mask: u32 = 0x01 << offset;
254 pub mod R {}
255 pub mod W {}
256 pub mod RW {}
257 }
258 #[doc = "Set this bit to make the LCDIF act as a bus master"]
259 pub mod MASTER {
260 pub const offset: u32 = 5;
261 pub const mask: u32 = 0x01 << offset;
262 pub mod R {}
263 pub mod W {}
264 pub mod RW {}
265 }
266 #[doc = "If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on"]
267 pub mod ENABLE_PXP_HANDSHAKE {
268 pub const offset: u32 = 6;
269 pub const mask: u32 = 0x01 << offset;
270 pub mod R {}
271 pub mod W {}
272 pub mod RW {}
273 }
274 #[doc = "Input data format."]
275 pub mod WORD_LENGTH {
276 pub const offset: u32 = 8;
277 pub const mask: u32 = 0x03 << offset;
278 pub mod R {}
279 pub mod W {}
280 pub mod RW {
281 #[doc = "Input data is 16 bits per pixel."]
282 pub const _16_BIT: u32 = 0;
283 #[doc = "Input data is 8 bits wide."]
284 pub const _8_BIT: u32 = 0x01;
285 #[doc = "Input data is 18 bits per pixel."]
286 pub const _18_BIT: u32 = 0x02;
287 #[doc = "Input data is 24 bits per pixel."]
288 pub const _24_BIT: u32 = 0x03;
289 }
290 }
291 #[doc = "LCD Data bus transfer width."]
292 pub mod LCD_DATABUS_WIDTH {
293 pub const offset: u32 = 10;
294 pub const mask: u32 = 0x03 << offset;
295 pub mod R {}
296 pub mod W {}
297 pub mod RW {
298 #[doc = "16-bit data bus mode."]
299 pub const _16_BIT: u32 = 0;
300 #[doc = "8-bit data bus mode."]
301 pub const _8_BIT: u32 = 0x01;
302 #[doc = "18-bit data bus mode."]
303 pub const _18_BIT: u32 = 0x02;
304 #[doc = "24-bit data bus mode."]
305 pub const _24_BIT: u32 = 0x03;
306 }
307 }
308 #[doc = "This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus"]
309 pub mod CSC_DATA_SWIZZLE {
310 pub const offset: u32 = 12;
311 pub const mask: u32 = 0x03 << offset;
312 pub mod R {}
313 pub mod W {}
314 pub mod RW {
315 #[doc = "No byte swapping.(Little endian)"]
316 pub const NO_SWAP: u32 = 0;
317 #[doc = "Big Endian swap (swap bytes 0,3 and 1,2)."]
318 pub const BIG_ENDIAN_SWAP: u32 = 0x01;
319 #[doc = "Swap half-words."]
320 pub const HWD_SWAP: u32 = 0x02;
321 #[doc = "Swap bytes within each half-word."]
322 pub const HWD_BYTE_SWAP: u32 = 0x03;
323 }
324 }
325 #[doc = "This field specifies how to swap the bytes fetched by the bus master interface"]
326 pub mod INPUT_DATA_SWIZZLE {
327 pub const offset: u32 = 14;
328 pub const mask: u32 = 0x03 << offset;
329 pub mod R {}
330 pub mod W {}
331 pub mod RW {
332 #[doc = "No byte swapping.(Little endian)"]
333 pub const NO_SWAP: u32 = 0;
334 #[doc = "Big Endian swap (swap bytes 0,3 and 1,2)."]
335 pub const BIG_ENDIAN_SWAP: u32 = 0x01;
336 #[doc = "Swap half-words."]
337 pub const HWD_SWAP: u32 = 0x02;
338 #[doc = "Swap bytes within each half-word."]
339 pub const HWD_BYTE_SWAP: u32 = 0x03;
340 }
341 }
342 #[doc = "Set this bit to 1 to make the hardware go into the DOTCLK mode, i"]
343 pub mod DOTCLK_MODE {
344 pub const offset: u32 = 17;
345 pub const mask: u32 = 0x01 << offset;
346 pub mod R {}
347 pub mod W {}
348 pub mod RW {}
349 }
350 #[doc = "When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out"]
351 pub mod BYPASS_COUNT {
352 pub const offset: u32 = 19;
353 pub const mask: u32 = 0x01 << offset;
354 pub mod R {}
355 pub mod W {}
356 pub mod RW {}
357 }
358 #[doc = "The data to be transmitted is shifted left or right by this number of bits."]
359 pub mod SHIFT_NUM_BITS {
360 pub const offset: u32 = 21;
361 pub const mask: u32 = 0x1f << offset;
362 pub mod R {}
363 pub mod W {}
364 pub mod RW {}
365 }
366 #[doc = "Use this bit to determine the direction of shift of transmit data."]
367 pub mod DATA_SHIFT_DIR {
368 pub const offset: u32 = 26;
369 pub const mask: u32 = 0x01 << offset;
370 pub mod R {}
371 pub mod W {}
372 pub mod RW {
373 #[doc = "Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits."]
374 pub const TXDATA_SHIFT_LEFT: u32 = 0;
375 #[doc = "Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits."]
376 pub const TXDATA_SHIFT_RIGHT: u32 = 0x01;
377 }
378 }
379 #[doc = "This bit must be set to zero for normal operation"]
380 pub mod CLKGATE {
381 pub const offset: u32 = 30;
382 pub const mask: u32 = 0x01 << offset;
383 pub mod R {}
384 pub mod W {}
385 pub mod RW {}
386 }
387 #[doc = "This bit must be set to zero to enable normal operation of the LCDIF"]
388 pub mod SFTRST {
389 pub const offset: u32 = 31;
390 pub const mask: u32 = 0x01 << offset;
391 pub mod R {}
392 pub mod W {}
393 pub mod RW {}
394 }
395}
396#[doc = "LCDIF General Control Register"]
397pub mod CTRL_SET {
398 #[doc = "When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display"]
399 pub mod RUN {
400 pub const offset: u32 = 0;
401 pub const mask: u32 = 0x01 << offset;
402 pub mod R {}
403 pub mod W {}
404 pub mod RW {}
405 }
406 #[doc = "Used only when WORD_LENGTH = 3, i"]
407 pub mod DATA_FORMAT_24_BIT {
408 pub const offset: u32 = 1;
409 pub const mask: u32 = 0x01 << offset;
410 pub mod R {}
411 pub mod W {}
412 pub mod RW {
413 #[doc = "Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits."]
414 pub const ALL_24_BITS_VALID: u32 = 0;
415 #[doc = "Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped."]
416 pub const DROP_UPPER_2_BITS_PER_BYTE: u32 = 0x01;
417 }
418 }
419 #[doc = "Used only when WORD_LENGTH = 2, i.e. 18-bit."]
420 pub mod DATA_FORMAT_18_BIT {
421 pub const offset: u32 = 2;
422 pub const mask: u32 = 0x01 << offset;
423 pub mod R {}
424 pub mod W {}
425 pub mod RW {
426 #[doc = "Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data."]
427 pub const LOWER_18_BITS_VALID: u32 = 0;
428 #[doc = "Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data."]
429 pub const UPPER_18_BITS_VALID: u32 = 0x01;
430 }
431 }
432 #[doc = "When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format"]
433 pub mod DATA_FORMAT_16_BIT {
434 pub const offset: u32 = 3;
435 pub const mask: u32 = 0x01 << offset;
436 pub mod R {}
437 pub mod W {}
438 pub mod RW {}
439 }
440 #[doc = "Set this bit to make the LCDIF act as a bus master"]
441 pub mod MASTER {
442 pub const offset: u32 = 5;
443 pub const mask: u32 = 0x01 << offset;
444 pub mod R {}
445 pub mod W {}
446 pub mod RW {}
447 }
448 #[doc = "If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on"]
449 pub mod ENABLE_PXP_HANDSHAKE {
450 pub const offset: u32 = 6;
451 pub const mask: u32 = 0x01 << offset;
452 pub mod R {}
453 pub mod W {}
454 pub mod RW {}
455 }
456 #[doc = "Input data format."]
457 pub mod WORD_LENGTH {
458 pub const offset: u32 = 8;
459 pub const mask: u32 = 0x03 << offset;
460 pub mod R {}
461 pub mod W {}
462 pub mod RW {
463 #[doc = "Input data is 16 bits per pixel."]
464 pub const _16_BIT: u32 = 0;
465 #[doc = "Input data is 8 bits wide."]
466 pub const _8_BIT: u32 = 0x01;
467 #[doc = "Input data is 18 bits per pixel."]
468 pub const _18_BIT: u32 = 0x02;
469 #[doc = "Input data is 24 bits per pixel."]
470 pub const _24_BIT: u32 = 0x03;
471 }
472 }
473 #[doc = "LCD Data bus transfer width."]
474 pub mod LCD_DATABUS_WIDTH {
475 pub const offset: u32 = 10;
476 pub const mask: u32 = 0x03 << offset;
477 pub mod R {}
478 pub mod W {}
479 pub mod RW {
480 #[doc = "16-bit data bus mode."]
481 pub const _16_BIT: u32 = 0;
482 #[doc = "8-bit data bus mode."]
483 pub const _8_BIT: u32 = 0x01;
484 #[doc = "18-bit data bus mode."]
485 pub const _18_BIT: u32 = 0x02;
486 #[doc = "24-bit data bus mode."]
487 pub const _24_BIT: u32 = 0x03;
488 }
489 }
490 #[doc = "This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus"]
491 pub mod CSC_DATA_SWIZZLE {
492 pub const offset: u32 = 12;
493 pub const mask: u32 = 0x03 << offset;
494 pub mod R {}
495 pub mod W {}
496 pub mod RW {
497 #[doc = "No byte swapping.(Little endian)"]
498 pub const NO_SWAP: u32 = 0;
499 #[doc = "Big Endian swap (swap bytes 0,3 and 1,2)."]
500 pub const BIG_ENDIAN_SWAP: u32 = 0x01;
501 #[doc = "Swap half-words."]
502 pub const HWD_SWAP: u32 = 0x02;
503 #[doc = "Swap bytes within each half-word."]
504 pub const HWD_BYTE_SWAP: u32 = 0x03;
505 }
506 }
507 #[doc = "This field specifies how to swap the bytes fetched by the bus master interface"]
508 pub mod INPUT_DATA_SWIZZLE {
509 pub const offset: u32 = 14;
510 pub const mask: u32 = 0x03 << offset;
511 pub mod R {}
512 pub mod W {}
513 pub mod RW {
514 #[doc = "No byte swapping.(Little endian)"]
515 pub const NO_SWAP: u32 = 0;
516 #[doc = "Big Endian swap (swap bytes 0,3 and 1,2)."]
517 pub const BIG_ENDIAN_SWAP: u32 = 0x01;
518 #[doc = "Swap half-words."]
519 pub const HWD_SWAP: u32 = 0x02;
520 #[doc = "Swap bytes within each half-word."]
521 pub const HWD_BYTE_SWAP: u32 = 0x03;
522 }
523 }
524 #[doc = "Set this bit to 1 to make the hardware go into the DOTCLK mode, i"]
525 pub mod DOTCLK_MODE {
526 pub const offset: u32 = 17;
527 pub const mask: u32 = 0x01 << offset;
528 pub mod R {}
529 pub mod W {}
530 pub mod RW {}
531 }
532 #[doc = "When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out"]
533 pub mod BYPASS_COUNT {
534 pub const offset: u32 = 19;
535 pub const mask: u32 = 0x01 << offset;
536 pub mod R {}
537 pub mod W {}
538 pub mod RW {}
539 }
540 #[doc = "The data to be transmitted is shifted left or right by this number of bits."]
541 pub mod SHIFT_NUM_BITS {
542 pub const offset: u32 = 21;
543 pub const mask: u32 = 0x1f << offset;
544 pub mod R {}
545 pub mod W {}
546 pub mod RW {}
547 }
548 #[doc = "Use this bit to determine the direction of shift of transmit data."]
549 pub mod DATA_SHIFT_DIR {
550 pub const offset: u32 = 26;
551 pub const mask: u32 = 0x01 << offset;
552 pub mod R {}
553 pub mod W {}
554 pub mod RW {
555 #[doc = "Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits."]
556 pub const TXDATA_SHIFT_LEFT: u32 = 0;
557 #[doc = "Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits."]
558 pub const TXDATA_SHIFT_RIGHT: u32 = 0x01;
559 }
560 }
561 #[doc = "This bit must be set to zero for normal operation"]
562 pub mod CLKGATE {
563 pub const offset: u32 = 30;
564 pub const mask: u32 = 0x01 << offset;
565 pub mod R {}
566 pub mod W {}
567 pub mod RW {}
568 }
569 #[doc = "This bit must be set to zero to enable normal operation of the LCDIF"]
570 pub mod SFTRST {
571 pub const offset: u32 = 31;
572 pub const mask: u32 = 0x01 << offset;
573 pub mod R {}
574 pub mod W {}
575 pub mod RW {}
576 }
577}
578#[doc = "LCDIF General Control Register"]
579pub mod CTRL_CLR {
580 #[doc = "When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display"]
581 pub mod RUN {
582 pub const offset: u32 = 0;
583 pub const mask: u32 = 0x01 << offset;
584 pub mod R {}
585 pub mod W {}
586 pub mod RW {}
587 }
588 #[doc = "Used only when WORD_LENGTH = 3, i"]
589 pub mod DATA_FORMAT_24_BIT {
590 pub const offset: u32 = 1;
591 pub const mask: u32 = 0x01 << offset;
592 pub mod R {}
593 pub mod W {}
594 pub mod RW {
595 #[doc = "Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits."]
596 pub const ALL_24_BITS_VALID: u32 = 0;
597 #[doc = "Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped."]
598 pub const DROP_UPPER_2_BITS_PER_BYTE: u32 = 0x01;
599 }
600 }
601 #[doc = "Used only when WORD_LENGTH = 2, i.e. 18-bit."]
602 pub mod DATA_FORMAT_18_BIT {
603 pub const offset: u32 = 2;
604 pub const mask: u32 = 0x01 << offset;
605 pub mod R {}
606 pub mod W {}
607 pub mod RW {
608 #[doc = "Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data."]
609 pub const LOWER_18_BITS_VALID: u32 = 0;
610 #[doc = "Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data."]
611 pub const UPPER_18_BITS_VALID: u32 = 0x01;
612 }
613 }
614 #[doc = "When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format"]
615 pub mod DATA_FORMAT_16_BIT {
616 pub const offset: u32 = 3;
617 pub const mask: u32 = 0x01 << offset;
618 pub mod R {}
619 pub mod W {}
620 pub mod RW {}
621 }
622 #[doc = "Set this bit to make the LCDIF act as a bus master"]
623 pub mod MASTER {
624 pub const offset: u32 = 5;
625 pub const mask: u32 = 0x01 << offset;
626 pub mod R {}
627 pub mod W {}
628 pub mod RW {}
629 }
630 #[doc = "If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on"]
631 pub mod ENABLE_PXP_HANDSHAKE {
632 pub const offset: u32 = 6;
633 pub const mask: u32 = 0x01 << offset;
634 pub mod R {}
635 pub mod W {}
636 pub mod RW {}
637 }
638 #[doc = "Input data format."]
639 pub mod WORD_LENGTH {
640 pub const offset: u32 = 8;
641 pub const mask: u32 = 0x03 << offset;
642 pub mod R {}
643 pub mod W {}
644 pub mod RW {
645 #[doc = "Input data is 16 bits per pixel."]
646 pub const _16_BIT: u32 = 0;
647 #[doc = "Input data is 8 bits wide."]
648 pub const _8_BIT: u32 = 0x01;
649 #[doc = "Input data is 18 bits per pixel."]
650 pub const _18_BIT: u32 = 0x02;
651 #[doc = "Input data is 24 bits per pixel."]
652 pub const _24_BIT: u32 = 0x03;
653 }
654 }
655 #[doc = "LCD Data bus transfer width."]
656 pub mod LCD_DATABUS_WIDTH {
657 pub const offset: u32 = 10;
658 pub const mask: u32 = 0x03 << offset;
659 pub mod R {}
660 pub mod W {}
661 pub mod RW {
662 #[doc = "16-bit data bus mode."]
663 pub const _16_BIT: u32 = 0;
664 #[doc = "8-bit data bus mode."]
665 pub const _8_BIT: u32 = 0x01;
666 #[doc = "18-bit data bus mode."]
667 pub const _18_BIT: u32 = 0x02;
668 #[doc = "24-bit data bus mode."]
669 pub const _24_BIT: u32 = 0x03;
670 }
671 }
672 #[doc = "This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus"]
673 pub mod CSC_DATA_SWIZZLE {
674 pub const offset: u32 = 12;
675 pub const mask: u32 = 0x03 << offset;
676 pub mod R {}
677 pub mod W {}
678 pub mod RW {
679 #[doc = "No byte swapping.(Little endian)"]
680 pub const NO_SWAP: u32 = 0;
681 #[doc = "Big Endian swap (swap bytes 0,3 and 1,2)."]
682 pub const BIG_ENDIAN_SWAP: u32 = 0x01;
683 #[doc = "Swap half-words."]
684 pub const HWD_SWAP: u32 = 0x02;
685 #[doc = "Swap bytes within each half-word."]
686 pub const HWD_BYTE_SWAP: u32 = 0x03;
687 }
688 }
689 #[doc = "This field specifies how to swap the bytes fetched by the bus master interface"]
690 pub mod INPUT_DATA_SWIZZLE {
691 pub const offset: u32 = 14;
692 pub const mask: u32 = 0x03 << offset;
693 pub mod R {}
694 pub mod W {}
695 pub mod RW {
696 #[doc = "No byte swapping.(Little endian)"]
697 pub const NO_SWAP: u32 = 0;
698 #[doc = "Big Endian swap (swap bytes 0,3 and 1,2)."]
699 pub const BIG_ENDIAN_SWAP: u32 = 0x01;
700 #[doc = "Swap half-words."]
701 pub const HWD_SWAP: u32 = 0x02;
702 #[doc = "Swap bytes within each half-word."]
703 pub const HWD_BYTE_SWAP: u32 = 0x03;
704 }
705 }
706 #[doc = "Set this bit to 1 to make the hardware go into the DOTCLK mode, i"]
707 pub mod DOTCLK_MODE {
708 pub const offset: u32 = 17;
709 pub const mask: u32 = 0x01 << offset;
710 pub mod R {}
711 pub mod W {}
712 pub mod RW {}
713 }
714 #[doc = "When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out"]
715 pub mod BYPASS_COUNT {
716 pub const offset: u32 = 19;
717 pub const mask: u32 = 0x01 << offset;
718 pub mod R {}
719 pub mod W {}
720 pub mod RW {}
721 }
722 #[doc = "The data to be transmitted is shifted left or right by this number of bits."]
723 pub mod SHIFT_NUM_BITS {
724 pub const offset: u32 = 21;
725 pub const mask: u32 = 0x1f << offset;
726 pub mod R {}
727 pub mod W {}
728 pub mod RW {}
729 }
730 #[doc = "Use this bit to determine the direction of shift of transmit data."]
731 pub mod DATA_SHIFT_DIR {
732 pub const offset: u32 = 26;
733 pub const mask: u32 = 0x01 << offset;
734 pub mod R {}
735 pub mod W {}
736 pub mod RW {
737 #[doc = "Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits."]
738 pub const TXDATA_SHIFT_LEFT: u32 = 0;
739 #[doc = "Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits."]
740 pub const TXDATA_SHIFT_RIGHT: u32 = 0x01;
741 }
742 }
743 #[doc = "This bit must be set to zero for normal operation"]
744 pub mod CLKGATE {
745 pub const offset: u32 = 30;
746 pub const mask: u32 = 0x01 << offset;
747 pub mod R {}
748 pub mod W {}
749 pub mod RW {}
750 }
751 #[doc = "This bit must be set to zero to enable normal operation of the LCDIF"]
752 pub mod SFTRST {
753 pub const offset: u32 = 31;
754 pub const mask: u32 = 0x01 << offset;
755 pub mod R {}
756 pub mod W {}
757 pub mod RW {}
758 }
759}
760#[doc = "LCDIF General Control Register"]
761pub mod CTRL_TOG {
762 #[doc = "When this bit is set by software, the LCDIF will begin transferring data between the SoC and the display"]
763 pub mod RUN {
764 pub const offset: u32 = 0;
765 pub const mask: u32 = 0x01 << offset;
766 pub mod R {}
767 pub mod W {}
768 pub mod RW {}
769 }
770 #[doc = "Used only when WORD_LENGTH = 3, i"]
771 pub mod DATA_FORMAT_24_BIT {
772 pub const offset: u32 = 1;
773 pub const mask: u32 = 0x01 << offset;
774 pub mod R {}
775 pub mod W {}
776 pub mod RW {
777 #[doc = "Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits."]
778 pub const ALL_24_BITS_VALID: u32 = 0;
779 #[doc = "Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped."]
780 pub const DROP_UPPER_2_BITS_PER_BYTE: u32 = 0x01;
781 }
782 }
783 #[doc = "Used only when WORD_LENGTH = 2, i.e. 18-bit."]
784 pub mod DATA_FORMAT_18_BIT {
785 pub const offset: u32 = 2;
786 pub const mask: u32 = 0x01 << offset;
787 pub mod R {}
788 pub mod W {}
789 pub mod RW {
790 #[doc = "Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data."]
791 pub const LOWER_18_BITS_VALID: u32 = 0;
792 #[doc = "Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data."]
793 pub const UPPER_18_BITS_VALID: u32 = 0x01;
794 }
795 }
796 #[doc = "When this bit is 1 and WORD_LENGTH = 0, it implies that the 16-bit data is in ARGB555 format"]
797 pub mod DATA_FORMAT_16_BIT {
798 pub const offset: u32 = 3;
799 pub const mask: u32 = 0x01 << offset;
800 pub mod R {}
801 pub mod W {}
802 pub mod RW {}
803 }
804 #[doc = "Set this bit to make the LCDIF act as a bus master"]
805 pub mod MASTER {
806 pub const offset: u32 = 5;
807 pub const mask: u32 = 0x01 << offset;
808 pub mod R {}
809 pub mod W {}
810 pub mod RW {}
811 }
812 #[doc = "If this bit is set and LCDIF_MASTER bit is set, the LCDIF will act as bus master and the handshake mechanism between LCDIF and PXP will be turned on"]
813 pub mod ENABLE_PXP_HANDSHAKE {
814 pub const offset: u32 = 6;
815 pub const mask: u32 = 0x01 << offset;
816 pub mod R {}
817 pub mod W {}
818 pub mod RW {}
819 }
820 #[doc = "Input data format."]
821 pub mod WORD_LENGTH {
822 pub const offset: u32 = 8;
823 pub const mask: u32 = 0x03 << offset;
824 pub mod R {}
825 pub mod W {}
826 pub mod RW {
827 #[doc = "Input data is 16 bits per pixel."]
828 pub const _16_BIT: u32 = 0;
829 #[doc = "Input data is 8 bits wide."]
830 pub const _8_BIT: u32 = 0x01;
831 #[doc = "Input data is 18 bits per pixel."]
832 pub const _18_BIT: u32 = 0x02;
833 #[doc = "Input data is 24 bits per pixel."]
834 pub const _24_BIT: u32 = 0x03;
835 }
836 }
837 #[doc = "LCD Data bus transfer width."]
838 pub mod LCD_DATABUS_WIDTH {
839 pub const offset: u32 = 10;
840 pub const mask: u32 = 0x03 << offset;
841 pub mod R {}
842 pub mod W {}
843 pub mod RW {
844 #[doc = "16-bit data bus mode."]
845 pub const _16_BIT: u32 = 0;
846 #[doc = "8-bit data bus mode."]
847 pub const _8_BIT: u32 = 0x01;
848 #[doc = "18-bit data bus mode."]
849 pub const _18_BIT: u32 = 0x02;
850 #[doc = "24-bit data bus mode."]
851 pub const _24_BIT: u32 = 0x03;
852 }
853 }
854 #[doc = "This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus"]
855 pub mod CSC_DATA_SWIZZLE {
856 pub const offset: u32 = 12;
857 pub const mask: u32 = 0x03 << offset;
858 pub mod R {}
859 pub mod W {}
860 pub mod RW {
861 #[doc = "No byte swapping.(Little endian)"]
862 pub const NO_SWAP: u32 = 0;
863 #[doc = "Big Endian swap (swap bytes 0,3 and 1,2)."]
864 pub const BIG_ENDIAN_SWAP: u32 = 0x01;
865 #[doc = "Swap half-words."]
866 pub const HWD_SWAP: u32 = 0x02;
867 #[doc = "Swap bytes within each half-word."]
868 pub const HWD_BYTE_SWAP: u32 = 0x03;
869 }
870 }
871 #[doc = "This field specifies how to swap the bytes fetched by the bus master interface"]
872 pub mod INPUT_DATA_SWIZZLE {
873 pub const offset: u32 = 14;
874 pub const mask: u32 = 0x03 << offset;
875 pub mod R {}
876 pub mod W {}
877 pub mod RW {
878 #[doc = "No byte swapping.(Little endian)"]
879 pub const NO_SWAP: u32 = 0;
880 #[doc = "Big Endian swap (swap bytes 0,3 and 1,2)."]
881 pub const BIG_ENDIAN_SWAP: u32 = 0x01;
882 #[doc = "Swap half-words."]
883 pub const HWD_SWAP: u32 = 0x02;
884 #[doc = "Swap bytes within each half-word."]
885 pub const HWD_BYTE_SWAP: u32 = 0x03;
886 }
887 }
888 #[doc = "Set this bit to 1 to make the hardware go into the DOTCLK mode, i"]
889 pub mod DOTCLK_MODE {
890 pub const offset: u32 = 17;
891 pub const mask: u32 = 0x01 << offset;
892 pub mod R {}
893 pub mod W {}
894 pub mod RW {}
895 }
896 #[doc = "When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the LCDIF_TRANSFER_COUNT register has been transferred out"]
897 pub mod BYPASS_COUNT {
898 pub const offset: u32 = 19;
899 pub const mask: u32 = 0x01 << offset;
900 pub mod R {}
901 pub mod W {}
902 pub mod RW {}
903 }
904 #[doc = "The data to be transmitted is shifted left or right by this number of bits."]
905 pub mod SHIFT_NUM_BITS {
906 pub const offset: u32 = 21;
907 pub const mask: u32 = 0x1f << offset;
908 pub mod R {}
909 pub mod W {}
910 pub mod RW {}
911 }
912 #[doc = "Use this bit to determine the direction of shift of transmit data."]
913 pub mod DATA_SHIFT_DIR {
914 pub const offset: u32 = 26;
915 pub const mask: u32 = 0x01 << offset;
916 pub mod R {}
917 pub mod W {}
918 pub mod RW {
919 #[doc = "Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits."]
920 pub const TXDATA_SHIFT_LEFT: u32 = 0;
921 #[doc = "Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits."]
922 pub const TXDATA_SHIFT_RIGHT: u32 = 0x01;
923 }
924 }
925 #[doc = "This bit must be set to zero for normal operation"]
926 pub mod CLKGATE {
927 pub const offset: u32 = 30;
928 pub const mask: u32 = 0x01 << offset;
929 pub mod R {}
930 pub mod W {}
931 pub mod RW {}
932 }
933 #[doc = "This bit must be set to zero to enable normal operation of the LCDIF"]
934 pub mod SFTRST {
935 pub const offset: u32 = 31;
936 pub const mask: u32 = 0x01 << offset;
937 pub mod R {}
938 pub mod W {}
939 pub mod RW {}
940 }
941}
942#[doc = "LCDIF General Control1 Register"]
943pub mod CTRL1 {
944 #[doc = "This bit is set to indicate that an interrupt is requested by the LCDIF block"]
945 pub mod VSYNC_EDGE_IRQ {
946 pub const offset: u32 = 8;
947 pub const mask: u32 = 0x01 << offset;
948 pub mod R {}
949 pub mod W {}
950 pub mod RW {
951 #[doc = "No Interrupt Request Pending."]
952 pub const NO_REQUEST: u32 = 0;
953 #[doc = "Interrupt Request Pending."]
954 pub const REQUEST: u32 = 0x01;
955 }
956 }
957 #[doc = "This bit is set to indicate that an interrupt is requested by the LCDIF block"]
958 pub mod CUR_FRAME_DONE_IRQ {
959 pub const offset: u32 = 9;
960 pub const mask: u32 = 0x01 << offset;
961 pub mod R {}
962 pub mod W {}
963 pub mod RW {
964 #[doc = "No Interrupt Request Pending."]
965 pub const NO_REQUEST: u32 = 0;
966 #[doc = "Interrupt Request Pending."]
967 pub const REQUEST: u32 = 0x01;
968 }
969 }
970 #[doc = "This bit is set to indicate that an interrupt is requested by the LCDIF block"]
971 pub mod UNDERFLOW_IRQ {
972 pub const offset: u32 = 10;
973 pub const mask: u32 = 0x01 << offset;
974 pub mod R {}
975 pub mod W {}
976 pub mod RW {
977 #[doc = "No Interrupt Request Pending."]
978 pub const NO_REQUEST: u32 = 0;
979 #[doc = "Interrupt Request Pending."]
980 pub const REQUEST: u32 = 0x01;
981 }
982 }
983 #[doc = "This bit is set to indicate that an interrupt is requested by the LCDIF block"]
984 pub mod OVERFLOW_IRQ {
985 pub const offset: u32 = 11;
986 pub const mask: u32 = 0x01 << offset;
987 pub mod R {}
988 pub mod W {}
989 pub mod RW {
990 #[doc = "No Interrupt Request Pending."]
991 pub const NO_REQUEST: u32 = 0;
992 #[doc = "Interrupt Request Pending."]
993 pub const REQUEST: u32 = 0x01;
994 }
995 }
996 #[doc = "This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode"]
997 pub mod VSYNC_EDGE_IRQ_EN {
998 pub const offset: u32 = 12;
999 pub const mask: u32 = 0x01 << offset;
1000 pub mod R {}
1001 pub mod W {}
1002 pub mod RW {}
1003 }
1004 #[doc = "This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state"]
1005 pub mod CUR_FRAME_DONE_IRQ_EN {
1006 pub const offset: u32 = 13;
1007 pub const mask: u32 = 0x01 << offset;
1008 pub mod R {}
1009 pub mod W {}
1010 pub mod RW {}
1011 }
1012 #[doc = "This bit is set to enable an underflow interrupt in the TXFIFO in the write mode."]
1013 pub mod UNDERFLOW_IRQ_EN {
1014 pub const offset: u32 = 14;
1015 pub const mask: u32 = 0x01 << offset;
1016 pub mod R {}
1017 pub mod W {}
1018 pub mod RW {}
1019 }
1020 #[doc = "This bit is set to enable an overflow interrupt in the TXFIFO in the write mode."]
1021 pub mod OVERFLOW_IRQ_EN {
1022 pub const offset: u32 = 15;
1023 pub const mask: u32 = 0x01 << offset;
1024 pub mod R {}
1025 pub mod W {}
1026 pub mod RW {}
1027 }
1028 #[doc = "This bitfield is used to show which data bytes in a 32-bit word are valid"]
1029 pub mod BYTE_PACKING_FORMAT {
1030 pub const offset: u32 = 16;
1031 pub const mask: u32 = 0x0f << offset;
1032 pub mod R {}
1033 pub mod W {}
1034 pub mod RW {}
1035 }
1036 #[doc = "If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field"]
1037 pub mod IRQ_ON_ALTERNATE_FIELDS {
1038 pub const offset: u32 = 20;
1039 pub const mask: u32 = 0x01 << offset;
1040 pub mod R {}
1041 pub mod W {}
1042 pub mod RW {}
1043 }
1044 #[doc = "Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO."]
1045 pub mod FIFO_CLEAR {
1046 pub const offset: u32 = 21;
1047 pub const mask: u32 = 0x01 << offset;
1048 pub mod R {}
1049 pub mod W {}
1050 pub mod RW {}
1051 }
1052 #[doc = "The default is to grab the odd lines first and then the even lines"]
1053 pub mod START_INTERLACE_FROM_SECOND_FIELD {
1054 pub const offset: u32 = 22;
1055 pub const mask: u32 = 0x01 << offset;
1056 pub mod R {}
1057 pub mod W {}
1058 pub mod RW {}
1059 }
1060 #[doc = "Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field"]
1061 pub mod INTERLACE_FIELDS {
1062 pub const offset: u32 = 23;
1063 pub const mask: u32 = 0x01 << offset;
1064 pub mod R {}
1065 pub mod W {}
1066 pub mod RW {}
1067 }
1068 #[doc = "Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame"]
1069 pub mod RECOVER_ON_UNDERFLOW {
1070 pub const offset: u32 = 24;
1071 pub const mask: u32 = 0x01 << offset;
1072 pub mod R {}
1073 pub mod W {}
1074 pub mod RW {}
1075 }
1076 #[doc = "This bit is set to indicate that an interrupt is requested by the LCDIF block"]
1077 pub mod BM_ERROR_IRQ {
1078 pub const offset: u32 = 25;
1079 pub const mask: u32 = 0x01 << offset;
1080 pub mod R {}
1081 pub mod W {}
1082 pub mod RW {
1083 #[doc = "No Interrupt Request Pending."]
1084 pub const NO_REQUEST: u32 = 0;
1085 #[doc = "Interrupt Request Pending."]
1086 pub const REQUEST: u32 = 0x01;
1087 }
1088 }
1089 #[doc = "This bit is set to enable bus master error interrupt in the LCDIF master mode."]
1090 pub mod BM_ERROR_IRQ_EN {
1091 pub const offset: u32 = 26;
1092 pub const mask: u32 = 0x01 << offset;
1093 pub mod R {}
1094 pub mod W {}
1095 pub mod RW {}
1096 }
1097 #[doc = "This bit is CS0/CS1 valid select signals"]
1098 pub mod CS_OUT_SELECT {
1099 pub const offset: u32 = 30;
1100 pub const mask: u32 = 0x01 << offset;
1101 pub mod R {}
1102 pub mod W {}
1103 pub mod RW {}
1104 }
1105 #[doc = "Command Mode MIPI image data select bit"]
1106 pub mod IMAGE_DATA_SELECT {
1107 pub const offset: u32 = 31;
1108 pub const mask: u32 = 0x01 << offset;
1109 pub mod R {}
1110 pub mod W {}
1111 pub mod RW {}
1112 }
1113}
1114#[doc = "LCDIF General Control1 Register"]
1115pub mod CTRL1_SET {
1116 #[doc = "This bit is set to indicate that an interrupt is requested by the LCDIF block"]
1117 pub mod VSYNC_EDGE_IRQ {
1118 pub const offset: u32 = 8;
1119 pub const mask: u32 = 0x01 << offset;
1120 pub mod R {}
1121 pub mod W {}
1122 pub mod RW {
1123 #[doc = "No Interrupt Request Pending."]
1124 pub const NO_REQUEST: u32 = 0;
1125 #[doc = "Interrupt Request Pending."]
1126 pub const REQUEST: u32 = 0x01;
1127 }
1128 }
1129 #[doc = "This bit is set to indicate that an interrupt is requested by the LCDIF block"]
1130 pub mod CUR_FRAME_DONE_IRQ {
1131 pub const offset: u32 = 9;
1132 pub const mask: u32 = 0x01 << offset;
1133 pub mod R {}
1134 pub mod W {}
1135 pub mod RW {
1136 #[doc = "No Interrupt Request Pending."]
1137 pub const NO_REQUEST: u32 = 0;
1138 #[doc = "Interrupt Request Pending."]
1139 pub const REQUEST: u32 = 0x01;
1140 }
1141 }
1142 #[doc = "This bit is set to indicate that an interrupt is requested by the LCDIF block"]
1143 pub mod UNDERFLOW_IRQ {
1144 pub const offset: u32 = 10;
1145 pub const mask: u32 = 0x01 << offset;
1146 pub mod R {}
1147 pub mod W {}
1148 pub mod RW {
1149 #[doc = "No Interrupt Request Pending."]
1150 pub const NO_REQUEST: u32 = 0;
1151 #[doc = "Interrupt Request Pending."]
1152 pub const REQUEST: u32 = 0x01;
1153 }
1154 }
1155 #[doc = "This bit is set to indicate that an interrupt is requested by the LCDIF block"]
1156 pub mod OVERFLOW_IRQ {
1157 pub const offset: u32 = 11;
1158 pub const mask: u32 = 0x01 << offset;
1159 pub mod R {}
1160 pub mod W {}
1161 pub mod RW {
1162 #[doc = "No Interrupt Request Pending."]
1163 pub const NO_REQUEST: u32 = 0;
1164 #[doc = "Interrupt Request Pending."]
1165 pub const REQUEST: u32 = 0x01;
1166 }
1167 }
1168 #[doc = "This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode"]
1169 pub mod VSYNC_EDGE_IRQ_EN {
1170 pub const offset: u32 = 12;
1171 pub const mask: u32 = 0x01 << offset;
1172 pub mod R {}
1173 pub mod W {}
1174 pub mod RW {}
1175 }
1176 #[doc = "This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state"]
1177 pub mod CUR_FRAME_DONE_IRQ_EN {
1178 pub const offset: u32 = 13;
1179 pub const mask: u32 = 0x01 << offset;
1180 pub mod R {}
1181 pub mod W {}
1182 pub mod RW {}
1183 }
1184 #[doc = "This bit is set to enable an underflow interrupt in the TXFIFO in the write mode."]
1185 pub mod UNDERFLOW_IRQ_EN {
1186 pub const offset: u32 = 14;
1187 pub const mask: u32 = 0x01 << offset;
1188 pub mod R {}
1189 pub mod W {}
1190 pub mod RW {}
1191 }
1192 #[doc = "This bit is set to enable an overflow interrupt in the TXFIFO in the write mode."]
1193 pub mod OVERFLOW_IRQ_EN {
1194 pub const offset: u32 = 15;
1195 pub const mask: u32 = 0x01 << offset;
1196 pub mod R {}
1197 pub mod W {}
1198 pub mod RW {}
1199 }
1200 #[doc = "This bitfield is used to show which data bytes in a 32-bit word are valid"]
1201 pub mod BYTE_PACKING_FORMAT {
1202 pub const offset: u32 = 16;
1203 pub const mask: u32 = 0x0f << offset;
1204 pub mod R {}
1205 pub mod W {}
1206 pub mod RW {}
1207 }
1208 #[doc = "If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field"]
1209 pub mod IRQ_ON_ALTERNATE_FIELDS {
1210 pub const offset: u32 = 20;
1211 pub const mask: u32 = 0x01 << offset;
1212 pub mod R {}
1213 pub mod W {}
1214 pub mod RW {}
1215 }
1216 #[doc = "Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO."]
1217 pub mod FIFO_CLEAR {
1218 pub const offset: u32 = 21;
1219 pub const mask: u32 = 0x01 << offset;
1220 pub mod R {}
1221 pub mod W {}
1222 pub mod RW {}
1223 }
1224 #[doc = "The default is to grab the odd lines first and then the even lines"]
1225 pub mod START_INTERLACE_FROM_SECOND_FIELD {
1226 pub const offset: u32 = 22;
1227 pub const mask: u32 = 0x01 << offset;
1228 pub mod R {}
1229 pub mod W {}
1230 pub mod RW {}
1231 }
1232 #[doc = "Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field"]
1233 pub mod INTERLACE_FIELDS {
1234 pub const offset: u32 = 23;
1235 pub const mask: u32 = 0x01 << offset;
1236 pub mod R {}
1237 pub mod W {}
1238 pub mod RW {}
1239 }
1240 #[doc = "Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame"]
1241 pub mod RECOVER_ON_UNDERFLOW {
1242 pub const offset: u32 = 24;
1243 pub const mask: u32 = 0x01 << offset;
1244 pub mod R {}
1245 pub mod W {}
1246 pub mod RW {}
1247 }
1248 #[doc = "This bit is set to indicate that an interrupt is requested by the LCDIF block"]
1249 pub mod BM_ERROR_IRQ {
1250 pub const offset: u32 = 25;
1251 pub const mask: u32 = 0x01 << offset;
1252 pub mod R {}
1253 pub mod W {}
1254 pub mod RW {
1255 #[doc = "No Interrupt Request Pending."]
1256 pub const NO_REQUEST: u32 = 0;
1257 #[doc = "Interrupt Request Pending."]
1258 pub const REQUEST: u32 = 0x01;
1259 }
1260 }
1261 #[doc = "This bit is set to enable bus master error interrupt in the LCDIF master mode."]
1262 pub mod BM_ERROR_IRQ_EN {
1263 pub const offset: u32 = 26;
1264 pub const mask: u32 = 0x01 << offset;
1265 pub mod R {}
1266 pub mod W {}
1267 pub mod RW {}
1268 }
1269 #[doc = "This bit is CS0/CS1 valid select signals"]
1270 pub mod CS_OUT_SELECT {
1271 pub const offset: u32 = 30;
1272 pub const mask: u32 = 0x01 << offset;
1273 pub mod R {}
1274 pub mod W {}
1275 pub mod RW {}
1276 }
1277 #[doc = "Command Mode MIPI image data select bit"]
1278 pub mod IMAGE_DATA_SELECT {
1279 pub const offset: u32 = 31;
1280 pub const mask: u32 = 0x01 << offset;
1281 pub mod R {}
1282 pub mod W {}
1283 pub mod RW {}
1284 }
1285}
1286#[doc = "LCDIF General Control1 Register"]
1287pub mod CTRL1_CLR {
1288 #[doc = "This bit is set to indicate that an interrupt is requested by the LCDIF block"]
1289 pub mod VSYNC_EDGE_IRQ {
1290 pub const offset: u32 = 8;
1291 pub const mask: u32 = 0x01 << offset;
1292 pub mod R {}
1293 pub mod W {}
1294 pub mod RW {
1295 #[doc = "No Interrupt Request Pending."]
1296 pub const NO_REQUEST: u32 = 0;
1297 #[doc = "Interrupt Request Pending."]
1298 pub const REQUEST: u32 = 0x01;
1299 }
1300 }
1301 #[doc = "This bit is set to indicate that an interrupt is requested by the LCDIF block"]
1302 pub mod CUR_FRAME_DONE_IRQ {
1303 pub const offset: u32 = 9;
1304 pub const mask: u32 = 0x01 << offset;
1305 pub mod R {}
1306 pub mod W {}
1307 pub mod RW {
1308 #[doc = "No Interrupt Request Pending."]
1309 pub const NO_REQUEST: u32 = 0;
1310 #[doc = "Interrupt Request Pending."]
1311 pub const REQUEST: u32 = 0x01;
1312 }
1313 }
1314 #[doc = "This bit is set to indicate that an interrupt is requested by the LCDIF block"]
1315 pub mod UNDERFLOW_IRQ {
1316 pub const offset: u32 = 10;
1317 pub const mask: u32 = 0x01 << offset;
1318 pub mod R {}
1319 pub mod W {}
1320 pub mod RW {
1321 #[doc = "No Interrupt Request Pending."]
1322 pub const NO_REQUEST: u32 = 0;
1323 #[doc = "Interrupt Request Pending."]
1324 pub const REQUEST: u32 = 0x01;
1325 }
1326 }
1327 #[doc = "This bit is set to indicate that an interrupt is requested by the LCDIF block"]
1328 pub mod OVERFLOW_IRQ {
1329 pub const offset: u32 = 11;
1330 pub const mask: u32 = 0x01 << offset;
1331 pub mod R {}
1332 pub mod W {}
1333 pub mod RW {
1334 #[doc = "No Interrupt Request Pending."]
1335 pub const NO_REQUEST: u32 = 0;
1336 #[doc = "Interrupt Request Pending."]
1337 pub const REQUEST: u32 = 0x01;
1338 }
1339 }
1340 #[doc = "This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode"]
1341 pub mod VSYNC_EDGE_IRQ_EN {
1342 pub const offset: u32 = 12;
1343 pub const mask: u32 = 0x01 << offset;
1344 pub mod R {}
1345 pub mod W {}
1346 pub mod RW {}
1347 }
1348 #[doc = "This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state"]
1349 pub mod CUR_FRAME_DONE_IRQ_EN {
1350 pub const offset: u32 = 13;
1351 pub const mask: u32 = 0x01 << offset;
1352 pub mod R {}
1353 pub mod W {}
1354 pub mod RW {}
1355 }
1356 #[doc = "This bit is set to enable an underflow interrupt in the TXFIFO in the write mode."]
1357 pub mod UNDERFLOW_IRQ_EN {
1358 pub const offset: u32 = 14;
1359 pub const mask: u32 = 0x01 << offset;
1360 pub mod R {}
1361 pub mod W {}
1362 pub mod RW {}
1363 }
1364 #[doc = "This bit is set to enable an overflow interrupt in the TXFIFO in the write mode."]
1365 pub mod OVERFLOW_IRQ_EN {
1366 pub const offset: u32 = 15;
1367 pub const mask: u32 = 0x01 << offset;
1368 pub mod R {}
1369 pub mod W {}
1370 pub mod RW {}
1371 }
1372 #[doc = "This bitfield is used to show which data bytes in a 32-bit word are valid"]
1373 pub mod BYTE_PACKING_FORMAT {
1374 pub const offset: u32 = 16;
1375 pub const mask: u32 = 0x0f << offset;
1376 pub mod R {}
1377 pub mod W {}
1378 pub mod RW {}
1379 }
1380 #[doc = "If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field"]
1381 pub mod IRQ_ON_ALTERNATE_FIELDS {
1382 pub const offset: u32 = 20;
1383 pub const mask: u32 = 0x01 << offset;
1384 pub mod R {}
1385 pub mod W {}
1386 pub mod RW {}
1387 }
1388 #[doc = "Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO."]
1389 pub mod FIFO_CLEAR {
1390 pub const offset: u32 = 21;
1391 pub const mask: u32 = 0x01 << offset;
1392 pub mod R {}
1393 pub mod W {}
1394 pub mod RW {}
1395 }
1396 #[doc = "The default is to grab the odd lines first and then the even lines"]
1397 pub mod START_INTERLACE_FROM_SECOND_FIELD {
1398 pub const offset: u32 = 22;
1399 pub const mask: u32 = 0x01 << offset;
1400 pub mod R {}
1401 pub mod W {}
1402 pub mod RW {}
1403 }
1404 #[doc = "Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field"]
1405 pub mod INTERLACE_FIELDS {
1406 pub const offset: u32 = 23;
1407 pub const mask: u32 = 0x01 << offset;
1408 pub mod R {}
1409 pub mod W {}
1410 pub mod RW {}
1411 }
1412 #[doc = "Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame"]
1413 pub mod RECOVER_ON_UNDERFLOW {
1414 pub const offset: u32 = 24;
1415 pub const mask: u32 = 0x01 << offset;
1416 pub mod R {}
1417 pub mod W {}
1418 pub mod RW {}
1419 }
1420 #[doc = "This bit is set to indicate that an interrupt is requested by the LCDIF block"]
1421 pub mod BM_ERROR_IRQ {
1422 pub const offset: u32 = 25;
1423 pub const mask: u32 = 0x01 << offset;
1424 pub mod R {}
1425 pub mod W {}
1426 pub mod RW {
1427 #[doc = "No Interrupt Request Pending."]
1428 pub const NO_REQUEST: u32 = 0;
1429 #[doc = "Interrupt Request Pending."]
1430 pub const REQUEST: u32 = 0x01;
1431 }
1432 }
1433 #[doc = "This bit is set to enable bus master error interrupt in the LCDIF master mode."]
1434 pub mod BM_ERROR_IRQ_EN {
1435 pub const offset: u32 = 26;
1436 pub const mask: u32 = 0x01 << offset;
1437 pub mod R {}
1438 pub mod W {}
1439 pub mod RW {}
1440 }
1441 #[doc = "This bit is CS0/CS1 valid select signals"]
1442 pub mod CS_OUT_SELECT {
1443 pub const offset: u32 = 30;
1444 pub const mask: u32 = 0x01 << offset;
1445 pub mod R {}
1446 pub mod W {}
1447 pub mod RW {}
1448 }
1449 #[doc = "Command Mode MIPI image data select bit"]
1450 pub mod IMAGE_DATA_SELECT {
1451 pub const offset: u32 = 31;
1452 pub const mask: u32 = 0x01 << offset;
1453 pub mod R {}
1454 pub mod W {}
1455 pub mod RW {}
1456 }
1457}
1458#[doc = "LCDIF General Control1 Register"]
1459pub mod CTRL1_TOG {
1460 #[doc = "This bit is set to indicate that an interrupt is requested by the LCDIF block"]
1461 pub mod VSYNC_EDGE_IRQ {
1462 pub const offset: u32 = 8;
1463 pub const mask: u32 = 0x01 << offset;
1464 pub mod R {}
1465 pub mod W {}
1466 pub mod RW {
1467 #[doc = "No Interrupt Request Pending."]
1468 pub const NO_REQUEST: u32 = 0;
1469 #[doc = "Interrupt Request Pending."]
1470 pub const REQUEST: u32 = 0x01;
1471 }
1472 }
1473 #[doc = "This bit is set to indicate that an interrupt is requested by the LCDIF block"]
1474 pub mod CUR_FRAME_DONE_IRQ {
1475 pub const offset: u32 = 9;
1476 pub const mask: u32 = 0x01 << offset;
1477 pub mod R {}
1478 pub mod W {}
1479 pub mod RW {
1480 #[doc = "No Interrupt Request Pending."]
1481 pub const NO_REQUEST: u32 = 0;
1482 #[doc = "Interrupt Request Pending."]
1483 pub const REQUEST: u32 = 0x01;
1484 }
1485 }
1486 #[doc = "This bit is set to indicate that an interrupt is requested by the LCDIF block"]
1487 pub mod UNDERFLOW_IRQ {
1488 pub const offset: u32 = 10;
1489 pub const mask: u32 = 0x01 << offset;
1490 pub mod R {}
1491 pub mod W {}
1492 pub mod RW {
1493 #[doc = "No Interrupt Request Pending."]
1494 pub const NO_REQUEST: u32 = 0;
1495 #[doc = "Interrupt Request Pending."]
1496 pub const REQUEST: u32 = 0x01;
1497 }
1498 }
1499 #[doc = "This bit is set to indicate that an interrupt is requested by the LCDIF block"]
1500 pub mod OVERFLOW_IRQ {
1501 pub const offset: u32 = 11;
1502 pub const mask: u32 = 0x01 << offset;
1503 pub mod R {}
1504 pub mod W {}
1505 pub mod RW {
1506 #[doc = "No Interrupt Request Pending."]
1507 pub const NO_REQUEST: u32 = 0;
1508 #[doc = "Interrupt Request Pending."]
1509 pub const REQUEST: u32 = 0x01;
1510 }
1511 }
1512 #[doc = "This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode"]
1513 pub mod VSYNC_EDGE_IRQ_EN {
1514 pub const offset: u32 = 12;
1515 pub const mask: u32 = 0x01 << offset;
1516 pub mod R {}
1517 pub mod W {}
1518 pub mod RW {}
1519 }
1520 #[doc = "This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state"]
1521 pub mod CUR_FRAME_DONE_IRQ_EN {
1522 pub const offset: u32 = 13;
1523 pub const mask: u32 = 0x01 << offset;
1524 pub mod R {}
1525 pub mod W {}
1526 pub mod RW {}
1527 }
1528 #[doc = "This bit is set to enable an underflow interrupt in the TXFIFO in the write mode."]
1529 pub mod UNDERFLOW_IRQ_EN {
1530 pub const offset: u32 = 14;
1531 pub const mask: u32 = 0x01 << offset;
1532 pub mod R {}
1533 pub mod W {}
1534 pub mod RW {}
1535 }
1536 #[doc = "This bit is set to enable an overflow interrupt in the TXFIFO in the write mode."]
1537 pub mod OVERFLOW_IRQ_EN {
1538 pub const offset: u32 = 15;
1539 pub const mask: u32 = 0x01 << offset;
1540 pub mod R {}
1541 pub mod W {}
1542 pub mod RW {}
1543 }
1544 #[doc = "This bitfield is used to show which data bytes in a 32-bit word are valid"]
1545 pub mod BYTE_PACKING_FORMAT {
1546 pub const offset: u32 = 16;
1547 pub const mask: u32 = 0x0f << offset;
1548 pub mod R {}
1549 pub mod W {}
1550 pub mod RW {}
1551 }
1552 #[doc = "If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field"]
1553 pub mod IRQ_ON_ALTERNATE_FIELDS {
1554 pub const offset: u32 = 20;
1555 pub const mask: u32 = 0x01 << offset;
1556 pub mod R {}
1557 pub mod W {}
1558 pub mod RW {}
1559 }
1560 #[doc = "Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO."]
1561 pub mod FIFO_CLEAR {
1562 pub const offset: u32 = 21;
1563 pub const mask: u32 = 0x01 << offset;
1564 pub mod R {}
1565 pub mod W {}
1566 pub mod RW {}
1567 }
1568 #[doc = "The default is to grab the odd lines first and then the even lines"]
1569 pub mod START_INTERLACE_FROM_SECOND_FIELD {
1570 pub const offset: u32 = 22;
1571 pub const mask: u32 = 0x01 << offset;
1572 pub mod R {}
1573 pub mod W {}
1574 pub mod RW {}
1575 }
1576 #[doc = "Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field"]
1577 pub mod INTERLACE_FIELDS {
1578 pub const offset: u32 = 23;
1579 pub const mask: u32 = 0x01 << offset;
1580 pub mod R {}
1581 pub mod W {}
1582 pub mod RW {}
1583 }
1584 #[doc = "Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame"]
1585 pub mod RECOVER_ON_UNDERFLOW {
1586 pub const offset: u32 = 24;
1587 pub const mask: u32 = 0x01 << offset;
1588 pub mod R {}
1589 pub mod W {}
1590 pub mod RW {}
1591 }
1592 #[doc = "This bit is set to indicate that an interrupt is requested by the LCDIF block"]
1593 pub mod BM_ERROR_IRQ {
1594 pub const offset: u32 = 25;
1595 pub const mask: u32 = 0x01 << offset;
1596 pub mod R {}
1597 pub mod W {}
1598 pub mod RW {
1599 #[doc = "No Interrupt Request Pending."]
1600 pub const NO_REQUEST: u32 = 0;
1601 #[doc = "Interrupt Request Pending."]
1602 pub const REQUEST: u32 = 0x01;
1603 }
1604 }
1605 #[doc = "This bit is set to enable bus master error interrupt in the LCDIF master mode."]
1606 pub mod BM_ERROR_IRQ_EN {
1607 pub const offset: u32 = 26;
1608 pub const mask: u32 = 0x01 << offset;
1609 pub mod R {}
1610 pub mod W {}
1611 pub mod RW {}
1612 }
1613 #[doc = "This bit is CS0/CS1 valid select signals"]
1614 pub mod CS_OUT_SELECT {
1615 pub const offset: u32 = 30;
1616 pub const mask: u32 = 0x01 << offset;
1617 pub mod R {}
1618 pub mod W {}
1619 pub mod RW {}
1620 }
1621 #[doc = "Command Mode MIPI image data select bit"]
1622 pub mod IMAGE_DATA_SELECT {
1623 pub const offset: u32 = 31;
1624 pub const mask: u32 = 0x01 << offset;
1625 pub mod R {}
1626 pub mod W {}
1627 pub mod RW {}
1628 }
1629}
1630#[doc = "LCDIF General Control2 Register"]
1631pub mod CTRL2 {
1632 #[doc = "This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6,"]
1633 pub mod EVEN_LINE_PATTERN {
1634 pub const offset: u32 = 12;
1635 pub const mask: u32 = 0x07 << offset;
1636 pub mod R {}
1637 pub mod W {}
1638 pub mod RW {
1639 #[doc = "RGB"]
1640 pub const RGB: u32 = 0;
1641 #[doc = "RBG"]
1642 pub const RBG: u32 = 0x01;
1643 #[doc = "GBR"]
1644 pub const GBR: u32 = 0x02;
1645 #[doc = "GRB"]
1646 pub const GRB: u32 = 0x03;
1647 #[doc = "BRG"]
1648 pub const BRG: u32 = 0x04;
1649 #[doc = "BGR"]
1650 pub const BGR: u32 = 0x05;
1651 }
1652 }
1653 #[doc = "This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5,"]
1654 pub mod ODD_LINE_PATTERN {
1655 pub const offset: u32 = 16;
1656 pub const mask: u32 = 0x07 << offset;
1657 pub mod R {}
1658 pub mod W {}
1659 pub mod RW {
1660 #[doc = "RGB"]
1661 pub const RGB: u32 = 0;
1662 #[doc = "RBG"]
1663 pub const RBG: u32 = 0x01;
1664 #[doc = "GBR"]
1665 pub const GBR: u32 = 0x02;
1666 #[doc = "GRB"]
1667 pub const GRB: u32 = 0x03;
1668 #[doc = "BRG"]
1669 pub const BRG: u32 = 0x04;
1670 #[doc = "BGR"]
1671 pub const BGR: u32 = 0x05;
1672 }
1673 }
1674 #[doc = "By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15)"]
1675 pub mod BURST_LEN_8 {
1676 pub const offset: u32 = 20;
1677 pub const mask: u32 = 0x01 << offset;
1678 pub mod R {}
1679 pub mod W {}
1680 pub mod RW {}
1681 }
1682 #[doc = "This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master"]
1683 pub mod OUTSTANDING_REQS {
1684 pub const offset: u32 = 21;
1685 pub const mask: u32 = 0x07 << offset;
1686 pub mod R {}
1687 pub mod W {}
1688 pub mod RW {
1689 #[doc = "REQ_1"]
1690 pub const REQ_1: u32 = 0;
1691 #[doc = "REQ_2"]
1692 pub const REQ_2: u32 = 0x01;
1693 #[doc = "REQ_4"]
1694 pub const REQ_4: u32 = 0x02;
1695 #[doc = "REQ_8"]
1696 pub const REQ_8: u32 = 0x03;
1697 #[doc = "REQ_16"]
1698 pub const REQ_16: u32 = 0x04;
1699 }
1700 }
1701}
1702#[doc = "LCDIF General Control2 Register"]
1703pub mod CTRL2_SET {
1704 #[doc = "This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6,"]
1705 pub mod EVEN_LINE_PATTERN {
1706 pub const offset: u32 = 12;
1707 pub const mask: u32 = 0x07 << offset;
1708 pub mod R {}
1709 pub mod W {}
1710 pub mod RW {
1711 #[doc = "RGB"]
1712 pub const RGB: u32 = 0;
1713 #[doc = "RBG"]
1714 pub const RBG: u32 = 0x01;
1715 #[doc = "GBR"]
1716 pub const GBR: u32 = 0x02;
1717 #[doc = "GRB"]
1718 pub const GRB: u32 = 0x03;
1719 #[doc = "BRG"]
1720 pub const BRG: u32 = 0x04;
1721 #[doc = "BGR"]
1722 pub const BGR: u32 = 0x05;
1723 }
1724 }
1725 #[doc = "This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5,"]
1726 pub mod ODD_LINE_PATTERN {
1727 pub const offset: u32 = 16;
1728 pub const mask: u32 = 0x07 << offset;
1729 pub mod R {}
1730 pub mod W {}
1731 pub mod RW {
1732 #[doc = "RGB"]
1733 pub const RGB: u32 = 0;
1734 #[doc = "RBG"]
1735 pub const RBG: u32 = 0x01;
1736 #[doc = "GBR"]
1737 pub const GBR: u32 = 0x02;
1738 #[doc = "GRB"]
1739 pub const GRB: u32 = 0x03;
1740 #[doc = "BRG"]
1741 pub const BRG: u32 = 0x04;
1742 #[doc = "BGR"]
1743 pub const BGR: u32 = 0x05;
1744 }
1745 }
1746 #[doc = "By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15)"]
1747 pub mod BURST_LEN_8 {
1748 pub const offset: u32 = 20;
1749 pub const mask: u32 = 0x01 << offset;
1750 pub mod R {}
1751 pub mod W {}
1752 pub mod RW {}
1753 }
1754 #[doc = "This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master"]
1755 pub mod OUTSTANDING_REQS {
1756 pub const offset: u32 = 21;
1757 pub const mask: u32 = 0x07 << offset;
1758 pub mod R {}
1759 pub mod W {}
1760 pub mod RW {
1761 #[doc = "REQ_1"]
1762 pub const REQ_1: u32 = 0;
1763 #[doc = "REQ_2"]
1764 pub const REQ_2: u32 = 0x01;
1765 #[doc = "REQ_4"]
1766 pub const REQ_4: u32 = 0x02;
1767 #[doc = "REQ_8"]
1768 pub const REQ_8: u32 = 0x03;
1769 #[doc = "REQ_16"]
1770 pub const REQ_16: u32 = 0x04;
1771 }
1772 }
1773}
1774#[doc = "LCDIF General Control2 Register"]
1775pub mod CTRL2_CLR {
1776 #[doc = "This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6,"]
1777 pub mod EVEN_LINE_PATTERN {
1778 pub const offset: u32 = 12;
1779 pub const mask: u32 = 0x07 << offset;
1780 pub mod R {}
1781 pub mod W {}
1782 pub mod RW {
1783 #[doc = "RGB"]
1784 pub const RGB: u32 = 0;
1785 #[doc = "RBG"]
1786 pub const RBG: u32 = 0x01;
1787 #[doc = "GBR"]
1788 pub const GBR: u32 = 0x02;
1789 #[doc = "GRB"]
1790 pub const GRB: u32 = 0x03;
1791 #[doc = "BRG"]
1792 pub const BRG: u32 = 0x04;
1793 #[doc = "BGR"]
1794 pub const BGR: u32 = 0x05;
1795 }
1796 }
1797 #[doc = "This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5,"]
1798 pub mod ODD_LINE_PATTERN {
1799 pub const offset: u32 = 16;
1800 pub const mask: u32 = 0x07 << offset;
1801 pub mod R {}
1802 pub mod W {}
1803 pub mod RW {
1804 #[doc = "RGB"]
1805 pub const RGB: u32 = 0;
1806 #[doc = "RBG"]
1807 pub const RBG: u32 = 0x01;
1808 #[doc = "GBR"]
1809 pub const GBR: u32 = 0x02;
1810 #[doc = "GRB"]
1811 pub const GRB: u32 = 0x03;
1812 #[doc = "BRG"]
1813 pub const BRG: u32 = 0x04;
1814 #[doc = "BGR"]
1815 pub const BGR: u32 = 0x05;
1816 }
1817 }
1818 #[doc = "By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15)"]
1819 pub mod BURST_LEN_8 {
1820 pub const offset: u32 = 20;
1821 pub const mask: u32 = 0x01 << offset;
1822 pub mod R {}
1823 pub mod W {}
1824 pub mod RW {}
1825 }
1826 #[doc = "This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master"]
1827 pub mod OUTSTANDING_REQS {
1828 pub const offset: u32 = 21;
1829 pub const mask: u32 = 0x07 << offset;
1830 pub mod R {}
1831 pub mod W {}
1832 pub mod RW {
1833 #[doc = "REQ_1"]
1834 pub const REQ_1: u32 = 0;
1835 #[doc = "REQ_2"]
1836 pub const REQ_2: u32 = 0x01;
1837 #[doc = "REQ_4"]
1838 pub const REQ_4: u32 = 0x02;
1839 #[doc = "REQ_8"]
1840 pub const REQ_8: u32 = 0x03;
1841 #[doc = "REQ_16"]
1842 pub const REQ_16: u32 = 0x04;
1843 }
1844 }
1845}
1846#[doc = "LCDIF General Control2 Register"]
1847pub mod CTRL2_TOG {
1848 #[doc = "This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6,"]
1849 pub mod EVEN_LINE_PATTERN {
1850 pub const offset: u32 = 12;
1851 pub const mask: u32 = 0x07 << offset;
1852 pub mod R {}
1853 pub mod W {}
1854 pub mod RW {
1855 #[doc = "RGB"]
1856 pub const RGB: u32 = 0;
1857 #[doc = "RBG"]
1858 pub const RBG: u32 = 0x01;
1859 #[doc = "GBR"]
1860 pub const GBR: u32 = 0x02;
1861 #[doc = "GRB"]
1862 pub const GRB: u32 = 0x03;
1863 #[doc = "BRG"]
1864 pub const BRG: u32 = 0x04;
1865 #[doc = "BGR"]
1866 pub const BGR: u32 = 0x05;
1867 }
1868 }
1869 #[doc = "This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5,"]
1870 pub mod ODD_LINE_PATTERN {
1871 pub const offset: u32 = 16;
1872 pub const mask: u32 = 0x07 << offset;
1873 pub mod R {}
1874 pub mod W {}
1875 pub mod RW {
1876 #[doc = "RGB"]
1877 pub const RGB: u32 = 0;
1878 #[doc = "RBG"]
1879 pub const RBG: u32 = 0x01;
1880 #[doc = "GBR"]
1881 pub const GBR: u32 = 0x02;
1882 #[doc = "GRB"]
1883 pub const GRB: u32 = 0x03;
1884 #[doc = "BRG"]
1885 pub const BRG: u32 = 0x04;
1886 #[doc = "BGR"]
1887 pub const BGR: u32 = 0x05;
1888 }
1889 }
1890 #[doc = "By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15)"]
1891 pub mod BURST_LEN_8 {
1892 pub const offset: u32 = 20;
1893 pub const mask: u32 = 0x01 << offset;
1894 pub mod R {}
1895 pub mod W {}
1896 pub mod RW {}
1897 }
1898 #[doc = "This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when it is acting as a bus master"]
1899 pub mod OUTSTANDING_REQS {
1900 pub const offset: u32 = 21;
1901 pub const mask: u32 = 0x07 << offset;
1902 pub mod R {}
1903 pub mod W {}
1904 pub mod RW {
1905 #[doc = "REQ_1"]
1906 pub const REQ_1: u32 = 0;
1907 #[doc = "REQ_2"]
1908 pub const REQ_2: u32 = 0x01;
1909 #[doc = "REQ_4"]
1910 pub const REQ_4: u32 = 0x02;
1911 #[doc = "REQ_8"]
1912 pub const REQ_8: u32 = 0x03;
1913 #[doc = "REQ_16"]
1914 pub const REQ_16: u32 = 0x04;
1915 }
1916 }
1917}
1918#[doc = "LCDIF Horizontal and Vertical Valid Data Count Register"]
1919pub mod TRANSFER_COUNT {
1920 #[doc = "Total valid data (pixels) in each horizontal line"]
1921 pub mod H_COUNT {
1922 pub const offset: u32 = 0;
1923 pub const mask: u32 = 0xffff << offset;
1924 pub mod R {}
1925 pub mod W {}
1926 pub mod RW {}
1927 }
1928 #[doc = "Number of horizontal lines per frame which contain valid data"]
1929 pub mod V_COUNT {
1930 pub const offset: u32 = 16;
1931 pub const mask: u32 = 0xffff << offset;
1932 pub mod R {}
1933 pub mod W {}
1934 pub mod RW {}
1935 }
1936}
1937#[doc = "LCD Interface Current Buffer Address Register"]
1938pub mod CUR_BUF {
1939 #[doc = "Address of the current frame being transmitted by LCDIF."]
1940 pub mod ADDR {
1941 pub const offset: u32 = 0;
1942 pub const mask: u32 = 0xffff_ffff << offset;
1943 pub mod R {}
1944 pub mod W {}
1945 pub mod RW {}
1946 }
1947}
1948#[doc = "LCD Interface Next Buffer Address Register"]
1949pub mod NEXT_BUF {
1950 #[doc = "Address of the next frame that will be transmitted by LCDIF."]
1951 pub mod ADDR {
1952 pub const offset: u32 = 0;
1953 pub const mask: u32 = 0xffff_ffff << offset;
1954 pub mod R {}
1955 pub mod W {}
1956 pub mod RW {}
1957 }
1958}
1959#[doc = "LCDIF VSYNC Mode and Dotclk Mode Control Register0"]
1960pub mod VDCTRL0 {
1961 #[doc = "Number of units for which VSYNC signal is active"]
1962 pub mod VSYNC_PULSE_WIDTH {
1963 pub const offset: u32 = 0;
1964 pub const mask: u32 = 0x0003_ffff << offset;
1965 pub mod R {}
1966 pub mod W {}
1967 pub mod RW {}
1968 }
1969 #[doc = "When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line"]
1970 pub mod HALF_LINE_MODE {
1971 pub const offset: u32 = 18;
1972 pub const mask: u32 = 0x01 << offset;
1973 pub mod R {}
1974 pub mod W {}
1975 pub mod RW {}
1976 }
1977 #[doc = "Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i"]
1978 pub mod HALF_LINE {
1979 pub const offset: u32 = 19;
1980 pub const mask: u32 = 0x01 << offset;
1981 pub mod R {}
1982 pub mod W {}
1983 pub mod RW {}
1984 }
1985 #[doc = "Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles"]
1986 pub mod VSYNC_PULSE_WIDTH_UNIT {
1987 pub const offset: u32 = 20;
1988 pub const mask: u32 = 0x01 << offset;
1989 pub mod R {}
1990 pub mod W {}
1991 pub mod RW {}
1992 }
1993 #[doc = "Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles"]
1994 pub mod VSYNC_PERIOD_UNIT {
1995 pub const offset: u32 = 21;
1996 pub const mask: u32 = 0x01 << offset;
1997 pub mod R {}
1998 pub mod W {}
1999 pub mod RW {}
2000 }
2001 #[doc = "Default 0 active low during valid data transfer on each horizontal line."]
2002 pub mod ENABLE_POL {
2003 pub const offset: u32 = 24;
2004 pub const mask: u32 = 0x01 << offset;
2005 pub mod R {}
2006 pub mod W {}
2007 pub mod RW {}
2008 }
2009 #[doc = "Default is data launched at negative edge of DOTCLK and captured at positive edge"]
2010 pub mod DOTCLK_POL {
2011 pub const offset: u32 = 25;
2012 pub const mask: u32 = 0x01 << offset;
2013 pub mod R {}
2014 pub mod W {}
2015 pub mod RW {}
2016 }
2017 #[doc = "Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period"]
2018 pub mod HSYNC_POL {
2019 pub const offset: u32 = 26;
2020 pub const mask: u32 = 0x01 << offset;
2021 pub mod R {}
2022 pub mod W {}
2023 pub mod RW {}
2024 }
2025 #[doc = "Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period"]
2026 pub mod VSYNC_POL {
2027 pub const offset: u32 = 27;
2028 pub const mask: u32 = 0x01 << offset;
2029 pub mod R {}
2030 pub mod W {}
2031 pub mod RW {}
2032 }
2033 #[doc = "Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK"]
2034 pub mod ENABLE_PRESENT {
2035 pub const offset: u32 = 28;
2036 pub const mask: u32 = 0x01 << offset;
2037 pub mod R {}
2038 pub mod W {}
2039 pub mod RW {}
2040 }
2041}
2042#[doc = "LCDIF VSYNC Mode and Dotclk Mode Control Register0"]
2043pub mod VDCTRL0_SET {
2044 #[doc = "Number of units for which VSYNC signal is active"]
2045 pub mod VSYNC_PULSE_WIDTH {
2046 pub const offset: u32 = 0;
2047 pub const mask: u32 = 0x0003_ffff << offset;
2048 pub mod R {}
2049 pub mod W {}
2050 pub mod RW {}
2051 }
2052 #[doc = "When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line"]
2053 pub mod HALF_LINE_MODE {
2054 pub const offset: u32 = 18;
2055 pub const mask: u32 = 0x01 << offset;
2056 pub mod R {}
2057 pub mod W {}
2058 pub mod RW {}
2059 }
2060 #[doc = "Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i"]
2061 pub mod HALF_LINE {
2062 pub const offset: u32 = 19;
2063 pub const mask: u32 = 0x01 << offset;
2064 pub mod R {}
2065 pub mod W {}
2066 pub mod RW {}
2067 }
2068 #[doc = "Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles"]
2069 pub mod VSYNC_PULSE_WIDTH_UNIT {
2070 pub const offset: u32 = 20;
2071 pub const mask: u32 = 0x01 << offset;
2072 pub mod R {}
2073 pub mod W {}
2074 pub mod RW {}
2075 }
2076 #[doc = "Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles"]
2077 pub mod VSYNC_PERIOD_UNIT {
2078 pub const offset: u32 = 21;
2079 pub const mask: u32 = 0x01 << offset;
2080 pub mod R {}
2081 pub mod W {}
2082 pub mod RW {}
2083 }
2084 #[doc = "Default 0 active low during valid data transfer on each horizontal line."]
2085 pub mod ENABLE_POL {
2086 pub const offset: u32 = 24;
2087 pub const mask: u32 = 0x01 << offset;
2088 pub mod R {}
2089 pub mod W {}
2090 pub mod RW {}
2091 }
2092 #[doc = "Default is data launched at negative edge of DOTCLK and captured at positive edge"]
2093 pub mod DOTCLK_POL {
2094 pub const offset: u32 = 25;
2095 pub const mask: u32 = 0x01 << offset;
2096 pub mod R {}
2097 pub mod W {}
2098 pub mod RW {}
2099 }
2100 #[doc = "Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period"]
2101 pub mod HSYNC_POL {
2102 pub const offset: u32 = 26;
2103 pub const mask: u32 = 0x01 << offset;
2104 pub mod R {}
2105 pub mod W {}
2106 pub mod RW {}
2107 }
2108 #[doc = "Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period"]
2109 pub mod VSYNC_POL {
2110 pub const offset: u32 = 27;
2111 pub const mask: u32 = 0x01 << offset;
2112 pub mod R {}
2113 pub mod W {}
2114 pub mod RW {}
2115 }
2116 #[doc = "Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK"]
2117 pub mod ENABLE_PRESENT {
2118 pub const offset: u32 = 28;
2119 pub const mask: u32 = 0x01 << offset;
2120 pub mod R {}
2121 pub mod W {}
2122 pub mod RW {}
2123 }
2124}
2125#[doc = "LCDIF VSYNC Mode and Dotclk Mode Control Register0"]
2126pub mod VDCTRL0_CLR {
2127 #[doc = "Number of units for which VSYNC signal is active"]
2128 pub mod VSYNC_PULSE_WIDTH {
2129 pub const offset: u32 = 0;
2130 pub const mask: u32 = 0x0003_ffff << offset;
2131 pub mod R {}
2132 pub mod W {}
2133 pub mod RW {}
2134 }
2135 #[doc = "When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line"]
2136 pub mod HALF_LINE_MODE {
2137 pub const offset: u32 = 18;
2138 pub const mask: u32 = 0x01 << offset;
2139 pub mod R {}
2140 pub mod W {}
2141 pub mod RW {}
2142 }
2143 #[doc = "Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i"]
2144 pub mod HALF_LINE {
2145 pub const offset: u32 = 19;
2146 pub const mask: u32 = 0x01 << offset;
2147 pub mod R {}
2148 pub mod W {}
2149 pub mod RW {}
2150 }
2151 #[doc = "Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles"]
2152 pub mod VSYNC_PULSE_WIDTH_UNIT {
2153 pub const offset: u32 = 20;
2154 pub const mask: u32 = 0x01 << offset;
2155 pub mod R {}
2156 pub mod W {}
2157 pub mod RW {}
2158 }
2159 #[doc = "Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles"]
2160 pub mod VSYNC_PERIOD_UNIT {
2161 pub const offset: u32 = 21;
2162 pub const mask: u32 = 0x01 << offset;
2163 pub mod R {}
2164 pub mod W {}
2165 pub mod RW {}
2166 }
2167 #[doc = "Default 0 active low during valid data transfer on each horizontal line."]
2168 pub mod ENABLE_POL {
2169 pub const offset: u32 = 24;
2170 pub const mask: u32 = 0x01 << offset;
2171 pub mod R {}
2172 pub mod W {}
2173 pub mod RW {}
2174 }
2175 #[doc = "Default is data launched at negative edge of DOTCLK and captured at positive edge"]
2176 pub mod DOTCLK_POL {
2177 pub const offset: u32 = 25;
2178 pub const mask: u32 = 0x01 << offset;
2179 pub mod R {}
2180 pub mod W {}
2181 pub mod RW {}
2182 }
2183 #[doc = "Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period"]
2184 pub mod HSYNC_POL {
2185 pub const offset: u32 = 26;
2186 pub const mask: u32 = 0x01 << offset;
2187 pub mod R {}
2188 pub mod W {}
2189 pub mod RW {}
2190 }
2191 #[doc = "Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period"]
2192 pub mod VSYNC_POL {
2193 pub const offset: u32 = 27;
2194 pub const mask: u32 = 0x01 << offset;
2195 pub mod R {}
2196 pub mod W {}
2197 pub mod RW {}
2198 }
2199 #[doc = "Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK"]
2200 pub mod ENABLE_PRESENT {
2201 pub const offset: u32 = 28;
2202 pub const mask: u32 = 0x01 << offset;
2203 pub mod R {}
2204 pub mod W {}
2205 pub mod RW {}
2206 }
2207}
2208#[doc = "LCDIF VSYNC Mode and Dotclk Mode Control Register0"]
2209pub mod VDCTRL0_TOG {
2210 #[doc = "Number of units for which VSYNC signal is active"]
2211 pub mod VSYNC_PULSE_WIDTH {
2212 pub const offset: u32 = 0;
2213 pub const mask: u32 = 0x0003_ffff << offset;
2214 pub mod R {}
2215 pub mod W {}
2216 pub mod RW {}
2217 }
2218 #[doc = "When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line"]
2219 pub mod HALF_LINE_MODE {
2220 pub const offset: u32 = 18;
2221 pub const mask: u32 = 0x01 << offset;
2222 pub mod R {}
2223 pub mod W {}
2224 pub mod RW {}
2225 }
2226 #[doc = "Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i"]
2227 pub mod HALF_LINE {
2228 pub const offset: u32 = 19;
2229 pub const mask: u32 = 0x01 << offset;
2230 pub mod R {}
2231 pub mod W {}
2232 pub mod RW {}
2233 }
2234 #[doc = "Default 0 for counting VSYNC_PULSE_WIDTH in terms of DISPLAY CLOCK (pix_clk) cycles"]
2235 pub mod VSYNC_PULSE_WIDTH_UNIT {
2236 pub const offset: u32 = 20;
2237 pub const mask: u32 = 0x01 << offset;
2238 pub mod R {}
2239 pub mod W {}
2240 pub mod RW {}
2241 }
2242 #[doc = "Default 0 for counting VSYNC_PERIOD in terms of DISPLAY CLOCK (pix_clk) cycles"]
2243 pub mod VSYNC_PERIOD_UNIT {
2244 pub const offset: u32 = 21;
2245 pub const mask: u32 = 0x01 << offset;
2246 pub mod R {}
2247 pub mod W {}
2248 pub mod RW {}
2249 }
2250 #[doc = "Default 0 active low during valid data transfer on each horizontal line."]
2251 pub mod ENABLE_POL {
2252 pub const offset: u32 = 24;
2253 pub const mask: u32 = 0x01 << offset;
2254 pub mod R {}
2255 pub mod W {}
2256 pub mod RW {}
2257 }
2258 #[doc = "Default is data launched at negative edge of DOTCLK and captured at positive edge"]
2259 pub mod DOTCLK_POL {
2260 pub const offset: u32 = 25;
2261 pub const mask: u32 = 0x01 << offset;
2262 pub mod R {}
2263 pub mod W {}
2264 pub mod RW {}
2265 }
2266 #[doc = "Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period"]
2267 pub mod HSYNC_POL {
2268 pub const offset: u32 = 26;
2269 pub const mask: u32 = 0x01 << offset;
2270 pub mod R {}
2271 pub mod W {}
2272 pub mod RW {}
2273 }
2274 #[doc = "Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period"]
2275 pub mod VSYNC_POL {
2276 pub const offset: u32 = 27;
2277 pub const mask: u32 = 0x01 << offset;
2278 pub mod R {}
2279 pub mod W {}
2280 pub mod RW {}
2281 }
2282 #[doc = "Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK"]
2283 pub mod ENABLE_PRESENT {
2284 pub const offset: u32 = 28;
2285 pub const mask: u32 = 0x01 << offset;
2286 pub mod R {}
2287 pub mod W {}
2288 pub mod RW {}
2289 }
2290}
2291#[doc = "LCDIF VSYNC Mode and Dotclk Mode Control Register1"]
2292pub mod VDCTRL1 {
2293 #[doc = "Total number of units between two positive or two negative edges of the VSYNC signal"]
2294 pub mod VSYNC_PERIOD {
2295 pub const offset: u32 = 0;
2296 pub const mask: u32 = 0xffff_ffff << offset;
2297 pub mod R {}
2298 pub mod W {}
2299 pub mod RW {}
2300 }
2301}
2302#[doc = "LCDIF VSYNC Mode and Dotclk Mode Control Register2"]
2303pub mod VDCTRL2 {
2304 #[doc = "Total number of DISPLAY CLOCK (pix_clk) cycles between two positive or two negative edges of the HSYNC signal"]
2305 pub mod HSYNC_PERIOD {
2306 pub const offset: u32 = 0;
2307 pub const mask: u32 = 0x0003_ffff << offset;
2308 pub mod R {}
2309 pub mod W {}
2310 pub mod RW {}
2311 }
2312 #[doc = "Number of DISPLAY CLOCK (pix_clk) cycles for which HSYNC signal is active."]
2313 pub mod HSYNC_PULSE_WIDTH {
2314 pub const offset: u32 = 18;
2315 pub const mask: u32 = 0x3fff << offset;
2316 pub mod R {}
2317 pub mod W {}
2318 pub mod RW {}
2319 }
2320}
2321#[doc = "LCDIF VSYNC Mode and Dotclk Mode Control Register3"]
2322pub mod VDCTRL3 {
2323 #[doc = "In the VSYNC interface mode, wait for this number of DISPLAY CLOCK (pix_clk) cycles from the falling VSYNC edge (or rising if VSYNC_POL is 1) before starting LCD transactions and is applicable only if WAIT_FOR_VSYNC_EDGE is set"]
2324 pub mod VERTICAL_WAIT_CNT {
2325 pub const offset: u32 = 0;
2326 pub const mask: u32 = 0xffff << offset;
2327 pub mod R {}
2328 pub mod W {}
2329 pub mod RW {}
2330 }
2331 #[doc = "In the DOTCLK mode, wait for this number of clocks from falling edge (or rising if HSYNC_POL is 1) of HSYNC signal to account for horizontal back porch plus the number of DOTCLKs before the moving picture information begins"]
2332 pub mod HORIZONTAL_WAIT_CNT {
2333 pub const offset: u32 = 16;
2334 pub const mask: u32 = 0x0fff << offset;
2335 pub mod R {}
2336 pub mod W {}
2337 pub mod RW {}
2338 }
2339 #[doc = "This bit must be set to 1 in the VSYNC mode of operation, and 0 in the DOTCLK mode of operation."]
2340 pub mod VSYNC_ONLY {
2341 pub const offset: u32 = 28;
2342 pub const mask: u32 = 0x01 << offset;
2343 pub mod R {}
2344 pub mod W {}
2345 pub mod RW {}
2346 }
2347 #[doc = "When this bit is set, the LCDIF block will internally mux HSYNC with LCD_D14, DOTCLK with LCD_D13 and ENABLE with LCD_D12, otherwise these signals will go out on separate pins"]
2348 pub mod MUX_SYNC_SIGNALS {
2349 pub const offset: u32 = 29;
2350 pub const mask: u32 = 0x01 << offset;
2351 pub mod R {}
2352 pub mod W {}
2353 pub mod RW {}
2354 }
2355}
2356#[doc = "LCDIF VSYNC Mode and Dotclk Mode Control Register4"]
2357pub mod VDCTRL4 {
2358 #[doc = "Total number of DISPLAY CLOCK (pix_clk) cycles on each horizontal line that carry valid data in DOTCLK mode"]
2359 pub mod DOTCLK_H_VALID_DATA_CNT {
2360 pub const offset: u32 = 0;
2361 pub const mask: u32 = 0x0003_ffff << offset;
2362 pub mod R {}
2363 pub mod W {}
2364 pub mod RW {}
2365 }
2366 #[doc = "Set this field to 1 if the LCD controller requires that the VSYNC or VSYNC/HSYNC/DOTCLK control signals should be active at least one frame before the data transfers actually start and remain active at least one frame after the data transfers end"]
2367 pub mod SYNC_SIGNALS_ON {
2368 pub const offset: u32 = 18;
2369 pub const mask: u32 = 0x01 << offset;
2370 pub mod R {}
2371 pub mod W {}
2372 pub mod RW {}
2373 }
2374 #[doc = "This bitfield selects the amount of time by which the DOTCLK signal should be delayed before coming out of the LCD_DOTCK pin"]
2375 pub mod DOTCLK_DLY_SEL {
2376 pub const offset: u32 = 29;
2377 pub const mask: u32 = 0x07 << offset;
2378 pub mod R {}
2379 pub mod W {}
2380 pub mod RW {}
2381 }
2382}
2383#[doc = "Bus Master Error Status Register"]
2384pub mod BM_ERROR_STAT {
2385 #[doc = "Virtual address at which bus master error occurred."]
2386 pub mod ADDR {
2387 pub const offset: u32 = 0;
2388 pub const mask: u32 = 0xffff_ffff << offset;
2389 pub mod R {}
2390 pub mod W {}
2391 pub mod RW {}
2392 }
2393}
2394#[doc = "CRC Status Register"]
2395pub mod CRC_STAT {
2396 #[doc = "Calculated CRC value."]
2397 pub mod CRC_VALUE {
2398 pub const offset: u32 = 0;
2399 pub const mask: u32 = 0xffff_ffff << offset;
2400 pub mod R {}
2401 pub mod W {}
2402 pub mod RW {}
2403 }
2404}
2405#[doc = "LCD Interface Status Register"]
2406pub mod STAT {
2407 #[doc = "Read only view of the current count in Latency buffer (LFIFO)."]
2408 pub mod LFIFO_COUNT {
2409 pub const offset: u32 = 0;
2410 pub const mask: u32 = 0x01ff << offset;
2411 pub mod R {}
2412 pub mod W {}
2413 pub mod RW {}
2414 }
2415 #[doc = "Read only view of the signals that indicates LCD TXFIFO is empty."]
2416 pub mod TXFIFO_EMPTY {
2417 pub const offset: u32 = 26;
2418 pub const mask: u32 = 0x01 << offset;
2419 pub mod R {}
2420 pub mod W {}
2421 pub mod RW {}
2422 }
2423 #[doc = "Read only view of the signals that indicates LCD TXFIFO is full."]
2424 pub mod TXFIFO_FULL {
2425 pub const offset: u32 = 27;
2426 pub const mask: u32 = 0x01 << offset;
2427 pub mod R {}
2428 pub mod W {}
2429 pub mod RW {}
2430 }
2431 #[doc = "Read only view of the signals that indicates LCD LFIFO is empty."]
2432 pub mod LFIFO_EMPTY {
2433 pub const offset: u32 = 28;
2434 pub const mask: u32 = 0x01 << offset;
2435 pub mod R {}
2436 pub mod W {}
2437 pub mod RW {}
2438 }
2439 #[doc = "Read only view of the signals that indicates LCD LFIFO is full."]
2440 pub mod LFIFO_FULL {
2441 pub const offset: u32 = 29;
2442 pub const mask: u32 = 0x01 << offset;
2443 pub mod R {}
2444 pub mod W {}
2445 pub mod RW {}
2446 }
2447 #[doc = "Reflects the current state of the DMA Request line for the LCDIF"]
2448 pub mod DMA_REQ {
2449 pub const offset: u32 = 30;
2450 pub const mask: u32 = 0x01 << offset;
2451 pub mod R {}
2452 pub mod W {}
2453 pub mod RW {}
2454 }
2455 #[doc = "0: LCDIF not present on this product 1: LCDIF is present."]
2456 pub mod PRESENT {
2457 pub const offset: u32 = 31;
2458 pub const mask: u32 = 0x01 << offset;
2459 pub mod R {}
2460 pub mod W {}
2461 pub mod RW {}
2462 }
2463}
2464#[doc = "LCDIF Pigeon Mode Control0 Register"]
2465pub mod PIGEONCTRL0 {
2466 #[doc = "Period of line counter during FD phase"]
2467 pub mod FD_PERIOD {
2468 pub const offset: u32 = 0;
2469 pub const mask: u32 = 0x0fff << offset;
2470 pub mod R {}
2471 pub mod W {}
2472 pub mod RW {}
2473 }
2474 #[doc = "Period of pclk counter during LD phase"]
2475 pub mod LD_PERIOD {
2476 pub const offset: u32 = 16;
2477 pub const mask: u32 = 0x0fff << offset;
2478 pub mod R {}
2479 pub mod W {}
2480 pub mod RW {}
2481 }
2482}
2483#[doc = "LCDIF Pigeon Mode Control0 Register"]
2484pub mod PIGEONCTRL0_SET {
2485 #[doc = "Period of line counter during FD phase"]
2486 pub mod FD_PERIOD {
2487 pub const offset: u32 = 0;
2488 pub const mask: u32 = 0x0fff << offset;
2489 pub mod R {}
2490 pub mod W {}
2491 pub mod RW {}
2492 }
2493 #[doc = "Period of pclk counter during LD phase"]
2494 pub mod LD_PERIOD {
2495 pub const offset: u32 = 16;
2496 pub const mask: u32 = 0x0fff << offset;
2497 pub mod R {}
2498 pub mod W {}
2499 pub mod RW {}
2500 }
2501}
2502#[doc = "LCDIF Pigeon Mode Control0 Register"]
2503pub mod PIGEONCTRL0_CLR {
2504 #[doc = "Period of line counter during FD phase"]
2505 pub mod FD_PERIOD {
2506 pub const offset: u32 = 0;
2507 pub const mask: u32 = 0x0fff << offset;
2508 pub mod R {}
2509 pub mod W {}
2510 pub mod RW {}
2511 }
2512 #[doc = "Period of pclk counter during LD phase"]
2513 pub mod LD_PERIOD {
2514 pub const offset: u32 = 16;
2515 pub const mask: u32 = 0x0fff << offset;
2516 pub mod R {}
2517 pub mod W {}
2518 pub mod RW {}
2519 }
2520}
2521#[doc = "LCDIF Pigeon Mode Control0 Register"]
2522pub mod PIGEONCTRL0_TOG {
2523 #[doc = "Period of line counter during FD phase"]
2524 pub mod FD_PERIOD {
2525 pub const offset: u32 = 0;
2526 pub const mask: u32 = 0x0fff << offset;
2527 pub mod R {}
2528 pub mod W {}
2529 pub mod RW {}
2530 }
2531 #[doc = "Period of pclk counter during LD phase"]
2532 pub mod LD_PERIOD {
2533 pub const offset: u32 = 16;
2534 pub const mask: u32 = 0x0fff << offset;
2535 pub mod R {}
2536 pub mod W {}
2537 pub mod RW {}
2538 }
2539}
2540#[doc = "LCDIF Pigeon Mode Control1 Register"]
2541pub mod PIGEONCTRL1 {
2542 #[doc = "Period of frame counter"]
2543 pub mod FRAME_CNT_PERIOD {
2544 pub const offset: u32 = 0;
2545 pub const mask: u32 = 0x0fff << offset;
2546 pub mod R {}
2547 pub mod W {}
2548 pub mod RW {}
2549 }
2550 #[doc = "Max cycles of frame counter"]
2551 pub mod FRAME_CNT_CYCLES {
2552 pub const offset: u32 = 16;
2553 pub const mask: u32 = 0x0fff << offset;
2554 pub mod R {}
2555 pub mod W {}
2556 pub mod RW {}
2557 }
2558}
2559#[doc = "LCDIF Pigeon Mode Control1 Register"]
2560pub mod PIGEONCTRL1_SET {
2561 #[doc = "Period of frame counter"]
2562 pub mod FRAME_CNT_PERIOD {
2563 pub const offset: u32 = 0;
2564 pub const mask: u32 = 0x0fff << offset;
2565 pub mod R {}
2566 pub mod W {}
2567 pub mod RW {}
2568 }
2569 #[doc = "Max cycles of frame counter"]
2570 pub mod FRAME_CNT_CYCLES {
2571 pub const offset: u32 = 16;
2572 pub const mask: u32 = 0x0fff << offset;
2573 pub mod R {}
2574 pub mod W {}
2575 pub mod RW {}
2576 }
2577}
2578#[doc = "LCDIF Pigeon Mode Control1 Register"]
2579pub mod PIGEONCTRL1_CLR {
2580 #[doc = "Period of frame counter"]
2581 pub mod FRAME_CNT_PERIOD {
2582 pub const offset: u32 = 0;
2583 pub const mask: u32 = 0x0fff << offset;
2584 pub mod R {}
2585 pub mod W {}
2586 pub mod RW {}
2587 }
2588 #[doc = "Max cycles of frame counter"]
2589 pub mod FRAME_CNT_CYCLES {
2590 pub const offset: u32 = 16;
2591 pub const mask: u32 = 0x0fff << offset;
2592 pub mod R {}
2593 pub mod W {}
2594 pub mod RW {}
2595 }
2596}
2597#[doc = "LCDIF Pigeon Mode Control1 Register"]
2598pub mod PIGEONCTRL1_TOG {
2599 #[doc = "Period of frame counter"]
2600 pub mod FRAME_CNT_PERIOD {
2601 pub const offset: u32 = 0;
2602 pub const mask: u32 = 0x0fff << offset;
2603 pub mod R {}
2604 pub mod W {}
2605 pub mod RW {}
2606 }
2607 #[doc = "Max cycles of frame counter"]
2608 pub mod FRAME_CNT_CYCLES {
2609 pub const offset: u32 = 16;
2610 pub const mask: u32 = 0x0fff << offset;
2611 pub mod R {}
2612 pub mod W {}
2613 pub mod RW {}
2614 }
2615}
2616#[doc = "LCDIF Pigeon Mode Control2 Register"]
2617pub mod PIGEONCTRL2 {
2618 #[doc = "Pigeon mode data enable"]
2619 pub mod PIGEON_DATA_EN {
2620 pub const offset: u32 = 0;
2621 pub const mask: u32 = 0x01 << offset;
2622 pub mod R {}
2623 pub mod W {}
2624 pub mod RW {}
2625 }
2626 #[doc = "Pigeon mode dot clock gate enable"]
2627 pub mod PIGEON_CLK_GATE {
2628 pub const offset: u32 = 1;
2629 pub const mask: u32 = 0x01 << offset;
2630 pub mod R {}
2631 pub mod W {}
2632 pub mod RW {}
2633 }
2634}
2635#[doc = "LCDIF Pigeon Mode Control2 Register"]
2636pub mod PIGEONCTRL2_SET {
2637 #[doc = "Pigeon mode data enable"]
2638 pub mod PIGEON_DATA_EN {
2639 pub const offset: u32 = 0;
2640 pub const mask: u32 = 0x01 << offset;
2641 pub mod R {}
2642 pub mod W {}
2643 pub mod RW {}
2644 }
2645 #[doc = "Pigeon mode dot clock gate enable"]
2646 pub mod PIGEON_CLK_GATE {
2647 pub const offset: u32 = 1;
2648 pub const mask: u32 = 0x01 << offset;
2649 pub mod R {}
2650 pub mod W {}
2651 pub mod RW {}
2652 }
2653}
2654#[doc = "LCDIF Pigeon Mode Control2 Register"]
2655pub mod PIGEONCTRL2_CLR {
2656 #[doc = "Pigeon mode data enable"]
2657 pub mod PIGEON_DATA_EN {
2658 pub const offset: u32 = 0;
2659 pub const mask: u32 = 0x01 << offset;
2660 pub mod R {}
2661 pub mod W {}
2662 pub mod RW {}
2663 }
2664 #[doc = "Pigeon mode dot clock gate enable"]
2665 pub mod PIGEON_CLK_GATE {
2666 pub const offset: u32 = 1;
2667 pub const mask: u32 = 0x01 << offset;
2668 pub mod R {}
2669 pub mod W {}
2670 pub mod RW {}
2671 }
2672}
2673#[doc = "LCDIF Pigeon Mode Control2 Register"]
2674pub mod PIGEONCTRL2_TOG {
2675 #[doc = "Pigeon mode data enable"]
2676 pub mod PIGEON_DATA_EN {
2677 pub const offset: u32 = 0;
2678 pub const mask: u32 = 0x01 << offset;
2679 pub mod R {}
2680 pub mod W {}
2681 pub mod RW {}
2682 }
2683 #[doc = "Pigeon mode dot clock gate enable"]
2684 pub mod PIGEON_CLK_GATE {
2685 pub const offset: u32 = 1;
2686 pub const mask: u32 = 0x01 << offset;
2687 pub mod R {}
2688 pub mod W {}
2689 pub mod RW {}
2690 }
2691}
2692#[doc = "Panel Interface Signal Generator Register"]
2693pub mod PIGEON_0_0 {
2694 #[doc = "Enable pigeon Mode on this signal"]
2695 pub mod EN {
2696 pub const offset: u32 = 0;
2697 pub const mask: u32 = 0x01 << offset;
2698 pub mod R {}
2699 pub mod W {}
2700 pub mod RW {}
2701 }
2702 #[doc = "Polarity of signal output"]
2703 pub mod POL {
2704 pub const offset: u32 = 1;
2705 pub const mask: u32 = 0x01 << offset;
2706 pub mod R {}
2707 pub mod W {}
2708 pub mod RW {
2709 #[doc = "Normal Signal (Active high)"]
2710 pub const ACTIVE_HIGH: u32 = 0;
2711 #[doc = "Inverted signal (Active low)"]
2712 pub const ACTIVE_LOW: u32 = 0x01;
2713 }
2714 }
2715 #[doc = "Event to incrment local counter"]
2716 pub mod INC_SEL {
2717 pub const offset: u32 = 2;
2718 pub const mask: u32 = 0x03 << offset;
2719 pub mod R {}
2720 pub mod W {}
2721 pub mod RW {
2722 #[doc = "pclk"]
2723 pub const PCLK: u32 = 0;
2724 #[doc = "Line start pulse"]
2725 pub const LINE: u32 = 0x01;
2726 #[doc = "Frame start pulse"]
2727 pub const FRAME: u32 = 0x02;
2728 #[doc = "Use another signal as tick event"]
2729 pub const SIG_ANOTHER: u32 = 0x03;
2730 }
2731 }
2732 #[doc = "offset on pclk unit"]
2733 pub mod OFFSET {
2734 pub const offset: u32 = 4;
2735 pub const mask: u32 = 0x0f << offset;
2736 pub mod R {}
2737 pub mod W {}
2738 pub mod RW {}
2739 }
2740 #[doc = "select global counters as mask condition, use together with MASK_CNT"]
2741 pub mod MASK_CNT_SEL {
2742 pub const offset: u32 = 8;
2743 pub const mask: u32 = 0x0f << offset;
2744 pub mod R {}
2745 pub mod W {}
2746 pub mod RW {
2747 #[doc = "pclk counter within one hscan state"]
2748 pub const HSTATE_CNT: u32 = 0;
2749 #[doc = "pclk cycle within one hscan state"]
2750 pub const HSTATE_CYCLE: u32 = 0x01;
2751 #[doc = "line counter within one vscan state"]
2752 pub const VSTATE_CNT: u32 = 0x02;
2753 #[doc = "line cycle within one vscan state"]
2754 pub const VSTATE_CYCLE: u32 = 0x03;
2755 #[doc = "frame counter"]
2756 pub const FRAME_CNT: u32 = 0x04;
2757 #[doc = "frame cycle"]
2758 pub const FRAME_CYCLE: u32 = 0x05;
2759 #[doc = "horizontal counter (pclk counter within one line )"]
2760 pub const HCNT: u32 = 0x06;
2761 #[doc = "vertical counter (line counter within one frame)"]
2762 pub const VCNT: u32 = 0x07;
2763 }
2764 }
2765 #[doc = "When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking"]
2766 pub mod MASK_CNT {
2767 pub const offset: u32 = 12;
2768 pub const mask: u32 = 0x0fff << offset;
2769 pub mod R {}
2770 pub mod W {}
2771 pub mod RW {}
2772 }
2773 #[doc = "state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking"]
2774 pub mod STATE_MASK {
2775 pub const offset: u32 = 24;
2776 pub const mask: u32 = 0xff << offset;
2777 pub mod R {}
2778 pub mod W {}
2779 pub mod RW {
2780 #[doc = "FRAME SYNC"]
2781 pub const FS: u32 = 0x01;
2782 #[doc = "FRAME BEGIN"]
2783 pub const FB: u32 = 0x02;
2784 #[doc = "FRAME DATA"]
2785 pub const FD: u32 = 0x04;
2786 #[doc = "FRAME END"]
2787 pub const FE: u32 = 0x08;
2788 #[doc = "LINE SYNC"]
2789 pub const LS: u32 = 0x10;
2790 #[doc = "LINE BEGIN"]
2791 pub const LB: u32 = 0x20;
2792 #[doc = "LINE DATA"]
2793 pub const LD: u32 = 0x40;
2794 #[doc = "LINE END"]
2795 pub const LE: u32 = 0x80;
2796 }
2797 }
2798}
2799#[doc = "Panel Interface Signal Generator Register"]
2800pub mod PIGEON_0_1 {
2801 #[doc = "Assert signal output when counter match this value"]
2802 pub mod SET_CNT {
2803 pub const offset: u32 = 0;
2804 pub const mask: u32 = 0xffff << offset;
2805 pub mod R {}
2806 pub mod W {}
2807 pub mod RW {
2808 #[doc = "Start as active"]
2809 pub const START_ACTIVE: u32 = 0;
2810 }
2811 }
2812 #[doc = "Deassert signal output when counter match this value"]
2813 pub mod CLR_CNT {
2814 pub const offset: u32 = 16;
2815 pub const mask: u32 = 0xffff << offset;
2816 pub mod R {}
2817 pub mod W {}
2818 pub mod RW {
2819 #[doc = "Keep active until mask off"]
2820 pub const CLEAR_USING_MASK: u32 = 0;
2821 }
2822 }
2823}
2824#[doc = "Panel Interface Signal Generator Register"]
2825pub mod PIGEON_0_2 {
2826 #[doc = "Logic operation with another signal: DIS/AND/OR/COND"]
2827 pub mod SIG_LOGIC {
2828 pub const offset: u32 = 0;
2829 pub const mask: u32 = 0x0f << offset;
2830 pub mod R {}
2831 pub mod W {}
2832 pub mod RW {
2833 #[doc = "No logic operation"]
2834 pub const DIS: u32 = 0;
2835 #[doc = "sigout = sig_another AND this_sig"]
2836 pub const AND: u32 = 0x01;
2837 #[doc = "sigout = sig_another OR this_sig"]
2838 pub const OR: u32 = 0x02;
2839 #[doc = "mask = sig_another AND other_masks"]
2840 pub const MASK: u32 = 0x03;
2841 }
2842 }
2843 #[doc = "Select another signal for logic operation or as mask or counter tick event"]
2844 pub mod SIG_ANOTHER {
2845 pub const offset: u32 = 4;
2846 pub const mask: u32 = 0x1f << offset;
2847 pub mod R {}
2848 pub mod W {}
2849 pub mod RW {
2850 #[doc = "Keep active until mask off"]
2851 pub const CLEAR_USING_MASK: u32 = 0;
2852 }
2853 }
2854}
2855#[doc = "Panel Interface Signal Generator Register"]
2856pub mod PIGEON_1_0 {
2857 #[doc = "Enable pigeon Mode on this signal"]
2858 pub mod EN {
2859 pub const offset: u32 = 0;
2860 pub const mask: u32 = 0x01 << offset;
2861 pub mod R {}
2862 pub mod W {}
2863 pub mod RW {}
2864 }
2865 #[doc = "Polarity of signal output"]
2866 pub mod POL {
2867 pub const offset: u32 = 1;
2868 pub const mask: u32 = 0x01 << offset;
2869 pub mod R {}
2870 pub mod W {}
2871 pub mod RW {
2872 #[doc = "Normal Signal (Active high)"]
2873 pub const ACTIVE_HIGH: u32 = 0;
2874 #[doc = "Inverted signal (Active low)"]
2875 pub const ACTIVE_LOW: u32 = 0x01;
2876 }
2877 }
2878 #[doc = "Event to incrment local counter"]
2879 pub mod INC_SEL {
2880 pub const offset: u32 = 2;
2881 pub const mask: u32 = 0x03 << offset;
2882 pub mod R {}
2883 pub mod W {}
2884 pub mod RW {
2885 #[doc = "pclk"]
2886 pub const PCLK: u32 = 0;
2887 #[doc = "Line start pulse"]
2888 pub const LINE: u32 = 0x01;
2889 #[doc = "Frame start pulse"]
2890 pub const FRAME: u32 = 0x02;
2891 #[doc = "Use another signal as tick event"]
2892 pub const SIG_ANOTHER: u32 = 0x03;
2893 }
2894 }
2895 #[doc = "offset on pclk unit"]
2896 pub mod OFFSET {
2897 pub const offset: u32 = 4;
2898 pub const mask: u32 = 0x0f << offset;
2899 pub mod R {}
2900 pub mod W {}
2901 pub mod RW {}
2902 }
2903 #[doc = "select global counters as mask condition, use together with MASK_CNT"]
2904 pub mod MASK_CNT_SEL {
2905 pub const offset: u32 = 8;
2906 pub const mask: u32 = 0x0f << offset;
2907 pub mod R {}
2908 pub mod W {}
2909 pub mod RW {
2910 #[doc = "pclk counter within one hscan state"]
2911 pub const HSTATE_CNT: u32 = 0;
2912 #[doc = "pclk cycle within one hscan state"]
2913 pub const HSTATE_CYCLE: u32 = 0x01;
2914 #[doc = "line counter within one vscan state"]
2915 pub const VSTATE_CNT: u32 = 0x02;
2916 #[doc = "line cycle within one vscan state"]
2917 pub const VSTATE_CYCLE: u32 = 0x03;
2918 #[doc = "frame counter"]
2919 pub const FRAME_CNT: u32 = 0x04;
2920 #[doc = "frame cycle"]
2921 pub const FRAME_CYCLE: u32 = 0x05;
2922 #[doc = "horizontal counter (pclk counter within one line )"]
2923 pub const HCNT: u32 = 0x06;
2924 #[doc = "vertical counter (line counter within one frame)"]
2925 pub const VCNT: u32 = 0x07;
2926 }
2927 }
2928 #[doc = "When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking"]
2929 pub mod MASK_CNT {
2930 pub const offset: u32 = 12;
2931 pub const mask: u32 = 0x0fff << offset;
2932 pub mod R {}
2933 pub mod W {}
2934 pub mod RW {}
2935 }
2936 #[doc = "state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking"]
2937 pub mod STATE_MASK {
2938 pub const offset: u32 = 24;
2939 pub const mask: u32 = 0xff << offset;
2940 pub mod R {}
2941 pub mod W {}
2942 pub mod RW {
2943 #[doc = "FRAME SYNC"]
2944 pub const FS: u32 = 0x01;
2945 #[doc = "FRAME BEGIN"]
2946 pub const FB: u32 = 0x02;
2947 #[doc = "FRAME DATA"]
2948 pub const FD: u32 = 0x04;
2949 #[doc = "FRAME END"]
2950 pub const FE: u32 = 0x08;
2951 #[doc = "LINE SYNC"]
2952 pub const LS: u32 = 0x10;
2953 #[doc = "LINE BEGIN"]
2954 pub const LB: u32 = 0x20;
2955 #[doc = "LINE DATA"]
2956 pub const LD: u32 = 0x40;
2957 #[doc = "LINE END"]
2958 pub const LE: u32 = 0x80;
2959 }
2960 }
2961}
2962#[doc = "Panel Interface Signal Generator Register"]
2963pub mod PIGEON_1_1 {
2964 #[doc = "Assert signal output when counter match this value"]
2965 pub mod SET_CNT {
2966 pub const offset: u32 = 0;
2967 pub const mask: u32 = 0xffff << offset;
2968 pub mod R {}
2969 pub mod W {}
2970 pub mod RW {
2971 #[doc = "Start as active"]
2972 pub const START_ACTIVE: u32 = 0;
2973 }
2974 }
2975 #[doc = "Deassert signal output when counter match this value"]
2976 pub mod CLR_CNT {
2977 pub const offset: u32 = 16;
2978 pub const mask: u32 = 0xffff << offset;
2979 pub mod R {}
2980 pub mod W {}
2981 pub mod RW {
2982 #[doc = "Keep active until mask off"]
2983 pub const CLEAR_USING_MASK: u32 = 0;
2984 }
2985 }
2986}
2987#[doc = "Panel Interface Signal Generator Register"]
2988pub mod PIGEON_1_2 {
2989 #[doc = "Logic operation with another signal: DIS/AND/OR/COND"]
2990 pub mod SIG_LOGIC {
2991 pub const offset: u32 = 0;
2992 pub const mask: u32 = 0x0f << offset;
2993 pub mod R {}
2994 pub mod W {}
2995 pub mod RW {
2996 #[doc = "No logic operation"]
2997 pub const DIS: u32 = 0;
2998 #[doc = "sigout = sig_another AND this_sig"]
2999 pub const AND: u32 = 0x01;
3000 #[doc = "sigout = sig_another OR this_sig"]
3001 pub const OR: u32 = 0x02;
3002 #[doc = "mask = sig_another AND other_masks"]
3003 pub const MASK: u32 = 0x03;
3004 }
3005 }
3006 #[doc = "Select another signal for logic operation or as mask or counter tick event"]
3007 pub mod SIG_ANOTHER {
3008 pub const offset: u32 = 4;
3009 pub const mask: u32 = 0x1f << offset;
3010 pub mod R {}
3011 pub mod W {}
3012 pub mod RW {
3013 #[doc = "Keep active until mask off"]
3014 pub const CLEAR_USING_MASK: u32 = 0;
3015 }
3016 }
3017}
3018#[doc = "Panel Interface Signal Generator Register"]
3019pub mod PIGEON_2_0 {
3020 #[doc = "Enable pigeon Mode on this signal"]
3021 pub mod EN {
3022 pub const offset: u32 = 0;
3023 pub const mask: u32 = 0x01 << offset;
3024 pub mod R {}
3025 pub mod W {}
3026 pub mod RW {}
3027 }
3028 #[doc = "Polarity of signal output"]
3029 pub mod POL {
3030 pub const offset: u32 = 1;
3031 pub const mask: u32 = 0x01 << offset;
3032 pub mod R {}
3033 pub mod W {}
3034 pub mod RW {
3035 #[doc = "Normal Signal (Active high)"]
3036 pub const ACTIVE_HIGH: u32 = 0;
3037 #[doc = "Inverted signal (Active low)"]
3038 pub const ACTIVE_LOW: u32 = 0x01;
3039 }
3040 }
3041 #[doc = "Event to incrment local counter"]
3042 pub mod INC_SEL {
3043 pub const offset: u32 = 2;
3044 pub const mask: u32 = 0x03 << offset;
3045 pub mod R {}
3046 pub mod W {}
3047 pub mod RW {
3048 #[doc = "pclk"]
3049 pub const PCLK: u32 = 0;
3050 #[doc = "Line start pulse"]
3051 pub const LINE: u32 = 0x01;
3052 #[doc = "Frame start pulse"]
3053 pub const FRAME: u32 = 0x02;
3054 #[doc = "Use another signal as tick event"]
3055 pub const SIG_ANOTHER: u32 = 0x03;
3056 }
3057 }
3058 #[doc = "offset on pclk unit"]
3059 pub mod OFFSET {
3060 pub const offset: u32 = 4;
3061 pub const mask: u32 = 0x0f << offset;
3062 pub mod R {}
3063 pub mod W {}
3064 pub mod RW {}
3065 }
3066 #[doc = "select global counters as mask condition, use together with MASK_CNT"]
3067 pub mod MASK_CNT_SEL {
3068 pub const offset: u32 = 8;
3069 pub const mask: u32 = 0x0f << offset;
3070 pub mod R {}
3071 pub mod W {}
3072 pub mod RW {
3073 #[doc = "pclk counter within one hscan state"]
3074 pub const HSTATE_CNT: u32 = 0;
3075 #[doc = "pclk cycle within one hscan state"]
3076 pub const HSTATE_CYCLE: u32 = 0x01;
3077 #[doc = "line counter within one vscan state"]
3078 pub const VSTATE_CNT: u32 = 0x02;
3079 #[doc = "line cycle within one vscan state"]
3080 pub const VSTATE_CYCLE: u32 = 0x03;
3081 #[doc = "frame counter"]
3082 pub const FRAME_CNT: u32 = 0x04;
3083 #[doc = "frame cycle"]
3084 pub const FRAME_CYCLE: u32 = 0x05;
3085 #[doc = "horizontal counter (pclk counter within one line )"]
3086 pub const HCNT: u32 = 0x06;
3087 #[doc = "vertical counter (line counter within one frame)"]
3088 pub const VCNT: u32 = 0x07;
3089 }
3090 }
3091 #[doc = "When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking"]
3092 pub mod MASK_CNT {
3093 pub const offset: u32 = 12;
3094 pub const mask: u32 = 0x0fff << offset;
3095 pub mod R {}
3096 pub mod W {}
3097 pub mod RW {}
3098 }
3099 #[doc = "state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking"]
3100 pub mod STATE_MASK {
3101 pub const offset: u32 = 24;
3102 pub const mask: u32 = 0xff << offset;
3103 pub mod R {}
3104 pub mod W {}
3105 pub mod RW {
3106 #[doc = "FRAME SYNC"]
3107 pub const FS: u32 = 0x01;
3108 #[doc = "FRAME BEGIN"]
3109 pub const FB: u32 = 0x02;
3110 #[doc = "FRAME DATA"]
3111 pub const FD: u32 = 0x04;
3112 #[doc = "FRAME END"]
3113 pub const FE: u32 = 0x08;
3114 #[doc = "LINE SYNC"]
3115 pub const LS: u32 = 0x10;
3116 #[doc = "LINE BEGIN"]
3117 pub const LB: u32 = 0x20;
3118 #[doc = "LINE DATA"]
3119 pub const LD: u32 = 0x40;
3120 #[doc = "LINE END"]
3121 pub const LE: u32 = 0x80;
3122 }
3123 }
3124}
3125#[doc = "Panel Interface Signal Generator Register"]
3126pub mod PIGEON_2_1 {
3127 #[doc = "Assert signal output when counter match this value"]
3128 pub mod SET_CNT {
3129 pub const offset: u32 = 0;
3130 pub const mask: u32 = 0xffff << offset;
3131 pub mod R {}
3132 pub mod W {}
3133 pub mod RW {
3134 #[doc = "Start as active"]
3135 pub const START_ACTIVE: u32 = 0;
3136 }
3137 }
3138 #[doc = "Deassert signal output when counter match this value"]
3139 pub mod CLR_CNT {
3140 pub const offset: u32 = 16;
3141 pub const mask: u32 = 0xffff << offset;
3142 pub mod R {}
3143 pub mod W {}
3144 pub mod RW {
3145 #[doc = "Keep active until mask off"]
3146 pub const CLEAR_USING_MASK: u32 = 0;
3147 }
3148 }
3149}
3150#[doc = "Panel Interface Signal Generator Register"]
3151pub mod PIGEON_2_2 {
3152 #[doc = "Logic operation with another signal: DIS/AND/OR/COND"]
3153 pub mod SIG_LOGIC {
3154 pub const offset: u32 = 0;
3155 pub const mask: u32 = 0x0f << offset;
3156 pub mod R {}
3157 pub mod W {}
3158 pub mod RW {
3159 #[doc = "No logic operation"]
3160 pub const DIS: u32 = 0;
3161 #[doc = "sigout = sig_another AND this_sig"]
3162 pub const AND: u32 = 0x01;
3163 #[doc = "sigout = sig_another OR this_sig"]
3164 pub const OR: u32 = 0x02;
3165 #[doc = "mask = sig_another AND other_masks"]
3166 pub const MASK: u32 = 0x03;
3167 }
3168 }
3169 #[doc = "Select another signal for logic operation or as mask or counter tick event"]
3170 pub mod SIG_ANOTHER {
3171 pub const offset: u32 = 4;
3172 pub const mask: u32 = 0x1f << offset;
3173 pub mod R {}
3174 pub mod W {}
3175 pub mod RW {
3176 #[doc = "Keep active until mask off"]
3177 pub const CLEAR_USING_MASK: u32 = 0;
3178 }
3179 }
3180}
3181#[doc = "Panel Interface Signal Generator Register"]
3182pub mod PIGEON_3_0 {
3183 #[doc = "Enable pigeon Mode on this signal"]
3184 pub mod EN {
3185 pub const offset: u32 = 0;
3186 pub const mask: u32 = 0x01 << offset;
3187 pub mod R {}
3188 pub mod W {}
3189 pub mod RW {}
3190 }
3191 #[doc = "Polarity of signal output"]
3192 pub mod POL {
3193 pub const offset: u32 = 1;
3194 pub const mask: u32 = 0x01 << offset;
3195 pub mod R {}
3196 pub mod W {}
3197 pub mod RW {
3198 #[doc = "Normal Signal (Active high)"]
3199 pub const ACTIVE_HIGH: u32 = 0;
3200 #[doc = "Inverted signal (Active low)"]
3201 pub const ACTIVE_LOW: u32 = 0x01;
3202 }
3203 }
3204 #[doc = "Event to incrment local counter"]
3205 pub mod INC_SEL {
3206 pub const offset: u32 = 2;
3207 pub const mask: u32 = 0x03 << offset;
3208 pub mod R {}
3209 pub mod W {}
3210 pub mod RW {
3211 #[doc = "pclk"]
3212 pub const PCLK: u32 = 0;
3213 #[doc = "Line start pulse"]
3214 pub const LINE: u32 = 0x01;
3215 #[doc = "Frame start pulse"]
3216 pub const FRAME: u32 = 0x02;
3217 #[doc = "Use another signal as tick event"]
3218 pub const SIG_ANOTHER: u32 = 0x03;
3219 }
3220 }
3221 #[doc = "offset on pclk unit"]
3222 pub mod OFFSET {
3223 pub const offset: u32 = 4;
3224 pub const mask: u32 = 0x0f << offset;
3225 pub mod R {}
3226 pub mod W {}
3227 pub mod RW {}
3228 }
3229 #[doc = "select global counters as mask condition, use together with MASK_CNT"]
3230 pub mod MASK_CNT_SEL {
3231 pub const offset: u32 = 8;
3232 pub const mask: u32 = 0x0f << offset;
3233 pub mod R {}
3234 pub mod W {}
3235 pub mod RW {
3236 #[doc = "pclk counter within one hscan state"]
3237 pub const HSTATE_CNT: u32 = 0;
3238 #[doc = "pclk cycle within one hscan state"]
3239 pub const HSTATE_CYCLE: u32 = 0x01;
3240 #[doc = "line counter within one vscan state"]
3241 pub const VSTATE_CNT: u32 = 0x02;
3242 #[doc = "line cycle within one vscan state"]
3243 pub const VSTATE_CYCLE: u32 = 0x03;
3244 #[doc = "frame counter"]
3245 pub const FRAME_CNT: u32 = 0x04;
3246 #[doc = "frame cycle"]
3247 pub const FRAME_CYCLE: u32 = 0x05;
3248 #[doc = "horizontal counter (pclk counter within one line )"]
3249 pub const HCNT: u32 = 0x06;
3250 #[doc = "vertical counter (line counter within one frame)"]
3251 pub const VCNT: u32 = 0x07;
3252 }
3253 }
3254 #[doc = "When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking"]
3255 pub mod MASK_CNT {
3256 pub const offset: u32 = 12;
3257 pub const mask: u32 = 0x0fff << offset;
3258 pub mod R {}
3259 pub mod W {}
3260 pub mod RW {}
3261 }
3262 #[doc = "state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking"]
3263 pub mod STATE_MASK {
3264 pub const offset: u32 = 24;
3265 pub const mask: u32 = 0xff << offset;
3266 pub mod R {}
3267 pub mod W {}
3268 pub mod RW {
3269 #[doc = "FRAME SYNC"]
3270 pub const FS: u32 = 0x01;
3271 #[doc = "FRAME BEGIN"]
3272 pub const FB: u32 = 0x02;
3273 #[doc = "FRAME DATA"]
3274 pub const FD: u32 = 0x04;
3275 #[doc = "FRAME END"]
3276 pub const FE: u32 = 0x08;
3277 #[doc = "LINE SYNC"]
3278 pub const LS: u32 = 0x10;
3279 #[doc = "LINE BEGIN"]
3280 pub const LB: u32 = 0x20;
3281 #[doc = "LINE DATA"]
3282 pub const LD: u32 = 0x40;
3283 #[doc = "LINE END"]
3284 pub const LE: u32 = 0x80;
3285 }
3286 }
3287}
3288#[doc = "Panel Interface Signal Generator Register"]
3289pub mod PIGEON_3_1 {
3290 #[doc = "Assert signal output when counter match this value"]
3291 pub mod SET_CNT {
3292 pub const offset: u32 = 0;
3293 pub const mask: u32 = 0xffff << offset;
3294 pub mod R {}
3295 pub mod W {}
3296 pub mod RW {
3297 #[doc = "Start as active"]
3298 pub const START_ACTIVE: u32 = 0;
3299 }
3300 }
3301 #[doc = "Deassert signal output when counter match this value"]
3302 pub mod CLR_CNT {
3303 pub const offset: u32 = 16;
3304 pub const mask: u32 = 0xffff << offset;
3305 pub mod R {}
3306 pub mod W {}
3307 pub mod RW {
3308 #[doc = "Keep active until mask off"]
3309 pub const CLEAR_USING_MASK: u32 = 0;
3310 }
3311 }
3312}
3313#[doc = "Panel Interface Signal Generator Register"]
3314pub mod PIGEON_3_2 {
3315 #[doc = "Logic operation with another signal: DIS/AND/OR/COND"]
3316 pub mod SIG_LOGIC {
3317 pub const offset: u32 = 0;
3318 pub const mask: u32 = 0x0f << offset;
3319 pub mod R {}
3320 pub mod W {}
3321 pub mod RW {
3322 #[doc = "No logic operation"]
3323 pub const DIS: u32 = 0;
3324 #[doc = "sigout = sig_another AND this_sig"]
3325 pub const AND: u32 = 0x01;
3326 #[doc = "sigout = sig_another OR this_sig"]
3327 pub const OR: u32 = 0x02;
3328 #[doc = "mask = sig_another AND other_masks"]
3329 pub const MASK: u32 = 0x03;
3330 }
3331 }
3332 #[doc = "Select another signal for logic operation or as mask or counter tick event"]
3333 pub mod SIG_ANOTHER {
3334 pub const offset: u32 = 4;
3335 pub const mask: u32 = 0x1f << offset;
3336 pub mod R {}
3337 pub mod W {}
3338 pub mod RW {
3339 #[doc = "Keep active until mask off"]
3340 pub const CLEAR_USING_MASK: u32 = 0;
3341 }
3342 }
3343}
3344#[doc = "Panel Interface Signal Generator Register"]
3345pub mod PIGEON_4_0 {
3346 #[doc = "Enable pigeon Mode on this signal"]
3347 pub mod EN {
3348 pub const offset: u32 = 0;
3349 pub const mask: u32 = 0x01 << offset;
3350 pub mod R {}
3351 pub mod W {}
3352 pub mod RW {}
3353 }
3354 #[doc = "Polarity of signal output"]
3355 pub mod POL {
3356 pub const offset: u32 = 1;
3357 pub const mask: u32 = 0x01 << offset;
3358 pub mod R {}
3359 pub mod W {}
3360 pub mod RW {
3361 #[doc = "Normal Signal (Active high)"]
3362 pub const ACTIVE_HIGH: u32 = 0;
3363 #[doc = "Inverted signal (Active low)"]
3364 pub const ACTIVE_LOW: u32 = 0x01;
3365 }
3366 }
3367 #[doc = "Event to incrment local counter"]
3368 pub mod INC_SEL {
3369 pub const offset: u32 = 2;
3370 pub const mask: u32 = 0x03 << offset;
3371 pub mod R {}
3372 pub mod W {}
3373 pub mod RW {
3374 #[doc = "pclk"]
3375 pub const PCLK: u32 = 0;
3376 #[doc = "Line start pulse"]
3377 pub const LINE: u32 = 0x01;
3378 #[doc = "Frame start pulse"]
3379 pub const FRAME: u32 = 0x02;
3380 #[doc = "Use another signal as tick event"]
3381 pub const SIG_ANOTHER: u32 = 0x03;
3382 }
3383 }
3384 #[doc = "offset on pclk unit"]
3385 pub mod OFFSET {
3386 pub const offset: u32 = 4;
3387 pub const mask: u32 = 0x0f << offset;
3388 pub mod R {}
3389 pub mod W {}
3390 pub mod RW {}
3391 }
3392 #[doc = "select global counters as mask condition, use together with MASK_CNT"]
3393 pub mod MASK_CNT_SEL {
3394 pub const offset: u32 = 8;
3395 pub const mask: u32 = 0x0f << offset;
3396 pub mod R {}
3397 pub mod W {}
3398 pub mod RW {
3399 #[doc = "pclk counter within one hscan state"]
3400 pub const HSTATE_CNT: u32 = 0;
3401 #[doc = "pclk cycle within one hscan state"]
3402 pub const HSTATE_CYCLE: u32 = 0x01;
3403 #[doc = "line counter within one vscan state"]
3404 pub const VSTATE_CNT: u32 = 0x02;
3405 #[doc = "line cycle within one vscan state"]
3406 pub const VSTATE_CYCLE: u32 = 0x03;
3407 #[doc = "frame counter"]
3408 pub const FRAME_CNT: u32 = 0x04;
3409 #[doc = "frame cycle"]
3410 pub const FRAME_CYCLE: u32 = 0x05;
3411 #[doc = "horizontal counter (pclk counter within one line )"]
3412 pub const HCNT: u32 = 0x06;
3413 #[doc = "vertical counter (line counter within one frame)"]
3414 pub const VCNT: u32 = 0x07;
3415 }
3416 }
3417 #[doc = "When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking"]
3418 pub mod MASK_CNT {
3419 pub const offset: u32 = 12;
3420 pub const mask: u32 = 0x0fff << offset;
3421 pub mod R {}
3422 pub mod W {}
3423 pub mod RW {}
3424 }
3425 #[doc = "state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking"]
3426 pub mod STATE_MASK {
3427 pub const offset: u32 = 24;
3428 pub const mask: u32 = 0xff << offset;
3429 pub mod R {}
3430 pub mod W {}
3431 pub mod RW {
3432 #[doc = "FRAME SYNC"]
3433 pub const FS: u32 = 0x01;
3434 #[doc = "FRAME BEGIN"]
3435 pub const FB: u32 = 0x02;
3436 #[doc = "FRAME DATA"]
3437 pub const FD: u32 = 0x04;
3438 #[doc = "FRAME END"]
3439 pub const FE: u32 = 0x08;
3440 #[doc = "LINE SYNC"]
3441 pub const LS: u32 = 0x10;
3442 #[doc = "LINE BEGIN"]
3443 pub const LB: u32 = 0x20;
3444 #[doc = "LINE DATA"]
3445 pub const LD: u32 = 0x40;
3446 #[doc = "LINE END"]
3447 pub const LE: u32 = 0x80;
3448 }
3449 }
3450}
3451#[doc = "Panel Interface Signal Generator Register"]
3452pub mod PIGEON_4_1 {
3453 #[doc = "Assert signal output when counter match this value"]
3454 pub mod SET_CNT {
3455 pub const offset: u32 = 0;
3456 pub const mask: u32 = 0xffff << offset;
3457 pub mod R {}
3458 pub mod W {}
3459 pub mod RW {
3460 #[doc = "Start as active"]
3461 pub const START_ACTIVE: u32 = 0;
3462 }
3463 }
3464 #[doc = "Deassert signal output when counter match this value"]
3465 pub mod CLR_CNT {
3466 pub const offset: u32 = 16;
3467 pub const mask: u32 = 0xffff << offset;
3468 pub mod R {}
3469 pub mod W {}
3470 pub mod RW {
3471 #[doc = "Keep active until mask off"]
3472 pub const CLEAR_USING_MASK: u32 = 0;
3473 }
3474 }
3475}
3476#[doc = "Panel Interface Signal Generator Register"]
3477pub mod PIGEON_4_2 {
3478 #[doc = "Logic operation with another signal: DIS/AND/OR/COND"]
3479 pub mod SIG_LOGIC {
3480 pub const offset: u32 = 0;
3481 pub const mask: u32 = 0x0f << offset;
3482 pub mod R {}
3483 pub mod W {}
3484 pub mod RW {
3485 #[doc = "No logic operation"]
3486 pub const DIS: u32 = 0;
3487 #[doc = "sigout = sig_another AND this_sig"]
3488 pub const AND: u32 = 0x01;
3489 #[doc = "sigout = sig_another OR this_sig"]
3490 pub const OR: u32 = 0x02;
3491 #[doc = "mask = sig_another AND other_masks"]
3492 pub const MASK: u32 = 0x03;
3493 }
3494 }
3495 #[doc = "Select another signal for logic operation or as mask or counter tick event"]
3496 pub mod SIG_ANOTHER {
3497 pub const offset: u32 = 4;
3498 pub const mask: u32 = 0x1f << offset;
3499 pub mod R {}
3500 pub mod W {}
3501 pub mod RW {
3502 #[doc = "Keep active until mask off"]
3503 pub const CLEAR_USING_MASK: u32 = 0;
3504 }
3505 }
3506}
3507#[doc = "Panel Interface Signal Generator Register"]
3508pub mod PIGEON_5_0 {
3509 #[doc = "Enable pigeon Mode on this signal"]
3510 pub mod EN {
3511 pub const offset: u32 = 0;
3512 pub const mask: u32 = 0x01 << offset;
3513 pub mod R {}
3514 pub mod W {}
3515 pub mod RW {}
3516 }
3517 #[doc = "Polarity of signal output"]
3518 pub mod POL {
3519 pub const offset: u32 = 1;
3520 pub const mask: u32 = 0x01 << offset;
3521 pub mod R {}
3522 pub mod W {}
3523 pub mod RW {
3524 #[doc = "Normal Signal (Active high)"]
3525 pub const ACTIVE_HIGH: u32 = 0;
3526 #[doc = "Inverted signal (Active low)"]
3527 pub const ACTIVE_LOW: u32 = 0x01;
3528 }
3529 }
3530 #[doc = "Event to incrment local counter"]
3531 pub mod INC_SEL {
3532 pub const offset: u32 = 2;
3533 pub const mask: u32 = 0x03 << offset;
3534 pub mod R {}
3535 pub mod W {}
3536 pub mod RW {
3537 #[doc = "pclk"]
3538 pub const PCLK: u32 = 0;
3539 #[doc = "Line start pulse"]
3540 pub const LINE: u32 = 0x01;
3541 #[doc = "Frame start pulse"]
3542 pub const FRAME: u32 = 0x02;
3543 #[doc = "Use another signal as tick event"]
3544 pub const SIG_ANOTHER: u32 = 0x03;
3545 }
3546 }
3547 #[doc = "offset on pclk unit"]
3548 pub mod OFFSET {
3549 pub const offset: u32 = 4;
3550 pub const mask: u32 = 0x0f << offset;
3551 pub mod R {}
3552 pub mod W {}
3553 pub mod RW {}
3554 }
3555 #[doc = "select global counters as mask condition, use together with MASK_CNT"]
3556 pub mod MASK_CNT_SEL {
3557 pub const offset: u32 = 8;
3558 pub const mask: u32 = 0x0f << offset;
3559 pub mod R {}
3560 pub mod W {}
3561 pub mod RW {
3562 #[doc = "pclk counter within one hscan state"]
3563 pub const HSTATE_CNT: u32 = 0;
3564 #[doc = "pclk cycle within one hscan state"]
3565 pub const HSTATE_CYCLE: u32 = 0x01;
3566 #[doc = "line counter within one vscan state"]
3567 pub const VSTATE_CNT: u32 = 0x02;
3568 #[doc = "line cycle within one vscan state"]
3569 pub const VSTATE_CYCLE: u32 = 0x03;
3570 #[doc = "frame counter"]
3571 pub const FRAME_CNT: u32 = 0x04;
3572 #[doc = "frame cycle"]
3573 pub const FRAME_CYCLE: u32 = 0x05;
3574 #[doc = "horizontal counter (pclk counter within one line )"]
3575 pub const HCNT: u32 = 0x06;
3576 #[doc = "vertical counter (line counter within one frame)"]
3577 pub const VCNT: u32 = 0x07;
3578 }
3579 }
3580 #[doc = "When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking"]
3581 pub mod MASK_CNT {
3582 pub const offset: u32 = 12;
3583 pub const mask: u32 = 0x0fff << offset;
3584 pub mod R {}
3585 pub mod W {}
3586 pub mod RW {}
3587 }
3588 #[doc = "state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking"]
3589 pub mod STATE_MASK {
3590 pub const offset: u32 = 24;
3591 pub const mask: u32 = 0xff << offset;
3592 pub mod R {}
3593 pub mod W {}
3594 pub mod RW {
3595 #[doc = "FRAME SYNC"]
3596 pub const FS: u32 = 0x01;
3597 #[doc = "FRAME BEGIN"]
3598 pub const FB: u32 = 0x02;
3599 #[doc = "FRAME DATA"]
3600 pub const FD: u32 = 0x04;
3601 #[doc = "FRAME END"]
3602 pub const FE: u32 = 0x08;
3603 #[doc = "LINE SYNC"]
3604 pub const LS: u32 = 0x10;
3605 #[doc = "LINE BEGIN"]
3606 pub const LB: u32 = 0x20;
3607 #[doc = "LINE DATA"]
3608 pub const LD: u32 = 0x40;
3609 #[doc = "LINE END"]
3610 pub const LE: u32 = 0x80;
3611 }
3612 }
3613}
3614#[doc = "Panel Interface Signal Generator Register"]
3615pub mod PIGEON_5_1 {
3616 #[doc = "Assert signal output when counter match this value"]
3617 pub mod SET_CNT {
3618 pub const offset: u32 = 0;
3619 pub const mask: u32 = 0xffff << offset;
3620 pub mod R {}
3621 pub mod W {}
3622 pub mod RW {
3623 #[doc = "Start as active"]
3624 pub const START_ACTIVE: u32 = 0;
3625 }
3626 }
3627 #[doc = "Deassert signal output when counter match this value"]
3628 pub mod CLR_CNT {
3629 pub const offset: u32 = 16;
3630 pub const mask: u32 = 0xffff << offset;
3631 pub mod R {}
3632 pub mod W {}
3633 pub mod RW {
3634 #[doc = "Keep active until mask off"]
3635 pub const CLEAR_USING_MASK: u32 = 0;
3636 }
3637 }
3638}
3639#[doc = "Panel Interface Signal Generator Register"]
3640pub mod PIGEON_5_2 {
3641 #[doc = "Logic operation with another signal: DIS/AND/OR/COND"]
3642 pub mod SIG_LOGIC {
3643 pub const offset: u32 = 0;
3644 pub const mask: u32 = 0x0f << offset;
3645 pub mod R {}
3646 pub mod W {}
3647 pub mod RW {
3648 #[doc = "No logic operation"]
3649 pub const DIS: u32 = 0;
3650 #[doc = "sigout = sig_another AND this_sig"]
3651 pub const AND: u32 = 0x01;
3652 #[doc = "sigout = sig_another OR this_sig"]
3653 pub const OR: u32 = 0x02;
3654 #[doc = "mask = sig_another AND other_masks"]
3655 pub const MASK: u32 = 0x03;
3656 }
3657 }
3658 #[doc = "Select another signal for logic operation or as mask or counter tick event"]
3659 pub mod SIG_ANOTHER {
3660 pub const offset: u32 = 4;
3661 pub const mask: u32 = 0x1f << offset;
3662 pub mod R {}
3663 pub mod W {}
3664 pub mod RW {
3665 #[doc = "Keep active until mask off"]
3666 pub const CLEAR_USING_MASK: u32 = 0;
3667 }
3668 }
3669}
3670#[doc = "Panel Interface Signal Generator Register"]
3671pub mod PIGEON_6_0 {
3672 #[doc = "Enable pigeon Mode on this signal"]
3673 pub mod EN {
3674 pub const offset: u32 = 0;
3675 pub const mask: u32 = 0x01 << offset;
3676 pub mod R {}
3677 pub mod W {}
3678 pub mod RW {}
3679 }
3680 #[doc = "Polarity of signal output"]
3681 pub mod POL {
3682 pub const offset: u32 = 1;
3683 pub const mask: u32 = 0x01 << offset;
3684 pub mod R {}
3685 pub mod W {}
3686 pub mod RW {
3687 #[doc = "Normal Signal (Active high)"]
3688 pub const ACTIVE_HIGH: u32 = 0;
3689 #[doc = "Inverted signal (Active low)"]
3690 pub const ACTIVE_LOW: u32 = 0x01;
3691 }
3692 }
3693 #[doc = "Event to incrment local counter"]
3694 pub mod INC_SEL {
3695 pub const offset: u32 = 2;
3696 pub const mask: u32 = 0x03 << offset;
3697 pub mod R {}
3698 pub mod W {}
3699 pub mod RW {
3700 #[doc = "pclk"]
3701 pub const PCLK: u32 = 0;
3702 #[doc = "Line start pulse"]
3703 pub const LINE: u32 = 0x01;
3704 #[doc = "Frame start pulse"]
3705 pub const FRAME: u32 = 0x02;
3706 #[doc = "Use another signal as tick event"]
3707 pub const SIG_ANOTHER: u32 = 0x03;
3708 }
3709 }
3710 #[doc = "offset on pclk unit"]
3711 pub mod OFFSET {
3712 pub const offset: u32 = 4;
3713 pub const mask: u32 = 0x0f << offset;
3714 pub mod R {}
3715 pub mod W {}
3716 pub mod RW {}
3717 }
3718 #[doc = "select global counters as mask condition, use together with MASK_CNT"]
3719 pub mod MASK_CNT_SEL {
3720 pub const offset: u32 = 8;
3721 pub const mask: u32 = 0x0f << offset;
3722 pub mod R {}
3723 pub mod W {}
3724 pub mod RW {
3725 #[doc = "pclk counter within one hscan state"]
3726 pub const HSTATE_CNT: u32 = 0;
3727 #[doc = "pclk cycle within one hscan state"]
3728 pub const HSTATE_CYCLE: u32 = 0x01;
3729 #[doc = "line counter within one vscan state"]
3730 pub const VSTATE_CNT: u32 = 0x02;
3731 #[doc = "line cycle within one vscan state"]
3732 pub const VSTATE_CYCLE: u32 = 0x03;
3733 #[doc = "frame counter"]
3734 pub const FRAME_CNT: u32 = 0x04;
3735 #[doc = "frame cycle"]
3736 pub const FRAME_CYCLE: u32 = 0x05;
3737 #[doc = "horizontal counter (pclk counter within one line )"]
3738 pub const HCNT: u32 = 0x06;
3739 #[doc = "vertical counter (line counter within one frame)"]
3740 pub const VCNT: u32 = 0x07;
3741 }
3742 }
3743 #[doc = "When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking"]
3744 pub mod MASK_CNT {
3745 pub const offset: u32 = 12;
3746 pub const mask: u32 = 0x0fff << offset;
3747 pub mod R {}
3748 pub mod W {}
3749 pub mod RW {}
3750 }
3751 #[doc = "state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking"]
3752 pub mod STATE_MASK {
3753 pub const offset: u32 = 24;
3754 pub const mask: u32 = 0xff << offset;
3755 pub mod R {}
3756 pub mod W {}
3757 pub mod RW {
3758 #[doc = "FRAME SYNC"]
3759 pub const FS: u32 = 0x01;
3760 #[doc = "FRAME BEGIN"]
3761 pub const FB: u32 = 0x02;
3762 #[doc = "FRAME DATA"]
3763 pub const FD: u32 = 0x04;
3764 #[doc = "FRAME END"]
3765 pub const FE: u32 = 0x08;
3766 #[doc = "LINE SYNC"]
3767 pub const LS: u32 = 0x10;
3768 #[doc = "LINE BEGIN"]
3769 pub const LB: u32 = 0x20;
3770 #[doc = "LINE DATA"]
3771 pub const LD: u32 = 0x40;
3772 #[doc = "LINE END"]
3773 pub const LE: u32 = 0x80;
3774 }
3775 }
3776}
3777#[doc = "Panel Interface Signal Generator Register"]
3778pub mod PIGEON_6_1 {
3779 #[doc = "Assert signal output when counter match this value"]
3780 pub mod SET_CNT {
3781 pub const offset: u32 = 0;
3782 pub const mask: u32 = 0xffff << offset;
3783 pub mod R {}
3784 pub mod W {}
3785 pub mod RW {
3786 #[doc = "Start as active"]
3787 pub const START_ACTIVE: u32 = 0;
3788 }
3789 }
3790 #[doc = "Deassert signal output when counter match this value"]
3791 pub mod CLR_CNT {
3792 pub const offset: u32 = 16;
3793 pub const mask: u32 = 0xffff << offset;
3794 pub mod R {}
3795 pub mod W {}
3796 pub mod RW {
3797 #[doc = "Keep active until mask off"]
3798 pub const CLEAR_USING_MASK: u32 = 0;
3799 }
3800 }
3801}
3802#[doc = "Panel Interface Signal Generator Register"]
3803pub mod PIGEON_6_2 {
3804 #[doc = "Logic operation with another signal: DIS/AND/OR/COND"]
3805 pub mod SIG_LOGIC {
3806 pub const offset: u32 = 0;
3807 pub const mask: u32 = 0x0f << offset;
3808 pub mod R {}
3809 pub mod W {}
3810 pub mod RW {
3811 #[doc = "No logic operation"]
3812 pub const DIS: u32 = 0;
3813 #[doc = "sigout = sig_another AND this_sig"]
3814 pub const AND: u32 = 0x01;
3815 #[doc = "sigout = sig_another OR this_sig"]
3816 pub const OR: u32 = 0x02;
3817 #[doc = "mask = sig_another AND other_masks"]
3818 pub const MASK: u32 = 0x03;
3819 }
3820 }
3821 #[doc = "Select another signal for logic operation or as mask or counter tick event"]
3822 pub mod SIG_ANOTHER {
3823 pub const offset: u32 = 4;
3824 pub const mask: u32 = 0x1f << offset;
3825 pub mod R {}
3826 pub mod W {}
3827 pub mod RW {
3828 #[doc = "Keep active until mask off"]
3829 pub const CLEAR_USING_MASK: u32 = 0;
3830 }
3831 }
3832}
3833#[doc = "Panel Interface Signal Generator Register"]
3834pub mod PIGEON_7_0 {
3835 #[doc = "Enable pigeon Mode on this signal"]
3836 pub mod EN {
3837 pub const offset: u32 = 0;
3838 pub const mask: u32 = 0x01 << offset;
3839 pub mod R {}
3840 pub mod W {}
3841 pub mod RW {}
3842 }
3843 #[doc = "Polarity of signal output"]
3844 pub mod POL {
3845 pub const offset: u32 = 1;
3846 pub const mask: u32 = 0x01 << offset;
3847 pub mod R {}
3848 pub mod W {}
3849 pub mod RW {
3850 #[doc = "Normal Signal (Active high)"]
3851 pub const ACTIVE_HIGH: u32 = 0;
3852 #[doc = "Inverted signal (Active low)"]
3853 pub const ACTIVE_LOW: u32 = 0x01;
3854 }
3855 }
3856 #[doc = "Event to incrment local counter"]
3857 pub mod INC_SEL {
3858 pub const offset: u32 = 2;
3859 pub const mask: u32 = 0x03 << offset;
3860 pub mod R {}
3861 pub mod W {}
3862 pub mod RW {
3863 #[doc = "pclk"]
3864 pub const PCLK: u32 = 0;
3865 #[doc = "Line start pulse"]
3866 pub const LINE: u32 = 0x01;
3867 #[doc = "Frame start pulse"]
3868 pub const FRAME: u32 = 0x02;
3869 #[doc = "Use another signal as tick event"]
3870 pub const SIG_ANOTHER: u32 = 0x03;
3871 }
3872 }
3873 #[doc = "offset on pclk unit"]
3874 pub mod OFFSET {
3875 pub const offset: u32 = 4;
3876 pub const mask: u32 = 0x0f << offset;
3877 pub mod R {}
3878 pub mod W {}
3879 pub mod RW {}
3880 }
3881 #[doc = "select global counters as mask condition, use together with MASK_CNT"]
3882 pub mod MASK_CNT_SEL {
3883 pub const offset: u32 = 8;
3884 pub const mask: u32 = 0x0f << offset;
3885 pub mod R {}
3886 pub mod W {}
3887 pub mod RW {
3888 #[doc = "pclk counter within one hscan state"]
3889 pub const HSTATE_CNT: u32 = 0;
3890 #[doc = "pclk cycle within one hscan state"]
3891 pub const HSTATE_CYCLE: u32 = 0x01;
3892 #[doc = "line counter within one vscan state"]
3893 pub const VSTATE_CNT: u32 = 0x02;
3894 #[doc = "line cycle within one vscan state"]
3895 pub const VSTATE_CYCLE: u32 = 0x03;
3896 #[doc = "frame counter"]
3897 pub const FRAME_CNT: u32 = 0x04;
3898 #[doc = "frame cycle"]
3899 pub const FRAME_CYCLE: u32 = 0x05;
3900 #[doc = "horizontal counter (pclk counter within one line )"]
3901 pub const HCNT: u32 = 0x06;
3902 #[doc = "vertical counter (line counter within one frame)"]
3903 pub const VCNT: u32 = 0x07;
3904 }
3905 }
3906 #[doc = "When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking"]
3907 pub mod MASK_CNT {
3908 pub const offset: u32 = 12;
3909 pub const mask: u32 = 0x0fff << offset;
3910 pub mod R {}
3911 pub mod W {}
3912 pub mod RW {}
3913 }
3914 #[doc = "state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking"]
3915 pub mod STATE_MASK {
3916 pub const offset: u32 = 24;
3917 pub const mask: u32 = 0xff << offset;
3918 pub mod R {}
3919 pub mod W {}
3920 pub mod RW {
3921 #[doc = "FRAME SYNC"]
3922 pub const FS: u32 = 0x01;
3923 #[doc = "FRAME BEGIN"]
3924 pub const FB: u32 = 0x02;
3925 #[doc = "FRAME DATA"]
3926 pub const FD: u32 = 0x04;
3927 #[doc = "FRAME END"]
3928 pub const FE: u32 = 0x08;
3929 #[doc = "LINE SYNC"]
3930 pub const LS: u32 = 0x10;
3931 #[doc = "LINE BEGIN"]
3932 pub const LB: u32 = 0x20;
3933 #[doc = "LINE DATA"]
3934 pub const LD: u32 = 0x40;
3935 #[doc = "LINE END"]
3936 pub const LE: u32 = 0x80;
3937 }
3938 }
3939}
3940#[doc = "Panel Interface Signal Generator Register"]
3941pub mod PIGEON_7_1 {
3942 #[doc = "Assert signal output when counter match this value"]
3943 pub mod SET_CNT {
3944 pub const offset: u32 = 0;
3945 pub const mask: u32 = 0xffff << offset;
3946 pub mod R {}
3947 pub mod W {}
3948 pub mod RW {
3949 #[doc = "Start as active"]
3950 pub const START_ACTIVE: u32 = 0;
3951 }
3952 }
3953 #[doc = "Deassert signal output when counter match this value"]
3954 pub mod CLR_CNT {
3955 pub const offset: u32 = 16;
3956 pub const mask: u32 = 0xffff << offset;
3957 pub mod R {}
3958 pub mod W {}
3959 pub mod RW {
3960 #[doc = "Keep active until mask off"]
3961 pub const CLEAR_USING_MASK: u32 = 0;
3962 }
3963 }
3964}
3965#[doc = "Panel Interface Signal Generator Register"]
3966pub mod PIGEON_7_2 {
3967 #[doc = "Logic operation with another signal: DIS/AND/OR/COND"]
3968 pub mod SIG_LOGIC {
3969 pub const offset: u32 = 0;
3970 pub const mask: u32 = 0x0f << offset;
3971 pub mod R {}
3972 pub mod W {}
3973 pub mod RW {
3974 #[doc = "No logic operation"]
3975 pub const DIS: u32 = 0;
3976 #[doc = "sigout = sig_another AND this_sig"]
3977 pub const AND: u32 = 0x01;
3978 #[doc = "sigout = sig_another OR this_sig"]
3979 pub const OR: u32 = 0x02;
3980 #[doc = "mask = sig_another AND other_masks"]
3981 pub const MASK: u32 = 0x03;
3982 }
3983 }
3984 #[doc = "Select another signal for logic operation or as mask or counter tick event"]
3985 pub mod SIG_ANOTHER {
3986 pub const offset: u32 = 4;
3987 pub const mask: u32 = 0x1f << offset;
3988 pub mod R {}
3989 pub mod W {}
3990 pub mod RW {
3991 #[doc = "Keep active until mask off"]
3992 pub const CLEAR_USING_MASK: u32 = 0;
3993 }
3994 }
3995}
3996#[doc = "Panel Interface Signal Generator Register"]
3997pub mod PIGEON_8_0 {
3998 #[doc = "Enable pigeon Mode on this signal"]
3999 pub mod EN {
4000 pub const offset: u32 = 0;
4001 pub const mask: u32 = 0x01 << offset;
4002 pub mod R {}
4003 pub mod W {}
4004 pub mod RW {}
4005 }
4006 #[doc = "Polarity of signal output"]
4007 pub mod POL {
4008 pub const offset: u32 = 1;
4009 pub const mask: u32 = 0x01 << offset;
4010 pub mod R {}
4011 pub mod W {}
4012 pub mod RW {
4013 #[doc = "Normal Signal (Active high)"]
4014 pub const ACTIVE_HIGH: u32 = 0;
4015 #[doc = "Inverted signal (Active low)"]
4016 pub const ACTIVE_LOW: u32 = 0x01;
4017 }
4018 }
4019 #[doc = "Event to incrment local counter"]
4020 pub mod INC_SEL {
4021 pub const offset: u32 = 2;
4022 pub const mask: u32 = 0x03 << offset;
4023 pub mod R {}
4024 pub mod W {}
4025 pub mod RW {
4026 #[doc = "pclk"]
4027 pub const PCLK: u32 = 0;
4028 #[doc = "Line start pulse"]
4029 pub const LINE: u32 = 0x01;
4030 #[doc = "Frame start pulse"]
4031 pub const FRAME: u32 = 0x02;
4032 #[doc = "Use another signal as tick event"]
4033 pub const SIG_ANOTHER: u32 = 0x03;
4034 }
4035 }
4036 #[doc = "offset on pclk unit"]
4037 pub mod OFFSET {
4038 pub const offset: u32 = 4;
4039 pub const mask: u32 = 0x0f << offset;
4040 pub mod R {}
4041 pub mod W {}
4042 pub mod RW {}
4043 }
4044 #[doc = "select global counters as mask condition, use together with MASK_CNT"]
4045 pub mod MASK_CNT_SEL {
4046 pub const offset: u32 = 8;
4047 pub const mask: u32 = 0x0f << offset;
4048 pub mod R {}
4049 pub mod W {}
4050 pub mod RW {
4051 #[doc = "pclk counter within one hscan state"]
4052 pub const HSTATE_CNT: u32 = 0;
4053 #[doc = "pclk cycle within one hscan state"]
4054 pub const HSTATE_CYCLE: u32 = 0x01;
4055 #[doc = "line counter within one vscan state"]
4056 pub const VSTATE_CNT: u32 = 0x02;
4057 #[doc = "line cycle within one vscan state"]
4058 pub const VSTATE_CYCLE: u32 = 0x03;
4059 #[doc = "frame counter"]
4060 pub const FRAME_CNT: u32 = 0x04;
4061 #[doc = "frame cycle"]
4062 pub const FRAME_CYCLE: u32 = 0x05;
4063 #[doc = "horizontal counter (pclk counter within one line )"]
4064 pub const HCNT: u32 = 0x06;
4065 #[doc = "vertical counter (line counter within one frame)"]
4066 pub const VCNT: u32 = 0x07;
4067 }
4068 }
4069 #[doc = "When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking"]
4070 pub mod MASK_CNT {
4071 pub const offset: u32 = 12;
4072 pub const mask: u32 = 0x0fff << offset;
4073 pub mod R {}
4074 pub mod W {}
4075 pub mod RW {}
4076 }
4077 #[doc = "state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking"]
4078 pub mod STATE_MASK {
4079 pub const offset: u32 = 24;
4080 pub const mask: u32 = 0xff << offset;
4081 pub mod R {}
4082 pub mod W {}
4083 pub mod RW {
4084 #[doc = "FRAME SYNC"]
4085 pub const FS: u32 = 0x01;
4086 #[doc = "FRAME BEGIN"]
4087 pub const FB: u32 = 0x02;
4088 #[doc = "FRAME DATA"]
4089 pub const FD: u32 = 0x04;
4090 #[doc = "FRAME END"]
4091 pub const FE: u32 = 0x08;
4092 #[doc = "LINE SYNC"]
4093 pub const LS: u32 = 0x10;
4094 #[doc = "LINE BEGIN"]
4095 pub const LB: u32 = 0x20;
4096 #[doc = "LINE DATA"]
4097 pub const LD: u32 = 0x40;
4098 #[doc = "LINE END"]
4099 pub const LE: u32 = 0x80;
4100 }
4101 }
4102}
4103#[doc = "Panel Interface Signal Generator Register"]
4104pub mod PIGEON_8_1 {
4105 #[doc = "Assert signal output when counter match this value"]
4106 pub mod SET_CNT {
4107 pub const offset: u32 = 0;
4108 pub const mask: u32 = 0xffff << offset;
4109 pub mod R {}
4110 pub mod W {}
4111 pub mod RW {
4112 #[doc = "Start as active"]
4113 pub const START_ACTIVE: u32 = 0;
4114 }
4115 }
4116 #[doc = "Deassert signal output when counter match this value"]
4117 pub mod CLR_CNT {
4118 pub const offset: u32 = 16;
4119 pub const mask: u32 = 0xffff << offset;
4120 pub mod R {}
4121 pub mod W {}
4122 pub mod RW {
4123 #[doc = "Keep active until mask off"]
4124 pub const CLEAR_USING_MASK: u32 = 0;
4125 }
4126 }
4127}
4128#[doc = "Panel Interface Signal Generator Register"]
4129pub mod PIGEON_8_2 {
4130 #[doc = "Logic operation with another signal: DIS/AND/OR/COND"]
4131 pub mod SIG_LOGIC {
4132 pub const offset: u32 = 0;
4133 pub const mask: u32 = 0x0f << offset;
4134 pub mod R {}
4135 pub mod W {}
4136 pub mod RW {
4137 #[doc = "No logic operation"]
4138 pub const DIS: u32 = 0;
4139 #[doc = "sigout = sig_another AND this_sig"]
4140 pub const AND: u32 = 0x01;
4141 #[doc = "sigout = sig_another OR this_sig"]
4142 pub const OR: u32 = 0x02;
4143 #[doc = "mask = sig_another AND other_masks"]
4144 pub const MASK: u32 = 0x03;
4145 }
4146 }
4147 #[doc = "Select another signal for logic operation or as mask or counter tick event"]
4148 pub mod SIG_ANOTHER {
4149 pub const offset: u32 = 4;
4150 pub const mask: u32 = 0x1f << offset;
4151 pub mod R {}
4152 pub mod W {}
4153 pub mod RW {
4154 #[doc = "Keep active until mask off"]
4155 pub const CLEAR_USING_MASK: u32 = 0;
4156 }
4157 }
4158}
4159#[doc = "Panel Interface Signal Generator Register"]
4160pub mod PIGEON_9_0 {
4161 #[doc = "Enable pigeon Mode on this signal"]
4162 pub mod EN {
4163 pub const offset: u32 = 0;
4164 pub const mask: u32 = 0x01 << offset;
4165 pub mod R {}
4166 pub mod W {}
4167 pub mod RW {}
4168 }
4169 #[doc = "Polarity of signal output"]
4170 pub mod POL {
4171 pub const offset: u32 = 1;
4172 pub const mask: u32 = 0x01 << offset;
4173 pub mod R {}
4174 pub mod W {}
4175 pub mod RW {
4176 #[doc = "Normal Signal (Active high)"]
4177 pub const ACTIVE_HIGH: u32 = 0;
4178 #[doc = "Inverted signal (Active low)"]
4179 pub const ACTIVE_LOW: u32 = 0x01;
4180 }
4181 }
4182 #[doc = "Event to incrment local counter"]
4183 pub mod INC_SEL {
4184 pub const offset: u32 = 2;
4185 pub const mask: u32 = 0x03 << offset;
4186 pub mod R {}
4187 pub mod W {}
4188 pub mod RW {
4189 #[doc = "pclk"]
4190 pub const PCLK: u32 = 0;
4191 #[doc = "Line start pulse"]
4192 pub const LINE: u32 = 0x01;
4193 #[doc = "Frame start pulse"]
4194 pub const FRAME: u32 = 0x02;
4195 #[doc = "Use another signal as tick event"]
4196 pub const SIG_ANOTHER: u32 = 0x03;
4197 }
4198 }
4199 #[doc = "offset on pclk unit"]
4200 pub mod OFFSET {
4201 pub const offset: u32 = 4;
4202 pub const mask: u32 = 0x0f << offset;
4203 pub mod R {}
4204 pub mod W {}
4205 pub mod RW {}
4206 }
4207 #[doc = "select global counters as mask condition, use together with MASK_CNT"]
4208 pub mod MASK_CNT_SEL {
4209 pub const offset: u32 = 8;
4210 pub const mask: u32 = 0x0f << offset;
4211 pub mod R {}
4212 pub mod W {}
4213 pub mod RW {
4214 #[doc = "pclk counter within one hscan state"]
4215 pub const HSTATE_CNT: u32 = 0;
4216 #[doc = "pclk cycle within one hscan state"]
4217 pub const HSTATE_CYCLE: u32 = 0x01;
4218 #[doc = "line counter within one vscan state"]
4219 pub const VSTATE_CNT: u32 = 0x02;
4220 #[doc = "line cycle within one vscan state"]
4221 pub const VSTATE_CYCLE: u32 = 0x03;
4222 #[doc = "frame counter"]
4223 pub const FRAME_CNT: u32 = 0x04;
4224 #[doc = "frame cycle"]
4225 pub const FRAME_CYCLE: u32 = 0x05;
4226 #[doc = "horizontal counter (pclk counter within one line )"]
4227 pub const HCNT: u32 = 0x06;
4228 #[doc = "vertical counter (line counter within one frame)"]
4229 pub const VCNT: u32 = 0x07;
4230 }
4231 }
4232 #[doc = "When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking"]
4233 pub mod MASK_CNT {
4234 pub const offset: u32 = 12;
4235 pub const mask: u32 = 0x0fff << offset;
4236 pub mod R {}
4237 pub mod W {}
4238 pub mod RW {}
4239 }
4240 #[doc = "state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking"]
4241 pub mod STATE_MASK {
4242 pub const offset: u32 = 24;
4243 pub const mask: u32 = 0xff << offset;
4244 pub mod R {}
4245 pub mod W {}
4246 pub mod RW {
4247 #[doc = "FRAME SYNC"]
4248 pub const FS: u32 = 0x01;
4249 #[doc = "FRAME BEGIN"]
4250 pub const FB: u32 = 0x02;
4251 #[doc = "FRAME DATA"]
4252 pub const FD: u32 = 0x04;
4253 #[doc = "FRAME END"]
4254 pub const FE: u32 = 0x08;
4255 #[doc = "LINE SYNC"]
4256 pub const LS: u32 = 0x10;
4257 #[doc = "LINE BEGIN"]
4258 pub const LB: u32 = 0x20;
4259 #[doc = "LINE DATA"]
4260 pub const LD: u32 = 0x40;
4261 #[doc = "LINE END"]
4262 pub const LE: u32 = 0x80;
4263 }
4264 }
4265}
4266#[doc = "Panel Interface Signal Generator Register"]
4267pub mod PIGEON_9_1 {
4268 #[doc = "Assert signal output when counter match this value"]
4269 pub mod SET_CNT {
4270 pub const offset: u32 = 0;
4271 pub const mask: u32 = 0xffff << offset;
4272 pub mod R {}
4273 pub mod W {}
4274 pub mod RW {
4275 #[doc = "Start as active"]
4276 pub const START_ACTIVE: u32 = 0;
4277 }
4278 }
4279 #[doc = "Deassert signal output when counter match this value"]
4280 pub mod CLR_CNT {
4281 pub const offset: u32 = 16;
4282 pub const mask: u32 = 0xffff << offset;
4283 pub mod R {}
4284 pub mod W {}
4285 pub mod RW {
4286 #[doc = "Keep active until mask off"]
4287 pub const CLEAR_USING_MASK: u32 = 0;
4288 }
4289 }
4290}
4291#[doc = "Panel Interface Signal Generator Register"]
4292pub mod PIGEON_9_2 {
4293 #[doc = "Logic operation with another signal: DIS/AND/OR/COND"]
4294 pub mod SIG_LOGIC {
4295 pub const offset: u32 = 0;
4296 pub const mask: u32 = 0x0f << offset;
4297 pub mod R {}
4298 pub mod W {}
4299 pub mod RW {
4300 #[doc = "No logic operation"]
4301 pub const DIS: u32 = 0;
4302 #[doc = "sigout = sig_another AND this_sig"]
4303 pub const AND: u32 = 0x01;
4304 #[doc = "sigout = sig_another OR this_sig"]
4305 pub const OR: u32 = 0x02;
4306 #[doc = "mask = sig_another AND other_masks"]
4307 pub const MASK: u32 = 0x03;
4308 }
4309 }
4310 #[doc = "Select another signal for logic operation or as mask or counter tick event"]
4311 pub mod SIG_ANOTHER {
4312 pub const offset: u32 = 4;
4313 pub const mask: u32 = 0x1f << offset;
4314 pub mod R {}
4315 pub mod W {}
4316 pub mod RW {
4317 #[doc = "Keep active until mask off"]
4318 pub const CLEAR_USING_MASK: u32 = 0;
4319 }
4320 }
4321}
4322#[doc = "Panel Interface Signal Generator Register"]
4323pub mod PIGEON_10_0 {
4324 #[doc = "Enable pigeon Mode on this signal"]
4325 pub mod EN {
4326 pub const offset: u32 = 0;
4327 pub const mask: u32 = 0x01 << offset;
4328 pub mod R {}
4329 pub mod W {}
4330 pub mod RW {}
4331 }
4332 #[doc = "Polarity of signal output"]
4333 pub mod POL {
4334 pub const offset: u32 = 1;
4335 pub const mask: u32 = 0x01 << offset;
4336 pub mod R {}
4337 pub mod W {}
4338 pub mod RW {
4339 #[doc = "Normal Signal (Active high)"]
4340 pub const ACTIVE_HIGH: u32 = 0;
4341 #[doc = "Inverted signal (Active low)"]
4342 pub const ACTIVE_LOW: u32 = 0x01;
4343 }
4344 }
4345 #[doc = "Event to incrment local counter"]
4346 pub mod INC_SEL {
4347 pub const offset: u32 = 2;
4348 pub const mask: u32 = 0x03 << offset;
4349 pub mod R {}
4350 pub mod W {}
4351 pub mod RW {
4352 #[doc = "pclk"]
4353 pub const PCLK: u32 = 0;
4354 #[doc = "Line start pulse"]
4355 pub const LINE: u32 = 0x01;
4356 #[doc = "Frame start pulse"]
4357 pub const FRAME: u32 = 0x02;
4358 #[doc = "Use another signal as tick event"]
4359 pub const SIG_ANOTHER: u32 = 0x03;
4360 }
4361 }
4362 #[doc = "offset on pclk unit"]
4363 pub mod OFFSET {
4364 pub const offset: u32 = 4;
4365 pub const mask: u32 = 0x0f << offset;
4366 pub mod R {}
4367 pub mod W {}
4368 pub mod RW {}
4369 }
4370 #[doc = "select global counters as mask condition, use together with MASK_CNT"]
4371 pub mod MASK_CNT_SEL {
4372 pub const offset: u32 = 8;
4373 pub const mask: u32 = 0x0f << offset;
4374 pub mod R {}
4375 pub mod W {}
4376 pub mod RW {
4377 #[doc = "pclk counter within one hscan state"]
4378 pub const HSTATE_CNT: u32 = 0;
4379 #[doc = "pclk cycle within one hscan state"]
4380 pub const HSTATE_CYCLE: u32 = 0x01;
4381 #[doc = "line counter within one vscan state"]
4382 pub const VSTATE_CNT: u32 = 0x02;
4383 #[doc = "line cycle within one vscan state"]
4384 pub const VSTATE_CYCLE: u32 = 0x03;
4385 #[doc = "frame counter"]
4386 pub const FRAME_CNT: u32 = 0x04;
4387 #[doc = "frame cycle"]
4388 pub const FRAME_CYCLE: u32 = 0x05;
4389 #[doc = "horizontal counter (pclk counter within one line )"]
4390 pub const HCNT: u32 = 0x06;
4391 #[doc = "vertical counter (line counter within one frame)"]
4392 pub const VCNT: u32 = 0x07;
4393 }
4394 }
4395 #[doc = "When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking"]
4396 pub mod MASK_CNT {
4397 pub const offset: u32 = 12;
4398 pub const mask: u32 = 0x0fff << offset;
4399 pub mod R {}
4400 pub mod W {}
4401 pub mod RW {}
4402 }
4403 #[doc = "state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking"]
4404 pub mod STATE_MASK {
4405 pub const offset: u32 = 24;
4406 pub const mask: u32 = 0xff << offset;
4407 pub mod R {}
4408 pub mod W {}
4409 pub mod RW {
4410 #[doc = "FRAME SYNC"]
4411 pub const FS: u32 = 0x01;
4412 #[doc = "FRAME BEGIN"]
4413 pub const FB: u32 = 0x02;
4414 #[doc = "FRAME DATA"]
4415 pub const FD: u32 = 0x04;
4416 #[doc = "FRAME END"]
4417 pub const FE: u32 = 0x08;
4418 #[doc = "LINE SYNC"]
4419 pub const LS: u32 = 0x10;
4420 #[doc = "LINE BEGIN"]
4421 pub const LB: u32 = 0x20;
4422 #[doc = "LINE DATA"]
4423 pub const LD: u32 = 0x40;
4424 #[doc = "LINE END"]
4425 pub const LE: u32 = 0x80;
4426 }
4427 }
4428}
4429#[doc = "Panel Interface Signal Generator Register"]
4430pub mod PIGEON_10_1 {
4431 #[doc = "Assert signal output when counter match this value"]
4432 pub mod SET_CNT {
4433 pub const offset: u32 = 0;
4434 pub const mask: u32 = 0xffff << offset;
4435 pub mod R {}
4436 pub mod W {}
4437 pub mod RW {
4438 #[doc = "Start as active"]
4439 pub const START_ACTIVE: u32 = 0;
4440 }
4441 }
4442 #[doc = "Deassert signal output when counter match this value"]
4443 pub mod CLR_CNT {
4444 pub const offset: u32 = 16;
4445 pub const mask: u32 = 0xffff << offset;
4446 pub mod R {}
4447 pub mod W {}
4448 pub mod RW {
4449 #[doc = "Keep active until mask off"]
4450 pub const CLEAR_USING_MASK: u32 = 0;
4451 }
4452 }
4453}
4454#[doc = "Panel Interface Signal Generator Register"]
4455pub mod PIGEON_10_2 {
4456 #[doc = "Logic operation with another signal: DIS/AND/OR/COND"]
4457 pub mod SIG_LOGIC {
4458 pub const offset: u32 = 0;
4459 pub const mask: u32 = 0x0f << offset;
4460 pub mod R {}
4461 pub mod W {}
4462 pub mod RW {
4463 #[doc = "No logic operation"]
4464 pub const DIS: u32 = 0;
4465 #[doc = "sigout = sig_another AND this_sig"]
4466 pub const AND: u32 = 0x01;
4467 #[doc = "sigout = sig_another OR this_sig"]
4468 pub const OR: u32 = 0x02;
4469 #[doc = "mask = sig_another AND other_masks"]
4470 pub const MASK: u32 = 0x03;
4471 }
4472 }
4473 #[doc = "Select another signal for logic operation or as mask or counter tick event"]
4474 pub mod SIG_ANOTHER {
4475 pub const offset: u32 = 4;
4476 pub const mask: u32 = 0x1f << offset;
4477 pub mod R {}
4478 pub mod W {}
4479 pub mod RW {
4480 #[doc = "Keep active until mask off"]
4481 pub const CLEAR_USING_MASK: u32 = 0;
4482 }
4483 }
4484}
4485#[doc = "Panel Interface Signal Generator Register"]
4486pub mod PIGEON_11_0 {
4487 #[doc = "Enable pigeon Mode on this signal"]
4488 pub mod EN {
4489 pub const offset: u32 = 0;
4490 pub const mask: u32 = 0x01 << offset;
4491 pub mod R {}
4492 pub mod W {}
4493 pub mod RW {}
4494 }
4495 #[doc = "Polarity of signal output"]
4496 pub mod POL {
4497 pub const offset: u32 = 1;
4498 pub const mask: u32 = 0x01 << offset;
4499 pub mod R {}
4500 pub mod W {}
4501 pub mod RW {
4502 #[doc = "Normal Signal (Active high)"]
4503 pub const ACTIVE_HIGH: u32 = 0;
4504 #[doc = "Inverted signal (Active low)"]
4505 pub const ACTIVE_LOW: u32 = 0x01;
4506 }
4507 }
4508 #[doc = "Event to incrment local counter"]
4509 pub mod INC_SEL {
4510 pub const offset: u32 = 2;
4511 pub const mask: u32 = 0x03 << offset;
4512 pub mod R {}
4513 pub mod W {}
4514 pub mod RW {
4515 #[doc = "pclk"]
4516 pub const PCLK: u32 = 0;
4517 #[doc = "Line start pulse"]
4518 pub const LINE: u32 = 0x01;
4519 #[doc = "Frame start pulse"]
4520 pub const FRAME: u32 = 0x02;
4521 #[doc = "Use another signal as tick event"]
4522 pub const SIG_ANOTHER: u32 = 0x03;
4523 }
4524 }
4525 #[doc = "offset on pclk unit"]
4526 pub mod OFFSET {
4527 pub const offset: u32 = 4;
4528 pub const mask: u32 = 0x0f << offset;
4529 pub mod R {}
4530 pub mod W {}
4531 pub mod RW {}
4532 }
4533 #[doc = "select global counters as mask condition, use together with MASK_CNT"]
4534 pub mod MASK_CNT_SEL {
4535 pub const offset: u32 = 8;
4536 pub const mask: u32 = 0x0f << offset;
4537 pub mod R {}
4538 pub mod W {}
4539 pub mod RW {
4540 #[doc = "pclk counter within one hscan state"]
4541 pub const HSTATE_CNT: u32 = 0;
4542 #[doc = "pclk cycle within one hscan state"]
4543 pub const HSTATE_CYCLE: u32 = 0x01;
4544 #[doc = "line counter within one vscan state"]
4545 pub const VSTATE_CNT: u32 = 0x02;
4546 #[doc = "line cycle within one vscan state"]
4547 pub const VSTATE_CYCLE: u32 = 0x03;
4548 #[doc = "frame counter"]
4549 pub const FRAME_CNT: u32 = 0x04;
4550 #[doc = "frame cycle"]
4551 pub const FRAME_CYCLE: u32 = 0x05;
4552 #[doc = "horizontal counter (pclk counter within one line )"]
4553 pub const HCNT: u32 = 0x06;
4554 #[doc = "vertical counter (line counter within one frame)"]
4555 pub const VCNT: u32 = 0x07;
4556 }
4557 }
4558 #[doc = "When the global counter selected through MASK_CNT_SEL matches value in this reg, pigeon local counter start ticking"]
4559 pub mod MASK_CNT {
4560 pub const offset: u32 = 12;
4561 pub const mask: u32 = 0x0fff << offset;
4562 pub mod R {}
4563 pub mod W {}
4564 pub mod RW {}
4565 }
4566 #[doc = "state_mask = (FS|FB|FD|FE) and (LS|LB|LD|LE) , select any combination of scan states as reference point for local counter to start ticking"]
4567 pub mod STATE_MASK {
4568 pub const offset: u32 = 24;
4569 pub const mask: u32 = 0xff << offset;
4570 pub mod R {}
4571 pub mod W {}
4572 pub mod RW {
4573 #[doc = "FRAME SYNC"]
4574 pub const FS: u32 = 0x01;
4575 #[doc = "FRAME BEGIN"]
4576 pub const FB: u32 = 0x02;
4577 #[doc = "FRAME DATA"]
4578 pub const FD: u32 = 0x04;
4579 #[doc = "FRAME END"]
4580 pub const FE: u32 = 0x08;
4581 #[doc = "LINE SYNC"]
4582 pub const LS: u32 = 0x10;
4583 #[doc = "LINE BEGIN"]
4584 pub const LB: u32 = 0x20;
4585 #[doc = "LINE DATA"]
4586 pub const LD: u32 = 0x40;
4587 #[doc = "LINE END"]
4588 pub const LE: u32 = 0x80;
4589 }
4590 }
4591}
4592#[doc = "Panel Interface Signal Generator Register"]
4593pub mod PIGEON_11_1 {
4594 #[doc = "Assert signal output when counter match this value"]
4595 pub mod SET_CNT {
4596 pub const offset: u32 = 0;
4597 pub const mask: u32 = 0xffff << offset;
4598 pub mod R {}
4599 pub mod W {}
4600 pub mod RW {
4601 #[doc = "Start as active"]
4602 pub const START_ACTIVE: u32 = 0;
4603 }
4604 }
4605 #[doc = "Deassert signal output when counter match this value"]
4606 pub mod CLR_CNT {
4607 pub const offset: u32 = 16;
4608 pub const mask: u32 = 0xffff << offset;
4609 pub mod R {}
4610 pub mod W {}
4611 pub mod RW {
4612 #[doc = "Keep active until mask off"]
4613 pub const CLEAR_USING_MASK: u32 = 0;
4614 }
4615 }
4616}
4617#[doc = "Panel Interface Signal Generator Register"]
4618pub mod PIGEON_11_2 {
4619 #[doc = "Logic operation with another signal: DIS/AND/OR/COND"]
4620 pub mod SIG_LOGIC {
4621 pub const offset: u32 = 0;
4622 pub const mask: u32 = 0x0f << offset;
4623 pub mod R {}
4624 pub mod W {}
4625 pub mod RW {
4626 #[doc = "No logic operation"]
4627 pub const DIS: u32 = 0;
4628 #[doc = "sigout = sig_another AND this_sig"]
4629 pub const AND: u32 = 0x01;
4630 #[doc = "sigout = sig_another OR this_sig"]
4631 pub const OR: u32 = 0x02;
4632 #[doc = "mask = sig_another AND other_masks"]
4633 pub const MASK: u32 = 0x03;
4634 }
4635 }
4636 #[doc = "Select another signal for logic operation or as mask or counter tick event"]
4637 pub mod SIG_ANOTHER {
4638 pub const offset: u32 = 4;
4639 pub const mask: u32 = 0x1f << offset;
4640 pub mod R {}
4641 pub mod W {}
4642 pub mod RW {
4643 #[doc = "Keep active until mask off"]
4644 pub const CLEAR_USING_MASK: u32 = 0;
4645 }
4646 }
4647}
4648#[doc = "Lookup Table Data Register."]
4649pub mod LUT_CTRL {
4650 #[doc = "Setting this bit will bypass the LUT memory resource completely"]
4651 pub mod LUT_BYPASS {
4652 pub const offset: u32 = 0;
4653 pub const mask: u32 = 0x01 << offset;
4654 pub mod R {}
4655 pub mod W {}
4656 pub mod RW {}
4657 }
4658}
4659#[doc = "Lookup Table Control Register."]
4660pub mod LUT0_ADDR {
4661 #[doc = "LUT indexed address pointer"]
4662 pub mod ADDR {
4663 pub const offset: u32 = 0;
4664 pub const mask: u32 = 0xff << offset;
4665 pub mod R {}
4666 pub mod W {}
4667 pub mod RW {}
4668 }
4669}
4670#[doc = "Lookup Table Data Register."]
4671pub mod LUT0_DATA {
4672 #[doc = "Writing this field will load 4 bytes, aligned to four byte boundaries, of data indexed by the ADDR field of the REG_LUT_CTRL register"]
4673 pub mod DATA {
4674 pub const offset: u32 = 0;
4675 pub const mask: u32 = 0xffff_ffff << offset;
4676 pub mod R {}
4677 pub mod W {}
4678 pub mod RW {}
4679 }
4680}
4681#[doc = "Lookup Table Control Register."]
4682pub mod LUT1_ADDR {
4683 #[doc = "LUT indexed address pointer"]
4684 pub mod ADDR {
4685 pub const offset: u32 = 0;
4686 pub const mask: u32 = 0xff << offset;
4687 pub mod R {}
4688 pub mod W {}
4689 pub mod RW {}
4690 }
4691}
4692#[doc = "Lookup Table Data Register."]
4693pub mod LUT1_DATA {
4694 #[doc = "Writing this field will load 4 bytes, aligned to four byte boundaries, of data indexed by the ADDR field of the REG_LUT_CTRL register"]
4695 pub mod DATA {
4696 pub const offset: u32 = 0;
4697 pub const mask: u32 = 0xffff_ffff << offset;
4698 pub mod R {}
4699 pub mod W {}
4700 pub mod RW {}
4701 }
4702}