Module imxrt_ral::can::CTRL2

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Control 2 Register

Modules§

  • EACEN
    This bit controls the comparison of IDE and RTR bits within Rx Mailboxes filters with their corresponding bits in the incoming frame by the matching process
  • MRP
    If this bit is set the matching process starts from the Mailboxes and if no match occurs the matching continues on the Rx FIFO
  • RFFN
    This 4-bit field defines the number of Rx FIFO filters according to
  • RRS
    If this bit is asserted Remote Request Frame is submitted to a matching process and stored in the corresponding Message Buffer in the same fashion of a Data Frame
  • TASD
    This 5-bit field indicates how many CAN bits the Tx arbitration process start point can be delayed from the first bit of CRC field on CAN bus
  • WRMFRZ
    Enable unrestricted write access to FlexCAN memory in Freeze mode