Module imxrt_ral::can::ESR1

Error and Status 1 Register

Modules

• ACKERR
  This bit indicates that an Acknowledge Error has been detected by the transmitter node, i
• BIT0ERR
  This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message
• BIT1ERR
  This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message
• BOFFINT
  This bit is set when FLEXCAN enters ‘Bus Off’ state
• CRCERR
  This bit indicates that a CRC Error has been detected by the receiver node, i
• ERRINT
  This bit indicates that at least one of the Error Bits (bits 15-10) is set
• FLTCONF
  If the LOM bit in the Control Register is asserted, after some delay that depends on the CAN bit timing the FLT_CONF field will indicate “Error Passive”
• FRMERR
  This bit indicates that a Form Error has been detected by the receiver node, i
• IDLE
  This bit indicates when CAN bus is in IDLE state.Refer to .
• RWRNINT
  If the WRN_EN bit in MCR is asserted, the RWRN_INT bit is set when the RX_WRN flag transition from ‘0’ to ‘1’, meaning that the Rx error counters reached 96
• RX
  This bit indicates if FlexCAN is receiving a message. Refer to .
• RXWRN
  This bit indicates when repetitive errors are occurring during message reception.
• STFERR
  This bit indicates that a Stuffing Error has been detected.
• SYNCH
  This read-only flag indicates whether the FlexCAN is synchronized to the CAN bus and able to participate in the communication process
• TWRNINT
  If the WRN_EN bit in MCR is asserted, the TWRN_INT bit is set when the TX_WRN flag transition from ‘0’ to ‘1’, meaning that the Tx error counter reached 96
• TX
  This bit indicates if FLEXCAN is transmitting a message.Refer to .
• TXWRN
  This bit indicates when repetitive errors are occurring during message transmission.
• WAKINT
  When FLEXCAN is Stop Mode and a recessive to dominant transition is detected on the CAN bus and if the WAK_MSK bit in the MCR Register is set, an interrupt is generated to the Arm