Module MCR

Module Configuration Register

Modules

• AEN
  This bit is supplied for backwards compatibility reasons
• FRZ
  The FRZ bit specifies the FLEXCAN behavior when the HALT bit in the MCR Register is set or when Debug Mode is requested at Arm level
• FRZACK
  This read-only bit indicates that FLEXCAN is in Freeze Mode and its prescaler is stopped
• HALT
  Assertion of this bit puts the FLEXCAN module into Freeze Mode
• IDAM
  This 2-bit field identifies the format of the elements of the Rx FIFO filter table, as shown below
• IRMQ
  This bit indicates whether Rx matching process will be based either on individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and RX15MASK, RXFGMASK
• LPMACK
  This read-only bit indicates that FLEXCAN is either in Disable Mode or Stop Mode
• LPRIOEN
  This bit is provided for backwards compatibility reasons
• MAXMB
  This 7-bit field defines the number of the last Message Buffers that will take part in the matching and arbitration processes
• MDIS
  This bit controls whether FLEXCAN is enabled or not
• NOTRDY
  This read-only bit indicates that FLEXCAN is either in Disable Mode, Stop Mode or Freeze Mode
• RFEN
  This bit controls whether the Rx FIFO feature is enabled or not
• SLFWAK
  This bit enables the Self Wake Up feature when FLEXCAN is in Stop Mode
• SOFTRST
  When this bit is asserted, FlexCAN resets its internal state machines and some of the memory mapped registers
• SRXDIS
  This bit defines whether FlexCAN is allowed to receive frames transmitted by itself
• SUPV
  This bit configures some of the FLEXCAN registers to be either in Supervisor or User Mode
• WAKMSK
  This bit enables the Wake Up Interrupt generation.
• WAKSRC
  This bit defines whether the integrated low-pass filter is applied to protect the FLEXCAN_RX input from spurious wake up
• WRNEN
  When asserted, this bit enables the generation of the TWRN_INT and RWRN_INT flags in the Error and Status Register