imxrt_ral
0.6.0
In imxrt_ral::can3::ESR1::BIT0ERR::RW
Constant
imxrt_ral
::
can3
::
ESR1
::
BIT0ERR
::
RW
::
BIT0ERR_1
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source
ยท
[
−
]
pub const BIT0ERR_1:
u32
= 0x01;
Expand description
At least one bit sent as dominant is received as recessive.