Expand description
CCM Clock Gating Register 0
Modulesยง
- CG0
- aips_tz1 clocks (aips_tz1_clk_enable)
- CG1
- aips_tz2 clocks (aips_tz2_clk_enable)
- CG2
- mqs clock ( mqs_hmclk_clock_enable)
- CG3
- flexspi_exsc clock (flexspi_exsc_clk_enable)
- CG4
- sim_m or sim_main register access clock (sim_m_mainclk_r_enable)
- CG5
- dcp clock (dcp_clk_enable)
- CG6
- lpuart3 clock (lpuart3_clk_enable)
- CG7
- can1 clock (can1_clk_enable)
- CG8
- can1_serial clock (can1_serial_clk_enable)
- CG9
- can2 clock (can2_clk_enable)
- CG10
- can2_serial clock (can2_serial_clk_enable)
- CG11
- trace clock (trace_clk_enable)
- CG12
- gpt2 bus clocks (gpt2_bus_clk_enable)
- CG13
- gpt2 serial clocks (gpt2_serial_clk_enable)
- CG14
- lpuart2 clock (lpuart2_clk_enable)
- CG15
- gpio2_clocks (gpio2_clk_enable)