Module CDCDR

Source
Expand description

CCM D1 Clock Divider Register

Modulesยง

FLEXIO1_CLK_PODF
Divider for flexio1 clock podf. Divider should be updated when output clock is gated.
FLEXIO1_CLK_PRED
Divider for flexio1 clock pred. Divider should be updated when output clock is gated.
FLEXIO1_CLK_SEL
Selector for flexio1 clock multiplexer
SPDIF0_CLK_PODF
Divider for spdif0 clock podf. Divider should be updated when output clock is gated.
SPDIF0_CLK_PRED
Divider for spdif0 clock pred. Divider should be updated when output clock is gated.
SPDIF0_CLK_SEL
Selector for spdif0 clock multiplexer