Module CS1CDR

CCM Clock Divider Register

Modules

• FLEXIO2_CLK_PODF
  Divider for flexio2 clock. Divider should be updated when output clock is gated.
• FLEXIO2_CLK_PRED
  Divider for flexio2 clock.
• SAI1_CLK_PODF
  Divider for sai1 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.
• SAI1_CLK_PRED
  Divider for sai1 clock pred.
• SAI3_CLK_PODF
  Divider for sai3 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.
• SAI3_CLK_PRED
  Divider for sai3 clock pred.