imxrt_ral::ccm

Module CS2CDR

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CCM Clock Divider Register

Modulesยง

  • SAI2_CLK_PODF
    Divider for sai2 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.
  • SAI2_CLK_PRED
    Divider for sai2 clock pred.Divider should be updated when output clock is gated.