Module CSCDR2

Source
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CCM Serial Clock Divider Register 2

Modulesยง

LCDIF_PRED
Pre-divider for lcdif clock. Divider should be updated when output clock is gated.
LCDIF_PRE_CLK_SEL
Selector for lcdif root clock pre-multiplexer
LPI2C_CLK_PODF
Divider for lpi2c clock podf. Divider should be updated when output clock is gated. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.
LPI2C_CLK_SEL
Selector for the LPI2C clock multiplexor