FLEXIO2_CLK_SEL_0

imxrt_ral::ccm::CSCMR2::FLEXIO2_CLK_SEL::RW

Constant FLEXIO2_CLK_SEL_0 

Source 
pub const FLEXIO2_CLK_SEL_0: u32 = 0;
Expand description

derive clock from PLL4 divided clock