Module MISC0_CLR

Miscellaneous Register 0

Modules

• CLKGATE_CTRL
  This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block
• CLKGATE_DELAY
  This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block
• DISCON_HIGH_SNVS
  This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.
• OSC_I
  This field determines the bias current in the 24MHz oscillator
• OSC_XTALOK
  Status bit that signals that the output of the 24-MHz crystal oscillator is stable
• OSC_XTALOK_EN
  This bit enables the detector that signals when the 24MHz crystal oscillator is stable
• REFTOP_PWD
  Control bit to power-down the analog bandgap reference circuitry
• REFTOP_SELFBIASOFF
  Control bit to disable the self-bias circuit in the analog bandgap
• REFTOP_VBGADJ
  Not related to CCM. See Power Management Unit (PMU)
• REFTOP_VBGUP
  Status bit that signals the analog bandgap voltage is up and stable
• RTC_XTAL_SOURCE
  This field indicates which chip source is being used for the rtc clock
• STOP_MODE_CONFIG
  Configure the analog behavior in stop mode.
• XTAL_24M_PWD
  This field powers down the 24M crystal oscillator if set true