Module MISC2_CLR

Miscellaneous Register 2

Modules

• AUDIO_DIV_LSB
  LSB of Post-divider for Audio PLL
• AUDIO_DIV_MSB
  MSB of Post-divider for Audio PLL
• PLL3_DISABLE
  When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode
• REG0_BO_OFFSET
  This field defines the brown out voltage offset for the CORE power domain
• REG0_BO_STATUS
  Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU)
• REG0_ENABLE_BO
  Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)
• REG0_OK
  ARM supply Not related to CCM. See Power Management Unit (PMU)
• REG0_STEP_TIME
  Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)
• REG1_BO_OFFSET
  This field defines the brown out voltage offset for the xPU power domain
• REG1_BO_STATUS
  Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU)
• REG1_ENABLE_BO
  Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)
• REG1_OK
  GPU/VPU supply Not related to CCM. See Power Management Unit (PMU)
• REG1_STEP_TIME
  Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)
• REG2_BO_OFFSET
  This field defines the brown out voltage offset for the xPU power domain
• REG2_BO_STATUS
  Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU)
• REG2_ENABLE_BO
  Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)
• REG2_OK
  Signals that the voltage is above the brownout level for the SOC supply
• REG2_STEP_TIME
  Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)
• VIDEO_DIV
  Post-divider for video