Module PLL_ARM_CLR

Analog ARM PLL control Register

Modules

• BYPASS
  Bypass the PLL.
• BYPASS_CLK_SRC
  Determines the bypass source
• DIV_SELECT
  This field controls the PLL loop divider
• ENABLE
  Enable the clock output.
• LOCK
  1 - PLL is currently locked. 0 - PLL is not currently locked.
• POWERDOWN
  Powers down the PLL.