Module PLL_AUDIO_CLR

Analog Audio PLL control Register

Modules

• BYPASS
  Bypass the PLL.
• BYPASS_CLK_SRC
  Determines the bypass source.
• DIV_SELECT
  This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.
• ENABLE
  Enable PLL output
• LOCK
  1 - PLL is currently locked. 0 - PLL is not currently locked.
• POST_DIV_SELECT
  These bits implement a divider after the PLL, but before the enable and bypass mux.
• POWERDOWN
  Powers down the PLL.