Module PLL_ENET_CLR

Analog ENET PLL Control Register

Modules

• BYPASS
  Bypass the PLL.
• BYPASS_CLK_SRC
  Determines the bypass source.
• DIV_SELECT
  Controls the frequency of the ethernet reference clock
• ENABLE
  Enable the PLL providing the ENET reference clock.
• ENET2_DIV_SELECT
  Controls the frequency of the ENET2 reference clock.
• ENET2_REF_EN
  Enable the PLL providing the ENET2 reference clock
• ENET_25M_REF_EN
  Enable the PLL providing ENET 25 MHz reference clock
• LOCK
  1 - PLL is currently locked; 0 - PLL is not currently locked.
• POWERDOWN
  Powers down the PLL.