Module PLL_SYS_CLR

Analog System PLL Control Register

Modules

• BYPASS
  Bypass the PLL.
• BYPASS_CLK_SRC
  Determines the bypass source.
• DIV_SELECT
  This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22.
• ENABLE
  Enable PLL output
• LOCK
  1 - PLL is currently locked; 0 - PLL is not currently locked.
• POWERDOWN
  Powers down the PLL.