Module PLL_USB1_CLR

Analog USB1 480MHz PLL Control Register

Modules

• BYPASS
  Bypass the PLL.
• BYPASS_CLK_SRC
  Determines the bypass source.
• DIV_SELECT
  This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22.
• ENABLE
  Enable the PLL clock output.
• EN_USB_CLKS
  Powers the 9-phase PLL outputs for USBPHYn
• LOCK
  1 - PLL is currently locked. 0 - PLL is not currently locked.
• POWER
  Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens.