imxrt_ral::ccm_analog

Module PLL_USB1_TOG

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Expand description

Analog USB1 480MHz PLL Control Register

Modulesยง

  • Bypass the PLL.
  • Determines the bypass source.
  • This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22.
  • Enable the PLL clock output.
  • Powers the 9-phase PLL outputs for USBPHYn
  • 1 - PLL is currently locked. 0 - PLL is not currently locked.
  • Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens.