Module CSICR1

CSI Control Register 1

Modules

• CCIR_EN
  CCIR656 Interface Enable
• CCIR_MODE
  CCIR Mode Select
• CLR_RXFIFO
  Asynchronous RXFIFO Clear
• CLR_STATFIFO
  Asynchronous STATFIFO Clear
• COF_INT_EN
  Change Of Image Field (COF) Interrupt Enable
• EOF_INT_EN
  End-of-Frame Interrupt Enable. This bit enables and disables the EOF interrupt.
• EXT_VSYNC
  External VSYNC Enable
• FB1_DMA_DONE_INTEN
  Frame Buffer1 DMA Transfer Done Interrupt Enable
• FB2_DMA_DONE_INTEN
  Frame Buffer2 DMA Transfer Done Interrupt Enable
• FCC
  FIFO Clear Control
• GCLK_MODE
  Gated Clock Mode Enable
• HSYNC_POL
  HSYNC Polarity Select
• INV_DATA
  Invert Data Input. This bit enables or disables internal inverters on the data lines.
• INV_PCLK
  Invert Pixel Clock Input
• PACK_DIR
  Data Packing Direction
• PIXEL_BIT
  Pixel Bit
• PRP_IF_EN
  CSI-PrP Interface Enable
• REDGE
  Valid Pixel Clock Edge Select
• RF_OR_INTEN
  RxFIFO Overrun Interrupt Enable. This bit enables the RX FIFO overrun interrupt.
• RXFF_INTEN
  RxFIFO Full Interrupt Enable. This bit enables the RxFIFO full interrupt.
• SFF_DMA_DONE_INTEN
  STATFIFO DMA Transfer Done Interrupt Enable
• SF_OR_INTEN
  STAT FIFO Overrun Interrupt Enable. This bit enables the STATFIFO overrun interrupt.
• SOF_INTEN
  Start Of Frame (SOF) Interrupt Enable. This bit enables the SOF interrupt.
• SOF_POL
  SOF Interrupt Polarity. This bit controls the condition that generates an SOF interrupt.
• STATFF_INTEN
  STATFIFO Full Interrupt Enable. This bit enables the STAT FIFO interrupt.
• SWAP16_EN
  SWAP 16-Bit Enable