Expand description
CSI Control Register 1
Modulesยง
- CCIR_EN
- CCIR656 Interface Enable
- CCIR_
MODE - CCIR Mode Select
- CLR_
RXFIFO - Asynchronous RXFIFO Clear
- CLR_
STATFIFO - Asynchronous STATFIFO Clear
- COF_
INT_ EN - Change Of Image Field (COF) Interrupt Enable
- EOF_
INT_ EN - End-of-Frame Interrupt Enable. This bit enables and disables the EOF interrupt.
- EXT_
VSYNC - External VSYNC Enable
- FB1_
DMA_ DONE_ INTEN - Frame Buffer1 DMA Transfer Done Interrupt Enable
- FB2_
DMA_ DONE_ INTEN - Frame Buffer2 DMA Transfer Done Interrupt Enable
- FCC
- FIFO Clear Control
- GCLK_
MODE - Gated Clock Mode Enable
- HSYNC_
POL - HSYNC Polarity Select
- INV_
DATA - Invert Data Input. This bit enables or disables internal inverters on the data lines.
- INV_
PCLK - Invert Pixel Clock Input
- PACK_
DIR - Data Packing Direction
- PIXEL_
BIT - Pixel Bit
- PRP_
IF_ EN - CSI-PrP Interface Enable
- REDGE
- Valid Pixel Clock Edge Select
- RF_
OR_ INTEN - RxFIFO Overrun Interrupt Enable. This bit enables the RX FIFO overrun interrupt.
- RXFF_
INTEN - RxFIFO Full Interrupt Enable. This bit enables the RxFIFO full interrupt.
- SFF_
DMA_ DONE_ INTEN - STATFIFO DMA Transfer Done Interrupt Enable
- SF_
OR_ INTEN - STAT FIFO Overrun Interrupt Enable. This bit enables the STATFIFO overrun interrupt.
- SOF_
INTEN - Start Of Frame (SOF) Interrupt Enable. This bit enables the SOF interrupt.
- SOF_POL
- SOF Interrupt Polarity. This bit controls the condition that generates an SOF interrupt.
- STATFF_
INTEN - STATFIFO Full Interrupt Enable. This bit enables the STAT FIFO interrupt.
- SWAP16_
EN - SWAP 16-Bit Enable