Module imxrt_ral::csi::CSISR

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CSI Status Register

Modules§

  • When using base address switching enable, this bit will be 1 when switching occur before DMA complete
  • Change Of Field Interrupt Status
  • When DMA field 0 is complete, this bit will be set to 1(clear by writing 1).
  • When DMA field 0 is complete, this bit will be set to 1(clear by writing 1).
  • DMA Transfer Done in Frame Buffer1
  • DMA Transfer Done in Frame Buffer2
  • DMA Transfer Done from StatFIFO
  • RXFIFO Data Ready
  • CCIR Error Interrupt
  • End of Frame (EOF) Interrupt Status. Indicates when EOF is detected. (Cleared by writing 1)
  • CCIR Field 1 Interrupt Status
  • CCIR Field 2 Interrupt Status
  • Hresponse Error Interrupt Status
  • RxFIFO Overrun Interrupt Status
  • RXFIFO Full Interrupt Status
  • STATFIFO Overrun Interrupt Status
  • Start of Frame Interrupt Status. Indicates when SOF is detected. (Cleared by writing 1)
  • STATFIFO Full Interrupt Status