imxrt_ral::dcdc

Module REG3

source
Expand description

DCDC Register 3

Modulesยง

  • DISABLE_STEP
    Disable stepping for the output VDD_SOC of DCDC
  • MINPWR_DC_HALFCLK
    Set DCDC clock to half freqeuncy for continuous mode
  • MISC_DELAY_TIMING
    Ajust delay to reduce ground noise
  • TARGET_LP
    Target value of standby (low power) mode 0x0: 0
  • TRG
    Target value of VDD_SOC, 25 mV each step 0x0: 0.8V 0xE: 1.15V 0x1F:1.575V