Expand description
GPR1 General Purpose Register
Modules§
- CM7_
FORCE_ HCLK_ EN - ARM CM7 platform AHB clock enable
- ENET1_
CLK_ SEL - ENET1 reference clock mode select.
- ENET1_
TX_ CLK_ DIR - ENET1_TX_CLK data direction control
- ENET2_
CLK_ SEL - ENET2 reference clock mode select.
- ENET2_
TX_ CLK_ DIR - ENET2_TX_CLK data direction control
- ENET_
IPG_ CLK_ S_ EN - ENET and ENET2 ipg_clk_s clock gating enable
- EXC_MON
- Exclusive monitor response select of illegal command
- GINT
- Global interrupt “0” bit (connected to ARM M7 IRQ#0 and GPC)
- SAI1_
MCLK1_ SEL - SAI1 MCLK1 source select
- SAI1_
MCLK2_ SEL - SAI1 MCLK2 source select
- SAI1_
MCLK3_ SEL - SAI1 MCLK3 source select
- SAI1_
MCLK_ DIR - sai1.MCLK signal direction control
- SAI2_
MCLK3_ SEL - SAI2 MCLK3 source select
- SAI2_
MCLK_ DIR - sai2.MCLK signal direction control
- SAI3_
MCLK3_ SEL - SAI3 MCLK3 source select
- SAI3_
MCLK_ DIR - sai3.MCLK signal direction control
- USB_
EXP_ MODE - USB Exposure mode