Module GPR1

Source
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GPR1 General Purpose Register

Modules§

CM7_FORCE_HCLK_EN
ARM CM7 platform AHB clock enable
ENET1_CLK_SEL
ENET1 reference clock mode select.
ENET1_TX_CLK_DIR
ENET1_TX_CLK data direction control
ENET2_CLK_SEL
ENET2 reference clock mode select.
ENET2_TX_CLK_DIR
ENET2_TX_CLK data direction control
ENET_IPG_CLK_S_EN
ENET and ENET2 ipg_clk_s clock gating enable
EXC_MON
Exclusive monitor response select of illegal command
GINT
Global interrupt “0” bit (connected to ARM M7 IRQ#0 and GPC)
SAI1_MCLK1_SEL
SAI1 MCLK1 source select
SAI1_MCLK2_SEL
SAI1 MCLK2 source select
SAI1_MCLK3_SEL
SAI1 MCLK3 source select
SAI1_MCLK_DIR
sai1.MCLK signal direction control
SAI2_MCLK3_SEL
SAI2 MCLK3 source select
SAI2_MCLK_DIR
sai2.MCLK signal direction control
SAI3_MCLK3_SEL
SAI3 MCLK3 source select
SAI3_MCLK_DIR
sai3.MCLK signal direction control
USB_EXP_MODE
USB Exposure mode