Module CTRL1_TOG

LCDIF General Control1 Register

Modules

BM_ERROR_IRQ

This bit is set to indicate that an interrupt is requested by the LCDIF block

BM_ERROR_IRQ_EN

This bit is set to enable bus master error interrupt in the LCDIF master mode.

BYTE_PACKING_FORMAT

This bitfield is used to show which data bytes in a 32-bit word are valid

CS_OUT_SELECT

This bit is CS0/CS1 valid select signals

CUR_FRAME_DONE_IRQ

This bit is set to indicate that an interrupt is requested by the LCDIF block

CUR_FRAME_DONE_IRQ_EN

This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state

FIFO_CLEAR

Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO.

IMAGE_DATA_SELECT

Command Mode MIPI image data select bit

INTERLACE_FIELDS

Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field

IRQ_ON_ALTERNATE_FIELDS

If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field

OVERFLOW_IRQ

This bit is set to indicate that an interrupt is requested by the LCDIF block

OVERFLOW_IRQ_EN

This bit is set to enable an overflow interrupt in the TXFIFO in the write mode.

RECOVER_ON_UNDERFLOW

Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the current field/frame

START_INTERLACE_FROM_SECOND_FIELD

The default is to grab the odd lines first and then the even lines

UNDERFLOW_IRQ

This bit is set to indicate that an interrupt is requested by the LCDIF block

UNDERFLOW_IRQ_EN

This bit is set to enable an underflow interrupt in the TXFIFO in the write mode.

VSYNC_EDGE_IRQ

This bit is set to indicate that an interrupt is requested by the LCDIF block

VSYNC_EDGE_IRQ_EN

This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC and DOTCLK modes, or the beginning of every field in DVI mode